sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 479 {
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u32 rx_out_of_buffer = 0;
 503         int i;
 504         int j;
 505
 506         out = mlx5_vzalloc(outlen);
 507         if (out == NULL)
 508                 goto free_out;
 509
 510         /* Collect firts the SW counters and then HW for consistency */
 511         for (i = 0; i < priv->params.num_channels; i++) {
 512                 struct mlx5e_channel *pch = priv->channel + i;
 513                 struct mlx5e_rq *rq = &pch->rq;
 514                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 515
 516                 /* collect stats from LRO */
 517                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 518                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 519                 sw_lro_queued += rq_stats->sw_lro_queued;
 520                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 521                 lro_packets += rq_stats->lro_packets;
 522                 lro_bytes += rq_stats->lro_bytes;
 523                 rx_csum_none += rq_stats->csum_none;
 524                 rx_wqe_err += rq_stats->wqe_err;
 525
 526                 for (j = 0; j < priv->num_tc; j++) {
 527                         sq_stats = &pch->sq[j].stats;
 528                         sq_br = pch->sq[j].br;
 529
 530                         tso_packets += sq_stats->tso_packets;
 531                         tso_bytes += sq_stats->tso_bytes;
 532                         tx_queue_dropped += sq_stats->dropped;
 533                         if (sq_br != NULL)
 534                                 tx_queue_dropped += sq_br->br_drops;
 535                         tx_defragged += sq_stats->defragged;
 536                         tx_offload_none += sq_stats->csum_offload_none;
 537                 }
 538         }
 539
 540         /* update counters */
 541         s->tso_packets = tso_packets;
 542         s->tso_bytes = tso_bytes;
 543         s->tx_queue_dropped = tx_queue_dropped;
 544         s->tx_defragged = tx_defragged;
 545         s->lro_packets = lro_packets;
 546         s->lro_bytes = lro_bytes;
 547         s->sw_lro_queued = sw_lro_queued;
 548         s->sw_lro_flushed = sw_lro_flushed;
 549         s->rx_csum_none = rx_csum_none;
 550         s->rx_wqe_err = rx_wqe_err;
 551
 552         /* HW counters */
 553         memset(in, 0, sizeof(in));
 554
 555         MLX5_SET(query_vport_counter_in, in, opcode,
 556             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 557         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 558         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 559
 560         memset(out, 0, outlen);
 561
 562         /* get number of out-of-buffer drops first */
 563         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 564             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 565             &rx_out_of_buffer) == 0) {
 566                 /* accumulate difference into a 64-bit counter */
 567                 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer -
 568                     s->rx_out_of_buffer_prev);
 569                 s->rx_out_of_buffer_prev = rx_out_of_buffer;
 570         }
 571
 572         /* get port statistics */
 573         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 574 #define MLX5_GET_CTR(out, x) \
 575         MLX5_GET64(query_vport_counter_out, out, x)
 576
 577                 s->rx_error_packets =
 578                     MLX5_GET_CTR(out, received_errors.packets);
 579                 s->rx_error_bytes =
 580                     MLX5_GET_CTR(out, received_errors.octets);
 581                 s->tx_error_packets =
 582                     MLX5_GET_CTR(out, transmit_errors.packets);
 583                 s->tx_error_bytes =
 584                     MLX5_GET_CTR(out, transmit_errors.octets);
 585
 586                 s->rx_unicast_packets =
 587                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 588                 s->rx_unicast_bytes =
 589                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 590                 s->tx_unicast_packets =
 591                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 592                 s->tx_unicast_bytes =
 593                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 594
 595                 s->rx_multicast_packets =
 596                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 597                 s->rx_multicast_bytes =
 598                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 599                 s->tx_multicast_packets =
 600                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 601                 s->tx_multicast_bytes =
 602                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 603
 604                 s->rx_broadcast_packets =
 605                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 606                 s->rx_broadcast_bytes =
 607                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 608                 s->tx_broadcast_packets =
 609                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 610                 s->tx_broadcast_bytes =
 611                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 612
 613                 s->rx_packets = s->rx_unicast_packets +
 614                     s->rx_multicast_packets + s->rx_broadcast_packets -
 615                     s->rx_out_of_buffer;
 616                 s->rx_bytes = s->rx_unicast_bytes + s->rx_multicast_bytes +
 617                     s->rx_broadcast_bytes;
 618                 s->tx_packets = s->tx_unicast_packets +
 619                     s->tx_multicast_packets + s->tx_broadcast_packets;
 620                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 621                     s->tx_broadcast_bytes;
 622
 623                 /* Update calculated offload counters */
 624                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 625                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 626         }
 627
 628         /* Get physical port counters */
 629         mlx5e_update_pport_counters(priv);
 630
 631         s->tx_jumbo_packets =
 632             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 633             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 634             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 635             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 636
 637 #if (__FreeBSD_version < 1100000)
 638         /* no get_counters interface in fbsd 10 */
 639         ifp->if_ipackets = s->rx_packets;
 640         ifp->if_ierrors = s->rx_error_packets +
 641             priv->stats.pport.alignment_err +
 642             priv->stats.pport.check_seq_err +
 643             priv->stats.pport.crc_align_errors +
 644             priv->stats.pport.in_range_len_errors +
 645             priv->stats.pport.jabbers +
 646             priv->stats.pport.out_of_range_len +
 647             priv->stats.pport.oversize_pkts +
 648             priv->stats.pport.symbol_err +
 649             priv->stats.pport.too_long_errors +
 650             priv->stats.pport.undersize_pkts +
 651             priv->stats.pport.unsupported_op_rx;
 652         ifp->if_iqdrops = s->rx_out_of_buffer +
 653             priv->stats.pport.drop_events;
 654         ifp->if_opackets = s->tx_packets;
 655         ifp->if_oerrors = s->tx_error_packets;
 656         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 657         ifp->if_ibytes = s->rx_bytes;
 658         ifp->if_obytes = s->tx_bytes;
 659         ifp->if_collisions =
 660             priv->stats.pport.collisions;
 661 #endif
 662
 663 free_out:
 664         kvfree(out);
 665
 666         /* Update diagnostics, if any */
 667         if (priv->params_ethtool.diag_pci_enable ||
 668             priv->params_ethtool.diag_general_enable) {
 669                 int error = mlx5_core_get_diagnostics_full(mdev,
 670                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 671                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 672                 if (error != 0)
 673                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 674         }
 675 }
 676
 677 static void
 678 mlx5e_update_stats_work(struct work_struct *work)
 679 {
 680         struct mlx5e_priv *priv;
 681
 682         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
 683         PRIV_LOCK(priv);
 684         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
 685                 mlx5e_update_stats_locked(priv);
 686         PRIV_UNLOCK(priv);
 687 }
 688
 689 static void
 690 mlx5e_update_stats(void *arg)
 691 {
 692         struct mlx5e_priv *priv = arg;
 693
 694         queue_work(priv->wq, &priv->update_stats_work);
 695
 696         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 697 }
 698
 699 static void
 700 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 701     enum mlx5_dev_event event)
 702 {
 703         switch (event) {
 704         case MLX5_DEV_EVENT_PORT_UP:
 705         case MLX5_DEV_EVENT_PORT_DOWN:
 706                 queue_work(priv->wq, &priv->update_carrier_work);
 707                 break;
 708
 709         default:
 710                 break;
 711         }
 712 }
 713
 714 static void
 715 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 716     enum mlx5_dev_event event, unsigned long param)
 717 {
 718         struct mlx5e_priv *priv = vpriv;
 719
 720         mtx_lock(&priv->async_events_mtx);
 721         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 722                 mlx5e_async_event_sub(priv, event);
 723         mtx_unlock(&priv->async_events_mtx);
 724 }
 725
 726 static void
 727 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 728 {
 729         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730 }
 731
 732 static void
 733 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 734 {
 735         mtx_lock(&priv->async_events_mtx);
 736         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 737         mtx_unlock(&priv->async_events_mtx);
 738 }
 739
 740 static void mlx5e_calibration_callout(void *arg);
 741 static int mlx5e_calibration_duration = 20;
 742 static int mlx5e_fast_calibration = 1;
 743 static int mlx5e_normal_calibration = 30;
 744
 745 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 746     "MLX5 timestamp calibration parameteres");
 747
 748 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 749     &mlx5e_calibration_duration, 0,
 750     "Duration of initial calibration");
 751 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 752     &mlx5e_fast_calibration, 0,
 753     "Recalibration interval during initial calibration");
 754 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 755     &mlx5e_normal_calibration, 0,
 756     "Recalibration interval during normal operations");
 757
 758 /*
 759  * Ignites the calibration process.
 760  */
 761 static void
 762 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 763 {
 764
 765         if (priv->clbr_done == 0)
 766                 mlx5e_calibration_callout(priv);
 767         else
 768                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 769                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 770                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 771                     priv);
 772 }
 773
 774 static uint64_t
 775 mlx5e_timespec2usec(const struct timespec *ts)
 776 {
 777
 778         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 779 }
 780
 781 static uint64_t
 782 mlx5e_hw_clock(struct mlx5e_priv *priv)
 783 {
 784         struct mlx5_init_seg *iseg;
 785         uint32_t hw_h, hw_h1, hw_l;
 786
 787         iseg = priv->mdev->iseg;
 788         do {
 789                 hw_h = ioread32be(&iseg->internal_timer_h);
 790                 hw_l = ioread32be(&iseg->internal_timer_l);
 791                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 792         } while (hw_h1 != hw_h);
 793         return (((uint64_t)hw_h << 32) | hw_l);
 794 }
 795
 796 /*
 797  * The calibration callout, it runs either in the context of the
 798  * thread which enables calibration, or in callout.  It takes the
 799  * snapshot of system and adapter clocks, then advances the pointers to
 800  * the calibration point to allow rx path to read the consistent data
 801  * lockless.
 802  */
 803 static void
 804 mlx5e_calibration_callout(void *arg)
 805 {
 806         struct mlx5e_priv *priv;
 807         struct mlx5e_clbr_point *next, *curr;
 808         struct timespec ts;
 809         int clbr_curr_next;
 810
 811         priv = arg;
 812         curr = &priv->clbr_points[priv->clbr_curr];
 813         clbr_curr_next = priv->clbr_curr + 1;
 814         if (clbr_curr_next >= nitems(priv->clbr_points))
 815                 clbr_curr_next = 0;
 816         next = &priv->clbr_points[clbr_curr_next];
 817
 818         next->base_prev = curr->base_curr;
 819         next->clbr_hw_prev = curr->clbr_hw_curr;
 820
 821         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 822         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 823             0) {
 824                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 825                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 826                 priv->clbr_done = 0;
 827                 return;
 828         }
 829
 830         nanouptime(&ts);
 831         next->base_curr = mlx5e_timespec2usec(&ts);
 832
 833         curr->clbr_gen = 0;
 834         atomic_thread_fence_rel();
 835         priv->clbr_curr = clbr_curr_next;
 836         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 837
 838         if (priv->clbr_done < mlx5e_calibration_duration)
 839                 priv->clbr_done++;
 840         mlx5e_reset_calibration_callout(priv);
 841 }
 842
 843 static const char *mlx5e_rq_stats_desc[] = {
 844         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 845 };
 846
 847 static int
 848 mlx5e_create_rq(struct mlx5e_channel *c,
 849     struct mlx5e_rq_param *param,
 850     struct mlx5e_rq *rq)
 851 {
 852         struct mlx5e_priv *priv = c->priv;
 853         struct mlx5_core_dev *mdev = priv->mdev;
 854         char buffer[16];
 855         void *rqc = param->rqc;
 856         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 857         int wq_sz;
 858         int err;
 859         int i;
 860         u32 nsegs, wqe_sz;
 861
 862         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 863         if (err != 0)
 864                 goto done;
 865
 866         /* Create DMA descriptor TAG */
 867         if ((err = -bus_dma_tag_create(
 868             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 869             1,                          /* any alignment */
 870             0,                          /* no boundary */
 871             BUS_SPACE_MAXADDR,          /* lowaddr */
 872             BUS_SPACE_MAXADDR,          /* highaddr */
 873             NULL, NULL,                 /* filter, filterarg */
 874             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 875             nsegs,                      /* nsegments */
 876             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 877             0,                          /* flags */
 878             NULL, NULL,                 /* lockfunc, lockfuncarg */
 879             &rq->dma_tag)))
 880                 goto done;
 881
 882         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 883             &rq->wq_ctrl);
 884         if (err)
 885                 goto err_free_dma_tag;
 886
 887         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 888
 889         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 890         if (err != 0)
 891                 goto err_rq_wq_destroy;
 892
 893         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 894
 895         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 896         if (err)
 897                 goto err_rq_wq_destroy;
 898
 899         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 900         for (i = 0; i != wq_sz; i++) {
 901                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 902 #if (MLX5E_MAX_RX_SEGS == 1)
 903                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 904 #else
 905                 int j;
 906 #endif
 907
 908                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 909                 if (err != 0) {
 910                         while (i--)
 911                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 912                         goto err_rq_mbuf_free;
 913                 }
 914
 915                 /* set value for constant fields */
 916 #if (MLX5E_MAX_RX_SEGS == 1)
 917                 wqe->data[0].lkey = c->mkey_be;
 918                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 919 #else
 920                 for (j = 0; j < rq->nsegs; j++)
 921                         wqe->data[j].lkey = c->mkey_be;
 922 #endif
 923         }
 924
 925         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 926         if (priv->params.rx_cq_moderation_mode < 2) {
 927                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 928         } else {
 929                 void *cqc = container_of(param,
 930                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 931
 932                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 933                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 934                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 935                         break;
 936                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 937                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 938                         break;
 939                 default:
 940                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 941                         break;
 942                 }
 943         }
 944
 945         rq->ifp = c->tag.m_snd_tag.ifp;
 946         rq->channel = c;
 947         rq->ix = c->ix;
 948
 949         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 950         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 951             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 952             rq->stats.arg);
 953         return (0);
 954
 955 err_rq_mbuf_free:
 956         free(rq->mbuf, M_MLX5EN);
 957         tcp_lro_free(&rq->lro);
 958 err_rq_wq_destroy:
 959         mlx5_wq_destroy(&rq->wq_ctrl);
 960 err_free_dma_tag:
 961         bus_dma_tag_destroy(rq->dma_tag);
 962 done:
 963         return (err);
 964 }
 965
 966 static void
 967 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 968 {
 969         int wq_sz;
 970         int i;
 971
 972         /* destroy all sysctl nodes */
 973         sysctl_ctx_free(&rq->stats.ctx);
 974
 975         /* free leftover LRO packets, if any */
 976         tcp_lro_free(&rq->lro);
 977
 978         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 979         for (i = 0; i != wq_sz; i++) {
 980                 if (rq->mbuf[i].mbuf != NULL) {
 981                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 982                         m_freem(rq->mbuf[i].mbuf);
 983                 }
 984                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 985         }
 986         free(rq->mbuf, M_MLX5EN);
 987         mlx5_wq_destroy(&rq->wq_ctrl);
 988 }
 989
 990 static int
 991 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 992 {
 993         struct mlx5e_channel *c = rq->channel;
 994         struct mlx5e_priv *priv = c->priv;
 995         struct mlx5_core_dev *mdev = priv->mdev;
 996
 997         void *in;
 998         void *rqc;
 999         void *wq;
1000         int inlen;
1001         int err;
1002
1003         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1004             sizeof(u64) * rq->wq_ctrl.buf.npages;
1005         in = mlx5_vzalloc(inlen);
1006         if (in == NULL)
1007                 return (-ENOMEM);
1008
1009         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1010         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1011
1012         memcpy(rqc, param->rqc, sizeof(param->rqc));
1013
1014         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1015         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1016         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1017         if (priv->counter_set_id >= 0)
1018                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1019         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1020             PAGE_SHIFT);
1021         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1022
1023         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1024             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1025
1026         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1027
1028         kvfree(in);
1029
1030         return (err);
1031 }
1032
1033 static int
1034 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1035 {
1036         struct mlx5e_channel *c = rq->channel;
1037         struct mlx5e_priv *priv = c->priv;
1038         struct mlx5_core_dev *mdev = priv->mdev;
1039
1040         void *in;
1041         void *rqc;
1042         int inlen;
1043         int err;
1044
1045         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1046         in = mlx5_vzalloc(inlen);
1047         if (in == NULL)
1048                 return (-ENOMEM);
1049
1050         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1051
1052         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1053         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1054         MLX5_SET(rqc, rqc, state, next_state);
1055
1056         err = mlx5_core_modify_rq(mdev, in, inlen);
1057
1058         kvfree(in);
1059
1060         return (err);
1061 }
1062
1063 static void
1064 mlx5e_disable_rq(struct mlx5e_rq *rq)
1065 {
1066         struct mlx5e_channel *c = rq->channel;
1067         struct mlx5e_priv *priv = c->priv;
1068         struct mlx5_core_dev *mdev = priv->mdev;
1069
1070         mlx5_core_destroy_rq(mdev, rq->rqn);
1071 }
1072
1073 static int
1074 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1075 {
1076         struct mlx5e_channel *c = rq->channel;
1077         struct mlx5e_priv *priv = c->priv;
1078         struct mlx5_wq_ll *wq = &rq->wq;
1079         int i;
1080
1081         for (i = 0; i < 1000; i++) {
1082                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1083                         return (0);
1084
1085                 msleep(4);
1086         }
1087         return (-ETIMEDOUT);
1088 }
1089
1090 static int
1091 mlx5e_open_rq(struct mlx5e_channel *c,
1092     struct mlx5e_rq_param *param,
1093     struct mlx5e_rq *rq)
1094 {
1095         int err;
1096
1097         err = mlx5e_create_rq(c, param, rq);
1098         if (err)
1099                 return (err);
1100
1101         err = mlx5e_enable_rq(rq, param);
1102         if (err)
1103                 goto err_destroy_rq;
1104
1105         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1106         if (err)
1107                 goto err_disable_rq;
1108
1109         c->rq.enabled = 1;
1110
1111         return (0);
1112
1113 err_disable_rq:
1114         mlx5e_disable_rq(rq);
1115 err_destroy_rq:
1116         mlx5e_destroy_rq(rq);
1117
1118         return (err);
1119 }
1120
1121 static void
1122 mlx5e_close_rq(struct mlx5e_rq *rq)
1123 {
1124         mtx_lock(&rq->mtx);
1125         rq->enabled = 0;
1126         callout_stop(&rq->watchdog);
1127         mtx_unlock(&rq->mtx);
1128
1129         callout_drain(&rq->watchdog);
1130
1131         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1132 }
1133
1134 static void
1135 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1136 {
1137
1138         mlx5e_disable_rq(rq);
1139         mlx5e_close_cq(&rq->cq);
1140         cancel_work_sync(&rq->dim.work);
1141         mlx5e_destroy_rq(rq);
1142 }
1143
1144 void
1145 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1146 {
1147         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1148         int x;
1149
1150         for (x = 0; x != wq_sz; x++) {
1151                 if (sq->mbuf[x].mbuf != NULL) {
1152                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1153                         m_freem(sq->mbuf[x].mbuf);
1154                 }
1155                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1156         }
1157         free(sq->mbuf, M_MLX5EN);
1158 }
1159
1160 int
1161 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1162 {
1163         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1164         int err;
1165         int x;
1166
1167         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1168
1169         /* Create DMA descriptor MAPs */
1170         for (x = 0; x != wq_sz; x++) {
1171                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1172                 if (err != 0) {
1173                         while (x--)
1174                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1175                         free(sq->mbuf, M_MLX5EN);
1176                         return (err);
1177                 }
1178         }
1179         return (0);
1180 }
1181
1182 static const char *mlx5e_sq_stats_desc[] = {
1183         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1184 };
1185
1186 void
1187 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1188 {
1189         sq->max_inline = sq->priv->params.tx_max_inline;
1190         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1191
1192         /*
1193          * Check if trust state is DSCP or if inline mode is NONE which
1194          * indicates CX-5 or newer hardware.
1195          */
1196         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1197             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1198                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1199                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1200                 else
1201                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1202         } else {
1203                 sq->min_insert_caps = 0;
1204         }
1205 }
1206
1207 static void
1208 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1209 {
1210         int i;
1211
1212         for (i = 0; i != c->num_tc; i++) {
1213                 mtx_lock(&c->sq[i].lock);
1214                 mlx5e_update_sq_inline(&c->sq[i]);
1215                 mtx_unlock(&c->sq[i].lock);
1216         }
1217 }
1218
1219 void
1220 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1221 {
1222         int i;
1223
1224         /* check if channels are closed */
1225         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1226                 return;
1227
1228         for (i = 0; i < priv->params.num_channels; i++)
1229                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1230 }
1231
1232 static int
1233 mlx5e_create_sq(struct mlx5e_channel *c,
1234     int tc,
1235     struct mlx5e_sq_param *param,
1236     struct mlx5e_sq *sq)
1237 {
1238         struct mlx5e_priv *priv = c->priv;
1239         struct mlx5_core_dev *mdev = priv->mdev;
1240         char buffer[16];
1241         void *sqc = param->sqc;
1242         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1243         int err;
1244
1245         /* Create DMA descriptor TAG */
1246         if ((err = -bus_dma_tag_create(
1247             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1248             1,                          /* any alignment */
1249             0,                          /* no boundary */
1250             BUS_SPACE_MAXADDR,          /* lowaddr */
1251             BUS_SPACE_MAXADDR,          /* highaddr */
1252             NULL, NULL,                 /* filter, filterarg */
1253             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1254             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1255             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1256             0,                          /* flags */
1257             NULL, NULL,                 /* lockfunc, lockfuncarg */
1258             &sq->dma_tag)))
1259                 goto done;
1260
1261         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1262         if (err)
1263                 goto err_free_dma_tag;
1264
1265         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1266             &sq->wq_ctrl);
1267         if (err)
1268                 goto err_unmap_free_uar;
1269
1270         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1271         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1272
1273         err = mlx5e_alloc_sq_db(sq);
1274         if (err)
1275                 goto err_sq_wq_destroy;
1276
1277         sq->mkey_be = c->mkey_be;
1278         sq->ifp = priv->ifp;
1279         sq->priv = priv;
1280         sq->tc = tc;
1281
1282         mlx5e_update_sq_inline(sq);
1283
1284         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1285         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1286             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1287             sq->stats.arg);
1288
1289         return (0);
1290
1291 err_sq_wq_destroy:
1292         mlx5_wq_destroy(&sq->wq_ctrl);
1293
1294 err_unmap_free_uar:
1295         mlx5_unmap_free_uar(mdev, &sq->uar);
1296
1297 err_free_dma_tag:
1298         bus_dma_tag_destroy(sq->dma_tag);
1299 done:
1300         return (err);
1301 }
1302
1303 static void
1304 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1305 {
1306         /* destroy all sysctl nodes */
1307         sysctl_ctx_free(&sq->stats.ctx);
1308
1309         mlx5e_free_sq_db(sq);
1310         mlx5_wq_destroy(&sq->wq_ctrl);
1311         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1312 }
1313
1314 int
1315 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1316     int tis_num)
1317 {
1318         void *in;
1319         void *sqc;
1320         void *wq;
1321         int inlen;
1322         int err;
1323
1324         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1325             sizeof(u64) * sq->wq_ctrl.buf.npages;
1326         in = mlx5_vzalloc(inlen);
1327         if (in == NULL)
1328                 return (-ENOMEM);
1329
1330         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1331         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1332
1333         memcpy(sqc, param->sqc, sizeof(param->sqc));
1334
1335         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1336         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1337         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1338         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1339         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1340
1341         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1342         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1343         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1344             PAGE_SHIFT);
1345         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1346
1347         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1348             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1349
1350         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1351
1352         kvfree(in);
1353
1354         return (err);
1355 }
1356
1357 int
1358 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1359 {
1360         void *in;
1361         void *sqc;
1362         int inlen;
1363         int err;
1364
1365         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1366         in = mlx5_vzalloc(inlen);
1367         if (in == NULL)
1368                 return (-ENOMEM);
1369
1370         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1371
1372         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1373         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1374         MLX5_SET(sqc, sqc, state, next_state);
1375
1376         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1377
1378         kvfree(in);
1379
1380         return (err);
1381 }
1382
1383 void
1384 mlx5e_disable_sq(struct mlx5e_sq *sq)
1385 {
1386
1387         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1388 }
1389
1390 static int
1391 mlx5e_open_sq(struct mlx5e_channel *c,
1392     int tc,
1393     struct mlx5e_sq_param *param,
1394     struct mlx5e_sq *sq)
1395 {
1396         int err;
1397
1398         err = mlx5e_create_sq(c, tc, param, sq);
1399         if (err)
1400                 return (err);
1401
1402         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1403         if (err)
1404                 goto err_destroy_sq;
1405
1406         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1407         if (err)
1408                 goto err_disable_sq;
1409
1410         WRITE_ONCE(sq->running, 1);
1411
1412         return (0);
1413
1414 err_disable_sq:
1415         mlx5e_disable_sq(sq);
1416 err_destroy_sq:
1417         mlx5e_destroy_sq(sq);
1418
1419         return (err);
1420 }
1421
1422 static void
1423 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1424 {
1425         /* fill up remainder with NOPs */
1426         while (sq->cev_counter != 0) {
1427                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1428                         if (can_sleep != 0) {
1429                                 mtx_unlock(&sq->lock);
1430                                 msleep(4);
1431                                 mtx_lock(&sq->lock);
1432                         } else {
1433                                 goto done;
1434                         }
1435                 }
1436                 /* send a single NOP */
1437                 mlx5e_send_nop(sq, 1);
1438                 atomic_thread_fence_rel();
1439         }
1440 done:
1441         /* Check if we need to write the doorbell */
1442         if (likely(sq->doorbell.d64 != 0)) {
1443                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1444                 sq->doorbell.d64 = 0;
1445         }
1446 }
1447
1448 void
1449 mlx5e_sq_cev_timeout(void *arg)
1450 {
1451         struct mlx5e_sq *sq = arg;
1452
1453         mtx_assert(&sq->lock, MA_OWNED);
1454
1455         /* check next state */
1456         switch (sq->cev_next_state) {
1457         case MLX5E_CEV_STATE_SEND_NOPS:
1458                 /* fill TX ring with NOPs, if any */
1459                 mlx5e_sq_send_nops_locked(sq, 0);
1460
1461                 /* check if completed */
1462                 if (sq->cev_counter == 0) {
1463                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1464                         return;
1465                 }
1466                 break;
1467         default:
1468                 /* send NOPs on next timeout */
1469                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1470                 break;
1471         }
1472
1473         /* restart timer */
1474         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1475 }
1476
1477 void
1478 mlx5e_drain_sq(struct mlx5e_sq *sq)
1479 {
1480         int error;
1481         struct mlx5_core_dev *mdev= sq->priv->mdev;
1482
1483         /*
1484          * Check if already stopped.
1485          *
1486          * NOTE: Serialization of this function is managed by the
1487          * caller ensuring the priv's state lock is locked or in case
1488          * of rate limit support, a single thread manages drain and
1489          * resume of SQs. The "running" variable can therefore safely
1490          * be read without any locks.
1491          */
1492         if (READ_ONCE(sq->running) == 0)
1493                 return;
1494
1495         /* don't put more packets into the SQ */
1496         WRITE_ONCE(sq->running, 0);
1497
1498         /* serialize access to DMA rings */
1499         mtx_lock(&sq->lock);
1500
1501         /* teardown event factor timer, if any */
1502         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1503         callout_stop(&sq->cev_callout);
1504
1505         /* send dummy NOPs in order to flush the transmit ring */
1506         mlx5e_sq_send_nops_locked(sq, 1);
1507         mtx_unlock(&sq->lock);
1508
1509         /* make sure it is safe to free the callout */
1510         callout_drain(&sq->cev_callout);
1511
1512         /* wait till SQ is empty or link is down */
1513         mtx_lock(&sq->lock);
1514         while (sq->cc != sq->pc &&
1515             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1516             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1517                 mtx_unlock(&sq->lock);
1518                 msleep(1);
1519                 sq->cq.mcq.comp(&sq->cq.mcq);
1520                 mtx_lock(&sq->lock);
1521         }
1522         mtx_unlock(&sq->lock);
1523
1524         /* error out remaining requests */
1525         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1526         if (error != 0) {
1527                 if_printf(sq->ifp,
1528                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1529         }
1530
1531         /* wait till SQ is empty */
1532         mtx_lock(&sq->lock);
1533         while (sq->cc != sq->pc &&
1534                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1535                 mtx_unlock(&sq->lock);
1536                 msleep(1);
1537                 sq->cq.mcq.comp(&sq->cq.mcq);
1538                 mtx_lock(&sq->lock);
1539         }
1540         mtx_unlock(&sq->lock);
1541 }
1542
1543 static void
1544 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1545 {
1546
1547         mlx5e_drain_sq(sq);
1548         mlx5e_disable_sq(sq);
1549         mlx5e_destroy_sq(sq);
1550 }
1551
1552 static int
1553 mlx5e_create_cq(struct mlx5e_priv *priv,
1554     struct mlx5e_cq_param *param,
1555     struct mlx5e_cq *cq,
1556     mlx5e_cq_comp_t *comp,
1557     int eq_ix)
1558 {
1559         struct mlx5_core_dev *mdev = priv->mdev;
1560         struct mlx5_core_cq *mcq = &cq->mcq;
1561         int eqn_not_used;
1562         int irqn;
1563         int err;
1564         u32 i;
1565
1566         param->wq.buf_numa_node = 0;
1567         param->wq.db_numa_node = 0;
1568
1569         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1570             &cq->wq_ctrl);
1571         if (err)
1572                 return (err);
1573
1574         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1575
1576         mcq->cqe_sz = 64;
1577         mcq->set_ci_db = cq->wq_ctrl.db.db;
1578         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1579         *mcq->set_ci_db = 0;
1580         *mcq->arm_db = 0;
1581         mcq->vector = eq_ix;
1582         mcq->comp = comp;
1583         mcq->event = mlx5e_cq_error_event;
1584         mcq->irqn = irqn;
1585         mcq->uar = &priv->cq_uar;
1586
1587         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1588                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1589
1590                 cqe->op_own = 0xf1;
1591         }
1592
1593         cq->priv = priv;
1594
1595         return (0);
1596 }
1597
1598 static void
1599 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1600 {
1601         mlx5_wq_destroy(&cq->wq_ctrl);
1602 }
1603
1604 static int
1605 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1606 {
1607         struct mlx5_core_cq *mcq = &cq->mcq;
1608         void *in;
1609         void *cqc;
1610         int inlen;
1611         int irqn_not_used;
1612         int eqn;
1613         int err;
1614
1615         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1616             sizeof(u64) * cq->wq_ctrl.buf.npages;
1617         in = mlx5_vzalloc(inlen);
1618         if (in == NULL)
1619                 return (-ENOMEM);
1620
1621         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1622
1623         memcpy(cqc, param->cqc, sizeof(param->cqc));
1624
1625         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1626             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1627
1628         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1629
1630         MLX5_SET(cqc, cqc, c_eqn, eqn);
1631         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1632         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1633             PAGE_SHIFT);
1634         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1635
1636         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1637
1638         kvfree(in);
1639
1640         if (err)
1641                 return (err);
1642
1643         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1644
1645         return (0);
1646 }
1647
1648 static void
1649 mlx5e_disable_cq(struct mlx5e_cq *cq)
1650 {
1651
1652         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1653 }
1654
1655 int
1656 mlx5e_open_cq(struct mlx5e_priv *priv,
1657     struct mlx5e_cq_param *param,
1658     struct mlx5e_cq *cq,
1659     mlx5e_cq_comp_t *comp,
1660     int eq_ix)
1661 {
1662         int err;
1663
1664         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1665         if (err)
1666                 return (err);
1667
1668         err = mlx5e_enable_cq(cq, param, eq_ix);
1669         if (err)
1670                 goto err_destroy_cq;
1671
1672         return (0);
1673
1674 err_destroy_cq:
1675         mlx5e_destroy_cq(cq);
1676
1677         return (err);
1678 }
1679
1680 void
1681 mlx5e_close_cq(struct mlx5e_cq *cq)
1682 {
1683         mlx5e_disable_cq(cq);
1684         mlx5e_destroy_cq(cq);
1685 }
1686
1687 static int
1688 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1689     struct mlx5e_channel_param *cparam)
1690 {
1691         int err;
1692         int tc;
1693
1694         for (tc = 0; tc < c->num_tc; tc++) {
1695                 /* open completion queue */
1696                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1697                     &mlx5e_tx_cq_comp, c->ix);
1698                 if (err)
1699                         goto err_close_tx_cqs;
1700         }
1701         return (0);
1702
1703 err_close_tx_cqs:
1704         for (tc--; tc >= 0; tc--)
1705                 mlx5e_close_cq(&c->sq[tc].cq);
1706
1707         return (err);
1708 }
1709
1710 static void
1711 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1712 {
1713         int tc;
1714
1715         for (tc = 0; tc < c->num_tc; tc++)
1716                 mlx5e_close_cq(&c->sq[tc].cq);
1717 }
1718
1719 static int
1720 mlx5e_open_sqs(struct mlx5e_channel *c,
1721     struct mlx5e_channel_param *cparam)
1722 {
1723         int err;
1724         int tc;
1725
1726         for (tc = 0; tc < c->num_tc; tc++) {
1727                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1728                 if (err)
1729                         goto err_close_sqs;
1730         }
1731
1732         return (0);
1733
1734 err_close_sqs:
1735         for (tc--; tc >= 0; tc--)
1736                 mlx5e_close_sq_wait(&c->sq[tc]);
1737
1738         return (err);
1739 }
1740
1741 static void
1742 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1743 {
1744         int tc;
1745
1746         for (tc = 0; tc < c->num_tc; tc++)
1747                 mlx5e_close_sq_wait(&c->sq[tc]);
1748 }
1749
1750 static void
1751 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1752 {
1753         int tc;
1754
1755         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1756
1757         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1758
1759         for (tc = 0; tc < c->num_tc; tc++) {
1760                 struct mlx5e_sq *sq = c->sq + tc;
1761
1762                 mtx_init(&sq->lock, "mlx5tx",
1763                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1764                 mtx_init(&sq->comp_lock, "mlx5comp",
1765                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1766
1767                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1768
1769                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1770
1771                 /* ensure the TX completion event factor is not zero */
1772                 if (sq->cev_factor == 0)
1773                         sq->cev_factor = 1;
1774         }
1775 }
1776
1777 static void
1778 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1779 {
1780         int tc;
1781
1782         mtx_destroy(&c->rq.mtx);
1783
1784         for (tc = 0; tc < c->num_tc; tc++) {
1785                 mtx_destroy(&c->sq[tc].lock);
1786                 mtx_destroy(&c->sq[tc].comp_lock);
1787         }
1788 }
1789
1790 static int
1791 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1792     struct mlx5e_channel_param *cparam,
1793     struct mlx5e_channel *c)
1794 {
1795         int err;
1796
1797         memset(c, 0, sizeof(*c));
1798
1799         c->priv = priv;
1800         c->ix = ix;
1801         /* setup send tag */
1802         c->tag.m_snd_tag.ifp = priv->ifp;
1803         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1804         c->mkey_be = cpu_to_be32(priv->mr.key);
1805         c->num_tc = priv->num_tc;
1806
1807         /* init mutexes */
1808         mlx5e_chan_mtx_init(c);
1809
1810         /* open transmit completion queue */
1811         err = mlx5e_open_tx_cqs(c, cparam);
1812         if (err)
1813                 goto err_free;
1814
1815         /* open receive completion queue */
1816         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1817             &mlx5e_rx_cq_comp, c->ix);
1818         if (err)
1819                 goto err_close_tx_cqs;
1820
1821         err = mlx5e_open_sqs(c, cparam);
1822         if (err)
1823                 goto err_close_rx_cq;
1824
1825         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1826         if (err)
1827                 goto err_close_sqs;
1828
1829         /* poll receive queue initially */
1830         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1831
1832         return (0);
1833
1834 err_close_sqs:
1835         mlx5e_close_sqs_wait(c);
1836
1837 err_close_rx_cq:
1838         mlx5e_close_cq(&c->rq.cq);
1839
1840 err_close_tx_cqs:
1841         mlx5e_close_tx_cqs(c);
1842
1843 err_free:
1844         /* destroy mutexes */
1845         mlx5e_chan_mtx_destroy(c);
1846         return (err);
1847 }
1848
1849 static void
1850 mlx5e_close_channel(struct mlx5e_channel *c)
1851 {
1852         mlx5e_close_rq(&c->rq);
1853 }
1854
1855 static void
1856 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1857 {
1858         mlx5e_close_rq_wait(&c->rq);
1859         mlx5e_close_sqs_wait(c);
1860         mlx5e_close_tx_cqs(c);
1861         /* destroy mutexes */
1862         mlx5e_chan_mtx_destroy(c);
1863 }
1864
1865 static int
1866 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1867 {
1868         u32 r, n;
1869
1870         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1871             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1872         if (r > MJUM16BYTES)
1873                 return (-ENOMEM);
1874
1875         if (r > MJUM9BYTES)
1876                 r = MJUM16BYTES;
1877         else if (r > MJUMPAGESIZE)
1878                 r = MJUM9BYTES;
1879         else if (r > MCLBYTES)
1880                 r = MJUMPAGESIZE;
1881         else
1882                 r = MCLBYTES;
1883
1884         /*
1885          * n + 1 must be a power of two, because stride size must be.
1886          * Stride size is 16 * (n + 1), as the first segment is
1887          * control.
1888          */
1889         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1890                 ;
1891
1892         *wqe_sz = r;
1893         *nsegs = n;
1894         return (0);
1895 }
1896
1897 static void
1898 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1899     struct mlx5e_rq_param *param)
1900 {
1901         void *rqc = param->rqc;
1902         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1903         u32 wqe_sz, nsegs;
1904
1905         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1906         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1907         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1908         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1909             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1910         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1911         MLX5_SET(wq, wq, pd, priv->pdn);
1912
1913         param->wq.buf_numa_node = 0;
1914         param->wq.db_numa_node = 0;
1915         param->wq.linear = 1;
1916 }
1917
1918 static void
1919 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1920     struct mlx5e_sq_param *param)
1921 {
1922         void *sqc = param->sqc;
1923         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1924
1925         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1926         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1927         MLX5_SET(wq, wq, pd, priv->pdn);
1928
1929         param->wq.buf_numa_node = 0;
1930         param->wq.db_numa_node = 0;
1931         param->wq.linear = 1;
1932 }
1933
1934 static void
1935 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1936     struct mlx5e_cq_param *param)
1937 {
1938         void *cqc = param->cqc;
1939
1940         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1941 }
1942
1943 static void
1944 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1945 {
1946
1947         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1948
1949         /* apply LRO restrictions */
1950         if (priv->params.hw_lro_en &&
1951             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1952                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1953         }
1954 }
1955
1956 static void
1957 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1958     struct mlx5e_cq_param *param)
1959 {
1960         struct net_dim_cq_moder curr;
1961         void *cqc = param->cqc;
1962
1963         /*
1964          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
1965          * format is more beneficial for FreeBSD use case.
1966          *
1967          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
1968          * in mlx5e_decompress_cqe.
1969          */
1970         if (priv->params.cqe_zipping_en) {
1971                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
1972                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1973         }
1974
1975         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1976
1977         switch (priv->params.rx_cq_moderation_mode) {
1978         case 0:
1979                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1980                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1981                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1982                 break;
1983         case 1:
1984                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1985                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1986                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1987                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1988                 else
1989                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1990                 break;
1991         case 2:
1992                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1993                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1994                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1995                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1996                 break;
1997         case 3:
1998                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1999                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2000                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2001                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2002                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2003                 else
2004                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2005                 break;
2006         default:
2007                 break;
2008         }
2009
2010         mlx5e_dim_build_cq_param(priv, param);
2011
2012         mlx5e_build_common_cq_param(priv, param);
2013 }
2014
2015 static void
2016 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2017     struct mlx5e_cq_param *param)
2018 {
2019         void *cqc = param->cqc;
2020
2021         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2022         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2023         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2024
2025         switch (priv->params.tx_cq_moderation_mode) {
2026         case 0:
2027                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2028                 break;
2029         default:
2030                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2031                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2032                 else
2033                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2034                 break;
2035         }
2036
2037         mlx5e_build_common_cq_param(priv, param);
2038 }
2039
2040 static void
2041 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2042     struct mlx5e_channel_param *cparam)
2043 {
2044         memset(cparam, 0, sizeof(*cparam));
2045
2046         mlx5e_build_rq_param(priv, &cparam->rq);
2047         mlx5e_build_sq_param(priv, &cparam->sq);
2048         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2049         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2050 }
2051
2052 static int
2053 mlx5e_open_channels(struct mlx5e_priv *priv)
2054 {
2055         struct mlx5e_channel_param cparam;
2056         int err;
2057         int i;
2058         int j;
2059
2060         mlx5e_build_channel_param(priv, &cparam);
2061         for (i = 0; i < priv->params.num_channels; i++) {
2062                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2063                 if (err)
2064                         goto err_close_channels;
2065         }
2066
2067         for (j = 0; j < priv->params.num_channels; j++) {
2068                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2069                 if (err)
2070                         goto err_close_channels;
2071         }
2072         return (0);
2073
2074 err_close_channels:
2075         while (i--) {
2076                 mlx5e_close_channel(&priv->channel[i]);
2077                 mlx5e_close_channel_wait(&priv->channel[i]);
2078         }
2079         return (err);
2080 }
2081
2082 static void
2083 mlx5e_close_channels(struct mlx5e_priv *priv)
2084 {
2085         int i;
2086
2087         for (i = 0; i < priv->params.num_channels; i++)
2088                 mlx5e_close_channel(&priv->channel[i]);
2089         for (i = 0; i < priv->params.num_channels; i++)
2090                 mlx5e_close_channel_wait(&priv->channel[i]);
2091 }
2092
2093 static int
2094 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2095 {
2096
2097         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2098                 uint8_t cq_mode;
2099
2100                 switch (priv->params.tx_cq_moderation_mode) {
2101                 case 0:
2102                 case 2:
2103                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2104                         break;
2105                 default:
2106                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2107                         break;
2108                 }
2109
2110                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2111                     priv->params.tx_cq_moderation_usec,
2112                     priv->params.tx_cq_moderation_pkts,
2113                     cq_mode));
2114         }
2115
2116         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2117             priv->params.tx_cq_moderation_usec,
2118             priv->params.tx_cq_moderation_pkts));
2119 }
2120
2121 static int
2122 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2123 {
2124
2125         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2126                 uint8_t cq_mode;
2127                 uint8_t dim_mode;
2128                 int retval;
2129
2130                 switch (priv->params.rx_cq_moderation_mode) {
2131                 case 0:
2132                 case 2:
2133                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2134                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2135                         break;
2136                 default:
2137                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2138                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2139                         break;
2140                 }
2141
2142                 /* tear down dynamic interrupt moderation */
2143                 mtx_lock(&rq->mtx);
2144                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2145                 mtx_unlock(&rq->mtx);
2146
2147                 /* wait for dynamic interrupt moderation work task, if any */
2148                 cancel_work_sync(&rq->dim.work);
2149
2150                 if (priv->params.rx_cq_moderation_mode >= 2) {
2151                         struct net_dim_cq_moder curr;
2152
2153                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2154
2155                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2156                             curr.usec, curr.pkts, cq_mode);
2157
2158                         /* set dynamic interrupt moderation mode and zero defaults */
2159                         mtx_lock(&rq->mtx);
2160                         rq->dim.mode = dim_mode;
2161                         rq->dim.state = 0;
2162                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2163                         mtx_unlock(&rq->mtx);
2164                 } else {
2165                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2166                             priv->params.rx_cq_moderation_usec,
2167                             priv->params.rx_cq_moderation_pkts,
2168                             cq_mode);
2169                 }
2170                 return (retval);
2171         }
2172
2173         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2174             priv->params.rx_cq_moderation_usec,
2175             priv->params.rx_cq_moderation_pkts));
2176 }
2177
2178 static int
2179 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2180 {
2181         int err;
2182         int i;
2183
2184         err = mlx5e_refresh_rq_params(priv, &c->rq);
2185         if (err)
2186                 goto done;
2187
2188         for (i = 0; i != c->num_tc; i++) {
2189                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2190                 if (err)
2191                         goto done;
2192         }
2193 done:
2194         return (err);
2195 }
2196
2197 int
2198 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2199 {
2200         int i;
2201
2202         /* check if channels are closed */
2203         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2204                 return (EINVAL);
2205
2206         for (i = 0; i < priv->params.num_channels; i++) {
2207                 int err;
2208
2209                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2210                 if (err)
2211                         return (err);
2212         }
2213         return (0);
2214 }
2215
2216 static int
2217 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2218 {
2219         struct mlx5_core_dev *mdev = priv->mdev;
2220         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2221         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2222
2223         memset(in, 0, sizeof(in));
2224
2225         MLX5_SET(tisc, tisc, prio, tc);
2226         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2227
2228         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2229 }
2230
2231 static void
2232 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2233 {
2234         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2235 }
2236
2237 static int
2238 mlx5e_open_tises(struct mlx5e_priv *priv)
2239 {
2240         int num_tc = priv->num_tc;
2241         int err;
2242         int tc;
2243
2244         for (tc = 0; tc < num_tc; tc++) {
2245                 err = mlx5e_open_tis(priv, tc);
2246                 if (err)
2247                         goto err_close_tises;
2248         }
2249
2250         return (0);
2251
2252 err_close_tises:
2253         for (tc--; tc >= 0; tc--)
2254                 mlx5e_close_tis(priv, tc);
2255
2256         return (err);
2257 }
2258
2259 static void
2260 mlx5e_close_tises(struct mlx5e_priv *priv)
2261 {
2262         int num_tc = priv->num_tc;
2263         int tc;
2264
2265         for (tc = 0; tc < num_tc; tc++)
2266                 mlx5e_close_tis(priv, tc);
2267 }
2268
2269 static int
2270 mlx5e_open_rqt(struct mlx5e_priv *priv)
2271 {
2272         struct mlx5_core_dev *mdev = priv->mdev;
2273         u32 *in;
2274         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2275         void *rqtc;
2276         int inlen;
2277         int err;
2278         int sz;
2279         int i;
2280
2281         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2282
2283         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2284         in = mlx5_vzalloc(inlen);
2285         if (in == NULL)
2286                 return (-ENOMEM);
2287         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2288
2289         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2290         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2291
2292         for (i = 0; i < sz; i++) {
2293                 int ix = i;
2294 #ifdef RSS
2295                 ix = rss_get_indirection_to_bucket(ix);
2296 #endif
2297                 /* ensure we don't overflow */
2298                 ix %= priv->params.num_channels;
2299
2300                 /* apply receive side scaling stride, if any */
2301                 ix -= ix % (int)priv->params.channels_rsss;
2302
2303                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2304         }
2305
2306         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2307
2308         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2309         if (!err)
2310                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2311
2312         kvfree(in);
2313
2314         return (err);
2315 }
2316
2317 static void
2318 mlx5e_close_rqt(struct mlx5e_priv *priv)
2319 {
2320         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2321         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2322
2323         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2324         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2325
2326         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2327 }
2328
2329 static void
2330 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2331 {
2332         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2333         __be32 *hkey;
2334
2335         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2336
2337 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2338
2339 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2340                           MLX5_HASH_FIELD_SEL_DST_IP)
2341
2342 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2343                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2344                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2345                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2346
2347 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2348                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2349                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2350
2351         if (priv->params.hw_lro_en) {
2352                 MLX5_SET(tirc, tirc, lro_enable_mask,
2353                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2354                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2355                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2356                     (priv->params.lro_wqe_sz -
2357                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2358                 /* TODO: add the option to choose timer value dynamically */
2359                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2360                     MLX5_CAP_ETH(priv->mdev,
2361                     lro_timer_supported_periods[2]));
2362         }
2363
2364         /* setup parameters for hashing TIR type, if any */
2365         switch (tt) {
2366         case MLX5E_TT_ANY:
2367                 MLX5_SET(tirc, tirc, disp_type,
2368                     MLX5_TIRC_DISP_TYPE_DIRECT);
2369                 MLX5_SET(tirc, tirc, inline_rqn,
2370                     priv->channel[0].rq.rqn);
2371                 break;
2372         default:
2373                 MLX5_SET(tirc, tirc, disp_type,
2374                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2375                 MLX5_SET(tirc, tirc, indirect_table,
2376                     priv->rqtn);
2377                 MLX5_SET(tirc, tirc, rx_hash_fn,
2378                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2379                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2380 #ifdef RSS
2381                 /*
2382                  * The FreeBSD RSS implementation does currently not
2383                  * support symmetric Toeplitz hashes:
2384                  */
2385                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2386                 rss_getkey((uint8_t *)hkey);
2387 #else
2388                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2389                 hkey[0] = cpu_to_be32(0xD181C62C);
2390                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2391                 hkey[2] = cpu_to_be32(0x1983A2FC);
2392                 hkey[3] = cpu_to_be32(0x943E1ADB);
2393                 hkey[4] = cpu_to_be32(0xD9389E6B);
2394                 hkey[5] = cpu_to_be32(0xD1039C2C);
2395                 hkey[6] = cpu_to_be32(0xA74499AD);
2396                 hkey[7] = cpu_to_be32(0x593D56D9);
2397                 hkey[8] = cpu_to_be32(0xF3253C06);
2398                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2399 #endif
2400                 break;
2401         }
2402
2403         switch (tt) {
2404         case MLX5E_TT_IPV4_TCP:
2405                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2406                     MLX5_L3_PROT_TYPE_IPV4);
2407                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2408                     MLX5_L4_PROT_TYPE_TCP);
2409 #ifdef RSS
2410                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2411                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2412                             MLX5_HASH_IP);
2413                 } else
2414 #endif
2415                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416                     MLX5_HASH_ALL);
2417                 break;
2418
2419         case MLX5E_TT_IPV6_TCP:
2420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421                     MLX5_L3_PROT_TYPE_IPV6);
2422                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2423                     MLX5_L4_PROT_TYPE_TCP);
2424 #ifdef RSS
2425                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2426                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2427                             MLX5_HASH_IP);
2428                 } else
2429 #endif
2430                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2431                     MLX5_HASH_ALL);
2432                 break;
2433
2434         case MLX5E_TT_IPV4_UDP:
2435                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2436                     MLX5_L3_PROT_TYPE_IPV4);
2437                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2438                     MLX5_L4_PROT_TYPE_UDP);
2439 #ifdef RSS
2440                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2441                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442                             MLX5_HASH_IP);
2443                 } else
2444 #endif
2445                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2446                     MLX5_HASH_ALL);
2447                 break;
2448
2449         case MLX5E_TT_IPV6_UDP:
2450                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2451                     MLX5_L3_PROT_TYPE_IPV6);
2452                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2453                     MLX5_L4_PROT_TYPE_UDP);
2454 #ifdef RSS
2455                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2456                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457                             MLX5_HASH_IP);
2458                 } else
2459 #endif
2460                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461                     MLX5_HASH_ALL);
2462                 break;
2463
2464         case MLX5E_TT_IPV4_IPSEC_AH:
2465                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2466                     MLX5_L3_PROT_TYPE_IPV4);
2467                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2468                     MLX5_HASH_IP_IPSEC_SPI);
2469                 break;
2470
2471         case MLX5E_TT_IPV6_IPSEC_AH:
2472                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2473                     MLX5_L3_PROT_TYPE_IPV6);
2474                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475                     MLX5_HASH_IP_IPSEC_SPI);
2476                 break;
2477
2478         case MLX5E_TT_IPV4_IPSEC_ESP:
2479                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2480                     MLX5_L3_PROT_TYPE_IPV4);
2481                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2482                     MLX5_HASH_IP_IPSEC_SPI);
2483                 break;
2484
2485         case MLX5E_TT_IPV6_IPSEC_ESP:
2486                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2487                     MLX5_L3_PROT_TYPE_IPV6);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                     MLX5_HASH_IP_IPSEC_SPI);
2490                 break;
2491
2492         case MLX5E_TT_IPV4:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                     MLX5_L3_PROT_TYPE_IPV4);
2495                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496                     MLX5_HASH_IP);
2497                 break;
2498
2499         case MLX5E_TT_IPV6:
2500                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2501                     MLX5_L3_PROT_TYPE_IPV6);
2502                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2503                     MLX5_HASH_IP);
2504                 break;
2505
2506         default:
2507                 break;
2508         }
2509 }
2510
2511 static int
2512 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2513 {
2514         struct mlx5_core_dev *mdev = priv->mdev;
2515         u32 *in;
2516         void *tirc;
2517         int inlen;
2518         int err;
2519
2520         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2521         in = mlx5_vzalloc(inlen);
2522         if (in == NULL)
2523                 return (-ENOMEM);
2524         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2525
2526         mlx5e_build_tir_ctx(priv, tirc, tt);
2527
2528         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2529
2530         kvfree(in);
2531
2532         return (err);
2533 }
2534
2535 static void
2536 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2537 {
2538         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2539 }
2540
2541 static int
2542 mlx5e_open_tirs(struct mlx5e_priv *priv)
2543 {
2544         int err;
2545         int i;
2546
2547         for (i = 0; i < MLX5E_NUM_TT; i++) {
2548                 err = mlx5e_open_tir(priv, i);
2549                 if (err)
2550                         goto err_close_tirs;
2551         }
2552
2553         return (0);
2554
2555 err_close_tirs:
2556         for (i--; i >= 0; i--)
2557                 mlx5e_close_tir(priv, i);
2558
2559         return (err);
2560 }
2561
2562 static void
2563 mlx5e_close_tirs(struct mlx5e_priv *priv)
2564 {
2565         int i;
2566
2567         for (i = 0; i < MLX5E_NUM_TT; i++)
2568                 mlx5e_close_tir(priv, i);
2569 }
2570
2571 /*
2572  * SW MTU does not include headers,
2573  * HW MTU includes all headers and checksums.
2574  */
2575 static int
2576 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2577 {
2578         struct mlx5e_priv *priv = ifp->if_softc;
2579         struct mlx5_core_dev *mdev = priv->mdev;
2580         int hw_mtu;
2581         int err;
2582
2583         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2584
2585         err = mlx5_set_port_mtu(mdev, hw_mtu);
2586         if (err) {
2587                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2588                     __func__, sw_mtu, err);
2589                 return (err);
2590         }
2591
2592         /* Update vport context MTU */
2593         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2594         if (err) {
2595                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2596                     __func__, err);
2597         }
2598
2599         ifp->if_mtu = sw_mtu;
2600
2601         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2602         if (err || !hw_mtu) {
2603                 /* fallback to port oper mtu */
2604                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2605         }
2606         if (err) {
2607                 if_printf(ifp, "Query port MTU, after setting new "
2608                     "MTU value, failed\n");
2609                 return (err);
2610         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2611                 err = -E2BIG,
2612                 if_printf(ifp, "Port MTU %d is smaller than "
2613                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2614         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2615                 err = -EINVAL;
2616                 if_printf(ifp, "Port MTU %d is bigger than "
2617                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2618         }
2619         priv->params_ethtool.hw_mtu = hw_mtu;
2620
2621         return (err);
2622 }
2623
2624 int
2625 mlx5e_open_locked(struct ifnet *ifp)
2626 {
2627         struct mlx5e_priv *priv = ifp->if_softc;
2628         int err;
2629         u16 set_id;
2630
2631         /* check if already opened */
2632         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2633                 return (0);
2634
2635 #ifdef RSS
2636         if (rss_getnumbuckets() > priv->params.num_channels) {
2637                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2638                     "channels(%u) available\n", rss_getnumbuckets(),
2639                     priv->params.num_channels);
2640         }
2641 #endif
2642         err = mlx5e_open_tises(priv);
2643         if (err) {
2644                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2645                     __func__, err);
2646                 return (err);
2647         }
2648         err = mlx5_vport_alloc_q_counter(priv->mdev,
2649             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2650         if (err) {
2651                 if_printf(priv->ifp,
2652                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2653                     __func__, err);
2654                 goto err_close_tises;
2655         }
2656         /* store counter set ID */
2657         priv->counter_set_id = set_id;
2658
2659         err = mlx5e_open_channels(priv);
2660         if (err) {
2661                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2662                     __func__, err);
2663                 goto err_dalloc_q_counter;
2664         }
2665         err = mlx5e_open_rqt(priv);
2666         if (err) {
2667                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2668                     __func__, err);
2669                 goto err_close_channels;
2670         }
2671         err = mlx5e_open_tirs(priv);
2672         if (err) {
2673                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2674                     __func__, err);
2675                 goto err_close_rqls;
2676         }
2677         err = mlx5e_open_flow_table(priv);
2678         if (err) {
2679                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2680                     __func__, err);
2681                 goto err_close_tirs;
2682         }
2683         err = mlx5e_add_all_vlan_rules(priv);
2684         if (err) {
2685                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2686                     __func__, err);
2687                 goto err_close_flow_table;
2688         }
2689         set_bit(MLX5E_STATE_OPENED, &priv->state);
2690
2691         mlx5e_update_carrier(priv);
2692         mlx5e_set_rx_mode_core(priv);
2693
2694         return (0);
2695
2696 err_close_flow_table:
2697         mlx5e_close_flow_table(priv);
2698
2699 err_close_tirs:
2700         mlx5e_close_tirs(priv);
2701
2702 err_close_rqls:
2703         mlx5e_close_rqt(priv);
2704
2705 err_close_channels:
2706         mlx5e_close_channels(priv);
2707
2708 err_dalloc_q_counter:
2709         mlx5_vport_dealloc_q_counter(priv->mdev,
2710             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2711
2712 err_close_tises:
2713         mlx5e_close_tises(priv);
2714
2715         return (err);
2716 }
2717
2718 static void
2719 mlx5e_open(void *arg)
2720 {
2721         struct mlx5e_priv *priv = arg;
2722
2723         PRIV_LOCK(priv);
2724         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2725                 if_printf(priv->ifp,
2726                     "%s: Setting port status to up failed\n",
2727                     __func__);
2728
2729         mlx5e_open_locked(priv->ifp);
2730         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2731         PRIV_UNLOCK(priv);
2732 }
2733
2734 int
2735 mlx5e_close_locked(struct ifnet *ifp)
2736 {
2737         struct mlx5e_priv *priv = ifp->if_softc;
2738
2739         /* check if already closed */
2740         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2741                 return (0);
2742
2743         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2744
2745         mlx5e_set_rx_mode_core(priv);
2746         mlx5e_del_all_vlan_rules(priv);
2747         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2748         mlx5e_close_flow_table(priv);
2749         mlx5e_close_tirs(priv);
2750         mlx5e_close_rqt(priv);
2751         mlx5e_close_channels(priv);
2752         mlx5_vport_dealloc_q_counter(priv->mdev,
2753             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2754         mlx5e_close_tises(priv);
2755
2756         return (0);
2757 }
2758
2759 #if (__FreeBSD_version >= 1100000)
2760 static uint64_t
2761 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2762 {
2763         struct mlx5e_priv *priv = ifp->if_softc;
2764         u64 retval;
2765
2766         /* PRIV_LOCK(priv); XXX not allowed */
2767         switch (cnt) {
2768         case IFCOUNTER_IPACKETS:
2769                 retval = priv->stats.vport.rx_packets;
2770                 break;
2771         case IFCOUNTER_IERRORS:
2772                 retval = priv->stats.vport.rx_error_packets +
2773                     priv->stats.pport.alignment_err +
2774                     priv->stats.pport.check_seq_err +
2775                     priv->stats.pport.crc_align_errors +
2776                     priv->stats.pport.in_range_len_errors +
2777                     priv->stats.pport.jabbers +
2778                     priv->stats.pport.out_of_range_len +
2779                     priv->stats.pport.oversize_pkts +
2780                     priv->stats.pport.symbol_err +
2781                     priv->stats.pport.too_long_errors +
2782                     priv->stats.pport.undersize_pkts +
2783                     priv->stats.pport.unsupported_op_rx;
2784                 break;
2785         case IFCOUNTER_IQDROPS:
2786                 retval = priv->stats.vport.rx_out_of_buffer +
2787                     priv->stats.pport.drop_events;
2788                 break;
2789         case IFCOUNTER_OPACKETS:
2790                 retval = priv->stats.vport.tx_packets;
2791                 break;
2792         case IFCOUNTER_OERRORS:
2793                 retval = priv->stats.vport.tx_error_packets;
2794                 break;
2795         case IFCOUNTER_IBYTES:
2796                 retval = priv->stats.vport.rx_bytes;
2797                 break;
2798         case IFCOUNTER_OBYTES:
2799                 retval = priv->stats.vport.tx_bytes;
2800                 break;
2801         case IFCOUNTER_IMCASTS:
2802                 retval = priv->stats.vport.rx_multicast_packets;
2803                 break;
2804         case IFCOUNTER_OMCASTS:
2805                 retval = priv->stats.vport.tx_multicast_packets;
2806                 break;
2807         case IFCOUNTER_OQDROPS:
2808                 retval = priv->stats.vport.tx_queue_dropped;
2809                 break;
2810         case IFCOUNTER_COLLISIONS:
2811                 retval = priv->stats.pport.collisions;
2812                 break;
2813         default:
2814                 retval = if_get_counter_default(ifp, cnt);
2815                 break;
2816         }
2817         /* PRIV_UNLOCK(priv); XXX not allowed */
2818         return (retval);
2819 }
2820 #endif
2821
2822 static void
2823 mlx5e_set_rx_mode(struct ifnet *ifp)
2824 {
2825         struct mlx5e_priv *priv = ifp->if_softc;
2826
2827         queue_work(priv->wq, &priv->set_rx_mode_work);
2828 }
2829
2830 static int
2831 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2832 {
2833         struct mlx5e_priv *priv;
2834         struct ifreq *ifr;
2835         struct ifi2creq i2c;
2836         int error = 0;
2837         int mask = 0;
2838         int size_read = 0;
2839         int module_status;
2840         int module_num;
2841         int max_mtu;
2842         uint8_t read_addr;
2843
2844         priv = ifp->if_softc;
2845
2846         /* check if detaching */
2847         if (priv == NULL || priv->gone != 0)
2848                 return (ENXIO);
2849
2850         switch (command) {
2851         case SIOCSIFMTU:
2852                 ifr = (struct ifreq *)data;
2853
2854                 PRIV_LOCK(priv);
2855                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2856
2857                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2858                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2859                         int was_opened;
2860
2861                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2862                         if (was_opened)
2863                                 mlx5e_close_locked(ifp);
2864
2865                         /* set new MTU */
2866                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2867
2868                         if (was_opened)
2869                                 mlx5e_open_locked(ifp);
2870                 } else {
2871                         error = EINVAL;
2872                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2873                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2874                 }
2875                 PRIV_UNLOCK(priv);
2876                 break;
2877         case SIOCSIFFLAGS:
2878                 if ((ifp->if_flags & IFF_UP) &&
2879                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2880                         mlx5e_set_rx_mode(ifp);
2881                         break;
2882                 }
2883                 PRIV_LOCK(priv);
2884                 if (ifp->if_flags & IFF_UP) {
2885                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2886                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2887                                         mlx5e_open_locked(ifp);
2888                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2889                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2890                         }
2891                 } else {
2892                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2893                                 mlx5_set_port_status(priv->mdev,
2894                                     MLX5_PORT_DOWN);
2895                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2896                                         mlx5e_close_locked(ifp);
2897                                 mlx5e_update_carrier(priv);
2898                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2899                         }
2900                 }
2901                 PRIV_UNLOCK(priv);
2902                 break;
2903         case SIOCADDMULTI:
2904         case SIOCDELMULTI:
2905                 mlx5e_set_rx_mode(ifp);
2906                 break;
2907         case SIOCSIFMEDIA:
2908         case SIOCGIFMEDIA:
2909         case SIOCGIFXMEDIA:
2910                 ifr = (struct ifreq *)data;
2911                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2912                 break;
2913         case SIOCSIFCAP:
2914                 ifr = (struct ifreq *)data;
2915                 PRIV_LOCK(priv);
2916                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2917
2918                 if (mask & IFCAP_TXCSUM) {
2919                         ifp->if_capenable ^= IFCAP_TXCSUM;
2920                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2921
2922                         if (IFCAP_TSO4 & ifp->if_capenable &&
2923                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2924                                 ifp->if_capenable &= ~IFCAP_TSO4;
2925                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2926                                 if_printf(ifp,
2927                                     "tso4 disabled due to -txcsum.\n");
2928                         }
2929                 }
2930                 if (mask & IFCAP_TXCSUM_IPV6) {
2931                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2932                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2933
2934                         if (IFCAP_TSO6 & ifp->if_capenable &&
2935                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2936                                 ifp->if_capenable &= ~IFCAP_TSO6;
2937                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2938                                 if_printf(ifp,
2939                                     "tso6 disabled due to -txcsum6.\n");
2940                         }
2941                 }
2942                 if (mask & IFCAP_RXCSUM)
2943                         ifp->if_capenable ^= IFCAP_RXCSUM;
2944                 if (mask & IFCAP_RXCSUM_IPV6)
2945                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2946                 if (mask & IFCAP_TSO4) {
2947                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2948                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2949                                 if_printf(ifp, "enable txcsum first.\n");
2950                                 error = EAGAIN;
2951                                 goto out;
2952                         }
2953                         ifp->if_capenable ^= IFCAP_TSO4;
2954                         ifp->if_hwassist ^= CSUM_IP_TSO;
2955                 }
2956                 if (mask & IFCAP_TSO6) {
2957                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2958                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2959                                 if_printf(ifp, "enable txcsum6 first.\n");
2960                                 error = EAGAIN;
2961                                 goto out;
2962                         }
2963                         ifp->if_capenable ^= IFCAP_TSO6;
2964                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2965                 }
2966                 if (mask & IFCAP_VLAN_HWFILTER) {
2967                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2968                                 mlx5e_disable_vlan_filter(priv);
2969                         else
2970                                 mlx5e_enable_vlan_filter(priv);
2971
2972                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2973                 }
2974                 if (mask & IFCAP_VLAN_HWTAGGING)
2975                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2976                 if (mask & IFCAP_WOL_MAGIC)
2977                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2978
2979                 VLAN_CAPABILITIES(ifp);
2980                 /* turn off LRO means also turn of HW LRO - if it's on */
2981                 if (mask & IFCAP_LRO) {
2982                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2983                         bool need_restart = false;
2984
2985                         ifp->if_capenable ^= IFCAP_LRO;
2986
2987                         /* figure out if updating HW LRO is needed */
2988                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2989                                 if (priv->params.hw_lro_en) {
2990                                         priv->params.hw_lro_en = false;
2991                                         need_restart = true;
2992                                 }
2993                         } else {
2994                                 if (priv->params.hw_lro_en == false &&
2995                                     priv->params_ethtool.hw_lro != 0) {
2996                                         priv->params.hw_lro_en = true;
2997                                         need_restart = true;
2998                                 }
2999                         }
3000                         if (was_opened && need_restart) {
3001                                 mlx5e_close_locked(ifp);
3002                                 mlx5e_open_locked(ifp);
3003                         }
3004                 }
3005                 if (mask & IFCAP_HWRXTSTMP) {
3006                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3007                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3008                                 if (priv->clbr_done == 0)
3009                                         mlx5e_reset_calibration_callout(priv);
3010                         } else {
3011                                 callout_drain(&priv->tstmp_clbr);
3012                                 priv->clbr_done = 0;
3013                         }
3014                 }
3015 out:
3016                 PRIV_UNLOCK(priv);
3017                 break;
3018
3019         case SIOCGI2C:
3020                 ifr = (struct ifreq *)data;
3021
3022                 /*
3023                  * Copy from the user-space address ifr_data to the
3024                  * kernel-space address i2c
3025                  */
3026                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3027                 if (error)
3028                         break;
3029
3030                 if (i2c.len > sizeof(i2c.data)) {
3031                         error = EINVAL;
3032                         break;
3033                 }
3034
3035                 PRIV_LOCK(priv);
3036                 /* Get module_num which is required for the query_eeprom */
3037                 error = mlx5_query_module_num(priv->mdev, &module_num);
3038                 if (error) {
3039                         if_printf(ifp, "Query module num failed, eeprom "
3040                             "reading is not supported\n");
3041                         error = EINVAL;
3042                         goto err_i2c;
3043                 }
3044                 /* Check if module is present before doing an access */
3045                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3046                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3047                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3048                         error = EINVAL;
3049                         goto err_i2c;
3050                 }
3051                 /*
3052                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3053                  * The internal conversion is as follows:
3054                  */
3055                 if (i2c.dev_addr == 0xA0)
3056                         read_addr = MLX5E_I2C_ADDR_LOW;
3057                 else if (i2c.dev_addr == 0xA2)
3058                         read_addr = MLX5E_I2C_ADDR_HIGH;
3059                 else {
3060                         if_printf(ifp, "Query eeprom failed, "
3061                             "Invalid Address: %X\n", i2c.dev_addr);
3062                         error = EINVAL;
3063                         goto err_i2c;
3064                 }
3065                 error = mlx5_query_eeprom(priv->mdev,
3066                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3067                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3068                     (uint32_t *)i2c.data, &size_read);
3069                 if (error) {
3070                         if_printf(ifp, "Query eeprom failed, eeprom "
3071                             "reading is not supported\n");
3072                         error = EINVAL;
3073                         goto err_i2c;
3074                 }
3075
3076                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3077                         error = mlx5_query_eeprom(priv->mdev,
3078                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3079                             (uint32_t)(i2c.offset + size_read),
3080                             (uint32_t)(i2c.len - size_read), module_num,
3081                             (uint32_t *)(i2c.data + size_read), &size_read);
3082                 }
3083                 if (error) {
3084                         if_printf(ifp, "Query eeprom failed, eeprom "
3085                             "reading is not supported\n");
3086                         error = EINVAL;
3087                         goto err_i2c;
3088                 }
3089
3090                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3091 err_i2c:
3092                 PRIV_UNLOCK(priv);
3093                 break;
3094
3095         default:
3096                 error = ether_ioctl(ifp, command, data);
3097                 break;
3098         }
3099         return (error);
3100 }
3101
3102 static int
3103 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3104 {
3105         /*
3106          * TODO: uncoment once FW really sets all these bits if
3107          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3108          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3109          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3110          * -ENOTSUPP;
3111          */
3112
3113         /* TODO: add more must-to-have features */
3114
3115         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3116                 return (-ENODEV);
3117
3118         return (0);
3119 }
3120
3121 static u16
3122 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3123 {
3124         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3125
3126         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3127
3128         /* verify against driver hardware limit */
3129         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3130                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3131
3132         return (bf_buf_size);
3133 }
3134
3135 static int
3136 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3137     struct mlx5e_priv *priv,
3138     int num_comp_vectors)
3139 {
3140         int err;
3141
3142         /*
3143          * TODO: Consider link speed for setting "log_sq_size",
3144          * "log_rq_size" and "cq_moderation_xxx":
3145          */
3146         priv->params.log_sq_size =
3147             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3148         priv->params.log_rq_size =
3149             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3150         priv->params.rx_cq_moderation_usec =
3151             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3152             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3153             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3154         priv->params.rx_cq_moderation_mode =
3155             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3156         priv->params.rx_cq_moderation_pkts =
3157             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3158         priv->params.tx_cq_moderation_usec =
3159             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3160         priv->params.tx_cq_moderation_pkts =
3161             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3162         priv->params.min_rx_wqes =
3163             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3164         priv->params.rx_hash_log_tbl_sz =
3165             (order_base_2(num_comp_vectors) >
3166             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3167             order_base_2(num_comp_vectors) :
3168             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3169         priv->params.num_tc = 1;
3170         priv->params.default_vlan_prio = 0;
3171         priv->counter_set_id = -1;
3172         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3173
3174         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3175         if (err)
3176                 return (err);
3177
3178         /*
3179          * hw lro is currently defaulted to off. when it won't anymore we
3180          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3181          */
3182         priv->params.hw_lro_en = false;
3183         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3184
3185         /*
3186          * CQE zipping is currently defaulted to off. when it won't
3187          * anymore we will consider the HW capability:
3188          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3189          */
3190         priv->params.cqe_zipping_en = false;
3191
3192         priv->mdev = mdev;
3193         priv->params.num_channels = num_comp_vectors;
3194         priv->params.channels_rsss = 1;
3195         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3196         priv->queue_mapping_channel_mask =
3197             roundup_pow_of_two(num_comp_vectors) - 1;
3198         priv->num_tc = priv->params.num_tc;
3199         priv->default_vlan_prio = priv->params.default_vlan_prio;
3200
3201         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3202         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3203         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3204
3205         return (0);
3206 }
3207
3208 static int
3209 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3210                   struct mlx5_core_mr *mkey)
3211 {
3212         struct ifnet *ifp = priv->ifp;
3213         struct mlx5_core_dev *mdev = priv->mdev;
3214         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3215         void *mkc;
3216         u32 *in;
3217         int err;
3218
3219         in = mlx5_vzalloc(inlen);
3220         if (in == NULL) {
3221                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3222                 return (-ENOMEM);
3223         }
3224
3225         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3226         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3227         MLX5_SET(mkc, mkc, lw, 1);
3228         MLX5_SET(mkc, mkc, lr, 1);
3229
3230         MLX5_SET(mkc, mkc, pd, pdn);
3231         MLX5_SET(mkc, mkc, length64, 1);
3232         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3233
3234         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3235         if (err)
3236                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3237                     __func__, err);
3238
3239         kvfree(in);
3240         return (err);
3241 }
3242
3243 static const char *mlx5e_vport_stats_desc[] = {
3244         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3245 };
3246
3247 static const char *mlx5e_pport_stats_desc[] = {
3248         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3249 };
3250
3251 static void
3252 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3253 {
3254         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3255         sx_init(&priv->state_lock, "mlx5state");
3256         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3257         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3258 }
3259
3260 static void
3261 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3262 {
3263         mtx_destroy(&priv->async_events_mtx);
3264         sx_destroy(&priv->state_lock);
3265 }
3266
3267 static int
3268 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3269 {
3270         /*
3271          * %d.%d%.d the string format.
3272          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3273          * We need at most 5 chars to store that.
3274          * It also has: two "." and NULL at the end, which means we need 18
3275          * (5*3 + 3) chars at most.
3276          */
3277         char fw[18];
3278         struct mlx5e_priv *priv = arg1;
3279         int error;
3280
3281         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3282             fw_rev_sub(priv->mdev));
3283         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3284         return (error);
3285 }
3286
3287 static void
3288 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3289 {
3290         int i;
3291
3292         for (i = 0; i < ch->num_tc; i++)
3293                 mlx5e_drain_sq(&ch->sq[i]);
3294 }
3295
3296 static void
3297 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3298 {
3299
3300         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3301         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3302         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3303         sq->doorbell.d64 = 0;
3304 }
3305
3306 void
3307 mlx5e_resume_sq(struct mlx5e_sq *sq)
3308 {
3309         int err;
3310
3311         /* check if already enabled */
3312         if (READ_ONCE(sq->running) != 0)
3313                 return;
3314
3315         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3316             MLX5_SQC_STATE_RST);
3317         if (err != 0) {
3318                 if_printf(sq->ifp,
3319                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3320         }
3321
3322         sq->cc = 0;
3323         sq->pc = 0;
3324
3325         /* reset doorbell prior to moving from RST to RDY */
3326         mlx5e_reset_sq_doorbell_record(sq);
3327
3328         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3329             MLX5_SQC_STATE_RDY);
3330         if (err != 0) {
3331                 if_printf(sq->ifp,
3332                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3333         }
3334
3335         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3336         WRITE_ONCE(sq->running, 1);
3337 }
3338
3339 static void
3340 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3341 {
3342         int i;
3343
3344         for (i = 0; i < ch->num_tc; i++)
3345                 mlx5e_resume_sq(&ch->sq[i]);
3346 }
3347
3348 static void
3349 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3350 {
3351         struct mlx5e_rq *rq = &ch->rq;
3352         int err;
3353
3354         mtx_lock(&rq->mtx);
3355         rq->enabled = 0;
3356         callout_stop(&rq->watchdog);
3357         mtx_unlock(&rq->mtx);
3358
3359         callout_drain(&rq->watchdog);
3360
3361         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3362         if (err != 0) {
3363                 if_printf(rq->ifp,
3364                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3365         }
3366
3367         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3368                 msleep(1);
3369                 rq->cq.mcq.comp(&rq->cq.mcq);
3370         }
3371
3372         /*
3373          * Transitioning into RST state will allow the FW to track less ERR state queues,
3374          * thus reducing the recv queue flushing time
3375          */
3376         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3377         if (err != 0) {
3378                 if_printf(rq->ifp,
3379                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3380         }
3381 }
3382
3383 static void
3384 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3385 {
3386         struct mlx5e_rq *rq = &ch->rq;
3387         int err;
3388
3389         rq->wq.wqe_ctr = 0;
3390         mlx5_wq_ll_update_db_record(&rq->wq);
3391         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3392         if (err != 0) {
3393                 if_printf(rq->ifp,
3394                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3395         }
3396
3397         rq->enabled = 1;
3398
3399         rq->cq.mcq.comp(&rq->cq.mcq);
3400 }
3401
3402 void
3403 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3404 {
3405         int i;
3406
3407         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3408                 return;
3409
3410         for (i = 0; i < priv->params.num_channels; i++) {
3411                 if (value)
3412                         mlx5e_disable_tx_dma(&priv->channel[i]);
3413                 else
3414                         mlx5e_enable_tx_dma(&priv->channel[i]);
3415         }
3416 }
3417
3418 void
3419 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3420 {
3421         int i;
3422
3423         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3424                 return;
3425
3426         for (i = 0; i < priv->params.num_channels; i++) {
3427                 if (value)
3428                         mlx5e_disable_rx_dma(&priv->channel[i]);
3429                 else
3430                         mlx5e_enable_rx_dma(&priv->channel[i]);
3431         }
3432 }
3433
3434 static void
3435 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3436 {
3437         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3438             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3439             sysctl_firmware, "A", "HCA firmware version");
3440
3441         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3442             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3443             "Board ID");
3444 }
3445
3446 static int
3447 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3448 {
3449         struct mlx5e_priv *priv = arg1;
3450         uint8_t temp[MLX5E_MAX_PRIORITY];
3451         uint32_t tx_pfc;
3452         int err;
3453         int i;
3454
3455         PRIV_LOCK(priv);
3456
3457         tx_pfc = priv->params.tx_priority_flow_control;
3458
3459         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3460                 temp[i] = (tx_pfc >> i) & 1;
3461
3462         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3463         if (err || !req->newptr)
3464                 goto done;
3465         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3466         if (err)
3467                 goto done;
3468
3469         priv->params.tx_priority_flow_control = 0;
3470
3471         /* range check input value */
3472         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3473                 if (temp[i] > 1) {
3474                         err = ERANGE;
3475                         goto done;
3476                 }
3477                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3478         }
3479
3480         /* check if update is required */
3481         if (tx_pfc != priv->params.tx_priority_flow_control)
3482                 err = -mlx5e_set_port_pfc(priv);
3483 done:
3484         if (err != 0)
3485                 priv->params.tx_priority_flow_control= tx_pfc;
3486         PRIV_UNLOCK(priv);
3487
3488         return (err);
3489 }
3490
3491 static int
3492 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3493 {
3494         struct mlx5e_priv *priv = arg1;
3495         uint8_t temp[MLX5E_MAX_PRIORITY];
3496         uint32_t rx_pfc;
3497         int err;
3498         int i;
3499
3500         PRIV_LOCK(priv);
3501
3502         rx_pfc = priv->params.rx_priority_flow_control;
3503
3504         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3505                 temp[i] = (rx_pfc >> i) & 1;
3506
3507         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3508         if (err || !req->newptr)
3509                 goto done;
3510         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3511         if (err)
3512                 goto done;
3513
3514         priv->params.rx_priority_flow_control = 0;
3515
3516         /* range check input value */
3517         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3518                 if (temp[i] > 1) {
3519                         err = ERANGE;
3520                         goto done;
3521                 }
3522                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3523         }
3524
3525         /* check if update is required */
3526         if (rx_pfc != priv->params.rx_priority_flow_control)
3527                 err = -mlx5e_set_port_pfc(priv);
3528 done:
3529         if (err != 0)
3530                 priv->params.rx_priority_flow_control= rx_pfc;
3531         PRIV_UNLOCK(priv);
3532
3533         return (err);
3534 }
3535
3536 static void
3537 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3538 {
3539 #if (__FreeBSD_version < 1100000)
3540         char path[96];
3541 #endif
3542         int error;
3543
3544         /* enable pauseframes by default */
3545         priv->params.tx_pauseframe_control = 1;
3546         priv->params.rx_pauseframe_control = 1;
3547
3548         /* disable ports flow control, PFC, by default */
3549         priv->params.tx_priority_flow_control = 0;
3550         priv->params.rx_priority_flow_control = 0;
3551
3552 #if (__FreeBSD_version < 1100000)
3553         /* compute path for sysctl */
3554         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3555             device_get_unit(priv->mdev->pdev->dev.bsddev));
3556
3557         /* try to fetch tunable, if any */
3558         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3559
3560         /* compute path for sysctl */
3561         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3562             device_get_unit(priv->mdev->pdev->dev.bsddev));
3563
3564         /* try to fetch tunable, if any */
3565         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3566 #endif
3567
3568         /* register pauseframe SYSCTLs */
3569         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3570             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3571             &priv->params.tx_pauseframe_control, 0,
3572             "Set to enable TX pause frames. Clear to disable.");
3573
3574         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3575             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3576             &priv->params.rx_pauseframe_control, 0,
3577             "Set to enable RX pause frames. Clear to disable.");
3578
3579         /* register priority flow control, PFC, SYSCTLs */
3580         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3581             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3582             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3583             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3584
3585         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3586             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3587             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3588             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3589
3590         PRIV_LOCK(priv);
3591
3592         /* range check */
3593         priv->params.tx_pauseframe_control =
3594             priv->params.tx_pauseframe_control ? 1 : 0;
3595         priv->params.rx_pauseframe_control =
3596             priv->params.rx_pauseframe_control ? 1 : 0;
3597
3598         /* update firmware */
3599         error = mlx5e_set_port_pause_and_pfc(priv);
3600         if (error == -EINVAL) {
3601                 if_printf(priv->ifp,
3602                     "Global pauseframes must be disabled before enabling PFC.\n");
3603                 priv->params.rx_priority_flow_control = 0;
3604                 priv->params.tx_priority_flow_control = 0;
3605
3606                 /* update firmware */
3607                 (void) mlx5e_set_port_pause_and_pfc(priv);
3608         }
3609         PRIV_UNLOCK(priv);
3610 }
3611
3612 static int
3613 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3614     union if_snd_tag_alloc_params *params,
3615     struct m_snd_tag **ppmt)
3616 {
3617         struct mlx5e_priv *priv;
3618         struct mlx5e_channel *pch;
3619
3620         priv = ifp->if_softc;
3621
3622         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3623                 return (EOPNOTSUPP);
3624         } else {
3625                 /* keep this code synced with mlx5e_select_queue() */
3626                 u32 ch = priv->params.num_channels;
3627 #ifdef RSS
3628                 u32 temp;
3629
3630                 if (rss_hash2bucket(params->hdr.flowid,
3631                     params->hdr.flowtype, &temp) == 0)
3632                         ch = temp % ch;
3633                 else
3634 #endif
3635                         ch = (params->hdr.flowid % 128) % ch;
3636
3637                 /*
3638                  * NOTE: The channels array is only freed at detach
3639                  * and it safe to return a pointer to the send tag
3640                  * inside the channels structure as long as we
3641                  * reference the priv.
3642                  */
3643                 pch = priv->channel + ch;
3644
3645                 /* check if send queue is not running */
3646                 if (unlikely(pch->sq[0].running == 0))
3647                         return (ENXIO);
3648                 mlx5e_ref_channel(priv);
3649                 *ppmt = &pch->tag.m_snd_tag;
3650                 return (0);
3651         }
3652 }
3653
3654 static int
3655 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3656 {
3657         struct mlx5e_channel *pch =
3658             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3659
3660         params->unlimited.max_rate = -1ULL;
3661         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3662         return (0);
3663 }
3664
3665 static void
3666 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3667 {
3668         struct mlx5e_channel *pch =
3669             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3670
3671         mlx5e_unref_channel(pch->priv);
3672 }
3673
3674 static int
3675 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3676     union if_snd_tag_alloc_params *params,
3677     struct m_snd_tag **ppmt)
3678 {
3679
3680         switch (params->hdr.type) {
3681 #ifdef RATELIMIT
3682         case IF_SND_TAG_TYPE_RATE_LIMIT:
3683                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3684 #endif
3685         case IF_SND_TAG_TYPE_UNLIMITED:
3686                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3687         default:
3688                 return (EOPNOTSUPP);
3689         }
3690 }
3691
3692 static int
3693 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3694 {
3695         struct mlx5e_snd_tag *tag =
3696             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3697
3698         switch (tag->type) {
3699 #ifdef RATELIMIT
3700         case IF_SND_TAG_TYPE_RATE_LIMIT:
3701                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3702 #endif
3703         case IF_SND_TAG_TYPE_UNLIMITED:
3704         default:
3705                 return (EOPNOTSUPP);
3706         }
3707 }
3708
3709 static int
3710 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3711 {
3712         struct mlx5e_snd_tag *tag =
3713             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3714
3715         switch (tag->type) {
3716 #ifdef RATELIMIT
3717         case IF_SND_TAG_TYPE_RATE_LIMIT:
3718                 return (mlx5e_rl_snd_tag_query(pmt, params));
3719 #endif
3720         case IF_SND_TAG_TYPE_UNLIMITED:
3721                 return (mlx5e_ul_snd_tag_query(pmt, params));
3722         default:
3723                 return (EOPNOTSUPP);
3724         }
3725 }
3726
3727 static void
3728 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3729 {
3730         struct mlx5e_snd_tag *tag =
3731             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3732
3733         switch (tag->type) {
3734 #ifdef RATELIMIT
3735         case IF_SND_TAG_TYPE_RATE_LIMIT:
3736                 mlx5e_rl_snd_tag_free(pmt);
3737                 break;
3738 #endif
3739         case IF_SND_TAG_TYPE_UNLIMITED:
3740                 mlx5e_ul_snd_tag_free(pmt);
3741                 break;
3742         default:
3743                 break;
3744         }
3745 }
3746
3747 static void *
3748 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3749 {
3750         struct ifnet *ifp;
3751         struct mlx5e_priv *priv;
3752         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3753         struct sysctl_oid_list *child;
3754         int ncv = mdev->priv.eq_table.num_comp_vectors;
3755         char unit[16];
3756         int err;
3757         int i;
3758         u32 eth_proto_cap;
3759
3760         if (mlx5e_check_required_hca_cap(mdev)) {
3761                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3762                 return (NULL);
3763         }
3764         /*
3765          * Try to allocate the priv and make room for worst-case
3766          * number of channel structures:
3767          */
3768         priv = malloc(sizeof(*priv) +
3769             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3770             M_MLX5EN, M_WAITOK | M_ZERO);
3771         mlx5e_priv_mtx_init(priv);
3772
3773         ifp = priv->ifp = if_alloc(IFT_ETHER);
3774         if (ifp == NULL) {
3775                 mlx5_core_err(mdev, "if_alloc() failed\n");
3776                 goto err_free_priv;
3777         }
3778         ifp->if_softc = priv;
3779         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3780         ifp->if_mtu = ETHERMTU;
3781         ifp->if_init = mlx5e_open;
3782         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3783         ifp->if_ioctl = mlx5e_ioctl;
3784         ifp->if_transmit = mlx5e_xmit;
3785         ifp->if_qflush = if_qflush;
3786 #if (__FreeBSD_version >= 1100000)
3787         ifp->if_get_counter = mlx5e_get_counter;
3788 #endif
3789         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3790         /*
3791          * Set driver features
3792          */
3793         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3794         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3795         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3796         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3797         ifp->if_capabilities |= IFCAP_LRO;
3798         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3799         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3800         ifp->if_capabilities |= IFCAP_TXRTLMT;
3801         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3802         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3803         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3804         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3805
3806         /* set TSO limits so that we don't have to drop TX packets */
3807         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3808         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3809         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3810
3811         ifp->if_capenable = ifp->if_capabilities;
3812         ifp->if_hwassist = 0;
3813         if (ifp->if_capenable & IFCAP_TSO)
3814                 ifp->if_hwassist |= CSUM_TSO;
3815         if (ifp->if_capenable & IFCAP_TXCSUM)
3816                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3817         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3818                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3819
3820         /* ifnet sysctl tree */
3821         sysctl_ctx_init(&priv->sysctl_ctx);
3822         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3823             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3824         if (priv->sysctl_ifnet == NULL) {
3825                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3826                 goto err_free_sysctl;
3827         }
3828         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3829         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3830             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3831         if (priv->sysctl_ifnet == NULL) {
3832                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3833                 goto err_free_sysctl;
3834         }
3835
3836         /* HW sysctl tree */
3837         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3838         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3839             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3840         if (priv->sysctl_hw == NULL) {
3841                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3842                 goto err_free_sysctl;
3843         }
3844
3845         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3846         if (err) {
3847                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3848                 goto err_free_sysctl;
3849         }
3850
3851         snprintf(unit, sizeof(unit), "mce%u_wq",
3852             device_get_unit(mdev->pdev->dev.bsddev));
3853         priv->wq = alloc_workqueue(unit, 0, 1);
3854         if (priv->wq == NULL) {
3855                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3856                 goto err_free_sysctl;
3857         }
3858
3859         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3860         if (err) {
3861                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3862                     __func__, err);
3863                 goto err_free_wq;
3864         }
3865         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3866         if (err) {
3867                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3868                     __func__, err);
3869                 goto err_unmap_free_uar;
3870         }
3871         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3872         if (err) {
3873                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3874                     __func__, err);
3875                 goto err_dealloc_pd;
3876         }
3877         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3878         if (err) {
3879                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3880                     __func__, err);
3881                 goto err_dealloc_transport_domain;
3882         }
3883         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3884
3885         /* check if we should generate a random MAC address */
3886         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3887             is_zero_ether_addr(dev_addr)) {
3888                 random_ether_addr(dev_addr);
3889                 if_printf(ifp, "Assigned random MAC address\n");
3890         }
3891 #ifdef RATELIMIT
3892         err = mlx5e_rl_init(priv);
3893         if (err) {
3894                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3895                     __func__, err);
3896                 goto err_create_mkey;
3897         }
3898 #endif
3899
3900         /* set default MTU */
3901         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3902
3903         /* Set default media status */
3904         priv->media_status_last = IFM_AVALID;
3905         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3906             IFM_ETH_RXPAUSE | IFM_FDX;
3907
3908         /* setup default pauseframes configuration */
3909         mlx5e_setup_pauseframes(priv);
3910
3911         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3912         if (err) {
3913                 eth_proto_cap = 0;
3914                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3915                     __func__, err);
3916         }
3917
3918         /* Setup supported medias */
3919         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3920             mlx5e_media_change, mlx5e_media_status);
3921
3922         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3923                 if (mlx5e_mode_table[i].baudrate == 0)
3924                         continue;
3925                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3926                         ifmedia_add(&priv->media,
3927                             mlx5e_mode_table[i].subtype |
3928                             IFM_ETHER, 0, NULL);
3929                         ifmedia_add(&priv->media,
3930                             mlx5e_mode_table[i].subtype |
3931                             IFM_ETHER | IFM_FDX |
3932                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3933                 }
3934         }
3935
3936         /* Additional supported medias */
3937         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3938         ifmedia_add(&priv->media, IFM_10G_LR |
3939             IFM_ETHER | IFM_FDX |
3940             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3941
3942         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3943         ifmedia_add(&priv->media, IFM_40G_ER4 |
3944             IFM_ETHER | IFM_FDX |
3945             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3946
3947         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3948         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3949             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3950
3951         /* Set autoselect by default */
3952         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3953             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3954         ether_ifattach(ifp, dev_addr);
3955
3956         /* Register for VLAN events */
3957         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3958             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3959         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3960             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3961
3962         /* Link is down by default */
3963         if_link_state_change(ifp, LINK_STATE_DOWN);
3964
3965         mlx5e_enable_async_events(priv);
3966
3967         mlx5e_add_hw_stats(priv);
3968
3969         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3970             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3971             priv->stats.vport.arg);
3972
3973         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3974             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3975             priv->stats.pport.arg);
3976
3977         mlx5e_create_ethtool(priv);
3978
3979         mtx_lock(&priv->async_events_mtx);
3980         mlx5e_update_stats(priv);
3981         mtx_unlock(&priv->async_events_mtx);
3982
3983         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3984             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3985             &priv->clbr_done, 0,
3986             "RX timestamps calibration state");
3987         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3988         mlx5e_reset_calibration_callout(priv);
3989
3990         return (priv);
3991
3992 #ifdef RATELIMIT
3993 err_create_mkey:
3994         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3995 #endif
3996 err_dealloc_transport_domain:
3997         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3998
3999 err_dealloc_pd:
4000         mlx5_core_dealloc_pd(mdev, priv->pdn);
4001
4002 err_unmap_free_uar:
4003         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4004
4005 err_free_wq:
4006         destroy_workqueue(priv->wq);
4007
4008 err_free_sysctl:
4009         sysctl_ctx_free(&priv->sysctl_ctx);
4010         if (priv->sysctl_debug)
4011                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4012         if_free(ifp);
4013
4014 err_free_priv:
4015         mlx5e_priv_mtx_destroy(priv);
4016         free(priv, M_MLX5EN);
4017         return (NULL);
4018 }
4019
4020 static void
4021 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4022 {
4023         struct mlx5e_priv *priv = vpriv;
4024         struct ifnet *ifp = priv->ifp;
4025
4026         /* don't allow more IOCTLs */
4027         priv->gone = 1;
4028
4029         /* XXX wait a bit to allow IOCTL handlers to complete */
4030         pause("W", hz);
4031
4032 #ifdef RATELIMIT
4033         /*
4034          * The kernel can have reference(s) via the m_snd_tag's into
4035          * the ratelimit channels, and these must go away before
4036          * detaching:
4037          */
4038         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4039                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4040                     "to terminate\n");
4041                 pause("W", hz);
4042         }
4043 #endif
4044         /* stop watchdog timer */
4045         callout_drain(&priv->watchdog);
4046
4047         callout_drain(&priv->tstmp_clbr);
4048
4049         if (priv->vlan_attach != NULL)
4050                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4051         if (priv->vlan_detach != NULL)
4052                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4053
4054         /* make sure device gets closed */
4055         PRIV_LOCK(priv);
4056         mlx5e_close_locked(ifp);
4057         PRIV_UNLOCK(priv);
4058
4059         /* wait for all unlimited send tags to go away */
4060         while (priv->channel_refs != 0) {
4061                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4062                     "to terminate\n");
4063                 pause("W", hz);
4064         }
4065
4066         /* unregister device */
4067         ifmedia_removeall(&priv->media);
4068         ether_ifdetach(ifp);
4069         if_free(ifp);
4070
4071 #ifdef RATELIMIT
4072         mlx5e_rl_cleanup(priv);
4073 #endif
4074         /* destroy all remaining sysctl nodes */
4075         sysctl_ctx_free(&priv->stats.vport.ctx);
4076         sysctl_ctx_free(&priv->stats.pport.ctx);
4077         if (priv->sysctl_debug)
4078                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4079         sysctl_ctx_free(&priv->sysctl_ctx);
4080
4081         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4082         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4083         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4084         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4085         mlx5e_disable_async_events(priv);
4086         destroy_workqueue(priv->wq);
4087         mlx5e_priv_mtx_destroy(priv);
4088         free(priv, M_MLX5EN);
4089 }
4090
4091 static void *
4092 mlx5e_get_ifp(void *vpriv)
4093 {
4094         struct mlx5e_priv *priv = vpriv;
4095
4096         return (priv->ifp);
4097 }
4098
4099 static struct mlx5_interface mlx5e_interface = {
4100         .add = mlx5e_create_ifp,
4101         .remove = mlx5e_destroy_ifp,
4102         .event = mlx5e_async_event,
4103         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4104         .get_dev = mlx5e_get_ifp,
4105 };
4106
4107 void
4108 mlx5e_init(void)
4109 {
4110         mlx5_register_interface(&mlx5e_interface);
4111 }
4112
4113 void
4114 mlx5e_cleanup(void)
4115 {
4116         mlx5_unregister_interface(&mlx5e_interface);
4117 }
4118
4119 static void
4120 mlx5e_show_version(void __unused *arg)
4121 {
4122
4123         printf("%s", mlx5e_version);
4124 }
4125 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4126
4127 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4128 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4129
4130 #if (__FreeBSD_version >= 1100000)
4131 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4132 #endif
4133 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4134 MODULE_VERSION(mlx5en, 1);