2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_kern_tls.h"
32 #include <sys/eventhandler.h>
33 #include <sys/sockio.h>
34 #include <machine/atomic.h>
36 #include <net/debugnet.h>
38 #ifndef ETH_DRIVER_VERSION
39 #define ETH_DRIVER_VERSION "3.5.2"
41 #define DRIVER_RELDATE "September 2019"
43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
44 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
48 struct mlx5e_channel_param {
49 struct mlx5e_rq_param rq;
50 struct mlx5e_sq_param sq;
51 struct mlx5e_cq_param rx_cq;
52 struct mlx5e_cq_param tx_cq;
60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
62 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
63 .subtype = IFM_1000_CX_SGMII,
64 .baudrate = IF_Mbps(1000ULL),
66 [MLX5E_1000BASE_KX][MLX5E_KX] = {
67 .subtype = IFM_1000_KX,
68 .baudrate = IF_Mbps(1000ULL),
70 [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
71 .subtype = IFM_10G_CX4,
72 .baudrate = IF_Gbps(10ULL),
74 [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
75 .subtype = IFM_10G_KX4,
76 .baudrate = IF_Gbps(10ULL),
78 [MLX5E_10GBASE_KR][MLX5E_KR] = {
79 .subtype = IFM_10G_KR,
80 .baudrate = IF_Gbps(10ULL),
82 [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
83 .subtype = IFM_20G_KR2,
84 .baudrate = IF_Gbps(20ULL),
86 [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
87 .subtype = IFM_40G_CR4,
88 .baudrate = IF_Gbps(40ULL),
90 [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
91 .subtype = IFM_40G_KR4,
92 .baudrate = IF_Gbps(40ULL),
94 [MLX5E_56GBASE_R4][MLX5E_R] = {
95 .subtype = IFM_56G_R4,
96 .baudrate = IF_Gbps(56ULL),
98 [MLX5E_10GBASE_CR][MLX5E_CR1] = {
99 .subtype = IFM_10G_CR1,
100 .baudrate = IF_Gbps(10ULL),
102 [MLX5E_10GBASE_SR][MLX5E_SR] = {
103 .subtype = IFM_10G_SR,
104 .baudrate = IF_Gbps(10ULL),
106 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
107 .subtype = IFM_10G_ER,
108 .baudrate = IF_Gbps(10ULL),
110 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
111 .subtype = IFM_10G_LR,
112 .baudrate = IF_Gbps(10ULL),
114 [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
115 .subtype = IFM_40G_SR4,
116 .baudrate = IF_Gbps(40ULL),
118 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
119 .subtype = IFM_40G_LR4,
120 .baudrate = IF_Gbps(40ULL),
122 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
123 .subtype = IFM_40G_ER4,
124 .baudrate = IF_Gbps(40ULL),
126 [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
127 .subtype = IFM_100G_CR4,
128 .baudrate = IF_Gbps(100ULL),
130 [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
131 .subtype = IFM_100G_SR4,
132 .baudrate = IF_Gbps(100ULL),
134 [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
135 .subtype = IFM_100G_KR4,
136 .baudrate = IF_Gbps(100ULL),
138 [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
139 .subtype = IFM_100G_LR4,
140 .baudrate = IF_Gbps(100ULL),
142 [MLX5E_100BASE_TX][MLX5E_TX] = {
143 .subtype = IFM_100_TX,
144 .baudrate = IF_Mbps(100ULL),
146 [MLX5E_1000BASE_T][MLX5E_T] = {
147 .subtype = IFM_1000_T,
148 .baudrate = IF_Mbps(1000ULL),
150 [MLX5E_10GBASE_T][MLX5E_T] = {
151 .subtype = IFM_10G_T,
152 .baudrate = IF_Gbps(10ULL),
154 [MLX5E_25GBASE_CR][MLX5E_CR] = {
155 .subtype = IFM_25G_CR,
156 .baudrate = IF_Gbps(25ULL),
158 [MLX5E_25GBASE_KR][MLX5E_KR] = {
159 .subtype = IFM_25G_KR,
160 .baudrate = IF_Gbps(25ULL),
162 [MLX5E_25GBASE_SR][MLX5E_SR] = {
163 .subtype = IFM_25G_SR,
164 .baudrate = IF_Gbps(25ULL),
166 [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
167 .subtype = IFM_50G_CR2,
168 .baudrate = IF_Gbps(50ULL),
170 [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
171 .subtype = IFM_50G_KR2,
172 .baudrate = IF_Gbps(50ULL),
174 [MLX5E_50GBASE_KR4][MLX5E_KR4] = {
175 .subtype = IFM_50G_KR4,
176 .baudrate = IF_Gbps(50ULL),
180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
181 [MLX5E_SGMII_100M][MLX5E_SGMII] = {
182 .subtype = IFM_100_SGMII,
183 .baudrate = IF_Mbps(100),
185 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
186 .subtype = IFM_1000_KX,
187 .baudrate = IF_Mbps(1000),
189 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
190 .subtype = IFM_1000_CX_SGMII,
191 .baudrate = IF_Mbps(1000),
193 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
194 .subtype = IFM_1000_CX,
195 .baudrate = IF_Mbps(1000),
197 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
198 .subtype = IFM_1000_LX,
199 .baudrate = IF_Mbps(1000),
201 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
202 .subtype = IFM_1000_SX,
203 .baudrate = IF_Mbps(1000),
205 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
206 .subtype = IFM_1000_T,
207 .baudrate = IF_Mbps(1000),
209 [MLX5E_5GBASE_R][MLX5E_T] = {
210 .subtype = IFM_5000_T,
211 .baudrate = IF_Mbps(5000),
213 [MLX5E_5GBASE_R][MLX5E_KR] = {
214 .subtype = IFM_5000_KR,
215 .baudrate = IF_Mbps(5000),
217 [MLX5E_5GBASE_R][MLX5E_KR1] = {
218 .subtype = IFM_5000_KR1,
219 .baudrate = IF_Mbps(5000),
221 [MLX5E_5GBASE_R][MLX5E_KR_S] = {
222 .subtype = IFM_5000_KR_S,
223 .baudrate = IF_Mbps(5000),
225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
226 .subtype = IFM_10G_ER,
227 .baudrate = IF_Gbps(10ULL),
229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
230 .subtype = IFM_10G_KR,
231 .baudrate = IF_Gbps(10ULL),
233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
234 .subtype = IFM_10G_LR,
235 .baudrate = IF_Gbps(10ULL),
237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
238 .subtype = IFM_10G_SR,
239 .baudrate = IF_Gbps(10ULL),
241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
242 .subtype = IFM_10G_T,
243 .baudrate = IF_Gbps(10ULL),
245 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
246 .subtype = IFM_10G_AOC,
247 .baudrate = IF_Gbps(10ULL),
249 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
250 .subtype = IFM_10G_CR1,
251 .baudrate = IF_Gbps(10ULL),
253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
254 .subtype = IFM_40G_CR4,
255 .baudrate = IF_Gbps(40ULL),
257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
258 .subtype = IFM_40G_KR4,
259 .baudrate = IF_Gbps(40ULL),
261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
262 .subtype = IFM_40G_LR4,
263 .baudrate = IF_Gbps(40ULL),
265 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
266 .subtype = IFM_40G_SR4,
267 .baudrate = IF_Gbps(40ULL),
269 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
270 .subtype = IFM_40G_ER4,
271 .baudrate = IF_Gbps(40ULL),
274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
275 .subtype = IFM_25G_CR,
276 .baudrate = IF_Gbps(25ULL),
278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
279 .subtype = IFM_25G_KR,
280 .baudrate = IF_Gbps(25ULL),
282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
283 .subtype = IFM_25G_SR,
284 .baudrate = IF_Gbps(25ULL),
286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
287 .subtype = IFM_25G_ACC,
288 .baudrate = IF_Gbps(25ULL),
290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
291 .subtype = IFM_25G_AOC,
292 .baudrate = IF_Gbps(25ULL),
294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
295 .subtype = IFM_25G_CR1,
296 .baudrate = IF_Gbps(25ULL),
298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
299 .subtype = IFM_25G_CR_S,
300 .baudrate = IF_Gbps(25ULL),
302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
303 .subtype = IFM_5000_KR1,
304 .baudrate = IF_Gbps(25ULL),
306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
307 .subtype = IFM_25G_KR_S,
308 .baudrate = IF_Gbps(25ULL),
310 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
311 .subtype = IFM_25G_LR,
312 .baudrate = IF_Gbps(25ULL),
314 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
315 .subtype = IFM_25G_T,
316 .baudrate = IF_Gbps(25ULL),
318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
319 .subtype = IFM_50G_CR2,
320 .baudrate = IF_Gbps(50ULL),
322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
323 .subtype = IFM_50G_KR2,
324 .baudrate = IF_Gbps(50ULL),
326 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = {
327 .subtype = IFM_50G_KR4,
328 .baudrate = IF_Gbps(50ULL),
330 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
331 .subtype = IFM_50G_SR2,
332 .baudrate = IF_Gbps(50ULL),
334 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
335 .subtype = IFM_50G_LR2,
336 .baudrate = IF_Gbps(50ULL),
338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
339 .subtype = IFM_50G_LR,
340 .baudrate = IF_Gbps(50ULL),
342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
343 .subtype = IFM_50G_SR,
344 .baudrate = IF_Gbps(50ULL),
346 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
347 .subtype = IFM_50G_CP,
348 .baudrate = IF_Gbps(50ULL),
350 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
351 .subtype = IFM_50G_FR,
352 .baudrate = IF_Gbps(50ULL),
354 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
355 .subtype = IFM_50G_KR_PAM4,
356 .baudrate = IF_Gbps(50ULL),
358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
359 .subtype = IFM_100G_CR4,
360 .baudrate = IF_Gbps(100ULL),
362 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
363 .subtype = IFM_100G_KR4,
364 .baudrate = IF_Gbps(100ULL),
366 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
367 .subtype = IFM_100G_LR4,
368 .baudrate = IF_Gbps(100ULL),
370 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
371 .subtype = IFM_100G_SR4,
372 .baudrate = IF_Gbps(100ULL),
374 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
375 .subtype = IFM_100G_SR2,
376 .baudrate = IF_Gbps(100ULL),
378 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
379 .subtype = IFM_100G_CP2,
380 .baudrate = IF_Gbps(100ULL),
382 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
383 .subtype = IFM_100G_KR2_PAM4,
384 .baudrate = IF_Gbps(100ULL),
386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
387 .subtype = IFM_200G_DR4,
388 .baudrate = IF_Gbps(200ULL),
390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
391 .subtype = IFM_200G_LR4,
392 .baudrate = IF_Gbps(200ULL),
394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
395 .subtype = IFM_200G_SR4,
396 .baudrate = IF_Gbps(200ULL),
398 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
399 .subtype = IFM_200G_FR4,
400 .baudrate = IF_Gbps(200ULL),
402 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
403 .subtype = IFM_200G_CR4_PAM4,
404 .baudrate = IF_Gbps(200ULL),
406 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
407 .subtype = IFM_200G_KR4_PAM4,
408 .baudrate = IF_Gbps(200ULL),
412 DEBUGNET_DEFINE(mlx5_en);
414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
417 mlx5e_update_carrier(struct mlx5e_priv *priv)
419 struct mlx5_core_dev *mdev = priv->mdev;
420 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
427 struct media media_entry = {};
429 port_state = mlx5_query_vport_state(mdev,
430 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
432 if (port_state == VPORT_STATE_UP) {
433 priv->media_status_last |= IFM_ACTIVE;
435 priv->media_status_last &= ~IFM_ACTIVE;
436 priv->media_active_last = IFM_ETHER;
437 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
441 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
444 priv->media_active_last = IFM_ETHER;
445 priv->ifp->if_baudrate = 1;
446 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
451 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
452 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
455 i = ilog2(eth_proto_oper);
457 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
458 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
459 mlx5e_mode_table[i][j];
460 if (media_entry.baudrate != 0)
464 if (media_entry.subtype == 0) {
465 mlx5_en_err(priv->ifp,
466 "Could not find operational media subtype\n");
470 switch (media_entry.subtype) {
472 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
474 mlx5_en_err(priv->ifp,
475 "query port pddr failed: %d\n", error);
477 if (error != 0 || is_er_type == 0)
478 media_entry.subtype = IFM_10G_LR;
481 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
483 mlx5_en_err(priv->ifp,
484 "query port pddr failed: %d\n", error);
486 if (error == 0 && is_er_type != 0)
487 media_entry.subtype = IFM_40G_ER4;
490 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
491 priv->ifp->if_baudrate = media_entry.baudrate;
493 if_link_state_change(priv->ifp, LINK_STATE_UP);
497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
499 struct mlx5e_priv *priv = dev->if_softc;
501 ifmr->ifm_status = priv->media_status_last;
502 ifmr->ifm_active = priv->media_active_last |
503 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
504 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
509 mlx5e_find_link_mode(u32 subtype, bool ext)
515 struct media media_entry = {};
519 subtype = IFM_10G_ER;
522 subtype = IFM_40G_LR4;
526 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
527 MLX5E_LINK_SPEEDS_NUMBER;
529 for (i = 0; i != speeds_num; i++) {
530 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
531 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
532 mlx5e_mode_table[i][j];
533 if (media_entry.baudrate == 0)
535 if (media_entry.subtype == subtype) {
536 link_mode |= MLX5E_PROT_MASK(i);
545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
547 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
548 priv->params.rx_pauseframe_control,
549 priv->params.tx_pauseframe_control,
550 priv->params.rx_priority_flow_control,
551 priv->params.tx_priority_flow_control));
555 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
559 if (priv->gone != 0) {
561 } else if (priv->params.rx_pauseframe_control ||
562 priv->params.tx_pauseframe_control) {
563 mlx5_en_err(priv->ifp,
564 "Global pauseframes must be disabled before enabling PFC.\n");
567 error = mlx5e_set_port_pause_and_pfc(priv);
573 mlx5e_media_change(struct ifnet *dev)
575 struct mlx5e_priv *priv = dev->if_softc;
576 struct mlx5_core_dev *mdev = priv->mdev;
579 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
585 locked = PRIV_LOCKED(priv);
589 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
594 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
597 mlx5_en_err(dev, "Query port media capability failed\n");
601 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
602 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
604 /* query supported capabilities */
605 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
606 eth_proto_capability);
608 /* check for autoselect */
609 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
610 link_mode = eth_proto_cap;
611 if (link_mode == 0) {
612 mlx5_en_err(dev, "Port media capability is zero\n");
617 link_mode = link_mode & eth_proto_cap;
618 if (link_mode == 0) {
619 mlx5_en_err(dev, "Not supported link mode requested\n");
624 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
625 /* check if PFC is enabled */
626 if (priv->params.rx_priority_flow_control ||
627 priv->params.tx_priority_flow_control) {
628 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
633 /* update pauseframe control bits */
634 priv->params.rx_pauseframe_control =
635 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
636 priv->params.tx_pauseframe_control =
637 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
639 /* check if device is opened */
640 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
642 /* reconfigure the hardware */
643 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
644 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
645 error = -mlx5e_set_port_pause_and_pfc(priv);
647 mlx5_set_port_status(mdev, MLX5_PORT_UP);
656 mlx5e_update_carrier_work(struct work_struct *work)
658 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
659 update_carrier_work);
662 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
663 mlx5e_update_carrier(priv);
667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
668 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
671 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
676 struct mlx5_core_dev *mdev = priv->mdev;
677 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
678 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
683 /* allocate firmware request structures */
684 in = mlx5_vzalloc(sz);
685 out = mlx5_vzalloc(sz);
686 if (in == NULL || out == NULL)
689 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
690 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
694 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
695 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
697 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
698 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
702 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
704 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
705 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
709 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
712 /* free firmware request structures */
718 * This function reads the physical port counters from the firmware
719 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
720 * macros. The output is converted from big-endian 64-bit values into
721 * host endian ones and stored in the "priv->stats.pport" structure.
724 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
726 struct mlx5_core_dev *mdev = priv->mdev;
727 struct mlx5e_pport_stats *s = &priv->stats.pport;
728 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
732 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
737 /* allocate firmware request structures */
738 in = mlx5_vzalloc(sz);
739 out = mlx5_vzalloc(sz);
740 if (in == NULL || out == NULL)
744 * Get pointer to the 64-bit counter set which is located at a
745 * fixed offset in the output firmware request structure:
747 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
749 MLX5_SET(ppcnt_reg, in, local_port, 1);
751 /* read IEEE802_3 counter group using predefined counter layout */
752 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
754 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
755 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
756 s->arg[y] = be64toh(ptr[x]);
758 /* read RFC2819 counter group using predefined counter layout */
759 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
760 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
761 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
762 s->arg[y] = be64toh(ptr[x]);
764 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
765 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
766 s_debug->arg[y] = be64toh(ptr[x]);
768 /* read RFC2863 counter group using predefined counter layout */
769 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
771 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
772 s_debug->arg[y] = be64toh(ptr[x]);
774 /* read physical layer stats counter group using predefined counter layout */
775 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
776 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
777 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
778 s_debug->arg[y] = be64toh(ptr[x]);
780 /* read Extended Ethernet counter group using predefined counter layout */
781 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
782 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
783 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
784 s_debug->arg[y] = be64toh(ptr[x]);
786 /* read Extended Statistical Group */
787 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
788 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
789 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
790 /* read Extended Statistical counter group using predefined counter layout */
791 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
792 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
794 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
795 s_debug->arg[y] = be64toh(ptr[x]);
798 /* read PCIE counters */
799 mlx5e_update_pcie_counters(priv);
801 /* read per-priority counters */
802 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
804 /* iterate all the priorities */
805 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
806 MLX5_SET(ppcnt_reg, in, prio_tc, z);
807 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
809 /* read per priority stats counter group using predefined counter layout */
810 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
811 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
812 s->arg[y] = be64toh(ptr[x]);
816 /* free firmware request structures */
822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
824 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
825 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
827 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
830 MLX5_SET(query_vnic_env_in, in, opcode,
831 MLX5_CMD_OP_QUERY_VNIC_ENV);
832 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
833 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
835 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
838 priv->stats.vport.rx_steer_missed_packets =
839 MLX5_GET64(query_vnic_env_out, out,
840 vport_env.nic_receive_steering_discard);
844 * This function is called regularly to collect all statistics
845 * counters from the firmware. The values can be viewed through the
846 * sysctl interface. Execution is serialized using the priv's global
847 * configuration lock.
850 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
852 struct mlx5_core_dev *mdev = priv->mdev;
853 struct mlx5e_vport_stats *s = &priv->stats.vport;
854 struct mlx5e_sq_stats *sq_stats;
855 #if (__FreeBSD_version < 1100000)
856 struct ifnet *ifp = priv->ifp;
859 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
861 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
864 u64 tx_queue_dropped = 0;
865 u64 tx_defragged = 0;
866 u64 tx_offload_none = 0;
869 u64 sw_lro_queued = 0;
870 u64 sw_lro_flushed = 0;
871 u64 rx_csum_none = 0;
875 u32 rx_out_of_buffer = 0;
880 out = mlx5_vzalloc(outlen);
884 /* Collect firts the SW counters and then HW for consistency */
885 for (i = 0; i < priv->params.num_channels; i++) {
886 struct mlx5e_channel *pch = priv->channel + i;
887 struct mlx5e_rq *rq = &pch->rq;
888 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
890 /* collect stats from LRO */
891 rq_stats->sw_lro_queued = rq->lro.lro_queued;
892 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
893 sw_lro_queued += rq_stats->sw_lro_queued;
894 sw_lro_flushed += rq_stats->sw_lro_flushed;
895 lro_packets += rq_stats->lro_packets;
896 lro_bytes += rq_stats->lro_bytes;
897 rx_csum_none += rq_stats->csum_none;
898 rx_wqe_err += rq_stats->wqe_err;
899 rx_packets += rq_stats->packets;
900 rx_bytes += rq_stats->bytes;
902 for (j = 0; j < priv->num_tc; j++) {
903 sq_stats = &pch->sq[j].stats;
905 tso_packets += sq_stats->tso_packets;
906 tso_bytes += sq_stats->tso_bytes;
907 tx_queue_dropped += sq_stats->dropped;
908 tx_queue_dropped += sq_stats->enobuf;
909 tx_defragged += sq_stats->defragged;
910 tx_offload_none += sq_stats->csum_offload_none;
914 /* update counters */
915 s->tso_packets = tso_packets;
916 s->tso_bytes = tso_bytes;
917 s->tx_queue_dropped = tx_queue_dropped;
918 s->tx_defragged = tx_defragged;
919 s->lro_packets = lro_packets;
920 s->lro_bytes = lro_bytes;
921 s->sw_lro_queued = sw_lro_queued;
922 s->sw_lro_flushed = sw_lro_flushed;
923 s->rx_csum_none = rx_csum_none;
924 s->rx_wqe_err = rx_wqe_err;
925 s->rx_packets = rx_packets;
926 s->rx_bytes = rx_bytes;
928 mlx5e_grp_vnic_env_update_stats(priv);
931 memset(in, 0, sizeof(in));
933 MLX5_SET(query_vport_counter_in, in, opcode,
934 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
935 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
936 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
938 memset(out, 0, outlen);
940 /* get number of out-of-buffer drops first */
941 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
942 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
943 &rx_out_of_buffer) == 0) {
944 s->rx_out_of_buffer = rx_out_of_buffer;
947 /* get port statistics */
948 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
949 #define MLX5_GET_CTR(out, x) \
950 MLX5_GET64(query_vport_counter_out, out, x)
952 s->rx_error_packets =
953 MLX5_GET_CTR(out, received_errors.packets);
955 MLX5_GET_CTR(out, received_errors.octets);
956 s->tx_error_packets =
957 MLX5_GET_CTR(out, transmit_errors.packets);
959 MLX5_GET_CTR(out, transmit_errors.octets);
961 s->rx_unicast_packets =
962 MLX5_GET_CTR(out, received_eth_unicast.packets);
963 s->rx_unicast_bytes =
964 MLX5_GET_CTR(out, received_eth_unicast.octets);
965 s->tx_unicast_packets =
966 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
967 s->tx_unicast_bytes =
968 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
970 s->rx_multicast_packets =
971 MLX5_GET_CTR(out, received_eth_multicast.packets);
972 s->rx_multicast_bytes =
973 MLX5_GET_CTR(out, received_eth_multicast.octets);
974 s->tx_multicast_packets =
975 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
976 s->tx_multicast_bytes =
977 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
979 s->rx_broadcast_packets =
980 MLX5_GET_CTR(out, received_eth_broadcast.packets);
981 s->rx_broadcast_bytes =
982 MLX5_GET_CTR(out, received_eth_broadcast.octets);
983 s->tx_broadcast_packets =
984 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
985 s->tx_broadcast_bytes =
986 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
988 s->tx_packets = s->tx_unicast_packets +
989 s->tx_multicast_packets + s->tx_broadcast_packets;
990 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
991 s->tx_broadcast_bytes;
993 /* Update calculated offload counters */
994 s->tx_csum_offload = s->tx_packets - tx_offload_none;
995 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
998 /* Get physical port counters */
999 mlx5e_update_pport_counters(priv);
1001 s->tx_jumbo_packets =
1002 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1003 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1004 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1005 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1007 #if (__FreeBSD_version < 1100000)
1008 /* no get_counters interface in fbsd 10 */
1009 ifp->if_ipackets = s->rx_packets;
1010 ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1011 priv->stats.pport.out_of_range_len +
1012 priv->stats.pport.too_long_errors +
1013 priv->stats.pport.check_seq_err +
1014 priv->stats.pport.alignment_err;
1015 ifp->if_iqdrops = s->rx_out_of_buffer;
1016 ifp->if_opackets = s->tx_packets;
1017 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1018 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1019 ifp->if_ibytes = s->rx_bytes;
1020 ifp->if_obytes = s->tx_bytes;
1021 ifp->if_collisions =
1022 priv->stats.pport.collisions;
1028 /* Update diagnostics, if any */
1029 if (priv->params_ethtool.diag_pci_enable ||
1030 priv->params_ethtool.diag_general_enable) {
1031 error = mlx5_core_get_diagnostics_full(mdev,
1032 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1033 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1035 mlx5_en_err(priv->ifp,
1036 "Failed reading diagnostics: %d\n", error);
1039 /* Update FEC, if any */
1040 error = mlx5e_fec_update(priv);
1041 if (error != 0 && error != EOPNOTSUPP) {
1042 mlx5_en_err(priv->ifp,
1043 "Updating FEC failed: %d\n", error);
1046 /* Update temperature, if any */
1047 if (priv->params_ethtool.hw_num_temp != 0) {
1048 error = mlx5e_hw_temperature_update(priv);
1049 if (error != 0 && error != EOPNOTSUPP) {
1050 mlx5_en_err(priv->ifp,
1051 "Updating temperature failed: %d\n", error);
1057 mlx5e_update_stats_work(struct work_struct *work)
1059 struct mlx5e_priv *priv;
1061 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1063 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1064 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1065 mlx5e_update_stats_locked(priv);
1070 mlx5e_update_stats(void *arg)
1072 struct mlx5e_priv *priv = arg;
1074 queue_work(priv->wq, &priv->update_stats_work);
1076 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1080 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1081 enum mlx5_dev_event event)
1084 case MLX5_DEV_EVENT_PORT_UP:
1085 case MLX5_DEV_EVENT_PORT_DOWN:
1086 queue_work(priv->wq, &priv->update_carrier_work);
1095 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1096 enum mlx5_dev_event event, unsigned long param)
1098 struct mlx5e_priv *priv = vpriv;
1100 mtx_lock(&priv->async_events_mtx);
1101 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1102 mlx5e_async_event_sub(priv, event);
1103 mtx_unlock(&priv->async_events_mtx);
1107 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1109 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1113 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1115 mtx_lock(&priv->async_events_mtx);
1116 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1117 mtx_unlock(&priv->async_events_mtx);
1120 static void mlx5e_calibration_callout(void *arg);
1121 static int mlx5e_calibration_duration = 20;
1122 static int mlx5e_fast_calibration = 1;
1123 static int mlx5e_normal_calibration = 30;
1125 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1126 "MLX5 timestamp calibration parameteres");
1128 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1129 &mlx5e_calibration_duration, 0,
1130 "Duration of initial calibration");
1131 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1132 &mlx5e_fast_calibration, 0,
1133 "Recalibration interval during initial calibration");
1134 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1135 &mlx5e_normal_calibration, 0,
1136 "Recalibration interval during normal operations");
1139 * Ignites the calibration process.
1142 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1145 if (priv->clbr_done == 0)
1146 mlx5e_calibration_callout(priv);
1148 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1149 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1150 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1155 mlx5e_timespec2usec(const struct timespec *ts)
1158 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1162 mlx5e_hw_clock(struct mlx5e_priv *priv)
1164 struct mlx5_init_seg *iseg;
1165 uint32_t hw_h, hw_h1, hw_l;
1167 iseg = priv->mdev->iseg;
1169 hw_h = ioread32be(&iseg->internal_timer_h);
1170 hw_l = ioread32be(&iseg->internal_timer_l);
1171 hw_h1 = ioread32be(&iseg->internal_timer_h);
1172 } while (hw_h1 != hw_h);
1173 return (((uint64_t)hw_h << 32) | hw_l);
1177 * The calibration callout, it runs either in the context of the
1178 * thread which enables calibration, or in callout. It takes the
1179 * snapshot of system and adapter clocks, then advances the pointers to
1180 * the calibration point to allow rx path to read the consistent data
1184 mlx5e_calibration_callout(void *arg)
1186 struct mlx5e_priv *priv;
1187 struct mlx5e_clbr_point *next, *curr;
1192 curr = &priv->clbr_points[priv->clbr_curr];
1193 clbr_curr_next = priv->clbr_curr + 1;
1194 if (clbr_curr_next >= nitems(priv->clbr_points))
1196 next = &priv->clbr_points[clbr_curr_next];
1198 next->base_prev = curr->base_curr;
1199 next->clbr_hw_prev = curr->clbr_hw_curr;
1201 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1202 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1204 if (priv->clbr_done != 0) {
1205 mlx5_en_err(priv->ifp,
1206 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1207 next->clbr_hw_curr, curr->clbr_hw_prev);
1208 priv->clbr_done = 0;
1210 atomic_store_rel_int(&curr->clbr_gen, 0);
1215 next->base_curr = mlx5e_timespec2usec(&ts);
1218 atomic_thread_fence_rel();
1219 priv->clbr_curr = clbr_curr_next;
1220 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1222 if (priv->clbr_done < mlx5e_calibration_duration)
1224 mlx5e_reset_calibration_callout(priv);
1227 static const char *mlx5e_rq_stats_desc[] = {
1228 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1232 mlx5e_create_rq(struct mlx5e_channel *c,
1233 struct mlx5e_rq_param *param,
1234 struct mlx5e_rq *rq)
1236 struct mlx5e_priv *priv = c->priv;
1237 struct mlx5_core_dev *mdev = priv->mdev;
1239 void *rqc = param->rqc;
1240 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1246 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1250 /* Create DMA descriptor TAG */
1251 if ((err = -bus_dma_tag_create(
1252 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1253 1, /* any alignment */
1254 0, /* no boundary */
1255 BUS_SPACE_MAXADDR, /* lowaddr */
1256 BUS_SPACE_MAXADDR, /* highaddr */
1257 NULL, NULL, /* filter, filterarg */
1258 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1259 nsegs, /* nsegments */
1260 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1262 NULL, NULL, /* lockfunc, lockfuncarg */
1266 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1269 goto err_free_dma_tag;
1271 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1273 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1275 goto err_rq_wq_destroy;
1277 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1279 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1281 goto err_rq_wq_destroy;
1283 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1284 for (i = 0; i != wq_sz; i++) {
1285 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1288 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1291 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1292 goto err_rq_mbuf_free;
1295 /* set value for constant fields */
1296 for (j = 0; j < rq->nsegs; j++)
1297 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1300 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1301 if (priv->params.rx_cq_moderation_mode < 2) {
1302 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1304 void *cqc = container_of(param,
1305 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1307 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1308 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1309 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1311 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1312 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1315 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1320 rq->ifp = priv->ifp;
1324 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1325 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1326 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1331 free(rq->mbuf, M_MLX5EN);
1332 tcp_lro_free(&rq->lro);
1334 mlx5_wq_destroy(&rq->wq_ctrl);
1336 bus_dma_tag_destroy(rq->dma_tag);
1342 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1347 /* destroy all sysctl nodes */
1348 sysctl_ctx_free(&rq->stats.ctx);
1350 /* free leftover LRO packets, if any */
1351 tcp_lro_free(&rq->lro);
1353 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1354 for (i = 0; i != wq_sz; i++) {
1355 if (rq->mbuf[i].mbuf != NULL) {
1356 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1357 m_freem(rq->mbuf[i].mbuf);
1359 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1361 free(rq->mbuf, M_MLX5EN);
1362 mlx5_wq_destroy(&rq->wq_ctrl);
1363 bus_dma_tag_destroy(rq->dma_tag);
1367 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1369 struct mlx5e_channel *c = rq->channel;
1370 struct mlx5e_priv *priv = c->priv;
1371 struct mlx5_core_dev *mdev = priv->mdev;
1379 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1380 sizeof(u64) * rq->wq_ctrl.buf.npages;
1381 in = mlx5_vzalloc(inlen);
1385 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1386 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1388 memcpy(rqc, param->rqc, sizeof(param->rqc));
1390 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1391 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1392 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1393 if (priv->counter_set_id >= 0)
1394 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1395 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1397 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1399 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1400 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1402 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1410 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1412 struct mlx5e_channel *c = rq->channel;
1413 struct mlx5e_priv *priv = c->priv;
1414 struct mlx5_core_dev *mdev = priv->mdev;
1421 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1422 in = mlx5_vzalloc(inlen);
1426 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1428 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1429 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1430 MLX5_SET(rqc, rqc, state, next_state);
1432 err = mlx5_core_modify_rq(mdev, in, inlen);
1440 mlx5e_disable_rq(struct mlx5e_rq *rq)
1442 struct mlx5e_channel *c = rq->channel;
1443 struct mlx5e_priv *priv = c->priv;
1444 struct mlx5_core_dev *mdev = priv->mdev;
1446 mlx5_core_destroy_rq(mdev, rq->rqn);
1450 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1452 struct mlx5e_channel *c = rq->channel;
1453 struct mlx5e_priv *priv = c->priv;
1454 struct mlx5_wq_ll *wq = &rq->wq;
1457 for (i = 0; i < 1000; i++) {
1458 if (wq->cur_sz >= priv->params.min_rx_wqes)
1463 return (-ETIMEDOUT);
1467 mlx5e_open_rq(struct mlx5e_channel *c,
1468 struct mlx5e_rq_param *param,
1469 struct mlx5e_rq *rq)
1473 err = mlx5e_create_rq(c, param, rq);
1477 err = mlx5e_enable_rq(rq, param);
1479 goto err_destroy_rq;
1481 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1483 goto err_disable_rq;
1490 mlx5e_disable_rq(rq);
1492 mlx5e_destroy_rq(rq);
1498 mlx5e_close_rq(struct mlx5e_rq *rq)
1502 callout_stop(&rq->watchdog);
1503 mtx_unlock(&rq->mtx);
1505 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1509 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1512 mlx5e_disable_rq(rq);
1513 mlx5e_close_cq(&rq->cq);
1514 cancel_work_sync(&rq->dim.work);
1515 mlx5e_destroy_rq(rq);
1519 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1521 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1524 for (x = 0; x != wq_sz; x++) {
1525 if (unlikely(sq->mbuf[x].p_refcount != NULL)) {
1526 atomic_add_int(sq->mbuf[x].p_refcount, -1);
1527 sq->mbuf[x].p_refcount = NULL;
1529 if (sq->mbuf[x].mbuf != NULL) {
1530 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1531 m_freem(sq->mbuf[x].mbuf);
1533 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1535 free(sq->mbuf, M_MLX5EN);
1539 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1541 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1545 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1547 /* Create DMA descriptor MAPs */
1548 for (x = 0; x != wq_sz; x++) {
1549 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1552 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1553 free(sq->mbuf, M_MLX5EN);
1560 static const char *mlx5e_sq_stats_desc[] = {
1561 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1565 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1567 sq->max_inline = sq->priv->params.tx_max_inline;
1568 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1571 * Check if trust state is DSCP or if inline mode is NONE which
1572 * indicates CX-5 or newer hardware.
1574 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1575 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1576 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1577 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1579 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1581 sq->min_insert_caps = 0;
1586 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1590 for (i = 0; i != priv->num_tc; i++) {
1591 mtx_lock(&c->sq[i].lock);
1592 mlx5e_update_sq_inline(&c->sq[i]);
1593 mtx_unlock(&c->sq[i].lock);
1598 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1602 /* check if channels are closed */
1603 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1606 for (i = 0; i < priv->params.num_channels; i++)
1607 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1611 mlx5e_create_sq(struct mlx5e_channel *c,
1613 struct mlx5e_sq_param *param,
1614 struct mlx5e_sq *sq)
1616 struct mlx5e_priv *priv = c->priv;
1617 struct mlx5_core_dev *mdev = priv->mdev;
1619 void *sqc = param->sqc;
1620 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1623 /* Create DMA descriptor TAG */
1624 if ((err = -bus_dma_tag_create(
1625 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1626 1, /* any alignment */
1627 0, /* no boundary */
1628 BUS_SPACE_MAXADDR, /* lowaddr */
1629 BUS_SPACE_MAXADDR, /* highaddr */
1630 NULL, NULL, /* filter, filterarg */
1631 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1632 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1633 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1635 NULL, NULL, /* lockfunc, lockfuncarg */
1639 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1641 goto err_free_dma_tag;
1643 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1646 goto err_unmap_free_uar;
1648 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1649 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1651 err = mlx5e_alloc_sq_db(sq);
1653 goto err_sq_wq_destroy;
1655 sq->mkey_be = cpu_to_be32(priv->mr.key);
1656 sq->ifp = priv->ifp;
1660 mlx5e_update_sq_inline(sq);
1662 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1663 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1664 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1670 mlx5_wq_destroy(&sq->wq_ctrl);
1673 mlx5_unmap_free_uar(mdev, &sq->uar);
1676 bus_dma_tag_destroy(sq->dma_tag);
1682 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1684 /* destroy all sysctl nodes */
1685 sysctl_ctx_free(&sq->stats.ctx);
1687 mlx5e_free_sq_db(sq);
1688 mlx5_wq_destroy(&sq->wq_ctrl);
1689 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1690 bus_dma_tag_destroy(sq->dma_tag);
1694 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1703 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1704 sizeof(u64) * sq->wq_ctrl.buf.npages;
1705 in = mlx5_vzalloc(inlen);
1709 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1710 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1712 memcpy(sqc, param->sqc, sizeof(param->sqc));
1714 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1715 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1716 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1717 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1718 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1720 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1721 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1722 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1724 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1726 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1727 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1729 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1737 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1744 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1745 in = mlx5_vzalloc(inlen);
1749 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1751 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1752 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1753 MLX5_SET(sqc, sqc, state, next_state);
1755 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1763 mlx5e_disable_sq(struct mlx5e_sq *sq)
1766 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1770 mlx5e_open_sq(struct mlx5e_channel *c,
1772 struct mlx5e_sq_param *param,
1773 struct mlx5e_sq *sq)
1777 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1779 /* ensure the TX completion event factor is not zero */
1780 if (sq->cev_factor == 0)
1783 err = mlx5e_create_sq(c, tc, param, sq);
1787 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1789 goto err_destroy_sq;
1791 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1793 goto err_disable_sq;
1795 WRITE_ONCE(sq->running, 1);
1800 mlx5e_disable_sq(sq);
1802 mlx5e_destroy_sq(sq);
1808 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1810 /* fill up remainder with NOPs */
1811 while (sq->cev_counter != 0) {
1812 while (!mlx5e_sq_has_room_for(sq, 1)) {
1813 if (can_sleep != 0) {
1814 mtx_unlock(&sq->lock);
1816 mtx_lock(&sq->lock);
1821 /* send a single NOP */
1822 mlx5e_send_nop(sq, 1);
1823 atomic_thread_fence_rel();
1826 /* Check if we need to write the doorbell */
1827 if (likely(sq->doorbell.d64 != 0)) {
1828 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1829 sq->doorbell.d64 = 0;
1834 mlx5e_sq_cev_timeout(void *arg)
1836 struct mlx5e_sq *sq = arg;
1838 mtx_assert(&sq->lock, MA_OWNED);
1840 /* check next state */
1841 switch (sq->cev_next_state) {
1842 case MLX5E_CEV_STATE_SEND_NOPS:
1843 /* fill TX ring with NOPs, if any */
1844 mlx5e_sq_send_nops_locked(sq, 0);
1846 /* check if completed */
1847 if (sq->cev_counter == 0) {
1848 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1853 /* send NOPs on next timeout */
1854 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1859 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1863 mlx5e_drain_sq(struct mlx5e_sq *sq)
1866 struct mlx5_core_dev *mdev= sq->priv->mdev;
1869 * Check if already stopped.
1871 * NOTE: Serialization of this function is managed by the
1872 * caller ensuring the priv's state lock is locked or in case
1873 * of rate limit support, a single thread manages drain and
1874 * resume of SQs. The "running" variable can therefore safely
1875 * be read without any locks.
1877 if (READ_ONCE(sq->running) == 0)
1880 /* don't put more packets into the SQ */
1881 WRITE_ONCE(sq->running, 0);
1883 /* serialize access to DMA rings */
1884 mtx_lock(&sq->lock);
1886 /* teardown event factor timer, if any */
1887 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1888 callout_stop(&sq->cev_callout);
1890 /* send dummy NOPs in order to flush the transmit ring */
1891 mlx5e_sq_send_nops_locked(sq, 1);
1892 mtx_unlock(&sq->lock);
1894 /* wait till SQ is empty or link is down */
1895 mtx_lock(&sq->lock);
1896 while (sq->cc != sq->pc &&
1897 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1898 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1899 mtx_unlock(&sq->lock);
1901 sq->cq.mcq.comp(&sq->cq.mcq);
1902 mtx_lock(&sq->lock);
1904 mtx_unlock(&sq->lock);
1906 /* error out remaining requests */
1907 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1909 mlx5_en_err(sq->ifp,
1910 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1913 /* wait till SQ is empty */
1914 mtx_lock(&sq->lock);
1915 while (sq->cc != sq->pc &&
1916 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1917 mtx_unlock(&sq->lock);
1919 sq->cq.mcq.comp(&sq->cq.mcq);
1920 mtx_lock(&sq->lock);
1922 mtx_unlock(&sq->lock);
1926 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1930 mlx5e_disable_sq(sq);
1931 mlx5e_destroy_sq(sq);
1935 mlx5e_create_cq(struct mlx5e_priv *priv,
1936 struct mlx5e_cq_param *param,
1937 struct mlx5e_cq *cq,
1938 mlx5e_cq_comp_t *comp,
1941 struct mlx5_core_dev *mdev = priv->mdev;
1942 struct mlx5_core_cq *mcq = &cq->mcq;
1948 param->wq.buf_numa_node = 0;
1949 param->wq.db_numa_node = 0;
1951 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1955 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1961 mcq->set_ci_db = cq->wq_ctrl.db.db;
1962 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1963 *mcq->set_ci_db = 0;
1965 mcq->vector = eq_ix;
1967 mcq->event = mlx5e_cq_error_event;
1969 mcq->uar = &priv->cq_uar;
1971 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1972 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1983 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1985 mlx5_wq_destroy(&cq->wq_ctrl);
1989 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1991 struct mlx5_core_cq *mcq = &cq->mcq;
1999 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2000 sizeof(u64) * cq->wq_ctrl.buf.npages;
2001 in = mlx5_vzalloc(inlen);
2005 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2007 memcpy(cqc, param->cqc, sizeof(param->cqc));
2009 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2010 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2012 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2014 MLX5_SET(cqc, cqc, c_eqn, eqn);
2015 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2016 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2018 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2020 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2027 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2033 mlx5e_disable_cq(struct mlx5e_cq *cq)
2036 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2040 mlx5e_open_cq(struct mlx5e_priv *priv,
2041 struct mlx5e_cq_param *param,
2042 struct mlx5e_cq *cq,
2043 mlx5e_cq_comp_t *comp,
2048 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2052 err = mlx5e_enable_cq(cq, param, eq_ix);
2054 goto err_destroy_cq;
2059 mlx5e_destroy_cq(cq);
2065 mlx5e_close_cq(struct mlx5e_cq *cq)
2067 mlx5e_disable_cq(cq);
2068 mlx5e_destroy_cq(cq);
2072 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2073 struct mlx5e_channel_param *cparam)
2078 for (tc = 0; tc < c->priv->num_tc; tc++) {
2079 /* open completion queue */
2080 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2081 &mlx5e_tx_cq_comp, c->ix);
2083 goto err_close_tx_cqs;
2088 for (tc--; tc >= 0; tc--)
2089 mlx5e_close_cq(&c->sq[tc].cq);
2095 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2099 for (tc = 0; tc < c->priv->num_tc; tc++)
2100 mlx5e_close_cq(&c->sq[tc].cq);
2104 mlx5e_open_sqs(struct mlx5e_channel *c,
2105 struct mlx5e_channel_param *cparam)
2110 for (tc = 0; tc < c->priv->num_tc; tc++) {
2111 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2119 for (tc--; tc >= 0; tc--)
2120 mlx5e_close_sq_wait(&c->sq[tc]);
2126 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2130 for (tc = 0; tc < c->priv->num_tc; tc++)
2131 mlx5e_close_sq_wait(&c->sq[tc]);
2135 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2139 /* setup priv and channel number */
2143 /* setup send tag */
2144 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2145 m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2147 init_completion(&c->completion);
2149 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2151 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2153 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2154 struct mlx5e_sq *sq = c->sq + tc;
2156 mtx_init(&sq->lock, "mlx5tx",
2157 MTX_NETWORK_LOCK " TX", MTX_DEF);
2158 mtx_init(&sq->comp_lock, "mlx5comp",
2159 MTX_NETWORK_LOCK " TX", MTX_DEF);
2161 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2166 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2169 m_snd_tag_rele(&c->tag.m_snd_tag);
2170 wait_for_completion(&c->completion);
2174 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2178 for (x = 0; x != channels; x++)
2179 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2183 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2187 callout_drain(&c->rq.watchdog);
2189 mtx_destroy(&c->rq.mtx);
2191 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2192 callout_drain(&c->sq[tc].cev_callout);
2193 mtx_destroy(&c->sq[tc].lock);
2194 mtx_destroy(&c->sq[tc].comp_lock);
2199 mlx5e_open_channel(struct mlx5e_priv *priv,
2200 struct mlx5e_channel_param *cparam,
2201 struct mlx5e_channel *c)
2203 struct epoch_tracker et;
2206 /* zero non-persistant data */
2207 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2208 for (i = 0; i != priv->num_tc; i++)
2209 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2211 /* open transmit completion queue */
2212 err = mlx5e_open_tx_cqs(c, cparam);
2216 /* open receive completion queue */
2217 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2218 &mlx5e_rx_cq_comp, c->ix);
2220 goto err_close_tx_cqs;
2222 err = mlx5e_open_sqs(c, cparam);
2224 goto err_close_rx_cq;
2226 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2230 /* poll receive queue initially */
2231 NET_EPOCH_ENTER(et);
2232 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2238 mlx5e_close_sqs_wait(c);
2241 mlx5e_close_cq(&c->rq.cq);
2244 mlx5e_close_tx_cqs(c);
2251 mlx5e_close_channel(struct mlx5e_channel *c)
2253 mlx5e_close_rq(&c->rq);
2257 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2259 mlx5e_close_rq_wait(&c->rq);
2260 mlx5e_close_sqs_wait(c);
2261 mlx5e_close_tx_cqs(c);
2265 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2269 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2270 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2271 if (r > MJUM16BYTES)
2276 else if (r > MJUMPAGESIZE)
2278 else if (r > MCLBYTES)
2284 * n + 1 must be a power of two, because stride size must be.
2285 * Stride size is 16 * (n + 1), as the first segment is
2288 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2291 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2300 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2301 struct mlx5e_rq_param *param)
2303 void *rqc = param->rqc;
2304 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2307 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2308 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2309 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2310 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2311 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2312 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2313 MLX5_SET(wq, wq, pd, priv->pdn);
2315 param->wq.buf_numa_node = 0;
2316 param->wq.db_numa_node = 0;
2317 param->wq.linear = 1;
2321 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2322 struct mlx5e_sq_param *param)
2324 void *sqc = param->sqc;
2325 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2327 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2328 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2329 MLX5_SET(wq, wq, pd, priv->pdn);
2331 param->wq.buf_numa_node = 0;
2332 param->wq.db_numa_node = 0;
2333 param->wq.linear = 1;
2337 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2338 struct mlx5e_cq_param *param)
2340 void *cqc = param->cqc;
2342 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2346 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2349 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2351 /* apply LRO restrictions */
2352 if (priv->params.hw_lro_en &&
2353 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2354 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2359 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2360 struct mlx5e_cq_param *param)
2362 struct net_dim_cq_moder curr;
2363 void *cqc = param->cqc;
2366 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2367 * format is more beneficial for FreeBSD use case.
2369 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2370 * in mlx5e_decompress_cqe.
2372 if (priv->params.cqe_zipping_en) {
2373 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2374 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2377 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2379 switch (priv->params.rx_cq_moderation_mode) {
2381 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2382 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2383 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2386 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2387 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2388 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2389 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2391 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2394 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2395 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2396 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2397 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2400 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2401 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2402 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2403 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2404 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2406 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2412 mlx5e_dim_build_cq_param(priv, param);
2414 mlx5e_build_common_cq_param(priv, param);
2418 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2419 struct mlx5e_cq_param *param)
2421 void *cqc = param->cqc;
2423 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2424 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2425 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2427 switch (priv->params.tx_cq_moderation_mode) {
2429 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2432 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2433 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2435 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2439 mlx5e_build_common_cq_param(priv, param);
2443 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2444 struct mlx5e_channel_param *cparam)
2446 memset(cparam, 0, sizeof(*cparam));
2448 mlx5e_build_rq_param(priv, &cparam->rq);
2449 mlx5e_build_sq_param(priv, &cparam->sq);
2450 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2451 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2455 mlx5e_open_channels(struct mlx5e_priv *priv)
2457 struct mlx5e_channel_param *cparam;
2462 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2464 mlx5e_build_channel_param(priv, cparam);
2465 for (i = 0; i < priv->params.num_channels; i++) {
2466 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2468 goto err_close_channels;
2471 for (j = 0; j < priv->params.num_channels; j++) {
2472 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2474 goto err_close_channels;
2476 free(cparam, M_MLX5EN);
2481 mlx5e_close_channel(&priv->channel[i]);
2482 mlx5e_close_channel_wait(&priv->channel[i]);
2484 free(cparam, M_MLX5EN);
2489 mlx5e_close_channels(struct mlx5e_priv *priv)
2493 for (i = 0; i < priv->params.num_channels; i++)
2494 mlx5e_close_channel(&priv->channel[i]);
2495 for (i = 0; i < priv->params.num_channels; i++)
2496 mlx5e_close_channel_wait(&priv->channel[i]);
2500 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2503 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2506 switch (priv->params.tx_cq_moderation_mode) {
2509 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2512 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2516 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2517 priv->params.tx_cq_moderation_usec,
2518 priv->params.tx_cq_moderation_pkts,
2522 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2523 priv->params.tx_cq_moderation_usec,
2524 priv->params.tx_cq_moderation_pkts));
2528 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2531 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2536 switch (priv->params.rx_cq_moderation_mode) {
2539 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2540 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2543 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2544 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2548 /* tear down dynamic interrupt moderation */
2550 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2551 mtx_unlock(&rq->mtx);
2553 /* wait for dynamic interrupt moderation work task, if any */
2554 cancel_work_sync(&rq->dim.work);
2556 if (priv->params.rx_cq_moderation_mode >= 2) {
2557 struct net_dim_cq_moder curr;
2559 mlx5e_get_default_profile(priv, dim_mode, &curr);
2561 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2562 curr.usec, curr.pkts, cq_mode);
2564 /* set dynamic interrupt moderation mode and zero defaults */
2566 rq->dim.mode = dim_mode;
2568 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2569 mtx_unlock(&rq->mtx);
2571 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2572 priv->params.rx_cq_moderation_usec,
2573 priv->params.rx_cq_moderation_pkts,
2579 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2580 priv->params.rx_cq_moderation_usec,
2581 priv->params.rx_cq_moderation_pkts));
2585 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2590 err = mlx5e_refresh_rq_params(priv, &c->rq);
2594 for (i = 0; i != priv->num_tc; i++) {
2595 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2604 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2608 /* check if channels are closed */
2609 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2612 for (i = 0; i < priv->params.num_channels; i++) {
2615 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2623 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2625 struct mlx5_core_dev *mdev = priv->mdev;
2626 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2627 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2629 memset(in, 0, sizeof(in));
2631 MLX5_SET(tisc, tisc, prio, tc);
2632 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2634 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2638 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2640 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2644 mlx5e_open_tises(struct mlx5e_priv *priv)
2646 int num_tc = priv->num_tc;
2650 for (tc = 0; tc < num_tc; tc++) {
2651 err = mlx5e_open_tis(priv, tc);
2653 goto err_close_tises;
2659 for (tc--; tc >= 0; tc--)
2660 mlx5e_close_tis(priv, tc);
2666 mlx5e_close_tises(struct mlx5e_priv *priv)
2668 int num_tc = priv->num_tc;
2671 for (tc = 0; tc < num_tc; tc++)
2672 mlx5e_close_tis(priv, tc);
2676 mlx5e_open_rqt(struct mlx5e_priv *priv)
2678 struct mlx5_core_dev *mdev = priv->mdev;
2680 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2687 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2689 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2690 in = mlx5_vzalloc(inlen);
2693 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2695 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2696 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2698 for (i = 0; i < sz; i++) {
2701 ix = rss_get_indirection_to_bucket(ix);
2703 /* ensure we don't overflow */
2704 ix %= priv->params.num_channels;
2706 /* apply receive side scaling stride, if any */
2707 ix -= ix % (int)priv->params.channels_rsss;
2709 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2712 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2714 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2716 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2724 mlx5e_close_rqt(struct mlx5e_priv *priv)
2726 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2727 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2729 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2730 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2732 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2736 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2738 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2741 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2743 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2745 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2746 MLX5_HASH_FIELD_SEL_DST_IP)
2748 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2749 MLX5_HASH_FIELD_SEL_DST_IP |\
2750 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2751 MLX5_HASH_FIELD_SEL_L4_DPORT)
2753 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2754 MLX5_HASH_FIELD_SEL_DST_IP |\
2755 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2757 if (priv->params.hw_lro_en) {
2758 MLX5_SET(tirc, tirc, lro_enable_mask,
2759 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2760 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2761 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2762 (priv->params.lro_wqe_sz -
2763 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2764 /* TODO: add the option to choose timer value dynamically */
2765 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2766 MLX5_CAP_ETH(priv->mdev,
2767 lro_timer_supported_periods[2]));
2770 /* setup parameters for hashing TIR type, if any */
2773 MLX5_SET(tirc, tirc, disp_type,
2774 MLX5_TIRC_DISP_TYPE_DIRECT);
2775 MLX5_SET(tirc, tirc, inline_rqn,
2776 priv->channel[0].rq.rqn);
2779 MLX5_SET(tirc, tirc, disp_type,
2780 MLX5_TIRC_DISP_TYPE_INDIRECT);
2781 MLX5_SET(tirc, tirc, indirect_table,
2783 MLX5_SET(tirc, tirc, rx_hash_fn,
2784 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2785 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2788 * The FreeBSD RSS implementation does currently not
2789 * support symmetric Toeplitz hashes:
2791 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2792 rss_getkey((uint8_t *)hkey);
2794 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2795 hkey[0] = cpu_to_be32(0xD181C62C);
2796 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2797 hkey[2] = cpu_to_be32(0x1983A2FC);
2798 hkey[3] = cpu_to_be32(0x943E1ADB);
2799 hkey[4] = cpu_to_be32(0xD9389E6B);
2800 hkey[5] = cpu_to_be32(0xD1039C2C);
2801 hkey[6] = cpu_to_be32(0xA74499AD);
2802 hkey[7] = cpu_to_be32(0x593D56D9);
2803 hkey[8] = cpu_to_be32(0xF3253C06);
2804 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2810 case MLX5E_TT_IPV4_TCP:
2811 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2812 MLX5_L3_PROT_TYPE_IPV4);
2813 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2814 MLX5_L4_PROT_TYPE_TCP);
2816 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2817 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2821 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2825 case MLX5E_TT_IPV6_TCP:
2826 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2827 MLX5_L3_PROT_TYPE_IPV6);
2828 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2829 MLX5_L4_PROT_TYPE_TCP);
2831 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2832 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2836 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2840 case MLX5E_TT_IPV4_UDP:
2841 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2842 MLX5_L3_PROT_TYPE_IPV4);
2843 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2844 MLX5_L4_PROT_TYPE_UDP);
2846 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2847 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2851 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2855 case MLX5E_TT_IPV6_UDP:
2856 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2857 MLX5_L3_PROT_TYPE_IPV6);
2858 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2859 MLX5_L4_PROT_TYPE_UDP);
2861 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2862 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2866 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2870 case MLX5E_TT_IPV4_IPSEC_AH:
2871 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2872 MLX5_L3_PROT_TYPE_IPV4);
2873 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2874 MLX5_HASH_IP_IPSEC_SPI);
2877 case MLX5E_TT_IPV6_IPSEC_AH:
2878 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2879 MLX5_L3_PROT_TYPE_IPV6);
2880 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2881 MLX5_HASH_IP_IPSEC_SPI);
2884 case MLX5E_TT_IPV4_IPSEC_ESP:
2885 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2886 MLX5_L3_PROT_TYPE_IPV4);
2887 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2888 MLX5_HASH_IP_IPSEC_SPI);
2891 case MLX5E_TT_IPV6_IPSEC_ESP:
2892 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2893 MLX5_L3_PROT_TYPE_IPV6);
2894 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2895 MLX5_HASH_IP_IPSEC_SPI);
2899 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2900 MLX5_L3_PROT_TYPE_IPV4);
2901 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2906 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2907 MLX5_L3_PROT_TYPE_IPV6);
2908 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2918 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2920 struct mlx5_core_dev *mdev = priv->mdev;
2926 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2927 in = mlx5_vzalloc(inlen);
2930 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2932 mlx5e_build_tir_ctx(priv, tirc, tt);
2934 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2942 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2944 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2948 mlx5e_open_tirs(struct mlx5e_priv *priv)
2953 for (i = 0; i < MLX5E_NUM_TT; i++) {
2954 err = mlx5e_open_tir(priv, i);
2956 goto err_close_tirs;
2962 for (i--; i >= 0; i--)
2963 mlx5e_close_tir(priv, i);
2969 mlx5e_close_tirs(struct mlx5e_priv *priv)
2973 for (i = 0; i < MLX5E_NUM_TT; i++)
2974 mlx5e_close_tir(priv, i);
2978 * SW MTU does not include headers,
2979 * HW MTU includes all headers and checksums.
2982 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2984 struct mlx5e_priv *priv = ifp->if_softc;
2985 struct mlx5_core_dev *mdev = priv->mdev;
2989 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2991 err = mlx5_set_port_mtu(mdev, hw_mtu);
2993 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2998 /* Update vport context MTU */
2999 err = mlx5_set_vport_mtu(mdev, hw_mtu);
3002 "Failed updating vport context with MTU size, err=%d\n",
3006 ifp->if_mtu = sw_mtu;
3008 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3009 if (err || !hw_mtu) {
3010 /* fallback to port oper mtu */
3011 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3015 "Query port MTU, after setting new MTU value, failed\n");
3017 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3020 "Port MTU %d is smaller than ifp mtu %d\n",
3022 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3025 "Port MTU %d is bigger than ifp mtu %d\n",
3028 priv->params_ethtool.hw_mtu = hw_mtu;
3031 while (hw_mtu & (hw_mtu - 1))
3032 hw_mtu &= (hw_mtu - 1);
3033 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3039 mlx5e_open_locked(struct ifnet *ifp)
3041 struct mlx5e_priv *priv = ifp->if_softc;
3045 /* check if already opened */
3046 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3050 if (rss_getnumbuckets() > priv->params.num_channels) {
3052 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3053 rss_getnumbuckets(), priv->params.num_channels);
3056 err = mlx5e_open_tises(priv);
3058 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3061 err = mlx5_vport_alloc_q_counter(priv->mdev,
3062 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3064 mlx5_en_err(priv->ifp,
3065 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3066 goto err_close_tises;
3068 /* store counter set ID */
3069 priv->counter_set_id = set_id;
3071 err = mlx5e_open_channels(priv);
3074 "mlx5e_open_channels failed, %d\n", err);
3075 goto err_dalloc_q_counter;
3077 err = mlx5e_open_rqt(priv);
3079 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3080 goto err_close_channels;
3082 err = mlx5e_open_tirs(priv);
3084 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3085 goto err_close_rqls;
3087 err = mlx5e_open_flow_table(priv);
3090 "mlx5e_open_flow_table failed, %d\n", err);
3091 goto err_close_tirs;
3093 err = mlx5e_add_all_vlan_rules(priv);
3096 "mlx5e_add_all_vlan_rules failed, %d\n", err);
3097 goto err_close_flow_table;
3099 set_bit(MLX5E_STATE_OPENED, &priv->state);
3101 mlx5e_update_carrier(priv);
3102 mlx5e_set_rx_mode_core(priv);
3106 err_close_flow_table:
3107 mlx5e_close_flow_table(priv);
3110 mlx5e_close_tirs(priv);
3113 mlx5e_close_rqt(priv);
3116 mlx5e_close_channels(priv);
3118 err_dalloc_q_counter:
3119 mlx5_vport_dealloc_q_counter(priv->mdev,
3120 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3123 mlx5e_close_tises(priv);
3129 mlx5e_open(void *arg)
3131 struct mlx5e_priv *priv = arg;
3134 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3135 mlx5_en_err(priv->ifp,
3136 "Setting port status to up failed\n");
3138 mlx5e_open_locked(priv->ifp);
3139 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3144 mlx5e_close_locked(struct ifnet *ifp)
3146 struct mlx5e_priv *priv = ifp->if_softc;
3148 /* check if already closed */
3149 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3152 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3154 mlx5e_set_rx_mode_core(priv);
3155 mlx5e_del_all_vlan_rules(priv);
3156 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3157 mlx5e_close_flow_table(priv);
3158 mlx5e_close_tirs(priv);
3159 mlx5e_close_rqt(priv);
3160 mlx5e_close_channels(priv);
3161 mlx5_vport_dealloc_q_counter(priv->mdev,
3162 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3163 mlx5e_close_tises(priv);
3168 #if (__FreeBSD_version >= 1100000)
3170 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3172 struct mlx5e_priv *priv = ifp->if_softc;
3175 /* PRIV_LOCK(priv); XXX not allowed */
3177 case IFCOUNTER_IPACKETS:
3178 retval = priv->stats.vport.rx_packets;
3180 case IFCOUNTER_IERRORS:
3181 retval = priv->stats.pport.in_range_len_errors +
3182 priv->stats.pport.out_of_range_len +
3183 priv->stats.pport.too_long_errors +
3184 priv->stats.pport.check_seq_err +
3185 priv->stats.pport.alignment_err;
3187 case IFCOUNTER_IQDROPS:
3188 retval = priv->stats.vport.rx_out_of_buffer;
3190 case IFCOUNTER_OPACKETS:
3191 retval = priv->stats.vport.tx_packets;
3193 case IFCOUNTER_OERRORS:
3194 retval = priv->stats.port_stats_debug.out_discards;
3196 case IFCOUNTER_IBYTES:
3197 retval = priv->stats.vport.rx_bytes;
3199 case IFCOUNTER_OBYTES:
3200 retval = priv->stats.vport.tx_bytes;
3202 case IFCOUNTER_IMCASTS:
3203 retval = priv->stats.vport.rx_multicast_packets;
3205 case IFCOUNTER_OMCASTS:
3206 retval = priv->stats.vport.tx_multicast_packets;
3208 case IFCOUNTER_OQDROPS:
3209 retval = priv->stats.vport.tx_queue_dropped;
3211 case IFCOUNTER_COLLISIONS:
3212 retval = priv->stats.pport.collisions;
3215 retval = if_get_counter_default(ifp, cnt);
3218 /* PRIV_UNLOCK(priv); XXX not allowed */
3224 mlx5e_set_rx_mode(struct ifnet *ifp)
3226 struct mlx5e_priv *priv = ifp->if_softc;
3228 queue_work(priv->wq, &priv->set_rx_mode_work);
3232 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3234 struct mlx5e_priv *priv;
3236 struct ifi2creq i2c;
3245 priv = ifp->if_softc;
3247 /* check if detaching */
3248 if (priv == NULL || priv->gone != 0)
3253 ifr = (struct ifreq *)data;
3256 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3258 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3259 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3262 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3264 mlx5e_close_locked(ifp);
3267 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3270 mlx5e_open_locked(ifp);
3274 "Invalid MTU value. Min val: %d, Max val: %d\n",
3275 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3280 if ((ifp->if_flags & IFF_UP) &&
3281 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3282 mlx5e_set_rx_mode(ifp);
3286 if (ifp->if_flags & IFF_UP) {
3287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3288 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3289 mlx5e_open_locked(ifp);
3290 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3291 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3294 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3295 mlx5_set_port_status(priv->mdev,
3297 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3298 mlx5e_close_locked(ifp);
3299 mlx5e_update_carrier(priv);
3300 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3307 mlx5e_set_rx_mode(ifp);
3312 ifr = (struct ifreq *)data;
3313 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3316 ifr = (struct ifreq *)data;
3318 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3320 if (mask & IFCAP_TXCSUM) {
3321 ifp->if_capenable ^= IFCAP_TXCSUM;
3322 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3324 if (IFCAP_TSO4 & ifp->if_capenable &&
3325 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3326 mask &= ~IFCAP_TSO4;
3327 ifp->if_capenable &= ~IFCAP_TSO4;
3328 ifp->if_hwassist &= ~CSUM_IP_TSO;
3330 "tso4 disabled due to -txcsum.\n");
3333 if (mask & IFCAP_TXCSUM_IPV6) {
3334 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3335 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3337 if (IFCAP_TSO6 & ifp->if_capenable &&
3338 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3339 mask &= ~IFCAP_TSO6;
3340 ifp->if_capenable &= ~IFCAP_TSO6;
3341 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3343 "tso6 disabled due to -txcsum6.\n");
3346 if (mask & IFCAP_NOMAP)
3347 ifp->if_capenable ^= IFCAP_NOMAP;
3348 if (mask & IFCAP_TXTLS4)
3349 ifp->if_capenable ^= IFCAP_TXTLS4;
3350 if (mask & IFCAP_TXTLS6)
3351 ifp->if_capenable ^= IFCAP_TXTLS6;
3352 if (mask & IFCAP_RXCSUM)
3353 ifp->if_capenable ^= IFCAP_RXCSUM;
3354 if (mask & IFCAP_RXCSUM_IPV6)
3355 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3356 if (mask & IFCAP_TSO4) {
3357 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3358 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3359 mlx5_en_err(ifp, "enable txcsum first.\n");
3363 ifp->if_capenable ^= IFCAP_TSO4;
3364 ifp->if_hwassist ^= CSUM_IP_TSO;
3366 if (mask & IFCAP_TSO6) {
3367 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3368 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3369 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3373 ifp->if_capenable ^= IFCAP_TSO6;
3374 ifp->if_hwassist ^= CSUM_IP6_TSO;
3376 if (mask & IFCAP_VLAN_HWFILTER) {
3377 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3378 mlx5e_disable_vlan_filter(priv);
3380 mlx5e_enable_vlan_filter(priv);
3382 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3384 if (mask & IFCAP_VLAN_HWTAGGING)
3385 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3386 if (mask & IFCAP_WOL_MAGIC)
3387 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3389 VLAN_CAPABILITIES(ifp);
3390 /* turn off LRO means also turn of HW LRO - if it's on */
3391 if (mask & IFCAP_LRO) {
3392 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3393 bool need_restart = false;
3395 ifp->if_capenable ^= IFCAP_LRO;
3397 /* figure out if updating HW LRO is needed */
3398 if (!(ifp->if_capenable & IFCAP_LRO)) {
3399 if (priv->params.hw_lro_en) {
3400 priv->params.hw_lro_en = false;
3401 need_restart = true;
3404 if (priv->params.hw_lro_en == false &&
3405 priv->params_ethtool.hw_lro != 0) {
3406 priv->params.hw_lro_en = true;
3407 need_restart = true;
3410 if (was_opened && need_restart) {
3411 mlx5e_close_locked(ifp);
3412 mlx5e_open_locked(ifp);
3415 if (mask & IFCAP_HWRXTSTMP) {
3416 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3417 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3418 if (priv->clbr_done == 0)
3419 mlx5e_reset_calibration_callout(priv);
3421 callout_drain(&priv->tstmp_clbr);
3422 priv->clbr_done = 0;
3430 ifr = (struct ifreq *)data;
3433 * Copy from the user-space address ifr_data to the
3434 * kernel-space address i2c
3436 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3440 if (i2c.len > sizeof(i2c.data)) {
3446 /* Get module_num which is required for the query_eeprom */
3447 error = mlx5_query_module_num(priv->mdev, &module_num);
3450 "Query module num failed, eeprom reading is not supported\n");
3454 /* Check if module is present before doing an access */
3455 module_status = mlx5_query_module_status(priv->mdev, module_num);
3456 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3461 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3462 * The internal conversion is as follows:
3464 if (i2c.dev_addr == 0xA0)
3465 read_addr = MLX5_I2C_ADDR_LOW;
3466 else if (i2c.dev_addr == 0xA2)
3467 read_addr = MLX5_I2C_ADDR_HIGH;
3470 "Query eeprom failed, Invalid Address: %X\n",
3475 error = mlx5_query_eeprom(priv->mdev,
3476 read_addr, MLX5_EEPROM_LOW_PAGE,
3477 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3478 (uint32_t *)i2c.data, &size_read);
3481 "Query eeprom failed, eeprom reading is not supported\n");
3486 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3487 error = mlx5_query_eeprom(priv->mdev,
3488 read_addr, MLX5_EEPROM_LOW_PAGE,
3489 (uint32_t)(i2c.offset + size_read),
3490 (uint32_t)(i2c.len - size_read), module_num,
3491 (uint32_t *)(i2c.data + size_read), &size_read);
3495 "Query eeprom failed, eeprom reading is not supported\n");
3500 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3506 error = ether_ioctl(ifp, command, data);
3513 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3516 * TODO: uncoment once FW really sets all these bits if
3517 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3518 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3519 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3523 /* TODO: add more must-to-have features */
3525 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3532 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3534 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3535 const int max_size = MLX5E_MAX_TX_INLINE;
3536 const int bf_buf_size =
3537 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3538 (sizeof(struct mlx5e_tx_wqe) - 2);
3540 /* verify against driver limits */
3541 if (bf_buf_size > max_size)
3543 else if (bf_buf_size < min_size)
3546 return (bf_buf_size);
3550 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3551 struct mlx5e_priv *priv,
3552 int num_comp_vectors)
3557 * TODO: Consider link speed for setting "log_sq_size",
3558 * "log_rq_size" and "cq_moderation_xxx":
3560 priv->params.log_sq_size =
3561 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3562 priv->params.log_rq_size =
3563 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3564 priv->params.rx_cq_moderation_usec =
3565 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3566 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3567 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3568 priv->params.rx_cq_moderation_mode =
3569 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3570 priv->params.rx_cq_moderation_pkts =
3571 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3572 priv->params.tx_cq_moderation_usec =
3573 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3574 priv->params.tx_cq_moderation_pkts =
3575 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3576 priv->params.min_rx_wqes =
3577 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3578 priv->params.rx_hash_log_tbl_sz =
3579 (order_base_2(num_comp_vectors) >
3580 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3581 order_base_2(num_comp_vectors) :
3582 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3583 priv->params.num_tc = 1;
3584 priv->params.default_vlan_prio = 0;
3585 priv->counter_set_id = -1;
3586 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3588 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3593 * hw lro is currently defaulted to off. when it won't anymore we
3594 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3596 priv->params.hw_lro_en = false;
3597 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3600 * CQE zipping is currently defaulted to off. when it won't
3601 * anymore we will consider the HW capability:
3602 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3604 priv->params.cqe_zipping_en = false;
3607 priv->params.num_channels = num_comp_vectors;
3608 priv->params.channels_rsss = 1;
3609 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3610 priv->queue_mapping_channel_mask =
3611 roundup_pow_of_two(num_comp_vectors) - 1;
3612 priv->num_tc = priv->params.num_tc;
3613 priv->default_vlan_prio = priv->params.default_vlan_prio;
3615 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3616 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3617 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3623 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3624 struct mlx5_core_mr *mkey)
3626 struct ifnet *ifp = priv->ifp;
3627 struct mlx5_core_dev *mdev = priv->mdev;
3628 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3633 in = mlx5_vzalloc(inlen);
3635 mlx5_en_err(ifp, "failed to allocate inbox\n");
3639 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3640 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3641 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */
3642 MLX5_SET(mkc, mkc, lw, 1);
3643 MLX5_SET(mkc, mkc, lr, 1);
3645 MLX5_SET(mkc, mkc, pd, pdn);
3646 MLX5_SET(mkc, mkc, length64, 1);
3647 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3649 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3651 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3658 static const char *mlx5e_vport_stats_desc[] = {
3659 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3662 static const char *mlx5e_pport_stats_desc[] = {
3663 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3667 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3671 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3672 sx_init(&priv->state_lock, "mlx5state");
3673 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3674 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3675 for (x = 0; x != channels; x++)
3676 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3680 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3684 for (x = 0; x != channels; x++)
3685 mlx5e_chan_static_destroy(&priv->channel[x]);
3686 callout_drain(&priv->watchdog);
3687 mtx_destroy(&priv->async_events_mtx);
3688 sx_destroy(&priv->state_lock);
3692 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3695 * %d.%d%.d the string format.
3696 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3697 * We need at most 5 chars to store that.
3698 * It also has: two "." and NULL at the end, which means we need 18
3699 * (5*3 + 3) chars at most.
3702 struct mlx5e_priv *priv = arg1;
3705 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3706 fw_rev_sub(priv->mdev));
3707 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3712 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3716 for (i = 0; i < ch->priv->num_tc; i++)
3717 mlx5e_drain_sq(&ch->sq[i]);
3721 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3724 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3725 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3726 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3727 sq->doorbell.d64 = 0;
3731 mlx5e_resume_sq(struct mlx5e_sq *sq)
3735 /* check if already enabled */
3736 if (READ_ONCE(sq->running) != 0)
3739 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3740 MLX5_SQC_STATE_RST);
3742 mlx5_en_err(sq->ifp,
3743 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3749 /* reset doorbell prior to moving from RST to RDY */
3750 mlx5e_reset_sq_doorbell_record(sq);
3752 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3753 MLX5_SQC_STATE_RDY);
3755 mlx5_en_err(sq->ifp,
3756 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3759 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3760 WRITE_ONCE(sq->running, 1);
3764 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3768 for (i = 0; i < ch->priv->num_tc; i++)
3769 mlx5e_resume_sq(&ch->sq[i]);
3773 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3775 struct mlx5e_rq *rq = &ch->rq;
3776 struct epoch_tracker et;
3781 callout_stop(&rq->watchdog);
3782 mtx_unlock(&rq->mtx);
3784 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3786 mlx5_en_err(rq->ifp,
3787 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3790 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3792 NET_EPOCH_ENTER(et);
3793 rq->cq.mcq.comp(&rq->cq.mcq);
3798 * Transitioning into RST state will allow the FW to track less ERR state queues,
3799 * thus reducing the recv queue flushing time
3801 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3803 mlx5_en_err(rq->ifp,
3804 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3809 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3811 struct mlx5e_rq *rq = &ch->rq;
3812 struct epoch_tracker et;
3816 mlx5_wq_ll_update_db_record(&rq->wq);
3817 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3819 mlx5_en_err(rq->ifp,
3820 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3825 NET_EPOCH_ENTER(et);
3826 rq->cq.mcq.comp(&rq->cq.mcq);
3831 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3835 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3838 for (i = 0; i < priv->params.num_channels; i++) {
3840 mlx5e_disable_tx_dma(&priv->channel[i]);
3842 mlx5e_enable_tx_dma(&priv->channel[i]);
3847 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3851 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3854 for (i = 0; i < priv->params.num_channels; i++) {
3856 mlx5e_disable_rx_dma(&priv->channel[i]);
3858 mlx5e_enable_rx_dma(&priv->channel[i]);
3863 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3865 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3866 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
3867 priv, 0, sysctl_firmware, "A", "HCA firmware version");
3869 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3870 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3875 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3877 struct mlx5e_priv *priv = arg1;
3878 uint8_t temp[MLX5E_MAX_PRIORITY];
3885 tx_pfc = priv->params.tx_priority_flow_control;
3887 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3888 temp[i] = (tx_pfc >> i) & 1;
3890 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3891 if (err || !req->newptr)
3893 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3897 priv->params.tx_priority_flow_control = 0;
3899 /* range check input value */
3900 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3905 priv->params.tx_priority_flow_control |= (temp[i] << i);
3908 /* check if update is required */
3909 if (tx_pfc != priv->params.tx_priority_flow_control)
3910 err = -mlx5e_set_port_pfc(priv);
3913 priv->params.tx_priority_flow_control= tx_pfc;
3920 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3922 struct mlx5e_priv *priv = arg1;
3923 uint8_t temp[MLX5E_MAX_PRIORITY];
3930 rx_pfc = priv->params.rx_priority_flow_control;
3932 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3933 temp[i] = (rx_pfc >> i) & 1;
3935 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3936 if (err || !req->newptr)
3938 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3942 priv->params.rx_priority_flow_control = 0;
3944 /* range check input value */
3945 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3950 priv->params.rx_priority_flow_control |= (temp[i] << i);
3953 /* check if update is required */
3954 if (rx_pfc != priv->params.rx_priority_flow_control) {
3955 err = -mlx5e_set_port_pfc(priv);
3956 if (err == 0 && priv->sw_is_port_buf_owner)
3957 err = mlx5e_update_buf_lossy(priv);
3961 priv->params.rx_priority_flow_control= rx_pfc;
3968 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3970 #if (__FreeBSD_version < 1100000)
3975 /* enable pauseframes by default */
3976 priv->params.tx_pauseframe_control = 1;
3977 priv->params.rx_pauseframe_control = 1;
3979 /* disable ports flow control, PFC, by default */
3980 priv->params.tx_priority_flow_control = 0;
3981 priv->params.rx_priority_flow_control = 0;
3983 #if (__FreeBSD_version < 1100000)
3984 /* compute path for sysctl */
3985 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3986 device_get_unit(priv->mdev->pdev->dev.bsddev));
3988 /* try to fetch tunable, if any */
3989 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3991 /* compute path for sysctl */
3992 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3993 device_get_unit(priv->mdev->pdev->dev.bsddev));
3995 /* try to fetch tunable, if any */
3996 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3999 /* register pauseframe SYSCTLs */
4000 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4001 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4002 &priv->params.tx_pauseframe_control, 0,
4003 "Set to enable TX pause frames. Clear to disable.");
4005 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4006 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4007 &priv->params.rx_pauseframe_control, 0,
4008 "Set to enable RX pause frames. Clear to disable.");
4010 /* register priority flow control, PFC, SYSCTLs */
4011 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4012 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4013 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4014 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4016 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4017 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4018 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4019 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4024 priv->params.tx_pauseframe_control =
4025 priv->params.tx_pauseframe_control ? 1 : 0;
4026 priv->params.rx_pauseframe_control =
4027 priv->params.rx_pauseframe_control ? 1 : 0;
4029 /* update firmware */
4030 error = mlx5e_set_port_pause_and_pfc(priv);
4031 if (error == -EINVAL) {
4032 mlx5_en_err(priv->ifp,
4033 "Global pauseframes must be disabled before enabling PFC.\n");
4034 priv->params.rx_priority_flow_control = 0;
4035 priv->params.tx_priority_flow_control = 0;
4037 /* update firmware */
4038 (void) mlx5e_set_port_pause_and_pfc(priv);
4044 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4045 union if_snd_tag_alloc_params *params,
4046 struct m_snd_tag **ppmt)
4048 struct mlx5e_priv *priv;
4049 struct mlx5e_channel *pch;
4051 priv = ifp->if_softc;
4053 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4054 return (EOPNOTSUPP);
4056 /* keep this code synced with mlx5e_select_queue() */
4057 u32 ch = priv->params.num_channels;
4061 if (rss_hash2bucket(params->hdr.flowid,
4062 params->hdr.flowtype, &temp) == 0)
4066 ch = (params->hdr.flowid % 128) % ch;
4069 * NOTE: The channels array is only freed at detach
4070 * and it safe to return a pointer to the send tag
4071 * inside the channels structure as long as we
4072 * reference the priv.
4074 pch = priv->channel + ch;
4076 /* check if send queue is not running */
4077 if (unlikely(pch->sq[0].running == 0))
4079 m_snd_tag_ref(&pch->tag.m_snd_tag);
4080 *ppmt = &pch->tag.m_snd_tag;
4086 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4088 struct mlx5e_channel *pch =
4089 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4091 params->unlimited.max_rate = -1ULL;
4092 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4097 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4099 struct mlx5e_channel *pch =
4100 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4102 complete(&pch->completion);
4106 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4107 union if_snd_tag_alloc_params *params,
4108 struct m_snd_tag **ppmt)
4111 switch (params->hdr.type) {
4113 case IF_SND_TAG_TYPE_RATE_LIMIT:
4114 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4115 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4116 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4117 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4120 case IF_SND_TAG_TYPE_UNLIMITED:
4121 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4123 case IF_SND_TAG_TYPE_TLS:
4124 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4127 return (EOPNOTSUPP);
4132 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4134 struct mlx5e_snd_tag *tag =
4135 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4137 switch (tag->type) {
4139 case IF_SND_TAG_TYPE_RATE_LIMIT:
4140 return (mlx5e_rl_snd_tag_modify(pmt, params));
4141 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4142 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4143 return (mlx5e_tls_snd_tag_modify(pmt, params));
4146 case IF_SND_TAG_TYPE_UNLIMITED:
4148 case IF_SND_TAG_TYPE_TLS:
4151 return (EOPNOTSUPP);
4156 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4158 struct mlx5e_snd_tag *tag =
4159 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4161 switch (tag->type) {
4163 case IF_SND_TAG_TYPE_RATE_LIMIT:
4164 return (mlx5e_rl_snd_tag_query(pmt, params));
4165 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4166 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4167 return (mlx5e_tls_snd_tag_query(pmt, params));
4170 case IF_SND_TAG_TYPE_UNLIMITED:
4171 return (mlx5e_ul_snd_tag_query(pmt, params));
4173 case IF_SND_TAG_TYPE_TLS:
4174 return (mlx5e_tls_snd_tag_query(pmt, params));
4177 return (EOPNOTSUPP);
4182 #define NUM_HDWR_RATES_MLX 13
4183 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4184 135375, /* 1,083,000 */
4185 180500, /* 1,444,000 */
4186 270750, /* 2,166,000 */
4187 361000, /* 2,888,000 */
4188 541500, /* 4,332,000 */
4189 721875, /* 5,775,000 */
4190 1082875, /* 8,663,000 */
4191 1443875, /* 11,551,000 */
4192 2165750, /* 17,326,000 */
4193 2887750, /* 23,102,000 */
4194 4331625, /* 34,653,000 */
4195 5775500, /* 46,204,000 */
4196 8663125 /* 69,305,000 */
4200 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4203 * This function needs updating by the driver maintainer!
4204 * For the MLX card there are currently (ConectX-4?) 13
4205 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4207 * This will change based on later adapters
4208 * and this code should be updated to look at ifp
4209 * and figure out the specific adapter type
4210 * settings i.e. how many rates as well
4211 * as if they are fixed (as is shown here) or
4212 * if they are dynamic (example chelsio t4). Also if there
4213 * is a maximum number of flows that the adapter
4214 * can handle that too needs to be updated in
4215 * the max_flows field.
4217 q->rate_table = adapter_rates_mlx;
4218 q->flags = RT_IS_FIXED_TABLE;
4219 q->max_flows = 0; /* mlx has no limit */
4220 q->number_of_rates = NUM_HDWR_RATES_MLX;
4221 q->min_segment_burst = 1;
4226 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4228 struct mlx5e_snd_tag *tag =
4229 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4231 switch (tag->type) {
4233 case IF_SND_TAG_TYPE_RATE_LIMIT:
4234 mlx5e_rl_snd_tag_free(pmt);
4236 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4237 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4238 mlx5e_tls_snd_tag_free(pmt);
4242 case IF_SND_TAG_TYPE_UNLIMITED:
4243 mlx5e_ul_snd_tag_free(pmt);
4246 case IF_SND_TAG_TYPE_TLS:
4247 mlx5e_tls_snd_tag_free(pmt);
4256 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4259 struct mlx5e_priv *priv;
4260 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4262 struct sysctl_oid_list *child;
4263 int ncv = mdev->priv.eq_table.num_comp_vectors;
4265 struct pfil_head_args pa;
4269 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4272 struct media media_entry = {};
4274 if (mlx5e_check_required_hca_cap(mdev)) {
4275 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4279 * Try to allocate the priv and make room for worst-case
4280 * number of channel structures:
4282 priv = malloc(sizeof(*priv) +
4283 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4284 M_MLX5EN, M_WAITOK | M_ZERO);
4286 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4288 mlx5_core_err(mdev, "if_alloc() failed\n");
4291 /* setup all static fields */
4292 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4294 ifp->if_softc = priv;
4295 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4296 ifp->if_mtu = ETHERMTU;
4297 ifp->if_init = mlx5e_open;
4298 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
4300 ifp->if_ioctl = mlx5e_ioctl;
4301 ifp->if_transmit = mlx5e_xmit;
4302 ifp->if_qflush = if_qflush;
4303 #if (__FreeBSD_version >= 1100000)
4304 ifp->if_get_counter = mlx5e_get_counter;
4306 ifp->if_snd.ifq_maxlen = ifqmaxlen;
4308 * Set driver features
4310 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4311 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4312 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4313 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4314 ifp->if_capabilities |= IFCAP_LRO;
4315 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4316 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4317 ifp->if_capabilities |= IFCAP_NOMAP;
4318 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4319 ifp->if_capabilities |= IFCAP_TXRTLMT;
4320 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4321 ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4322 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4323 ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4325 ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4327 /* set TSO limits so that we don't have to drop TX packets */
4328 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4329 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4330 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4332 ifp->if_capenable = ifp->if_capabilities;
4333 ifp->if_hwassist = 0;
4334 if (ifp->if_capenable & IFCAP_TSO)
4335 ifp->if_hwassist |= CSUM_TSO;
4336 if (ifp->if_capenable & IFCAP_TXCSUM)
4337 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4338 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4339 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4341 /* ifnet sysctl tree */
4342 sysctl_ctx_init(&priv->sysctl_ctx);
4343 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4344 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4345 "MLX5 ethernet - interface name");
4346 if (priv->sysctl_ifnet == NULL) {
4347 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4348 goto err_free_sysctl;
4350 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4351 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4352 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4353 "MLX5 ethernet - interface unit");
4354 if (priv->sysctl_ifnet == NULL) {
4355 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4356 goto err_free_sysctl;
4359 /* HW sysctl tree */
4360 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4361 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4362 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4363 "MLX5 ethernet dev hw");
4364 if (priv->sysctl_hw == NULL) {
4365 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4366 goto err_free_sysctl;
4369 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4371 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4372 goto err_free_sysctl;
4375 /* reuse mlx5core's watchdog workqueue */
4376 priv->wq = mdev->priv.health.wq_watchdog;
4378 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4380 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4383 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4385 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4386 goto err_unmap_free_uar;
4388 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4391 "mlx5_alloc_transport_domain failed, %d\n", err);
4392 goto err_dealloc_pd;
4394 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4396 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4397 goto err_dealloc_transport_domain;
4399 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4401 /* check if we should generate a random MAC address */
4402 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4403 is_zero_ether_addr(dev_addr)) {
4404 random_ether_addr(dev_addr);
4405 mlx5_en_err(ifp, "Assigned random MAC address\n");
4408 err = mlx5e_rl_init(priv);
4410 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4411 goto err_create_mkey;
4414 err = mlx5e_tls_init(priv);
4416 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4420 /* set default MTU */
4421 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4423 /* Set default media status */
4424 priv->media_status_last = IFM_AVALID;
4425 priv->media_active_last = IFM_ETHER | IFM_AUTO |
4426 IFM_ETH_RXPAUSE | IFM_FDX;
4428 /* setup default pauseframes configuration */
4429 mlx5e_setup_pauseframes(priv);
4431 /* Setup supported medias */
4432 //TODO: If we failed to query ptys is it ok to proceed??
4433 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4434 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4435 ptys_extended_ethernet);
4436 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4437 eth_proto_capability);
4438 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4439 connector_type = MLX5_GET(ptys_reg, out,
4443 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4446 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4447 mlx5e_media_change, mlx5e_media_status);
4449 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4450 for (i = 0; i != speeds_num; i++) {
4451 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4452 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4453 mlx5e_mode_table[i][j];
4454 if (media_entry.baudrate == 0)
4456 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4457 ifmedia_add(&priv->media,
4458 media_entry.subtype |
4459 IFM_ETHER, 0, NULL);
4460 ifmedia_add(&priv->media,
4461 media_entry.subtype |
4462 IFM_ETHER | IFM_FDX |
4463 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4468 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4469 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4470 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4472 /* Set autoselect by default */
4473 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4474 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4476 DEBUGNET_SET(ifp, mlx5_en);
4478 ether_ifattach(ifp, dev_addr);
4480 /* Register for VLAN events */
4481 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4482 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4483 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4484 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4486 /* Link is down by default */
4487 if_link_state_change(ifp, LINK_STATE_DOWN);
4489 mlx5e_enable_async_events(priv);
4491 mlx5e_add_hw_stats(priv);
4493 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4494 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4495 priv->stats.vport.arg);
4497 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4498 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4499 priv->stats.pport.arg);
4501 mlx5e_create_ethtool(priv);
4503 mtx_lock(&priv->async_events_mtx);
4504 mlx5e_update_stats(priv);
4505 mtx_unlock(&priv->async_events_mtx);
4507 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4508 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4509 &priv->clbr_done, 0,
4510 "RX timestamps calibration state");
4511 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4512 mlx5e_reset_calibration_callout(priv);
4514 pa.pa_version = PFIL_VERSION;
4515 pa.pa_flags = PFIL_IN;
4516 pa.pa_type = PFIL_TYPE_ETHERNET;
4517 pa.pa_headname = ifp->if_xname;
4518 priv->pfil = pfil_head_register(&pa);
4523 mlx5e_rl_cleanup(priv);
4526 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4528 err_dealloc_transport_domain:
4529 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4532 mlx5_core_dealloc_pd(mdev, priv->pdn);
4535 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4538 flush_workqueue(priv->wq);
4541 sysctl_ctx_free(&priv->sysctl_ctx);
4542 if (priv->sysctl_debug)
4543 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4544 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4548 free(priv, M_MLX5EN);
4553 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4555 struct mlx5e_priv *priv = vpriv;
4556 struct ifnet *ifp = priv->ifp;
4558 /* don't allow more IOCTLs */
4561 /* XXX wait a bit to allow IOCTL handlers to complete */
4566 * The kernel can have reference(s) via the m_snd_tag's into
4567 * the ratelimit channels, and these must go away before
4570 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4571 mlx5_en_err(priv->ifp,
4572 "Waiting for all ratelimit connections to terminate\n");
4576 /* wait for all unlimited send tags to complete */
4577 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4579 /* stop watchdog timer */
4580 callout_drain(&priv->watchdog);
4582 callout_drain(&priv->tstmp_clbr);
4584 if (priv->vlan_attach != NULL)
4585 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4586 if (priv->vlan_detach != NULL)
4587 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4589 /* make sure device gets closed */
4591 mlx5e_close_locked(ifp);
4594 /* deregister pfil */
4595 if (priv->pfil != NULL) {
4596 pfil_head_unregister(priv->pfil);
4600 /* unregister device */
4601 ifmedia_removeall(&priv->media);
4602 ether_ifdetach(ifp);
4604 mlx5e_tls_cleanup(priv);
4605 mlx5e_rl_cleanup(priv);
4607 /* destroy all remaining sysctl nodes */
4608 sysctl_ctx_free(&priv->stats.vport.ctx);
4609 sysctl_ctx_free(&priv->stats.pport.ctx);
4610 if (priv->sysctl_debug)
4611 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4612 sysctl_ctx_free(&priv->sysctl_ctx);
4614 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4615 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4616 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4617 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4618 mlx5e_disable_async_events(priv);
4619 flush_workqueue(priv->wq);
4620 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4622 free(priv, M_MLX5EN);
4627 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4629 struct mlx5e_priv *priv = if_getsoftc(dev);
4632 *nrxr = priv->params.num_channels;
4633 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4634 *clsize = MLX5E_MAX_RX_BYTES;
4639 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4644 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
4646 struct mlx5e_priv *priv = if_getsoftc(dev);
4647 struct mlx5e_sq *sq;
4650 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4651 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
4654 sq = &priv->channel[0].sq[0];
4656 if (sq->running == 0) {
4661 if (mlx5e_sq_xmit(sq, &m) != 0) {
4668 if (likely(sq->doorbell.d64 != 0)) {
4669 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
4670 sq->doorbell.d64 = 0;
4676 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
4678 struct mlx5e_priv *priv = if_getsoftc(dev);
4680 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
4681 (priv->media_status_last & IFM_ACTIVE) == 0)
4684 mlx5_poll_interrupts(priv->mdev);
4688 #endif /* DEBUGNET */
4691 mlx5e_get_ifp(void *vpriv)
4693 struct mlx5e_priv *priv = vpriv;
4698 static struct mlx5_interface mlx5e_interface = {
4699 .add = mlx5e_create_ifp,
4700 .remove = mlx5e_destroy_ifp,
4701 .event = mlx5e_async_event,
4702 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4703 .get_dev = mlx5e_get_ifp,
4709 mlx5_register_interface(&mlx5e_interface);
4715 mlx5_unregister_interface(&mlx5e_interface);
4719 mlx5e_show_version(void __unused *arg)
4722 printf("%s", mlx5e_version);
4724 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4726 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
4727 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
4729 #if (__FreeBSD_version >= 1100000)
4730 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4732 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4733 MODULE_VERSION(mlx5en, 1);