2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_channel_param {
38 struct mlx5e_rq_param rq;
39 struct mlx5e_sq_param sq;
40 struct mlx5e_cq_param rx_cq;
41 struct mlx5e_cq_param tx_cq;
47 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
49 [MLX5E_1000BASE_CX_SGMII] = {
50 .subtype = IFM_1000_CX_SGMII,
51 .baudrate = IF_Mbps(1000ULL),
53 [MLX5E_1000BASE_KX] = {
54 .subtype = IFM_1000_KX,
55 .baudrate = IF_Mbps(1000ULL),
57 [MLX5E_10GBASE_CX4] = {
58 .subtype = IFM_10G_CX4,
59 .baudrate = IF_Gbps(10ULL),
61 [MLX5E_10GBASE_KX4] = {
62 .subtype = IFM_10G_KX4,
63 .baudrate = IF_Gbps(10ULL),
65 [MLX5E_10GBASE_KR] = {
66 .subtype = IFM_10G_KR,
67 .baudrate = IF_Gbps(10ULL),
69 [MLX5E_20GBASE_KR2] = {
70 .subtype = IFM_20G_KR2,
71 .baudrate = IF_Gbps(20ULL),
73 [MLX5E_40GBASE_CR4] = {
74 .subtype = IFM_40G_CR4,
75 .baudrate = IF_Gbps(40ULL),
77 [MLX5E_40GBASE_KR4] = {
78 .subtype = IFM_40G_KR4,
79 .baudrate = IF_Gbps(40ULL),
81 [MLX5E_56GBASE_R4] = {
82 .subtype = IFM_56G_R4,
83 .baudrate = IF_Gbps(56ULL),
85 [MLX5E_10GBASE_CR] = {
86 .subtype = IFM_10G_CR1,
87 .baudrate = IF_Gbps(10ULL),
89 [MLX5E_10GBASE_SR] = {
90 .subtype = IFM_10G_SR,
91 .baudrate = IF_Gbps(10ULL),
93 [MLX5E_10GBASE_ER] = {
94 .subtype = IFM_10G_ER,
95 .baudrate = IF_Gbps(10ULL),
97 [MLX5E_40GBASE_SR4] = {
98 .subtype = IFM_40G_SR4,
99 .baudrate = IF_Gbps(40ULL),
101 [MLX5E_40GBASE_LR4] = {
102 .subtype = IFM_40G_LR4,
103 .baudrate = IF_Gbps(40ULL),
105 [MLX5E_100GBASE_CR4] = {
106 .subtype = IFM_100G_CR4,
107 .baudrate = IF_Gbps(100ULL),
109 [MLX5E_100GBASE_SR4] = {
110 .subtype = IFM_100G_SR4,
111 .baudrate = IF_Gbps(100ULL),
113 [MLX5E_100GBASE_KR4] = {
114 .subtype = IFM_100G_KR4,
115 .baudrate = IF_Gbps(100ULL),
117 [MLX5E_100GBASE_LR4] = {
118 .subtype = IFM_100G_LR4,
119 .baudrate = IF_Gbps(100ULL),
121 [MLX5E_100BASE_TX] = {
122 .subtype = IFM_100_TX,
123 .baudrate = IF_Mbps(100ULL),
125 [MLX5E_1000BASE_T] = {
126 .subtype = IFM_1000_T,
127 .baudrate = IF_Mbps(1000ULL),
129 [MLX5E_10GBASE_T] = {
130 .subtype = IFM_10G_T,
131 .baudrate = IF_Gbps(10ULL),
133 [MLX5E_25GBASE_CR] = {
134 .subtype = IFM_25G_CR,
135 .baudrate = IF_Gbps(25ULL),
137 [MLX5E_25GBASE_KR] = {
138 .subtype = IFM_25G_KR,
139 .baudrate = IF_Gbps(25ULL),
141 [MLX5E_25GBASE_SR] = {
142 .subtype = IFM_25G_SR,
143 .baudrate = IF_Gbps(25ULL),
145 [MLX5E_50GBASE_CR2] = {
146 .subtype = IFM_50G_CR2,
147 .baudrate = IF_Gbps(50ULL),
149 [MLX5E_50GBASE_KR2] = {
150 .subtype = IFM_50G_KR2,
151 .baudrate = IF_Gbps(50ULL),
155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
157 static SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "MLX5 driver parameters");
160 mlx5e_update_carrier(struct mlx5e_priv *priv)
162 struct mlx5_core_dev *mdev = priv->mdev;
163 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
169 port_state = mlx5_query_vport_state(mdev,
170 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
172 if (port_state == VPORT_STATE_UP) {
173 priv->media_status_last |= IFM_ACTIVE;
175 priv->media_status_last &= ~IFM_ACTIVE;
176 priv->media_active_last = IFM_ETHER;
177 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
181 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
183 priv->media_active_last = IFM_ETHER;
184 priv->ifp->if_baudrate = 1;
185 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
189 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
191 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
192 if (mlx5e_mode_table[i].baudrate == 0)
194 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
195 priv->ifp->if_baudrate =
196 mlx5e_mode_table[i].baudrate;
197 priv->media_active_last =
198 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
201 if_link_state_change(priv->ifp, LINK_STATE_UP);
205 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
207 struct mlx5e_priv *priv = dev->if_softc;
209 ifmr->ifm_status = priv->media_status_last;
210 ifmr->ifm_active = priv->media_active_last |
211 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
212 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
217 mlx5e_find_link_mode(u32 subtype)
222 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
223 if (mlx5e_mode_table[i].baudrate == 0)
225 if (mlx5e_mode_table[i].subtype == subtype)
226 link_mode |= MLX5E_PROT_MASK(i);
233 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
235 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
236 priv->params.rx_pauseframe_control,
237 priv->params.tx_pauseframe_control,
238 priv->params.rx_priority_flow_control,
239 priv->params.tx_priority_flow_control));
243 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
247 if (priv->params.rx_pauseframe_control ||
248 priv->params.tx_pauseframe_control) {
250 "Global pauseframes must be disabled before enabling PFC.\n");
253 error = mlx5e_set_port_pause_and_pfc(priv);
259 mlx5e_media_change(struct ifnet *dev)
261 struct mlx5e_priv *priv = dev->if_softc;
262 struct mlx5_core_dev *mdev = priv->mdev;
269 locked = PRIV_LOCKED(priv);
273 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
277 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
279 /* query supported capabilities */
280 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
282 if_printf(dev, "Query port media capability failed\n");
285 /* check for autoselect */
286 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
287 link_mode = eth_proto_cap;
288 if (link_mode == 0) {
289 if_printf(dev, "Port media capability is zero\n");
294 link_mode = link_mode & eth_proto_cap;
295 if (link_mode == 0) {
296 if_printf(dev, "Not supported link mode requested\n");
301 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
302 /* check if PFC is enabled */
303 if (priv->params.rx_priority_flow_control ||
304 priv->params.tx_priority_flow_control) {
305 if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
310 /* update pauseframe control bits */
311 priv->params.rx_pauseframe_control =
312 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
313 priv->params.tx_pauseframe_control =
314 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
316 /* check if device is opened */
317 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
319 /* reconfigure the hardware */
320 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
321 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
322 error = -mlx5e_set_port_pause_and_pfc(priv);
324 mlx5_set_port_status(mdev, MLX5_PORT_UP);
333 mlx5e_update_carrier_work(struct work_struct *work)
335 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
336 update_carrier_work);
339 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
340 mlx5e_update_carrier(priv);
345 * This function reads the physical port counters from the firmware
346 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
347 * macros. The output is converted from big-endian 64-bit values into
348 * host endian ones and stored in the "priv->stats.pport" structure.
351 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
353 struct mlx5_core_dev *mdev = priv->mdev;
354 struct mlx5e_pport_stats *s = &priv->stats.pport;
355 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
359 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
364 /* allocate firmware request structures */
365 in = mlx5_vzalloc(sz);
366 out = mlx5_vzalloc(sz);
367 if (in == NULL || out == NULL)
371 * Get pointer to the 64-bit counter set which is located at a
372 * fixed offset in the output firmware request structure:
374 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
376 MLX5_SET(ppcnt_reg, in, local_port, 1);
378 /* read IEEE802_3 counter group using predefined counter layout */
379 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
380 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
381 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
382 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
383 s->arg[y] = be64toh(ptr[x]);
385 /* read RFC2819 counter group using predefined counter layout */
386 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
387 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
388 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
389 s->arg[y] = be64toh(ptr[x]);
390 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
391 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
392 s_debug->arg[y] = be64toh(ptr[x]);
394 /* read RFC2863 counter group using predefined counter layout */
395 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
396 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
397 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
398 s_debug->arg[y] = be64toh(ptr[x]);
400 /* read physical layer stats counter group using predefined counter layout */
401 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
402 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
403 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
404 s_debug->arg[y] = be64toh(ptr[x]);
406 /* read per-priority counters */
407 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
409 /* iterate all the priorities */
410 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
411 MLX5_SET(ppcnt_reg, in, prio_tc, z);
412 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
414 /* read per priority stats counter group using predefined counter layout */
415 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
416 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
417 s->arg[y] = be64toh(ptr[x]);
420 /* free firmware request structures */
426 * This function is called regularly to collect all statistics
427 * counters from the firmware. The values can be viewed through the
428 * sysctl interface. Execution is serialized using the priv's global
429 * configuration lock.
432 mlx5e_update_stats_work(struct work_struct *work)
434 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
436 struct mlx5_core_dev *mdev = priv->mdev;
437 struct mlx5e_vport_stats *s = &priv->stats.vport;
438 struct mlx5e_rq_stats *rq_stats;
439 struct mlx5e_sq_stats *sq_stats;
440 struct buf_ring *sq_br;
441 #if (__FreeBSD_version < 1100000)
442 struct ifnet *ifp = priv->ifp;
445 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
447 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
450 u64 tx_queue_dropped = 0;
451 u64 tx_defragged = 0;
452 u64 tx_offload_none = 0;
455 u64 sw_lro_queued = 0;
456 u64 sw_lro_flushed = 0;
457 u64 rx_csum_none = 0;
459 u32 rx_out_of_buffer = 0;
464 out = mlx5_vzalloc(outlen);
467 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
470 /* Collect firts the SW counters and then HW for consistency */
471 for (i = 0; i < priv->params.num_channels; i++) {
472 struct mlx5e_rq *rq = &priv->channel[i]->rq;
474 rq_stats = &priv->channel[i]->rq.stats;
476 /* collect stats from LRO */
477 rq_stats->sw_lro_queued = rq->lro.lro_queued;
478 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
479 sw_lro_queued += rq_stats->sw_lro_queued;
480 sw_lro_flushed += rq_stats->sw_lro_flushed;
481 lro_packets += rq_stats->lro_packets;
482 lro_bytes += rq_stats->lro_bytes;
483 rx_csum_none += rq_stats->csum_none;
484 rx_wqe_err += rq_stats->wqe_err;
486 for (j = 0; j < priv->num_tc; j++) {
487 sq_stats = &priv->channel[i]->sq[j].stats;
488 sq_br = priv->channel[i]->sq[j].br;
490 tso_packets += sq_stats->tso_packets;
491 tso_bytes += sq_stats->tso_bytes;
492 tx_queue_dropped += sq_stats->dropped;
494 tx_queue_dropped += sq_br->br_drops;
495 tx_defragged += sq_stats->defragged;
496 tx_offload_none += sq_stats->csum_offload_none;
500 /* update counters */
501 s->tso_packets = tso_packets;
502 s->tso_bytes = tso_bytes;
503 s->tx_queue_dropped = tx_queue_dropped;
504 s->tx_defragged = tx_defragged;
505 s->lro_packets = lro_packets;
506 s->lro_bytes = lro_bytes;
507 s->sw_lro_queued = sw_lro_queued;
508 s->sw_lro_flushed = sw_lro_flushed;
509 s->rx_csum_none = rx_csum_none;
510 s->rx_wqe_err = rx_wqe_err;
513 memset(in, 0, sizeof(in));
515 MLX5_SET(query_vport_counter_in, in, opcode,
516 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
517 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
518 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
520 memset(out, 0, outlen);
522 /* get number of out-of-buffer drops first */
523 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
527 /* accumulate difference into a 64-bit counter */
528 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
529 s->rx_out_of_buffer_prev = rx_out_of_buffer;
531 /* get port statistics */
532 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
535 #define MLX5_GET_CTR(out, x) \
536 MLX5_GET64(query_vport_counter_out, out, x)
538 s->rx_error_packets =
539 MLX5_GET_CTR(out, received_errors.packets);
541 MLX5_GET_CTR(out, received_errors.octets);
542 s->tx_error_packets =
543 MLX5_GET_CTR(out, transmit_errors.packets);
545 MLX5_GET_CTR(out, transmit_errors.octets);
547 s->rx_unicast_packets =
548 MLX5_GET_CTR(out, received_eth_unicast.packets);
549 s->rx_unicast_bytes =
550 MLX5_GET_CTR(out, received_eth_unicast.octets);
551 s->tx_unicast_packets =
552 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
553 s->tx_unicast_bytes =
554 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
556 s->rx_multicast_packets =
557 MLX5_GET_CTR(out, received_eth_multicast.packets);
558 s->rx_multicast_bytes =
559 MLX5_GET_CTR(out, received_eth_multicast.octets);
560 s->tx_multicast_packets =
561 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
562 s->tx_multicast_bytes =
563 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
565 s->rx_broadcast_packets =
566 MLX5_GET_CTR(out, received_eth_broadcast.packets);
567 s->rx_broadcast_bytes =
568 MLX5_GET_CTR(out, received_eth_broadcast.octets);
569 s->tx_broadcast_packets =
570 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
571 s->tx_broadcast_bytes =
572 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
575 s->rx_unicast_packets +
576 s->rx_multicast_packets +
577 s->rx_broadcast_packets -
580 s->rx_unicast_bytes +
581 s->rx_multicast_bytes +
582 s->rx_broadcast_bytes;
584 s->tx_unicast_packets +
585 s->tx_multicast_packets +
586 s->tx_broadcast_packets;
588 s->tx_unicast_bytes +
589 s->tx_multicast_bytes +
590 s->tx_broadcast_bytes;
592 /* Update calculated offload counters */
593 s->tx_csum_offload = s->tx_packets - tx_offload_none;
594 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
596 /* Get physical port counters */
597 mlx5e_update_pport_counters(priv);
599 #if (__FreeBSD_version < 1100000)
600 /* no get_counters interface in fbsd 10 */
601 ifp->if_ipackets = s->rx_packets;
602 ifp->if_ierrors = s->rx_error_packets +
603 priv->stats.pport.alignment_err +
604 priv->stats.pport.check_seq_err +
605 priv->stats.pport.crc_align_errors +
606 priv->stats.pport.in_range_len_errors +
607 priv->stats.pport.jabbers +
608 priv->stats.pport.out_of_range_len +
609 priv->stats.pport.oversize_pkts +
610 priv->stats.pport.symbol_err +
611 priv->stats.pport.too_long_errors +
612 priv->stats.pport.undersize_pkts +
613 priv->stats.pport.unsupported_op_rx;
614 ifp->if_iqdrops = s->rx_out_of_buffer +
615 priv->stats.pport.drop_events;
616 ifp->if_opackets = s->tx_packets;
617 ifp->if_oerrors = s->tx_error_packets;
618 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
619 ifp->if_ibytes = s->rx_bytes;
620 ifp->if_obytes = s->tx_bytes;
622 priv->stats.pport.collisions;
628 /* Update diagnostics, if any */
629 if (priv->params_ethtool.diag_pci_enable ||
630 priv->params_ethtool.diag_general_enable) {
631 int error = mlx5_core_get_diagnostics_full(mdev,
632 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
633 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
635 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
641 mlx5e_update_stats(void *arg)
643 struct mlx5e_priv *priv = arg;
645 queue_work(priv->wq, &priv->update_stats_work);
647 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
651 mlx5e_async_event_sub(struct mlx5e_priv *priv,
652 enum mlx5_dev_event event)
655 case MLX5_DEV_EVENT_PORT_UP:
656 case MLX5_DEV_EVENT_PORT_DOWN:
657 queue_work(priv->wq, &priv->update_carrier_work);
666 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
667 enum mlx5_dev_event event, unsigned long param)
669 struct mlx5e_priv *priv = vpriv;
671 mtx_lock(&priv->async_events_mtx);
672 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
673 mlx5e_async_event_sub(priv, event);
674 mtx_unlock(&priv->async_events_mtx);
678 mlx5e_enable_async_events(struct mlx5e_priv *priv)
680 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
684 mlx5e_disable_async_events(struct mlx5e_priv *priv)
686 mtx_lock(&priv->async_events_mtx);
687 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
688 mtx_unlock(&priv->async_events_mtx);
691 static void mlx5e_calibration_callout(void *arg);
692 static int mlx5e_calibration_duration = 20;
693 static int mlx5e_fast_calibration = 1;
694 static int mlx5e_normal_calibration = 30;
696 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
697 "MLX5 timestamp calibration parameteres");
699 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
700 &mlx5e_calibration_duration, 0,
701 "Duration of initial calibration");
702 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
703 &mlx5e_fast_calibration, 0,
704 "Recalibration interval during initial calibration");
705 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
706 &mlx5e_normal_calibration, 0,
707 "Recalibration interval during normal operations");
710 * Ignites the calibration process.
713 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
716 if (priv->clbr_done == 0)
717 mlx5e_calibration_callout(priv);
719 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
720 mlx5e_calibration_duration ? mlx5e_fast_calibration :
721 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
726 mlx5e_timespec2usec(const struct timespec *ts)
729 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
733 mlx5e_hw_clock(struct mlx5e_priv *priv)
735 struct mlx5_init_seg *iseg;
736 uint32_t hw_h, hw_h1, hw_l;
738 iseg = priv->mdev->iseg;
740 hw_h = ioread32be(&iseg->internal_timer_h);
741 hw_l = ioread32be(&iseg->internal_timer_l);
742 hw_h1 = ioread32be(&iseg->internal_timer_h);
743 } while (hw_h1 != hw_h);
744 return (((uint64_t)hw_h << 32) | hw_l);
748 * The calibration callout, it runs either in the context of the
749 * thread which enables calibration, or in callout. It takes the
750 * snapshot of system and adapter clocks, then advances the pointers to
751 * the calibration point to allow rx path to read the consistent data
755 mlx5e_calibration_callout(void *arg)
757 struct mlx5e_priv *priv;
758 struct mlx5e_clbr_point *next, *curr;
763 curr = &priv->clbr_points[priv->clbr_curr];
764 clbr_curr_next = priv->clbr_curr + 1;
765 if (clbr_curr_next >= nitems(priv->clbr_points))
767 next = &priv->clbr_points[clbr_curr_next];
769 next->base_prev = curr->base_curr;
770 next->clbr_hw_prev = curr->clbr_hw_curr;
772 next->clbr_hw_curr = mlx5e_hw_clock(priv);
773 if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
775 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
776 "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
782 next->base_curr = mlx5e_timespec2usec(&ts);
785 atomic_thread_fence_rel();
786 priv->clbr_curr = clbr_curr_next;
787 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
789 if (priv->clbr_done < mlx5e_calibration_duration)
791 mlx5e_reset_calibration_callout(priv);
794 static const char *mlx5e_rq_stats_desc[] = {
795 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
799 mlx5e_create_rq(struct mlx5e_channel *c,
800 struct mlx5e_rq_param *param,
803 struct mlx5e_priv *priv = c->priv;
804 struct mlx5_core_dev *mdev = priv->mdev;
806 void *rqc = param->rqc;
807 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
812 /* Create DMA descriptor TAG */
813 if ((err = -bus_dma_tag_create(
814 bus_get_dma_tag(mdev->pdev->dev.bsddev),
815 1, /* any alignment */
817 BUS_SPACE_MAXADDR, /* lowaddr */
818 BUS_SPACE_MAXADDR, /* highaddr */
819 NULL, NULL, /* filter, filterarg */
820 MJUM16BYTES, /* maxsize */
822 MJUM16BYTES, /* maxsegsize */
824 NULL, NULL, /* lockfunc, lockfuncarg */
828 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
831 goto err_free_dma_tag;
833 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
835 if (priv->params.hw_lro_en) {
836 rq->wqe_sz = priv->params.lro_wqe_sz;
838 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
840 if (rq->wqe_sz > MJUM16BYTES) {
842 goto err_rq_wq_destroy;
843 } else if (rq->wqe_sz > MJUM9BYTES) {
844 rq->wqe_sz = MJUM16BYTES;
845 } else if (rq->wqe_sz > MJUMPAGESIZE) {
846 rq->wqe_sz = MJUM9BYTES;
847 } else if (rq->wqe_sz > MCLBYTES) {
848 rq->wqe_sz = MJUMPAGESIZE;
850 rq->wqe_sz = MCLBYTES;
853 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
855 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
857 goto err_rq_wq_destroy;
859 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
860 for (i = 0; i != wq_sz; i++) {
861 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
862 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
864 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
867 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
868 goto err_rq_mbuf_free;
870 wqe->data.lkey = c->mkey_be;
871 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
878 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
879 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
880 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
885 free(rq->mbuf, M_MLX5EN);
886 tcp_lro_free(&rq->lro);
888 mlx5_wq_destroy(&rq->wq_ctrl);
890 bus_dma_tag_destroy(rq->dma_tag);
896 mlx5e_destroy_rq(struct mlx5e_rq *rq)
901 /* destroy all sysctl nodes */
902 sysctl_ctx_free(&rq->stats.ctx);
904 /* free leftover LRO packets, if any */
905 tcp_lro_free(&rq->lro);
907 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
908 for (i = 0; i != wq_sz; i++) {
909 if (rq->mbuf[i].mbuf != NULL) {
910 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
911 m_freem(rq->mbuf[i].mbuf);
913 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
915 free(rq->mbuf, M_MLX5EN);
916 mlx5_wq_destroy(&rq->wq_ctrl);
920 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
922 struct mlx5e_channel *c = rq->channel;
923 struct mlx5e_priv *priv = c->priv;
924 struct mlx5_core_dev *mdev = priv->mdev;
932 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
933 sizeof(u64) * rq->wq_ctrl.buf.npages;
934 in = mlx5_vzalloc(inlen);
938 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
939 wq = MLX5_ADDR_OF(rqc, rqc, wq);
941 memcpy(rqc, param->rqc, sizeof(param->rqc));
943 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
944 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
945 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
946 if (priv->counter_set_id >= 0)
947 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
948 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
950 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
952 mlx5_fill_page_array(&rq->wq_ctrl.buf,
953 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
955 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
963 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
965 struct mlx5e_channel *c = rq->channel;
966 struct mlx5e_priv *priv = c->priv;
967 struct mlx5_core_dev *mdev = priv->mdev;
974 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
975 in = mlx5_vzalloc(inlen);
979 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
981 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
982 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
983 MLX5_SET(rqc, rqc, state, next_state);
985 err = mlx5_core_modify_rq(mdev, in, inlen);
993 mlx5e_disable_rq(struct mlx5e_rq *rq)
995 struct mlx5e_channel *c = rq->channel;
996 struct mlx5e_priv *priv = c->priv;
997 struct mlx5_core_dev *mdev = priv->mdev;
999 mlx5_core_destroy_rq(mdev, rq->rqn);
1003 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1005 struct mlx5e_channel *c = rq->channel;
1006 struct mlx5e_priv *priv = c->priv;
1007 struct mlx5_wq_ll *wq = &rq->wq;
1010 for (i = 0; i < 1000; i++) {
1011 if (wq->cur_sz >= priv->params.min_rx_wqes)
1016 return (-ETIMEDOUT);
1020 mlx5e_open_rq(struct mlx5e_channel *c,
1021 struct mlx5e_rq_param *param,
1022 struct mlx5e_rq *rq)
1026 err = mlx5e_create_rq(c, param, rq);
1030 err = mlx5e_enable_rq(rq, param);
1032 goto err_destroy_rq;
1034 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1036 goto err_disable_rq;
1043 mlx5e_disable_rq(rq);
1045 mlx5e_destroy_rq(rq);
1051 mlx5e_close_rq(struct mlx5e_rq *rq)
1055 callout_stop(&rq->watchdog);
1056 mtx_unlock(&rq->mtx);
1058 callout_drain(&rq->watchdog);
1060 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1064 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1066 struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1068 /* wait till RQ is empty */
1069 while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1070 (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1072 rq->cq.mcq.comp(&rq->cq.mcq);
1075 mlx5e_disable_rq(rq);
1076 mlx5e_destroy_rq(rq);
1080 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1082 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1085 for (x = 0; x != wq_sz; x++)
1086 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1087 free(sq->mbuf, M_MLX5EN);
1091 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1093 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1097 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1099 /* Create DMA descriptor MAPs */
1100 for (x = 0; x != wq_sz; x++) {
1101 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1104 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1105 free(sq->mbuf, M_MLX5EN);
1112 static const char *mlx5e_sq_stats_desc[] = {
1113 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1117 mlx5e_create_sq(struct mlx5e_channel *c,
1119 struct mlx5e_sq_param *param,
1120 struct mlx5e_sq *sq)
1122 struct mlx5e_priv *priv = c->priv;
1123 struct mlx5_core_dev *mdev = priv->mdev;
1126 void *sqc = param->sqc;
1127 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1134 /* Create DMA descriptor TAG */
1135 if ((err = -bus_dma_tag_create(
1136 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1137 1, /* any alignment */
1138 0, /* no boundary */
1139 BUS_SPACE_MAXADDR, /* lowaddr */
1140 BUS_SPACE_MAXADDR, /* highaddr */
1141 NULL, NULL, /* filter, filterarg */
1142 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1143 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1144 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1146 NULL, NULL, /* lockfunc, lockfuncarg */
1150 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1152 goto err_free_dma_tag;
1154 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1157 goto err_unmap_free_uar;
1159 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1160 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1162 err = mlx5e_alloc_sq_db(sq);
1164 goto err_sq_wq_destroy;
1166 sq->mkey_be = c->mkey_be;
1167 sq->ifp = priv->ifp;
1171 /* check if we should allocate a second packet buffer */
1172 if (priv->params_ethtool.tx_bufring_disable == 0) {
1173 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1174 M_WAITOK, &sq->lock);
1175 if (sq->br == NULL) {
1176 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1179 goto err_free_sq_db;
1182 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1183 taskqueue_thread_enqueue, &sq->sq_tq);
1184 if (sq->sq_tq == NULL) {
1185 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1191 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1193 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1194 CPU_SETOF(cpu_id, &cpu_mask);
1195 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1196 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1198 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1199 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1202 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1203 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1204 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1210 buf_ring_free(sq->br, M_MLX5EN);
1212 mlx5e_free_sq_db(sq);
1214 mlx5_wq_destroy(&sq->wq_ctrl);
1217 mlx5_unmap_free_uar(mdev, &sq->uar);
1220 bus_dma_tag_destroy(sq->dma_tag);
1226 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1228 /* destroy all sysctl nodes */
1229 sysctl_ctx_free(&sq->stats.ctx);
1231 mlx5e_free_sq_db(sq);
1232 mlx5_wq_destroy(&sq->wq_ctrl);
1233 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1234 if (sq->sq_tq != NULL) {
1235 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1236 taskqueue_free(sq->sq_tq);
1239 buf_ring_free(sq->br, M_MLX5EN);
1243 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1252 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1253 sizeof(u64) * sq->wq_ctrl.buf.npages;
1254 in = mlx5_vzalloc(inlen);
1258 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1259 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1261 memcpy(sqc, param->sqc, sizeof(param->sqc));
1263 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1264 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1265 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1266 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1267 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1269 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1270 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1271 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1273 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1275 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1276 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1278 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1286 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1293 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1294 in = mlx5_vzalloc(inlen);
1298 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1300 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1301 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1302 MLX5_SET(sqc, sqc, state, next_state);
1304 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1312 mlx5e_disable_sq(struct mlx5e_sq *sq)
1315 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1319 mlx5e_open_sq(struct mlx5e_channel *c,
1321 struct mlx5e_sq_param *param,
1322 struct mlx5e_sq *sq)
1326 err = mlx5e_create_sq(c, tc, param, sq);
1330 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1332 goto err_destroy_sq;
1334 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1336 goto err_disable_sq;
1338 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1343 mlx5e_disable_sq(sq);
1345 mlx5e_destroy_sq(sq);
1351 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1353 /* fill up remainder with NOPs */
1354 while (sq->cev_counter != 0) {
1355 while (!mlx5e_sq_has_room_for(sq, 1)) {
1356 if (can_sleep != 0) {
1357 mtx_unlock(&sq->lock);
1359 mtx_lock(&sq->lock);
1364 /* send a single NOP */
1365 mlx5e_send_nop(sq, 1);
1366 atomic_thread_fence_rel();
1369 /* Check if we need to write the doorbell */
1370 if (likely(sq->doorbell.d64 != 0)) {
1371 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1372 sq->doorbell.d64 = 0;
1377 mlx5e_sq_cev_timeout(void *arg)
1379 struct mlx5e_sq *sq = arg;
1381 mtx_assert(&sq->lock, MA_OWNED);
1383 /* check next state */
1384 switch (sq->cev_next_state) {
1385 case MLX5E_CEV_STATE_SEND_NOPS:
1386 /* fill TX ring with NOPs, if any */
1387 mlx5e_sq_send_nops_locked(sq, 0);
1389 /* check if completed */
1390 if (sq->cev_counter == 0) {
1391 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1396 /* send NOPs on next timeout */
1397 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1402 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1406 mlx5e_drain_sq(struct mlx5e_sq *sq)
1409 struct mlx5_core_dev *mdev= sq->priv->mdev;
1412 * Check if already stopped.
1414 * NOTE: The "stopped" variable is only written when both the
1415 * priv's configuration lock and the SQ's lock is locked. It
1416 * can therefore safely be read when only one of the two locks
1417 * is locked. This function is always called when the priv's
1418 * configuration lock is locked.
1420 if (sq->stopped != 0)
1423 mtx_lock(&sq->lock);
1425 /* don't put more packets into the SQ */
1428 /* teardown event factor timer, if any */
1429 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1430 callout_stop(&sq->cev_callout);
1432 /* send dummy NOPs in order to flush the transmit ring */
1433 mlx5e_sq_send_nops_locked(sq, 1);
1434 mtx_unlock(&sq->lock);
1436 /* make sure it is safe to free the callout */
1437 callout_drain(&sq->cev_callout);
1439 /* wait till SQ is empty or link is down */
1440 mtx_lock(&sq->lock);
1441 while (sq->cc != sq->pc &&
1442 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1443 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1444 mtx_unlock(&sq->lock);
1446 sq->cq.mcq.comp(&sq->cq.mcq);
1447 mtx_lock(&sq->lock);
1449 mtx_unlock(&sq->lock);
1451 /* error out remaining requests */
1452 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1455 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1458 /* wait till SQ is empty */
1459 mtx_lock(&sq->lock);
1460 while (sq->cc != sq->pc &&
1461 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1462 mtx_unlock(&sq->lock);
1464 sq->cq.mcq.comp(&sq->cq.mcq);
1465 mtx_lock(&sq->lock);
1467 mtx_unlock(&sq->lock);
1471 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1475 mlx5e_disable_sq(sq);
1476 mlx5e_destroy_sq(sq);
1480 mlx5e_create_cq(struct mlx5e_priv *priv,
1481 struct mlx5e_cq_param *param,
1482 struct mlx5e_cq *cq,
1483 mlx5e_cq_comp_t *comp,
1486 struct mlx5_core_dev *mdev = priv->mdev;
1487 struct mlx5_core_cq *mcq = &cq->mcq;
1493 param->wq.buf_numa_node = 0;
1494 param->wq.db_numa_node = 0;
1496 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1501 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1504 mcq->set_ci_db = cq->wq_ctrl.db.db;
1505 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1506 *mcq->set_ci_db = 0;
1508 mcq->vector = eq_ix;
1510 mcq->event = mlx5e_cq_error_event;
1512 mcq->uar = &priv->cq_uar;
1514 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1515 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1526 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1528 mlx5_wq_destroy(&cq->wq_ctrl);
1532 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1534 struct mlx5_core_cq *mcq = &cq->mcq;
1542 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1543 sizeof(u64) * cq->wq_ctrl.buf.npages;
1544 in = mlx5_vzalloc(inlen);
1548 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1550 memcpy(cqc, param->cqc, sizeof(param->cqc));
1552 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1553 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1555 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1557 MLX5_SET(cqc, cqc, c_eqn, eqn);
1558 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1559 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1561 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1563 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1570 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1576 mlx5e_disable_cq(struct mlx5e_cq *cq)
1579 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1583 mlx5e_open_cq(struct mlx5e_priv *priv,
1584 struct mlx5e_cq_param *param,
1585 struct mlx5e_cq *cq,
1586 mlx5e_cq_comp_t *comp,
1591 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1595 err = mlx5e_enable_cq(cq, param, eq_ix);
1597 goto err_destroy_cq;
1602 mlx5e_destroy_cq(cq);
1608 mlx5e_close_cq(struct mlx5e_cq *cq)
1610 mlx5e_disable_cq(cq);
1611 mlx5e_destroy_cq(cq);
1615 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1616 struct mlx5e_channel_param *cparam)
1621 for (tc = 0; tc < c->num_tc; tc++) {
1622 /* open completion queue */
1623 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1624 &mlx5e_tx_cq_comp, c->ix);
1626 goto err_close_tx_cqs;
1631 for (tc--; tc >= 0; tc--)
1632 mlx5e_close_cq(&c->sq[tc].cq);
1638 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1642 for (tc = 0; tc < c->num_tc; tc++)
1643 mlx5e_close_cq(&c->sq[tc].cq);
1647 mlx5e_open_sqs(struct mlx5e_channel *c,
1648 struct mlx5e_channel_param *cparam)
1653 for (tc = 0; tc < c->num_tc; tc++) {
1654 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1662 for (tc--; tc >= 0; tc--)
1663 mlx5e_close_sq_wait(&c->sq[tc]);
1669 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1673 for (tc = 0; tc < c->num_tc; tc++)
1674 mlx5e_close_sq_wait(&c->sq[tc]);
1678 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1682 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1684 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1686 for (tc = 0; tc < c->num_tc; tc++) {
1687 struct mlx5e_sq *sq = c->sq + tc;
1689 mtx_init(&sq->lock, "mlx5tx",
1690 MTX_NETWORK_LOCK " TX", MTX_DEF);
1691 mtx_init(&sq->comp_lock, "mlx5comp",
1692 MTX_NETWORK_LOCK " TX", MTX_DEF);
1694 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1696 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1698 /* ensure the TX completion event factor is not zero */
1699 if (sq->cev_factor == 0)
1705 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1709 mtx_destroy(&c->rq.mtx);
1711 for (tc = 0; tc < c->num_tc; tc++) {
1712 mtx_destroy(&c->sq[tc].lock);
1713 mtx_destroy(&c->sq[tc].comp_lock);
1718 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1719 struct mlx5e_channel_param *cparam,
1720 struct mlx5e_channel *volatile *cp)
1722 struct mlx5e_channel *c;
1725 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1730 c->mkey_be = cpu_to_be32(priv->mr.key);
1731 c->num_tc = priv->num_tc;
1734 mlx5e_chan_mtx_init(c);
1736 /* open transmit completion queue */
1737 err = mlx5e_open_tx_cqs(c, cparam);
1741 /* open receive completion queue */
1742 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1743 &mlx5e_rx_cq_comp, c->ix);
1745 goto err_close_tx_cqs;
1747 err = mlx5e_open_sqs(c, cparam);
1749 goto err_close_rx_cq;
1751 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1755 /* store channel pointer */
1758 /* poll receive queue initially */
1759 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1764 mlx5e_close_sqs_wait(c);
1767 mlx5e_close_cq(&c->rq.cq);
1770 mlx5e_close_tx_cqs(c);
1773 /* destroy mutexes */
1774 mlx5e_chan_mtx_destroy(c);
1780 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1782 struct mlx5e_channel *c = *pp;
1784 /* check if channel is already closed */
1787 mlx5e_close_rq(&c->rq);
1791 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1793 struct mlx5e_channel *c = *pp;
1795 /* check if channel is already closed */
1798 /* ensure channel pointer is no longer used */
1801 mlx5e_close_rq_wait(&c->rq);
1802 mlx5e_close_sqs_wait(c);
1803 mlx5e_close_cq(&c->rq.cq);
1804 mlx5e_close_tx_cqs(c);
1805 /* destroy mutexes */
1806 mlx5e_chan_mtx_destroy(c);
1811 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1812 struct mlx5e_rq_param *param)
1814 void *rqc = param->rqc;
1815 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1817 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1818 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1819 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1820 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1821 MLX5_SET(wq, wq, pd, priv->pdn);
1823 param->wq.buf_numa_node = 0;
1824 param->wq.db_numa_node = 0;
1825 param->wq.linear = 1;
1829 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1830 struct mlx5e_sq_param *param)
1832 void *sqc = param->sqc;
1833 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1835 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1836 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1837 MLX5_SET(wq, wq, pd, priv->pdn);
1839 param->wq.buf_numa_node = 0;
1840 param->wq.db_numa_node = 0;
1841 param->wq.linear = 1;
1845 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1846 struct mlx5e_cq_param *param)
1848 void *cqc = param->cqc;
1850 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1854 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1855 struct mlx5e_cq_param *param)
1857 void *cqc = param->cqc;
1861 * TODO The sysctl to control on/off is a bool value for now, which means
1862 * we only support CSUM, once HASH is implemnted we'll need to address that.
1864 if (priv->params.cqe_zipping_en) {
1865 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1866 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1869 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1870 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1871 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1873 switch (priv->params.rx_cq_moderation_mode) {
1875 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1878 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1879 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1881 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1885 mlx5e_build_common_cq_param(priv, param);
1889 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1890 struct mlx5e_cq_param *param)
1892 void *cqc = param->cqc;
1894 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1895 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1896 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1898 switch (priv->params.tx_cq_moderation_mode) {
1900 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1903 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1904 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1906 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1910 mlx5e_build_common_cq_param(priv, param);
1914 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1915 struct mlx5e_channel_param *cparam)
1917 memset(cparam, 0, sizeof(*cparam));
1919 mlx5e_build_rq_param(priv, &cparam->rq);
1920 mlx5e_build_sq_param(priv, &cparam->sq);
1921 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1922 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1926 mlx5e_open_channels(struct mlx5e_priv *priv)
1928 struct mlx5e_channel_param cparam;
1934 priv->channel = malloc(priv->params.num_channels *
1935 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1937 mlx5e_build_channel_param(priv, &cparam);
1938 for (i = 0; i < priv->params.num_channels; i++) {
1939 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1941 goto err_close_channels;
1944 for (j = 0; j < priv->params.num_channels; j++) {
1945 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1947 goto err_close_channels;
1953 for (i--; i >= 0; i--) {
1954 mlx5e_close_channel(&priv->channel[i]);
1955 mlx5e_close_channel_wait(&priv->channel[i]);
1958 /* remove "volatile" attribute from "channel" pointer */
1959 ptr = __DECONST(void *, priv->channel);
1960 priv->channel = NULL;
1962 free(ptr, M_MLX5EN);
1968 mlx5e_close_channels(struct mlx5e_priv *priv)
1973 if (priv->channel == NULL)
1976 for (i = 0; i < priv->params.num_channels; i++)
1977 mlx5e_close_channel(&priv->channel[i]);
1978 for (i = 0; i < priv->params.num_channels; i++)
1979 mlx5e_close_channel_wait(&priv->channel[i]);
1981 /* remove "volatile" attribute from "channel" pointer */
1982 ptr = __DECONST(void *, priv->channel);
1983 priv->channel = NULL;
1985 free(ptr, M_MLX5EN);
1989 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1992 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1995 switch (priv->params.tx_cq_moderation_mode) {
1997 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2000 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2004 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2005 priv->params.tx_cq_moderation_usec,
2006 priv->params.tx_cq_moderation_pkts,
2010 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2011 priv->params.tx_cq_moderation_usec,
2012 priv->params.tx_cq_moderation_pkts));
2016 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2019 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2023 switch (priv->params.rx_cq_moderation_mode) {
2025 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2028 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2032 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2033 priv->params.rx_cq_moderation_usec,
2034 priv->params.rx_cq_moderation_pkts,
2040 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2041 priv->params.rx_cq_moderation_usec,
2042 priv->params.rx_cq_moderation_pkts));
2046 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2054 err = mlx5e_refresh_rq_params(priv, &c->rq);
2058 for (i = 0; i != c->num_tc; i++) {
2059 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2068 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2072 if (priv->channel == NULL)
2075 for (i = 0; i < priv->params.num_channels; i++) {
2078 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
2086 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2088 struct mlx5_core_dev *mdev = priv->mdev;
2089 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2090 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2092 memset(in, 0, sizeof(in));
2094 MLX5_SET(tisc, tisc, prio, tc);
2095 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2097 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2101 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2103 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2107 mlx5e_open_tises(struct mlx5e_priv *priv)
2109 int num_tc = priv->num_tc;
2113 for (tc = 0; tc < num_tc; tc++) {
2114 err = mlx5e_open_tis(priv, tc);
2116 goto err_close_tises;
2122 for (tc--; tc >= 0; tc--)
2123 mlx5e_close_tis(priv, tc);
2129 mlx5e_close_tises(struct mlx5e_priv *priv)
2131 int num_tc = priv->num_tc;
2134 for (tc = 0; tc < num_tc; tc++)
2135 mlx5e_close_tis(priv, tc);
2139 mlx5e_open_rqt(struct mlx5e_priv *priv)
2141 struct mlx5_core_dev *mdev = priv->mdev;
2143 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2150 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2152 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2153 in = mlx5_vzalloc(inlen);
2156 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2158 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2159 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2161 for (i = 0; i < sz; i++) {
2164 ix = rss_get_indirection_to_bucket(i);
2168 /* ensure we don't overflow */
2169 ix %= priv->params.num_channels;
2170 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2173 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2175 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2177 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2185 mlx5e_close_rqt(struct mlx5e_priv *priv)
2187 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2188 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2190 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2191 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2193 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2197 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2199 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2202 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2204 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2206 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2207 MLX5_HASH_FIELD_SEL_DST_IP)
2209 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2210 MLX5_HASH_FIELD_SEL_DST_IP |\
2211 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2212 MLX5_HASH_FIELD_SEL_L4_DPORT)
2214 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2215 MLX5_HASH_FIELD_SEL_DST_IP |\
2216 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2218 if (priv->params.hw_lro_en) {
2219 MLX5_SET(tirc, tirc, lro_enable_mask,
2220 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2221 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2222 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2223 (priv->params.lro_wqe_sz -
2224 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2225 /* TODO: add the option to choose timer value dynamically */
2226 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2227 MLX5_CAP_ETH(priv->mdev,
2228 lro_timer_supported_periods[2]));
2231 /* setup parameters for hashing TIR type, if any */
2234 MLX5_SET(tirc, tirc, disp_type,
2235 MLX5_TIRC_DISP_TYPE_DIRECT);
2236 MLX5_SET(tirc, tirc, inline_rqn,
2237 priv->channel[0]->rq.rqn);
2240 MLX5_SET(tirc, tirc, disp_type,
2241 MLX5_TIRC_DISP_TYPE_INDIRECT);
2242 MLX5_SET(tirc, tirc, indirect_table,
2244 MLX5_SET(tirc, tirc, rx_hash_fn,
2245 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2246 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2249 * The FreeBSD RSS implementation does currently not
2250 * support symmetric Toeplitz hashes:
2252 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2253 rss_getkey((uint8_t *)hkey);
2255 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2256 hkey[0] = cpu_to_be32(0xD181C62C);
2257 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2258 hkey[2] = cpu_to_be32(0x1983A2FC);
2259 hkey[3] = cpu_to_be32(0x943E1ADB);
2260 hkey[4] = cpu_to_be32(0xD9389E6B);
2261 hkey[5] = cpu_to_be32(0xD1039C2C);
2262 hkey[6] = cpu_to_be32(0xA74499AD);
2263 hkey[7] = cpu_to_be32(0x593D56D9);
2264 hkey[8] = cpu_to_be32(0xF3253C06);
2265 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2271 case MLX5E_TT_IPV4_TCP:
2272 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2273 MLX5_L3_PROT_TYPE_IPV4);
2274 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2275 MLX5_L4_PROT_TYPE_TCP);
2277 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2278 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2282 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2286 case MLX5E_TT_IPV6_TCP:
2287 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2288 MLX5_L3_PROT_TYPE_IPV6);
2289 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2290 MLX5_L4_PROT_TYPE_TCP);
2292 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2293 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2297 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301 case MLX5E_TT_IPV4_UDP:
2302 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2303 MLX5_L3_PROT_TYPE_IPV4);
2304 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2305 MLX5_L4_PROT_TYPE_UDP);
2307 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2308 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2312 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2316 case MLX5E_TT_IPV6_UDP:
2317 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2318 MLX5_L3_PROT_TYPE_IPV6);
2319 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2320 MLX5_L4_PROT_TYPE_UDP);
2322 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2323 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2327 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2331 case MLX5E_TT_IPV4_IPSEC_AH:
2332 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2333 MLX5_L3_PROT_TYPE_IPV4);
2334 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2335 MLX5_HASH_IP_IPSEC_SPI);
2338 case MLX5E_TT_IPV6_IPSEC_AH:
2339 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2340 MLX5_L3_PROT_TYPE_IPV6);
2341 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2342 MLX5_HASH_IP_IPSEC_SPI);
2345 case MLX5E_TT_IPV4_IPSEC_ESP:
2346 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2347 MLX5_L3_PROT_TYPE_IPV4);
2348 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2349 MLX5_HASH_IP_IPSEC_SPI);
2352 case MLX5E_TT_IPV6_IPSEC_ESP:
2353 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2354 MLX5_L3_PROT_TYPE_IPV6);
2355 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2356 MLX5_HASH_IP_IPSEC_SPI);
2360 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2361 MLX5_L3_PROT_TYPE_IPV4);
2362 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2367 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2368 MLX5_L3_PROT_TYPE_IPV6);
2369 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2379 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2381 struct mlx5_core_dev *mdev = priv->mdev;
2387 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2388 in = mlx5_vzalloc(inlen);
2391 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2393 mlx5e_build_tir_ctx(priv, tirc, tt);
2395 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2403 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2405 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2409 mlx5e_open_tirs(struct mlx5e_priv *priv)
2414 for (i = 0; i < MLX5E_NUM_TT; i++) {
2415 err = mlx5e_open_tir(priv, i);
2417 goto err_close_tirs;
2423 for (i--; i >= 0; i--)
2424 mlx5e_close_tir(priv, i);
2430 mlx5e_close_tirs(struct mlx5e_priv *priv)
2434 for (i = 0; i < MLX5E_NUM_TT; i++)
2435 mlx5e_close_tir(priv, i);
2439 * SW MTU does not include headers,
2440 * HW MTU includes all headers and checksums.
2443 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2445 struct mlx5e_priv *priv = ifp->if_softc;
2446 struct mlx5_core_dev *mdev = priv->mdev;
2450 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2452 err = mlx5_set_port_mtu(mdev, hw_mtu);
2454 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2455 __func__, sw_mtu, err);
2459 /* Update vport context MTU */
2460 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2462 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2466 ifp->if_mtu = sw_mtu;
2468 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2469 if (err || !hw_mtu) {
2470 /* fallback to port oper mtu */
2471 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2474 if_printf(ifp, "Query port MTU, after setting new "
2475 "MTU value, failed\n");
2477 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2479 if_printf(ifp, "Port MTU %d is smaller than "
2480 "ifp mtu %d\n", hw_mtu, sw_mtu);
2481 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2483 if_printf(ifp, "Port MTU %d is bigger than "
2484 "ifp mtu %d\n", hw_mtu, sw_mtu);
2486 priv->params_ethtool.hw_mtu = hw_mtu;
2492 mlx5e_open_locked(struct ifnet *ifp)
2494 struct mlx5e_priv *priv = ifp->if_softc;
2498 /* check if already opened */
2499 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2503 if (rss_getnumbuckets() > priv->params.num_channels) {
2504 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2505 "channels(%u) available\n", rss_getnumbuckets(),
2506 priv->params.num_channels);
2509 err = mlx5e_open_tises(priv);
2511 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2515 err = mlx5_vport_alloc_q_counter(priv->mdev,
2516 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2518 if_printf(priv->ifp,
2519 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2521 goto err_close_tises;
2523 /* store counter set ID */
2524 priv->counter_set_id = set_id;
2526 err = mlx5e_open_channels(priv);
2528 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2530 goto err_dalloc_q_counter;
2532 err = mlx5e_open_rqt(priv);
2534 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2536 goto err_close_channels;
2538 err = mlx5e_open_tirs(priv);
2540 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2542 goto err_close_rqls;
2544 err = mlx5e_open_flow_table(priv);
2546 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2548 goto err_close_tirs;
2550 err = mlx5e_add_all_vlan_rules(priv);
2552 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2554 goto err_close_flow_table;
2556 set_bit(MLX5E_STATE_OPENED, &priv->state);
2558 mlx5e_update_carrier(priv);
2559 mlx5e_set_rx_mode_core(priv);
2563 err_close_flow_table:
2564 mlx5e_close_flow_table(priv);
2567 mlx5e_close_tirs(priv);
2570 mlx5e_close_rqt(priv);
2573 mlx5e_close_channels(priv);
2575 err_dalloc_q_counter:
2576 mlx5_vport_dealloc_q_counter(priv->mdev,
2577 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2580 mlx5e_close_tises(priv);
2586 mlx5e_open(void *arg)
2588 struct mlx5e_priv *priv = arg;
2591 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2592 if_printf(priv->ifp,
2593 "%s: Setting port status to up failed\n",
2596 mlx5e_open_locked(priv->ifp);
2597 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2602 mlx5e_close_locked(struct ifnet *ifp)
2604 struct mlx5e_priv *priv = ifp->if_softc;
2606 /* check if already closed */
2607 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2610 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2612 mlx5e_set_rx_mode_core(priv);
2613 mlx5e_del_all_vlan_rules(priv);
2614 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2615 mlx5e_close_flow_table(priv);
2616 mlx5e_close_tirs(priv);
2617 mlx5e_close_rqt(priv);
2618 mlx5e_close_channels(priv);
2619 mlx5_vport_dealloc_q_counter(priv->mdev,
2620 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2621 mlx5e_close_tises(priv);
2626 #if (__FreeBSD_version >= 1100000)
2628 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2630 struct mlx5e_priv *priv = ifp->if_softc;
2633 /* PRIV_LOCK(priv); XXX not allowed */
2635 case IFCOUNTER_IPACKETS:
2636 retval = priv->stats.vport.rx_packets;
2638 case IFCOUNTER_IERRORS:
2639 retval = priv->stats.vport.rx_error_packets +
2640 priv->stats.pport.alignment_err +
2641 priv->stats.pport.check_seq_err +
2642 priv->stats.pport.crc_align_errors +
2643 priv->stats.pport.in_range_len_errors +
2644 priv->stats.pport.jabbers +
2645 priv->stats.pport.out_of_range_len +
2646 priv->stats.pport.oversize_pkts +
2647 priv->stats.pport.symbol_err +
2648 priv->stats.pport.too_long_errors +
2649 priv->stats.pport.undersize_pkts +
2650 priv->stats.pport.unsupported_op_rx;
2652 case IFCOUNTER_IQDROPS:
2653 retval = priv->stats.vport.rx_out_of_buffer +
2654 priv->stats.pport.drop_events;
2656 case IFCOUNTER_OPACKETS:
2657 retval = priv->stats.vport.tx_packets;
2659 case IFCOUNTER_OERRORS:
2660 retval = priv->stats.vport.tx_error_packets;
2662 case IFCOUNTER_IBYTES:
2663 retval = priv->stats.vport.rx_bytes;
2665 case IFCOUNTER_OBYTES:
2666 retval = priv->stats.vport.tx_bytes;
2668 case IFCOUNTER_IMCASTS:
2669 retval = priv->stats.vport.rx_multicast_packets;
2671 case IFCOUNTER_OMCASTS:
2672 retval = priv->stats.vport.tx_multicast_packets;
2674 case IFCOUNTER_OQDROPS:
2675 retval = priv->stats.vport.tx_queue_dropped;
2677 case IFCOUNTER_COLLISIONS:
2678 retval = priv->stats.pport.collisions;
2681 retval = if_get_counter_default(ifp, cnt);
2684 /* PRIV_UNLOCK(priv); XXX not allowed */
2690 mlx5e_set_rx_mode(struct ifnet *ifp)
2692 struct mlx5e_priv *priv = ifp->if_softc;
2694 queue_work(priv->wq, &priv->set_rx_mode_work);
2698 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2700 struct mlx5e_priv *priv;
2702 struct ifi2creq i2c;
2711 priv = ifp->if_softc;
2713 /* check if detaching */
2714 if (priv == NULL || priv->gone != 0)
2719 ifr = (struct ifreq *)data;
2722 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2724 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2725 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2728 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2730 mlx5e_close_locked(ifp);
2733 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2736 mlx5e_open_locked(ifp);
2739 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2740 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2745 if ((ifp->if_flags & IFF_UP) &&
2746 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2747 mlx5e_set_rx_mode(ifp);
2751 if (ifp->if_flags & IFF_UP) {
2752 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2753 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2754 mlx5e_open_locked(ifp);
2755 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2756 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2759 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2760 mlx5_set_port_status(priv->mdev,
2762 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2763 mlx5e_close_locked(ifp);
2764 mlx5e_update_carrier(priv);
2765 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2772 mlx5e_set_rx_mode(ifp);
2777 ifr = (struct ifreq *)data;
2778 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2781 ifr = (struct ifreq *)data;
2783 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2785 if (mask & IFCAP_TXCSUM) {
2786 ifp->if_capenable ^= IFCAP_TXCSUM;
2787 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2789 if (IFCAP_TSO4 & ifp->if_capenable &&
2790 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2791 ifp->if_capenable &= ~IFCAP_TSO4;
2792 ifp->if_hwassist &= ~CSUM_IP_TSO;
2794 "tso4 disabled due to -txcsum.\n");
2797 if (mask & IFCAP_TXCSUM_IPV6) {
2798 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2799 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2801 if (IFCAP_TSO6 & ifp->if_capenable &&
2802 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2803 ifp->if_capenable &= ~IFCAP_TSO6;
2804 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2806 "tso6 disabled due to -txcsum6.\n");
2809 if (mask & IFCAP_RXCSUM)
2810 ifp->if_capenable ^= IFCAP_RXCSUM;
2811 if (mask & IFCAP_RXCSUM_IPV6)
2812 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2813 if (mask & IFCAP_TSO4) {
2814 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2815 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2816 if_printf(ifp, "enable txcsum first.\n");
2820 ifp->if_capenable ^= IFCAP_TSO4;
2821 ifp->if_hwassist ^= CSUM_IP_TSO;
2823 if (mask & IFCAP_TSO6) {
2824 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2825 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2826 if_printf(ifp, "enable txcsum6 first.\n");
2830 ifp->if_capenable ^= IFCAP_TSO6;
2831 ifp->if_hwassist ^= CSUM_IP6_TSO;
2833 if (mask & IFCAP_VLAN_HWFILTER) {
2834 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2835 mlx5e_disable_vlan_filter(priv);
2837 mlx5e_enable_vlan_filter(priv);
2839 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2841 if (mask & IFCAP_VLAN_HWTAGGING)
2842 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2843 if (mask & IFCAP_WOL_MAGIC)
2844 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2846 VLAN_CAPABILITIES(ifp);
2847 /* turn off LRO means also turn of HW LRO - if it's on */
2848 if (mask & IFCAP_LRO) {
2849 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2850 bool need_restart = false;
2852 ifp->if_capenable ^= IFCAP_LRO;
2853 if (!(ifp->if_capenable & IFCAP_LRO)) {
2854 if (priv->params.hw_lro_en) {
2855 priv->params.hw_lro_en = false;
2856 need_restart = true;
2857 /* Not sure this is the correct way */
2858 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2861 if (was_opened && need_restart) {
2862 mlx5e_close_locked(ifp);
2863 mlx5e_open_locked(ifp);
2866 if (mask & IFCAP_HWRXTSTMP) {
2867 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2868 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
2869 if (priv->clbr_done == 0)
2870 mlx5e_reset_calibration_callout(priv);
2872 callout_drain(&priv->tstmp_clbr);
2873 priv->clbr_done = 0;
2881 ifr = (struct ifreq *)data;
2884 * Copy from the user-space address ifr_data to the
2885 * kernel-space address i2c
2887 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2891 if (i2c.len > sizeof(i2c.data)) {
2897 /* Get module_num which is required for the query_eeprom */
2898 error = mlx5_query_module_num(priv->mdev, &module_num);
2900 if_printf(ifp, "Query module num failed, eeprom "
2901 "reading is not supported\n");
2905 /* Check if module is present before doing an access */
2906 module_status = mlx5_query_module_status(priv->mdev, module_num);
2907 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2908 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2913 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2914 * The internal conversion is as follows:
2916 if (i2c.dev_addr == 0xA0)
2917 read_addr = MLX5E_I2C_ADDR_LOW;
2918 else if (i2c.dev_addr == 0xA2)
2919 read_addr = MLX5E_I2C_ADDR_HIGH;
2921 if_printf(ifp, "Query eeprom failed, "
2922 "Invalid Address: %X\n", i2c.dev_addr);
2926 error = mlx5_query_eeprom(priv->mdev,
2927 read_addr, MLX5E_EEPROM_LOW_PAGE,
2928 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2929 (uint32_t *)i2c.data, &size_read);
2931 if_printf(ifp, "Query eeprom failed, eeprom "
2932 "reading is not supported\n");
2937 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2938 error = mlx5_query_eeprom(priv->mdev,
2939 read_addr, MLX5E_EEPROM_LOW_PAGE,
2940 (uint32_t)(i2c.offset + size_read),
2941 (uint32_t)(i2c.len - size_read), module_num,
2942 (uint32_t *)(i2c.data + size_read), &size_read);
2945 if_printf(ifp, "Query eeprom failed, eeprom "
2946 "reading is not supported\n");
2951 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2957 error = ether_ioctl(ifp, command, data);
2964 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2967 * TODO: uncoment once FW really sets all these bits if
2968 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2969 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2970 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2974 /* TODO: add more must-to-have features */
2976 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2983 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2984 struct mlx5e_priv *priv,
2985 int num_comp_vectors)
2988 * TODO: Consider link speed for setting "log_sq_size",
2989 * "log_rq_size" and "cq_moderation_xxx":
2991 priv->params.log_sq_size =
2992 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2993 priv->params.log_rq_size =
2994 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2995 priv->params.rx_cq_moderation_usec =
2996 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2997 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2998 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2999 priv->params.rx_cq_moderation_mode =
3000 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3001 priv->params.rx_cq_moderation_pkts =
3002 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3003 priv->params.tx_cq_moderation_usec =
3004 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3005 priv->params.tx_cq_moderation_pkts =
3006 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3007 priv->params.min_rx_wqes =
3008 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3009 priv->params.rx_hash_log_tbl_sz =
3010 (order_base_2(num_comp_vectors) >
3011 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3012 order_base_2(num_comp_vectors) :
3013 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3014 priv->params.num_tc = 1;
3015 priv->params.default_vlan_prio = 0;
3016 priv->counter_set_id = -1;
3019 * hw lro is currently defaulted to off. when it won't anymore we
3020 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3022 priv->params.hw_lro_en = false;
3023 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3025 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3028 priv->params.num_channels = num_comp_vectors;
3029 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3030 priv->queue_mapping_channel_mask =
3031 roundup_pow_of_two(num_comp_vectors) - 1;
3032 priv->num_tc = priv->params.num_tc;
3033 priv->default_vlan_prio = priv->params.default_vlan_prio;
3035 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3036 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3037 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3041 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3042 struct mlx5_core_mr *mkey)
3044 struct ifnet *ifp = priv->ifp;
3045 struct mlx5_core_dev *mdev = priv->mdev;
3046 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3051 in = mlx5_vzalloc(inlen);
3053 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3057 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3058 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3059 MLX5_SET(mkc, mkc, lw, 1);
3060 MLX5_SET(mkc, mkc, lr, 1);
3062 MLX5_SET(mkc, mkc, pd, pdn);
3063 MLX5_SET(mkc, mkc, length64, 1);
3064 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3066 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3068 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3075 static const char *mlx5e_vport_stats_desc[] = {
3076 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3079 static const char *mlx5e_pport_stats_desc[] = {
3080 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3084 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3086 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3087 sx_init(&priv->state_lock, "mlx5state");
3088 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3089 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3093 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3095 mtx_destroy(&priv->async_events_mtx);
3096 sx_destroy(&priv->state_lock);
3100 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3103 * %d.%d%.d the string format.
3104 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3105 * We need at most 5 chars to store that.
3106 * It also has: two "." and NULL at the end, which means we need 18
3107 * (5*3 + 3) chars at most.
3110 struct mlx5e_priv *priv = arg1;
3113 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3114 fw_rev_sub(priv->mdev));
3115 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3120 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3124 for (i = 0; i < ch->num_tc; i++)
3125 mlx5e_drain_sq(&ch->sq[i]);
3129 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3132 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3133 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3134 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3135 sq->doorbell.d64 = 0;
3139 mlx5e_resume_sq(struct mlx5e_sq *sq)
3143 /* check if already enabled */
3144 if (sq->stopped == 0)
3147 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3148 MLX5_SQC_STATE_RST);
3151 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3157 /* reset doorbell prior to moving from RST to RDY */
3158 mlx5e_reset_sq_doorbell_record(sq);
3160 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3161 MLX5_SQC_STATE_RDY);
3164 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3167 mtx_lock(&sq->lock);
3168 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3170 mtx_unlock(&sq->lock);
3175 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3179 for (i = 0; i < ch->num_tc; i++)
3180 mlx5e_resume_sq(&ch->sq[i]);
3184 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3186 struct mlx5e_rq *rq = &ch->rq;
3191 callout_stop(&rq->watchdog);
3192 mtx_unlock(&rq->mtx);
3194 callout_drain(&rq->watchdog);
3196 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3199 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3202 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3204 rq->cq.mcq.comp(&rq->cq.mcq);
3208 * Transitioning into RST state will allow the FW to track less ERR state queues,
3209 * thus reducing the recv queue flushing time
3211 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3214 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3219 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3221 struct mlx5e_rq *rq = &ch->rq;
3225 mlx5_wq_ll_update_db_record(&rq->wq);
3226 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3229 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3234 rq->cq.mcq.comp(&rq->cq.mcq);
3238 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3242 if (priv->channel == NULL)
3245 for (i = 0; i < priv->params.num_channels; i++) {
3247 if (!priv->channel[i])
3251 mlx5e_disable_tx_dma(priv->channel[i]);
3253 mlx5e_enable_tx_dma(priv->channel[i]);
3258 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3262 if (priv->channel == NULL)
3265 for (i = 0; i < priv->params.num_channels; i++) {
3267 if (!priv->channel[i])
3271 mlx5e_disable_rx_dma(priv->channel[i]);
3273 mlx5e_enable_rx_dma(priv->channel[i]);
3278 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3280 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3281 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3282 sysctl_firmware, "A", "HCA firmware version");
3284 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3285 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3290 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3292 struct mlx5e_priv *priv = arg1;
3299 tx_pfc = priv->params.tx_priority_flow_control;
3301 /* get current value */
3302 value = (tx_pfc >> arg2) & 1;
3304 error = sysctl_handle_32(oidp, &value, 0, req);
3306 /* range check value */
3308 priv->params.tx_priority_flow_control |= (1 << arg2);
3310 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3312 /* check if update is required */
3313 if (error == 0 && priv->gone == 0 &&
3314 tx_pfc != priv->params.tx_priority_flow_control) {
3315 error = -mlx5e_set_port_pfc(priv);
3316 /* restore previous value */
3318 priv->params.tx_priority_flow_control= tx_pfc;
3326 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3328 struct mlx5e_priv *priv = arg1;
3335 rx_pfc = priv->params.rx_priority_flow_control;
3337 /* get current value */
3338 value = (rx_pfc >> arg2) & 1;
3340 error = sysctl_handle_32(oidp, &value, 0, req);
3342 /* range check value */
3344 priv->params.rx_priority_flow_control |= (1 << arg2);
3346 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3348 /* check if update is required */
3349 if (error == 0 && priv->gone == 0 &&
3350 rx_pfc != priv->params.rx_priority_flow_control) {
3351 error = -mlx5e_set_port_pfc(priv);
3352 /* restore previous value */
3354 priv->params.rx_priority_flow_control= rx_pfc;
3362 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3368 /* Only receiving pauseframes is enabled by default */
3369 priv->params.tx_pauseframe_control = 0;
3370 priv->params.rx_pauseframe_control = 1;
3372 /* disable ports flow control, PFC, by default */
3373 priv->params.tx_priority_flow_control = 0;
3374 priv->params.rx_priority_flow_control = 0;
3376 #if (__FreeBSD_version < 1100000)
3377 /* compute path for sysctl */
3378 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3379 device_get_unit(priv->mdev->pdev->dev.bsddev));
3381 /* try to fetch tunable, if any */
3382 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3384 /* compute path for sysctl */
3385 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3386 device_get_unit(priv->mdev->pdev->dev.bsddev));
3388 /* try to fetch tunable, if any */
3389 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3391 for (x = 0; x != 8; x++) {
3393 /* compute path for sysctl */
3394 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3395 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3397 /* try to fetch tunable, if any */
3398 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3399 priv->params.tx_priority_flow_control |= 1 << x;
3401 /* compute path for sysctl */
3402 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3403 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3405 /* try to fetch tunable, if any */
3406 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3407 priv->params.rx_priority_flow_control |= 1 << x;
3411 /* register pauseframe SYSCTLs */
3412 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3413 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3414 &priv->params.tx_pauseframe_control, 0,
3415 "Set to enable TX pause frames. Clear to disable.");
3417 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3418 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3419 &priv->params.rx_pauseframe_control, 0,
3420 "Set to enable RX pause frames. Clear to disable.");
3422 /* register priority_flow control, PFC, SYSCTLs */
3423 for (x = 0; x != 8; x++) {
3424 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3426 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3427 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3428 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3429 "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3431 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3433 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3434 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3435 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3436 "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3442 priv->params.tx_pauseframe_control =
3443 priv->params.tx_pauseframe_control ? 1 : 0;
3444 priv->params.rx_pauseframe_control =
3445 priv->params.rx_pauseframe_control ? 1 : 0;
3447 /* update firmware */
3448 error = mlx5e_set_port_pause_and_pfc(priv);
3449 if (error == -EINVAL) {
3450 if_printf(priv->ifp,
3451 "Global pauseframes must be disabled before enabling PFC.\n");
3452 priv->params.rx_priority_flow_control = 0;
3453 priv->params.tx_priority_flow_control = 0;
3455 /* update firmware */
3456 (void) mlx5e_set_port_pause_and_pfc(priv);
3462 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3465 struct mlx5e_priv *priv;
3466 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3467 struct sysctl_oid_list *child;
3468 int ncv = mdev->priv.eq_table.num_comp_vectors;
3474 if (mlx5e_check_required_hca_cap(mdev)) {
3475 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3478 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3479 mlx5e_priv_mtx_init(priv);
3481 ifp = priv->ifp = if_alloc(IFT_ETHER);
3483 mlx5_core_err(mdev, "if_alloc() failed\n");
3486 ifp->if_softc = priv;
3487 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3488 ifp->if_mtu = ETHERMTU;
3489 ifp->if_init = mlx5e_open;
3490 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3491 ifp->if_ioctl = mlx5e_ioctl;
3492 ifp->if_transmit = mlx5e_xmit;
3493 ifp->if_qflush = if_qflush;
3494 #if (__FreeBSD_version >= 1100000)
3495 ifp->if_get_counter = mlx5e_get_counter;
3497 ifp->if_snd.ifq_maxlen = ifqmaxlen;
3499 * Set driver features
3501 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3502 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3503 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3504 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3505 ifp->if_capabilities |= IFCAP_LRO;
3506 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3507 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3509 /* set TSO limits so that we don't have to drop TX packets */
3510 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3511 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3512 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3514 ifp->if_capenable = ifp->if_capabilities;
3515 ifp->if_hwassist = 0;
3516 if (ifp->if_capenable & IFCAP_TSO)
3517 ifp->if_hwassist |= CSUM_TSO;
3518 if (ifp->if_capenable & IFCAP_TXCSUM)
3519 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3520 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3521 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3523 /* ifnet sysctl tree */
3524 sysctl_ctx_init(&priv->sysctl_ctx);
3525 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3526 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3527 if (priv->sysctl_ifnet == NULL) {
3528 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3529 goto err_free_sysctl;
3531 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3532 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3533 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3534 if (priv->sysctl_ifnet == NULL) {
3535 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3536 goto err_free_sysctl;
3539 /* HW sysctl tree */
3540 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3541 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3542 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3543 if (priv->sysctl_hw == NULL) {
3544 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3545 goto err_free_sysctl;
3547 mlx5e_build_ifp_priv(mdev, priv, ncv);
3549 snprintf(unit, sizeof(unit), "mce%u_wq",
3550 device_get_unit(mdev->pdev->dev.bsddev));
3551 priv->wq = alloc_workqueue(unit, 0, 1);
3552 if (priv->wq == NULL) {
3553 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3554 goto err_free_sysctl;
3557 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3559 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3563 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3565 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3567 goto err_unmap_free_uar;
3569 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3571 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3573 goto err_dealloc_pd;
3575 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3577 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3579 goto err_dealloc_transport_domain;
3581 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3583 /* check if we should generate a random MAC address */
3584 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3585 is_zero_ether_addr(dev_addr)) {
3586 random_ether_addr(dev_addr);
3587 if_printf(ifp, "Assigned random MAC address\n");
3590 /* set default MTU */
3591 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3594 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3596 /* Set default media status */
3597 priv->media_status_last = IFM_AVALID;
3598 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3599 IFM_ETH_RXPAUSE | IFM_FDX;
3601 /* setup default pauseframes configuration */
3602 mlx5e_setup_pauseframes(priv);
3604 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3607 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3611 /* Setup supported medias */
3612 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3613 mlx5e_media_change, mlx5e_media_status);
3615 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3616 if (mlx5e_mode_table[i].baudrate == 0)
3618 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3619 ifmedia_add(&priv->media,
3620 mlx5e_mode_table[i].subtype |
3621 IFM_ETHER, 0, NULL);
3622 ifmedia_add(&priv->media,
3623 mlx5e_mode_table[i].subtype |
3624 IFM_ETHER | IFM_FDX |
3625 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3629 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3630 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3631 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3633 /* Set autoselect by default */
3634 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3635 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3636 ether_ifattach(ifp, dev_addr);
3638 /* Register for VLAN events */
3639 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3640 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3641 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3642 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3644 /* Link is down by default */
3645 if_link_state_change(ifp, LINK_STATE_DOWN);
3647 mlx5e_enable_async_events(priv);
3649 mlx5e_add_hw_stats(priv);
3651 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3652 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3653 priv->stats.vport.arg);
3655 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3656 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3657 priv->stats.pport.arg);
3659 mlx5e_create_ethtool(priv);
3661 mtx_lock(&priv->async_events_mtx);
3662 mlx5e_update_stats(priv);
3663 mtx_unlock(&priv->async_events_mtx);
3665 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3666 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3667 &priv->clbr_done, 0,
3668 "RX timestamps calibration state");
3669 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3670 mlx5e_reset_calibration_callout(priv);
3674 err_dealloc_transport_domain:
3675 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3678 mlx5_core_dealloc_pd(mdev, priv->pdn);
3681 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3684 destroy_workqueue(priv->wq);
3687 sysctl_ctx_free(&priv->sysctl_ctx);
3692 mlx5e_priv_mtx_destroy(priv);
3693 free(priv, M_MLX5EN);
3698 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3700 struct mlx5e_priv *priv = vpriv;
3701 struct ifnet *ifp = priv->ifp;
3703 /* don't allow more IOCTLs */
3707 * Clear the device description to avoid use after free,
3708 * because the bsddev is not destroyed when this module is
3711 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3713 /* XXX wait a bit to allow IOCTL handlers to complete */
3716 /* stop watchdog timer */
3717 callout_drain(&priv->watchdog);
3719 callout_drain(&priv->tstmp_clbr);
3721 if (priv->vlan_attach != NULL)
3722 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3723 if (priv->vlan_detach != NULL)
3724 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3726 /* make sure device gets closed */
3728 mlx5e_close_locked(ifp);
3731 /* unregister device */
3732 ifmedia_removeall(&priv->media);
3733 ether_ifdetach(ifp);
3736 /* destroy all remaining sysctl nodes */
3737 if (priv->sysctl_debug)
3738 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3739 sysctl_ctx_free(&priv->stats.vport.ctx);
3740 sysctl_ctx_free(&priv->stats.pport.ctx);
3741 sysctl_ctx_free(&priv->sysctl_ctx);
3743 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3744 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3745 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3746 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3747 mlx5e_disable_async_events(priv);
3748 destroy_workqueue(priv->wq);
3749 mlx5e_priv_mtx_destroy(priv);
3750 free(priv, M_MLX5EN);
3754 mlx5e_get_ifp(void *vpriv)
3756 struct mlx5e_priv *priv = vpriv;
3761 static struct mlx5_interface mlx5e_interface = {
3762 .add = mlx5e_create_ifp,
3763 .remove = mlx5e_destroy_ifp,
3764 .event = mlx5e_async_event,
3765 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3766 .get_dev = mlx5e_get_ifp,
3772 mlx5_register_interface(&mlx5e_interface);
3778 mlx5_unregister_interface(&mlx5e_interface);
3781 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3782 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3784 #if (__FreeBSD_version >= 1100000)
3785 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3787 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3788 MODULE_VERSION(mlx5en, 1);