sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 /*
 310  * This function reads the physical port counters from the firmware
 311  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 312  * macros. The output is converted from big-endian 64-bit values into
 313  * host endian ones and stored in the "priv->stats.pport" structure.
 314  */
 315 static void
 316 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 317 {
 318         struct mlx5_core_dev *mdev = priv->mdev;
 319         struct mlx5e_pport_stats *s = &priv->stats.pport;
 320         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 321         u32 *in;
 322         u32 *out;
 323         const u64 *ptr;
 324         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 325         unsigned x;
 326         unsigned y;
 327
 328         /* allocate firmware request structures */
 329         in = mlx5_vzalloc(sz);
 330         out = mlx5_vzalloc(sz);
 331         if (in == NULL || out == NULL)
 332                 goto free_out;
 333
 334         /*
 335          * Get pointer to the 64-bit counter set which is located at a
 336          * fixed offset in the output firmware request structure:
 337          */
 338         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 339
 340         MLX5_SET(ppcnt_reg, in, local_port, 1);
 341
 342         /* read IEEE802_3 counter group using predefined counter layout */
 343         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 344         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 345         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 346                 s->arg[y] = be64toh(ptr[x]);
 347
 348         /* read RFC2819 counter group using predefined counter layout */
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 352                 s->arg[y] = be64toh(ptr[x]);
 353         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 354             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 355                 s_debug->arg[y] = be64toh(ptr[x]);
 356
 357         /* read RFC2863 counter group using predefined counter layout */
 358         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 359         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 360         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 361                 s_debug->arg[y] = be64toh(ptr[x]);
 362
 363         /* read physical layer stats counter group using predefined counter layout */
 364         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 365         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 366         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 367                 s_debug->arg[y] = be64toh(ptr[x]);
 368 free_out:
 369         /* free firmware request structures */
 370         kvfree(in);
 371         kvfree(out);
 372 }
 373
 374 /*
 375  * This function is called regularly to collect all statistics
 376  * counters from the firmware. The values can be viewed through the
 377  * sysctl interface. Execution is serialized using the priv's global
 378  * configuration lock.
 379  */
 380 static void
 381 mlx5e_update_stats_work(struct work_struct *work)
 382 {
 383         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 384             update_stats_work);
 385         struct mlx5_core_dev *mdev = priv->mdev;
 386         struct mlx5e_vport_stats *s = &priv->stats.vport;
 387         struct mlx5e_rq_stats *rq_stats;
 388         struct mlx5e_sq_stats *sq_stats;
 389         struct buf_ring *sq_br;
 390 #if (__FreeBSD_version < 1100000)
 391         struct ifnet *ifp = priv->ifp;
 392 #endif
 393
 394         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 395         u32 *out;
 396         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 397         u64 tso_packets = 0;
 398         u64 tso_bytes = 0;
 399         u64 tx_queue_dropped = 0;
 400         u64 tx_defragged = 0;
 401         u64 tx_offload_none = 0;
 402         u64 lro_packets = 0;
 403         u64 lro_bytes = 0;
 404         u64 sw_lro_queued = 0;
 405         u64 sw_lro_flushed = 0;
 406         u64 rx_csum_none = 0;
 407         u64 rx_wqe_err = 0;
 408         u32 rx_out_of_buffer = 0;
 409         int i;
 410         int j;
 411
 412         PRIV_LOCK(priv);
 413         out = mlx5_vzalloc(outlen);
 414         if (out == NULL)
 415                 goto free_out;
 416         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 417                 goto free_out;
 418
 419         /* Collect firts the SW counters and then HW for consistency */
 420         for (i = 0; i < priv->params.num_channels; i++) {
 421                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 422
 423                 rq_stats = &priv->channel[i]->rq.stats;
 424
 425                 /* collect stats from LRO */
 426                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 427                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 428                 sw_lro_queued += rq_stats->sw_lro_queued;
 429                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 430                 lro_packets += rq_stats->lro_packets;
 431                 lro_bytes += rq_stats->lro_bytes;
 432                 rx_csum_none += rq_stats->csum_none;
 433                 rx_wqe_err += rq_stats->wqe_err;
 434
 435                 for (j = 0; j < priv->num_tc; j++) {
 436                         sq_stats = &priv->channel[i]->sq[j].stats;
 437                         sq_br = priv->channel[i]->sq[j].br;
 438
 439                         tso_packets += sq_stats->tso_packets;
 440                         tso_bytes += sq_stats->tso_bytes;
 441                         tx_queue_dropped += sq_stats->dropped;
 442                         tx_queue_dropped += sq_br->br_drops;
 443                         tx_defragged += sq_stats->defragged;
 444                         tx_offload_none += sq_stats->csum_offload_none;
 445                 }
 446         }
 447
 448         /* update counters */
 449         s->tso_packets = tso_packets;
 450         s->tso_bytes = tso_bytes;
 451         s->tx_queue_dropped = tx_queue_dropped;
 452         s->tx_defragged = tx_defragged;
 453         s->lro_packets = lro_packets;
 454         s->lro_bytes = lro_bytes;
 455         s->sw_lro_queued = sw_lro_queued;
 456         s->sw_lro_flushed = sw_lro_flushed;
 457         s->rx_csum_none = rx_csum_none;
 458         s->rx_wqe_err = rx_wqe_err;
 459
 460         /* HW counters */
 461         memset(in, 0, sizeof(in));
 462
 463         MLX5_SET(query_vport_counter_in, in, opcode,
 464             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 465         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 466         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 467
 468         memset(out, 0, outlen);
 469
 470         /* get number of out-of-buffer drops first */
 471         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 472             &rx_out_of_buffer))
 473                 goto free_out;
 474
 475         /* accumulate difference into a 64-bit counter */
 476         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 477         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 478
 479         /* get port statistics */
 480         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 481                 goto free_out;
 482
 483 #define MLX5_GET_CTR(out, x) \
 484         MLX5_GET64(query_vport_counter_out, out, x)
 485
 486         s->rx_error_packets =
 487             MLX5_GET_CTR(out, received_errors.packets);
 488         s->rx_error_bytes =
 489             MLX5_GET_CTR(out, received_errors.octets);
 490         s->tx_error_packets =
 491             MLX5_GET_CTR(out, transmit_errors.packets);
 492         s->tx_error_bytes =
 493             MLX5_GET_CTR(out, transmit_errors.octets);
 494
 495         s->rx_unicast_packets =
 496             MLX5_GET_CTR(out, received_eth_unicast.packets);
 497         s->rx_unicast_bytes =
 498             MLX5_GET_CTR(out, received_eth_unicast.octets);
 499         s->tx_unicast_packets =
 500             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 501         s->tx_unicast_bytes =
 502             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 503
 504         s->rx_multicast_packets =
 505             MLX5_GET_CTR(out, received_eth_multicast.packets);
 506         s->rx_multicast_bytes =
 507             MLX5_GET_CTR(out, received_eth_multicast.octets);
 508         s->tx_multicast_packets =
 509             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 510         s->tx_multicast_bytes =
 511             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 512
 513         s->rx_broadcast_packets =
 514             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 515         s->rx_broadcast_bytes =
 516             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 517         s->tx_broadcast_packets =
 518             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 519         s->tx_broadcast_bytes =
 520             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 521
 522         s->rx_packets =
 523             s->rx_unicast_packets +
 524             s->rx_multicast_packets +
 525             s->rx_broadcast_packets -
 526             s->rx_out_of_buffer;
 527         s->rx_bytes =
 528             s->rx_unicast_bytes +
 529             s->rx_multicast_bytes +
 530             s->rx_broadcast_bytes;
 531         s->tx_packets =
 532             s->tx_unicast_packets +
 533             s->tx_multicast_packets +
 534             s->tx_broadcast_packets;
 535         s->tx_bytes =
 536             s->tx_unicast_bytes +
 537             s->tx_multicast_bytes +
 538             s->tx_broadcast_bytes;
 539
 540         /* Update calculated offload counters */
 541         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 542         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 543
 544         /* Get physical port counters */
 545         mlx5e_update_pport_counters(priv);
 546
 547 #if (__FreeBSD_version < 1100000)
 548         /* no get_counters interface in fbsd 10 */
 549         ifp->if_ipackets = s->rx_packets;
 550         ifp->if_ierrors = s->rx_error_packets +
 551             priv->stats.pport.alignment_err +
 552             priv->stats.pport.check_seq_err +
 553             priv->stats.pport.crc_align_errors +
 554             priv->stats.pport.drop_events +
 555             priv->stats.pport.in_range_len_errors +
 556             priv->stats.pport.jabbers +
 557             priv->stats.pport.out_of_range_len +
 558             priv->stats.pport.oversize_pkts +
 559             priv->stats.pport.symbol_err +
 560             priv->stats.pport.too_long_errors +
 561             priv->stats.pport.undersize_pkts +
 562             priv->stats.pport.unsupported_op_rx;
 563         ifp->if_iqdrops = s->rx_out_of_buffer;
 564         ifp->if_opackets = s->tx_packets;
 565         ifp->if_oerrors = s->tx_error_packets;
 566         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 567         ifp->if_ibytes = s->rx_bytes;
 568         ifp->if_obytes = s->tx_bytes;
 569         ifp->if_collisions =
 570             priv->stats.pport.collisions;
 571 #endif
 572
 573 free_out:
 574         kvfree(out);
 575         PRIV_UNLOCK(priv);
 576 }
 577
 578 static void
 579 mlx5e_update_stats(void *arg)
 580 {
 581         struct mlx5e_priv *priv = arg;
 582
 583         schedule_work(&priv->update_stats_work);
 584
 585         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 586 }
 587
 588 static void
 589 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 590     enum mlx5_dev_event event)
 591 {
 592         switch (event) {
 593         case MLX5_DEV_EVENT_PORT_UP:
 594         case MLX5_DEV_EVENT_PORT_DOWN:
 595                 schedule_work(&priv->update_carrier_work);
 596                 break;
 597
 598         default:
 599                 break;
 600         }
 601 }
 602
 603 static void
 604 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 605     enum mlx5_dev_event event, unsigned long param)
 606 {
 607         struct mlx5e_priv *priv = vpriv;
 608
 609         mtx_lock(&priv->async_events_mtx);
 610         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 611                 mlx5e_async_event_sub(priv, event);
 612         mtx_unlock(&priv->async_events_mtx);
 613 }
 614
 615 static void
 616 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 617 {
 618         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 619 }
 620
 621 static void
 622 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 623 {
 624         mtx_lock(&priv->async_events_mtx);
 625         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 626         mtx_unlock(&priv->async_events_mtx);
 627 }
 628
 629 static const char *mlx5e_rq_stats_desc[] = {
 630         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 631 };
 632
 633 static int
 634 mlx5e_create_rq(struct mlx5e_channel *c,
 635     struct mlx5e_rq_param *param,
 636     struct mlx5e_rq *rq)
 637 {
 638         struct mlx5e_priv *priv = c->priv;
 639         struct mlx5_core_dev *mdev = priv->mdev;
 640         char buffer[16];
 641         void *rqc = param->rqc;
 642         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 643         int wq_sz;
 644         int err;
 645         int i;
 646
 647         /* Create DMA descriptor TAG */
 648         if ((err = -bus_dma_tag_create(
 649             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 650             1,                          /* any alignment */
 651             0,                          /* no boundary */
 652             BUS_SPACE_MAXADDR,          /* lowaddr */
 653             BUS_SPACE_MAXADDR,          /* highaddr */
 654             NULL, NULL,                 /* filter, filterarg */
 655             MJUM16BYTES,                /* maxsize */
 656             1,                          /* nsegments */
 657             MJUM16BYTES,                /* maxsegsize */
 658             0,                          /* flags */
 659             NULL, NULL,                 /* lockfunc, lockfuncarg */
 660             &rq->dma_tag)))
 661                 goto done;
 662
 663         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 664             &rq->wq_ctrl);
 665         if (err)
 666                 goto err_free_dma_tag;
 667
 668         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 669
 670         if (priv->params.hw_lro_en) {
 671                 rq->wqe_sz = priv->params.lro_wqe_sz;
 672         } else {
 673                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 674         }
 675         if (rq->wqe_sz > MJUM16BYTES) {
 676                 err = -ENOMEM;
 677                 goto err_rq_wq_destroy;
 678         } else if (rq->wqe_sz > MJUM9BYTES) {
 679                 rq->wqe_sz = MJUM16BYTES;
 680         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 681                 rq->wqe_sz = MJUM9BYTES;
 682         } else if (rq->wqe_sz > MCLBYTES) {
 683                 rq->wqe_sz = MJUMPAGESIZE;
 684         } else {
 685                 rq->wqe_sz = MCLBYTES;
 686         }
 687
 688         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 689
 690         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 691         if (err)
 692                 goto err_rq_wq_destroy;
 693
 694         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 695         for (i = 0; i != wq_sz; i++) {
 696                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 697                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 698
 699                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 700                 if (err != 0) {
 701                         while (i--)
 702                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 703                         goto err_rq_mbuf_free;
 704                 }
 705                 wqe->data.lkey = c->mkey_be;
 706                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 707         }
 708
 709         rq->ifp = c->ifp;
 710         rq->channel = c;
 711         rq->ix = c->ix;
 712
 713         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 714         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 715             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 716             rq->stats.arg);
 717         return (0);
 718
 719 err_rq_mbuf_free:
 720         free(rq->mbuf, M_MLX5EN);
 721         tcp_lro_free(&rq->lro);
 722 err_rq_wq_destroy:
 723         mlx5_wq_destroy(&rq->wq_ctrl);
 724 err_free_dma_tag:
 725         bus_dma_tag_destroy(rq->dma_tag);
 726 done:
 727         return (err);
 728 }
 729
 730 static void
 731 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 732 {
 733         int wq_sz;
 734         int i;
 735
 736         /* destroy all sysctl nodes */
 737         sysctl_ctx_free(&rq->stats.ctx);
 738
 739         /* free leftover LRO packets, if any */
 740         tcp_lro_free(&rq->lro);
 741
 742         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 743         for (i = 0; i != wq_sz; i++) {
 744                 if (rq->mbuf[i].mbuf != NULL) {
 745                         bus_dmamap_unload(rq->dma_tag,
 746                             rq->mbuf[i].dma_map);
 747                         m_freem(rq->mbuf[i].mbuf);
 748                 }
 749                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 750         }
 751         free(rq->mbuf, M_MLX5EN);
 752         mlx5_wq_destroy(&rq->wq_ctrl);
 753 }
 754
 755 static int
 756 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 757 {
 758         struct mlx5e_channel *c = rq->channel;
 759         struct mlx5e_priv *priv = c->priv;
 760         struct mlx5_core_dev *mdev = priv->mdev;
 761
 762         void *in;
 763         void *rqc;
 764         void *wq;
 765         int inlen;
 766         int err;
 767
 768         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 769             sizeof(u64) * rq->wq_ctrl.buf.npages;
 770         in = mlx5_vzalloc(inlen);
 771         if (in == NULL)
 772                 return (-ENOMEM);
 773
 774         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 775         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 776
 777         memcpy(rqc, param->rqc, sizeof(param->rqc));
 778
 779         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 780         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 781         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 782         if (priv->counter_set_id >= 0)
 783                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 784         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 785             PAGE_SHIFT);
 786         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 787
 788         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 789             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 790
 791         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 792
 793         kvfree(in);
 794
 795         return (err);
 796 }
 797
 798 static int
 799 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 800 {
 801         struct mlx5e_channel *c = rq->channel;
 802         struct mlx5e_priv *priv = c->priv;
 803         struct mlx5_core_dev *mdev = priv->mdev;
 804
 805         void *in;
 806         void *rqc;
 807         int inlen;
 808         int err;
 809
 810         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 811         in = mlx5_vzalloc(inlen);
 812         if (in == NULL)
 813                 return (-ENOMEM);
 814
 815         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 816
 817         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 818         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 819         MLX5_SET(rqc, rqc, state, next_state);
 820
 821         err = mlx5_core_modify_rq(mdev, in, inlen);
 822
 823         kvfree(in);
 824
 825         return (err);
 826 }
 827
 828 static void
 829 mlx5e_disable_rq(struct mlx5e_rq *rq)
 830 {
 831         struct mlx5e_channel *c = rq->channel;
 832         struct mlx5e_priv *priv = c->priv;
 833         struct mlx5_core_dev *mdev = priv->mdev;
 834
 835         mlx5_core_destroy_rq(mdev, rq->rqn);
 836 }
 837
 838 static int
 839 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 840 {
 841         struct mlx5e_channel *c = rq->channel;
 842         struct mlx5e_priv *priv = c->priv;
 843         struct mlx5_wq_ll *wq = &rq->wq;
 844         int i;
 845
 846         for (i = 0; i < 1000; i++) {
 847                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 848                         return (0);
 849
 850                 msleep(4);
 851         }
 852         return (-ETIMEDOUT);
 853 }
 854
 855 static int
 856 mlx5e_open_rq(struct mlx5e_channel *c,
 857     struct mlx5e_rq_param *param,
 858     struct mlx5e_rq *rq)
 859 {
 860         int err;
 861
 862         err = mlx5e_create_rq(c, param, rq);
 863         if (err)
 864                 return (err);
 865
 866         err = mlx5e_enable_rq(rq, param);
 867         if (err)
 868                 goto err_destroy_rq;
 869
 870         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 871         if (err)
 872                 goto err_disable_rq;
 873
 874         c->rq.enabled = 1;
 875
 876         return (0);
 877
 878 err_disable_rq:
 879         mlx5e_disable_rq(rq);
 880 err_destroy_rq:
 881         mlx5e_destroy_rq(rq);
 882
 883         return (err);
 884 }
 885
 886 static void
 887 mlx5e_close_rq(struct mlx5e_rq *rq)
 888 {
 889         mtx_lock(&rq->mtx);
 890         rq->enabled = 0;
 891         callout_stop(&rq->watchdog);
 892         mtx_unlock(&rq->mtx);
 893
 894         callout_drain(&rq->watchdog);
 895
 896         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 897 }
 898
 899 static void
 900 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 901 {
 902         /* wait till RQ is empty */
 903         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 904                 msleep(4);
 905                 rq->cq.mcq.comp(&rq->cq.mcq);
 906         }
 907
 908         mlx5e_disable_rq(rq);
 909         mlx5e_destroy_rq(rq);
 910 }
 911
 912 void
 913 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 914 {
 915         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 916         int x;
 917
 918         for (x = 0; x != wq_sz; x++)
 919                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 920         free(sq->mbuf, M_MLX5EN);
 921 }
 922
 923 int
 924 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 925 {
 926         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 927         int err;
 928         int x;
 929
 930         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 931
 932         /* Create DMA descriptor MAPs */
 933         for (x = 0; x != wq_sz; x++) {
 934                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 935                 if (err != 0) {
 936                         while (x--)
 937                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 938                         free(sq->mbuf, M_MLX5EN);
 939                         return (err);
 940                 }
 941         }
 942         return (0);
 943 }
 944
 945 static const char *mlx5e_sq_stats_desc[] = {
 946         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 947 };
 948
 949 static int
 950 mlx5e_create_sq(struct mlx5e_channel *c,
 951     int tc,
 952     struct mlx5e_sq_param *param,
 953     struct mlx5e_sq *sq)
 954 {
 955         struct mlx5e_priv *priv = c->priv;
 956         struct mlx5_core_dev *mdev = priv->mdev;
 957         char buffer[16];
 958
 959         void *sqc = param->sqc;
 960         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 961 #ifdef RSS
 962         cpuset_t cpu_mask;
 963         int cpu_id;
 964 #endif
 965         int err;
 966
 967         /* Create DMA descriptor TAG */
 968         if ((err = -bus_dma_tag_create(
 969             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 970             1,                          /* any alignment */
 971             0,                          /* no boundary */
 972             BUS_SPACE_MAXADDR,          /* lowaddr */
 973             BUS_SPACE_MAXADDR,          /* highaddr */
 974             NULL, NULL,                 /* filter, filterarg */
 975             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 976             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 977             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 978             0,                          /* flags */
 979             NULL, NULL,                 /* lockfunc, lockfuncarg */
 980             &sq->dma_tag)))
 981                 goto done;
 982
 983         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 984         if (err)
 985                 goto err_free_dma_tag;
 986
 987         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 988             &sq->wq_ctrl);
 989         if (err)
 990                 goto err_unmap_free_uar;
 991
 992         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 993         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 994
 995         err = mlx5e_alloc_sq_db(sq);
 996         if (err)
 997                 goto err_sq_wq_destroy;
 998
 999         sq->mkey_be = c->mkey_be;
1000         sq->ifp = priv->ifp;
1001         sq->priv = priv;
1002         sq->tc = tc;
1003
1004         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1005             M_WAITOK, &sq->lock);
1006         if (sq->br == NULL) {
1007                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1008                     __func__);
1009                 err = -ENOMEM;
1010                 goto err_free_sq_db;
1011         }
1012
1013         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1014             taskqueue_thread_enqueue, &sq->sq_tq);
1015         if (sq->sq_tq == NULL) {
1016                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1017                     __func__);
1018                 err = -ENOMEM;
1019                 goto err_free_drbr;
1020         }
1021
1022         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1023 #ifdef RSS
1024         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1025         CPU_SETOF(cpu_id, &cpu_mask);
1026         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1027             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1028 #else
1029         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1030             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1031 #endif
1032         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1033         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1034             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1035             sq->stats.arg);
1036
1037         return (0);
1038
1039 err_free_drbr:
1040         buf_ring_free(sq->br, M_MLX5EN);
1041 err_free_sq_db:
1042         mlx5e_free_sq_db(sq);
1043 err_sq_wq_destroy:
1044         mlx5_wq_destroy(&sq->wq_ctrl);
1045
1046 err_unmap_free_uar:
1047         mlx5_unmap_free_uar(mdev, &sq->uar);
1048
1049 err_free_dma_tag:
1050         bus_dma_tag_destroy(sq->dma_tag);
1051 done:
1052         return (err);
1053 }
1054
1055 static void
1056 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1057 {
1058         /* destroy all sysctl nodes */
1059         sysctl_ctx_free(&sq->stats.ctx);
1060
1061         mlx5e_free_sq_db(sq);
1062         mlx5_wq_destroy(&sq->wq_ctrl);
1063         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1064         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1065         taskqueue_free(sq->sq_tq);
1066         buf_ring_free(sq->br, M_MLX5EN);
1067 }
1068
1069 int
1070 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1071     int tis_num)
1072 {
1073         void *in;
1074         void *sqc;
1075         void *wq;
1076         int inlen;
1077         int err;
1078
1079         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1080             sizeof(u64) * sq->wq_ctrl.buf.npages;
1081         in = mlx5_vzalloc(inlen);
1082         if (in == NULL)
1083                 return (-ENOMEM);
1084
1085         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1086         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1087
1088         memcpy(sqc, param->sqc, sizeof(param->sqc));
1089
1090         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1091         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1092         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1093         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1094         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1095
1096         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1097         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1098         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1099             PAGE_SHIFT);
1100         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1101
1102         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1103             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1104
1105         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1106
1107         kvfree(in);
1108
1109         return (err);
1110 }
1111
1112 int
1113 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1114 {
1115         void *in;
1116         void *sqc;
1117         int inlen;
1118         int err;
1119
1120         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1121         in = mlx5_vzalloc(inlen);
1122         if (in == NULL)
1123                 return (-ENOMEM);
1124
1125         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1126
1127         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1128         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1129         MLX5_SET(sqc, sqc, state, next_state);
1130
1131         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1132
1133         kvfree(in);
1134
1135         return (err);
1136 }
1137
1138 void
1139 mlx5e_disable_sq(struct mlx5e_sq *sq)
1140 {
1141
1142         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1143 }
1144
1145 static int
1146 mlx5e_open_sq(struct mlx5e_channel *c,
1147     int tc,
1148     struct mlx5e_sq_param *param,
1149     struct mlx5e_sq *sq)
1150 {
1151         int err;
1152
1153         err = mlx5e_create_sq(c, tc, param, sq);
1154         if (err)
1155                 return (err);
1156
1157         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1158         if (err)
1159                 goto err_destroy_sq;
1160
1161         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1162         if (err)
1163                 goto err_disable_sq;
1164
1165         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1166
1167         return (0);
1168
1169 err_disable_sq:
1170         mlx5e_disable_sq(sq);
1171 err_destroy_sq:
1172         mlx5e_destroy_sq(sq);
1173
1174         return (err);
1175 }
1176
1177 static void
1178 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1179 {
1180         /* fill up remainder with NOPs */
1181         while (sq->cev_counter != 0) {
1182                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1183                         if (can_sleep != 0) {
1184                                 mtx_unlock(&sq->lock);
1185                                 msleep(4);
1186                                 mtx_lock(&sq->lock);
1187                         } else {
1188                                 goto done;
1189                         }
1190                 }
1191                 /* send a single NOP */
1192                 mlx5e_send_nop(sq, 1);
1193                 wmb();
1194         }
1195 done:
1196         /* Check if we need to write the doorbell */
1197         if (likely(sq->doorbell.d64 != 0)) {
1198                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1199                 sq->doorbell.d64 = 0;
1200         }
1201         return;
1202 }
1203
1204 void
1205 mlx5e_sq_cev_timeout(void *arg)
1206 {
1207         struct mlx5e_sq *sq = arg;
1208
1209         mtx_assert(&sq->lock, MA_OWNED);
1210
1211         /* check next state */
1212         switch (sq->cev_next_state) {
1213         case MLX5E_CEV_STATE_SEND_NOPS:
1214                 /* fill TX ring with NOPs, if any */
1215                 mlx5e_sq_send_nops_locked(sq, 0);
1216
1217                 /* check if completed */
1218                 if (sq->cev_counter == 0) {
1219                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1220                         return;
1221                 }
1222                 break;
1223         default:
1224                 /* send NOPs on next timeout */
1225                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1226                 break;
1227         }
1228
1229         /* restart timer */
1230         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1231 }
1232
1233 void
1234 mlx5e_drain_sq(struct mlx5e_sq *sq)
1235 {
1236
1237         mtx_lock(&sq->lock);
1238         /* teardown event factor timer, if any */
1239         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1240         callout_stop(&sq->cev_callout);
1241
1242         /* send dummy NOPs in order to flush the transmit ring */
1243         mlx5e_sq_send_nops_locked(sq, 1);
1244         mtx_unlock(&sq->lock);
1245
1246         /* make sure it is safe to free the callout */
1247         callout_drain(&sq->cev_callout);
1248
1249         /* error out remaining requests */
1250         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1251
1252         /* wait till SQ is empty */
1253         mtx_lock(&sq->lock);
1254         while (sq->cc != sq->pc) {
1255                 mtx_unlock(&sq->lock);
1256                 msleep(4);
1257                 sq->cq.mcq.comp(&sq->cq.mcq);
1258                 mtx_lock(&sq->lock);
1259         }
1260         mtx_unlock(&sq->lock);
1261 }
1262
1263 static void
1264 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1265 {
1266
1267         mlx5e_drain_sq(sq);
1268         mlx5e_disable_sq(sq);
1269         mlx5e_destroy_sq(sq);
1270 }
1271
1272 static int
1273 mlx5e_create_cq(struct mlx5e_priv *priv,
1274     struct mlx5e_cq_param *param,
1275     struct mlx5e_cq *cq,
1276     mlx5e_cq_comp_t *comp,
1277     int eq_ix)
1278 {
1279         struct mlx5_core_dev *mdev = priv->mdev;
1280         struct mlx5_core_cq *mcq = &cq->mcq;
1281         int eqn_not_used;
1282         int irqn;
1283         int err;
1284         u32 i;
1285
1286         param->wq.buf_numa_node = 0;
1287         param->wq.db_numa_node = 0;
1288
1289         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1290             &cq->wq_ctrl);
1291         if (err)
1292                 return (err);
1293
1294         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1295
1296         mcq->cqe_sz = 64;
1297         mcq->set_ci_db = cq->wq_ctrl.db.db;
1298         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1299         *mcq->set_ci_db = 0;
1300         *mcq->arm_db = 0;
1301         mcq->vector = eq_ix;
1302         mcq->comp = comp;
1303         mcq->event = mlx5e_cq_error_event;
1304         mcq->irqn = irqn;
1305         mcq->uar = &priv->cq_uar;
1306
1307         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1308                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1309
1310                 cqe->op_own = 0xf1;
1311         }
1312
1313         cq->priv = priv;
1314
1315         return (0);
1316 }
1317
1318 static void
1319 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1320 {
1321         mlx5_wq_destroy(&cq->wq_ctrl);
1322 }
1323
1324 static int
1325 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1326 {
1327         struct mlx5_core_cq *mcq = &cq->mcq;
1328         void *in;
1329         void *cqc;
1330         int inlen;
1331         int irqn_not_used;
1332         int eqn;
1333         int err;
1334
1335         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1336             sizeof(u64) * cq->wq_ctrl.buf.npages;
1337         in = mlx5_vzalloc(inlen);
1338         if (in == NULL)
1339                 return (-ENOMEM);
1340
1341         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1342
1343         memcpy(cqc, param->cqc, sizeof(param->cqc));
1344
1345         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1346             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1347
1348         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1349
1350         MLX5_SET(cqc, cqc, c_eqn, eqn);
1351         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1352         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1353             PAGE_SHIFT);
1354         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1355
1356         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1357
1358         kvfree(in);
1359
1360         if (err)
1361                 return (err);
1362
1363         mlx5e_cq_arm(cq);
1364
1365         return (0);
1366 }
1367
1368 static void
1369 mlx5e_disable_cq(struct mlx5e_cq *cq)
1370 {
1371
1372         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1373 }
1374
1375 int
1376 mlx5e_open_cq(struct mlx5e_priv *priv,
1377     struct mlx5e_cq_param *param,
1378     struct mlx5e_cq *cq,
1379     mlx5e_cq_comp_t *comp,
1380     int eq_ix)
1381 {
1382         int err;
1383
1384         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1385         if (err)
1386                 return (err);
1387
1388         err = mlx5e_enable_cq(cq, param, eq_ix);
1389         if (err)
1390                 goto err_destroy_cq;
1391
1392         return (0);
1393
1394 err_destroy_cq:
1395         mlx5e_destroy_cq(cq);
1396
1397         return (err);
1398 }
1399
1400 void
1401 mlx5e_close_cq(struct mlx5e_cq *cq)
1402 {
1403         mlx5e_disable_cq(cq);
1404         mlx5e_destroy_cq(cq);
1405 }
1406
1407 static int
1408 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1409     struct mlx5e_channel_param *cparam)
1410 {
1411         int err;
1412         int tc;
1413
1414         for (tc = 0; tc < c->num_tc; tc++) {
1415                 /* open completion queue */
1416                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1417                     &mlx5e_tx_cq_comp, c->ix);
1418                 if (err)
1419                         goto err_close_tx_cqs;
1420         }
1421         return (0);
1422
1423 err_close_tx_cqs:
1424         for (tc--; tc >= 0; tc--)
1425                 mlx5e_close_cq(&c->sq[tc].cq);
1426
1427         return (err);
1428 }
1429
1430 static void
1431 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1432 {
1433         int tc;
1434
1435         for (tc = 0; tc < c->num_tc; tc++)
1436                 mlx5e_close_cq(&c->sq[tc].cq);
1437 }
1438
1439 static int
1440 mlx5e_open_sqs(struct mlx5e_channel *c,
1441     struct mlx5e_channel_param *cparam)
1442 {
1443         int err;
1444         int tc;
1445
1446         for (tc = 0; tc < c->num_tc; tc++) {
1447                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1448                 if (err)
1449                         goto err_close_sqs;
1450         }
1451
1452         return (0);
1453
1454 err_close_sqs:
1455         for (tc--; tc >= 0; tc--)
1456                 mlx5e_close_sq_wait(&c->sq[tc]);
1457
1458         return (err);
1459 }
1460
1461 static void
1462 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1463 {
1464         int tc;
1465
1466         for (tc = 0; tc < c->num_tc; tc++)
1467                 mlx5e_close_sq_wait(&c->sq[tc]);
1468 }
1469
1470 static void
1471 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1472 {
1473         int tc;
1474
1475         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1476
1477         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1478
1479         for (tc = 0; tc < c->num_tc; tc++) {
1480                 struct mlx5e_sq *sq = c->sq + tc;
1481
1482                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1483                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1484                     MTX_DEF);
1485
1486                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1487
1488                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1489
1490                 /* ensure the TX completion event factor is not zero */
1491                 if (sq->cev_factor == 0)
1492                         sq->cev_factor = 1;
1493         }
1494 }
1495
1496 static void
1497 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1498 {
1499         int tc;
1500
1501         mtx_destroy(&c->rq.mtx);
1502
1503         for (tc = 0; tc < c->num_tc; tc++) {
1504                 mtx_destroy(&c->sq[tc].lock);
1505                 mtx_destroy(&c->sq[tc].comp_lock);
1506         }
1507 }
1508
1509 static int
1510 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1511     struct mlx5e_channel_param *cparam,
1512     struct mlx5e_channel *volatile *cp)
1513 {
1514         struct mlx5e_channel *c;
1515         int err;
1516
1517         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1518         c->priv = priv;
1519         c->ix = ix;
1520         c->cpu = 0;
1521         c->ifp = priv->ifp;
1522         c->mkey_be = cpu_to_be32(priv->mr.key);
1523         c->num_tc = priv->num_tc;
1524
1525         /* init mutexes */
1526         mlx5e_chan_mtx_init(c);
1527
1528         /* open transmit completion queue */
1529         err = mlx5e_open_tx_cqs(c, cparam);
1530         if (err)
1531                 goto err_free;
1532
1533         /* open receive completion queue */
1534         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1535             &mlx5e_rx_cq_comp, c->ix);
1536         if (err)
1537                 goto err_close_tx_cqs;
1538
1539         err = mlx5e_open_sqs(c, cparam);
1540         if (err)
1541                 goto err_close_rx_cq;
1542
1543         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1544         if (err)
1545                 goto err_close_sqs;
1546
1547         /* store channel pointer */
1548         *cp = c;
1549
1550         /* poll receive queue initially */
1551         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1552
1553         return (0);
1554
1555 err_close_sqs:
1556         mlx5e_close_sqs_wait(c);
1557
1558 err_close_rx_cq:
1559         mlx5e_close_cq(&c->rq.cq);
1560
1561 err_close_tx_cqs:
1562         mlx5e_close_tx_cqs(c);
1563
1564 err_free:
1565         /* destroy mutexes */
1566         mlx5e_chan_mtx_destroy(c);
1567         free(c, M_MLX5EN);
1568         return (err);
1569 }
1570
1571 static void
1572 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1573 {
1574         struct mlx5e_channel *c = *pp;
1575
1576         /* check if channel is already closed */
1577         if (c == NULL)
1578                 return;
1579         mlx5e_close_rq(&c->rq);
1580 }
1581
1582 static void
1583 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1584 {
1585         struct mlx5e_channel *c = *pp;
1586
1587         /* check if channel is already closed */
1588         if (c == NULL)
1589                 return;
1590         /* ensure channel pointer is no longer used */
1591         *pp = NULL;
1592
1593         mlx5e_close_rq_wait(&c->rq);
1594         mlx5e_close_sqs_wait(c);
1595         mlx5e_close_cq(&c->rq.cq);
1596         mlx5e_close_tx_cqs(c);
1597         /* destroy mutexes */
1598         mlx5e_chan_mtx_destroy(c);
1599         free(c, M_MLX5EN);
1600 }
1601
1602 static void
1603 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1604     struct mlx5e_rq_param *param)
1605 {
1606         void *rqc = param->rqc;
1607         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1608
1609         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1610         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1611         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1612         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1613         MLX5_SET(wq, wq, pd, priv->pdn);
1614
1615         param->wq.buf_numa_node = 0;
1616         param->wq.db_numa_node = 0;
1617         param->wq.linear = 1;
1618 }
1619
1620 static void
1621 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1622     struct mlx5e_sq_param *param)
1623 {
1624         void *sqc = param->sqc;
1625         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1626
1627         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1628         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1629         MLX5_SET(wq, wq, pd, priv->pdn);
1630
1631         param->wq.buf_numa_node = 0;
1632         param->wq.db_numa_node = 0;
1633         param->wq.linear = 1;
1634 }
1635
1636 static void
1637 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1638     struct mlx5e_cq_param *param)
1639 {
1640         void *cqc = param->cqc;
1641
1642         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1643 }
1644
1645 static void
1646 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1647     struct mlx5e_cq_param *param)
1648 {
1649         void *cqc = param->cqc;
1650
1651
1652         /*
1653          * TODO The sysctl to control on/off is a bool value for now, which means
1654          * we only support CSUM, once HASH is implemnted we'll need to address that.
1655          */
1656         if (priv->params.cqe_zipping_en) {
1657                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1658                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1659         }
1660
1661         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1662         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1663         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1664
1665         switch (priv->params.rx_cq_moderation_mode) {
1666         case 0:
1667                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1668                 break;
1669         default:
1670                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1671                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1672                 else
1673                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1674                 break;
1675         }
1676
1677         mlx5e_build_common_cq_param(priv, param);
1678 }
1679
1680 static void
1681 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1682     struct mlx5e_cq_param *param)
1683 {
1684         void *cqc = param->cqc;
1685
1686         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1687         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1688         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1689
1690         switch (priv->params.tx_cq_moderation_mode) {
1691         case 0:
1692                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1693                 break;
1694         default:
1695                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1696                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1697                 else
1698                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1699                 break;
1700         }
1701
1702         mlx5e_build_common_cq_param(priv, param);
1703 }
1704
1705 static void
1706 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1707     struct mlx5e_channel_param *cparam)
1708 {
1709         memset(cparam, 0, sizeof(*cparam));
1710
1711         mlx5e_build_rq_param(priv, &cparam->rq);
1712         mlx5e_build_sq_param(priv, &cparam->sq);
1713         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1714         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1715 }
1716
1717 static int
1718 mlx5e_open_channels(struct mlx5e_priv *priv)
1719 {
1720         struct mlx5e_channel_param cparam;
1721         void *ptr;
1722         int err;
1723         int i;
1724         int j;
1725
1726         priv->channel = malloc(priv->params.num_channels *
1727             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1728
1729         mlx5e_build_channel_param(priv, &cparam);
1730         for (i = 0; i < priv->params.num_channels; i++) {
1731                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1732                 if (err)
1733                         goto err_close_channels;
1734         }
1735
1736         for (j = 0; j < priv->params.num_channels; j++) {
1737                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1738                 if (err)
1739                         goto err_close_channels;
1740         }
1741
1742         return (0);
1743
1744 err_close_channels:
1745         for (i--; i >= 0; i--) {
1746                 mlx5e_close_channel(&priv->channel[i]);
1747                 mlx5e_close_channel_wait(&priv->channel[i]);
1748         }
1749
1750         /* remove "volatile" attribute from "channel" pointer */
1751         ptr = __DECONST(void *, priv->channel);
1752         priv->channel = NULL;
1753
1754         free(ptr, M_MLX5EN);
1755
1756         return (err);
1757 }
1758
1759 static void
1760 mlx5e_close_channels(struct mlx5e_priv *priv)
1761 {
1762         void *ptr;
1763         int i;
1764
1765         if (priv->channel == NULL)
1766                 return;
1767
1768         for (i = 0; i < priv->params.num_channels; i++)
1769                 mlx5e_close_channel(&priv->channel[i]);
1770         for (i = 0; i < priv->params.num_channels; i++)
1771                 mlx5e_close_channel_wait(&priv->channel[i]);
1772
1773         /* remove "volatile" attribute from "channel" pointer */
1774         ptr = __DECONST(void *, priv->channel);
1775         priv->channel = NULL;
1776
1777         free(ptr, M_MLX5EN);
1778 }
1779
1780 static int
1781 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1782 {
1783         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1784             priv->params.tx_cq_moderation_usec,
1785             priv->params.tx_cq_moderation_pkts));
1786 }
1787
1788 static int
1789 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1790 {
1791         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1792             priv->params.rx_cq_moderation_usec,
1793             priv->params.rx_cq_moderation_pkts));
1794 }
1795
1796 static int
1797 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1798 {
1799         int err;
1800         int i;
1801
1802         if (c == NULL)
1803                 return (EINVAL);
1804
1805         err = mlx5e_refresh_rq_params(priv, &c->rq);
1806         if (err)
1807                 goto done;
1808
1809         for (i = 0; i != c->num_tc; i++) {
1810                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1811                 if (err)
1812                         goto done;
1813         }
1814 done:
1815         return (err);
1816 }
1817
1818 int
1819 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1820 {
1821         int i;
1822
1823         if (priv->channel == NULL)
1824                 return (EINVAL);
1825
1826         for (i = 0; i < priv->params.num_channels; i++) {
1827                 int err;
1828
1829                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1830                 if (err)
1831                         return (err);
1832         }
1833         return (0);
1834 }
1835
1836 static int
1837 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1838 {
1839         struct mlx5_core_dev *mdev = priv->mdev;
1840         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1841         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1842
1843         memset(in, 0, sizeof(in));
1844
1845         MLX5_SET(tisc, tisc, prio, tc);
1846         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1847
1848         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1849 }
1850
1851 static void
1852 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1853 {
1854         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1855 }
1856
1857 static int
1858 mlx5e_open_tises(struct mlx5e_priv *priv)
1859 {
1860         int num_tc = priv->num_tc;
1861         int err;
1862         int tc;
1863
1864         for (tc = 0; tc < num_tc; tc++) {
1865                 err = mlx5e_open_tis(priv, tc);
1866                 if (err)
1867                         goto err_close_tises;
1868         }
1869
1870         return (0);
1871
1872 err_close_tises:
1873         for (tc--; tc >= 0; tc--)
1874                 mlx5e_close_tis(priv, tc);
1875
1876         return (err);
1877 }
1878
1879 static void
1880 mlx5e_close_tises(struct mlx5e_priv *priv)
1881 {
1882         int num_tc = priv->num_tc;
1883         int tc;
1884
1885         for (tc = 0; tc < num_tc; tc++)
1886                 mlx5e_close_tis(priv, tc);
1887 }
1888
1889 static int
1890 mlx5e_open_rqt(struct mlx5e_priv *priv)
1891 {
1892         struct mlx5_core_dev *mdev = priv->mdev;
1893         u32 *in;
1894         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1895         void *rqtc;
1896         int inlen;
1897         int err;
1898         int sz;
1899         int i;
1900
1901         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1902
1903         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1904         in = mlx5_vzalloc(inlen);
1905         if (in == NULL)
1906                 return (-ENOMEM);
1907         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1908
1909         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1910         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1911
1912         for (i = 0; i < sz; i++) {
1913                 int ix;
1914 #ifdef RSS
1915                 ix = rss_get_indirection_to_bucket(i);
1916 #else
1917                 ix = i;
1918 #endif
1919                 /* ensure we don't overflow */
1920                 ix %= priv->params.num_channels;
1921                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1922         }
1923
1924         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1925
1926         memset(out, 0, sizeof(out));
1927         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1928         if (!err)
1929                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1930
1931         kvfree(in);
1932
1933         return (err);
1934 }
1935
1936 static void
1937 mlx5e_close_rqt(struct mlx5e_priv *priv)
1938 {
1939         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1940         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1941
1942         memset(in, 0, sizeof(in));
1943
1944         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1945         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1946
1947         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1948             sizeof(out));
1949 }
1950
1951 static void
1952 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1953 {
1954         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1955         __be32 *hkey;
1956
1957         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1958
1959 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1960
1961 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1962                           MLX5_HASH_FIELD_SEL_DST_IP)
1963
1964 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1965                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1966                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1967                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1968
1969 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1970                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1971                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1972
1973         if (priv->params.hw_lro_en) {
1974                 MLX5_SET(tirc, tirc, lro_enable_mask,
1975                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1976                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1977                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1978                     (priv->params.lro_wqe_sz -
1979                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1980                 /* TODO: add the option to choose timer value dynamically */
1981                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1982                     MLX5_CAP_ETH(priv->mdev,
1983                     lro_timer_supported_periods[2]));
1984         }
1985
1986         /* setup parameters for hashing TIR type, if any */
1987         switch (tt) {
1988         case MLX5E_TT_ANY:
1989                 MLX5_SET(tirc, tirc, disp_type,
1990                     MLX5_TIRC_DISP_TYPE_DIRECT);
1991                 MLX5_SET(tirc, tirc, inline_rqn,
1992                     priv->channel[0]->rq.rqn);
1993                 break;
1994         default:
1995                 MLX5_SET(tirc, tirc, disp_type,
1996                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1997                 MLX5_SET(tirc, tirc, indirect_table,
1998                     priv->rqtn);
1999                 MLX5_SET(tirc, tirc, rx_hash_fn,
2000                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2001                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2002 #ifdef RSS
2003                 /*
2004                  * The FreeBSD RSS implementation does currently not
2005                  * support symmetric Toeplitz hashes:
2006                  */
2007                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2008                 rss_getkey((uint8_t *)hkey);
2009 #else
2010                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2011                 hkey[0] = cpu_to_be32(0xD181C62C);
2012                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2013                 hkey[2] = cpu_to_be32(0x1983A2FC);
2014                 hkey[3] = cpu_to_be32(0x943E1ADB);
2015                 hkey[4] = cpu_to_be32(0xD9389E6B);
2016                 hkey[5] = cpu_to_be32(0xD1039C2C);
2017                 hkey[6] = cpu_to_be32(0xA74499AD);
2018                 hkey[7] = cpu_to_be32(0x593D56D9);
2019                 hkey[8] = cpu_to_be32(0xF3253C06);
2020                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2021 #endif
2022                 break;
2023         }
2024
2025         switch (tt) {
2026         case MLX5E_TT_IPV4_TCP:
2027                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2028                     MLX5_L3_PROT_TYPE_IPV4);
2029                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2030                     MLX5_L4_PROT_TYPE_TCP);
2031 #ifdef RSS
2032                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2033                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2034                             MLX5_HASH_IP);
2035                 } else
2036 #endif
2037                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2038                     MLX5_HASH_ALL);
2039                 break;
2040
2041         case MLX5E_TT_IPV6_TCP:
2042                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2043                     MLX5_L3_PROT_TYPE_IPV6);
2044                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2045                     MLX5_L4_PROT_TYPE_TCP);
2046 #ifdef RSS
2047                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2048                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2049                             MLX5_HASH_IP);
2050                 } else
2051 #endif
2052                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2053                     MLX5_HASH_ALL);
2054                 break;
2055
2056         case MLX5E_TT_IPV4_UDP:
2057                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2058                     MLX5_L3_PROT_TYPE_IPV4);
2059                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2060                     MLX5_L4_PROT_TYPE_UDP);
2061 #ifdef RSS
2062                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2063                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2064                             MLX5_HASH_IP);
2065                 } else
2066 #endif
2067                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2068                     MLX5_HASH_ALL);
2069                 break;
2070
2071         case MLX5E_TT_IPV6_UDP:
2072                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2073                     MLX5_L3_PROT_TYPE_IPV6);
2074                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2075                     MLX5_L4_PROT_TYPE_UDP);
2076 #ifdef RSS
2077                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2078                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2079                             MLX5_HASH_IP);
2080                 } else
2081 #endif
2082                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2083                     MLX5_HASH_ALL);
2084                 break;
2085
2086         case MLX5E_TT_IPV4_IPSEC_AH:
2087                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2088                     MLX5_L3_PROT_TYPE_IPV4);
2089                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2090                     MLX5_HASH_IP_IPSEC_SPI);
2091                 break;
2092
2093         case MLX5E_TT_IPV6_IPSEC_AH:
2094                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2095                     MLX5_L3_PROT_TYPE_IPV6);
2096                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2097                     MLX5_HASH_IP_IPSEC_SPI);
2098                 break;
2099
2100         case MLX5E_TT_IPV4_IPSEC_ESP:
2101                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2102                     MLX5_L3_PROT_TYPE_IPV4);
2103                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104                     MLX5_HASH_IP_IPSEC_SPI);
2105                 break;
2106
2107         case MLX5E_TT_IPV6_IPSEC_ESP:
2108                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109                     MLX5_L3_PROT_TYPE_IPV6);
2110                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2111                     MLX5_HASH_IP_IPSEC_SPI);
2112                 break;
2113
2114         case MLX5E_TT_IPV4:
2115                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2116                     MLX5_L3_PROT_TYPE_IPV4);
2117                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2118                     MLX5_HASH_IP);
2119                 break;
2120
2121         case MLX5E_TT_IPV6:
2122                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2123                     MLX5_L3_PROT_TYPE_IPV6);
2124                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2125                     MLX5_HASH_IP);
2126                 break;
2127
2128         default:
2129                 break;
2130         }
2131 }
2132
2133 static int
2134 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2135 {
2136         struct mlx5_core_dev *mdev = priv->mdev;
2137         u32 *in;
2138         void *tirc;
2139         int inlen;
2140         int err;
2141
2142         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2143         in = mlx5_vzalloc(inlen);
2144         if (in == NULL)
2145                 return (-ENOMEM);
2146         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2147
2148         mlx5e_build_tir_ctx(priv, tirc, tt);
2149
2150         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2151
2152         kvfree(in);
2153
2154         return (err);
2155 }
2156
2157 static void
2158 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2159 {
2160         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2161 }
2162
2163 static int
2164 mlx5e_open_tirs(struct mlx5e_priv *priv)
2165 {
2166         int err;
2167         int i;
2168
2169         for (i = 0; i < MLX5E_NUM_TT; i++) {
2170                 err = mlx5e_open_tir(priv, i);
2171                 if (err)
2172                         goto err_close_tirs;
2173         }
2174
2175         return (0);
2176
2177 err_close_tirs:
2178         for (i--; i >= 0; i--)
2179                 mlx5e_close_tir(priv, i);
2180
2181         return (err);
2182 }
2183
2184 static void
2185 mlx5e_close_tirs(struct mlx5e_priv *priv)
2186 {
2187         int i;
2188
2189         for (i = 0; i < MLX5E_NUM_TT; i++)
2190                 mlx5e_close_tir(priv, i);
2191 }
2192
2193 /*
2194  * SW MTU does not include headers,
2195  * HW MTU includes all headers and checksums.
2196  */
2197 static int
2198 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2199 {
2200         struct mlx5e_priv *priv = ifp->if_softc;
2201         struct mlx5_core_dev *mdev = priv->mdev;
2202         int hw_mtu;
2203         int err;
2204
2205         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2206         if (err) {
2207                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2208                     __func__, sw_mtu, err);
2209                 return (err);
2210         }
2211         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2212         if (err) {
2213                 if_printf(ifp, "Query port MTU, after setting new "
2214                     "MTU value, failed\n");
2215         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2216                 err = -E2BIG,
2217                 if_printf(ifp, "Port MTU %d is smaller than "
2218                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2219         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2220                 err = -EINVAL;
2221                 if_printf(ifp, "Port MTU %d is bigger than "
2222                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2223         }
2224         ifp->if_mtu = sw_mtu;
2225         return (err);
2226 }
2227
2228 int
2229 mlx5e_open_locked(struct ifnet *ifp)
2230 {
2231         struct mlx5e_priv *priv = ifp->if_softc;
2232         int err;
2233         u16 set_id;
2234
2235         /* check if already opened */
2236         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2237                 return (0);
2238
2239 #ifdef RSS
2240         if (rss_getnumbuckets() > priv->params.num_channels) {
2241                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2242                     "channels(%u) available\n", rss_getnumbuckets(),
2243                     priv->params.num_channels);
2244         }
2245 #endif
2246         err = mlx5e_open_tises(priv);
2247         if (err) {
2248                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2249                     __func__, err);
2250                 return (err);
2251         }
2252         err = mlx5_vport_alloc_q_counter(priv->mdev,
2253             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2254         if (err) {
2255                 if_printf(priv->ifp,
2256                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2257                     __func__, err);
2258                 goto err_close_tises;
2259         }
2260         /* store counter set ID */
2261         priv->counter_set_id = set_id;
2262
2263         err = mlx5e_open_channels(priv);
2264         if (err) {
2265                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2266                     __func__, err);
2267                 goto err_dalloc_q_counter;
2268         }
2269         err = mlx5e_open_rqt(priv);
2270         if (err) {
2271                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2272                     __func__, err);
2273                 goto err_close_channels;
2274         }
2275         err = mlx5e_open_tirs(priv);
2276         if (err) {
2277                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2278                     __func__, err);
2279                 goto err_close_rqls;
2280         }
2281         err = mlx5e_open_flow_table(priv);
2282         if (err) {
2283                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2284                     __func__, err);
2285                 goto err_close_tirs;
2286         }
2287         err = mlx5e_add_all_vlan_rules(priv);
2288         if (err) {
2289                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2290                     __func__, err);
2291                 goto err_close_flow_table;
2292         }
2293         set_bit(MLX5E_STATE_OPENED, &priv->state);
2294
2295         mlx5e_update_carrier(priv);
2296         mlx5e_set_rx_mode_core(priv);
2297
2298         return (0);
2299
2300 err_close_flow_table:
2301         mlx5e_close_flow_table(priv);
2302
2303 err_close_tirs:
2304         mlx5e_close_tirs(priv);
2305
2306 err_close_rqls:
2307         mlx5e_close_rqt(priv);
2308
2309 err_close_channels:
2310         mlx5e_close_channels(priv);
2311
2312 err_dalloc_q_counter:
2313         mlx5_vport_dealloc_q_counter(priv->mdev,
2314             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2315
2316 err_close_tises:
2317         mlx5e_close_tises(priv);
2318
2319         return (err);
2320 }
2321
2322 static void
2323 mlx5e_open(void *arg)
2324 {
2325         struct mlx5e_priv *priv = arg;
2326
2327         PRIV_LOCK(priv);
2328         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2329                 if_printf(priv->ifp,
2330                     "%s: Setting port status to up failed\n",
2331                     __func__);
2332
2333         mlx5e_open_locked(priv->ifp);
2334         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2335         PRIV_UNLOCK(priv);
2336 }
2337
2338 int
2339 mlx5e_close_locked(struct ifnet *ifp)
2340 {
2341         struct mlx5e_priv *priv = ifp->if_softc;
2342
2343         /* check if already closed */
2344         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2345                 return (0);
2346
2347         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2348
2349         mlx5e_set_rx_mode_core(priv);
2350         mlx5e_del_all_vlan_rules(priv);
2351         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2352         mlx5e_close_flow_table(priv);
2353         mlx5e_close_tirs(priv);
2354         mlx5e_close_rqt(priv);
2355         mlx5e_close_channels(priv);
2356         mlx5_vport_dealloc_q_counter(priv->mdev,
2357             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2358         mlx5e_close_tises(priv);
2359
2360         return (0);
2361 }
2362
2363 #if (__FreeBSD_version >= 1100000)
2364 static uint64_t
2365 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2366 {
2367         struct mlx5e_priv *priv = ifp->if_softc;
2368         u64 retval;
2369
2370         /* PRIV_LOCK(priv); XXX not allowed */
2371         switch (cnt) {
2372         case IFCOUNTER_IPACKETS:
2373                 retval = priv->stats.vport.rx_packets;
2374                 break;
2375         case IFCOUNTER_IERRORS:
2376                 retval = priv->stats.vport.rx_error_packets +
2377                     priv->stats.pport.alignment_err +
2378                     priv->stats.pport.check_seq_err +
2379                     priv->stats.pport.crc_align_errors +
2380                     priv->stats.pport.drop_events +
2381                     priv->stats.pport.in_range_len_errors +
2382                     priv->stats.pport.jabbers +
2383                     priv->stats.pport.out_of_range_len +
2384                     priv->stats.pport.oversize_pkts +
2385                     priv->stats.pport.symbol_err +
2386                     priv->stats.pport.too_long_errors +
2387                     priv->stats.pport.undersize_pkts +
2388                     priv->stats.pport.unsupported_op_rx;
2389                 break;
2390         case IFCOUNTER_IQDROPS:
2391                 retval = priv->stats.vport.rx_out_of_buffer;
2392                 break;
2393         case IFCOUNTER_OPACKETS:
2394                 retval = priv->stats.vport.tx_packets;
2395                 break;
2396         case IFCOUNTER_OERRORS:
2397                 retval = priv->stats.vport.tx_error_packets;
2398                 break;
2399         case IFCOUNTER_IBYTES:
2400                 retval = priv->stats.vport.rx_bytes;
2401                 break;
2402         case IFCOUNTER_OBYTES:
2403                 retval = priv->stats.vport.tx_bytes;
2404                 break;
2405         case IFCOUNTER_IMCASTS:
2406                 retval = priv->stats.vport.rx_multicast_packets;
2407                 break;
2408         case IFCOUNTER_OMCASTS:
2409                 retval = priv->stats.vport.tx_multicast_packets;
2410                 break;
2411         case IFCOUNTER_OQDROPS:
2412                 retval = priv->stats.vport.tx_queue_dropped;
2413                 break;
2414         case IFCOUNTER_COLLISIONS:
2415                 retval = priv->stats.pport.collisions;
2416                 break;
2417         default:
2418                 retval = if_get_counter_default(ifp, cnt);
2419                 break;
2420         }
2421         /* PRIV_UNLOCK(priv); XXX not allowed */
2422         return (retval);
2423 }
2424 #endif
2425
2426 static void
2427 mlx5e_set_rx_mode(struct ifnet *ifp)
2428 {
2429         struct mlx5e_priv *priv = ifp->if_softc;
2430
2431         schedule_work(&priv->set_rx_mode_work);
2432 }
2433
2434 static int
2435 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2436 {
2437         struct mlx5e_priv *priv;
2438         struct ifreq *ifr;
2439         struct ifi2creq i2c;
2440         int error = 0;
2441         int mask = 0;
2442         int size_read = 0;
2443         int module_num;
2444         int max_mtu;
2445         uint8_t read_addr;
2446
2447         priv = ifp->if_softc;
2448
2449         /* check if detaching */
2450         if (priv == NULL || priv->gone != 0)
2451                 return (ENXIO);
2452
2453         switch (command) {
2454         case SIOCSIFMTU:
2455                 ifr = (struct ifreq *)data;
2456
2457                 PRIV_LOCK(priv);
2458                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2459
2460                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2461                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2462                         int was_opened;
2463
2464                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2465                         if (was_opened)
2466                                 mlx5e_close_locked(ifp);
2467
2468                         /* set new MTU */
2469                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2470
2471                         if (was_opened)
2472                                 mlx5e_open_locked(ifp);
2473                 } else {
2474                         error = EINVAL;
2475                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2476                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2477                 }
2478                 PRIV_UNLOCK(priv);
2479                 break;
2480         case SIOCSIFFLAGS:
2481                 if ((ifp->if_flags & IFF_UP) &&
2482                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2483                         mlx5e_set_rx_mode(ifp);
2484                         break;
2485                 }
2486                 PRIV_LOCK(priv);
2487                 if (ifp->if_flags & IFF_UP) {
2488                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2489                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2490                                         mlx5e_open_locked(ifp);
2491                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2492                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2493                         }
2494                 } else {
2495                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2496                                 mlx5_set_port_status(priv->mdev,
2497                                     MLX5_PORT_DOWN);
2498                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2499                                         mlx5e_close_locked(ifp);
2500                                 mlx5e_update_carrier(priv);
2501                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2502                         }
2503                 }
2504                 PRIV_UNLOCK(priv);
2505                 break;
2506         case SIOCADDMULTI:
2507         case SIOCDELMULTI:
2508                 mlx5e_set_rx_mode(ifp);
2509                 break;
2510         case SIOCSIFMEDIA:
2511         case SIOCGIFMEDIA:
2512         case SIOCGIFXMEDIA:
2513                 ifr = (struct ifreq *)data;
2514                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2515                 break;
2516         case SIOCSIFCAP:
2517                 ifr = (struct ifreq *)data;
2518                 PRIV_LOCK(priv);
2519                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2520
2521                 if (mask & IFCAP_TXCSUM) {
2522                         ifp->if_capenable ^= IFCAP_TXCSUM;
2523                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2524
2525                         if (IFCAP_TSO4 & ifp->if_capenable &&
2526                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2527                                 ifp->if_capenable &= ~IFCAP_TSO4;
2528                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2529                                 if_printf(ifp,
2530                                     "tso4 disabled due to -txcsum.\n");
2531                         }
2532                 }
2533                 if (mask & IFCAP_TXCSUM_IPV6) {
2534                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2535                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2536
2537                         if (IFCAP_TSO6 & ifp->if_capenable &&
2538                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2539                                 ifp->if_capenable &= ~IFCAP_TSO6;
2540                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2541                                 if_printf(ifp,
2542                                     "tso6 disabled due to -txcsum6.\n");
2543                         }
2544                 }
2545                 if (mask & IFCAP_RXCSUM)
2546                         ifp->if_capenable ^= IFCAP_RXCSUM;
2547                 if (mask & IFCAP_RXCSUM_IPV6)
2548                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2549                 if (mask & IFCAP_TSO4) {
2550                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2551                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2552                                 if_printf(ifp, "enable txcsum first.\n");
2553                                 error = EAGAIN;
2554                                 goto out;
2555                         }
2556                         ifp->if_capenable ^= IFCAP_TSO4;
2557                         ifp->if_hwassist ^= CSUM_IP_TSO;
2558                 }
2559                 if (mask & IFCAP_TSO6) {
2560                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2561                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2562                                 if_printf(ifp, "enable txcsum6 first.\n");
2563                                 error = EAGAIN;
2564                                 goto out;
2565                         }
2566                         ifp->if_capenable ^= IFCAP_TSO6;
2567                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2568                 }
2569                 if (mask & IFCAP_VLAN_HWFILTER) {
2570                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2571                                 mlx5e_disable_vlan_filter(priv);
2572                         else
2573                                 mlx5e_enable_vlan_filter(priv);
2574
2575                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2576                 }
2577                 if (mask & IFCAP_VLAN_HWTAGGING)
2578                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2579                 if (mask & IFCAP_WOL_MAGIC)
2580                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2581
2582                 VLAN_CAPABILITIES(ifp);
2583                 /* turn off LRO means also turn of HW LRO - if it's on */
2584                 if (mask & IFCAP_LRO) {
2585                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2586                         bool need_restart = false;
2587
2588                         ifp->if_capenable ^= IFCAP_LRO;
2589                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2590                                 if (priv->params.hw_lro_en) {
2591                                         priv->params.hw_lro_en = false;
2592                                         need_restart = true;
2593                                         /* Not sure this is the correct way */
2594                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2595                                 }
2596                         }
2597                         if (was_opened && need_restart) {
2598                                 mlx5e_close_locked(ifp);
2599                                 mlx5e_open_locked(ifp);
2600                         }
2601                 }
2602 out:
2603                 PRIV_UNLOCK(priv);
2604                 break;
2605
2606         case SIOCGI2C:
2607                 ifr = (struct ifreq *)data;
2608
2609                 /*
2610                  * Copy from the user-space address ifr_data to the
2611                  * kernel-space address i2c
2612                  */
2613                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2614                 if (error)
2615                         break;
2616
2617                 if (i2c.len > sizeof(i2c.data)) {
2618                         error = EINVAL;
2619                         break;
2620                 }
2621
2622                 PRIV_LOCK(priv);
2623                 /* Get module_num which is required for the query_eeprom */
2624                 error = mlx5_query_module_num(priv->mdev, &module_num);
2625                 if (error) {
2626                         if_printf(ifp, "Query module num failed, eeprom "
2627                             "reading is not supported\n");
2628                         error = EINVAL;
2629                         goto err_i2c;
2630                 }
2631                 /* Check if module is present before doing an access */
2632                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2633                     MLX5_MODULE_STATUS_PLUGGED) {
2634                         error = EINVAL;
2635                         goto err_i2c;
2636                 }
2637                 /*
2638                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2639                  * The internal conversion is as follows:
2640                  */
2641                 if (i2c.dev_addr == 0xA0)
2642                         read_addr = MLX5E_I2C_ADDR_LOW;
2643                 else if (i2c.dev_addr == 0xA2)
2644                         read_addr = MLX5E_I2C_ADDR_HIGH;
2645                 else {
2646                         if_printf(ifp, "Query eeprom failed, "
2647                             "Invalid Address: %X\n", i2c.dev_addr);
2648                         error = EINVAL;
2649                         goto err_i2c;
2650                 }
2651                 error = mlx5_query_eeprom(priv->mdev,
2652                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2653                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2654                     (uint32_t *)i2c.data, &size_read);
2655                 if (error) {
2656                         if_printf(ifp, "Query eeprom failed, eeprom "
2657                             "reading is not supported\n");
2658                         error = EINVAL;
2659                         goto err_i2c;
2660                 }
2661
2662                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2663                         error = mlx5_query_eeprom(priv->mdev,
2664                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2665                             (uint32_t)(i2c.offset + size_read),
2666                             (uint32_t)(i2c.len - size_read), module_num,
2667                             (uint32_t *)(i2c.data + size_read), &size_read);
2668                 }
2669                 if (error) {
2670                         if_printf(ifp, "Query eeprom failed, eeprom "
2671                             "reading is not supported\n");
2672                         error = EINVAL;
2673                         goto err_i2c;
2674                 }
2675
2676                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2677 err_i2c:
2678                 PRIV_UNLOCK(priv);
2679                 break;
2680
2681         default:
2682                 error = ether_ioctl(ifp, command, data);
2683                 break;
2684         }
2685         return (error);
2686 }
2687
2688 static int
2689 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2690 {
2691         /*
2692          * TODO: uncoment once FW really sets all these bits if
2693          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2694          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2695          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2696          * -ENOTSUPP;
2697          */
2698
2699         /* TODO: add more must-to-have features */
2700
2701         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2702                 return (-ENODEV);
2703
2704         return (0);
2705 }
2706
2707 static void
2708 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2709     struct mlx5e_priv *priv,
2710     int num_comp_vectors)
2711 {
2712         /*
2713          * TODO: Consider link speed for setting "log_sq_size",
2714          * "log_rq_size" and "cq_moderation_xxx":
2715          */
2716         priv->params.log_sq_size =
2717             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2718         priv->params.log_rq_size =
2719             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2720         priv->params.rx_cq_moderation_usec =
2721             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2722             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2723             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2724         priv->params.rx_cq_moderation_mode =
2725             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2726         priv->params.rx_cq_moderation_pkts =
2727             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2728         priv->params.tx_cq_moderation_usec =
2729             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2730         priv->params.tx_cq_moderation_pkts =
2731             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2732         priv->params.min_rx_wqes =
2733             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2734         priv->params.rx_hash_log_tbl_sz =
2735             (order_base_2(num_comp_vectors) >
2736             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2737             order_base_2(num_comp_vectors) :
2738             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2739         priv->params.num_tc = 1;
2740         priv->params.default_vlan_prio = 0;
2741         priv->counter_set_id = -1;
2742
2743         /*
2744          * hw lro is currently defaulted to off. when it won't anymore we
2745          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2746          */
2747         priv->params.hw_lro_en = false;
2748         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2749
2750         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2751
2752         priv->mdev = mdev;
2753         priv->params.num_channels = num_comp_vectors;
2754         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2755         priv->queue_mapping_channel_mask =
2756             roundup_pow_of_two(num_comp_vectors) - 1;
2757         priv->num_tc = priv->params.num_tc;
2758         priv->default_vlan_prio = priv->params.default_vlan_prio;
2759
2760         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2761         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2762         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2763 }
2764
2765 static int
2766 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2767     struct mlx5_core_mr *mr)
2768 {
2769         struct ifnet *ifp = priv->ifp;
2770         struct mlx5_core_dev *mdev = priv->mdev;
2771         struct mlx5_create_mkey_mbox_in *in;
2772         int err;
2773
2774         in = mlx5_vzalloc(sizeof(*in));
2775         if (in == NULL) {
2776                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2777                 return (-ENOMEM);
2778         }
2779         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2780             MLX5_PERM_LOCAL_READ |
2781             MLX5_ACCESS_MODE_PA;
2782         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2783         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2784
2785         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2786             NULL);
2787         if (err)
2788                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2789                     __func__, err);
2790
2791         kvfree(in);
2792
2793         return (err);
2794 }
2795
2796 static const char *mlx5e_vport_stats_desc[] = {
2797         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2798 };
2799
2800 static const char *mlx5e_pport_stats_desc[] = {
2801         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2802 };
2803
2804 static void
2805 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2806 {
2807         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2808         sx_init(&priv->state_lock, "mlx5state");
2809         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2810         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2811 }
2812
2813 static void
2814 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2815 {
2816         mtx_destroy(&priv->async_events_mtx);
2817         sx_destroy(&priv->state_lock);
2818 }
2819
2820 static int
2821 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2822 {
2823         /*
2824          * %d.%d%.d the string format.
2825          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2826          * We need at most 5 chars to store that.
2827          * It also has: two "." and NULL at the end, which means we need 18
2828          * (5*3 + 3) chars at most.
2829          */
2830         char fw[18];
2831         struct mlx5e_priv *priv = arg1;
2832         int error;
2833
2834         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2835             fw_rev_sub(priv->mdev));
2836         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2837         return (error);
2838 }
2839
2840 static void
2841 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2842 {
2843         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2844             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2845             sysctl_firmware, "A", "HCA firmware version");
2846
2847         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2848             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2849             "Board ID");
2850 }
2851
2852 static void
2853 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2854 {
2855 #if (__FreeBSD_version < 1100000)
2856         char path[64];
2857
2858 #endif
2859         /* Only receiving pauseframes is enabled by default */
2860         priv->params.tx_pauseframe_control = 0;
2861         priv->params.rx_pauseframe_control = 1;
2862
2863 #if (__FreeBSD_version < 1100000)
2864         /* compute path for sysctl */
2865         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2866             device_get_unit(priv->mdev->pdev->dev.bsddev));
2867
2868         /* try to fetch tunable, if any */
2869         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2870
2871         /* compute path for sysctl */
2872         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2873             device_get_unit(priv->mdev->pdev->dev.bsddev));
2874
2875         /* try to fetch tunable, if any */
2876         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2877 #endif
2878
2879         /* register pausframe SYSCTLs */
2880         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2881             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2882             &priv->params.tx_pauseframe_control, 0,
2883             "Set to enable TX pause frames. Clear to disable.");
2884
2885         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2886             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2887             &priv->params.rx_pauseframe_control, 0,
2888             "Set to enable RX pause frames. Clear to disable.");
2889
2890         /* range check */
2891         priv->params.tx_pauseframe_control =
2892             priv->params.tx_pauseframe_control ? 1 : 0;
2893         priv->params.rx_pauseframe_control =
2894             priv->params.rx_pauseframe_control ? 1 : 0;
2895
2896         /* update firmware */
2897         mlx5_set_port_pause(priv->mdev, 1,
2898             priv->params.rx_pauseframe_control,
2899             priv->params.tx_pauseframe_control);
2900 }
2901
2902 static void *
2903 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2904 {
2905         static volatile int mlx5_en_unit;
2906         struct ifnet *ifp;
2907         struct mlx5e_priv *priv;
2908         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2909         struct sysctl_oid_list *child;
2910         int ncv = mdev->priv.eq_table.num_comp_vectors;
2911         char unit[16];
2912         int err;
2913         int i;
2914         u32 eth_proto_cap;
2915
2916         if (mlx5e_check_required_hca_cap(mdev)) {
2917                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2918                 return (NULL);
2919         }
2920         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2921         mlx5e_priv_mtx_init(priv);
2922
2923         ifp = priv->ifp = if_alloc(IFT_ETHER);
2924         if (ifp == NULL) {
2925                 mlx5_core_err(mdev, "if_alloc() failed\n");
2926                 goto err_free_priv;
2927         }
2928         ifp->if_softc = priv;
2929         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2930         ifp->if_mtu = ETHERMTU;
2931         ifp->if_init = mlx5e_open;
2932         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2933         ifp->if_ioctl = mlx5e_ioctl;
2934         ifp->if_transmit = mlx5e_xmit;
2935         ifp->if_qflush = if_qflush;
2936 #if (__FreeBSD_version >= 1100000)
2937         ifp->if_get_counter = mlx5e_get_counter;
2938 #endif
2939         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2940         /*
2941          * Set driver features
2942          */
2943         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2944         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2945         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2946         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2947         ifp->if_capabilities |= IFCAP_LRO;
2948         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2949         ifp->if_capabilities |= IFCAP_HWSTATS;
2950
2951         /* set TSO limits so that we don't have to drop TX packets */
2952         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2953         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2954         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2955
2956         ifp->if_capenable = ifp->if_capabilities;
2957         ifp->if_hwassist = 0;
2958         if (ifp->if_capenable & IFCAP_TSO)
2959                 ifp->if_hwassist |= CSUM_TSO;
2960         if (ifp->if_capenable & IFCAP_TXCSUM)
2961                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2962         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2963                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2964
2965         /* ifnet sysctl tree */
2966         sysctl_ctx_init(&priv->sysctl_ctx);
2967         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2968             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2969         if (priv->sysctl_ifnet == NULL) {
2970                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2971                 goto err_free_sysctl;
2972         }
2973         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2974         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2975             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2976         if (priv->sysctl_ifnet == NULL) {
2977                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2978                 goto err_free_sysctl;
2979         }
2980
2981         /* HW sysctl tree */
2982         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2983         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2984             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2985         if (priv->sysctl_hw == NULL) {
2986                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2987                 goto err_free_sysctl;
2988         }
2989         mlx5e_build_ifp_priv(mdev, priv, ncv);
2990         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2991         if (err) {
2992                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2993                     __func__, err);
2994                 goto err_free_sysctl;
2995         }
2996         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2997         if (err) {
2998                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2999                     __func__, err);
3000                 goto err_unmap_free_uar;
3001         }
3002         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3003         if (err) {
3004                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3005                     __func__, err);
3006                 goto err_dealloc_pd;
3007         }
3008         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3009         if (err) {
3010                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3011                     __func__, err);
3012                 goto err_dealloc_transport_domain;
3013         }
3014         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3015
3016         /* check if we should generate a random MAC address */
3017         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3018             is_zero_ether_addr(dev_addr)) {
3019                 random_ether_addr(dev_addr);
3020                 if_printf(ifp, "Assigned random MAC address\n");
3021         }
3022
3023         /* set default MTU */
3024         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3025
3026         /* Set desc */
3027         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3028
3029         /* Set default media status */
3030         priv->media_status_last = IFM_AVALID;
3031         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3032             IFM_ETH_RXPAUSE | IFM_FDX;
3033
3034         /* setup default pauseframes configuration */
3035         mlx5e_setup_pauseframes(priv);
3036
3037         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3038         if (err) {
3039                 eth_proto_cap = 0;
3040                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3041                     __func__, err);
3042         }
3043
3044         /* Setup supported medias */
3045         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3046             mlx5e_media_change, mlx5e_media_status);
3047
3048         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3049                 if (mlx5e_mode_table[i].baudrate == 0)
3050                         continue;
3051                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3052                         ifmedia_add(&priv->media,
3053                             mlx5e_mode_table[i].subtype |
3054                             IFM_ETHER, 0, NULL);
3055                         ifmedia_add(&priv->media,
3056                             mlx5e_mode_table[i].subtype |
3057                             IFM_ETHER | IFM_FDX |
3058                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3059                 }
3060         }
3061
3062         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3063         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3064             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3065
3066         /* Set autoselect by default */
3067         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3068             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3069         ether_ifattach(ifp, dev_addr);
3070
3071         /* Register for VLAN events */
3072         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3073             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3074         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3075             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3076
3077         /* Link is down by default */
3078         if_link_state_change(ifp, LINK_STATE_DOWN);
3079
3080         mlx5e_enable_async_events(priv);
3081
3082         mlx5e_add_hw_stats(priv);
3083
3084         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3085             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3086             priv->stats.vport.arg);
3087
3088         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3089             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3090             priv->stats.pport.arg);
3091
3092         mlx5e_create_ethtool(priv);
3093
3094         mtx_lock(&priv->async_events_mtx);
3095         mlx5e_update_stats(priv);
3096         mtx_unlock(&priv->async_events_mtx);
3097
3098         return (priv);
3099
3100 err_dealloc_transport_domain:
3101         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3102
3103 err_dealloc_pd:
3104         mlx5_core_dealloc_pd(mdev, priv->pdn);
3105
3106 err_unmap_free_uar:
3107         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3108
3109 err_free_sysctl:
3110         sysctl_ctx_free(&priv->sysctl_ctx);
3111
3112         if_free(ifp);
3113
3114 err_free_priv:
3115         mlx5e_priv_mtx_destroy(priv);
3116         free(priv, M_MLX5EN);
3117         return (NULL);
3118 }
3119
3120 static void
3121 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3122 {
3123         struct mlx5e_priv *priv = vpriv;
3124         struct ifnet *ifp = priv->ifp;
3125
3126         /* don't allow more IOCTLs */
3127         priv->gone = 1;
3128
3129         /*
3130          * Clear the device description to avoid use after free,
3131          * because the bsddev is not destroyed when this module is
3132          * unloaded:
3133          */
3134         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3135
3136         /* XXX wait a bit to allow IOCTL handlers to complete */
3137         pause("W", hz);
3138
3139         /* stop watchdog timer */
3140         callout_drain(&priv->watchdog);
3141
3142         if (priv->vlan_attach != NULL)
3143                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3144         if (priv->vlan_detach != NULL)
3145                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3146
3147         /* make sure device gets closed */
3148         PRIV_LOCK(priv);
3149         mlx5e_close_locked(ifp);
3150         PRIV_UNLOCK(priv);
3151
3152         /* unregister device */
3153         ifmedia_removeall(&priv->media);
3154         ether_ifdetach(ifp);
3155         if_free(ifp);
3156
3157         /* destroy all remaining sysctl nodes */
3158         if (priv->sysctl_debug)
3159                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3160         sysctl_ctx_free(&priv->stats.vport.ctx);
3161         sysctl_ctx_free(&priv->stats.pport.ctx);
3162         sysctl_ctx_free(&priv->sysctl_ctx);
3163
3164         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3165         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3166         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3167         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3168         mlx5e_disable_async_events(priv);
3169         flush_scheduled_work();
3170         mlx5e_priv_mtx_destroy(priv);
3171         free(priv, M_MLX5EN);
3172 }
3173
3174 static void *
3175 mlx5e_get_ifp(void *vpriv)
3176 {
3177         struct mlx5e_priv *priv = vpriv;
3178
3179         return (priv->ifp);
3180 }
3181
3182 static struct mlx5_interface mlx5e_interface = {
3183         .add = mlx5e_create_ifp,
3184         .remove = mlx5e_destroy_ifp,
3185         .event = mlx5e_async_event,
3186         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3187         .get_dev = mlx5e_get_ifp,
3188 };
3189
3190 void
3191 mlx5e_init(void)
3192 {
3193         mlx5_register_interface(&mlx5e_interface);
3194 }
3195
3196 void
3197 mlx5e_cleanup(void)
3198 {
3199         mlx5_unregister_interface(&mlx5e_interface);
3200 }
3201
3202 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3203 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3204
3205 #if (__FreeBSD_version >= 1100000)
3206 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3207 #endif
3208 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3209 MODULE_VERSION(mlx5en, 1);