2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_channel_param {
38 struct mlx5e_rq_param rq;
39 struct mlx5e_sq_param sq;
40 struct mlx5e_cq_param rx_cq;
41 struct mlx5e_cq_param tx_cq;
47 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
49 [MLX5E_1000BASE_CX_SGMII] = {
50 .subtype = IFM_1000_CX_SGMII,
51 .baudrate = IF_Mbps(1000ULL),
53 [MLX5E_1000BASE_KX] = {
54 .subtype = IFM_1000_KX,
55 .baudrate = IF_Mbps(1000ULL),
57 [MLX5E_10GBASE_CX4] = {
58 .subtype = IFM_10G_CX4,
59 .baudrate = IF_Gbps(10ULL),
61 [MLX5E_10GBASE_KX4] = {
62 .subtype = IFM_10G_KX4,
63 .baudrate = IF_Gbps(10ULL),
65 [MLX5E_10GBASE_KR] = {
66 .subtype = IFM_10G_KR,
67 .baudrate = IF_Gbps(10ULL),
69 [MLX5E_20GBASE_KR2] = {
70 .subtype = IFM_20G_KR2,
71 .baudrate = IF_Gbps(20ULL),
73 [MLX5E_40GBASE_CR4] = {
74 .subtype = IFM_40G_CR4,
75 .baudrate = IF_Gbps(40ULL),
77 [MLX5E_40GBASE_KR4] = {
78 .subtype = IFM_40G_KR4,
79 .baudrate = IF_Gbps(40ULL),
81 [MLX5E_56GBASE_R4] = {
82 .subtype = IFM_56G_R4,
83 .baudrate = IF_Gbps(56ULL),
85 [MLX5E_10GBASE_CR] = {
86 .subtype = IFM_10G_CR1,
87 .baudrate = IF_Gbps(10ULL),
89 [MLX5E_10GBASE_SR] = {
90 .subtype = IFM_10G_SR,
91 .baudrate = IF_Gbps(10ULL),
93 [MLX5E_10GBASE_ER] = {
94 .subtype = IFM_10G_ER,
95 .baudrate = IF_Gbps(10ULL),
97 [MLX5E_40GBASE_SR4] = {
98 .subtype = IFM_40G_SR4,
99 .baudrate = IF_Gbps(40ULL),
101 [MLX5E_40GBASE_LR4] = {
102 .subtype = IFM_40G_LR4,
103 .baudrate = IF_Gbps(40ULL),
105 [MLX5E_100GBASE_CR4] = {
106 .subtype = IFM_100G_CR4,
107 .baudrate = IF_Gbps(100ULL),
109 [MLX5E_100GBASE_SR4] = {
110 .subtype = IFM_100G_SR4,
111 .baudrate = IF_Gbps(100ULL),
113 [MLX5E_100GBASE_KR4] = {
114 .subtype = IFM_100G_KR4,
115 .baudrate = IF_Gbps(100ULL),
117 [MLX5E_100GBASE_LR4] = {
118 .subtype = IFM_100G_LR4,
119 .baudrate = IF_Gbps(100ULL),
121 [MLX5E_100BASE_TX] = {
122 .subtype = IFM_100_TX,
123 .baudrate = IF_Mbps(100ULL),
125 [MLX5E_1000BASE_T] = {
126 .subtype = IFM_1000_T,
127 .baudrate = IF_Mbps(1000ULL),
129 [MLX5E_10GBASE_T] = {
130 .subtype = IFM_10G_T,
131 .baudrate = IF_Gbps(10ULL),
133 [MLX5E_25GBASE_CR] = {
134 .subtype = IFM_25G_CR,
135 .baudrate = IF_Gbps(25ULL),
137 [MLX5E_25GBASE_KR] = {
138 .subtype = IFM_25G_KR,
139 .baudrate = IF_Gbps(25ULL),
141 [MLX5E_25GBASE_SR] = {
142 .subtype = IFM_25G_SR,
143 .baudrate = IF_Gbps(25ULL),
145 [MLX5E_50GBASE_CR2] = {
146 .subtype = IFM_50G_CR2,
147 .baudrate = IF_Gbps(50ULL),
149 [MLX5E_50GBASE_KR2] = {
150 .subtype = IFM_50G_KR2,
151 .baudrate = IF_Gbps(50ULL),
155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
157 static SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "MLX5 driver parameters");
160 mlx5e_update_carrier(struct mlx5e_priv *priv)
162 struct mlx5_core_dev *mdev = priv->mdev;
163 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
169 port_state = mlx5_query_vport_state(mdev,
170 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
172 if (port_state == VPORT_STATE_UP) {
173 priv->media_status_last |= IFM_ACTIVE;
175 priv->media_status_last &= ~IFM_ACTIVE;
176 priv->media_active_last = IFM_ETHER;
177 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
181 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
183 priv->media_active_last = IFM_ETHER;
184 priv->ifp->if_baudrate = 1;
185 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
189 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
191 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
192 if (mlx5e_mode_table[i].baudrate == 0)
194 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
195 priv->ifp->if_baudrate =
196 mlx5e_mode_table[i].baudrate;
197 priv->media_active_last =
198 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
201 if_link_state_change(priv->ifp, LINK_STATE_UP);
205 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
207 struct mlx5e_priv *priv = dev->if_softc;
209 ifmr->ifm_status = priv->media_status_last;
210 ifmr->ifm_active = priv->media_active_last |
211 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
212 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
217 mlx5e_find_link_mode(u32 subtype)
222 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
223 if (mlx5e_mode_table[i].baudrate == 0)
225 if (mlx5e_mode_table[i].subtype == subtype)
226 link_mode |= MLX5E_PROT_MASK(i);
233 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
235 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
236 priv->params.rx_pauseframe_control,
237 priv->params.tx_pauseframe_control,
238 priv->params.rx_priority_flow_control,
239 priv->params.tx_priority_flow_control));
243 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
247 if (priv->params.rx_pauseframe_control ||
248 priv->params.tx_pauseframe_control) {
250 "Global pauseframes must be disabled before enabling PFC.\n");
253 error = mlx5e_set_port_pause_and_pfc(priv);
259 mlx5e_media_change(struct ifnet *dev)
261 struct mlx5e_priv *priv = dev->if_softc;
262 struct mlx5_core_dev *mdev = priv->mdev;
269 locked = PRIV_LOCKED(priv);
273 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
277 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
279 /* query supported capabilities */
280 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
282 if_printf(dev, "Query port media capability failed\n");
285 /* check for autoselect */
286 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
287 link_mode = eth_proto_cap;
288 if (link_mode == 0) {
289 if_printf(dev, "Port media capability is zero\n");
294 link_mode = link_mode & eth_proto_cap;
295 if (link_mode == 0) {
296 if_printf(dev, "Not supported link mode requested\n");
301 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
302 /* check if PFC is enabled */
303 if (priv->params.rx_priority_flow_control ||
304 priv->params.tx_priority_flow_control) {
305 if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
310 /* update pauseframe control bits */
311 priv->params.rx_pauseframe_control =
312 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
313 priv->params.tx_pauseframe_control =
314 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
316 /* check if device is opened */
317 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
319 /* reconfigure the hardware */
320 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
321 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
322 error = -mlx5e_set_port_pause_and_pfc(priv);
324 mlx5_set_port_status(mdev, MLX5_PORT_UP);
333 mlx5e_update_carrier_work(struct work_struct *work)
335 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
336 update_carrier_work);
339 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
340 mlx5e_update_carrier(priv);
345 * This function reads the physical port counters from the firmware
346 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
347 * macros. The output is converted from big-endian 64-bit values into
348 * host endian ones and stored in the "priv->stats.pport" structure.
351 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
353 struct mlx5_core_dev *mdev = priv->mdev;
354 struct mlx5e_pport_stats *s = &priv->stats.pport;
355 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
359 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
364 /* allocate firmware request structures */
365 in = mlx5_vzalloc(sz);
366 out = mlx5_vzalloc(sz);
367 if (in == NULL || out == NULL)
371 * Get pointer to the 64-bit counter set which is located at a
372 * fixed offset in the output firmware request structure:
374 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
376 MLX5_SET(ppcnt_reg, in, local_port, 1);
378 /* read IEEE802_3 counter group using predefined counter layout */
379 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
380 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
381 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
382 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
383 s->arg[y] = be64toh(ptr[x]);
385 /* read RFC2819 counter group using predefined counter layout */
386 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
387 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
388 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
389 s->arg[y] = be64toh(ptr[x]);
390 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
391 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
392 s_debug->arg[y] = be64toh(ptr[x]);
394 /* read RFC2863 counter group using predefined counter layout */
395 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
396 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
397 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
398 s_debug->arg[y] = be64toh(ptr[x]);
400 /* read physical layer stats counter group using predefined counter layout */
401 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
402 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
403 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
404 s_debug->arg[y] = be64toh(ptr[x]);
406 /* read per-priority counters */
407 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
409 /* iterate all the priorities */
410 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
411 MLX5_SET(ppcnt_reg, in, prio_tc, z);
412 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
414 /* read per priority stats counter group using predefined counter layout */
415 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
416 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
417 s->arg[y] = be64toh(ptr[x]);
420 /* free firmware request structures */
426 * This function is called regularly to collect all statistics
427 * counters from the firmware. The values can be viewed through the
428 * sysctl interface. Execution is serialized using the priv's global
429 * configuration lock.
432 mlx5e_update_stats_work(struct work_struct *work)
434 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
436 struct mlx5_core_dev *mdev = priv->mdev;
437 struct mlx5e_vport_stats *s = &priv->stats.vport;
438 struct mlx5e_rq_stats *rq_stats;
439 struct mlx5e_sq_stats *sq_stats;
440 struct buf_ring *sq_br;
441 #if (__FreeBSD_version < 1100000)
442 struct ifnet *ifp = priv->ifp;
445 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
447 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
450 u64 tx_queue_dropped = 0;
451 u64 tx_defragged = 0;
452 u64 tx_offload_none = 0;
455 u64 sw_lro_queued = 0;
456 u64 sw_lro_flushed = 0;
457 u64 rx_csum_none = 0;
459 u32 rx_out_of_buffer = 0;
464 out = mlx5_vzalloc(outlen);
467 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
470 /* Collect firts the SW counters and then HW for consistency */
471 for (i = 0; i < priv->params.num_channels; i++) {
472 struct mlx5e_rq *rq = &priv->channel[i]->rq;
474 rq_stats = &priv->channel[i]->rq.stats;
476 /* collect stats from LRO */
477 rq_stats->sw_lro_queued = rq->lro.lro_queued;
478 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
479 sw_lro_queued += rq_stats->sw_lro_queued;
480 sw_lro_flushed += rq_stats->sw_lro_flushed;
481 lro_packets += rq_stats->lro_packets;
482 lro_bytes += rq_stats->lro_bytes;
483 rx_csum_none += rq_stats->csum_none;
484 rx_wqe_err += rq_stats->wqe_err;
486 for (j = 0; j < priv->num_tc; j++) {
487 sq_stats = &priv->channel[i]->sq[j].stats;
488 sq_br = priv->channel[i]->sq[j].br;
490 tso_packets += sq_stats->tso_packets;
491 tso_bytes += sq_stats->tso_bytes;
492 tx_queue_dropped += sq_stats->dropped;
494 tx_queue_dropped += sq_br->br_drops;
495 tx_defragged += sq_stats->defragged;
496 tx_offload_none += sq_stats->csum_offload_none;
500 /* update counters */
501 s->tso_packets = tso_packets;
502 s->tso_bytes = tso_bytes;
503 s->tx_queue_dropped = tx_queue_dropped;
504 s->tx_defragged = tx_defragged;
505 s->lro_packets = lro_packets;
506 s->lro_bytes = lro_bytes;
507 s->sw_lro_queued = sw_lro_queued;
508 s->sw_lro_flushed = sw_lro_flushed;
509 s->rx_csum_none = rx_csum_none;
510 s->rx_wqe_err = rx_wqe_err;
513 memset(in, 0, sizeof(in));
515 MLX5_SET(query_vport_counter_in, in, opcode,
516 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
517 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
518 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
520 memset(out, 0, outlen);
522 /* get number of out-of-buffer drops first */
523 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
527 /* accumulate difference into a 64-bit counter */
528 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
529 s->rx_out_of_buffer_prev = rx_out_of_buffer;
531 /* get port statistics */
532 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
535 #define MLX5_GET_CTR(out, x) \
536 MLX5_GET64(query_vport_counter_out, out, x)
538 s->rx_error_packets =
539 MLX5_GET_CTR(out, received_errors.packets);
541 MLX5_GET_CTR(out, received_errors.octets);
542 s->tx_error_packets =
543 MLX5_GET_CTR(out, transmit_errors.packets);
545 MLX5_GET_CTR(out, transmit_errors.octets);
547 s->rx_unicast_packets =
548 MLX5_GET_CTR(out, received_eth_unicast.packets);
549 s->rx_unicast_bytes =
550 MLX5_GET_CTR(out, received_eth_unicast.octets);
551 s->tx_unicast_packets =
552 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
553 s->tx_unicast_bytes =
554 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
556 s->rx_multicast_packets =
557 MLX5_GET_CTR(out, received_eth_multicast.packets);
558 s->rx_multicast_bytes =
559 MLX5_GET_CTR(out, received_eth_multicast.octets);
560 s->tx_multicast_packets =
561 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
562 s->tx_multicast_bytes =
563 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
565 s->rx_broadcast_packets =
566 MLX5_GET_CTR(out, received_eth_broadcast.packets);
567 s->rx_broadcast_bytes =
568 MLX5_GET_CTR(out, received_eth_broadcast.octets);
569 s->tx_broadcast_packets =
570 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
571 s->tx_broadcast_bytes =
572 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
575 s->rx_unicast_packets +
576 s->rx_multicast_packets +
577 s->rx_broadcast_packets -
580 s->rx_unicast_bytes +
581 s->rx_multicast_bytes +
582 s->rx_broadcast_bytes;
584 s->tx_unicast_packets +
585 s->tx_multicast_packets +
586 s->tx_broadcast_packets;
588 s->tx_unicast_bytes +
589 s->tx_multicast_bytes +
590 s->tx_broadcast_bytes;
592 /* Update calculated offload counters */
593 s->tx_csum_offload = s->tx_packets - tx_offload_none;
594 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
596 /* Get physical port counters */
597 mlx5e_update_pport_counters(priv);
599 #if (__FreeBSD_version < 1100000)
600 /* no get_counters interface in fbsd 10 */
601 ifp->if_ipackets = s->rx_packets;
602 ifp->if_ierrors = s->rx_error_packets +
603 priv->stats.pport.alignment_err +
604 priv->stats.pport.check_seq_err +
605 priv->stats.pport.crc_align_errors +
606 priv->stats.pport.in_range_len_errors +
607 priv->stats.pport.jabbers +
608 priv->stats.pport.out_of_range_len +
609 priv->stats.pport.oversize_pkts +
610 priv->stats.pport.symbol_err +
611 priv->stats.pport.too_long_errors +
612 priv->stats.pport.undersize_pkts +
613 priv->stats.pport.unsupported_op_rx;
614 ifp->if_iqdrops = s->rx_out_of_buffer +
615 priv->stats.pport.drop_events;
616 ifp->if_opackets = s->tx_packets;
617 ifp->if_oerrors = s->tx_error_packets;
618 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
619 ifp->if_ibytes = s->rx_bytes;
620 ifp->if_obytes = s->tx_bytes;
622 priv->stats.pport.collisions;
628 /* Update diagnostics, if any */
629 if (priv->params_ethtool.diag_pci_enable ||
630 priv->params_ethtool.diag_general_enable) {
631 int error = mlx5_core_get_diagnostics_full(mdev,
632 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
633 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
635 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
641 mlx5e_update_stats(void *arg)
643 struct mlx5e_priv *priv = arg;
645 schedule_work(&priv->update_stats_work);
647 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
651 mlx5e_async_event_sub(struct mlx5e_priv *priv,
652 enum mlx5_dev_event event)
655 case MLX5_DEV_EVENT_PORT_UP:
656 case MLX5_DEV_EVENT_PORT_DOWN:
657 schedule_work(&priv->update_carrier_work);
666 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
667 enum mlx5_dev_event event, unsigned long param)
669 struct mlx5e_priv *priv = vpriv;
671 mtx_lock(&priv->async_events_mtx);
672 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
673 mlx5e_async_event_sub(priv, event);
674 mtx_unlock(&priv->async_events_mtx);
678 mlx5e_enable_async_events(struct mlx5e_priv *priv)
680 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
684 mlx5e_disable_async_events(struct mlx5e_priv *priv)
686 mtx_lock(&priv->async_events_mtx);
687 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
688 mtx_unlock(&priv->async_events_mtx);
691 static void mlx5e_calibration_callout(void *arg);
692 static int mlx5e_calibration_duration = 20;
693 static int mlx5e_fast_calibration = 1;
694 static int mlx5e_normal_calibration = 30;
696 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
697 "MLX5 timestamp calibration parameteres");
699 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
700 &mlx5e_calibration_duration, 0,
701 "Duration of initial calibration");
702 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
703 &mlx5e_fast_calibration, 0,
704 "Recalibration interval during initial calibration");
705 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
706 &mlx5e_normal_calibration, 0,
707 "Recalibration interval during normal operations");
710 * Ignites the calibration process.
713 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
716 if (priv->clbr_done == 0)
717 mlx5e_calibration_callout(priv);
719 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
720 mlx5e_calibration_duration ? mlx5e_fast_calibration :
721 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
726 mlx5e_timespec2usec(const struct timespec *ts)
729 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
733 mlx5e_hw_clock(struct mlx5e_priv *priv)
735 struct mlx5_init_seg *iseg;
736 uint32_t hw_h, hw_h1, hw_l;
738 iseg = priv->mdev->iseg;
740 hw_h = ioread32be(&iseg->internal_timer_h);
741 hw_l = ioread32be(&iseg->internal_timer_l);
742 hw_h1 = ioread32be(&iseg->internal_timer_h);
743 } while (hw_h1 != hw_h);
744 return (((uint64_t)hw_h << 32) | hw_l);
748 * The calibration callout, it runs either in the context of the
749 * thread which enables calibration, or in callout. It takes the
750 * snapshot of system and adapter clocks, then advances the pointers to
751 * the calibration point to allow rx path to read the consistent data
755 mlx5e_calibration_callout(void *arg)
757 struct mlx5e_priv *priv;
758 struct mlx5e_clbr_point *next, *curr;
763 curr = &priv->clbr_points[priv->clbr_curr];
764 clbr_curr_next = priv->clbr_curr + 1;
765 if (clbr_curr_next >= nitems(priv->clbr_points))
767 next = &priv->clbr_points[clbr_curr_next];
769 next->base_prev = curr->base_curr;
770 next->clbr_hw_prev = curr->clbr_hw_curr;
772 next->clbr_hw_curr = mlx5e_hw_clock(priv);
773 if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
775 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
776 "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
782 next->base_curr = mlx5e_timespec2usec(&ts);
785 atomic_thread_fence_rel();
786 priv->clbr_curr = clbr_curr_next;
787 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
789 if (priv->clbr_done < mlx5e_calibration_duration)
791 mlx5e_reset_calibration_callout(priv);
794 static const char *mlx5e_rq_stats_desc[] = {
795 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
799 mlx5e_create_rq(struct mlx5e_channel *c,
800 struct mlx5e_rq_param *param,
803 struct mlx5e_priv *priv = c->priv;
804 struct mlx5_core_dev *mdev = priv->mdev;
806 void *rqc = param->rqc;
807 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
812 /* Create DMA descriptor TAG */
813 if ((err = -bus_dma_tag_create(
814 bus_get_dma_tag(mdev->pdev->dev.bsddev),
815 1, /* any alignment */
817 BUS_SPACE_MAXADDR, /* lowaddr */
818 BUS_SPACE_MAXADDR, /* highaddr */
819 NULL, NULL, /* filter, filterarg */
820 MJUM16BYTES, /* maxsize */
822 MJUM16BYTES, /* maxsegsize */
824 NULL, NULL, /* lockfunc, lockfuncarg */
828 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
831 goto err_free_dma_tag;
833 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
835 if (priv->params.hw_lro_en) {
836 rq->wqe_sz = priv->params.lro_wqe_sz;
838 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
840 if (rq->wqe_sz > MJUM16BYTES) {
842 goto err_rq_wq_destroy;
843 } else if (rq->wqe_sz > MJUM9BYTES) {
844 rq->wqe_sz = MJUM16BYTES;
845 } else if (rq->wqe_sz > MJUMPAGESIZE) {
846 rq->wqe_sz = MJUM9BYTES;
847 } else if (rq->wqe_sz > MCLBYTES) {
848 rq->wqe_sz = MJUMPAGESIZE;
850 rq->wqe_sz = MCLBYTES;
853 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
855 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
857 goto err_rq_wq_destroy;
859 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
860 for (i = 0; i != wq_sz; i++) {
861 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
862 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
864 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
867 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
868 goto err_rq_mbuf_free;
870 wqe->data.lkey = c->mkey_be;
871 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
878 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
879 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
880 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
885 free(rq->mbuf, M_MLX5EN);
886 tcp_lro_free(&rq->lro);
888 mlx5_wq_destroy(&rq->wq_ctrl);
890 bus_dma_tag_destroy(rq->dma_tag);
896 mlx5e_destroy_rq(struct mlx5e_rq *rq)
901 /* destroy all sysctl nodes */
902 sysctl_ctx_free(&rq->stats.ctx);
904 /* free leftover LRO packets, if any */
905 tcp_lro_free(&rq->lro);
907 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
908 for (i = 0; i != wq_sz; i++) {
909 if (rq->mbuf[i].mbuf != NULL) {
910 bus_dmamap_unload(rq->dma_tag,
911 rq->mbuf[i].dma_map);
912 m_freem(rq->mbuf[i].mbuf);
914 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
916 free(rq->mbuf, M_MLX5EN);
917 mlx5_wq_destroy(&rq->wq_ctrl);
921 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
923 struct mlx5e_channel *c = rq->channel;
924 struct mlx5e_priv *priv = c->priv;
925 struct mlx5_core_dev *mdev = priv->mdev;
933 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
934 sizeof(u64) * rq->wq_ctrl.buf.npages;
935 in = mlx5_vzalloc(inlen);
939 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
940 wq = MLX5_ADDR_OF(rqc, rqc, wq);
942 memcpy(rqc, param->rqc, sizeof(param->rqc));
944 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
945 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
946 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
947 if (priv->counter_set_id >= 0)
948 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
949 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
951 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
953 mlx5_fill_page_array(&rq->wq_ctrl.buf,
954 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
956 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
964 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
966 struct mlx5e_channel *c = rq->channel;
967 struct mlx5e_priv *priv = c->priv;
968 struct mlx5_core_dev *mdev = priv->mdev;
975 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
976 in = mlx5_vzalloc(inlen);
980 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
982 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
983 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
984 MLX5_SET(rqc, rqc, state, next_state);
986 err = mlx5_core_modify_rq(mdev, in, inlen);
994 mlx5e_disable_rq(struct mlx5e_rq *rq)
996 struct mlx5e_channel *c = rq->channel;
997 struct mlx5e_priv *priv = c->priv;
998 struct mlx5_core_dev *mdev = priv->mdev;
1000 mlx5_core_destroy_rq(mdev, rq->rqn);
1004 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1006 struct mlx5e_channel *c = rq->channel;
1007 struct mlx5e_priv *priv = c->priv;
1008 struct mlx5_wq_ll *wq = &rq->wq;
1011 for (i = 0; i < 1000; i++) {
1012 if (wq->cur_sz >= priv->params.min_rx_wqes)
1017 return (-ETIMEDOUT);
1021 mlx5e_open_rq(struct mlx5e_channel *c,
1022 struct mlx5e_rq_param *param,
1023 struct mlx5e_rq *rq)
1027 err = mlx5e_create_rq(c, param, rq);
1031 err = mlx5e_enable_rq(rq, param);
1033 goto err_destroy_rq;
1035 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1037 goto err_disable_rq;
1044 mlx5e_disable_rq(rq);
1046 mlx5e_destroy_rq(rq);
1052 mlx5e_close_rq(struct mlx5e_rq *rq)
1056 callout_stop(&rq->watchdog);
1057 mtx_unlock(&rq->mtx);
1059 callout_drain(&rq->watchdog);
1061 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1065 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1067 /* wait till RQ is empty */
1068 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
1070 rq->cq.mcq.comp(&rq->cq.mcq);
1073 mlx5e_disable_rq(rq);
1074 mlx5e_destroy_rq(rq);
1078 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1080 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1083 for (x = 0; x != wq_sz; x++)
1084 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1085 free(sq->mbuf, M_MLX5EN);
1089 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1091 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1095 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1097 /* Create DMA descriptor MAPs */
1098 for (x = 0; x != wq_sz; x++) {
1099 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1102 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1103 free(sq->mbuf, M_MLX5EN);
1110 static const char *mlx5e_sq_stats_desc[] = {
1111 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1115 mlx5e_create_sq(struct mlx5e_channel *c,
1117 struct mlx5e_sq_param *param,
1118 struct mlx5e_sq *sq)
1120 struct mlx5e_priv *priv = c->priv;
1121 struct mlx5_core_dev *mdev = priv->mdev;
1124 void *sqc = param->sqc;
1125 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1132 /* Create DMA descriptor TAG */
1133 if ((err = -bus_dma_tag_create(
1134 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1135 1, /* any alignment */
1136 0, /* no boundary */
1137 BUS_SPACE_MAXADDR, /* lowaddr */
1138 BUS_SPACE_MAXADDR, /* highaddr */
1139 NULL, NULL, /* filter, filterarg */
1140 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1141 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1142 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1144 NULL, NULL, /* lockfunc, lockfuncarg */
1148 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1150 goto err_free_dma_tag;
1152 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1155 goto err_unmap_free_uar;
1157 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1158 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1160 err = mlx5e_alloc_sq_db(sq);
1162 goto err_sq_wq_destroy;
1164 sq->mkey_be = c->mkey_be;
1165 sq->ifp = priv->ifp;
1169 /* check if we should allocate a second packet buffer */
1170 if (priv->params_ethtool.tx_bufring_disable == 0) {
1171 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1172 M_WAITOK, &sq->lock);
1173 if (sq->br == NULL) {
1174 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1177 goto err_free_sq_db;
1180 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1181 taskqueue_thread_enqueue, &sq->sq_tq);
1182 if (sq->sq_tq == NULL) {
1183 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1189 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1191 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1192 CPU_SETOF(cpu_id, &cpu_mask);
1193 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1194 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1196 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1197 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1200 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1201 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1202 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1208 buf_ring_free(sq->br, M_MLX5EN);
1210 mlx5e_free_sq_db(sq);
1212 mlx5_wq_destroy(&sq->wq_ctrl);
1215 mlx5_unmap_free_uar(mdev, &sq->uar);
1218 bus_dma_tag_destroy(sq->dma_tag);
1224 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1226 /* destroy all sysctl nodes */
1227 sysctl_ctx_free(&sq->stats.ctx);
1229 mlx5e_free_sq_db(sq);
1230 mlx5_wq_destroy(&sq->wq_ctrl);
1231 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1232 if (sq->sq_tq != NULL) {
1233 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1234 taskqueue_free(sq->sq_tq);
1237 buf_ring_free(sq->br, M_MLX5EN);
1241 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1250 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1251 sizeof(u64) * sq->wq_ctrl.buf.npages;
1252 in = mlx5_vzalloc(inlen);
1256 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1257 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1259 memcpy(sqc, param->sqc, sizeof(param->sqc));
1261 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1262 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1263 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1264 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1265 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1267 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1268 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1269 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1271 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1273 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1274 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1276 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1284 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1291 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1292 in = mlx5_vzalloc(inlen);
1296 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1298 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1299 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1300 MLX5_SET(sqc, sqc, state, next_state);
1302 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1310 mlx5e_disable_sq(struct mlx5e_sq *sq)
1313 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1317 mlx5e_open_sq(struct mlx5e_channel *c,
1319 struct mlx5e_sq_param *param,
1320 struct mlx5e_sq *sq)
1324 err = mlx5e_create_sq(c, tc, param, sq);
1328 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1330 goto err_destroy_sq;
1332 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1334 goto err_disable_sq;
1336 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1341 mlx5e_disable_sq(sq);
1343 mlx5e_destroy_sq(sq);
1349 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1351 /* fill up remainder with NOPs */
1352 while (sq->cev_counter != 0) {
1353 while (!mlx5e_sq_has_room_for(sq, 1)) {
1354 if (can_sleep != 0) {
1355 mtx_unlock(&sq->lock);
1357 mtx_lock(&sq->lock);
1362 /* send a single NOP */
1363 mlx5e_send_nop(sq, 1);
1364 atomic_thread_fence_rel();
1367 /* Check if we need to write the doorbell */
1368 if (likely(sq->doorbell.d64 != 0)) {
1369 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1370 sq->doorbell.d64 = 0;
1375 mlx5e_sq_cev_timeout(void *arg)
1377 struct mlx5e_sq *sq = arg;
1379 mtx_assert(&sq->lock, MA_OWNED);
1381 /* check next state */
1382 switch (sq->cev_next_state) {
1383 case MLX5E_CEV_STATE_SEND_NOPS:
1384 /* fill TX ring with NOPs, if any */
1385 mlx5e_sq_send_nops_locked(sq, 0);
1387 /* check if completed */
1388 if (sq->cev_counter == 0) {
1389 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1394 /* send NOPs on next timeout */
1395 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1400 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1404 mlx5e_drain_sq(struct mlx5e_sq *sq)
1409 * Check if already stopped.
1411 * NOTE: The "stopped" variable is only written when both the
1412 * priv's configuration lock and the SQ's lock is locked. It
1413 * can therefore safely be read when only one of the two locks
1414 * is locked. This function is always called when the priv's
1415 * configuration lock is locked.
1417 if (sq->stopped != 0)
1420 mtx_lock(&sq->lock);
1422 /* don't put more packets into the SQ */
1425 /* teardown event factor timer, if any */
1426 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1427 callout_stop(&sq->cev_callout);
1429 /* send dummy NOPs in order to flush the transmit ring */
1430 mlx5e_sq_send_nops_locked(sq, 1);
1431 mtx_unlock(&sq->lock);
1433 /* make sure it is safe to free the callout */
1434 callout_drain(&sq->cev_callout);
1436 /* wait till SQ is empty or link is down */
1437 mtx_lock(&sq->lock);
1438 while (sq->cc != sq->pc &&
1439 (sq->priv->media_status_last & IFM_ACTIVE) != 0) {
1440 mtx_unlock(&sq->lock);
1442 sq->cq.mcq.comp(&sq->cq.mcq);
1443 mtx_lock(&sq->lock);
1445 mtx_unlock(&sq->lock);
1447 /* error out remaining requests */
1448 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1451 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1454 /* wait till SQ is empty */
1455 mtx_lock(&sq->lock);
1456 while (sq->cc != sq->pc) {
1457 mtx_unlock(&sq->lock);
1459 sq->cq.mcq.comp(&sq->cq.mcq);
1460 mtx_lock(&sq->lock);
1462 mtx_unlock(&sq->lock);
1466 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1470 mlx5e_disable_sq(sq);
1471 mlx5e_destroy_sq(sq);
1475 mlx5e_create_cq(struct mlx5e_priv *priv,
1476 struct mlx5e_cq_param *param,
1477 struct mlx5e_cq *cq,
1478 mlx5e_cq_comp_t *comp,
1481 struct mlx5_core_dev *mdev = priv->mdev;
1482 struct mlx5_core_cq *mcq = &cq->mcq;
1488 param->wq.buf_numa_node = 0;
1489 param->wq.db_numa_node = 0;
1491 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1496 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1499 mcq->set_ci_db = cq->wq_ctrl.db.db;
1500 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1501 *mcq->set_ci_db = 0;
1503 mcq->vector = eq_ix;
1505 mcq->event = mlx5e_cq_error_event;
1507 mcq->uar = &priv->cq_uar;
1509 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1510 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1521 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1523 mlx5_wq_destroy(&cq->wq_ctrl);
1527 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1529 struct mlx5_core_cq *mcq = &cq->mcq;
1537 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1538 sizeof(u64) * cq->wq_ctrl.buf.npages;
1539 in = mlx5_vzalloc(inlen);
1543 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1545 memcpy(cqc, param->cqc, sizeof(param->cqc));
1547 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1548 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1550 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1552 MLX5_SET(cqc, cqc, c_eqn, eqn);
1553 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1554 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1556 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1558 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1565 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1571 mlx5e_disable_cq(struct mlx5e_cq *cq)
1574 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1578 mlx5e_open_cq(struct mlx5e_priv *priv,
1579 struct mlx5e_cq_param *param,
1580 struct mlx5e_cq *cq,
1581 mlx5e_cq_comp_t *comp,
1586 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1590 err = mlx5e_enable_cq(cq, param, eq_ix);
1592 goto err_destroy_cq;
1597 mlx5e_destroy_cq(cq);
1603 mlx5e_close_cq(struct mlx5e_cq *cq)
1605 mlx5e_disable_cq(cq);
1606 mlx5e_destroy_cq(cq);
1610 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1611 struct mlx5e_channel_param *cparam)
1616 for (tc = 0; tc < c->num_tc; tc++) {
1617 /* open completion queue */
1618 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1619 &mlx5e_tx_cq_comp, c->ix);
1621 goto err_close_tx_cqs;
1626 for (tc--; tc >= 0; tc--)
1627 mlx5e_close_cq(&c->sq[tc].cq);
1633 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1637 for (tc = 0; tc < c->num_tc; tc++)
1638 mlx5e_close_cq(&c->sq[tc].cq);
1642 mlx5e_open_sqs(struct mlx5e_channel *c,
1643 struct mlx5e_channel_param *cparam)
1648 for (tc = 0; tc < c->num_tc; tc++) {
1649 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1657 for (tc--; tc >= 0; tc--)
1658 mlx5e_close_sq_wait(&c->sq[tc]);
1664 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1668 for (tc = 0; tc < c->num_tc; tc++)
1669 mlx5e_close_sq_wait(&c->sq[tc]);
1673 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1677 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1679 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1681 for (tc = 0; tc < c->num_tc; tc++) {
1682 struct mlx5e_sq *sq = c->sq + tc;
1684 mtx_init(&sq->lock, "mlx5tx",
1685 MTX_NETWORK_LOCK " TX", MTX_DEF);
1686 mtx_init(&sq->comp_lock, "mlx5comp",
1687 MTX_NETWORK_LOCK " TX", MTX_DEF);
1689 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1691 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1693 /* ensure the TX completion event factor is not zero */
1694 if (sq->cev_factor == 0)
1700 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1704 mtx_destroy(&c->rq.mtx);
1706 for (tc = 0; tc < c->num_tc; tc++) {
1707 mtx_destroy(&c->sq[tc].lock);
1708 mtx_destroy(&c->sq[tc].comp_lock);
1713 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1714 struct mlx5e_channel_param *cparam,
1715 struct mlx5e_channel *volatile *cp)
1717 struct mlx5e_channel *c;
1720 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1725 c->mkey_be = cpu_to_be32(priv->mr.key);
1726 c->num_tc = priv->num_tc;
1729 mlx5e_chan_mtx_init(c);
1731 /* open transmit completion queue */
1732 err = mlx5e_open_tx_cqs(c, cparam);
1736 /* open receive completion queue */
1737 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1738 &mlx5e_rx_cq_comp, c->ix);
1740 goto err_close_tx_cqs;
1742 err = mlx5e_open_sqs(c, cparam);
1744 goto err_close_rx_cq;
1746 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1750 /* store channel pointer */
1753 /* poll receive queue initially */
1754 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1759 mlx5e_close_sqs_wait(c);
1762 mlx5e_close_cq(&c->rq.cq);
1765 mlx5e_close_tx_cqs(c);
1768 /* destroy mutexes */
1769 mlx5e_chan_mtx_destroy(c);
1775 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1777 struct mlx5e_channel *c = *pp;
1779 /* check if channel is already closed */
1782 mlx5e_close_rq(&c->rq);
1786 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1788 struct mlx5e_channel *c = *pp;
1790 /* check if channel is already closed */
1793 /* ensure channel pointer is no longer used */
1796 mlx5e_close_rq_wait(&c->rq);
1797 mlx5e_close_sqs_wait(c);
1798 mlx5e_close_cq(&c->rq.cq);
1799 mlx5e_close_tx_cqs(c);
1800 /* destroy mutexes */
1801 mlx5e_chan_mtx_destroy(c);
1806 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1807 struct mlx5e_rq_param *param)
1809 void *rqc = param->rqc;
1810 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1812 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1813 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1814 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1815 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1816 MLX5_SET(wq, wq, pd, priv->pdn);
1818 param->wq.buf_numa_node = 0;
1819 param->wq.db_numa_node = 0;
1820 param->wq.linear = 1;
1824 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1825 struct mlx5e_sq_param *param)
1827 void *sqc = param->sqc;
1828 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1830 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1831 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1832 MLX5_SET(wq, wq, pd, priv->pdn);
1834 param->wq.buf_numa_node = 0;
1835 param->wq.db_numa_node = 0;
1836 param->wq.linear = 1;
1840 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1841 struct mlx5e_cq_param *param)
1843 void *cqc = param->cqc;
1845 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1849 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1850 struct mlx5e_cq_param *param)
1852 void *cqc = param->cqc;
1856 * TODO The sysctl to control on/off is a bool value for now, which means
1857 * we only support CSUM, once HASH is implemnted we'll need to address that.
1859 if (priv->params.cqe_zipping_en) {
1860 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1861 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1864 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1865 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1866 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1868 switch (priv->params.rx_cq_moderation_mode) {
1870 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1873 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1874 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1876 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1880 mlx5e_build_common_cq_param(priv, param);
1884 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1885 struct mlx5e_cq_param *param)
1887 void *cqc = param->cqc;
1889 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1890 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1891 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1893 switch (priv->params.tx_cq_moderation_mode) {
1895 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1898 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1899 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1901 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1905 mlx5e_build_common_cq_param(priv, param);
1909 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1910 struct mlx5e_channel_param *cparam)
1912 memset(cparam, 0, sizeof(*cparam));
1914 mlx5e_build_rq_param(priv, &cparam->rq);
1915 mlx5e_build_sq_param(priv, &cparam->sq);
1916 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1917 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1921 mlx5e_open_channels(struct mlx5e_priv *priv)
1923 struct mlx5e_channel_param cparam;
1929 priv->channel = malloc(priv->params.num_channels *
1930 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1932 mlx5e_build_channel_param(priv, &cparam);
1933 for (i = 0; i < priv->params.num_channels; i++) {
1934 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1936 goto err_close_channels;
1939 for (j = 0; j < priv->params.num_channels; j++) {
1940 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1942 goto err_close_channels;
1948 for (i--; i >= 0; i--) {
1949 mlx5e_close_channel(&priv->channel[i]);
1950 mlx5e_close_channel_wait(&priv->channel[i]);
1953 /* remove "volatile" attribute from "channel" pointer */
1954 ptr = __DECONST(void *, priv->channel);
1955 priv->channel = NULL;
1957 free(ptr, M_MLX5EN);
1963 mlx5e_close_channels(struct mlx5e_priv *priv)
1968 if (priv->channel == NULL)
1971 for (i = 0; i < priv->params.num_channels; i++)
1972 mlx5e_close_channel(&priv->channel[i]);
1973 for (i = 0; i < priv->params.num_channels; i++)
1974 mlx5e_close_channel_wait(&priv->channel[i]);
1976 /* remove "volatile" attribute from "channel" pointer */
1977 ptr = __DECONST(void *, priv->channel);
1978 priv->channel = NULL;
1980 free(ptr, M_MLX5EN);
1984 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1987 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1990 switch (priv->params.tx_cq_moderation_mode) {
1992 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1995 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1999 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2000 priv->params.tx_cq_moderation_usec,
2001 priv->params.tx_cq_moderation_pkts,
2005 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2006 priv->params.tx_cq_moderation_usec,
2007 priv->params.tx_cq_moderation_pkts));
2011 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2014 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2018 switch (priv->params.rx_cq_moderation_mode) {
2020 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2023 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2027 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2028 priv->params.rx_cq_moderation_usec,
2029 priv->params.rx_cq_moderation_pkts,
2035 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2036 priv->params.rx_cq_moderation_usec,
2037 priv->params.rx_cq_moderation_pkts));
2041 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2049 err = mlx5e_refresh_rq_params(priv, &c->rq);
2053 for (i = 0; i != c->num_tc; i++) {
2054 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2063 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2067 if (priv->channel == NULL)
2070 for (i = 0; i < priv->params.num_channels; i++) {
2073 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
2081 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2083 struct mlx5_core_dev *mdev = priv->mdev;
2084 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2085 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2087 memset(in, 0, sizeof(in));
2089 MLX5_SET(tisc, tisc, prio, tc);
2090 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2092 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2096 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2098 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2102 mlx5e_open_tises(struct mlx5e_priv *priv)
2104 int num_tc = priv->num_tc;
2108 for (tc = 0; tc < num_tc; tc++) {
2109 err = mlx5e_open_tis(priv, tc);
2111 goto err_close_tises;
2117 for (tc--; tc >= 0; tc--)
2118 mlx5e_close_tis(priv, tc);
2124 mlx5e_close_tises(struct mlx5e_priv *priv)
2126 int num_tc = priv->num_tc;
2129 for (tc = 0; tc < num_tc; tc++)
2130 mlx5e_close_tis(priv, tc);
2134 mlx5e_open_rqt(struct mlx5e_priv *priv)
2136 struct mlx5_core_dev *mdev = priv->mdev;
2138 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2145 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2147 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2148 in = mlx5_vzalloc(inlen);
2151 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2153 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2154 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2156 for (i = 0; i < sz; i++) {
2159 ix = rss_get_indirection_to_bucket(i);
2163 /* ensure we don't overflow */
2164 ix %= priv->params.num_channels;
2165 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2168 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2170 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2172 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2180 mlx5e_close_rqt(struct mlx5e_priv *priv)
2182 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2183 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2185 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2186 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2188 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2192 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2194 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2197 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2199 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2201 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2202 MLX5_HASH_FIELD_SEL_DST_IP)
2204 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2205 MLX5_HASH_FIELD_SEL_DST_IP |\
2206 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2207 MLX5_HASH_FIELD_SEL_L4_DPORT)
2209 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2210 MLX5_HASH_FIELD_SEL_DST_IP |\
2211 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2213 if (priv->params.hw_lro_en) {
2214 MLX5_SET(tirc, tirc, lro_enable_mask,
2215 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2216 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2217 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2218 (priv->params.lro_wqe_sz -
2219 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2220 /* TODO: add the option to choose timer value dynamically */
2221 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2222 MLX5_CAP_ETH(priv->mdev,
2223 lro_timer_supported_periods[2]));
2226 /* setup parameters for hashing TIR type, if any */
2229 MLX5_SET(tirc, tirc, disp_type,
2230 MLX5_TIRC_DISP_TYPE_DIRECT);
2231 MLX5_SET(tirc, tirc, inline_rqn,
2232 priv->channel[0]->rq.rqn);
2235 MLX5_SET(tirc, tirc, disp_type,
2236 MLX5_TIRC_DISP_TYPE_INDIRECT);
2237 MLX5_SET(tirc, tirc, indirect_table,
2239 MLX5_SET(tirc, tirc, rx_hash_fn,
2240 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2241 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2244 * The FreeBSD RSS implementation does currently not
2245 * support symmetric Toeplitz hashes:
2247 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2248 rss_getkey((uint8_t *)hkey);
2250 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2251 hkey[0] = cpu_to_be32(0xD181C62C);
2252 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2253 hkey[2] = cpu_to_be32(0x1983A2FC);
2254 hkey[3] = cpu_to_be32(0x943E1ADB);
2255 hkey[4] = cpu_to_be32(0xD9389E6B);
2256 hkey[5] = cpu_to_be32(0xD1039C2C);
2257 hkey[6] = cpu_to_be32(0xA74499AD);
2258 hkey[7] = cpu_to_be32(0x593D56D9);
2259 hkey[8] = cpu_to_be32(0xF3253C06);
2260 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2266 case MLX5E_TT_IPV4_TCP:
2267 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2268 MLX5_L3_PROT_TYPE_IPV4);
2269 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2270 MLX5_L4_PROT_TYPE_TCP);
2272 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2273 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2277 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2281 case MLX5E_TT_IPV6_TCP:
2282 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2283 MLX5_L3_PROT_TYPE_IPV6);
2284 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2285 MLX5_L4_PROT_TYPE_TCP);
2287 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2288 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2292 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2296 case MLX5E_TT_IPV4_UDP:
2297 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2298 MLX5_L3_PROT_TYPE_IPV4);
2299 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2300 MLX5_L4_PROT_TYPE_UDP);
2302 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2303 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2307 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2311 case MLX5E_TT_IPV6_UDP:
2312 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2313 MLX5_L3_PROT_TYPE_IPV6);
2314 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2315 MLX5_L4_PROT_TYPE_UDP);
2317 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2318 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2322 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2326 case MLX5E_TT_IPV4_IPSEC_AH:
2327 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2328 MLX5_L3_PROT_TYPE_IPV4);
2329 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2330 MLX5_HASH_IP_IPSEC_SPI);
2333 case MLX5E_TT_IPV6_IPSEC_AH:
2334 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2335 MLX5_L3_PROT_TYPE_IPV6);
2336 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2337 MLX5_HASH_IP_IPSEC_SPI);
2340 case MLX5E_TT_IPV4_IPSEC_ESP:
2341 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2342 MLX5_L3_PROT_TYPE_IPV4);
2343 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2344 MLX5_HASH_IP_IPSEC_SPI);
2347 case MLX5E_TT_IPV6_IPSEC_ESP:
2348 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2349 MLX5_L3_PROT_TYPE_IPV6);
2350 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2351 MLX5_HASH_IP_IPSEC_SPI);
2355 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2356 MLX5_L3_PROT_TYPE_IPV4);
2357 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2362 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2363 MLX5_L3_PROT_TYPE_IPV6);
2364 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2374 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2376 struct mlx5_core_dev *mdev = priv->mdev;
2382 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2383 in = mlx5_vzalloc(inlen);
2386 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2388 mlx5e_build_tir_ctx(priv, tirc, tt);
2390 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2398 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2400 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2404 mlx5e_open_tirs(struct mlx5e_priv *priv)
2409 for (i = 0; i < MLX5E_NUM_TT; i++) {
2410 err = mlx5e_open_tir(priv, i);
2412 goto err_close_tirs;
2418 for (i--; i >= 0; i--)
2419 mlx5e_close_tir(priv, i);
2425 mlx5e_close_tirs(struct mlx5e_priv *priv)
2429 for (i = 0; i < MLX5E_NUM_TT; i++)
2430 mlx5e_close_tir(priv, i);
2434 * SW MTU does not include headers,
2435 * HW MTU includes all headers and checksums.
2438 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2440 struct mlx5e_priv *priv = ifp->if_softc;
2441 struct mlx5_core_dev *mdev = priv->mdev;
2445 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2447 err = mlx5_set_port_mtu(mdev, hw_mtu);
2449 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2450 __func__, sw_mtu, err);
2454 /* Update vport context MTU */
2455 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2457 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2461 ifp->if_mtu = sw_mtu;
2463 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2464 if (err || !hw_mtu) {
2465 /* fallback to port oper mtu */
2466 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2469 if_printf(ifp, "Query port MTU, after setting new "
2470 "MTU value, failed\n");
2472 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2474 if_printf(ifp, "Port MTU %d is smaller than "
2475 "ifp mtu %d\n", hw_mtu, sw_mtu);
2476 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2478 if_printf(ifp, "Port MTU %d is bigger than "
2479 "ifp mtu %d\n", hw_mtu, sw_mtu);
2481 priv->params_ethtool.hw_mtu = hw_mtu;
2487 mlx5e_open_locked(struct ifnet *ifp)
2489 struct mlx5e_priv *priv = ifp->if_softc;
2493 /* check if already opened */
2494 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2498 if (rss_getnumbuckets() > priv->params.num_channels) {
2499 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2500 "channels(%u) available\n", rss_getnumbuckets(),
2501 priv->params.num_channels);
2504 err = mlx5e_open_tises(priv);
2506 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2510 err = mlx5_vport_alloc_q_counter(priv->mdev,
2511 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2513 if_printf(priv->ifp,
2514 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2516 goto err_close_tises;
2518 /* store counter set ID */
2519 priv->counter_set_id = set_id;
2521 err = mlx5e_open_channels(priv);
2523 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2525 goto err_dalloc_q_counter;
2527 err = mlx5e_open_rqt(priv);
2529 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2531 goto err_close_channels;
2533 err = mlx5e_open_tirs(priv);
2535 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2537 goto err_close_rqls;
2539 err = mlx5e_open_flow_table(priv);
2541 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2543 goto err_close_tirs;
2545 err = mlx5e_add_all_vlan_rules(priv);
2547 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2549 goto err_close_flow_table;
2551 set_bit(MLX5E_STATE_OPENED, &priv->state);
2553 mlx5e_update_carrier(priv);
2554 mlx5e_set_rx_mode_core(priv);
2558 err_close_flow_table:
2559 mlx5e_close_flow_table(priv);
2562 mlx5e_close_tirs(priv);
2565 mlx5e_close_rqt(priv);
2568 mlx5e_close_channels(priv);
2570 err_dalloc_q_counter:
2571 mlx5_vport_dealloc_q_counter(priv->mdev,
2572 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2575 mlx5e_close_tises(priv);
2581 mlx5e_open(void *arg)
2583 struct mlx5e_priv *priv = arg;
2586 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2587 if_printf(priv->ifp,
2588 "%s: Setting port status to up failed\n",
2591 mlx5e_open_locked(priv->ifp);
2592 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2597 mlx5e_close_locked(struct ifnet *ifp)
2599 struct mlx5e_priv *priv = ifp->if_softc;
2601 /* check if already closed */
2602 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2605 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2607 mlx5e_set_rx_mode_core(priv);
2608 mlx5e_del_all_vlan_rules(priv);
2609 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2610 mlx5e_close_flow_table(priv);
2611 mlx5e_close_tirs(priv);
2612 mlx5e_close_rqt(priv);
2613 mlx5e_close_channels(priv);
2614 mlx5_vport_dealloc_q_counter(priv->mdev,
2615 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2616 mlx5e_close_tises(priv);
2621 #if (__FreeBSD_version >= 1100000)
2623 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2625 struct mlx5e_priv *priv = ifp->if_softc;
2628 /* PRIV_LOCK(priv); XXX not allowed */
2630 case IFCOUNTER_IPACKETS:
2631 retval = priv->stats.vport.rx_packets;
2633 case IFCOUNTER_IERRORS:
2634 retval = priv->stats.vport.rx_error_packets +
2635 priv->stats.pport.alignment_err +
2636 priv->stats.pport.check_seq_err +
2637 priv->stats.pport.crc_align_errors +
2638 priv->stats.pport.in_range_len_errors +
2639 priv->stats.pport.jabbers +
2640 priv->stats.pport.out_of_range_len +
2641 priv->stats.pport.oversize_pkts +
2642 priv->stats.pport.symbol_err +
2643 priv->stats.pport.too_long_errors +
2644 priv->stats.pport.undersize_pkts +
2645 priv->stats.pport.unsupported_op_rx;
2647 case IFCOUNTER_IQDROPS:
2648 retval = priv->stats.vport.rx_out_of_buffer +
2649 priv->stats.pport.drop_events;
2651 case IFCOUNTER_OPACKETS:
2652 retval = priv->stats.vport.tx_packets;
2654 case IFCOUNTER_OERRORS:
2655 retval = priv->stats.vport.tx_error_packets;
2657 case IFCOUNTER_IBYTES:
2658 retval = priv->stats.vport.rx_bytes;
2660 case IFCOUNTER_OBYTES:
2661 retval = priv->stats.vport.tx_bytes;
2663 case IFCOUNTER_IMCASTS:
2664 retval = priv->stats.vport.rx_multicast_packets;
2666 case IFCOUNTER_OMCASTS:
2667 retval = priv->stats.vport.tx_multicast_packets;
2669 case IFCOUNTER_OQDROPS:
2670 retval = priv->stats.vport.tx_queue_dropped;
2672 case IFCOUNTER_COLLISIONS:
2673 retval = priv->stats.pport.collisions;
2676 retval = if_get_counter_default(ifp, cnt);
2679 /* PRIV_UNLOCK(priv); XXX not allowed */
2685 mlx5e_set_rx_mode(struct ifnet *ifp)
2687 struct mlx5e_priv *priv = ifp->if_softc;
2689 schedule_work(&priv->set_rx_mode_work);
2693 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2695 struct mlx5e_priv *priv;
2697 struct ifi2creq i2c;
2706 priv = ifp->if_softc;
2708 /* check if detaching */
2709 if (priv == NULL || priv->gone != 0)
2714 ifr = (struct ifreq *)data;
2717 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2719 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2720 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2723 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2725 mlx5e_close_locked(ifp);
2728 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2731 mlx5e_open_locked(ifp);
2734 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2735 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2740 if ((ifp->if_flags & IFF_UP) &&
2741 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2742 mlx5e_set_rx_mode(ifp);
2746 if (ifp->if_flags & IFF_UP) {
2747 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2748 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2749 mlx5e_open_locked(ifp);
2750 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2751 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2754 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2755 mlx5_set_port_status(priv->mdev,
2757 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2758 mlx5e_close_locked(ifp);
2759 mlx5e_update_carrier(priv);
2760 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2767 mlx5e_set_rx_mode(ifp);
2772 ifr = (struct ifreq *)data;
2773 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2776 ifr = (struct ifreq *)data;
2778 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2780 if (mask & IFCAP_TXCSUM) {
2781 ifp->if_capenable ^= IFCAP_TXCSUM;
2782 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2784 if (IFCAP_TSO4 & ifp->if_capenable &&
2785 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2786 ifp->if_capenable &= ~IFCAP_TSO4;
2787 ifp->if_hwassist &= ~CSUM_IP_TSO;
2789 "tso4 disabled due to -txcsum.\n");
2792 if (mask & IFCAP_TXCSUM_IPV6) {
2793 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2794 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2796 if (IFCAP_TSO6 & ifp->if_capenable &&
2797 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2798 ifp->if_capenable &= ~IFCAP_TSO6;
2799 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2801 "tso6 disabled due to -txcsum6.\n");
2804 if (mask & IFCAP_RXCSUM)
2805 ifp->if_capenable ^= IFCAP_RXCSUM;
2806 if (mask & IFCAP_RXCSUM_IPV6)
2807 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2808 if (mask & IFCAP_TSO4) {
2809 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2810 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2811 if_printf(ifp, "enable txcsum first.\n");
2815 ifp->if_capenable ^= IFCAP_TSO4;
2816 ifp->if_hwassist ^= CSUM_IP_TSO;
2818 if (mask & IFCAP_TSO6) {
2819 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2820 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2821 if_printf(ifp, "enable txcsum6 first.\n");
2825 ifp->if_capenable ^= IFCAP_TSO6;
2826 ifp->if_hwassist ^= CSUM_IP6_TSO;
2828 if (mask & IFCAP_VLAN_HWFILTER) {
2829 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2830 mlx5e_disable_vlan_filter(priv);
2832 mlx5e_enable_vlan_filter(priv);
2834 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2836 if (mask & IFCAP_VLAN_HWTAGGING)
2837 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2838 if (mask & IFCAP_WOL_MAGIC)
2839 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2841 VLAN_CAPABILITIES(ifp);
2842 /* turn off LRO means also turn of HW LRO - if it's on */
2843 if (mask & IFCAP_LRO) {
2844 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2845 bool need_restart = false;
2847 ifp->if_capenable ^= IFCAP_LRO;
2848 if (!(ifp->if_capenable & IFCAP_LRO)) {
2849 if (priv->params.hw_lro_en) {
2850 priv->params.hw_lro_en = false;
2851 need_restart = true;
2852 /* Not sure this is the correct way */
2853 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2856 if (was_opened && need_restart) {
2857 mlx5e_close_locked(ifp);
2858 mlx5e_open_locked(ifp);
2861 if (mask & IFCAP_HWRXTSTMP) {
2862 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2863 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
2864 if (priv->clbr_done == 0)
2865 mlx5e_reset_calibration_callout(priv);
2867 callout_drain(&priv->tstmp_clbr);
2868 priv->clbr_done = 0;
2876 ifr = (struct ifreq *)data;
2879 * Copy from the user-space address ifr_data to the
2880 * kernel-space address i2c
2882 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2886 if (i2c.len > sizeof(i2c.data)) {
2892 /* Get module_num which is required for the query_eeprom */
2893 error = mlx5_query_module_num(priv->mdev, &module_num);
2895 if_printf(ifp, "Query module num failed, eeprom "
2896 "reading is not supported\n");
2900 /* Check if module is present before doing an access */
2901 module_status = mlx5_query_module_status(priv->mdev, module_num);
2902 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2903 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2908 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2909 * The internal conversion is as follows:
2911 if (i2c.dev_addr == 0xA0)
2912 read_addr = MLX5E_I2C_ADDR_LOW;
2913 else if (i2c.dev_addr == 0xA2)
2914 read_addr = MLX5E_I2C_ADDR_HIGH;
2916 if_printf(ifp, "Query eeprom failed, "
2917 "Invalid Address: %X\n", i2c.dev_addr);
2921 error = mlx5_query_eeprom(priv->mdev,
2922 read_addr, MLX5E_EEPROM_LOW_PAGE,
2923 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2924 (uint32_t *)i2c.data, &size_read);
2926 if_printf(ifp, "Query eeprom failed, eeprom "
2927 "reading is not supported\n");
2932 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2933 error = mlx5_query_eeprom(priv->mdev,
2934 read_addr, MLX5E_EEPROM_LOW_PAGE,
2935 (uint32_t)(i2c.offset + size_read),
2936 (uint32_t)(i2c.len - size_read), module_num,
2937 (uint32_t *)(i2c.data + size_read), &size_read);
2940 if_printf(ifp, "Query eeprom failed, eeprom "
2941 "reading is not supported\n");
2946 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2952 error = ether_ioctl(ifp, command, data);
2959 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2962 * TODO: uncoment once FW really sets all these bits if
2963 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2964 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2965 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2969 /* TODO: add more must-to-have features */
2971 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2978 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2979 struct mlx5e_priv *priv,
2980 int num_comp_vectors)
2983 * TODO: Consider link speed for setting "log_sq_size",
2984 * "log_rq_size" and "cq_moderation_xxx":
2986 priv->params.log_sq_size =
2987 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2988 priv->params.log_rq_size =
2989 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2990 priv->params.rx_cq_moderation_usec =
2991 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2992 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2993 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2994 priv->params.rx_cq_moderation_mode =
2995 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2996 priv->params.rx_cq_moderation_pkts =
2997 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2998 priv->params.tx_cq_moderation_usec =
2999 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3000 priv->params.tx_cq_moderation_pkts =
3001 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3002 priv->params.min_rx_wqes =
3003 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3004 priv->params.rx_hash_log_tbl_sz =
3005 (order_base_2(num_comp_vectors) >
3006 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3007 order_base_2(num_comp_vectors) :
3008 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3009 priv->params.num_tc = 1;
3010 priv->params.default_vlan_prio = 0;
3011 priv->counter_set_id = -1;
3014 * hw lro is currently defaulted to off. when it won't anymore we
3015 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3017 priv->params.hw_lro_en = false;
3018 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3020 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3023 priv->params.num_channels = num_comp_vectors;
3024 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3025 priv->queue_mapping_channel_mask =
3026 roundup_pow_of_two(num_comp_vectors) - 1;
3027 priv->num_tc = priv->params.num_tc;
3028 priv->default_vlan_prio = priv->params.default_vlan_prio;
3030 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3031 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3032 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3036 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3037 struct mlx5_core_mr *mkey)
3039 struct ifnet *ifp = priv->ifp;
3040 struct mlx5_core_dev *mdev = priv->mdev;
3041 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3046 in = mlx5_vzalloc(inlen);
3048 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3052 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3053 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3054 MLX5_SET(mkc, mkc, lw, 1);
3055 MLX5_SET(mkc, mkc, lr, 1);
3057 MLX5_SET(mkc, mkc, pd, pdn);
3058 MLX5_SET(mkc, mkc, length64, 1);
3059 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3061 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3063 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3070 static const char *mlx5e_vport_stats_desc[] = {
3071 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3074 static const char *mlx5e_pport_stats_desc[] = {
3075 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3079 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3081 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3082 sx_init(&priv->state_lock, "mlx5state");
3083 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3084 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3088 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3090 mtx_destroy(&priv->async_events_mtx);
3091 sx_destroy(&priv->state_lock);
3095 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3098 * %d.%d%.d the string format.
3099 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3100 * We need at most 5 chars to store that.
3101 * It also has: two "." and NULL at the end, which means we need 18
3102 * (5*3 + 3) chars at most.
3105 struct mlx5e_priv *priv = arg1;
3108 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3109 fw_rev_sub(priv->mdev));
3110 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3115 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3119 for (i = 0; i < ch->num_tc; i++)
3120 mlx5e_drain_sq(&ch->sq[i]);
3124 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3127 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3128 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3129 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3130 sq->doorbell.d64 = 0;
3134 mlx5e_resume_sq(struct mlx5e_sq *sq)
3138 /* check if already enabled */
3139 if (sq->stopped == 0)
3142 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3143 MLX5_SQC_STATE_RST);
3146 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3152 /* reset doorbell prior to moving from RST to RDY */
3153 mlx5e_reset_sq_doorbell_record(sq);
3155 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3156 MLX5_SQC_STATE_RDY);
3159 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3162 mtx_lock(&sq->lock);
3163 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3165 mtx_unlock(&sq->lock);
3170 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3174 for (i = 0; i < ch->num_tc; i++)
3175 mlx5e_resume_sq(&ch->sq[i]);
3179 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3181 struct mlx5e_rq *rq = &ch->rq;
3186 callout_stop(&rq->watchdog);
3187 mtx_unlock(&rq->mtx);
3189 callout_drain(&rq->watchdog);
3191 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3194 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3197 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3199 rq->cq.mcq.comp(&rq->cq.mcq);
3203 * Transitioning into RST state will allow the FW to track less ERR state queues,
3204 * thus reducing the recv queue flushing time
3206 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3209 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3214 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3216 struct mlx5e_rq *rq = &ch->rq;
3220 mlx5_wq_ll_update_db_record(&rq->wq);
3221 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3224 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3229 rq->cq.mcq.comp(&rq->cq.mcq);
3233 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3237 if (priv->channel == NULL)
3240 for (i = 0; i < priv->params.num_channels; i++) {
3242 if (!priv->channel[i])
3246 mlx5e_disable_tx_dma(priv->channel[i]);
3248 mlx5e_enable_tx_dma(priv->channel[i]);
3253 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3257 if (priv->channel == NULL)
3260 for (i = 0; i < priv->params.num_channels; i++) {
3262 if (!priv->channel[i])
3266 mlx5e_disable_rx_dma(priv->channel[i]);
3268 mlx5e_enable_rx_dma(priv->channel[i]);
3273 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3275 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3276 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3277 sysctl_firmware, "A", "HCA firmware version");
3279 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3280 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3285 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3287 struct mlx5e_priv *priv = arg1;
3294 tx_pfc = priv->params.tx_priority_flow_control;
3296 /* get current value */
3297 value = (tx_pfc >> arg2) & 1;
3299 error = sysctl_handle_32(oidp, &value, 0, req);
3301 /* range check value */
3303 priv->params.tx_priority_flow_control |= (1 << arg2);
3305 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3307 /* check if update is required */
3308 if (error == 0 && priv->gone == 0 &&
3309 tx_pfc != priv->params.tx_priority_flow_control) {
3310 error = -mlx5e_set_port_pfc(priv);
3311 /* restore previous value */
3313 priv->params.tx_priority_flow_control= tx_pfc;
3321 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3323 struct mlx5e_priv *priv = arg1;
3330 rx_pfc = priv->params.rx_priority_flow_control;
3332 /* get current value */
3333 value = (rx_pfc >> arg2) & 1;
3335 error = sysctl_handle_32(oidp, &value, 0, req);
3337 /* range check value */
3339 priv->params.rx_priority_flow_control |= (1 << arg2);
3341 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3343 /* check if update is required */
3344 if (error == 0 && priv->gone == 0 &&
3345 rx_pfc != priv->params.rx_priority_flow_control) {
3346 error = -mlx5e_set_port_pfc(priv);
3347 /* restore previous value */
3349 priv->params.rx_priority_flow_control= rx_pfc;
3357 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3363 /* Only receiving pauseframes is enabled by default */
3364 priv->params.tx_pauseframe_control = 0;
3365 priv->params.rx_pauseframe_control = 1;
3367 /* disable ports flow control, PFC, by default */
3368 priv->params.tx_priority_flow_control = 0;
3369 priv->params.rx_priority_flow_control = 0;
3371 #if (__FreeBSD_version < 1100000)
3372 /* compute path for sysctl */
3373 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3374 device_get_unit(priv->mdev->pdev->dev.bsddev));
3376 /* try to fetch tunable, if any */
3377 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3379 /* compute path for sysctl */
3380 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3381 device_get_unit(priv->mdev->pdev->dev.bsddev));
3383 /* try to fetch tunable, if any */
3384 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3386 for (x = 0; x != 8; x++) {
3388 /* compute path for sysctl */
3389 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3390 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3392 /* try to fetch tunable, if any */
3393 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3394 priv->params.tx_priority_flow_control |= 1 << x;
3396 /* compute path for sysctl */
3397 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3398 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3400 /* try to fetch tunable, if any */
3401 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3402 priv->params.rx_priority_flow_control |= 1 << x;
3406 /* register pauseframe SYSCTLs */
3407 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3408 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3409 &priv->params.tx_pauseframe_control, 0,
3410 "Set to enable TX pause frames. Clear to disable.");
3412 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3413 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3414 &priv->params.rx_pauseframe_control, 0,
3415 "Set to enable RX pause frames. Clear to disable.");
3417 /* register priority_flow control, PFC, SYSCTLs */
3418 for (x = 0; x != 8; x++) {
3419 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3421 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3422 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3423 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3424 "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3426 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3428 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3429 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3430 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3431 "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3437 priv->params.tx_pauseframe_control =
3438 priv->params.tx_pauseframe_control ? 1 : 0;
3439 priv->params.rx_pauseframe_control =
3440 priv->params.rx_pauseframe_control ? 1 : 0;
3442 /* update firmware */
3443 error = mlx5e_set_port_pause_and_pfc(priv);
3444 if (error == -EINVAL) {
3445 if_printf(priv->ifp,
3446 "Global pauseframes must be disabled before enabling PFC.\n");
3447 priv->params.rx_priority_flow_control = 0;
3448 priv->params.tx_priority_flow_control = 0;
3450 /* update firmware */
3451 (void) mlx5e_set_port_pause_and_pfc(priv);
3457 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3460 struct mlx5e_priv *priv;
3461 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3462 struct sysctl_oid_list *child;
3463 int ncv = mdev->priv.eq_table.num_comp_vectors;
3469 if (mlx5e_check_required_hca_cap(mdev)) {
3470 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3473 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3474 mlx5e_priv_mtx_init(priv);
3476 ifp = priv->ifp = if_alloc(IFT_ETHER);
3478 mlx5_core_err(mdev, "if_alloc() failed\n");
3481 ifp->if_softc = priv;
3482 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3483 ifp->if_mtu = ETHERMTU;
3484 ifp->if_init = mlx5e_open;
3485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3486 ifp->if_ioctl = mlx5e_ioctl;
3487 ifp->if_transmit = mlx5e_xmit;
3488 ifp->if_qflush = if_qflush;
3489 #if (__FreeBSD_version >= 1100000)
3490 ifp->if_get_counter = mlx5e_get_counter;
3492 ifp->if_snd.ifq_maxlen = ifqmaxlen;
3494 * Set driver features
3496 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3497 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3498 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3499 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3500 ifp->if_capabilities |= IFCAP_LRO;
3501 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3502 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3504 /* set TSO limits so that we don't have to drop TX packets */
3505 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3506 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3507 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3509 ifp->if_capenable = ifp->if_capabilities;
3510 ifp->if_hwassist = 0;
3511 if (ifp->if_capenable & IFCAP_TSO)
3512 ifp->if_hwassist |= CSUM_TSO;
3513 if (ifp->if_capenable & IFCAP_TXCSUM)
3514 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3515 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3516 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3518 /* ifnet sysctl tree */
3519 sysctl_ctx_init(&priv->sysctl_ctx);
3520 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3521 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3522 if (priv->sysctl_ifnet == NULL) {
3523 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3524 goto err_free_sysctl;
3526 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3527 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3528 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3529 if (priv->sysctl_ifnet == NULL) {
3530 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3531 goto err_free_sysctl;
3534 /* HW sysctl tree */
3535 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3536 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3537 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3538 if (priv->sysctl_hw == NULL) {
3539 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3540 goto err_free_sysctl;
3542 mlx5e_build_ifp_priv(mdev, priv, ncv);
3543 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3545 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3547 goto err_free_sysctl;
3549 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3551 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3553 goto err_unmap_free_uar;
3555 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3557 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3559 goto err_dealloc_pd;
3561 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3563 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3565 goto err_dealloc_transport_domain;
3567 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3569 /* check if we should generate a random MAC address */
3570 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3571 is_zero_ether_addr(dev_addr)) {
3572 random_ether_addr(dev_addr);
3573 if_printf(ifp, "Assigned random MAC address\n");
3576 /* set default MTU */
3577 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3580 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3582 /* Set default media status */
3583 priv->media_status_last = IFM_AVALID;
3584 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3585 IFM_ETH_RXPAUSE | IFM_FDX;
3587 /* setup default pauseframes configuration */
3588 mlx5e_setup_pauseframes(priv);
3590 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3593 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3597 /* Setup supported medias */
3598 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3599 mlx5e_media_change, mlx5e_media_status);
3601 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3602 if (mlx5e_mode_table[i].baudrate == 0)
3604 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3605 ifmedia_add(&priv->media,
3606 mlx5e_mode_table[i].subtype |
3607 IFM_ETHER, 0, NULL);
3608 ifmedia_add(&priv->media,
3609 mlx5e_mode_table[i].subtype |
3610 IFM_ETHER | IFM_FDX |
3611 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3615 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3616 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3617 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3619 /* Set autoselect by default */
3620 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3621 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3622 ether_ifattach(ifp, dev_addr);
3624 /* Register for VLAN events */
3625 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3626 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3627 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3628 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3630 /* Link is down by default */
3631 if_link_state_change(ifp, LINK_STATE_DOWN);
3633 mlx5e_enable_async_events(priv);
3635 mlx5e_add_hw_stats(priv);
3637 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3638 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3639 priv->stats.vport.arg);
3641 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3642 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3643 priv->stats.pport.arg);
3645 mlx5e_create_ethtool(priv);
3647 mtx_lock(&priv->async_events_mtx);
3648 mlx5e_update_stats(priv);
3649 mtx_unlock(&priv->async_events_mtx);
3651 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3652 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3653 &priv->clbr_done, 0,
3654 "RX timestamps calibration state");
3655 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3656 mlx5e_reset_calibration_callout(priv);
3660 err_dealloc_transport_domain:
3661 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3664 mlx5_core_dealloc_pd(mdev, priv->pdn);
3667 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3670 sysctl_ctx_free(&priv->sysctl_ctx);
3675 mlx5e_priv_mtx_destroy(priv);
3676 free(priv, M_MLX5EN);
3681 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3683 struct mlx5e_priv *priv = vpriv;
3684 struct ifnet *ifp = priv->ifp;
3686 /* don't allow more IOCTLs */
3690 * Clear the device description to avoid use after free,
3691 * because the bsddev is not destroyed when this module is
3694 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3696 /* XXX wait a bit to allow IOCTL handlers to complete */
3699 /* stop watchdog timer */
3700 callout_drain(&priv->watchdog);
3702 callout_drain(&priv->tstmp_clbr);
3704 if (priv->vlan_attach != NULL)
3705 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3706 if (priv->vlan_detach != NULL)
3707 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3709 /* make sure device gets closed */
3711 mlx5e_close_locked(ifp);
3714 /* unregister device */
3715 ifmedia_removeall(&priv->media);
3716 ether_ifdetach(ifp);
3719 /* destroy all remaining sysctl nodes */
3720 if (priv->sysctl_debug)
3721 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3722 sysctl_ctx_free(&priv->stats.vport.ctx);
3723 sysctl_ctx_free(&priv->stats.pport.ctx);
3724 sysctl_ctx_free(&priv->sysctl_ctx);
3726 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3727 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3728 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3729 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3730 mlx5e_disable_async_events(priv);
3731 flush_scheduled_work();
3732 mlx5e_priv_mtx_destroy(priv);
3733 free(priv, M_MLX5EN);
3737 mlx5e_get_ifp(void *vpriv)
3739 struct mlx5e_priv *priv = vpriv;
3744 static struct mlx5_interface mlx5e_interface = {
3745 .add = mlx5e_create_ifp,
3746 .remove = mlx5e_destroy_ifp,
3747 .event = mlx5e_async_event,
3748 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3749 .get_dev = mlx5e_get_ifp,
3755 mlx5_register_interface(&mlx5e_interface);
3761 mlx5_unregister_interface(&mlx5e_interface);
3764 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3765 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3767 #if (__FreeBSD_version >= 1100000)
3768 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3770 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3771 MODULE_VERSION(mlx5en, 1);