2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_channel_param {
38 struct mlx5e_rq_param rq;
39 struct mlx5e_sq_param sq;
40 struct mlx5e_cq_param rx_cq;
41 struct mlx5e_cq_param tx_cq;
47 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
49 [MLX5E_1000BASE_CX_SGMII] = {
50 .subtype = IFM_1000_CX_SGMII,
51 .baudrate = IF_Mbps(1000ULL),
53 [MLX5E_1000BASE_KX] = {
54 .subtype = IFM_1000_KX,
55 .baudrate = IF_Mbps(1000ULL),
57 [MLX5E_10GBASE_CX4] = {
58 .subtype = IFM_10G_CX4,
59 .baudrate = IF_Gbps(10ULL),
61 [MLX5E_10GBASE_KX4] = {
62 .subtype = IFM_10G_KX4,
63 .baudrate = IF_Gbps(10ULL),
65 [MLX5E_10GBASE_KR] = {
66 .subtype = IFM_10G_KR,
67 .baudrate = IF_Gbps(10ULL),
69 [MLX5E_20GBASE_KR2] = {
70 .subtype = IFM_20G_KR2,
71 .baudrate = IF_Gbps(20ULL),
73 [MLX5E_40GBASE_CR4] = {
74 .subtype = IFM_40G_CR4,
75 .baudrate = IF_Gbps(40ULL),
77 [MLX5E_40GBASE_KR4] = {
78 .subtype = IFM_40G_KR4,
79 .baudrate = IF_Gbps(40ULL),
81 [MLX5E_56GBASE_R4] = {
82 .subtype = IFM_56G_R4,
83 .baudrate = IF_Gbps(56ULL),
85 [MLX5E_10GBASE_CR] = {
86 .subtype = IFM_10G_CR1,
87 .baudrate = IF_Gbps(10ULL),
89 [MLX5E_10GBASE_SR] = {
90 .subtype = IFM_10G_SR,
91 .baudrate = IF_Gbps(10ULL),
93 [MLX5E_10GBASE_ER] = {
94 .subtype = IFM_10G_ER,
95 .baudrate = IF_Gbps(10ULL),
97 [MLX5E_40GBASE_SR4] = {
98 .subtype = IFM_40G_SR4,
99 .baudrate = IF_Gbps(40ULL),
101 [MLX5E_40GBASE_LR4] = {
102 .subtype = IFM_40G_LR4,
103 .baudrate = IF_Gbps(40ULL),
105 [MLX5E_100GBASE_CR4] = {
106 .subtype = IFM_100G_CR4,
107 .baudrate = IF_Gbps(100ULL),
109 [MLX5E_100GBASE_SR4] = {
110 .subtype = IFM_100G_SR4,
111 .baudrate = IF_Gbps(100ULL),
113 [MLX5E_100GBASE_KR4] = {
114 .subtype = IFM_100G_KR4,
115 .baudrate = IF_Gbps(100ULL),
117 [MLX5E_100GBASE_LR4] = {
118 .subtype = IFM_100G_LR4,
119 .baudrate = IF_Gbps(100ULL),
121 [MLX5E_100BASE_TX] = {
122 .subtype = IFM_100_TX,
123 .baudrate = IF_Mbps(100ULL),
125 [MLX5E_1000BASE_T] = {
126 .subtype = IFM_1000_T,
127 .baudrate = IF_Mbps(1000ULL),
129 [MLX5E_10GBASE_T] = {
130 .subtype = IFM_10G_T,
131 .baudrate = IF_Gbps(10ULL),
133 [MLX5E_25GBASE_CR] = {
134 .subtype = IFM_25G_CR,
135 .baudrate = IF_Gbps(25ULL),
137 [MLX5E_25GBASE_KR] = {
138 .subtype = IFM_25G_KR,
139 .baudrate = IF_Gbps(25ULL),
141 [MLX5E_25GBASE_SR] = {
142 .subtype = IFM_25G_SR,
143 .baudrate = IF_Gbps(25ULL),
145 [MLX5E_50GBASE_CR2] = {
146 .subtype = IFM_50G_CR2,
147 .baudrate = IF_Gbps(50ULL),
149 [MLX5E_50GBASE_KR2] = {
150 .subtype = IFM_50G_KR2,
151 .baudrate = IF_Gbps(50ULL),
155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
158 mlx5e_update_carrier(struct mlx5e_priv *priv)
160 struct mlx5_core_dev *mdev = priv->mdev;
161 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
167 port_state = mlx5_query_vport_state(mdev,
168 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
170 if (port_state == VPORT_STATE_UP) {
171 priv->media_status_last |= IFM_ACTIVE;
173 priv->media_status_last &= ~IFM_ACTIVE;
174 priv->media_active_last = IFM_ETHER;
175 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
179 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
181 priv->media_active_last = IFM_ETHER;
182 priv->ifp->if_baudrate = 1;
183 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
187 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
189 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
190 if (mlx5e_mode_table[i].baudrate == 0)
192 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
193 priv->ifp->if_baudrate =
194 mlx5e_mode_table[i].baudrate;
195 priv->media_active_last =
196 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
199 if_link_state_change(priv->ifp, LINK_STATE_UP);
203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
205 struct mlx5e_priv *priv = dev->if_softc;
207 ifmr->ifm_status = priv->media_status_last;
208 ifmr->ifm_active = priv->media_active_last |
209 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
210 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
215 mlx5e_find_link_mode(u32 subtype)
220 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
221 if (mlx5e_mode_table[i].baudrate == 0)
223 if (mlx5e_mode_table[i].subtype == subtype)
224 link_mode |= MLX5E_PROT_MASK(i);
231 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
233 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
234 priv->params.rx_pauseframe_control,
235 priv->params.tx_pauseframe_control,
236 priv->params.rx_priority_flow_control,
237 priv->params.tx_priority_flow_control));
241 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
245 if (priv->params.rx_pauseframe_control ||
246 priv->params.tx_pauseframe_control) {
248 "Global pauseframes must be disabled before enabling PFC.\n");
251 error = mlx5e_set_port_pause_and_pfc(priv);
257 mlx5e_media_change(struct ifnet *dev)
259 struct mlx5e_priv *priv = dev->if_softc;
260 struct mlx5_core_dev *mdev = priv->mdev;
267 locked = PRIV_LOCKED(priv);
271 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
275 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
277 /* query supported capabilities */
278 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
280 if_printf(dev, "Query port media capability failed\n");
283 /* check for autoselect */
284 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
285 link_mode = eth_proto_cap;
286 if (link_mode == 0) {
287 if_printf(dev, "Port media capability is zero\n");
292 link_mode = link_mode & eth_proto_cap;
293 if (link_mode == 0) {
294 if_printf(dev, "Not supported link mode requested\n");
299 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
300 /* check if PFC is enabled */
301 if (priv->params.rx_priority_flow_control ||
302 priv->params.tx_priority_flow_control) {
303 if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
308 /* update pauseframe control bits */
309 priv->params.rx_pauseframe_control =
310 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
311 priv->params.tx_pauseframe_control =
312 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
314 /* check if device is opened */
315 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
317 /* reconfigure the hardware */
318 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
319 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
320 error = -mlx5e_set_port_pause_and_pfc(priv);
322 mlx5_set_port_status(mdev, MLX5_PORT_UP);
331 mlx5e_update_carrier_work(struct work_struct *work)
333 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
334 update_carrier_work);
337 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
338 mlx5e_update_carrier(priv);
343 * This function reads the physical port counters from the firmware
344 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
345 * macros. The output is converted from big-endian 64-bit values into
346 * host endian ones and stored in the "priv->stats.pport" structure.
349 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
351 struct mlx5_core_dev *mdev = priv->mdev;
352 struct mlx5e_pport_stats *s = &priv->stats.pport;
353 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
357 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
362 /* allocate firmware request structures */
363 in = mlx5_vzalloc(sz);
364 out = mlx5_vzalloc(sz);
365 if (in == NULL || out == NULL)
369 * Get pointer to the 64-bit counter set which is located at a
370 * fixed offset in the output firmware request structure:
372 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
374 MLX5_SET(ppcnt_reg, in, local_port, 1);
376 /* read IEEE802_3 counter group using predefined counter layout */
377 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
378 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
379 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
380 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
381 s->arg[y] = be64toh(ptr[x]);
383 /* read RFC2819 counter group using predefined counter layout */
384 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
385 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
386 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
387 s->arg[y] = be64toh(ptr[x]);
388 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
389 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
390 s_debug->arg[y] = be64toh(ptr[x]);
392 /* read RFC2863 counter group using predefined counter layout */
393 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
394 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
395 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
396 s_debug->arg[y] = be64toh(ptr[x]);
398 /* read physical layer stats counter group using predefined counter layout */
399 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
400 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
401 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
402 s_debug->arg[y] = be64toh(ptr[x]);
404 /* read per-priority counters */
405 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
407 /* iterate all the priorities */
408 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
409 MLX5_SET(ppcnt_reg, in, prio_tc, z);
410 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
412 /* read per priority stats counter group using predefined counter layout */
413 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
414 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
415 s->arg[y] = be64toh(ptr[x]);
418 /* free firmware request structures */
424 * This function is called regularly to collect all statistics
425 * counters from the firmware. The values can be viewed through the
426 * sysctl interface. Execution is serialized using the priv's global
427 * configuration lock.
430 mlx5e_update_stats_work(struct work_struct *work)
432 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
434 struct mlx5_core_dev *mdev = priv->mdev;
435 struct mlx5e_vport_stats *s = &priv->stats.vport;
436 struct mlx5e_rq_stats *rq_stats;
437 struct mlx5e_sq_stats *sq_stats;
438 struct buf_ring *sq_br;
439 #if (__FreeBSD_version < 1100000)
440 struct ifnet *ifp = priv->ifp;
443 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
445 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
448 u64 tx_queue_dropped = 0;
449 u64 tx_defragged = 0;
450 u64 tx_offload_none = 0;
453 u64 sw_lro_queued = 0;
454 u64 sw_lro_flushed = 0;
455 u64 rx_csum_none = 0;
457 u32 rx_out_of_buffer = 0;
462 out = mlx5_vzalloc(outlen);
465 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
468 /* Collect firts the SW counters and then HW for consistency */
469 for (i = 0; i < priv->params.num_channels; i++) {
470 struct mlx5e_rq *rq = &priv->channel[i]->rq;
472 rq_stats = &priv->channel[i]->rq.stats;
474 /* collect stats from LRO */
475 rq_stats->sw_lro_queued = rq->lro.lro_queued;
476 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
477 sw_lro_queued += rq_stats->sw_lro_queued;
478 sw_lro_flushed += rq_stats->sw_lro_flushed;
479 lro_packets += rq_stats->lro_packets;
480 lro_bytes += rq_stats->lro_bytes;
481 rx_csum_none += rq_stats->csum_none;
482 rx_wqe_err += rq_stats->wqe_err;
484 for (j = 0; j < priv->num_tc; j++) {
485 sq_stats = &priv->channel[i]->sq[j].stats;
486 sq_br = priv->channel[i]->sq[j].br;
488 tso_packets += sq_stats->tso_packets;
489 tso_bytes += sq_stats->tso_bytes;
490 tx_queue_dropped += sq_stats->dropped;
492 tx_queue_dropped += sq_br->br_drops;
493 tx_defragged += sq_stats->defragged;
494 tx_offload_none += sq_stats->csum_offload_none;
498 /* update counters */
499 s->tso_packets = tso_packets;
500 s->tso_bytes = tso_bytes;
501 s->tx_queue_dropped = tx_queue_dropped;
502 s->tx_defragged = tx_defragged;
503 s->lro_packets = lro_packets;
504 s->lro_bytes = lro_bytes;
505 s->sw_lro_queued = sw_lro_queued;
506 s->sw_lro_flushed = sw_lro_flushed;
507 s->rx_csum_none = rx_csum_none;
508 s->rx_wqe_err = rx_wqe_err;
511 memset(in, 0, sizeof(in));
513 MLX5_SET(query_vport_counter_in, in, opcode,
514 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
515 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
516 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
518 memset(out, 0, outlen);
520 /* get number of out-of-buffer drops first */
521 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
525 /* accumulate difference into a 64-bit counter */
526 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
527 s->rx_out_of_buffer_prev = rx_out_of_buffer;
529 /* get port statistics */
530 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
533 #define MLX5_GET_CTR(out, x) \
534 MLX5_GET64(query_vport_counter_out, out, x)
536 s->rx_error_packets =
537 MLX5_GET_CTR(out, received_errors.packets);
539 MLX5_GET_CTR(out, received_errors.octets);
540 s->tx_error_packets =
541 MLX5_GET_CTR(out, transmit_errors.packets);
543 MLX5_GET_CTR(out, transmit_errors.octets);
545 s->rx_unicast_packets =
546 MLX5_GET_CTR(out, received_eth_unicast.packets);
547 s->rx_unicast_bytes =
548 MLX5_GET_CTR(out, received_eth_unicast.octets);
549 s->tx_unicast_packets =
550 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
551 s->tx_unicast_bytes =
552 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
554 s->rx_multicast_packets =
555 MLX5_GET_CTR(out, received_eth_multicast.packets);
556 s->rx_multicast_bytes =
557 MLX5_GET_CTR(out, received_eth_multicast.octets);
558 s->tx_multicast_packets =
559 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
560 s->tx_multicast_bytes =
561 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
563 s->rx_broadcast_packets =
564 MLX5_GET_CTR(out, received_eth_broadcast.packets);
565 s->rx_broadcast_bytes =
566 MLX5_GET_CTR(out, received_eth_broadcast.octets);
567 s->tx_broadcast_packets =
568 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
569 s->tx_broadcast_bytes =
570 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
573 s->rx_unicast_packets +
574 s->rx_multicast_packets +
575 s->rx_broadcast_packets -
578 s->rx_unicast_bytes +
579 s->rx_multicast_bytes +
580 s->rx_broadcast_bytes;
582 s->tx_unicast_packets +
583 s->tx_multicast_packets +
584 s->tx_broadcast_packets;
586 s->tx_unicast_bytes +
587 s->tx_multicast_bytes +
588 s->tx_broadcast_bytes;
590 /* Update calculated offload counters */
591 s->tx_csum_offload = s->tx_packets - tx_offload_none;
592 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
594 /* Get physical port counters */
595 mlx5e_update_pport_counters(priv);
597 #if (__FreeBSD_version < 1100000)
598 /* no get_counters interface in fbsd 10 */
599 ifp->if_ipackets = s->rx_packets;
600 ifp->if_ierrors = s->rx_error_packets +
601 priv->stats.pport.alignment_err +
602 priv->stats.pport.check_seq_err +
603 priv->stats.pport.crc_align_errors +
604 priv->stats.pport.in_range_len_errors +
605 priv->stats.pport.jabbers +
606 priv->stats.pport.out_of_range_len +
607 priv->stats.pport.oversize_pkts +
608 priv->stats.pport.symbol_err +
609 priv->stats.pport.too_long_errors +
610 priv->stats.pport.undersize_pkts +
611 priv->stats.pport.unsupported_op_rx;
612 ifp->if_iqdrops = s->rx_out_of_buffer +
613 priv->stats.pport.drop_events;
614 ifp->if_opackets = s->tx_packets;
615 ifp->if_oerrors = s->tx_error_packets;
616 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
617 ifp->if_ibytes = s->rx_bytes;
618 ifp->if_obytes = s->tx_bytes;
620 priv->stats.pport.collisions;
626 /* Update diagnostics, if any */
627 if (priv->params_ethtool.diag_pci_enable ||
628 priv->params_ethtool.diag_general_enable) {
629 int error = mlx5_core_get_diagnostics_full(mdev,
630 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
631 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
633 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
639 mlx5e_update_stats(void *arg)
641 struct mlx5e_priv *priv = arg;
643 queue_work(priv->wq, &priv->update_stats_work);
645 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
649 mlx5e_async_event_sub(struct mlx5e_priv *priv,
650 enum mlx5_dev_event event)
653 case MLX5_DEV_EVENT_PORT_UP:
654 case MLX5_DEV_EVENT_PORT_DOWN:
655 queue_work(priv->wq, &priv->update_carrier_work);
664 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
665 enum mlx5_dev_event event, unsigned long param)
667 struct mlx5e_priv *priv = vpriv;
669 mtx_lock(&priv->async_events_mtx);
670 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
671 mlx5e_async_event_sub(priv, event);
672 mtx_unlock(&priv->async_events_mtx);
676 mlx5e_enable_async_events(struct mlx5e_priv *priv)
678 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
682 mlx5e_disable_async_events(struct mlx5e_priv *priv)
684 mtx_lock(&priv->async_events_mtx);
685 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
686 mtx_unlock(&priv->async_events_mtx);
689 static const char *mlx5e_rq_stats_desc[] = {
690 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
694 mlx5e_create_rq(struct mlx5e_channel *c,
695 struct mlx5e_rq_param *param,
698 struct mlx5e_priv *priv = c->priv;
699 struct mlx5_core_dev *mdev = priv->mdev;
701 void *rqc = param->rqc;
702 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
707 /* Create DMA descriptor TAG */
708 if ((err = -bus_dma_tag_create(
709 bus_get_dma_tag(mdev->pdev->dev.bsddev),
710 1, /* any alignment */
712 BUS_SPACE_MAXADDR, /* lowaddr */
713 BUS_SPACE_MAXADDR, /* highaddr */
714 NULL, NULL, /* filter, filterarg */
715 MJUM16BYTES, /* maxsize */
717 MJUM16BYTES, /* maxsegsize */
719 NULL, NULL, /* lockfunc, lockfuncarg */
723 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
726 goto err_free_dma_tag;
728 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
730 if (priv->params.hw_lro_en) {
731 rq->wqe_sz = priv->params.lro_wqe_sz;
733 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
735 if (rq->wqe_sz > MJUM16BYTES) {
737 goto err_rq_wq_destroy;
738 } else if (rq->wqe_sz > MJUM9BYTES) {
739 rq->wqe_sz = MJUM16BYTES;
740 } else if (rq->wqe_sz > MJUMPAGESIZE) {
741 rq->wqe_sz = MJUM9BYTES;
742 } else if (rq->wqe_sz > MCLBYTES) {
743 rq->wqe_sz = MJUMPAGESIZE;
745 rq->wqe_sz = MCLBYTES;
748 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
750 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
752 goto err_rq_wq_destroy;
754 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
755 for (i = 0; i != wq_sz; i++) {
756 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
757 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
759 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
762 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
763 goto err_rq_mbuf_free;
765 wqe->data.lkey = c->mkey_be;
766 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
773 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
774 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
775 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
780 free(rq->mbuf, M_MLX5EN);
781 tcp_lro_free(&rq->lro);
783 mlx5_wq_destroy(&rq->wq_ctrl);
785 bus_dma_tag_destroy(rq->dma_tag);
791 mlx5e_destroy_rq(struct mlx5e_rq *rq)
796 /* destroy all sysctl nodes */
797 sysctl_ctx_free(&rq->stats.ctx);
799 /* free leftover LRO packets, if any */
800 tcp_lro_free(&rq->lro);
802 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
803 for (i = 0; i != wq_sz; i++) {
804 if (rq->mbuf[i].mbuf != NULL) {
805 bus_dmamap_unload(rq->dma_tag,
806 rq->mbuf[i].dma_map);
807 m_freem(rq->mbuf[i].mbuf);
809 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
811 free(rq->mbuf, M_MLX5EN);
812 mlx5_wq_destroy(&rq->wq_ctrl);
816 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
818 struct mlx5e_channel *c = rq->channel;
819 struct mlx5e_priv *priv = c->priv;
820 struct mlx5_core_dev *mdev = priv->mdev;
828 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
829 sizeof(u64) * rq->wq_ctrl.buf.npages;
830 in = mlx5_vzalloc(inlen);
834 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
835 wq = MLX5_ADDR_OF(rqc, rqc, wq);
837 memcpy(rqc, param->rqc, sizeof(param->rqc));
839 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
840 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
841 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
842 if (priv->counter_set_id >= 0)
843 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
844 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
846 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
848 mlx5_fill_page_array(&rq->wq_ctrl.buf,
849 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
851 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
859 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
861 struct mlx5e_channel *c = rq->channel;
862 struct mlx5e_priv *priv = c->priv;
863 struct mlx5_core_dev *mdev = priv->mdev;
870 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
871 in = mlx5_vzalloc(inlen);
875 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
877 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
878 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
879 MLX5_SET(rqc, rqc, state, next_state);
881 err = mlx5_core_modify_rq(mdev, in, inlen);
889 mlx5e_disable_rq(struct mlx5e_rq *rq)
891 struct mlx5e_channel *c = rq->channel;
892 struct mlx5e_priv *priv = c->priv;
893 struct mlx5_core_dev *mdev = priv->mdev;
895 mlx5_core_destroy_rq(mdev, rq->rqn);
899 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
901 struct mlx5e_channel *c = rq->channel;
902 struct mlx5e_priv *priv = c->priv;
903 struct mlx5_wq_ll *wq = &rq->wq;
906 for (i = 0; i < 1000; i++) {
907 if (wq->cur_sz >= priv->params.min_rx_wqes)
916 mlx5e_open_rq(struct mlx5e_channel *c,
917 struct mlx5e_rq_param *param,
922 err = mlx5e_create_rq(c, param, rq);
926 err = mlx5e_enable_rq(rq, param);
930 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
939 mlx5e_disable_rq(rq);
941 mlx5e_destroy_rq(rq);
947 mlx5e_close_rq(struct mlx5e_rq *rq)
951 callout_stop(&rq->watchdog);
952 mtx_unlock(&rq->mtx);
954 callout_drain(&rq->watchdog);
956 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
960 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
962 /* wait till RQ is empty */
963 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
965 rq->cq.mcq.comp(&rq->cq.mcq);
968 mlx5e_disable_rq(rq);
969 mlx5e_destroy_rq(rq);
973 mlx5e_free_sq_db(struct mlx5e_sq *sq)
975 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
978 for (x = 0; x != wq_sz; x++)
979 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
980 free(sq->mbuf, M_MLX5EN);
984 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
986 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
990 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
992 /* Create DMA descriptor MAPs */
993 for (x = 0; x != wq_sz; x++) {
994 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
997 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
998 free(sq->mbuf, M_MLX5EN);
1005 static const char *mlx5e_sq_stats_desc[] = {
1006 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1010 mlx5e_create_sq(struct mlx5e_channel *c,
1012 struct mlx5e_sq_param *param,
1013 struct mlx5e_sq *sq)
1015 struct mlx5e_priv *priv = c->priv;
1016 struct mlx5_core_dev *mdev = priv->mdev;
1019 void *sqc = param->sqc;
1020 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1027 /* Create DMA descriptor TAG */
1028 if ((err = -bus_dma_tag_create(
1029 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1030 1, /* any alignment */
1031 0, /* no boundary */
1032 BUS_SPACE_MAXADDR, /* lowaddr */
1033 BUS_SPACE_MAXADDR, /* highaddr */
1034 NULL, NULL, /* filter, filterarg */
1035 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1036 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1037 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1039 NULL, NULL, /* lockfunc, lockfuncarg */
1043 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1045 goto err_free_dma_tag;
1047 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1050 goto err_unmap_free_uar;
1052 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1053 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1055 err = mlx5e_alloc_sq_db(sq);
1057 goto err_sq_wq_destroy;
1059 sq->mkey_be = c->mkey_be;
1060 sq->ifp = priv->ifp;
1064 /* check if we should allocate a second packet buffer */
1065 if (priv->params_ethtool.tx_bufring_disable == 0) {
1066 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1067 M_WAITOK, &sq->lock);
1068 if (sq->br == NULL) {
1069 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1072 goto err_free_sq_db;
1075 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1076 taskqueue_thread_enqueue, &sq->sq_tq);
1077 if (sq->sq_tq == NULL) {
1078 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1084 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1086 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1087 CPU_SETOF(cpu_id, &cpu_mask);
1088 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1089 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1091 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1092 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1095 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1096 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1097 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1103 buf_ring_free(sq->br, M_MLX5EN);
1105 mlx5e_free_sq_db(sq);
1107 mlx5_wq_destroy(&sq->wq_ctrl);
1110 mlx5_unmap_free_uar(mdev, &sq->uar);
1113 bus_dma_tag_destroy(sq->dma_tag);
1119 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1121 /* destroy all sysctl nodes */
1122 sysctl_ctx_free(&sq->stats.ctx);
1124 mlx5e_free_sq_db(sq);
1125 mlx5_wq_destroy(&sq->wq_ctrl);
1126 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1127 if (sq->sq_tq != NULL) {
1128 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1129 taskqueue_free(sq->sq_tq);
1132 buf_ring_free(sq->br, M_MLX5EN);
1136 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1145 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1146 sizeof(u64) * sq->wq_ctrl.buf.npages;
1147 in = mlx5_vzalloc(inlen);
1151 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1152 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1154 memcpy(sqc, param->sqc, sizeof(param->sqc));
1156 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1157 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1158 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1159 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1160 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1162 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1163 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1164 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1166 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1168 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1169 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1171 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1179 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1186 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1187 in = mlx5_vzalloc(inlen);
1191 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1193 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1194 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1195 MLX5_SET(sqc, sqc, state, next_state);
1197 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1205 mlx5e_disable_sq(struct mlx5e_sq *sq)
1208 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1212 mlx5e_open_sq(struct mlx5e_channel *c,
1214 struct mlx5e_sq_param *param,
1215 struct mlx5e_sq *sq)
1219 err = mlx5e_create_sq(c, tc, param, sq);
1223 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1225 goto err_destroy_sq;
1227 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1229 goto err_disable_sq;
1231 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1236 mlx5e_disable_sq(sq);
1238 mlx5e_destroy_sq(sq);
1244 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1246 /* fill up remainder with NOPs */
1247 while (sq->cev_counter != 0) {
1248 while (!mlx5e_sq_has_room_for(sq, 1)) {
1249 if (can_sleep != 0) {
1250 mtx_unlock(&sq->lock);
1252 mtx_lock(&sq->lock);
1257 /* send a single NOP */
1258 mlx5e_send_nop(sq, 1);
1259 atomic_thread_fence_rel();
1262 /* Check if we need to write the doorbell */
1263 if (likely(sq->doorbell.d64 != 0)) {
1264 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1265 sq->doorbell.d64 = 0;
1270 mlx5e_sq_cev_timeout(void *arg)
1272 struct mlx5e_sq *sq = arg;
1274 mtx_assert(&sq->lock, MA_OWNED);
1276 /* check next state */
1277 switch (sq->cev_next_state) {
1278 case MLX5E_CEV_STATE_SEND_NOPS:
1279 /* fill TX ring with NOPs, if any */
1280 mlx5e_sq_send_nops_locked(sq, 0);
1282 /* check if completed */
1283 if (sq->cev_counter == 0) {
1284 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1289 /* send NOPs on next timeout */
1290 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1295 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1299 mlx5e_drain_sq(struct mlx5e_sq *sq)
1304 * Check if already stopped.
1306 * NOTE: The "stopped" variable is only written when both the
1307 * priv's configuration lock and the SQ's lock is locked. It
1308 * can therefore safely be read when only one of the two locks
1309 * is locked. This function is always called when the priv's
1310 * configuration lock is locked.
1312 if (sq->stopped != 0)
1315 mtx_lock(&sq->lock);
1317 /* don't put more packets into the SQ */
1320 /* teardown event factor timer, if any */
1321 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1322 callout_stop(&sq->cev_callout);
1324 /* send dummy NOPs in order to flush the transmit ring */
1325 mlx5e_sq_send_nops_locked(sq, 1);
1326 mtx_unlock(&sq->lock);
1328 /* make sure it is safe to free the callout */
1329 callout_drain(&sq->cev_callout);
1331 /* wait till SQ is empty or link is down */
1332 mtx_lock(&sq->lock);
1333 while (sq->cc != sq->pc &&
1334 (sq->priv->media_status_last & IFM_ACTIVE) != 0) {
1335 mtx_unlock(&sq->lock);
1337 sq->cq.mcq.comp(&sq->cq.mcq);
1338 mtx_lock(&sq->lock);
1340 mtx_unlock(&sq->lock);
1342 /* error out remaining requests */
1343 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1346 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1349 /* wait till SQ is empty */
1350 mtx_lock(&sq->lock);
1351 while (sq->cc != sq->pc) {
1352 mtx_unlock(&sq->lock);
1354 sq->cq.mcq.comp(&sq->cq.mcq);
1355 mtx_lock(&sq->lock);
1357 mtx_unlock(&sq->lock);
1361 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1365 mlx5e_disable_sq(sq);
1366 mlx5e_destroy_sq(sq);
1370 mlx5e_create_cq(struct mlx5e_priv *priv,
1371 struct mlx5e_cq_param *param,
1372 struct mlx5e_cq *cq,
1373 mlx5e_cq_comp_t *comp,
1376 struct mlx5_core_dev *mdev = priv->mdev;
1377 struct mlx5_core_cq *mcq = &cq->mcq;
1383 param->wq.buf_numa_node = 0;
1384 param->wq.db_numa_node = 0;
1386 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1391 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1394 mcq->set_ci_db = cq->wq_ctrl.db.db;
1395 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1396 *mcq->set_ci_db = 0;
1398 mcq->vector = eq_ix;
1400 mcq->event = mlx5e_cq_error_event;
1402 mcq->uar = &priv->cq_uar;
1404 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1405 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1416 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1418 mlx5_wq_destroy(&cq->wq_ctrl);
1422 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1424 struct mlx5_core_cq *mcq = &cq->mcq;
1432 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1433 sizeof(u64) * cq->wq_ctrl.buf.npages;
1434 in = mlx5_vzalloc(inlen);
1438 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1440 memcpy(cqc, param->cqc, sizeof(param->cqc));
1442 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1443 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1445 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1447 MLX5_SET(cqc, cqc, c_eqn, eqn);
1448 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1449 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1451 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1453 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1460 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1466 mlx5e_disable_cq(struct mlx5e_cq *cq)
1469 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1473 mlx5e_open_cq(struct mlx5e_priv *priv,
1474 struct mlx5e_cq_param *param,
1475 struct mlx5e_cq *cq,
1476 mlx5e_cq_comp_t *comp,
1481 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1485 err = mlx5e_enable_cq(cq, param, eq_ix);
1487 goto err_destroy_cq;
1492 mlx5e_destroy_cq(cq);
1498 mlx5e_close_cq(struct mlx5e_cq *cq)
1500 mlx5e_disable_cq(cq);
1501 mlx5e_destroy_cq(cq);
1505 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1506 struct mlx5e_channel_param *cparam)
1511 for (tc = 0; tc < c->num_tc; tc++) {
1512 /* open completion queue */
1513 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1514 &mlx5e_tx_cq_comp, c->ix);
1516 goto err_close_tx_cqs;
1521 for (tc--; tc >= 0; tc--)
1522 mlx5e_close_cq(&c->sq[tc].cq);
1528 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1532 for (tc = 0; tc < c->num_tc; tc++)
1533 mlx5e_close_cq(&c->sq[tc].cq);
1537 mlx5e_open_sqs(struct mlx5e_channel *c,
1538 struct mlx5e_channel_param *cparam)
1543 for (tc = 0; tc < c->num_tc; tc++) {
1544 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1552 for (tc--; tc >= 0; tc--)
1553 mlx5e_close_sq_wait(&c->sq[tc]);
1559 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1563 for (tc = 0; tc < c->num_tc; tc++)
1564 mlx5e_close_sq_wait(&c->sq[tc]);
1568 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1572 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1574 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1576 for (tc = 0; tc < c->num_tc; tc++) {
1577 struct mlx5e_sq *sq = c->sq + tc;
1579 mtx_init(&sq->lock, "mlx5tx",
1580 MTX_NETWORK_LOCK " TX", MTX_DEF);
1581 mtx_init(&sq->comp_lock, "mlx5comp",
1582 MTX_NETWORK_LOCK " TX", MTX_DEF);
1584 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1586 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1588 /* ensure the TX completion event factor is not zero */
1589 if (sq->cev_factor == 0)
1595 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1599 mtx_destroy(&c->rq.mtx);
1601 for (tc = 0; tc < c->num_tc; tc++) {
1602 mtx_destroy(&c->sq[tc].lock);
1603 mtx_destroy(&c->sq[tc].comp_lock);
1608 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1609 struct mlx5e_channel_param *cparam,
1610 struct mlx5e_channel *volatile *cp)
1612 struct mlx5e_channel *c;
1615 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1620 c->mkey_be = cpu_to_be32(priv->mr.key);
1621 c->num_tc = priv->num_tc;
1624 mlx5e_chan_mtx_init(c);
1626 /* open transmit completion queue */
1627 err = mlx5e_open_tx_cqs(c, cparam);
1631 /* open receive completion queue */
1632 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1633 &mlx5e_rx_cq_comp, c->ix);
1635 goto err_close_tx_cqs;
1637 err = mlx5e_open_sqs(c, cparam);
1639 goto err_close_rx_cq;
1641 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1645 /* store channel pointer */
1648 /* poll receive queue initially */
1649 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1654 mlx5e_close_sqs_wait(c);
1657 mlx5e_close_cq(&c->rq.cq);
1660 mlx5e_close_tx_cqs(c);
1663 /* destroy mutexes */
1664 mlx5e_chan_mtx_destroy(c);
1670 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1672 struct mlx5e_channel *c = *pp;
1674 /* check if channel is already closed */
1677 mlx5e_close_rq(&c->rq);
1681 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1683 struct mlx5e_channel *c = *pp;
1685 /* check if channel is already closed */
1688 /* ensure channel pointer is no longer used */
1691 mlx5e_close_rq_wait(&c->rq);
1692 mlx5e_close_sqs_wait(c);
1693 mlx5e_close_cq(&c->rq.cq);
1694 mlx5e_close_tx_cqs(c);
1695 /* destroy mutexes */
1696 mlx5e_chan_mtx_destroy(c);
1701 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1702 struct mlx5e_rq_param *param)
1704 void *rqc = param->rqc;
1705 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1707 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1708 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1709 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1710 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1711 MLX5_SET(wq, wq, pd, priv->pdn);
1713 param->wq.buf_numa_node = 0;
1714 param->wq.db_numa_node = 0;
1715 param->wq.linear = 1;
1719 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1720 struct mlx5e_sq_param *param)
1722 void *sqc = param->sqc;
1723 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1725 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1726 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1727 MLX5_SET(wq, wq, pd, priv->pdn);
1729 param->wq.buf_numa_node = 0;
1730 param->wq.db_numa_node = 0;
1731 param->wq.linear = 1;
1735 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1736 struct mlx5e_cq_param *param)
1738 void *cqc = param->cqc;
1740 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1744 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1745 struct mlx5e_cq_param *param)
1747 void *cqc = param->cqc;
1751 * TODO The sysctl to control on/off is a bool value for now, which means
1752 * we only support CSUM, once HASH is implemnted we'll need to address that.
1754 if (priv->params.cqe_zipping_en) {
1755 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1756 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1759 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1760 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1761 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1763 switch (priv->params.rx_cq_moderation_mode) {
1765 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1768 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1769 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1771 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1775 mlx5e_build_common_cq_param(priv, param);
1779 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1780 struct mlx5e_cq_param *param)
1782 void *cqc = param->cqc;
1784 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1785 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1786 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1788 switch (priv->params.tx_cq_moderation_mode) {
1790 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1793 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1794 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1796 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1800 mlx5e_build_common_cq_param(priv, param);
1804 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1805 struct mlx5e_channel_param *cparam)
1807 memset(cparam, 0, sizeof(*cparam));
1809 mlx5e_build_rq_param(priv, &cparam->rq);
1810 mlx5e_build_sq_param(priv, &cparam->sq);
1811 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1812 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1816 mlx5e_open_channels(struct mlx5e_priv *priv)
1818 struct mlx5e_channel_param cparam;
1824 priv->channel = malloc(priv->params.num_channels *
1825 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1827 mlx5e_build_channel_param(priv, &cparam);
1828 for (i = 0; i < priv->params.num_channels; i++) {
1829 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1831 goto err_close_channels;
1834 for (j = 0; j < priv->params.num_channels; j++) {
1835 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1837 goto err_close_channels;
1843 for (i--; i >= 0; i--) {
1844 mlx5e_close_channel(&priv->channel[i]);
1845 mlx5e_close_channel_wait(&priv->channel[i]);
1848 /* remove "volatile" attribute from "channel" pointer */
1849 ptr = __DECONST(void *, priv->channel);
1850 priv->channel = NULL;
1852 free(ptr, M_MLX5EN);
1858 mlx5e_close_channels(struct mlx5e_priv *priv)
1863 if (priv->channel == NULL)
1866 for (i = 0; i < priv->params.num_channels; i++)
1867 mlx5e_close_channel(&priv->channel[i]);
1868 for (i = 0; i < priv->params.num_channels; i++)
1869 mlx5e_close_channel_wait(&priv->channel[i]);
1871 /* remove "volatile" attribute from "channel" pointer */
1872 ptr = __DECONST(void *, priv->channel);
1873 priv->channel = NULL;
1875 free(ptr, M_MLX5EN);
1879 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1882 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1885 switch (priv->params.tx_cq_moderation_mode) {
1887 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1890 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1894 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1895 priv->params.tx_cq_moderation_usec,
1896 priv->params.tx_cq_moderation_pkts,
1900 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1901 priv->params.tx_cq_moderation_usec,
1902 priv->params.tx_cq_moderation_pkts));
1906 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1909 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1913 switch (priv->params.rx_cq_moderation_mode) {
1915 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1918 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1922 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1923 priv->params.rx_cq_moderation_usec,
1924 priv->params.rx_cq_moderation_pkts,
1930 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1931 priv->params.rx_cq_moderation_usec,
1932 priv->params.rx_cq_moderation_pkts));
1936 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1944 err = mlx5e_refresh_rq_params(priv, &c->rq);
1948 for (i = 0; i != c->num_tc; i++) {
1949 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1958 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1962 if (priv->channel == NULL)
1965 for (i = 0; i < priv->params.num_channels; i++) {
1968 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1976 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1978 struct mlx5_core_dev *mdev = priv->mdev;
1979 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1980 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1982 memset(in, 0, sizeof(in));
1984 MLX5_SET(tisc, tisc, prio, tc);
1985 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1987 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1991 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1993 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1997 mlx5e_open_tises(struct mlx5e_priv *priv)
1999 int num_tc = priv->num_tc;
2003 for (tc = 0; tc < num_tc; tc++) {
2004 err = mlx5e_open_tis(priv, tc);
2006 goto err_close_tises;
2012 for (tc--; tc >= 0; tc--)
2013 mlx5e_close_tis(priv, tc);
2019 mlx5e_close_tises(struct mlx5e_priv *priv)
2021 int num_tc = priv->num_tc;
2024 for (tc = 0; tc < num_tc; tc++)
2025 mlx5e_close_tis(priv, tc);
2029 mlx5e_open_rqt(struct mlx5e_priv *priv)
2031 struct mlx5_core_dev *mdev = priv->mdev;
2033 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2040 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2042 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2043 in = mlx5_vzalloc(inlen);
2046 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2048 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2049 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2051 for (i = 0; i < sz; i++) {
2054 ix = rss_get_indirection_to_bucket(i);
2058 /* ensure we don't overflow */
2059 ix %= priv->params.num_channels;
2060 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2063 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2065 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2067 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2075 mlx5e_close_rqt(struct mlx5e_priv *priv)
2077 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2078 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2080 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2081 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2083 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2087 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2089 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2092 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2094 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2096 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2097 MLX5_HASH_FIELD_SEL_DST_IP)
2099 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2100 MLX5_HASH_FIELD_SEL_DST_IP |\
2101 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2102 MLX5_HASH_FIELD_SEL_L4_DPORT)
2104 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2105 MLX5_HASH_FIELD_SEL_DST_IP |\
2106 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2108 if (priv->params.hw_lro_en) {
2109 MLX5_SET(tirc, tirc, lro_enable_mask,
2110 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2111 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2112 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2113 (priv->params.lro_wqe_sz -
2114 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2115 /* TODO: add the option to choose timer value dynamically */
2116 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2117 MLX5_CAP_ETH(priv->mdev,
2118 lro_timer_supported_periods[2]));
2121 /* setup parameters for hashing TIR type, if any */
2124 MLX5_SET(tirc, tirc, disp_type,
2125 MLX5_TIRC_DISP_TYPE_DIRECT);
2126 MLX5_SET(tirc, tirc, inline_rqn,
2127 priv->channel[0]->rq.rqn);
2130 MLX5_SET(tirc, tirc, disp_type,
2131 MLX5_TIRC_DISP_TYPE_INDIRECT);
2132 MLX5_SET(tirc, tirc, indirect_table,
2134 MLX5_SET(tirc, tirc, rx_hash_fn,
2135 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2136 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2139 * The FreeBSD RSS implementation does currently not
2140 * support symmetric Toeplitz hashes:
2142 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2143 rss_getkey((uint8_t *)hkey);
2145 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2146 hkey[0] = cpu_to_be32(0xD181C62C);
2147 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2148 hkey[2] = cpu_to_be32(0x1983A2FC);
2149 hkey[3] = cpu_to_be32(0x943E1ADB);
2150 hkey[4] = cpu_to_be32(0xD9389E6B);
2151 hkey[5] = cpu_to_be32(0xD1039C2C);
2152 hkey[6] = cpu_to_be32(0xA74499AD);
2153 hkey[7] = cpu_to_be32(0x593D56D9);
2154 hkey[8] = cpu_to_be32(0xF3253C06);
2155 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2161 case MLX5E_TT_IPV4_TCP:
2162 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2163 MLX5_L3_PROT_TYPE_IPV4);
2164 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2165 MLX5_L4_PROT_TYPE_TCP);
2167 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2168 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2172 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2176 case MLX5E_TT_IPV6_TCP:
2177 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2178 MLX5_L3_PROT_TYPE_IPV6);
2179 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2180 MLX5_L4_PROT_TYPE_TCP);
2182 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2183 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2187 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2191 case MLX5E_TT_IPV4_UDP:
2192 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2193 MLX5_L3_PROT_TYPE_IPV4);
2194 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2195 MLX5_L4_PROT_TYPE_UDP);
2197 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2198 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2202 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2206 case MLX5E_TT_IPV6_UDP:
2207 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2208 MLX5_L3_PROT_TYPE_IPV6);
2209 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2210 MLX5_L4_PROT_TYPE_UDP);
2212 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2213 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2217 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2221 case MLX5E_TT_IPV4_IPSEC_AH:
2222 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2223 MLX5_L3_PROT_TYPE_IPV4);
2224 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2225 MLX5_HASH_IP_IPSEC_SPI);
2228 case MLX5E_TT_IPV6_IPSEC_AH:
2229 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2230 MLX5_L3_PROT_TYPE_IPV6);
2231 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2232 MLX5_HASH_IP_IPSEC_SPI);
2235 case MLX5E_TT_IPV4_IPSEC_ESP:
2236 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2237 MLX5_L3_PROT_TYPE_IPV4);
2238 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2239 MLX5_HASH_IP_IPSEC_SPI);
2242 case MLX5E_TT_IPV6_IPSEC_ESP:
2243 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2244 MLX5_L3_PROT_TYPE_IPV6);
2245 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2246 MLX5_HASH_IP_IPSEC_SPI);
2250 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2251 MLX5_L3_PROT_TYPE_IPV4);
2252 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2257 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2258 MLX5_L3_PROT_TYPE_IPV6);
2259 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2269 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2271 struct mlx5_core_dev *mdev = priv->mdev;
2277 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2278 in = mlx5_vzalloc(inlen);
2281 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2283 mlx5e_build_tir_ctx(priv, tirc, tt);
2285 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2293 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2295 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2299 mlx5e_open_tirs(struct mlx5e_priv *priv)
2304 for (i = 0; i < MLX5E_NUM_TT; i++) {
2305 err = mlx5e_open_tir(priv, i);
2307 goto err_close_tirs;
2313 for (i--; i >= 0; i--)
2314 mlx5e_close_tir(priv, i);
2320 mlx5e_close_tirs(struct mlx5e_priv *priv)
2324 for (i = 0; i < MLX5E_NUM_TT; i++)
2325 mlx5e_close_tir(priv, i);
2329 * SW MTU does not include headers,
2330 * HW MTU includes all headers and checksums.
2333 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2335 struct mlx5e_priv *priv = ifp->if_softc;
2336 struct mlx5_core_dev *mdev = priv->mdev;
2340 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2342 err = mlx5_set_port_mtu(mdev, hw_mtu);
2344 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2345 __func__, sw_mtu, err);
2349 /* Update vport context MTU */
2350 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2352 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2356 ifp->if_mtu = sw_mtu;
2358 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2359 if (err || !hw_mtu) {
2360 /* fallback to port oper mtu */
2361 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2364 if_printf(ifp, "Query port MTU, after setting new "
2365 "MTU value, failed\n");
2367 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2369 if_printf(ifp, "Port MTU %d is smaller than "
2370 "ifp mtu %d\n", hw_mtu, sw_mtu);
2371 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2373 if_printf(ifp, "Port MTU %d is bigger than "
2374 "ifp mtu %d\n", hw_mtu, sw_mtu);
2376 priv->params_ethtool.hw_mtu = hw_mtu;
2382 mlx5e_open_locked(struct ifnet *ifp)
2384 struct mlx5e_priv *priv = ifp->if_softc;
2388 /* check if already opened */
2389 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2393 if (rss_getnumbuckets() > priv->params.num_channels) {
2394 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2395 "channels(%u) available\n", rss_getnumbuckets(),
2396 priv->params.num_channels);
2399 err = mlx5e_open_tises(priv);
2401 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2405 err = mlx5_vport_alloc_q_counter(priv->mdev,
2406 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2408 if_printf(priv->ifp,
2409 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2411 goto err_close_tises;
2413 /* store counter set ID */
2414 priv->counter_set_id = set_id;
2416 err = mlx5e_open_channels(priv);
2418 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2420 goto err_dalloc_q_counter;
2422 err = mlx5e_open_rqt(priv);
2424 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2426 goto err_close_channels;
2428 err = mlx5e_open_tirs(priv);
2430 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2432 goto err_close_rqls;
2434 err = mlx5e_open_flow_table(priv);
2436 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2438 goto err_close_tirs;
2440 err = mlx5e_add_all_vlan_rules(priv);
2442 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2444 goto err_close_flow_table;
2446 set_bit(MLX5E_STATE_OPENED, &priv->state);
2448 mlx5e_update_carrier(priv);
2449 mlx5e_set_rx_mode_core(priv);
2453 err_close_flow_table:
2454 mlx5e_close_flow_table(priv);
2457 mlx5e_close_tirs(priv);
2460 mlx5e_close_rqt(priv);
2463 mlx5e_close_channels(priv);
2465 err_dalloc_q_counter:
2466 mlx5_vport_dealloc_q_counter(priv->mdev,
2467 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2470 mlx5e_close_tises(priv);
2476 mlx5e_open(void *arg)
2478 struct mlx5e_priv *priv = arg;
2481 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2482 if_printf(priv->ifp,
2483 "%s: Setting port status to up failed\n",
2486 mlx5e_open_locked(priv->ifp);
2487 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2492 mlx5e_close_locked(struct ifnet *ifp)
2494 struct mlx5e_priv *priv = ifp->if_softc;
2496 /* check if already closed */
2497 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2500 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2502 mlx5e_set_rx_mode_core(priv);
2503 mlx5e_del_all_vlan_rules(priv);
2504 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2505 mlx5e_close_flow_table(priv);
2506 mlx5e_close_tirs(priv);
2507 mlx5e_close_rqt(priv);
2508 mlx5e_close_channels(priv);
2509 mlx5_vport_dealloc_q_counter(priv->mdev,
2510 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2511 mlx5e_close_tises(priv);
2516 #if (__FreeBSD_version >= 1100000)
2518 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2520 struct mlx5e_priv *priv = ifp->if_softc;
2523 /* PRIV_LOCK(priv); XXX not allowed */
2525 case IFCOUNTER_IPACKETS:
2526 retval = priv->stats.vport.rx_packets;
2528 case IFCOUNTER_IERRORS:
2529 retval = priv->stats.vport.rx_error_packets +
2530 priv->stats.pport.alignment_err +
2531 priv->stats.pport.check_seq_err +
2532 priv->stats.pport.crc_align_errors +
2533 priv->stats.pport.in_range_len_errors +
2534 priv->stats.pport.jabbers +
2535 priv->stats.pport.out_of_range_len +
2536 priv->stats.pport.oversize_pkts +
2537 priv->stats.pport.symbol_err +
2538 priv->stats.pport.too_long_errors +
2539 priv->stats.pport.undersize_pkts +
2540 priv->stats.pport.unsupported_op_rx;
2542 case IFCOUNTER_IQDROPS:
2543 retval = priv->stats.vport.rx_out_of_buffer +
2544 priv->stats.pport.drop_events;
2546 case IFCOUNTER_OPACKETS:
2547 retval = priv->stats.vport.tx_packets;
2549 case IFCOUNTER_OERRORS:
2550 retval = priv->stats.vport.tx_error_packets;
2552 case IFCOUNTER_IBYTES:
2553 retval = priv->stats.vport.rx_bytes;
2555 case IFCOUNTER_OBYTES:
2556 retval = priv->stats.vport.tx_bytes;
2558 case IFCOUNTER_IMCASTS:
2559 retval = priv->stats.vport.rx_multicast_packets;
2561 case IFCOUNTER_OMCASTS:
2562 retval = priv->stats.vport.tx_multicast_packets;
2564 case IFCOUNTER_OQDROPS:
2565 retval = priv->stats.vport.tx_queue_dropped;
2567 case IFCOUNTER_COLLISIONS:
2568 retval = priv->stats.pport.collisions;
2571 retval = if_get_counter_default(ifp, cnt);
2574 /* PRIV_UNLOCK(priv); XXX not allowed */
2580 mlx5e_set_rx_mode(struct ifnet *ifp)
2582 struct mlx5e_priv *priv = ifp->if_softc;
2584 queue_work(priv->wq, &priv->set_rx_mode_work);
2588 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2590 struct mlx5e_priv *priv;
2592 struct ifi2creq i2c;
2601 priv = ifp->if_softc;
2603 /* check if detaching */
2604 if (priv == NULL || priv->gone != 0)
2609 ifr = (struct ifreq *)data;
2612 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2614 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2615 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2618 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2620 mlx5e_close_locked(ifp);
2623 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2626 mlx5e_open_locked(ifp);
2629 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2630 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2635 if ((ifp->if_flags & IFF_UP) &&
2636 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2637 mlx5e_set_rx_mode(ifp);
2641 if (ifp->if_flags & IFF_UP) {
2642 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2643 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2644 mlx5e_open_locked(ifp);
2645 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2646 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2649 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2650 mlx5_set_port_status(priv->mdev,
2652 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2653 mlx5e_close_locked(ifp);
2654 mlx5e_update_carrier(priv);
2655 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2662 mlx5e_set_rx_mode(ifp);
2667 ifr = (struct ifreq *)data;
2668 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2671 ifr = (struct ifreq *)data;
2673 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2675 if (mask & IFCAP_TXCSUM) {
2676 ifp->if_capenable ^= IFCAP_TXCSUM;
2677 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2679 if (IFCAP_TSO4 & ifp->if_capenable &&
2680 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2681 ifp->if_capenable &= ~IFCAP_TSO4;
2682 ifp->if_hwassist &= ~CSUM_IP_TSO;
2684 "tso4 disabled due to -txcsum.\n");
2687 if (mask & IFCAP_TXCSUM_IPV6) {
2688 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2689 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2691 if (IFCAP_TSO6 & ifp->if_capenable &&
2692 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2693 ifp->if_capenable &= ~IFCAP_TSO6;
2694 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2696 "tso6 disabled due to -txcsum6.\n");
2699 if (mask & IFCAP_RXCSUM)
2700 ifp->if_capenable ^= IFCAP_RXCSUM;
2701 if (mask & IFCAP_RXCSUM_IPV6)
2702 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2703 if (mask & IFCAP_TSO4) {
2704 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2705 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2706 if_printf(ifp, "enable txcsum first.\n");
2710 ifp->if_capenable ^= IFCAP_TSO4;
2711 ifp->if_hwassist ^= CSUM_IP_TSO;
2713 if (mask & IFCAP_TSO6) {
2714 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2715 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2716 if_printf(ifp, "enable txcsum6 first.\n");
2720 ifp->if_capenable ^= IFCAP_TSO6;
2721 ifp->if_hwassist ^= CSUM_IP6_TSO;
2723 if (mask & IFCAP_VLAN_HWFILTER) {
2724 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2725 mlx5e_disable_vlan_filter(priv);
2727 mlx5e_enable_vlan_filter(priv);
2729 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2731 if (mask & IFCAP_VLAN_HWTAGGING)
2732 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2733 if (mask & IFCAP_WOL_MAGIC)
2734 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2736 VLAN_CAPABILITIES(ifp);
2737 /* turn off LRO means also turn of HW LRO - if it's on */
2738 if (mask & IFCAP_LRO) {
2739 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2740 bool need_restart = false;
2742 ifp->if_capenable ^= IFCAP_LRO;
2743 if (!(ifp->if_capenable & IFCAP_LRO)) {
2744 if (priv->params.hw_lro_en) {
2745 priv->params.hw_lro_en = false;
2746 need_restart = true;
2747 /* Not sure this is the correct way */
2748 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2751 if (was_opened && need_restart) {
2752 mlx5e_close_locked(ifp);
2753 mlx5e_open_locked(ifp);
2761 ifr = (struct ifreq *)data;
2764 * Copy from the user-space address ifr_data to the
2765 * kernel-space address i2c
2767 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2771 if (i2c.len > sizeof(i2c.data)) {
2777 /* Get module_num which is required for the query_eeprom */
2778 error = mlx5_query_module_num(priv->mdev, &module_num);
2780 if_printf(ifp, "Query module num failed, eeprom "
2781 "reading is not supported\n");
2785 /* Check if module is present before doing an access */
2786 module_status = mlx5_query_module_status(priv->mdev, module_num);
2787 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2788 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2793 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2794 * The internal conversion is as follows:
2796 if (i2c.dev_addr == 0xA0)
2797 read_addr = MLX5E_I2C_ADDR_LOW;
2798 else if (i2c.dev_addr == 0xA2)
2799 read_addr = MLX5E_I2C_ADDR_HIGH;
2801 if_printf(ifp, "Query eeprom failed, "
2802 "Invalid Address: %X\n", i2c.dev_addr);
2806 error = mlx5_query_eeprom(priv->mdev,
2807 read_addr, MLX5E_EEPROM_LOW_PAGE,
2808 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2809 (uint32_t *)i2c.data, &size_read);
2811 if_printf(ifp, "Query eeprom failed, eeprom "
2812 "reading is not supported\n");
2817 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2818 error = mlx5_query_eeprom(priv->mdev,
2819 read_addr, MLX5E_EEPROM_LOW_PAGE,
2820 (uint32_t)(i2c.offset + size_read),
2821 (uint32_t)(i2c.len - size_read), module_num,
2822 (uint32_t *)(i2c.data + size_read), &size_read);
2825 if_printf(ifp, "Query eeprom failed, eeprom "
2826 "reading is not supported\n");
2831 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2837 error = ether_ioctl(ifp, command, data);
2844 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2847 * TODO: uncoment once FW really sets all these bits if
2848 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2849 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2850 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2854 /* TODO: add more must-to-have features */
2856 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2863 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2864 struct mlx5e_priv *priv,
2865 int num_comp_vectors)
2868 * TODO: Consider link speed for setting "log_sq_size",
2869 * "log_rq_size" and "cq_moderation_xxx":
2871 priv->params.log_sq_size =
2872 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2873 priv->params.log_rq_size =
2874 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2875 priv->params.rx_cq_moderation_usec =
2876 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2877 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2878 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2879 priv->params.rx_cq_moderation_mode =
2880 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2881 priv->params.rx_cq_moderation_pkts =
2882 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2883 priv->params.tx_cq_moderation_usec =
2884 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2885 priv->params.tx_cq_moderation_pkts =
2886 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2887 priv->params.min_rx_wqes =
2888 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2889 priv->params.rx_hash_log_tbl_sz =
2890 (order_base_2(num_comp_vectors) >
2891 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2892 order_base_2(num_comp_vectors) :
2893 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2894 priv->params.num_tc = 1;
2895 priv->params.default_vlan_prio = 0;
2896 priv->counter_set_id = -1;
2899 * hw lro is currently defaulted to off. when it won't anymore we
2900 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2902 priv->params.hw_lro_en = false;
2903 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2905 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2908 priv->params.num_channels = num_comp_vectors;
2909 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2910 priv->queue_mapping_channel_mask =
2911 roundup_pow_of_two(num_comp_vectors) - 1;
2912 priv->num_tc = priv->params.num_tc;
2913 priv->default_vlan_prio = priv->params.default_vlan_prio;
2915 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2916 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2917 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2921 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2922 struct mlx5_core_mr *mkey)
2924 struct ifnet *ifp = priv->ifp;
2925 struct mlx5_core_dev *mdev = priv->mdev;
2926 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
2931 in = mlx5_vzalloc(inlen);
2933 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2937 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
2938 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
2939 MLX5_SET(mkc, mkc, lw, 1);
2940 MLX5_SET(mkc, mkc, lr, 1);
2942 MLX5_SET(mkc, mkc, pd, pdn);
2943 MLX5_SET(mkc, mkc, length64, 1);
2944 MLX5_SET(mkc, mkc, qpn, 0xffffff);
2946 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
2948 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2955 static const char *mlx5e_vport_stats_desc[] = {
2956 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2959 static const char *mlx5e_pport_stats_desc[] = {
2960 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2964 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2966 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2967 sx_init(&priv->state_lock, "mlx5state");
2968 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2969 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2973 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2975 mtx_destroy(&priv->async_events_mtx);
2976 sx_destroy(&priv->state_lock);
2980 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2983 * %d.%d%.d the string format.
2984 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2985 * We need at most 5 chars to store that.
2986 * It also has: two "." and NULL at the end, which means we need 18
2987 * (5*3 + 3) chars at most.
2990 struct mlx5e_priv *priv = arg1;
2993 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2994 fw_rev_sub(priv->mdev));
2995 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3000 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3004 for (i = 0; i < ch->num_tc; i++)
3005 mlx5e_drain_sq(&ch->sq[i]);
3009 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3012 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3013 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3014 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3015 sq->doorbell.d64 = 0;
3019 mlx5e_resume_sq(struct mlx5e_sq *sq)
3023 /* check if already enabled */
3024 if (sq->stopped == 0)
3027 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3028 MLX5_SQC_STATE_RST);
3031 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3037 /* reset doorbell prior to moving from RST to RDY */
3038 mlx5e_reset_sq_doorbell_record(sq);
3040 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3041 MLX5_SQC_STATE_RDY);
3044 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3047 mtx_lock(&sq->lock);
3048 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3050 mtx_unlock(&sq->lock);
3055 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3059 for (i = 0; i < ch->num_tc; i++)
3060 mlx5e_resume_sq(&ch->sq[i]);
3064 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3066 struct mlx5e_rq *rq = &ch->rq;
3071 callout_stop(&rq->watchdog);
3072 mtx_unlock(&rq->mtx);
3074 callout_drain(&rq->watchdog);
3076 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3079 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3082 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3084 rq->cq.mcq.comp(&rq->cq.mcq);
3088 * Transitioning into RST state will allow the FW to track less ERR state queues,
3089 * thus reducing the recv queue flushing time
3091 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3094 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3099 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3101 struct mlx5e_rq *rq = &ch->rq;
3105 mlx5_wq_ll_update_db_record(&rq->wq);
3106 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3109 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3114 rq->cq.mcq.comp(&rq->cq.mcq);
3118 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3122 if (priv->channel == NULL)
3125 for (i = 0; i < priv->params.num_channels; i++) {
3127 if (!priv->channel[i])
3131 mlx5e_disable_tx_dma(priv->channel[i]);
3133 mlx5e_enable_tx_dma(priv->channel[i]);
3138 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3142 if (priv->channel == NULL)
3145 for (i = 0; i < priv->params.num_channels; i++) {
3147 if (!priv->channel[i])
3151 mlx5e_disable_rx_dma(priv->channel[i]);
3153 mlx5e_enable_rx_dma(priv->channel[i]);
3158 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3160 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3161 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3162 sysctl_firmware, "A", "HCA firmware version");
3164 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3165 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3170 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3172 struct mlx5e_priv *priv = arg1;
3179 tx_pfc = priv->params.tx_priority_flow_control;
3181 /* get current value */
3182 value = (tx_pfc >> arg2) & 1;
3184 error = sysctl_handle_32(oidp, &value, 0, req);
3186 /* range check value */
3188 priv->params.tx_priority_flow_control |= (1 << arg2);
3190 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3192 /* check if update is required */
3193 if (error == 0 && priv->gone == 0 &&
3194 tx_pfc != priv->params.tx_priority_flow_control) {
3195 error = -mlx5e_set_port_pfc(priv);
3196 /* restore previous value */
3198 priv->params.tx_priority_flow_control= tx_pfc;
3206 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3208 struct mlx5e_priv *priv = arg1;
3215 rx_pfc = priv->params.rx_priority_flow_control;
3217 /* get current value */
3218 value = (rx_pfc >> arg2) & 1;
3220 error = sysctl_handle_32(oidp, &value, 0, req);
3222 /* range check value */
3224 priv->params.rx_priority_flow_control |= (1 << arg2);
3226 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3228 /* check if update is required */
3229 if (error == 0 && priv->gone == 0 &&
3230 rx_pfc != priv->params.rx_priority_flow_control) {
3231 error = -mlx5e_set_port_pfc(priv);
3232 /* restore previous value */
3234 priv->params.rx_priority_flow_control= rx_pfc;
3242 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3248 /* Only receiving pauseframes is enabled by default */
3249 priv->params.tx_pauseframe_control = 0;
3250 priv->params.rx_pauseframe_control = 1;
3252 /* disable ports flow control, PFC, by default */
3253 priv->params.tx_priority_flow_control = 0;
3254 priv->params.rx_priority_flow_control = 0;
3256 #if (__FreeBSD_version < 1100000)
3257 /* compute path for sysctl */
3258 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3259 device_get_unit(priv->mdev->pdev->dev.bsddev));
3261 /* try to fetch tunable, if any */
3262 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3264 /* compute path for sysctl */
3265 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3266 device_get_unit(priv->mdev->pdev->dev.bsddev));
3268 /* try to fetch tunable, if any */
3269 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3271 for (x = 0; x != 8; x++) {
3273 /* compute path for sysctl */
3274 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3275 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3277 /* try to fetch tunable, if any */
3278 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3279 priv->params.tx_priority_flow_control |= 1 << x;
3281 /* compute path for sysctl */
3282 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3283 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3285 /* try to fetch tunable, if any */
3286 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3287 priv->params.rx_priority_flow_control |= 1 << x;
3291 /* register pauseframe SYSCTLs */
3292 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3293 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3294 &priv->params.tx_pauseframe_control, 0,
3295 "Set to enable TX pause frames. Clear to disable.");
3297 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3298 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3299 &priv->params.rx_pauseframe_control, 0,
3300 "Set to enable RX pause frames. Clear to disable.");
3302 /* register priority_flow control, PFC, SYSCTLs */
3303 for (x = 0; x != 8; x++) {
3304 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3306 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3307 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3308 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3309 "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3311 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3313 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3314 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3315 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3316 "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3322 priv->params.tx_pauseframe_control =
3323 priv->params.tx_pauseframe_control ? 1 : 0;
3324 priv->params.rx_pauseframe_control =
3325 priv->params.rx_pauseframe_control ? 1 : 0;
3327 /* update firmware */
3328 error = mlx5e_set_port_pause_and_pfc(priv);
3329 if (error == -EINVAL) {
3330 if_printf(priv->ifp,
3331 "Global pauseframes must be disabled before enabling PFC.\n");
3332 priv->params.rx_priority_flow_control = 0;
3333 priv->params.tx_priority_flow_control = 0;
3335 /* update firmware */
3336 (void) mlx5e_set_port_pause_and_pfc(priv);
3342 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3345 struct mlx5e_priv *priv;
3346 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3347 struct sysctl_oid_list *child;
3348 int ncv = mdev->priv.eq_table.num_comp_vectors;
3354 if (mlx5e_check_required_hca_cap(mdev)) {
3355 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3358 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3359 mlx5e_priv_mtx_init(priv);
3361 ifp = priv->ifp = if_alloc(IFT_ETHER);
3363 mlx5_core_err(mdev, "if_alloc() failed\n");
3366 ifp->if_softc = priv;
3367 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3368 ifp->if_mtu = ETHERMTU;
3369 ifp->if_init = mlx5e_open;
3370 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3371 ifp->if_ioctl = mlx5e_ioctl;
3372 ifp->if_transmit = mlx5e_xmit;
3373 ifp->if_qflush = if_qflush;
3374 #if (__FreeBSD_version >= 1100000)
3375 ifp->if_get_counter = mlx5e_get_counter;
3377 ifp->if_snd.ifq_maxlen = ifqmaxlen;
3379 * Set driver features
3381 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3382 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3383 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3384 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3385 ifp->if_capabilities |= IFCAP_LRO;
3386 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3387 ifp->if_capabilities |= IFCAP_HWSTATS;
3389 /* set TSO limits so that we don't have to drop TX packets */
3390 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3391 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3392 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3394 ifp->if_capenable = ifp->if_capabilities;
3395 ifp->if_hwassist = 0;
3396 if (ifp->if_capenable & IFCAP_TSO)
3397 ifp->if_hwassist |= CSUM_TSO;
3398 if (ifp->if_capenable & IFCAP_TXCSUM)
3399 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3400 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3401 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3403 /* ifnet sysctl tree */
3404 sysctl_ctx_init(&priv->sysctl_ctx);
3405 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3406 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3407 if (priv->sysctl_ifnet == NULL) {
3408 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3409 goto err_free_sysctl;
3411 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3412 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3413 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3414 if (priv->sysctl_ifnet == NULL) {
3415 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3416 goto err_free_sysctl;
3419 /* HW sysctl tree */
3420 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3421 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3422 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3423 if (priv->sysctl_hw == NULL) {
3424 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3425 goto err_free_sysctl;
3427 mlx5e_build_ifp_priv(mdev, priv, ncv);
3429 snprintf(unit, sizeof(unit), "mce%u_wq",
3430 device_get_unit(mdev->pdev->dev.bsddev));
3431 priv->wq = alloc_workqueue(unit, 0, 1);
3432 if (priv->wq == NULL) {
3433 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3434 goto err_free_sysctl;
3437 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3439 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3443 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3445 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3447 goto err_unmap_free_uar;
3449 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3451 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3453 goto err_dealloc_pd;
3455 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3457 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3459 goto err_dealloc_transport_domain;
3461 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3463 /* check if we should generate a random MAC address */
3464 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3465 is_zero_ether_addr(dev_addr)) {
3466 random_ether_addr(dev_addr);
3467 if_printf(ifp, "Assigned random MAC address\n");
3470 /* set default MTU */
3471 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3474 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3476 /* Set default media status */
3477 priv->media_status_last = IFM_AVALID;
3478 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3479 IFM_ETH_RXPAUSE | IFM_FDX;
3481 /* setup default pauseframes configuration */
3482 mlx5e_setup_pauseframes(priv);
3484 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3487 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3491 /* Setup supported medias */
3492 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3493 mlx5e_media_change, mlx5e_media_status);
3495 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3496 if (mlx5e_mode_table[i].baudrate == 0)
3498 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3499 ifmedia_add(&priv->media,
3500 mlx5e_mode_table[i].subtype |
3501 IFM_ETHER, 0, NULL);
3502 ifmedia_add(&priv->media,
3503 mlx5e_mode_table[i].subtype |
3504 IFM_ETHER | IFM_FDX |
3505 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3509 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3510 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3511 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3513 /* Set autoselect by default */
3514 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3515 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3516 ether_ifattach(ifp, dev_addr);
3518 /* Register for VLAN events */
3519 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3520 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3521 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3522 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3524 /* Link is down by default */
3525 if_link_state_change(ifp, LINK_STATE_DOWN);
3527 mlx5e_enable_async_events(priv);
3529 mlx5e_add_hw_stats(priv);
3531 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3532 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3533 priv->stats.vport.arg);
3535 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3536 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3537 priv->stats.pport.arg);
3539 mlx5e_create_ethtool(priv);
3541 mtx_lock(&priv->async_events_mtx);
3542 mlx5e_update_stats(priv);
3543 mtx_unlock(&priv->async_events_mtx);
3547 err_dealloc_transport_domain:
3548 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3551 mlx5_core_dealloc_pd(mdev, priv->pdn);
3554 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3557 destroy_workqueue(priv->wq);
3560 sysctl_ctx_free(&priv->sysctl_ctx);
3565 mlx5e_priv_mtx_destroy(priv);
3566 free(priv, M_MLX5EN);
3571 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3573 struct mlx5e_priv *priv = vpriv;
3574 struct ifnet *ifp = priv->ifp;
3576 /* don't allow more IOCTLs */
3580 * Clear the device description to avoid use after free,
3581 * because the bsddev is not destroyed when this module is
3584 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3586 /* XXX wait a bit to allow IOCTL handlers to complete */
3589 /* stop watchdog timer */
3590 callout_drain(&priv->watchdog);
3592 if (priv->vlan_attach != NULL)
3593 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3594 if (priv->vlan_detach != NULL)
3595 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3597 /* make sure device gets closed */
3599 mlx5e_close_locked(ifp);
3602 /* unregister device */
3603 ifmedia_removeall(&priv->media);
3604 ether_ifdetach(ifp);
3607 /* destroy all remaining sysctl nodes */
3608 if (priv->sysctl_debug)
3609 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3610 sysctl_ctx_free(&priv->stats.vport.ctx);
3611 sysctl_ctx_free(&priv->stats.pport.ctx);
3612 sysctl_ctx_free(&priv->sysctl_ctx);
3614 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3615 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3616 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3617 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3618 mlx5e_disable_async_events(priv);
3619 destroy_workqueue(priv->wq);
3620 mlx5e_priv_mtx_destroy(priv);
3621 free(priv, M_MLX5EN);
3625 mlx5e_get_ifp(void *vpriv)
3627 struct mlx5e_priv *priv = vpriv;
3632 static struct mlx5_interface mlx5e_interface = {
3633 .add = mlx5e_create_ifp,
3634 .remove = mlx5e_destroy_ifp,
3635 .event = mlx5e_async_event,
3636 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3637 .get_dev = mlx5e_get_ifp,
3643 mlx5_register_interface(&mlx5e_interface);
3649 mlx5_unregister_interface(&mlx5e_interface);
3652 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3653 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3655 #if (__FreeBSD_version >= 1100000)
3656 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3658 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3659 MODULE_VERSION(mlx5en, 1);