2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_kern_tls.h"
32 #include <sys/eventhandler.h>
33 #include <sys/sockio.h>
34 #include <machine/atomic.h>
36 #include <net/debugnet.h>
38 #ifndef ETH_DRIVER_VERSION
39 #define ETH_DRIVER_VERSION "3.5.2"
41 #define DRIVER_RELDATE "September 2019"
43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
44 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
48 struct mlx5e_channel_param {
49 struct mlx5e_rq_param rq;
50 struct mlx5e_sq_param sq;
51 struct mlx5e_cq_param rx_cq;
52 struct mlx5e_cq_param tx_cq;
60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
62 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
63 .subtype = IFM_1000_CX_SGMII,
64 .baudrate = IF_Mbps(1000ULL),
66 [MLX5E_1000BASE_KX][MLX5E_KX] = {
67 .subtype = IFM_1000_KX,
68 .baudrate = IF_Mbps(1000ULL),
70 [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
71 .subtype = IFM_10G_CX4,
72 .baudrate = IF_Gbps(10ULL),
74 [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
75 .subtype = IFM_10G_KX4,
76 .baudrate = IF_Gbps(10ULL),
78 [MLX5E_10GBASE_KR][MLX5E_KR] = {
79 .subtype = IFM_10G_KR,
80 .baudrate = IF_Gbps(10ULL),
82 [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
83 .subtype = IFM_20G_KR2,
84 .baudrate = IF_Gbps(20ULL),
86 [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
87 .subtype = IFM_40G_CR4,
88 .baudrate = IF_Gbps(40ULL),
90 [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
91 .subtype = IFM_40G_KR4,
92 .baudrate = IF_Gbps(40ULL),
94 [MLX5E_56GBASE_R4][MLX5E_R] = {
95 .subtype = IFM_56G_R4,
96 .baudrate = IF_Gbps(56ULL),
98 [MLX5E_10GBASE_CR][MLX5E_CR1] = {
99 .subtype = IFM_10G_CR1,
100 .baudrate = IF_Gbps(10ULL),
102 [MLX5E_10GBASE_SR][MLX5E_SR] = {
103 .subtype = IFM_10G_SR,
104 .baudrate = IF_Gbps(10ULL),
106 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
107 .subtype = IFM_10G_ER,
108 .baudrate = IF_Gbps(10ULL),
110 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
111 .subtype = IFM_10G_LR,
112 .baudrate = IF_Gbps(10ULL),
114 [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
115 .subtype = IFM_40G_SR4,
116 .baudrate = IF_Gbps(40ULL),
118 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
119 .subtype = IFM_40G_LR4,
120 .baudrate = IF_Gbps(40ULL),
122 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
123 .subtype = IFM_40G_ER4,
124 .baudrate = IF_Gbps(40ULL),
126 [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
127 .subtype = IFM_100G_CR4,
128 .baudrate = IF_Gbps(100ULL),
130 [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
131 .subtype = IFM_100G_SR4,
132 .baudrate = IF_Gbps(100ULL),
134 [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
135 .subtype = IFM_100G_KR4,
136 .baudrate = IF_Gbps(100ULL),
138 [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
139 .subtype = IFM_100G_LR4,
140 .baudrate = IF_Gbps(100ULL),
142 [MLX5E_100BASE_TX][MLX5E_TX] = {
143 .subtype = IFM_100_TX,
144 .baudrate = IF_Mbps(100ULL),
146 [MLX5E_1000BASE_T][MLX5E_T] = {
147 .subtype = IFM_1000_T,
148 .baudrate = IF_Mbps(1000ULL),
150 [MLX5E_10GBASE_T][MLX5E_T] = {
151 .subtype = IFM_10G_T,
152 .baudrate = IF_Gbps(10ULL),
154 [MLX5E_25GBASE_CR][MLX5E_CR] = {
155 .subtype = IFM_25G_CR,
156 .baudrate = IF_Gbps(25ULL),
158 [MLX5E_25GBASE_KR][MLX5E_KR] = {
159 .subtype = IFM_25G_KR,
160 .baudrate = IF_Gbps(25ULL),
162 [MLX5E_25GBASE_SR][MLX5E_SR] = {
163 .subtype = IFM_25G_SR,
164 .baudrate = IF_Gbps(25ULL),
166 [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
167 .subtype = IFM_50G_CR2,
168 .baudrate = IF_Gbps(50ULL),
170 [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
171 .subtype = IFM_50G_KR2,
172 .baudrate = IF_Gbps(50ULL),
174 [MLX5E_50GBASE_KR4][MLX5E_KR4] = {
175 .subtype = IFM_50G_KR4,
176 .baudrate = IF_Gbps(50ULL),
180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
181 [MLX5E_SGMII_100M][MLX5E_SGMII] = {
182 .subtype = IFM_100_SGMII,
183 .baudrate = IF_Mbps(100),
185 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
186 .subtype = IFM_1000_KX,
187 .baudrate = IF_Mbps(1000),
189 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
190 .subtype = IFM_1000_CX_SGMII,
191 .baudrate = IF_Mbps(1000),
193 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
194 .subtype = IFM_1000_CX,
195 .baudrate = IF_Mbps(1000),
197 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
198 .subtype = IFM_1000_LX,
199 .baudrate = IF_Mbps(1000),
201 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
202 .subtype = IFM_1000_SX,
203 .baudrate = IF_Mbps(1000),
205 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
206 .subtype = IFM_1000_T,
207 .baudrate = IF_Mbps(1000),
209 [MLX5E_5GBASE_R][MLX5E_T] = {
210 .subtype = IFM_5000_T,
211 .baudrate = IF_Mbps(5000),
213 [MLX5E_5GBASE_R][MLX5E_KR] = {
214 .subtype = IFM_5000_KR,
215 .baudrate = IF_Mbps(5000),
217 [MLX5E_5GBASE_R][MLX5E_KR1] = {
218 .subtype = IFM_5000_KR1,
219 .baudrate = IF_Mbps(5000),
221 [MLX5E_5GBASE_R][MLX5E_KR_S] = {
222 .subtype = IFM_5000_KR_S,
223 .baudrate = IF_Mbps(5000),
225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
226 .subtype = IFM_10G_ER,
227 .baudrate = IF_Gbps(10ULL),
229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
230 .subtype = IFM_10G_KR,
231 .baudrate = IF_Gbps(10ULL),
233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
234 .subtype = IFM_10G_LR,
235 .baudrate = IF_Gbps(10ULL),
237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
238 .subtype = IFM_10G_SR,
239 .baudrate = IF_Gbps(10ULL),
241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
242 .subtype = IFM_10G_T,
243 .baudrate = IF_Gbps(10ULL),
245 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
246 .subtype = IFM_10G_AOC,
247 .baudrate = IF_Gbps(10ULL),
249 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
250 .subtype = IFM_10G_CR1,
251 .baudrate = IF_Gbps(10ULL),
253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
254 .subtype = IFM_40G_CR4,
255 .baudrate = IF_Gbps(40ULL),
257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
258 .subtype = IFM_40G_KR4,
259 .baudrate = IF_Gbps(40ULL),
261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
262 .subtype = IFM_40G_LR4,
263 .baudrate = IF_Gbps(40ULL),
265 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
266 .subtype = IFM_40G_SR4,
267 .baudrate = IF_Gbps(40ULL),
269 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
270 .subtype = IFM_40G_ER4,
271 .baudrate = IF_Gbps(40ULL),
274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
275 .subtype = IFM_25G_CR,
276 .baudrate = IF_Gbps(25ULL),
278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
279 .subtype = IFM_25G_KR,
280 .baudrate = IF_Gbps(25ULL),
282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
283 .subtype = IFM_25G_SR,
284 .baudrate = IF_Gbps(25ULL),
286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
287 .subtype = IFM_25G_ACC,
288 .baudrate = IF_Gbps(25ULL),
290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
291 .subtype = IFM_25G_AOC,
292 .baudrate = IF_Gbps(25ULL),
294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
295 .subtype = IFM_25G_CR1,
296 .baudrate = IF_Gbps(25ULL),
298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
299 .subtype = IFM_25G_CR_S,
300 .baudrate = IF_Gbps(25ULL),
302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
303 .subtype = IFM_5000_KR1,
304 .baudrate = IF_Gbps(25ULL),
306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
307 .subtype = IFM_25G_KR_S,
308 .baudrate = IF_Gbps(25ULL),
310 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
311 .subtype = IFM_25G_LR,
312 .baudrate = IF_Gbps(25ULL),
314 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
315 .subtype = IFM_25G_T,
316 .baudrate = IF_Gbps(25ULL),
318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
319 .subtype = IFM_50G_CR2,
320 .baudrate = IF_Gbps(50ULL),
322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
323 .subtype = IFM_50G_KR2,
324 .baudrate = IF_Gbps(50ULL),
326 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = {
327 .subtype = IFM_50G_KR4,
328 .baudrate = IF_Gbps(50ULL),
330 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
331 .subtype = IFM_50G_SR2,
332 .baudrate = IF_Gbps(50ULL),
334 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
335 .subtype = IFM_50G_LR2,
336 .baudrate = IF_Gbps(50ULL),
338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
339 .subtype = IFM_50G_LR,
340 .baudrate = IF_Gbps(50ULL),
342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
343 .subtype = IFM_50G_SR,
344 .baudrate = IF_Gbps(50ULL),
346 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
347 .subtype = IFM_50G_CP,
348 .baudrate = IF_Gbps(50ULL),
350 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
351 .subtype = IFM_50G_FR,
352 .baudrate = IF_Gbps(50ULL),
354 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
355 .subtype = IFM_50G_KR_PAM4,
356 .baudrate = IF_Gbps(50ULL),
358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
359 .subtype = IFM_100G_CR4,
360 .baudrate = IF_Gbps(100ULL),
362 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
363 .subtype = IFM_100G_KR4,
364 .baudrate = IF_Gbps(100ULL),
366 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
367 .subtype = IFM_100G_LR4,
368 .baudrate = IF_Gbps(100ULL),
370 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
371 .subtype = IFM_100G_SR4,
372 .baudrate = IF_Gbps(100ULL),
374 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
375 .subtype = IFM_100G_SR2,
376 .baudrate = IF_Gbps(100ULL),
378 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
379 .subtype = IFM_100G_CP2,
380 .baudrate = IF_Gbps(100ULL),
382 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
383 .subtype = IFM_100G_KR2_PAM4,
384 .baudrate = IF_Gbps(100ULL),
386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
387 .subtype = IFM_200G_DR4,
388 .baudrate = IF_Gbps(200ULL),
390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
391 .subtype = IFM_200G_LR4,
392 .baudrate = IF_Gbps(200ULL),
394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
395 .subtype = IFM_200G_SR4,
396 .baudrate = IF_Gbps(200ULL),
398 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
399 .subtype = IFM_200G_FR4,
400 .baudrate = IF_Gbps(200ULL),
402 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
403 .subtype = IFM_200G_CR4_PAM4,
404 .baudrate = IF_Gbps(200ULL),
406 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
407 .subtype = IFM_200G_KR4_PAM4,
408 .baudrate = IF_Gbps(200ULL),
412 DEBUGNET_DEFINE(mlx5_en);
414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
417 mlx5e_update_carrier(struct mlx5e_priv *priv)
419 struct mlx5_core_dev *mdev = priv->mdev;
420 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
427 struct media media_entry = {};
429 port_state = mlx5_query_vport_state(mdev,
430 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
432 if (port_state == VPORT_STATE_UP) {
433 priv->media_status_last |= IFM_ACTIVE;
435 priv->media_status_last &= ~IFM_ACTIVE;
436 priv->media_active_last = IFM_ETHER;
437 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
441 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
444 priv->media_active_last = IFM_ETHER;
445 priv->ifp->if_baudrate = 1;
446 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
451 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
452 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
455 i = ilog2(eth_proto_oper);
457 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
458 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
459 mlx5e_mode_table[i][j];
460 if (media_entry.baudrate != 0)
464 if (media_entry.subtype == 0) {
465 mlx5_en_err(priv->ifp,
466 "Could not find operational media subtype\n");
470 switch (media_entry.subtype) {
472 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
474 mlx5_en_err(priv->ifp,
475 "query port pddr failed: %d\n", error);
477 if (error != 0 || is_er_type == 0)
478 media_entry.subtype = IFM_10G_LR;
481 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
483 mlx5_en_err(priv->ifp,
484 "query port pddr failed: %d\n", error);
486 if (error == 0 && is_er_type != 0)
487 media_entry.subtype = IFM_40G_ER4;
490 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
491 priv->ifp->if_baudrate = media_entry.baudrate;
493 if_link_state_change(priv->ifp, LINK_STATE_UP);
497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
499 struct mlx5e_priv *priv = dev->if_softc;
501 ifmr->ifm_status = priv->media_status_last;
502 ifmr->ifm_active = priv->media_active_last |
503 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
504 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
509 mlx5e_find_link_mode(u32 subtype, bool ext)
515 struct media media_entry = {};
519 subtype = IFM_10G_ER;
522 subtype = IFM_40G_LR4;
526 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
527 MLX5E_LINK_SPEEDS_NUMBER;
529 for (i = 0; i != speeds_num; i++) {
530 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
531 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
532 mlx5e_mode_table[i][j];
533 if (media_entry.baudrate == 0)
535 if (media_entry.subtype == subtype) {
536 link_mode |= MLX5E_PROT_MASK(i);
545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
547 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
548 priv->params.rx_pauseframe_control,
549 priv->params.tx_pauseframe_control,
550 priv->params.rx_priority_flow_control,
551 priv->params.tx_priority_flow_control));
555 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
559 if (priv->gone != 0) {
561 } else if (priv->params.rx_pauseframe_control ||
562 priv->params.tx_pauseframe_control) {
563 mlx5_en_err(priv->ifp,
564 "Global pauseframes must be disabled before enabling PFC.\n");
567 error = mlx5e_set_port_pause_and_pfc(priv);
573 mlx5e_media_change(struct ifnet *dev)
575 struct mlx5e_priv *priv = dev->if_softc;
576 struct mlx5_core_dev *mdev = priv->mdev;
579 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
585 locked = PRIV_LOCKED(priv);
589 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
594 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
597 mlx5_en_err(dev, "Query port media capability failed\n");
601 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
602 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
604 /* query supported capabilities */
605 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
606 eth_proto_capability);
608 /* check for autoselect */
609 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
610 link_mode = eth_proto_cap;
611 if (link_mode == 0) {
612 mlx5_en_err(dev, "Port media capability is zero\n");
617 link_mode = link_mode & eth_proto_cap;
618 if (link_mode == 0) {
619 mlx5_en_err(dev, "Not supported link mode requested\n");
624 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
625 /* check if PFC is enabled */
626 if (priv->params.rx_priority_flow_control ||
627 priv->params.tx_priority_flow_control) {
628 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
633 /* update pauseframe control bits */
634 priv->params.rx_pauseframe_control =
635 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
636 priv->params.tx_pauseframe_control =
637 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
639 /* check if device is opened */
640 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
642 /* reconfigure the hardware */
643 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
644 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
645 error = -mlx5e_set_port_pause_and_pfc(priv);
647 mlx5_set_port_status(mdev, MLX5_PORT_UP);
656 mlx5e_update_carrier_work(struct work_struct *work)
658 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
659 update_carrier_work);
662 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
663 mlx5e_update_carrier(priv);
667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
668 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
671 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
676 struct mlx5_core_dev *mdev = priv->mdev;
677 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
678 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
683 /* allocate firmware request structures */
684 in = mlx5_vzalloc(sz);
685 out = mlx5_vzalloc(sz);
686 if (in == NULL || out == NULL)
689 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
690 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
694 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
695 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
697 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
698 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
702 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
704 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
705 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
709 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
712 /* free firmware request structures */
718 * This function reads the physical port counters from the firmware
719 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
720 * macros. The output is converted from big-endian 64-bit values into
721 * host endian ones and stored in the "priv->stats.pport" structure.
724 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
726 struct mlx5_core_dev *mdev = priv->mdev;
727 struct mlx5e_pport_stats *s = &priv->stats.pport;
728 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
732 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
737 /* allocate firmware request structures */
738 in = mlx5_vzalloc(sz);
739 out = mlx5_vzalloc(sz);
740 if (in == NULL || out == NULL)
744 * Get pointer to the 64-bit counter set which is located at a
745 * fixed offset in the output firmware request structure:
747 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
749 MLX5_SET(ppcnt_reg, in, local_port, 1);
751 /* read IEEE802_3 counter group using predefined counter layout */
752 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
754 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
755 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
756 s->arg[y] = be64toh(ptr[x]);
758 /* read RFC2819 counter group using predefined counter layout */
759 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
760 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
761 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
762 s->arg[y] = be64toh(ptr[x]);
764 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
765 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
766 s_debug->arg[y] = be64toh(ptr[x]);
768 /* read RFC2863 counter group using predefined counter layout */
769 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
771 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
772 s_debug->arg[y] = be64toh(ptr[x]);
774 /* read physical layer stats counter group using predefined counter layout */
775 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
776 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
777 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
778 s_debug->arg[y] = be64toh(ptr[x]);
780 /* read Extended Ethernet counter group using predefined counter layout */
781 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
782 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
783 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
784 s_debug->arg[y] = be64toh(ptr[x]);
786 /* read Extended Statistical Group */
787 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
788 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
789 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
790 /* read Extended Statistical counter group using predefined counter layout */
791 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
792 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
794 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
795 s_debug->arg[y] = be64toh(ptr[x]);
798 /* read PCIE counters */
799 mlx5e_update_pcie_counters(priv);
801 /* read per-priority counters */
802 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
804 /* iterate all the priorities */
805 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
806 MLX5_SET(ppcnt_reg, in, prio_tc, z);
807 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
809 /* read per priority stats counter group using predefined counter layout */
810 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
811 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
812 s->arg[y] = be64toh(ptr[x]);
816 /* free firmware request structures */
822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
824 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
825 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
827 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
830 MLX5_SET(query_vnic_env_in, in, opcode,
831 MLX5_CMD_OP_QUERY_VNIC_ENV);
832 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
833 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
835 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
838 priv->stats.vport.rx_steer_missed_packets =
839 MLX5_GET64(query_vnic_env_out, out,
840 vport_env.nic_receive_steering_discard);
844 * This function is called regularly to collect all statistics
845 * counters from the firmware. The values can be viewed through the
846 * sysctl interface. Execution is serialized using the priv's global
847 * configuration lock.
850 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
852 struct mlx5_core_dev *mdev = priv->mdev;
853 struct mlx5e_vport_stats *s = &priv->stats.vport;
854 struct mlx5e_sq_stats *sq_stats;
855 struct buf_ring *sq_br;
856 #if (__FreeBSD_version < 1100000)
857 struct ifnet *ifp = priv->ifp;
860 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
862 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
865 u64 tx_queue_dropped = 0;
866 u64 tx_defragged = 0;
867 u64 tx_offload_none = 0;
870 u64 sw_lro_queued = 0;
871 u64 sw_lro_flushed = 0;
872 u64 rx_csum_none = 0;
876 u32 rx_out_of_buffer = 0;
881 out = mlx5_vzalloc(outlen);
885 /* Collect firts the SW counters and then HW for consistency */
886 for (i = 0; i < priv->params.num_channels; i++) {
887 struct mlx5e_channel *pch = priv->channel + i;
888 struct mlx5e_rq *rq = &pch->rq;
889 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
891 /* collect stats from LRO */
892 rq_stats->sw_lro_queued = rq->lro.lro_queued;
893 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
894 sw_lro_queued += rq_stats->sw_lro_queued;
895 sw_lro_flushed += rq_stats->sw_lro_flushed;
896 lro_packets += rq_stats->lro_packets;
897 lro_bytes += rq_stats->lro_bytes;
898 rx_csum_none += rq_stats->csum_none;
899 rx_wqe_err += rq_stats->wqe_err;
900 rx_packets += rq_stats->packets;
901 rx_bytes += rq_stats->bytes;
903 for (j = 0; j < priv->num_tc; j++) {
904 sq_stats = &pch->sq[j].stats;
905 sq_br = pch->sq[j].br;
907 tso_packets += sq_stats->tso_packets;
908 tso_bytes += sq_stats->tso_bytes;
909 tx_queue_dropped += sq_stats->dropped;
911 tx_queue_dropped += sq_br->br_drops;
912 tx_defragged += sq_stats->defragged;
913 tx_offload_none += sq_stats->csum_offload_none;
917 /* update counters */
918 s->tso_packets = tso_packets;
919 s->tso_bytes = tso_bytes;
920 s->tx_queue_dropped = tx_queue_dropped;
921 s->tx_defragged = tx_defragged;
922 s->lro_packets = lro_packets;
923 s->lro_bytes = lro_bytes;
924 s->sw_lro_queued = sw_lro_queued;
925 s->sw_lro_flushed = sw_lro_flushed;
926 s->rx_csum_none = rx_csum_none;
927 s->rx_wqe_err = rx_wqe_err;
928 s->rx_packets = rx_packets;
929 s->rx_bytes = rx_bytes;
931 mlx5e_grp_vnic_env_update_stats(priv);
934 memset(in, 0, sizeof(in));
936 MLX5_SET(query_vport_counter_in, in, opcode,
937 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
938 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
939 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
941 memset(out, 0, outlen);
943 /* get number of out-of-buffer drops first */
944 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
945 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
946 &rx_out_of_buffer) == 0) {
947 s->rx_out_of_buffer = rx_out_of_buffer;
950 /* get port statistics */
951 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
952 #define MLX5_GET_CTR(out, x) \
953 MLX5_GET64(query_vport_counter_out, out, x)
955 s->rx_error_packets =
956 MLX5_GET_CTR(out, received_errors.packets);
958 MLX5_GET_CTR(out, received_errors.octets);
959 s->tx_error_packets =
960 MLX5_GET_CTR(out, transmit_errors.packets);
962 MLX5_GET_CTR(out, transmit_errors.octets);
964 s->rx_unicast_packets =
965 MLX5_GET_CTR(out, received_eth_unicast.packets);
966 s->rx_unicast_bytes =
967 MLX5_GET_CTR(out, received_eth_unicast.octets);
968 s->tx_unicast_packets =
969 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
970 s->tx_unicast_bytes =
971 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
973 s->rx_multicast_packets =
974 MLX5_GET_CTR(out, received_eth_multicast.packets);
975 s->rx_multicast_bytes =
976 MLX5_GET_CTR(out, received_eth_multicast.octets);
977 s->tx_multicast_packets =
978 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
979 s->tx_multicast_bytes =
980 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
982 s->rx_broadcast_packets =
983 MLX5_GET_CTR(out, received_eth_broadcast.packets);
984 s->rx_broadcast_bytes =
985 MLX5_GET_CTR(out, received_eth_broadcast.octets);
986 s->tx_broadcast_packets =
987 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
988 s->tx_broadcast_bytes =
989 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
991 s->tx_packets = s->tx_unicast_packets +
992 s->tx_multicast_packets + s->tx_broadcast_packets;
993 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
994 s->tx_broadcast_bytes;
996 /* Update calculated offload counters */
997 s->tx_csum_offload = s->tx_packets - tx_offload_none;
998 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
1001 /* Get physical port counters */
1002 mlx5e_update_pport_counters(priv);
1004 s->tx_jumbo_packets =
1005 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1006 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1007 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1008 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1010 #if (__FreeBSD_version < 1100000)
1011 /* no get_counters interface in fbsd 10 */
1012 ifp->if_ipackets = s->rx_packets;
1013 ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1014 priv->stats.pport.out_of_range_len +
1015 priv->stats.pport.too_long_errors +
1016 priv->stats.pport.check_seq_err +
1017 priv->stats.pport.alignment_err;
1018 ifp->if_iqdrops = s->rx_out_of_buffer;
1019 ifp->if_opackets = s->tx_packets;
1020 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1021 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1022 ifp->if_ibytes = s->rx_bytes;
1023 ifp->if_obytes = s->tx_bytes;
1024 ifp->if_collisions =
1025 priv->stats.pport.collisions;
1031 /* Update diagnostics, if any */
1032 if (priv->params_ethtool.diag_pci_enable ||
1033 priv->params_ethtool.diag_general_enable) {
1034 error = mlx5_core_get_diagnostics_full(mdev,
1035 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1036 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1038 mlx5_en_err(priv->ifp,
1039 "Failed reading diagnostics: %d\n", error);
1042 /* Update FEC, if any */
1043 error = mlx5e_fec_update(priv);
1044 if (error != 0 && error != EOPNOTSUPP) {
1045 mlx5_en_err(priv->ifp,
1046 "Updating FEC failed: %d\n", error);
1051 mlx5e_update_stats_work(struct work_struct *work)
1053 struct mlx5e_priv *priv;
1055 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1057 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1058 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1059 mlx5e_update_stats_locked(priv);
1064 mlx5e_update_stats(void *arg)
1066 struct mlx5e_priv *priv = arg;
1068 queue_work(priv->wq, &priv->update_stats_work);
1070 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1074 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1075 enum mlx5_dev_event event)
1078 case MLX5_DEV_EVENT_PORT_UP:
1079 case MLX5_DEV_EVENT_PORT_DOWN:
1080 queue_work(priv->wq, &priv->update_carrier_work);
1089 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1090 enum mlx5_dev_event event, unsigned long param)
1092 struct mlx5e_priv *priv = vpriv;
1094 mtx_lock(&priv->async_events_mtx);
1095 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1096 mlx5e_async_event_sub(priv, event);
1097 mtx_unlock(&priv->async_events_mtx);
1101 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1103 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1107 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1109 mtx_lock(&priv->async_events_mtx);
1110 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1111 mtx_unlock(&priv->async_events_mtx);
1114 static void mlx5e_calibration_callout(void *arg);
1115 static int mlx5e_calibration_duration = 20;
1116 static int mlx5e_fast_calibration = 1;
1117 static int mlx5e_normal_calibration = 30;
1119 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1120 "MLX5 timestamp calibration parameteres");
1122 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1123 &mlx5e_calibration_duration, 0,
1124 "Duration of initial calibration");
1125 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1126 &mlx5e_fast_calibration, 0,
1127 "Recalibration interval during initial calibration");
1128 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1129 &mlx5e_normal_calibration, 0,
1130 "Recalibration interval during normal operations");
1133 * Ignites the calibration process.
1136 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1139 if (priv->clbr_done == 0)
1140 mlx5e_calibration_callout(priv);
1142 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1143 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1144 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1149 mlx5e_timespec2usec(const struct timespec *ts)
1152 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1156 mlx5e_hw_clock(struct mlx5e_priv *priv)
1158 struct mlx5_init_seg *iseg;
1159 uint32_t hw_h, hw_h1, hw_l;
1161 iseg = priv->mdev->iseg;
1163 hw_h = ioread32be(&iseg->internal_timer_h);
1164 hw_l = ioread32be(&iseg->internal_timer_l);
1165 hw_h1 = ioread32be(&iseg->internal_timer_h);
1166 } while (hw_h1 != hw_h);
1167 return (((uint64_t)hw_h << 32) | hw_l);
1171 * The calibration callout, it runs either in the context of the
1172 * thread which enables calibration, or in callout. It takes the
1173 * snapshot of system and adapter clocks, then advances the pointers to
1174 * the calibration point to allow rx path to read the consistent data
1178 mlx5e_calibration_callout(void *arg)
1180 struct mlx5e_priv *priv;
1181 struct mlx5e_clbr_point *next, *curr;
1186 curr = &priv->clbr_points[priv->clbr_curr];
1187 clbr_curr_next = priv->clbr_curr + 1;
1188 if (clbr_curr_next >= nitems(priv->clbr_points))
1190 next = &priv->clbr_points[clbr_curr_next];
1192 next->base_prev = curr->base_curr;
1193 next->clbr_hw_prev = curr->clbr_hw_curr;
1195 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1196 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1198 if (priv->clbr_done != 0) {
1199 mlx5_en_err(priv->ifp,
1200 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1201 next->clbr_hw_curr, curr->clbr_hw_prev);
1202 priv->clbr_done = 0;
1204 atomic_store_rel_int(&curr->clbr_gen, 0);
1209 next->base_curr = mlx5e_timespec2usec(&ts);
1212 atomic_thread_fence_rel();
1213 priv->clbr_curr = clbr_curr_next;
1214 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1216 if (priv->clbr_done < mlx5e_calibration_duration)
1218 mlx5e_reset_calibration_callout(priv);
1221 static const char *mlx5e_rq_stats_desc[] = {
1222 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1226 mlx5e_create_rq(struct mlx5e_channel *c,
1227 struct mlx5e_rq_param *param,
1228 struct mlx5e_rq *rq)
1230 struct mlx5e_priv *priv = c->priv;
1231 struct mlx5_core_dev *mdev = priv->mdev;
1233 void *rqc = param->rqc;
1234 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1240 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1244 /* Create DMA descriptor TAG */
1245 if ((err = -bus_dma_tag_create(
1246 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1247 1, /* any alignment */
1248 0, /* no boundary */
1249 BUS_SPACE_MAXADDR, /* lowaddr */
1250 BUS_SPACE_MAXADDR, /* highaddr */
1251 NULL, NULL, /* filter, filterarg */
1252 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1253 nsegs, /* nsegments */
1254 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1256 NULL, NULL, /* lockfunc, lockfuncarg */
1260 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1263 goto err_free_dma_tag;
1265 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1267 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1269 goto err_rq_wq_destroy;
1271 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1273 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1275 goto err_rq_wq_destroy;
1277 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1278 for (i = 0; i != wq_sz; i++) {
1279 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1282 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1285 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1286 goto err_rq_mbuf_free;
1289 /* set value for constant fields */
1290 for (j = 0; j < rq->nsegs; j++)
1291 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1294 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1295 if (priv->params.rx_cq_moderation_mode < 2) {
1296 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1298 void *cqc = container_of(param,
1299 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1301 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1302 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1303 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1305 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1306 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1309 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1314 rq->ifp = priv->ifp;
1318 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1319 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1320 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1325 free(rq->mbuf, M_MLX5EN);
1326 tcp_lro_free(&rq->lro);
1328 mlx5_wq_destroy(&rq->wq_ctrl);
1330 bus_dma_tag_destroy(rq->dma_tag);
1336 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1341 /* destroy all sysctl nodes */
1342 sysctl_ctx_free(&rq->stats.ctx);
1344 /* free leftover LRO packets, if any */
1345 tcp_lro_free(&rq->lro);
1347 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1348 for (i = 0; i != wq_sz; i++) {
1349 if (rq->mbuf[i].mbuf != NULL) {
1350 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1351 m_freem(rq->mbuf[i].mbuf);
1353 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1355 free(rq->mbuf, M_MLX5EN);
1356 mlx5_wq_destroy(&rq->wq_ctrl);
1357 bus_dma_tag_destroy(rq->dma_tag);
1361 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1363 struct mlx5e_channel *c = rq->channel;
1364 struct mlx5e_priv *priv = c->priv;
1365 struct mlx5_core_dev *mdev = priv->mdev;
1373 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1374 sizeof(u64) * rq->wq_ctrl.buf.npages;
1375 in = mlx5_vzalloc(inlen);
1379 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1380 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1382 memcpy(rqc, param->rqc, sizeof(param->rqc));
1384 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1385 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1386 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1387 if (priv->counter_set_id >= 0)
1388 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1389 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1391 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1393 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1394 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1396 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1404 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1406 struct mlx5e_channel *c = rq->channel;
1407 struct mlx5e_priv *priv = c->priv;
1408 struct mlx5_core_dev *mdev = priv->mdev;
1415 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1416 in = mlx5_vzalloc(inlen);
1420 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1422 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1423 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1424 MLX5_SET(rqc, rqc, state, next_state);
1426 err = mlx5_core_modify_rq(mdev, in, inlen);
1434 mlx5e_disable_rq(struct mlx5e_rq *rq)
1436 struct mlx5e_channel *c = rq->channel;
1437 struct mlx5e_priv *priv = c->priv;
1438 struct mlx5_core_dev *mdev = priv->mdev;
1440 mlx5_core_destroy_rq(mdev, rq->rqn);
1444 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1446 struct mlx5e_channel *c = rq->channel;
1447 struct mlx5e_priv *priv = c->priv;
1448 struct mlx5_wq_ll *wq = &rq->wq;
1451 for (i = 0; i < 1000; i++) {
1452 if (wq->cur_sz >= priv->params.min_rx_wqes)
1457 return (-ETIMEDOUT);
1461 mlx5e_open_rq(struct mlx5e_channel *c,
1462 struct mlx5e_rq_param *param,
1463 struct mlx5e_rq *rq)
1467 err = mlx5e_create_rq(c, param, rq);
1471 err = mlx5e_enable_rq(rq, param);
1473 goto err_destroy_rq;
1475 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1477 goto err_disable_rq;
1484 mlx5e_disable_rq(rq);
1486 mlx5e_destroy_rq(rq);
1492 mlx5e_close_rq(struct mlx5e_rq *rq)
1496 callout_stop(&rq->watchdog);
1497 mtx_unlock(&rq->mtx);
1499 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1503 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1506 mlx5e_disable_rq(rq);
1507 mlx5e_close_cq(&rq->cq);
1508 cancel_work_sync(&rq->dim.work);
1509 mlx5e_destroy_rq(rq);
1513 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1515 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1518 for (x = 0; x != wq_sz; x++) {
1519 if (unlikely(sq->mbuf[x].p_refcount != NULL)) {
1520 atomic_add_int(sq->mbuf[x].p_refcount, -1);
1521 sq->mbuf[x].p_refcount = NULL;
1523 if (sq->mbuf[x].mbuf != NULL) {
1524 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1525 m_freem(sq->mbuf[x].mbuf);
1527 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1529 free(sq->mbuf, M_MLX5EN);
1533 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1535 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1539 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1541 /* Create DMA descriptor MAPs */
1542 for (x = 0; x != wq_sz; x++) {
1543 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1546 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1547 free(sq->mbuf, M_MLX5EN);
1554 static const char *mlx5e_sq_stats_desc[] = {
1555 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1559 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1561 sq->max_inline = sq->priv->params.tx_max_inline;
1562 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1565 * Check if trust state is DSCP or if inline mode is NONE which
1566 * indicates CX-5 or newer hardware.
1568 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1569 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1570 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1571 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1573 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1575 sq->min_insert_caps = 0;
1580 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1584 for (i = 0; i != priv->num_tc; i++) {
1585 mtx_lock(&c->sq[i].lock);
1586 mlx5e_update_sq_inline(&c->sq[i]);
1587 mtx_unlock(&c->sq[i].lock);
1592 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1596 /* check if channels are closed */
1597 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1600 for (i = 0; i < priv->params.num_channels; i++)
1601 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1605 mlx5e_create_sq(struct mlx5e_channel *c,
1607 struct mlx5e_sq_param *param,
1608 struct mlx5e_sq *sq)
1610 struct mlx5e_priv *priv = c->priv;
1611 struct mlx5_core_dev *mdev = priv->mdev;
1613 void *sqc = param->sqc;
1614 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1617 /* Create DMA descriptor TAG */
1618 if ((err = -bus_dma_tag_create(
1619 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1620 1, /* any alignment */
1621 0, /* no boundary */
1622 BUS_SPACE_MAXADDR, /* lowaddr */
1623 BUS_SPACE_MAXADDR, /* highaddr */
1624 NULL, NULL, /* filter, filterarg */
1625 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1626 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1627 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1629 NULL, NULL, /* lockfunc, lockfuncarg */
1633 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1635 goto err_free_dma_tag;
1637 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1640 goto err_unmap_free_uar;
1642 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1643 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1645 err = mlx5e_alloc_sq_db(sq);
1647 goto err_sq_wq_destroy;
1649 sq->mkey_be = cpu_to_be32(priv->mr.key);
1650 sq->ifp = priv->ifp;
1654 mlx5e_update_sq_inline(sq);
1656 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1657 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1658 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1664 mlx5_wq_destroy(&sq->wq_ctrl);
1667 mlx5_unmap_free_uar(mdev, &sq->uar);
1670 bus_dma_tag_destroy(sq->dma_tag);
1676 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1678 /* destroy all sysctl nodes */
1679 sysctl_ctx_free(&sq->stats.ctx);
1681 mlx5e_free_sq_db(sq);
1682 mlx5_wq_destroy(&sq->wq_ctrl);
1683 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1684 bus_dma_tag_destroy(sq->dma_tag);
1688 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1697 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1698 sizeof(u64) * sq->wq_ctrl.buf.npages;
1699 in = mlx5_vzalloc(inlen);
1703 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1704 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1706 memcpy(sqc, param->sqc, sizeof(param->sqc));
1708 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1709 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1710 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1711 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1712 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1714 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1715 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1716 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1718 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1720 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1721 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1723 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1731 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1738 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1739 in = mlx5_vzalloc(inlen);
1743 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1745 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1746 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1747 MLX5_SET(sqc, sqc, state, next_state);
1749 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1757 mlx5e_disable_sq(struct mlx5e_sq *sq)
1760 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1764 mlx5e_open_sq(struct mlx5e_channel *c,
1766 struct mlx5e_sq_param *param,
1767 struct mlx5e_sq *sq)
1771 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1773 /* ensure the TX completion event factor is not zero */
1774 if (sq->cev_factor == 0)
1777 err = mlx5e_create_sq(c, tc, param, sq);
1781 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1783 goto err_destroy_sq;
1785 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1787 goto err_disable_sq;
1789 WRITE_ONCE(sq->running, 1);
1794 mlx5e_disable_sq(sq);
1796 mlx5e_destroy_sq(sq);
1802 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1804 /* fill up remainder with NOPs */
1805 while (sq->cev_counter != 0) {
1806 while (!mlx5e_sq_has_room_for(sq, 1)) {
1807 if (can_sleep != 0) {
1808 mtx_unlock(&sq->lock);
1810 mtx_lock(&sq->lock);
1815 /* send a single NOP */
1816 mlx5e_send_nop(sq, 1);
1817 atomic_thread_fence_rel();
1820 /* Check if we need to write the doorbell */
1821 if (likely(sq->doorbell.d64 != 0)) {
1822 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1823 sq->doorbell.d64 = 0;
1828 mlx5e_sq_cev_timeout(void *arg)
1830 struct mlx5e_sq *sq = arg;
1832 mtx_assert(&sq->lock, MA_OWNED);
1834 /* check next state */
1835 switch (sq->cev_next_state) {
1836 case MLX5E_CEV_STATE_SEND_NOPS:
1837 /* fill TX ring with NOPs, if any */
1838 mlx5e_sq_send_nops_locked(sq, 0);
1840 /* check if completed */
1841 if (sq->cev_counter == 0) {
1842 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1847 /* send NOPs on next timeout */
1848 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1853 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1857 mlx5e_drain_sq(struct mlx5e_sq *sq)
1860 struct mlx5_core_dev *mdev= sq->priv->mdev;
1863 * Check if already stopped.
1865 * NOTE: Serialization of this function is managed by the
1866 * caller ensuring the priv's state lock is locked or in case
1867 * of rate limit support, a single thread manages drain and
1868 * resume of SQs. The "running" variable can therefore safely
1869 * be read without any locks.
1871 if (READ_ONCE(sq->running) == 0)
1874 /* don't put more packets into the SQ */
1875 WRITE_ONCE(sq->running, 0);
1877 /* serialize access to DMA rings */
1878 mtx_lock(&sq->lock);
1880 /* teardown event factor timer, if any */
1881 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1882 callout_stop(&sq->cev_callout);
1884 /* send dummy NOPs in order to flush the transmit ring */
1885 mlx5e_sq_send_nops_locked(sq, 1);
1886 mtx_unlock(&sq->lock);
1888 /* wait till SQ is empty or link is down */
1889 mtx_lock(&sq->lock);
1890 while (sq->cc != sq->pc &&
1891 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1892 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1893 mtx_unlock(&sq->lock);
1895 sq->cq.mcq.comp(&sq->cq.mcq);
1896 mtx_lock(&sq->lock);
1898 mtx_unlock(&sq->lock);
1900 /* error out remaining requests */
1901 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1903 mlx5_en_err(sq->ifp,
1904 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1907 /* wait till SQ is empty */
1908 mtx_lock(&sq->lock);
1909 while (sq->cc != sq->pc &&
1910 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1911 mtx_unlock(&sq->lock);
1913 sq->cq.mcq.comp(&sq->cq.mcq);
1914 mtx_lock(&sq->lock);
1916 mtx_unlock(&sq->lock);
1920 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1924 mlx5e_disable_sq(sq);
1925 mlx5e_destroy_sq(sq);
1929 mlx5e_create_cq(struct mlx5e_priv *priv,
1930 struct mlx5e_cq_param *param,
1931 struct mlx5e_cq *cq,
1932 mlx5e_cq_comp_t *comp,
1935 struct mlx5_core_dev *mdev = priv->mdev;
1936 struct mlx5_core_cq *mcq = &cq->mcq;
1942 param->wq.buf_numa_node = 0;
1943 param->wq.db_numa_node = 0;
1945 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1949 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1955 mcq->set_ci_db = cq->wq_ctrl.db.db;
1956 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1957 *mcq->set_ci_db = 0;
1959 mcq->vector = eq_ix;
1961 mcq->event = mlx5e_cq_error_event;
1963 mcq->uar = &priv->cq_uar;
1965 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1966 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1977 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1979 mlx5_wq_destroy(&cq->wq_ctrl);
1983 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1985 struct mlx5_core_cq *mcq = &cq->mcq;
1993 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1994 sizeof(u64) * cq->wq_ctrl.buf.npages;
1995 in = mlx5_vzalloc(inlen);
1999 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2001 memcpy(cqc, param->cqc, sizeof(param->cqc));
2003 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2004 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2006 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2008 MLX5_SET(cqc, cqc, c_eqn, eqn);
2009 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2010 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2012 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2014 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2021 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2027 mlx5e_disable_cq(struct mlx5e_cq *cq)
2030 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2034 mlx5e_open_cq(struct mlx5e_priv *priv,
2035 struct mlx5e_cq_param *param,
2036 struct mlx5e_cq *cq,
2037 mlx5e_cq_comp_t *comp,
2042 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2046 err = mlx5e_enable_cq(cq, param, eq_ix);
2048 goto err_destroy_cq;
2053 mlx5e_destroy_cq(cq);
2059 mlx5e_close_cq(struct mlx5e_cq *cq)
2061 mlx5e_disable_cq(cq);
2062 mlx5e_destroy_cq(cq);
2066 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2067 struct mlx5e_channel_param *cparam)
2072 for (tc = 0; tc < c->priv->num_tc; tc++) {
2073 /* open completion queue */
2074 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2075 &mlx5e_tx_cq_comp, c->ix);
2077 goto err_close_tx_cqs;
2082 for (tc--; tc >= 0; tc--)
2083 mlx5e_close_cq(&c->sq[tc].cq);
2089 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2093 for (tc = 0; tc < c->priv->num_tc; tc++)
2094 mlx5e_close_cq(&c->sq[tc].cq);
2098 mlx5e_open_sqs(struct mlx5e_channel *c,
2099 struct mlx5e_channel_param *cparam)
2104 for (tc = 0; tc < c->priv->num_tc; tc++) {
2105 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2113 for (tc--; tc >= 0; tc--)
2114 mlx5e_close_sq_wait(&c->sq[tc]);
2120 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2124 for (tc = 0; tc < c->priv->num_tc; tc++)
2125 mlx5e_close_sq_wait(&c->sq[tc]);
2129 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2133 /* setup priv and channel number */
2137 /* setup send tag */
2138 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2139 m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2141 init_completion(&c->completion);
2143 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2145 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2147 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2148 struct mlx5e_sq *sq = c->sq + tc;
2150 mtx_init(&sq->lock, "mlx5tx",
2151 MTX_NETWORK_LOCK " TX", MTX_DEF);
2152 mtx_init(&sq->comp_lock, "mlx5comp",
2153 MTX_NETWORK_LOCK " TX", MTX_DEF);
2155 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2160 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2163 m_snd_tag_rele(&c->tag.m_snd_tag);
2164 wait_for_completion(&c->completion);
2168 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2172 for (x = 0; x != channels; x++)
2173 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2177 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2181 callout_drain(&c->rq.watchdog);
2183 mtx_destroy(&c->rq.mtx);
2185 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2186 callout_drain(&c->sq[tc].cev_callout);
2187 mtx_destroy(&c->sq[tc].lock);
2188 mtx_destroy(&c->sq[tc].comp_lock);
2193 mlx5e_open_channel(struct mlx5e_priv *priv,
2194 struct mlx5e_channel_param *cparam,
2195 struct mlx5e_channel *c)
2197 struct epoch_tracker et;
2200 /* zero non-persistant data */
2201 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2202 for (i = 0; i != priv->num_tc; i++)
2203 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2205 /* open transmit completion queue */
2206 err = mlx5e_open_tx_cqs(c, cparam);
2210 /* open receive completion queue */
2211 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2212 &mlx5e_rx_cq_comp, c->ix);
2214 goto err_close_tx_cqs;
2216 err = mlx5e_open_sqs(c, cparam);
2218 goto err_close_rx_cq;
2220 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2224 /* poll receive queue initially */
2225 NET_EPOCH_ENTER(et);
2226 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2232 mlx5e_close_sqs_wait(c);
2235 mlx5e_close_cq(&c->rq.cq);
2238 mlx5e_close_tx_cqs(c);
2245 mlx5e_close_channel(struct mlx5e_channel *c)
2247 mlx5e_close_rq(&c->rq);
2251 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2253 mlx5e_close_rq_wait(&c->rq);
2254 mlx5e_close_sqs_wait(c);
2255 mlx5e_close_tx_cqs(c);
2259 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2263 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2264 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2265 if (r > MJUM16BYTES)
2270 else if (r > MJUMPAGESIZE)
2272 else if (r > MCLBYTES)
2278 * n + 1 must be a power of two, because stride size must be.
2279 * Stride size is 16 * (n + 1), as the first segment is
2282 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2285 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2294 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2295 struct mlx5e_rq_param *param)
2297 void *rqc = param->rqc;
2298 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2301 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2302 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2303 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2304 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2305 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2306 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2307 MLX5_SET(wq, wq, pd, priv->pdn);
2309 param->wq.buf_numa_node = 0;
2310 param->wq.db_numa_node = 0;
2311 param->wq.linear = 1;
2315 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2316 struct mlx5e_sq_param *param)
2318 void *sqc = param->sqc;
2319 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2321 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2322 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2323 MLX5_SET(wq, wq, pd, priv->pdn);
2325 param->wq.buf_numa_node = 0;
2326 param->wq.db_numa_node = 0;
2327 param->wq.linear = 1;
2331 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2332 struct mlx5e_cq_param *param)
2334 void *cqc = param->cqc;
2336 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2340 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2343 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2345 /* apply LRO restrictions */
2346 if (priv->params.hw_lro_en &&
2347 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2348 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2353 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2354 struct mlx5e_cq_param *param)
2356 struct net_dim_cq_moder curr;
2357 void *cqc = param->cqc;
2360 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2361 * format is more beneficial for FreeBSD use case.
2363 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2364 * in mlx5e_decompress_cqe.
2366 if (priv->params.cqe_zipping_en) {
2367 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2368 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2371 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2373 switch (priv->params.rx_cq_moderation_mode) {
2375 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2376 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2377 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2380 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2381 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2382 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2383 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2385 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2388 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2389 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2390 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2391 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2394 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2395 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2396 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2397 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2398 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2400 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2406 mlx5e_dim_build_cq_param(priv, param);
2408 mlx5e_build_common_cq_param(priv, param);
2412 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2413 struct mlx5e_cq_param *param)
2415 void *cqc = param->cqc;
2417 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2418 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2419 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2421 switch (priv->params.tx_cq_moderation_mode) {
2423 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2426 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2427 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2429 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2433 mlx5e_build_common_cq_param(priv, param);
2437 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2438 struct mlx5e_channel_param *cparam)
2440 memset(cparam, 0, sizeof(*cparam));
2442 mlx5e_build_rq_param(priv, &cparam->rq);
2443 mlx5e_build_sq_param(priv, &cparam->sq);
2444 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2445 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2449 mlx5e_open_channels(struct mlx5e_priv *priv)
2451 struct mlx5e_channel_param *cparam;
2456 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2458 mlx5e_build_channel_param(priv, cparam);
2459 for (i = 0; i < priv->params.num_channels; i++) {
2460 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2462 goto err_close_channels;
2465 for (j = 0; j < priv->params.num_channels; j++) {
2466 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2468 goto err_close_channels;
2470 free(cparam, M_MLX5EN);
2475 mlx5e_close_channel(&priv->channel[i]);
2476 mlx5e_close_channel_wait(&priv->channel[i]);
2478 free(cparam, M_MLX5EN);
2483 mlx5e_close_channels(struct mlx5e_priv *priv)
2487 for (i = 0; i < priv->params.num_channels; i++)
2488 mlx5e_close_channel(&priv->channel[i]);
2489 for (i = 0; i < priv->params.num_channels; i++)
2490 mlx5e_close_channel_wait(&priv->channel[i]);
2494 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2497 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2500 switch (priv->params.tx_cq_moderation_mode) {
2503 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2506 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2510 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2511 priv->params.tx_cq_moderation_usec,
2512 priv->params.tx_cq_moderation_pkts,
2516 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2517 priv->params.tx_cq_moderation_usec,
2518 priv->params.tx_cq_moderation_pkts));
2522 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2525 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2530 switch (priv->params.rx_cq_moderation_mode) {
2533 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2534 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2537 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2538 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2542 /* tear down dynamic interrupt moderation */
2544 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2545 mtx_unlock(&rq->mtx);
2547 /* wait for dynamic interrupt moderation work task, if any */
2548 cancel_work_sync(&rq->dim.work);
2550 if (priv->params.rx_cq_moderation_mode >= 2) {
2551 struct net_dim_cq_moder curr;
2553 mlx5e_get_default_profile(priv, dim_mode, &curr);
2555 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2556 curr.usec, curr.pkts, cq_mode);
2558 /* set dynamic interrupt moderation mode and zero defaults */
2560 rq->dim.mode = dim_mode;
2562 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2563 mtx_unlock(&rq->mtx);
2565 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2566 priv->params.rx_cq_moderation_usec,
2567 priv->params.rx_cq_moderation_pkts,
2573 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2574 priv->params.rx_cq_moderation_usec,
2575 priv->params.rx_cq_moderation_pkts));
2579 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2584 err = mlx5e_refresh_rq_params(priv, &c->rq);
2588 for (i = 0; i != priv->num_tc; i++) {
2589 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2598 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2602 /* check if channels are closed */
2603 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2606 for (i = 0; i < priv->params.num_channels; i++) {
2609 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2617 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2619 struct mlx5_core_dev *mdev = priv->mdev;
2620 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2621 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2623 memset(in, 0, sizeof(in));
2625 MLX5_SET(tisc, tisc, prio, tc);
2626 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2628 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2632 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2634 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2638 mlx5e_open_tises(struct mlx5e_priv *priv)
2640 int num_tc = priv->num_tc;
2644 for (tc = 0; tc < num_tc; tc++) {
2645 err = mlx5e_open_tis(priv, tc);
2647 goto err_close_tises;
2653 for (tc--; tc >= 0; tc--)
2654 mlx5e_close_tis(priv, tc);
2660 mlx5e_close_tises(struct mlx5e_priv *priv)
2662 int num_tc = priv->num_tc;
2665 for (tc = 0; tc < num_tc; tc++)
2666 mlx5e_close_tis(priv, tc);
2670 mlx5e_open_rqt(struct mlx5e_priv *priv)
2672 struct mlx5_core_dev *mdev = priv->mdev;
2674 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2681 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2683 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2684 in = mlx5_vzalloc(inlen);
2687 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2689 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2690 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2692 for (i = 0; i < sz; i++) {
2695 ix = rss_get_indirection_to_bucket(ix);
2697 /* ensure we don't overflow */
2698 ix %= priv->params.num_channels;
2700 /* apply receive side scaling stride, if any */
2701 ix -= ix % (int)priv->params.channels_rsss;
2703 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2706 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2708 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2710 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2718 mlx5e_close_rqt(struct mlx5e_priv *priv)
2720 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2721 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2723 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2724 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2726 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2730 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2732 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2735 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2737 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2739 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2740 MLX5_HASH_FIELD_SEL_DST_IP)
2742 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2743 MLX5_HASH_FIELD_SEL_DST_IP |\
2744 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2745 MLX5_HASH_FIELD_SEL_L4_DPORT)
2747 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2748 MLX5_HASH_FIELD_SEL_DST_IP |\
2749 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2751 if (priv->params.hw_lro_en) {
2752 MLX5_SET(tirc, tirc, lro_enable_mask,
2753 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2754 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2755 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2756 (priv->params.lro_wqe_sz -
2757 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2758 /* TODO: add the option to choose timer value dynamically */
2759 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2760 MLX5_CAP_ETH(priv->mdev,
2761 lro_timer_supported_periods[2]));
2764 /* setup parameters for hashing TIR type, if any */
2767 MLX5_SET(tirc, tirc, disp_type,
2768 MLX5_TIRC_DISP_TYPE_DIRECT);
2769 MLX5_SET(tirc, tirc, inline_rqn,
2770 priv->channel[0].rq.rqn);
2773 MLX5_SET(tirc, tirc, disp_type,
2774 MLX5_TIRC_DISP_TYPE_INDIRECT);
2775 MLX5_SET(tirc, tirc, indirect_table,
2777 MLX5_SET(tirc, tirc, rx_hash_fn,
2778 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2779 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2782 * The FreeBSD RSS implementation does currently not
2783 * support symmetric Toeplitz hashes:
2785 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2786 rss_getkey((uint8_t *)hkey);
2788 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2789 hkey[0] = cpu_to_be32(0xD181C62C);
2790 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2791 hkey[2] = cpu_to_be32(0x1983A2FC);
2792 hkey[3] = cpu_to_be32(0x943E1ADB);
2793 hkey[4] = cpu_to_be32(0xD9389E6B);
2794 hkey[5] = cpu_to_be32(0xD1039C2C);
2795 hkey[6] = cpu_to_be32(0xA74499AD);
2796 hkey[7] = cpu_to_be32(0x593D56D9);
2797 hkey[8] = cpu_to_be32(0xF3253C06);
2798 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2804 case MLX5E_TT_IPV4_TCP:
2805 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2806 MLX5_L3_PROT_TYPE_IPV4);
2807 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2808 MLX5_L4_PROT_TYPE_TCP);
2810 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2811 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2815 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2819 case MLX5E_TT_IPV6_TCP:
2820 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2821 MLX5_L3_PROT_TYPE_IPV6);
2822 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2823 MLX5_L4_PROT_TYPE_TCP);
2825 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2826 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2830 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2834 case MLX5E_TT_IPV4_UDP:
2835 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2836 MLX5_L3_PROT_TYPE_IPV4);
2837 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2838 MLX5_L4_PROT_TYPE_UDP);
2840 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2841 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2845 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2849 case MLX5E_TT_IPV6_UDP:
2850 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2851 MLX5_L3_PROT_TYPE_IPV6);
2852 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2853 MLX5_L4_PROT_TYPE_UDP);
2855 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2856 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2860 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2864 case MLX5E_TT_IPV4_IPSEC_AH:
2865 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2866 MLX5_L3_PROT_TYPE_IPV4);
2867 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2868 MLX5_HASH_IP_IPSEC_SPI);
2871 case MLX5E_TT_IPV6_IPSEC_AH:
2872 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2873 MLX5_L3_PROT_TYPE_IPV6);
2874 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2875 MLX5_HASH_IP_IPSEC_SPI);
2878 case MLX5E_TT_IPV4_IPSEC_ESP:
2879 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2880 MLX5_L3_PROT_TYPE_IPV4);
2881 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2882 MLX5_HASH_IP_IPSEC_SPI);
2885 case MLX5E_TT_IPV6_IPSEC_ESP:
2886 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2887 MLX5_L3_PROT_TYPE_IPV6);
2888 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2889 MLX5_HASH_IP_IPSEC_SPI);
2893 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2894 MLX5_L3_PROT_TYPE_IPV4);
2895 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2900 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2901 MLX5_L3_PROT_TYPE_IPV6);
2902 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2912 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2914 struct mlx5_core_dev *mdev = priv->mdev;
2920 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2921 in = mlx5_vzalloc(inlen);
2924 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2926 mlx5e_build_tir_ctx(priv, tirc, tt);
2928 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2936 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2938 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2942 mlx5e_open_tirs(struct mlx5e_priv *priv)
2947 for (i = 0; i < MLX5E_NUM_TT; i++) {
2948 err = mlx5e_open_tir(priv, i);
2950 goto err_close_tirs;
2956 for (i--; i >= 0; i--)
2957 mlx5e_close_tir(priv, i);
2963 mlx5e_close_tirs(struct mlx5e_priv *priv)
2967 for (i = 0; i < MLX5E_NUM_TT; i++)
2968 mlx5e_close_tir(priv, i);
2972 * SW MTU does not include headers,
2973 * HW MTU includes all headers and checksums.
2976 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2978 struct mlx5e_priv *priv = ifp->if_softc;
2979 struct mlx5_core_dev *mdev = priv->mdev;
2983 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2985 err = mlx5_set_port_mtu(mdev, hw_mtu);
2987 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2992 /* Update vport context MTU */
2993 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2996 "Failed updating vport context with MTU size, err=%d\n",
3000 ifp->if_mtu = sw_mtu;
3002 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3003 if (err || !hw_mtu) {
3004 /* fallback to port oper mtu */
3005 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3009 "Query port MTU, after setting new MTU value, failed\n");
3011 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3014 "Port MTU %d is smaller than ifp mtu %d\n",
3016 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3019 "Port MTU %d is bigger than ifp mtu %d\n",
3022 priv->params_ethtool.hw_mtu = hw_mtu;
3025 while (hw_mtu & (hw_mtu - 1))
3026 hw_mtu &= (hw_mtu - 1);
3027 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3033 mlx5e_open_locked(struct ifnet *ifp)
3035 struct mlx5e_priv *priv = ifp->if_softc;
3039 /* check if already opened */
3040 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3044 if (rss_getnumbuckets() > priv->params.num_channels) {
3046 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3047 rss_getnumbuckets(), priv->params.num_channels);
3050 err = mlx5e_open_tises(priv);
3052 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3055 err = mlx5_vport_alloc_q_counter(priv->mdev,
3056 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3058 mlx5_en_err(priv->ifp,
3059 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3060 goto err_close_tises;
3062 /* store counter set ID */
3063 priv->counter_set_id = set_id;
3065 err = mlx5e_open_channels(priv);
3068 "mlx5e_open_channels failed, %d\n", err);
3069 goto err_dalloc_q_counter;
3071 err = mlx5e_open_rqt(priv);
3073 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3074 goto err_close_channels;
3076 err = mlx5e_open_tirs(priv);
3078 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3079 goto err_close_rqls;
3081 err = mlx5e_open_flow_table(priv);
3084 "mlx5e_open_flow_table failed, %d\n", err);
3085 goto err_close_tirs;
3087 err = mlx5e_add_all_vlan_rules(priv);
3090 "mlx5e_add_all_vlan_rules failed, %d\n", err);
3091 goto err_close_flow_table;
3093 set_bit(MLX5E_STATE_OPENED, &priv->state);
3095 mlx5e_update_carrier(priv);
3096 mlx5e_set_rx_mode_core(priv);
3100 err_close_flow_table:
3101 mlx5e_close_flow_table(priv);
3104 mlx5e_close_tirs(priv);
3107 mlx5e_close_rqt(priv);
3110 mlx5e_close_channels(priv);
3112 err_dalloc_q_counter:
3113 mlx5_vport_dealloc_q_counter(priv->mdev,
3114 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3117 mlx5e_close_tises(priv);
3123 mlx5e_open(void *arg)
3125 struct mlx5e_priv *priv = arg;
3128 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3129 mlx5_en_err(priv->ifp,
3130 "Setting port status to up failed\n");
3132 mlx5e_open_locked(priv->ifp);
3133 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3138 mlx5e_close_locked(struct ifnet *ifp)
3140 struct mlx5e_priv *priv = ifp->if_softc;
3142 /* check if already closed */
3143 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3146 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3148 mlx5e_set_rx_mode_core(priv);
3149 mlx5e_del_all_vlan_rules(priv);
3150 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3151 mlx5e_close_flow_table(priv);
3152 mlx5e_close_tirs(priv);
3153 mlx5e_close_rqt(priv);
3154 mlx5e_close_channels(priv);
3155 mlx5_vport_dealloc_q_counter(priv->mdev,
3156 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3157 mlx5e_close_tises(priv);
3162 #if (__FreeBSD_version >= 1100000)
3164 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3166 struct mlx5e_priv *priv = ifp->if_softc;
3169 /* PRIV_LOCK(priv); XXX not allowed */
3171 case IFCOUNTER_IPACKETS:
3172 retval = priv->stats.vport.rx_packets;
3174 case IFCOUNTER_IERRORS:
3175 retval = priv->stats.pport.in_range_len_errors +
3176 priv->stats.pport.out_of_range_len +
3177 priv->stats.pport.too_long_errors +
3178 priv->stats.pport.check_seq_err +
3179 priv->stats.pport.alignment_err;
3181 case IFCOUNTER_IQDROPS:
3182 retval = priv->stats.vport.rx_out_of_buffer;
3184 case IFCOUNTER_OPACKETS:
3185 retval = priv->stats.vport.tx_packets;
3187 case IFCOUNTER_OERRORS:
3188 retval = priv->stats.port_stats_debug.out_discards;
3190 case IFCOUNTER_IBYTES:
3191 retval = priv->stats.vport.rx_bytes;
3193 case IFCOUNTER_OBYTES:
3194 retval = priv->stats.vport.tx_bytes;
3196 case IFCOUNTER_IMCASTS:
3197 retval = priv->stats.vport.rx_multicast_packets;
3199 case IFCOUNTER_OMCASTS:
3200 retval = priv->stats.vport.tx_multicast_packets;
3202 case IFCOUNTER_OQDROPS:
3203 retval = priv->stats.vport.tx_queue_dropped;
3205 case IFCOUNTER_COLLISIONS:
3206 retval = priv->stats.pport.collisions;
3209 retval = if_get_counter_default(ifp, cnt);
3212 /* PRIV_UNLOCK(priv); XXX not allowed */
3218 mlx5e_set_rx_mode(struct ifnet *ifp)
3220 struct mlx5e_priv *priv = ifp->if_softc;
3222 queue_work(priv->wq, &priv->set_rx_mode_work);
3226 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3228 struct mlx5e_priv *priv;
3230 struct ifi2creq i2c;
3239 priv = ifp->if_softc;
3241 /* check if detaching */
3242 if (priv == NULL || priv->gone != 0)
3247 ifr = (struct ifreq *)data;
3250 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3252 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3253 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3256 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3258 mlx5e_close_locked(ifp);
3261 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3264 mlx5e_open_locked(ifp);
3268 "Invalid MTU value. Min val: %d, Max val: %d\n",
3269 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3274 if ((ifp->if_flags & IFF_UP) &&
3275 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3276 mlx5e_set_rx_mode(ifp);
3280 if (ifp->if_flags & IFF_UP) {
3281 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3282 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3283 mlx5e_open_locked(ifp);
3284 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3285 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3288 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3289 mlx5_set_port_status(priv->mdev,
3291 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3292 mlx5e_close_locked(ifp);
3293 mlx5e_update_carrier(priv);
3294 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3301 mlx5e_set_rx_mode(ifp);
3306 ifr = (struct ifreq *)data;
3307 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3310 ifr = (struct ifreq *)data;
3312 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3314 if (mask & IFCAP_TXCSUM) {
3315 ifp->if_capenable ^= IFCAP_TXCSUM;
3316 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3318 if (IFCAP_TSO4 & ifp->if_capenable &&
3319 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3320 ifp->if_capenable &= ~IFCAP_TSO4;
3321 ifp->if_hwassist &= ~CSUM_IP_TSO;
3323 "tso4 disabled due to -txcsum.\n");
3326 if (mask & IFCAP_TXCSUM_IPV6) {
3327 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3328 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3330 if (IFCAP_TSO6 & ifp->if_capenable &&
3331 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3332 ifp->if_capenable &= ~IFCAP_TSO6;
3333 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3335 "tso6 disabled due to -txcsum6.\n");
3338 if (mask & IFCAP_NOMAP)
3339 ifp->if_capenable ^= IFCAP_NOMAP;
3340 if (mask & IFCAP_TXTLS4)
3341 ifp->if_capenable ^= IFCAP_TXTLS4;
3342 if (mask & IFCAP_TXTLS6)
3343 ifp->if_capenable ^= IFCAP_TXTLS6;
3344 if (mask & IFCAP_RXCSUM)
3345 ifp->if_capenable ^= IFCAP_RXCSUM;
3346 if (mask & IFCAP_RXCSUM_IPV6)
3347 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3348 if (mask & IFCAP_TSO4) {
3349 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3350 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3351 mlx5_en_err(ifp, "enable txcsum first.\n");
3355 ifp->if_capenable ^= IFCAP_TSO4;
3356 ifp->if_hwassist ^= CSUM_IP_TSO;
3358 if (mask & IFCAP_TSO6) {
3359 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3360 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3361 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3365 ifp->if_capenable ^= IFCAP_TSO6;
3366 ifp->if_hwassist ^= CSUM_IP6_TSO;
3368 if (mask & IFCAP_VLAN_HWFILTER) {
3369 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3370 mlx5e_disable_vlan_filter(priv);
3372 mlx5e_enable_vlan_filter(priv);
3374 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3376 if (mask & IFCAP_VLAN_HWTAGGING)
3377 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3378 if (mask & IFCAP_WOL_MAGIC)
3379 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3381 VLAN_CAPABILITIES(ifp);
3382 /* turn off LRO means also turn of HW LRO - if it's on */
3383 if (mask & IFCAP_LRO) {
3384 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3385 bool need_restart = false;
3387 ifp->if_capenable ^= IFCAP_LRO;
3389 /* figure out if updating HW LRO is needed */
3390 if (!(ifp->if_capenable & IFCAP_LRO)) {
3391 if (priv->params.hw_lro_en) {
3392 priv->params.hw_lro_en = false;
3393 need_restart = true;
3396 if (priv->params.hw_lro_en == false &&
3397 priv->params_ethtool.hw_lro != 0) {
3398 priv->params.hw_lro_en = true;
3399 need_restart = true;
3402 if (was_opened && need_restart) {
3403 mlx5e_close_locked(ifp);
3404 mlx5e_open_locked(ifp);
3407 if (mask & IFCAP_HWRXTSTMP) {
3408 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3409 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3410 if (priv->clbr_done == 0)
3411 mlx5e_reset_calibration_callout(priv);
3413 callout_drain(&priv->tstmp_clbr);
3414 priv->clbr_done = 0;
3422 ifr = (struct ifreq *)data;
3425 * Copy from the user-space address ifr_data to the
3426 * kernel-space address i2c
3428 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3432 if (i2c.len > sizeof(i2c.data)) {
3438 /* Get module_num which is required for the query_eeprom */
3439 error = mlx5_query_module_num(priv->mdev, &module_num);
3442 "Query module num failed, eeprom reading is not supported\n");
3446 /* Check if module is present before doing an access */
3447 module_status = mlx5_query_module_status(priv->mdev, module_num);
3448 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3453 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3454 * The internal conversion is as follows:
3456 if (i2c.dev_addr == 0xA0)
3457 read_addr = MLX5_I2C_ADDR_LOW;
3458 else if (i2c.dev_addr == 0xA2)
3459 read_addr = MLX5_I2C_ADDR_HIGH;
3462 "Query eeprom failed, Invalid Address: %X\n",
3467 error = mlx5_query_eeprom(priv->mdev,
3468 read_addr, MLX5_EEPROM_LOW_PAGE,
3469 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3470 (uint32_t *)i2c.data, &size_read);
3473 "Query eeprom failed, eeprom reading is not supported\n");
3478 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3479 error = mlx5_query_eeprom(priv->mdev,
3480 read_addr, MLX5_EEPROM_LOW_PAGE,
3481 (uint32_t)(i2c.offset + size_read),
3482 (uint32_t)(i2c.len - size_read), module_num,
3483 (uint32_t *)(i2c.data + size_read), &size_read);
3487 "Query eeprom failed, eeprom reading is not supported\n");
3492 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3498 error = ether_ioctl(ifp, command, data);
3505 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3508 * TODO: uncoment once FW really sets all these bits if
3509 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3510 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3511 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3515 /* TODO: add more must-to-have features */
3517 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3524 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3526 uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3528 bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3530 /* verify against driver hardware limit */
3531 if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3532 bf_buf_size = MLX5E_MAX_TX_INLINE;
3534 return (bf_buf_size);
3538 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3539 struct mlx5e_priv *priv,
3540 int num_comp_vectors)
3545 * TODO: Consider link speed for setting "log_sq_size",
3546 * "log_rq_size" and "cq_moderation_xxx":
3548 priv->params.log_sq_size =
3549 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3550 priv->params.log_rq_size =
3551 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3552 priv->params.rx_cq_moderation_usec =
3553 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3554 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3555 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3556 priv->params.rx_cq_moderation_mode =
3557 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3558 priv->params.rx_cq_moderation_pkts =
3559 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3560 priv->params.tx_cq_moderation_usec =
3561 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3562 priv->params.tx_cq_moderation_pkts =
3563 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3564 priv->params.min_rx_wqes =
3565 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3566 priv->params.rx_hash_log_tbl_sz =
3567 (order_base_2(num_comp_vectors) >
3568 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3569 order_base_2(num_comp_vectors) :
3570 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3571 priv->params.num_tc = 1;
3572 priv->params.default_vlan_prio = 0;
3573 priv->counter_set_id = -1;
3574 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3576 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3581 * hw lro is currently defaulted to off. when it won't anymore we
3582 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3584 priv->params.hw_lro_en = false;
3585 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3588 * CQE zipping is currently defaulted to off. when it won't
3589 * anymore we will consider the HW capability:
3590 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3592 priv->params.cqe_zipping_en = false;
3595 priv->params.num_channels = num_comp_vectors;
3596 priv->params.channels_rsss = 1;
3597 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3598 priv->queue_mapping_channel_mask =
3599 roundup_pow_of_two(num_comp_vectors) - 1;
3600 priv->num_tc = priv->params.num_tc;
3601 priv->default_vlan_prio = priv->params.default_vlan_prio;
3603 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3604 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3605 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3611 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3612 struct mlx5_core_mr *mkey)
3614 struct ifnet *ifp = priv->ifp;
3615 struct mlx5_core_dev *mdev = priv->mdev;
3616 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3621 in = mlx5_vzalloc(inlen);
3623 mlx5_en_err(ifp, "failed to allocate inbox\n");
3627 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3628 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3629 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */
3630 MLX5_SET(mkc, mkc, lw, 1);
3631 MLX5_SET(mkc, mkc, lr, 1);
3633 MLX5_SET(mkc, mkc, pd, pdn);
3634 MLX5_SET(mkc, mkc, length64, 1);
3635 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3637 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3639 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3646 static const char *mlx5e_vport_stats_desc[] = {
3647 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3650 static const char *mlx5e_pport_stats_desc[] = {
3651 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3655 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3659 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3660 sx_init(&priv->state_lock, "mlx5state");
3661 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3662 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3663 for (x = 0; x != channels; x++)
3664 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3668 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3672 for (x = 0; x != channels; x++)
3673 mlx5e_chan_static_destroy(&priv->channel[x]);
3674 callout_drain(&priv->watchdog);
3675 mtx_destroy(&priv->async_events_mtx);
3676 sx_destroy(&priv->state_lock);
3680 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3683 * %d.%d%.d the string format.
3684 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3685 * We need at most 5 chars to store that.
3686 * It also has: two "." and NULL at the end, which means we need 18
3687 * (5*3 + 3) chars at most.
3690 struct mlx5e_priv *priv = arg1;
3693 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3694 fw_rev_sub(priv->mdev));
3695 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3700 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3704 for (i = 0; i < ch->priv->num_tc; i++)
3705 mlx5e_drain_sq(&ch->sq[i]);
3709 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3712 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3713 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3714 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3715 sq->doorbell.d64 = 0;
3719 mlx5e_resume_sq(struct mlx5e_sq *sq)
3723 /* check if already enabled */
3724 if (READ_ONCE(sq->running) != 0)
3727 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3728 MLX5_SQC_STATE_RST);
3730 mlx5_en_err(sq->ifp,
3731 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3737 /* reset doorbell prior to moving from RST to RDY */
3738 mlx5e_reset_sq_doorbell_record(sq);
3740 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3741 MLX5_SQC_STATE_RDY);
3743 mlx5_en_err(sq->ifp,
3744 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3747 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3748 WRITE_ONCE(sq->running, 1);
3752 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3756 for (i = 0; i < ch->priv->num_tc; i++)
3757 mlx5e_resume_sq(&ch->sq[i]);
3761 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3763 struct mlx5e_rq *rq = &ch->rq;
3764 struct epoch_tracker et;
3769 callout_stop(&rq->watchdog);
3770 mtx_unlock(&rq->mtx);
3772 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3774 mlx5_en_err(rq->ifp,
3775 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3778 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3780 NET_EPOCH_ENTER(et);
3781 rq->cq.mcq.comp(&rq->cq.mcq);
3786 * Transitioning into RST state will allow the FW to track less ERR state queues,
3787 * thus reducing the recv queue flushing time
3789 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3791 mlx5_en_err(rq->ifp,
3792 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3797 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3799 struct mlx5e_rq *rq = &ch->rq;
3800 struct epoch_tracker et;
3804 mlx5_wq_ll_update_db_record(&rq->wq);
3805 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3807 mlx5_en_err(rq->ifp,
3808 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3813 NET_EPOCH_ENTER(et);
3814 rq->cq.mcq.comp(&rq->cq.mcq);
3819 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3823 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3826 for (i = 0; i < priv->params.num_channels; i++) {
3828 mlx5e_disable_tx_dma(&priv->channel[i]);
3830 mlx5e_enable_tx_dma(&priv->channel[i]);
3835 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3839 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3842 for (i = 0; i < priv->params.num_channels; i++) {
3844 mlx5e_disable_rx_dma(&priv->channel[i]);
3846 mlx5e_enable_rx_dma(&priv->channel[i]);
3851 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3853 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3854 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
3855 priv, 0, sysctl_firmware, "A", "HCA firmware version");
3857 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3858 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3863 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3865 struct mlx5e_priv *priv = arg1;
3866 uint8_t temp[MLX5E_MAX_PRIORITY];
3873 tx_pfc = priv->params.tx_priority_flow_control;
3875 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3876 temp[i] = (tx_pfc >> i) & 1;
3878 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3879 if (err || !req->newptr)
3881 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3885 priv->params.tx_priority_flow_control = 0;
3887 /* range check input value */
3888 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3893 priv->params.tx_priority_flow_control |= (temp[i] << i);
3896 /* check if update is required */
3897 if (tx_pfc != priv->params.tx_priority_flow_control)
3898 err = -mlx5e_set_port_pfc(priv);
3901 priv->params.tx_priority_flow_control= tx_pfc;
3908 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3910 struct mlx5e_priv *priv = arg1;
3911 uint8_t temp[MLX5E_MAX_PRIORITY];
3918 rx_pfc = priv->params.rx_priority_flow_control;
3920 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3921 temp[i] = (rx_pfc >> i) & 1;
3923 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3924 if (err || !req->newptr)
3926 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3930 priv->params.rx_priority_flow_control = 0;
3932 /* range check input value */
3933 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3938 priv->params.rx_priority_flow_control |= (temp[i] << i);
3941 /* check if update is required */
3942 if (rx_pfc != priv->params.rx_priority_flow_control) {
3943 err = -mlx5e_set_port_pfc(priv);
3944 if (err == 0 && priv->sw_is_port_buf_owner)
3945 err = mlx5e_update_buf_lossy(priv);
3949 priv->params.rx_priority_flow_control= rx_pfc;
3956 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3958 #if (__FreeBSD_version < 1100000)
3963 /* enable pauseframes by default */
3964 priv->params.tx_pauseframe_control = 1;
3965 priv->params.rx_pauseframe_control = 1;
3967 /* disable ports flow control, PFC, by default */
3968 priv->params.tx_priority_flow_control = 0;
3969 priv->params.rx_priority_flow_control = 0;
3971 #if (__FreeBSD_version < 1100000)
3972 /* compute path for sysctl */
3973 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3974 device_get_unit(priv->mdev->pdev->dev.bsddev));
3976 /* try to fetch tunable, if any */
3977 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3979 /* compute path for sysctl */
3980 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3981 device_get_unit(priv->mdev->pdev->dev.bsddev));
3983 /* try to fetch tunable, if any */
3984 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3987 /* register pauseframe SYSCTLs */
3988 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3989 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3990 &priv->params.tx_pauseframe_control, 0,
3991 "Set to enable TX pause frames. Clear to disable.");
3993 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3994 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3995 &priv->params.rx_pauseframe_control, 0,
3996 "Set to enable RX pause frames. Clear to disable.");
3998 /* register priority flow control, PFC, SYSCTLs */
3999 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4000 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4001 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4002 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4004 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4005 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4006 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4007 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4012 priv->params.tx_pauseframe_control =
4013 priv->params.tx_pauseframe_control ? 1 : 0;
4014 priv->params.rx_pauseframe_control =
4015 priv->params.rx_pauseframe_control ? 1 : 0;
4017 /* update firmware */
4018 error = mlx5e_set_port_pause_and_pfc(priv);
4019 if (error == -EINVAL) {
4020 mlx5_en_err(priv->ifp,
4021 "Global pauseframes must be disabled before enabling PFC.\n");
4022 priv->params.rx_priority_flow_control = 0;
4023 priv->params.tx_priority_flow_control = 0;
4025 /* update firmware */
4026 (void) mlx5e_set_port_pause_and_pfc(priv);
4032 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4033 union if_snd_tag_alloc_params *params,
4034 struct m_snd_tag **ppmt)
4036 struct mlx5e_priv *priv;
4037 struct mlx5e_channel *pch;
4039 priv = ifp->if_softc;
4041 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4042 return (EOPNOTSUPP);
4044 /* keep this code synced with mlx5e_select_queue() */
4045 u32 ch = priv->params.num_channels;
4049 if (rss_hash2bucket(params->hdr.flowid,
4050 params->hdr.flowtype, &temp) == 0)
4054 ch = (params->hdr.flowid % 128) % ch;
4057 * NOTE: The channels array is only freed at detach
4058 * and it safe to return a pointer to the send tag
4059 * inside the channels structure as long as we
4060 * reference the priv.
4062 pch = priv->channel + ch;
4064 /* check if send queue is not running */
4065 if (unlikely(pch->sq[0].running == 0))
4067 m_snd_tag_ref(&pch->tag.m_snd_tag);
4068 *ppmt = &pch->tag.m_snd_tag;
4074 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4076 struct mlx5e_channel *pch =
4077 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4079 params->unlimited.max_rate = -1ULL;
4080 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4085 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4087 struct mlx5e_channel *pch =
4088 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4090 complete(&pch->completion);
4094 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4095 union if_snd_tag_alloc_params *params,
4096 struct m_snd_tag **ppmt)
4099 switch (params->hdr.type) {
4101 case IF_SND_TAG_TYPE_RATE_LIMIT:
4102 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4103 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4104 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4105 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4108 case IF_SND_TAG_TYPE_UNLIMITED:
4109 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4111 case IF_SND_TAG_TYPE_TLS:
4112 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4115 return (EOPNOTSUPP);
4120 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4122 struct mlx5e_snd_tag *tag =
4123 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4125 switch (tag->type) {
4127 case IF_SND_TAG_TYPE_RATE_LIMIT:
4128 return (mlx5e_rl_snd_tag_modify(pmt, params));
4129 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4130 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4131 return (mlx5e_tls_snd_tag_modify(pmt, params));
4134 case IF_SND_TAG_TYPE_UNLIMITED:
4136 case IF_SND_TAG_TYPE_TLS:
4139 return (EOPNOTSUPP);
4144 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4146 struct mlx5e_snd_tag *tag =
4147 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4149 switch (tag->type) {
4151 case IF_SND_TAG_TYPE_RATE_LIMIT:
4152 return (mlx5e_rl_snd_tag_query(pmt, params));
4153 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4154 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4155 return (mlx5e_tls_snd_tag_query(pmt, params));
4158 case IF_SND_TAG_TYPE_UNLIMITED:
4159 return (mlx5e_ul_snd_tag_query(pmt, params));
4161 case IF_SND_TAG_TYPE_TLS:
4162 return (mlx5e_tls_snd_tag_query(pmt, params));
4165 return (EOPNOTSUPP);
4170 #define NUM_HDWR_RATES_MLX 13
4171 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4172 135375, /* 1,083,000 */
4173 180500, /* 1,444,000 */
4174 270750, /* 2,166,000 */
4175 361000, /* 2,888,000 */
4176 541500, /* 4,332,000 */
4177 721875, /* 5,775,000 */
4178 1082875, /* 8,663,000 */
4179 1443875, /* 11,551,000 */
4180 2165750, /* 17,326,000 */
4181 2887750, /* 23,102,000 */
4182 4331625, /* 34,653,000 */
4183 5775500, /* 46,204,000 */
4184 8663125 /* 69,305,000 */
4188 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4191 * This function needs updating by the driver maintainer!
4192 * For the MLX card there are currently (ConectX-4?) 13
4193 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4195 * This will change based on later adapters
4196 * and this code should be updated to look at ifp
4197 * and figure out the specific adapter type
4198 * settings i.e. how many rates as well
4199 * as if they are fixed (as is shown here) or
4200 * if they are dynamic (example chelsio t4). Also if there
4201 * is a maximum number of flows that the adapter
4202 * can handle that too needs to be updated in
4203 * the max_flows field.
4205 q->rate_table = adapter_rates_mlx;
4206 q->flags = RT_IS_FIXED_TABLE;
4207 q->max_flows = 0; /* mlx has no limit */
4208 q->number_of_rates = NUM_HDWR_RATES_MLX;
4209 q->min_segment_burst = 1;
4214 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4216 struct mlx5e_snd_tag *tag =
4217 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4219 switch (tag->type) {
4221 case IF_SND_TAG_TYPE_RATE_LIMIT:
4222 mlx5e_rl_snd_tag_free(pmt);
4224 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4225 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4226 mlx5e_tls_snd_tag_free(pmt);
4230 case IF_SND_TAG_TYPE_UNLIMITED:
4231 mlx5e_ul_snd_tag_free(pmt);
4234 case IF_SND_TAG_TYPE_TLS:
4235 mlx5e_tls_snd_tag_free(pmt);
4244 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4247 struct mlx5e_priv *priv;
4248 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4250 struct sysctl_oid_list *child;
4251 int ncv = mdev->priv.eq_table.num_comp_vectors;
4253 struct pfil_head_args pa;
4257 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4260 struct media media_entry = {};
4262 if (mlx5e_check_required_hca_cap(mdev)) {
4263 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4267 * Try to allocate the priv and make room for worst-case
4268 * number of channel structures:
4270 priv = malloc(sizeof(*priv) +
4271 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4272 M_MLX5EN, M_WAITOK | M_ZERO);
4274 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4276 mlx5_core_err(mdev, "if_alloc() failed\n");
4279 /* setup all static fields */
4280 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4282 ifp->if_softc = priv;
4283 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4284 ifp->if_mtu = ETHERMTU;
4285 ifp->if_init = mlx5e_open;
4286 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
4288 ifp->if_ioctl = mlx5e_ioctl;
4289 ifp->if_transmit = mlx5e_xmit;
4290 ifp->if_qflush = if_qflush;
4291 #if (__FreeBSD_version >= 1100000)
4292 ifp->if_get_counter = mlx5e_get_counter;
4294 ifp->if_snd.ifq_maxlen = ifqmaxlen;
4296 * Set driver features
4298 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4299 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4300 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4301 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4302 ifp->if_capabilities |= IFCAP_LRO;
4303 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4304 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4305 ifp->if_capabilities |= IFCAP_NOMAP;
4306 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4307 ifp->if_capabilities |= IFCAP_TXRTLMT;
4308 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4309 ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4310 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4311 ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4313 ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4315 /* set TSO limits so that we don't have to drop TX packets */
4316 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4317 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4318 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4320 ifp->if_capenable = ifp->if_capabilities;
4321 ifp->if_hwassist = 0;
4322 if (ifp->if_capenable & IFCAP_TSO)
4323 ifp->if_hwassist |= CSUM_TSO;
4324 if (ifp->if_capenable & IFCAP_TXCSUM)
4325 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4326 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4327 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4329 /* ifnet sysctl tree */
4330 sysctl_ctx_init(&priv->sysctl_ctx);
4331 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4332 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4333 "MLX5 ethernet - interface name");
4334 if (priv->sysctl_ifnet == NULL) {
4335 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4336 goto err_free_sysctl;
4338 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4339 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4340 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4341 "MLX5 ethernet - interface unit");
4342 if (priv->sysctl_ifnet == NULL) {
4343 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4344 goto err_free_sysctl;
4347 /* HW sysctl tree */
4348 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4349 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4350 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4351 "MLX5 ethernet dev hw");
4352 if (priv->sysctl_hw == NULL) {
4353 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4354 goto err_free_sysctl;
4357 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4359 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4360 goto err_free_sysctl;
4363 /* reuse mlx5core's watchdog workqueue */
4364 priv->wq = mdev->priv.health.wq_watchdog;
4366 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4368 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4371 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4373 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4374 goto err_unmap_free_uar;
4376 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4379 "mlx5_alloc_transport_domain failed, %d\n", err);
4380 goto err_dealloc_pd;
4382 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4384 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4385 goto err_dealloc_transport_domain;
4387 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4389 /* check if we should generate a random MAC address */
4390 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4391 is_zero_ether_addr(dev_addr)) {
4392 random_ether_addr(dev_addr);
4393 mlx5_en_err(ifp, "Assigned random MAC address\n");
4396 err = mlx5e_rl_init(priv);
4398 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4399 goto err_create_mkey;
4402 err = mlx5e_tls_init(priv);
4404 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4408 /* set default MTU */
4409 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4411 /* Set default media status */
4412 priv->media_status_last = IFM_AVALID;
4413 priv->media_active_last = IFM_ETHER | IFM_AUTO |
4414 IFM_ETH_RXPAUSE | IFM_FDX;
4416 /* setup default pauseframes configuration */
4417 mlx5e_setup_pauseframes(priv);
4419 /* Setup supported medias */
4420 //TODO: If we failed to query ptys is it ok to proceed??
4421 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4422 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4423 ptys_extended_ethernet);
4424 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4425 eth_proto_capability);
4426 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4427 connector_type = MLX5_GET(ptys_reg, out,
4431 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4434 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4435 mlx5e_media_change, mlx5e_media_status);
4437 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4438 for (i = 0; i != speeds_num; i++) {
4439 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4440 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4441 mlx5e_mode_table[i][j];
4442 if (media_entry.baudrate == 0)
4444 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4445 ifmedia_add(&priv->media,
4446 media_entry.subtype |
4447 IFM_ETHER, 0, NULL);
4448 ifmedia_add(&priv->media,
4449 media_entry.subtype |
4450 IFM_ETHER | IFM_FDX |
4451 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4456 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4457 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4458 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4460 /* Set autoselect by default */
4461 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4462 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4464 DEBUGNET_SET(ifp, mlx5_en);
4466 ether_ifattach(ifp, dev_addr);
4468 /* Register for VLAN events */
4469 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4470 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4471 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4472 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4474 /* Link is down by default */
4475 if_link_state_change(ifp, LINK_STATE_DOWN);
4477 mlx5e_enable_async_events(priv);
4479 mlx5e_add_hw_stats(priv);
4481 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4482 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4483 priv->stats.vport.arg);
4485 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4486 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4487 priv->stats.pport.arg);
4489 mlx5e_create_ethtool(priv);
4491 mtx_lock(&priv->async_events_mtx);
4492 mlx5e_update_stats(priv);
4493 mtx_unlock(&priv->async_events_mtx);
4495 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4496 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4497 &priv->clbr_done, 0,
4498 "RX timestamps calibration state");
4499 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4500 mlx5e_reset_calibration_callout(priv);
4502 pa.pa_version = PFIL_VERSION;
4503 pa.pa_flags = PFIL_IN;
4504 pa.pa_type = PFIL_TYPE_ETHERNET;
4505 pa.pa_headname = ifp->if_xname;
4506 priv->pfil = pfil_head_register(&pa);
4511 mlx5e_rl_cleanup(priv);
4514 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4516 err_dealloc_transport_domain:
4517 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4520 mlx5_core_dealloc_pd(mdev, priv->pdn);
4523 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4526 flush_workqueue(priv->wq);
4529 sysctl_ctx_free(&priv->sysctl_ctx);
4530 if (priv->sysctl_debug)
4531 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4532 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4536 free(priv, M_MLX5EN);
4541 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4543 struct mlx5e_priv *priv = vpriv;
4544 struct ifnet *ifp = priv->ifp;
4546 /* don't allow more IOCTLs */
4549 /* XXX wait a bit to allow IOCTL handlers to complete */
4554 * The kernel can have reference(s) via the m_snd_tag's into
4555 * the ratelimit channels, and these must go away before
4558 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4559 mlx5_en_err(priv->ifp,
4560 "Waiting for all ratelimit connections to terminate\n");
4564 /* wait for all unlimited send tags to complete */
4565 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4567 /* stop watchdog timer */
4568 callout_drain(&priv->watchdog);
4570 callout_drain(&priv->tstmp_clbr);
4572 if (priv->vlan_attach != NULL)
4573 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4574 if (priv->vlan_detach != NULL)
4575 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4577 /* make sure device gets closed */
4579 mlx5e_close_locked(ifp);
4582 /* deregister pfil */
4583 if (priv->pfil != NULL) {
4584 pfil_head_unregister(priv->pfil);
4588 /* unregister device */
4589 ifmedia_removeall(&priv->media);
4590 ether_ifdetach(ifp);
4592 mlx5e_tls_cleanup(priv);
4593 mlx5e_rl_cleanup(priv);
4595 /* destroy all remaining sysctl nodes */
4596 sysctl_ctx_free(&priv->stats.vport.ctx);
4597 sysctl_ctx_free(&priv->stats.pport.ctx);
4598 if (priv->sysctl_debug)
4599 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4600 sysctl_ctx_free(&priv->sysctl_ctx);
4602 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4603 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4604 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4605 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4606 mlx5e_disable_async_events(priv);
4607 flush_workqueue(priv->wq);
4608 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4610 free(priv, M_MLX5EN);
4615 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4617 struct mlx5e_priv *priv = if_getsoftc(dev);
4620 *nrxr = priv->params.num_channels;
4621 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4622 *clsize = MLX5E_MAX_RX_BYTES;
4627 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4632 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
4634 struct mlx5e_priv *priv = if_getsoftc(dev);
4635 struct mlx5e_sq *sq;
4638 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4639 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
4642 sq = &priv->channel[0].sq[0];
4644 if (sq->running == 0) {
4649 if (mlx5e_sq_xmit(sq, &m) != 0) {
4656 if (likely(sq->doorbell.d64 != 0)) {
4657 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
4658 sq->doorbell.d64 = 0;
4664 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
4666 struct mlx5e_priv *priv = if_getsoftc(dev);
4668 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
4669 (priv->media_status_last & IFM_ACTIVE) == 0)
4672 mlx5_poll_interrupts(priv->mdev);
4676 #endif /* DEBUGNET */
4679 mlx5e_get_ifp(void *vpriv)
4681 struct mlx5e_priv *priv = vpriv;
4686 static struct mlx5_interface mlx5e_interface = {
4687 .add = mlx5e_create_ifp,
4688 .remove = mlx5e_destroy_ifp,
4689 .event = mlx5e_async_event,
4690 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4691 .get_dev = mlx5e_get_ifp,
4697 mlx5_register_interface(&mlx5e_interface);
4703 mlx5_unregister_interface(&mlx5e_interface);
4707 mlx5e_show_version(void __unused *arg)
4710 printf("%s", mlx5e_version);
4712 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4714 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4715 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4717 #if (__FreeBSD_version >= 1100000)
4718 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4720 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4721 MODULE_VERSION(mlx5en, 1);