sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/eventhandler.h>
  31 #include <sys/sockio.h>
  32 #include <machine/atomic.h>
  33
  34 #ifndef ETH_DRIVER_VERSION
  35 #define ETH_DRIVER_VERSION      "3.5.2"
  36 #endif
  37 #define DRIVER_RELDATE  "September 2019"
  38
  39 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  40         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  41
  42 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  43
  44 struct mlx5e_channel_param {
  45         struct mlx5e_rq_param rq;
  46         struct mlx5e_sq_param sq;
  47         struct mlx5e_cq_param rx_cq;
  48         struct mlx5e_cq_param tx_cq;
  49 };
  50
  51 struct media {
  52         u32     subtype;
  53         u64     baudrate;
  54 };
  55
  56 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  57
  58         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  59                 .subtype = IFM_1000_CX_SGMII,
  60                 .baudrate = IF_Mbps(1000ULL),
  61         },
  62         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  63                 .subtype = IFM_1000_KX,
  64                 .baudrate = IF_Mbps(1000ULL),
  65         },
  66         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  67                 .subtype = IFM_10G_CX4,
  68                 .baudrate = IF_Gbps(10ULL),
  69         },
  70         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  71                 .subtype = IFM_10G_KX4,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  75                 .subtype = IFM_10G_KR,
  76                 .baudrate = IF_Gbps(10ULL),
  77         },
  78         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  79                 .subtype = IFM_20G_KR2,
  80                 .baudrate = IF_Gbps(20ULL),
  81         },
  82         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  83                 .subtype = IFM_40G_CR4,
  84                 .baudrate = IF_Gbps(40ULL),
  85         },
  86         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  87                 .subtype = IFM_40G_KR4,
  88                 .baudrate = IF_Gbps(40ULL),
  89         },
  90         [MLX5E_56GBASE_R4][MLX5E_R] = {
  91                 .subtype = IFM_56G_R4,
  92                 .baudrate = IF_Gbps(56ULL),
  93         },
  94         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  95                 .subtype = IFM_10G_CR1,
  96                 .baudrate = IF_Gbps(10ULL),
  97         },
  98         [MLX5E_10GBASE_SR][MLX5E_SR] = {
  99                 .subtype = IFM_10G_SR,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 103                 .subtype = IFM_10G_ER,
 104                 .baudrate = IF_Gbps(10ULL),
 105         },
 106         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 107                 .subtype = IFM_10G_LR,
 108                 .baudrate = IF_Gbps(10ULL),
 109         },
 110         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 111                 .subtype = IFM_40G_SR4,
 112                 .baudrate = IF_Gbps(40ULL),
 113         },
 114         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 115                 .subtype = IFM_40G_LR4,
 116                 .baudrate = IF_Gbps(40ULL),
 117         },
 118         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 119                 .subtype = IFM_40G_ER4,
 120                 .baudrate = IF_Gbps(40ULL),
 121         },
 122         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 123                 .subtype = IFM_100G_CR4,
 124                 .baudrate = IF_Gbps(100ULL),
 125         },
 126         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 127                 .subtype = IFM_100G_SR4,
 128                 .baudrate = IF_Gbps(100ULL),
 129         },
 130         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 131                 .subtype = IFM_100G_KR4,
 132                 .baudrate = IF_Gbps(100ULL),
 133         },
 134         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 135                 .subtype = IFM_100G_LR4,
 136                 .baudrate = IF_Gbps(100ULL),
 137         },
 138         [MLX5E_100BASE_TX][MLX5E_TX] = {
 139                 .subtype = IFM_100_TX,
 140                 .baudrate = IF_Mbps(100ULL),
 141         },
 142         [MLX5E_1000BASE_T][MLX5E_T] = {
 143                 .subtype = IFM_1000_T,
 144                 .baudrate = IF_Mbps(1000ULL),
 145         },
 146         [MLX5E_10GBASE_T][MLX5E_T] = {
 147                 .subtype = IFM_10G_T,
 148                 .baudrate = IF_Gbps(10ULL),
 149         },
 150         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 151                 .subtype = IFM_25G_CR,
 152                 .baudrate = IF_Gbps(25ULL),
 153         },
 154         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 155                 .subtype = IFM_25G_KR,
 156                 .baudrate = IF_Gbps(25ULL),
 157         },
 158         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 159                 .subtype = IFM_25G_SR,
 160                 .baudrate = IF_Gbps(25ULL),
 161         },
 162         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 163                 .subtype = IFM_50G_CR2,
 164                 .baudrate = IF_Gbps(50ULL),
 165         },
 166         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 167                 .subtype = IFM_50G_KR2,
 168                 .baudrate = IF_Gbps(50ULL),
 169         },
 170 };
 171
 172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 173         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 174                 .subtype = IFM_100_SGMII,
 175                 .baudrate = IF_Mbps(100),
 176         },
 177         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 178                 .subtype = IFM_1000_KX,
 179                 .baudrate = IF_Mbps(1000),
 180         },
 181         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 182                 .subtype = IFM_1000_CX_SGMII,
 183                 .baudrate = IF_Mbps(1000),
 184         },
 185         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 186                 .subtype = IFM_1000_CX,
 187                 .baudrate = IF_Mbps(1000),
 188         },
 189         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 190                 .subtype = IFM_1000_LX,
 191                 .baudrate = IF_Mbps(1000),
 192         },
 193         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 194                 .subtype = IFM_1000_SX,
 195                 .baudrate = IF_Mbps(1000),
 196         },
 197         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 198                 .subtype = IFM_1000_T,
 199                 .baudrate = IF_Mbps(1000),
 200         },
 201         [MLX5E_5GBASE_R][MLX5E_T] = {
 202                 .subtype = IFM_5000_T,
 203                 .baudrate = IF_Mbps(5000),
 204         },
 205         [MLX5E_5GBASE_R][MLX5E_KR] = {
 206                 .subtype = IFM_5000_KR,
 207                 .baudrate = IF_Mbps(5000),
 208         },
 209         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 210                 .subtype = IFM_5000_KR1,
 211                 .baudrate = IF_Mbps(5000),
 212         },
 213         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 214                 .subtype = IFM_5000_KR_S,
 215                 .baudrate = IF_Mbps(5000),
 216         },
 217         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 218                 .subtype = IFM_10G_ER,
 219                 .baudrate = IF_Gbps(10ULL),
 220         },
 221         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 222                 .subtype = IFM_10G_KR,
 223                 .baudrate = IF_Gbps(10ULL),
 224         },
 225         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 226                 .subtype = IFM_10G_LR,
 227                 .baudrate = IF_Gbps(10ULL),
 228         },
 229         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 230                 .subtype = IFM_10G_SR,
 231                 .baudrate = IF_Gbps(10ULL),
 232         },
 233         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 234                 .subtype = IFM_10G_T,
 235                 .baudrate = IF_Gbps(10ULL),
 236         },
 237         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 238                 .subtype = IFM_10G_AOC,
 239                 .baudrate = IF_Gbps(10ULL),
 240         },
 241         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 242                 .subtype = IFM_10G_CR1,
 243                 .baudrate = IF_Gbps(10ULL),
 244         },
 245         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 246                 .subtype = IFM_40G_CR4,
 247                 .baudrate = IF_Gbps(40ULL),
 248         },
 249         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 250                 .subtype = IFM_40G_KR4,
 251                 .baudrate = IF_Gbps(40ULL),
 252         },
 253         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 254                 .subtype = IFM_40G_LR4,
 255                 .baudrate = IF_Gbps(40ULL),
 256         },
 257         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 258                 .subtype = IFM_40G_SR4,
 259                 .baudrate = IF_Gbps(40ULL),
 260         },
 261         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 262                 .subtype = IFM_40G_ER4,
 263                 .baudrate = IF_Gbps(40ULL),
 264         },
 265
 266         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 267                 .subtype = IFM_25G_CR,
 268                 .baudrate = IF_Gbps(25ULL),
 269         },
 270         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 271                 .subtype = IFM_25G_KR,
 272                 .baudrate = IF_Gbps(25ULL),
 273         },
 274         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 275                 .subtype = IFM_25G_SR,
 276                 .baudrate = IF_Gbps(25ULL),
 277         },
 278         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 279                 .subtype = IFM_25G_ACC,
 280                 .baudrate = IF_Gbps(25ULL),
 281         },
 282         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 283                 .subtype = IFM_25G_AOC,
 284                 .baudrate = IF_Gbps(25ULL),
 285         },
 286         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 287                 .subtype = IFM_25G_CR1,
 288                 .baudrate = IF_Gbps(25ULL),
 289         },
 290         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 291                 .subtype = IFM_25G_CR_S,
 292                 .baudrate = IF_Gbps(25ULL),
 293         },
 294         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 295                 .subtype = IFM_5000_KR1,
 296                 .baudrate = IF_Gbps(25ULL),
 297         },
 298         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 299                 .subtype = IFM_25G_KR_S,
 300                 .baudrate = IF_Gbps(25ULL),
 301         },
 302         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 303                 .subtype = IFM_25G_LR,
 304                 .baudrate = IF_Gbps(25ULL),
 305         },
 306         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 307                 .subtype = IFM_25G_T,
 308                 .baudrate = IF_Gbps(25ULL),
 309         },
 310         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 311                 .subtype = IFM_50G_CR2,
 312                 .baudrate = IF_Gbps(50ULL),
 313         },
 314         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 315                 .subtype = IFM_50G_KR2,
 316                 .baudrate = IF_Gbps(50ULL),
 317         },
 318         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 319                 .subtype = IFM_50G_SR2,
 320                 .baudrate = IF_Gbps(50ULL),
 321         },
 322         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 323                 .subtype = IFM_50G_LR2,
 324                 .baudrate = IF_Gbps(50ULL),
 325         },
 326         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 327                 .subtype = IFM_50G_LR,
 328                 .baudrate = IF_Gbps(50ULL),
 329         },
 330         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 331                 .subtype = IFM_50G_SR,
 332                 .baudrate = IF_Gbps(50ULL),
 333         },
 334         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 335                 .subtype = IFM_50G_CP,
 336                 .baudrate = IF_Gbps(50ULL),
 337         },
 338         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 339                 .subtype = IFM_50G_FR,
 340                 .baudrate = IF_Gbps(50ULL),
 341         },
 342         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 343                 .subtype = IFM_50G_KR_PAM4,
 344                 .baudrate = IF_Gbps(50ULL),
 345         },
 346         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 347                 .subtype = IFM_100G_CR4,
 348                 .baudrate = IF_Gbps(100ULL),
 349         },
 350         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 351                 .subtype = IFM_100G_KR4,
 352                 .baudrate = IF_Gbps(100ULL),
 353         },
 354         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 355                 .subtype = IFM_100G_LR4,
 356                 .baudrate = IF_Gbps(100ULL),
 357         },
 358         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 359                 .subtype = IFM_100G_SR4,
 360                 .baudrate = IF_Gbps(100ULL),
 361         },
 362         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 363                 .subtype = IFM_100G_SR2,
 364                 .baudrate = IF_Gbps(100ULL),
 365         },
 366         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 367                 .subtype = IFM_100G_CP2,
 368                 .baudrate = IF_Gbps(100ULL),
 369         },
 370         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 371                 .subtype = IFM_100G_KR2_PAM4,
 372                 .baudrate = IF_Gbps(100ULL),
 373         },
 374         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 375                 .subtype = IFM_200G_DR4,
 376                 .baudrate = IF_Gbps(200ULL),
 377         },
 378         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 379                 .subtype = IFM_200G_LR4,
 380                 .baudrate = IF_Gbps(200ULL),
 381         },
 382         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 383                 .subtype = IFM_200G_SR4,
 384                 .baudrate = IF_Gbps(200ULL),
 385         },
 386         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 387                 .subtype = IFM_200G_FR4,
 388                 .baudrate = IF_Gbps(200ULL),
 389         },
 390         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 391                 .subtype = IFM_200G_CR4_PAM4,
 392                 .baudrate = IF_Gbps(200ULL),
 393         },
 394         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 395                 .subtype = IFM_200G_KR4_PAM4,
 396                 .baudrate = IF_Gbps(200ULL),
 397         },
 398 };
 399
 400 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 401
 402 static void
 403 mlx5e_update_carrier(struct mlx5e_priv *priv)
 404 {
 405         struct mlx5_core_dev *mdev = priv->mdev;
 406         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 407         u32 eth_proto_oper;
 408         int error;
 409         u8 port_state;
 410         u8 is_er_type;
 411         u8 i, j;
 412         bool ext;
 413         struct media media_entry = {};
 414
 415         port_state = mlx5_query_vport_state(mdev,
 416             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 417
 418         if (port_state == VPORT_STATE_UP) {
 419                 priv->media_status_last |= IFM_ACTIVE;
 420         } else {
 421                 priv->media_status_last &= ~IFM_ACTIVE;
 422                 priv->media_active_last = IFM_ETHER;
 423                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 424                 return;
 425         }
 426
 427         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 428             MLX5_PTYS_EN, 1);
 429         if (error) {
 430                 priv->media_active_last = IFM_ETHER;
 431                 priv->ifp->if_baudrate = 1;
 432                 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
 433                     error);
 434                 return;
 435         }
 436
 437         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 438         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 439             eth_proto_oper);
 440
 441         i = ilog2(eth_proto_oper);
 442
 443         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 444                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 445                     mlx5e_mode_table[i][j];
 446                 if (media_entry.baudrate != 0)
 447                         break;
 448         }
 449
 450         if (media_entry.subtype == 0) {
 451                 mlx5_en_err(priv->ifp,
 452                     "Could not find operational media subtype\n");
 453                 return;
 454         }
 455
 456         switch (media_entry.subtype) {
 457         case IFM_10G_ER:
 458                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 459                 if (error != 0) {
 460                         mlx5_en_err(priv->ifp,
 461                             "query port pddr failed: %d\n", error);
 462                 }
 463                 if (error != 0 || is_er_type == 0)
 464                         media_entry.subtype = IFM_10G_LR;
 465                 break;
 466         case IFM_40G_LR4:
 467                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 468                 if (error != 0) {
 469                         mlx5_en_err(priv->ifp,
 470                             "query port pddr failed: %d\n", error);
 471                 }
 472                 if (error == 0 && is_er_type != 0)
 473                         media_entry.subtype = IFM_40G_ER4;
 474                 break;
 475         }
 476         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 477         priv->ifp->if_baudrate = media_entry.baudrate;
 478
 479         if_link_state_change(priv->ifp, LINK_STATE_UP);
 480 }
 481
 482 static void
 483 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 484 {
 485         struct mlx5e_priv *priv = dev->if_softc;
 486
 487         ifmr->ifm_status = priv->media_status_last;
 488         ifmr->ifm_active = priv->media_active_last |
 489             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 490             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 491
 492 }
 493
 494 static u32
 495 mlx5e_find_link_mode(u32 subtype, bool ext)
 496 {
 497         u32 i;
 498         u32 j;
 499         u32 link_mode = 0;
 500         u32 speeds_num = 0;
 501         struct media media_entry = {};
 502
 503         switch (subtype) {
 504         case IFM_10G_LR:
 505                 subtype = IFM_10G_ER;
 506                 break;
 507         case IFM_40G_ER4:
 508                 subtype = IFM_40G_LR4;
 509                 break;
 510         }
 511
 512         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 513             MLX5E_LINK_SPEEDS_NUMBER;
 514
 515         for (i = 0; i != speeds_num; i++) {
 516                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 517                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 518                             mlx5e_mode_table[i][j];
 519                         if (media_entry.baudrate == 0)
 520                                 continue;
 521                         if (media_entry.subtype == subtype) {
 522                                 link_mode |= MLX5E_PROT_MASK(i);
 523                         }
 524                 }
 525         }
 526
 527         return (link_mode);
 528 }
 529
 530 static int
 531 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 532 {
 533         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 534             priv->params.rx_pauseframe_control,
 535             priv->params.tx_pauseframe_control,
 536             priv->params.rx_priority_flow_control,
 537             priv->params.tx_priority_flow_control));
 538 }
 539
 540 static int
 541 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 542 {
 543         int error;
 544
 545         if (priv->gone != 0) {
 546                 error = -ENXIO;
 547         } else if (priv->params.rx_pauseframe_control ||
 548             priv->params.tx_pauseframe_control) {
 549                 mlx5_en_err(priv->ifp,
 550                     "Global pauseframes must be disabled before enabling PFC.\n");
 551                 error = -EINVAL;
 552         } else {
 553                 error = mlx5e_set_port_pause_and_pfc(priv);
 554         }
 555         return (error);
 556 }
 557
 558 static int
 559 mlx5e_media_change(struct ifnet *dev)
 560 {
 561         struct mlx5e_priv *priv = dev->if_softc;
 562         struct mlx5_core_dev *mdev = priv->mdev;
 563         u32 eth_proto_cap;
 564         u32 link_mode;
 565         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 566         int was_opened;
 567         int locked;
 568         int error;
 569         bool ext;
 570
 571         locked = PRIV_LOCKED(priv);
 572         if (!locked)
 573                 PRIV_LOCK(priv);
 574
 575         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 576                 error = EINVAL;
 577                 goto done;
 578         }
 579
 580         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 581             MLX5_PTYS_EN, 1);
 582         if (error != 0) {
 583                 mlx5_en_err(dev, "Query port media capability failed\n");
 584                 goto done;
 585         }
 586
 587         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 588         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 589
 590         /* query supported capabilities */
 591         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 592             eth_proto_capability);
 593
 594         /* check for autoselect */
 595         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 596                 link_mode = eth_proto_cap;
 597                 if (link_mode == 0) {
 598                         mlx5_en_err(dev, "Port media capability is zero\n");
 599                         error = EINVAL;
 600                         goto done;
 601                 }
 602         } else {
 603                 link_mode = link_mode & eth_proto_cap;
 604                 if (link_mode == 0) {
 605                         mlx5_en_err(dev, "Not supported link mode requested\n");
 606                         error = EINVAL;
 607                         goto done;
 608                 }
 609         }
 610         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 611                 /* check if PFC is enabled */
 612                 if (priv->params.rx_priority_flow_control ||
 613                     priv->params.tx_priority_flow_control) {
 614                         mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
 615                         error = EINVAL;
 616                         goto done;
 617                 }
 618         }
 619         /* update pauseframe control bits */
 620         priv->params.rx_pauseframe_control =
 621             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 622         priv->params.tx_pauseframe_control =
 623             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 624
 625         /* check if device is opened */
 626         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 627
 628         /* reconfigure the hardware */
 629         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 630         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 631         error = -mlx5e_set_port_pause_and_pfc(priv);
 632         if (was_opened)
 633                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 634
 635 done:
 636         if (!locked)
 637                 PRIV_UNLOCK(priv);
 638         return (error);
 639 }
 640
 641 static void
 642 mlx5e_update_carrier_work(struct work_struct *work)
 643 {
 644         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 645             update_carrier_work);
 646
 647         PRIV_LOCK(priv);
 648         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 649                 mlx5e_update_carrier(priv);
 650         PRIV_UNLOCK(priv);
 651 }
 652
 653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 654         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 655
 656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 657         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 658
 659 static void
 660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 661 {
 662         struct mlx5_core_dev *mdev = priv->mdev;
 663         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 664         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 665         void *out;
 666         void *in;
 667         int err;
 668
 669         /* allocate firmware request structures */
 670         in = mlx5_vzalloc(sz);
 671         out = mlx5_vzalloc(sz);
 672         if (in == NULL || out == NULL)
 673                 goto free_out;
 674
 675         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 676         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 677         if (err != 0)
 678                 goto free_out;
 679
 680         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 681         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 682
 683         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 684         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 685         if (err != 0)
 686                 goto free_out;
 687
 688         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 689
 690         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 691         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 692         if (err != 0)
 693                 goto free_out;
 694
 695         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697 free_out:
 698         /* free firmware request structures */
 699         kvfree(in);
 700         kvfree(out);
 701 }
 702
 703 /*
 704  * This function reads the physical port counters from the firmware
 705  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 706  * macros. The output is converted from big-endian 64-bit values into
 707  * host endian ones and stored in the "priv->stats.pport" structure.
 708  */
 709 static void
 710 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 711 {
 712         struct mlx5_core_dev *mdev = priv->mdev;
 713         struct mlx5e_pport_stats *s = &priv->stats.pport;
 714         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 715         u32 *in;
 716         u32 *out;
 717         const u64 *ptr;
 718         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 719         unsigned x;
 720         unsigned y;
 721         unsigned z;
 722
 723         /* allocate firmware request structures */
 724         in = mlx5_vzalloc(sz);
 725         out = mlx5_vzalloc(sz);
 726         if (in == NULL || out == NULL)
 727                 goto free_out;
 728
 729         /*
 730          * Get pointer to the 64-bit counter set which is located at a
 731          * fixed offset in the output firmware request structure:
 732          */
 733         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 734
 735         MLX5_SET(ppcnt_reg, in, local_port, 1);
 736
 737         /* read IEEE802_3 counter group using predefined counter layout */
 738         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 739         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 740         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 741              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 742                 s->arg[y] = be64toh(ptr[x]);
 743
 744         /* read RFC2819 counter group using predefined counter layout */
 745         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 746         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 747         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 748                 s->arg[y] = be64toh(ptr[x]);
 749
 750         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 751             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 752                 s_debug->arg[y] = be64toh(ptr[x]);
 753
 754         /* read RFC2863 counter group using predefined counter layout */
 755         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 756         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 757         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 758                 s_debug->arg[y] = be64toh(ptr[x]);
 759
 760         /* read physical layer stats counter group using predefined counter layout */
 761         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 762         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 763         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 764                 s_debug->arg[y] = be64toh(ptr[x]);
 765
 766         /* read Extended Ethernet counter group using predefined counter layout */
 767         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 768         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 769         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 770                 s_debug->arg[y] = be64toh(ptr[x]);
 771
 772         /* read Extended Statistical Group */
 773         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 774             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 775             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 776                 /* read Extended Statistical counter group using predefined counter layout */
 777                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 778                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 779
 780                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 781                         s_debug->arg[y] = be64toh(ptr[x]);
 782         }
 783
 784         /* read PCIE counters */
 785         mlx5e_update_pcie_counters(priv);
 786
 787         /* read per-priority counters */
 788         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 789
 790         /* iterate all the priorities */
 791         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 792                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 793                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 794
 795                 /* read per priority stats counter group using predefined counter layout */
 796                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 797                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 798                         s->arg[y] = be64toh(ptr[x]);
 799         }
 800
 801 free_out:
 802         /* free firmware request structures */
 803         kvfree(in);
 804         kvfree(out);
 805 }
 806
 807 static void
 808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 809 {
 810         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 811         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 812
 813         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 814                 return;
 815
 816         MLX5_SET(query_vnic_env_in, in, opcode,
 817             MLX5_CMD_OP_QUERY_VNIC_ENV);
 818         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 819         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 820
 821         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 822                 return;
 823
 824         priv->stats.vport.rx_steer_missed_packets =
 825             MLX5_GET64(query_vnic_env_out, out,
 826             vport_env.nic_receive_steering_discard);
 827 }
 828
 829 /*
 830  * This function is called regularly to collect all statistics
 831  * counters from the firmware. The values can be viewed through the
 832  * sysctl interface. Execution is serialized using the priv's global
 833  * configuration lock.
 834  */
 835 static void
 836 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 837 {
 838         struct mlx5_core_dev *mdev = priv->mdev;
 839         struct mlx5e_vport_stats *s = &priv->stats.vport;
 840         struct mlx5e_sq_stats *sq_stats;
 841         struct buf_ring *sq_br;
 842 #if (__FreeBSD_version < 1100000)
 843         struct ifnet *ifp = priv->ifp;
 844 #endif
 845
 846         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 847         u32 *out;
 848         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 849         u64 tso_packets = 0;
 850         u64 tso_bytes = 0;
 851         u64 tx_queue_dropped = 0;
 852         u64 tx_defragged = 0;
 853         u64 tx_offload_none = 0;
 854         u64 lro_packets = 0;
 855         u64 lro_bytes = 0;
 856         u64 sw_lro_queued = 0;
 857         u64 sw_lro_flushed = 0;
 858         u64 rx_csum_none = 0;
 859         u64 rx_wqe_err = 0;
 860         u64 rx_packets = 0;
 861         u64 rx_bytes = 0;
 862         u32 rx_out_of_buffer = 0;
 863         int error;
 864         int i;
 865         int j;
 866
 867         out = mlx5_vzalloc(outlen);
 868         if (out == NULL)
 869                 goto free_out;
 870
 871         /* Collect firts the SW counters and then HW for consistency */
 872         for (i = 0; i < priv->params.num_channels; i++) {
 873                 struct mlx5e_channel *pch = priv->channel + i;
 874                 struct mlx5e_rq *rq = &pch->rq;
 875                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 876
 877                 /* collect stats from LRO */
 878                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 879                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 880                 sw_lro_queued += rq_stats->sw_lro_queued;
 881                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 882                 lro_packets += rq_stats->lro_packets;
 883                 lro_bytes += rq_stats->lro_bytes;
 884                 rx_csum_none += rq_stats->csum_none;
 885                 rx_wqe_err += rq_stats->wqe_err;
 886                 rx_packets += rq_stats->packets;
 887                 rx_bytes += rq_stats->bytes;
 888
 889                 for (j = 0; j < priv->num_tc; j++) {
 890                         sq_stats = &pch->sq[j].stats;
 891                         sq_br = pch->sq[j].br;
 892
 893                         tso_packets += sq_stats->tso_packets;
 894                         tso_bytes += sq_stats->tso_bytes;
 895                         tx_queue_dropped += sq_stats->dropped;
 896                         if (sq_br != NULL)
 897                                 tx_queue_dropped += sq_br->br_drops;
 898                         tx_defragged += sq_stats->defragged;
 899                         tx_offload_none += sq_stats->csum_offload_none;
 900                 }
 901         }
 902
 903         /* update counters */
 904         s->tso_packets = tso_packets;
 905         s->tso_bytes = tso_bytes;
 906         s->tx_queue_dropped = tx_queue_dropped;
 907         s->tx_defragged = tx_defragged;
 908         s->lro_packets = lro_packets;
 909         s->lro_bytes = lro_bytes;
 910         s->sw_lro_queued = sw_lro_queued;
 911         s->sw_lro_flushed = sw_lro_flushed;
 912         s->rx_csum_none = rx_csum_none;
 913         s->rx_wqe_err = rx_wqe_err;
 914         s->rx_packets = rx_packets;
 915         s->rx_bytes = rx_bytes;
 916
 917         mlx5e_grp_vnic_env_update_stats(priv);
 918
 919         /* HW counters */
 920         memset(in, 0, sizeof(in));
 921
 922         MLX5_SET(query_vport_counter_in, in, opcode,
 923             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 924         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 925         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 926
 927         memset(out, 0, outlen);
 928
 929         /* get number of out-of-buffer drops first */
 930         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 931             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 932             &rx_out_of_buffer) == 0) {
 933                 s->rx_out_of_buffer = rx_out_of_buffer;
 934         }
 935
 936         /* get port statistics */
 937         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 938 #define MLX5_GET_CTR(out, x) \
 939         MLX5_GET64(query_vport_counter_out, out, x)
 940
 941                 s->rx_error_packets =
 942                     MLX5_GET_CTR(out, received_errors.packets);
 943                 s->rx_error_bytes =
 944                     MLX5_GET_CTR(out, received_errors.octets);
 945                 s->tx_error_packets =
 946                     MLX5_GET_CTR(out, transmit_errors.packets);
 947                 s->tx_error_bytes =
 948                     MLX5_GET_CTR(out, transmit_errors.octets);
 949
 950                 s->rx_unicast_packets =
 951                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 952                 s->rx_unicast_bytes =
 953                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 954                 s->tx_unicast_packets =
 955                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 956                 s->tx_unicast_bytes =
 957                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 958
 959                 s->rx_multicast_packets =
 960                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 961                 s->rx_multicast_bytes =
 962                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 963                 s->tx_multicast_packets =
 964                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 965                 s->tx_multicast_bytes =
 966                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 967
 968                 s->rx_broadcast_packets =
 969                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 970                 s->rx_broadcast_bytes =
 971                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 972                 s->tx_broadcast_packets =
 973                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 974                 s->tx_broadcast_bytes =
 975                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 976
 977                 s->tx_packets = s->tx_unicast_packets +
 978                     s->tx_multicast_packets + s->tx_broadcast_packets;
 979                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 980                     s->tx_broadcast_bytes;
 981
 982                 /* Update calculated offload counters */
 983                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 984                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 985         }
 986
 987         /* Get physical port counters */
 988         mlx5e_update_pport_counters(priv);
 989
 990         s->tx_jumbo_packets =
 991             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 992             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 993             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 994             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 995
 996 #if (__FreeBSD_version < 1100000)
 997         /* no get_counters interface in fbsd 10 */
 998         ifp->if_ipackets = s->rx_packets;
 999         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1000             priv->stats.pport.out_of_range_len +
1001             priv->stats.pport.too_long_errors +
1002             priv->stats.pport.check_seq_err +
1003             priv->stats.pport.alignment_err;
1004         ifp->if_iqdrops = s->rx_out_of_buffer;
1005         ifp->if_opackets = s->tx_packets;
1006         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1007         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1008         ifp->if_ibytes = s->rx_bytes;
1009         ifp->if_obytes = s->tx_bytes;
1010         ifp->if_collisions =
1011             priv->stats.pport.collisions;
1012 #endif
1013
1014 free_out:
1015         kvfree(out);
1016
1017         /* Update diagnostics, if any */
1018         if (priv->params_ethtool.diag_pci_enable ||
1019             priv->params_ethtool.diag_general_enable) {
1020                 error = mlx5_core_get_diagnostics_full(mdev,
1021                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1022                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1023                 if (error != 0)
1024                         mlx5_en_err(priv->ifp,
1025                             "Failed reading diagnostics: %d\n", error);
1026         }
1027
1028         /* Update FEC, if any */
1029         error = mlx5e_fec_update(priv);
1030         if (error != 0 && error != EOPNOTSUPP) {
1031                 mlx5_en_err(priv->ifp,
1032                     "Updating FEC failed: %d\n", error);
1033         }
1034 }
1035
1036 static void
1037 mlx5e_update_stats_work(struct work_struct *work)
1038 {
1039         struct mlx5e_priv *priv;
1040
1041         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
1042         PRIV_LOCK(priv);
1043         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1044                 mlx5e_update_stats_locked(priv);
1045         PRIV_UNLOCK(priv);
1046 }
1047
1048 static void
1049 mlx5e_update_stats(void *arg)
1050 {
1051         struct mlx5e_priv *priv = arg;
1052
1053         queue_work(priv->wq, &priv->update_stats_work);
1054
1055         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1056 }
1057
1058 static void
1059 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1060     enum mlx5_dev_event event)
1061 {
1062         switch (event) {
1063         case MLX5_DEV_EVENT_PORT_UP:
1064         case MLX5_DEV_EVENT_PORT_DOWN:
1065                 queue_work(priv->wq, &priv->update_carrier_work);
1066                 break;
1067
1068         default:
1069                 break;
1070         }
1071 }
1072
1073 static void
1074 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1075     enum mlx5_dev_event event, unsigned long param)
1076 {
1077         struct mlx5e_priv *priv = vpriv;
1078
1079         mtx_lock(&priv->async_events_mtx);
1080         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1081                 mlx5e_async_event_sub(priv, event);
1082         mtx_unlock(&priv->async_events_mtx);
1083 }
1084
1085 static void
1086 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1087 {
1088         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1089 }
1090
1091 static void
1092 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1093 {
1094         mtx_lock(&priv->async_events_mtx);
1095         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1096         mtx_unlock(&priv->async_events_mtx);
1097 }
1098
1099 static void mlx5e_calibration_callout(void *arg);
1100 static int mlx5e_calibration_duration = 20;
1101 static int mlx5e_fast_calibration = 1;
1102 static int mlx5e_normal_calibration = 30;
1103
1104 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1105     "MLX5 timestamp calibration parameteres");
1106
1107 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1108     &mlx5e_calibration_duration, 0,
1109     "Duration of initial calibration");
1110 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1111     &mlx5e_fast_calibration, 0,
1112     "Recalibration interval during initial calibration");
1113 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1114     &mlx5e_normal_calibration, 0,
1115     "Recalibration interval during normal operations");
1116
1117 /*
1118  * Ignites the calibration process.
1119  */
1120 static void
1121 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1122 {
1123
1124         if (priv->clbr_done == 0)
1125                 mlx5e_calibration_callout(priv);
1126         else
1127                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1128                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1129                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1130                     priv);
1131 }
1132
1133 static uint64_t
1134 mlx5e_timespec2usec(const struct timespec *ts)
1135 {
1136
1137         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1138 }
1139
1140 static uint64_t
1141 mlx5e_hw_clock(struct mlx5e_priv *priv)
1142 {
1143         struct mlx5_init_seg *iseg;
1144         uint32_t hw_h, hw_h1, hw_l;
1145
1146         iseg = priv->mdev->iseg;
1147         do {
1148                 hw_h = ioread32be(&iseg->internal_timer_h);
1149                 hw_l = ioread32be(&iseg->internal_timer_l);
1150                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1151         } while (hw_h1 != hw_h);
1152         return (((uint64_t)hw_h << 32) | hw_l);
1153 }
1154
1155 /*
1156  * The calibration callout, it runs either in the context of the
1157  * thread which enables calibration, or in callout.  It takes the
1158  * snapshot of system and adapter clocks, then advances the pointers to
1159  * the calibration point to allow rx path to read the consistent data
1160  * lockless.
1161  */
1162 static void
1163 mlx5e_calibration_callout(void *arg)
1164 {
1165         struct mlx5e_priv *priv;
1166         struct mlx5e_clbr_point *next, *curr;
1167         struct timespec ts;
1168         int clbr_curr_next;
1169
1170         priv = arg;
1171         curr = &priv->clbr_points[priv->clbr_curr];
1172         clbr_curr_next = priv->clbr_curr + 1;
1173         if (clbr_curr_next >= nitems(priv->clbr_points))
1174                 clbr_curr_next = 0;
1175         next = &priv->clbr_points[clbr_curr_next];
1176
1177         next->base_prev = curr->base_curr;
1178         next->clbr_hw_prev = curr->clbr_hw_curr;
1179
1180         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1181         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1182             0) {
1183                 if (priv->clbr_done != 0) {
1184                         mlx5_en_err(priv->ifp,
1185                             "HW failed tstmp frozen %#jx %#jx, disabling\n",
1186                              next->clbr_hw_curr, curr->clbr_hw_prev);
1187                         priv->clbr_done = 0;
1188                 }
1189                 atomic_store_rel_int(&curr->clbr_gen, 0);
1190                 return;
1191         }
1192
1193         nanouptime(&ts);
1194         next->base_curr = mlx5e_timespec2usec(&ts);
1195
1196         curr->clbr_gen = 0;
1197         atomic_thread_fence_rel();
1198         priv->clbr_curr = clbr_curr_next;
1199         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1200
1201         if (priv->clbr_done < mlx5e_calibration_duration)
1202                 priv->clbr_done++;
1203         mlx5e_reset_calibration_callout(priv);
1204 }
1205
1206 static const char *mlx5e_rq_stats_desc[] = {
1207         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1208 };
1209
1210 static int
1211 mlx5e_create_rq(struct mlx5e_channel *c,
1212     struct mlx5e_rq_param *param,
1213     struct mlx5e_rq *rq)
1214 {
1215         struct mlx5e_priv *priv = c->priv;
1216         struct mlx5_core_dev *mdev = priv->mdev;
1217         char buffer[16];
1218         void *rqc = param->rqc;
1219         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1220         int wq_sz;
1221         int err;
1222         int i;
1223         u32 nsegs, wqe_sz;
1224
1225         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1226         if (err != 0)
1227                 goto done;
1228
1229         /* Create DMA descriptor TAG */
1230         if ((err = -bus_dma_tag_create(
1231             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1232             1,                          /* any alignment */
1233             0,                          /* no boundary */
1234             BUS_SPACE_MAXADDR,          /* lowaddr */
1235             BUS_SPACE_MAXADDR,          /* highaddr */
1236             NULL, NULL,                 /* filter, filterarg */
1237             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1238             nsegs,                      /* nsegments */
1239             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1240             0,                          /* flags */
1241             NULL, NULL,                 /* lockfunc, lockfuncarg */
1242             &rq->dma_tag)))
1243                 goto done;
1244
1245         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1246             &rq->wq_ctrl);
1247         if (err)
1248                 goto err_free_dma_tag;
1249
1250         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1251
1252         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1253         if (err != 0)
1254                 goto err_rq_wq_destroy;
1255
1256         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1257
1258         err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1259         if (err)
1260                 goto err_rq_wq_destroy;
1261
1262         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1263         for (i = 0; i != wq_sz; i++) {
1264                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1265                 int j;
1266
1267                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1268                 if (err != 0) {
1269                         while (i--)
1270                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1271                         goto err_rq_mbuf_free;
1272                 }
1273
1274                 /* set value for constant fields */
1275                 for (j = 0; j < rq->nsegs; j++)
1276                         wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1277         }
1278
1279         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1280         if (priv->params.rx_cq_moderation_mode < 2) {
1281                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1282         } else {
1283                 void *cqc = container_of(param,
1284                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1285
1286                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1287                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1288                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1289                         break;
1290                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1291                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1292                         break;
1293                 default:
1294                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1295                         break;
1296                 }
1297         }
1298
1299         rq->ifp = priv->ifp;
1300         rq->channel = c;
1301         rq->ix = c->ix;
1302
1303         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1304         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1305             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1306             rq->stats.arg);
1307         return (0);
1308
1309 err_rq_mbuf_free:
1310         free(rq->mbuf, M_MLX5EN);
1311         tcp_lro_free(&rq->lro);
1312 err_rq_wq_destroy:
1313         mlx5_wq_destroy(&rq->wq_ctrl);
1314 err_free_dma_tag:
1315         bus_dma_tag_destroy(rq->dma_tag);
1316 done:
1317         return (err);
1318 }
1319
1320 static void
1321 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1322 {
1323         int wq_sz;
1324         int i;
1325
1326         /* destroy all sysctl nodes */
1327         sysctl_ctx_free(&rq->stats.ctx);
1328
1329         /* free leftover LRO packets, if any */
1330         tcp_lro_free(&rq->lro);
1331
1332         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1333         for (i = 0; i != wq_sz; i++) {
1334                 if (rq->mbuf[i].mbuf != NULL) {
1335                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1336                         m_freem(rq->mbuf[i].mbuf);
1337                 }
1338                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1339         }
1340         free(rq->mbuf, M_MLX5EN);
1341         mlx5_wq_destroy(&rq->wq_ctrl);
1342         bus_dma_tag_destroy(rq->dma_tag);
1343 }
1344
1345 static int
1346 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1347 {
1348         struct mlx5e_channel *c = rq->channel;
1349         struct mlx5e_priv *priv = c->priv;
1350         struct mlx5_core_dev *mdev = priv->mdev;
1351
1352         void *in;
1353         void *rqc;
1354         void *wq;
1355         int inlen;
1356         int err;
1357
1358         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1359             sizeof(u64) * rq->wq_ctrl.buf.npages;
1360         in = mlx5_vzalloc(inlen);
1361         if (in == NULL)
1362                 return (-ENOMEM);
1363
1364         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1365         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1366
1367         memcpy(rqc, param->rqc, sizeof(param->rqc));
1368
1369         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1370         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1371         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1372         if (priv->counter_set_id >= 0)
1373                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1374         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1375             PAGE_SHIFT);
1376         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1377
1378         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1379             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1380
1381         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1382
1383         kvfree(in);
1384
1385         return (err);
1386 }
1387
1388 static int
1389 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1390 {
1391         struct mlx5e_channel *c = rq->channel;
1392         struct mlx5e_priv *priv = c->priv;
1393         struct mlx5_core_dev *mdev = priv->mdev;
1394
1395         void *in;
1396         void *rqc;
1397         int inlen;
1398         int err;
1399
1400         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1401         in = mlx5_vzalloc(inlen);
1402         if (in == NULL)
1403                 return (-ENOMEM);
1404
1405         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1406
1407         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1408         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1409         MLX5_SET(rqc, rqc, state, next_state);
1410
1411         err = mlx5_core_modify_rq(mdev, in, inlen);
1412
1413         kvfree(in);
1414
1415         return (err);
1416 }
1417
1418 static void
1419 mlx5e_disable_rq(struct mlx5e_rq *rq)
1420 {
1421         struct mlx5e_channel *c = rq->channel;
1422         struct mlx5e_priv *priv = c->priv;
1423         struct mlx5_core_dev *mdev = priv->mdev;
1424
1425         mlx5_core_destroy_rq(mdev, rq->rqn);
1426 }
1427
1428 static int
1429 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1430 {
1431         struct mlx5e_channel *c = rq->channel;
1432         struct mlx5e_priv *priv = c->priv;
1433         struct mlx5_wq_ll *wq = &rq->wq;
1434         int i;
1435
1436         for (i = 0; i < 1000; i++) {
1437                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1438                         return (0);
1439
1440                 msleep(4);
1441         }
1442         return (-ETIMEDOUT);
1443 }
1444
1445 static int
1446 mlx5e_open_rq(struct mlx5e_channel *c,
1447     struct mlx5e_rq_param *param,
1448     struct mlx5e_rq *rq)
1449 {
1450         int err;
1451
1452         err = mlx5e_create_rq(c, param, rq);
1453         if (err)
1454                 return (err);
1455
1456         err = mlx5e_enable_rq(rq, param);
1457         if (err)
1458                 goto err_destroy_rq;
1459
1460         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1461         if (err)
1462                 goto err_disable_rq;
1463
1464         c->rq.enabled = 1;
1465
1466         return (0);
1467
1468 err_disable_rq:
1469         mlx5e_disable_rq(rq);
1470 err_destroy_rq:
1471         mlx5e_destroy_rq(rq);
1472
1473         return (err);
1474 }
1475
1476 static void
1477 mlx5e_close_rq(struct mlx5e_rq *rq)
1478 {
1479         mtx_lock(&rq->mtx);
1480         rq->enabled = 0;
1481         callout_stop(&rq->watchdog);
1482         mtx_unlock(&rq->mtx);
1483
1484         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1485 }
1486
1487 static void
1488 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1489 {
1490
1491         mlx5e_disable_rq(rq);
1492         mlx5e_close_cq(&rq->cq);
1493         cancel_work_sync(&rq->dim.work);
1494         mlx5e_destroy_rq(rq);
1495 }
1496
1497 void
1498 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1499 {
1500         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1501         int x;
1502
1503         for (x = 0; x != wq_sz; x++) {
1504                 if (sq->mbuf[x].mbuf != NULL) {
1505                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1506                         m_freem(sq->mbuf[x].mbuf);
1507                 }
1508                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1509         }
1510         free(sq->mbuf, M_MLX5EN);
1511 }
1512
1513 int
1514 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1515 {
1516         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1517         int err;
1518         int x;
1519
1520         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1521
1522         /* Create DMA descriptor MAPs */
1523         for (x = 0; x != wq_sz; x++) {
1524                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1525                 if (err != 0) {
1526                         while (x--)
1527                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1528                         free(sq->mbuf, M_MLX5EN);
1529                         return (err);
1530                 }
1531         }
1532         return (0);
1533 }
1534
1535 static const char *mlx5e_sq_stats_desc[] = {
1536         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1537 };
1538
1539 void
1540 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1541 {
1542         sq->max_inline = sq->priv->params.tx_max_inline;
1543         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1544
1545         /*
1546          * Check if trust state is DSCP or if inline mode is NONE which
1547          * indicates CX-5 or newer hardware.
1548          */
1549         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1550             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1551                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1552                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1553                 else
1554                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1555         } else {
1556                 sq->min_insert_caps = 0;
1557         }
1558 }
1559
1560 static void
1561 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1562 {
1563         int i;
1564
1565         for (i = 0; i != priv->num_tc; i++) {
1566                 mtx_lock(&c->sq[i].lock);
1567                 mlx5e_update_sq_inline(&c->sq[i]);
1568                 mtx_unlock(&c->sq[i].lock);
1569         }
1570 }
1571
1572 void
1573 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1574 {
1575         int i;
1576
1577         /* check if channels are closed */
1578         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1579                 return;
1580
1581         for (i = 0; i < priv->params.num_channels; i++)
1582                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1583 }
1584
1585 static int
1586 mlx5e_create_sq(struct mlx5e_channel *c,
1587     int tc,
1588     struct mlx5e_sq_param *param,
1589     struct mlx5e_sq *sq)
1590 {
1591         struct mlx5e_priv *priv = c->priv;
1592         struct mlx5_core_dev *mdev = priv->mdev;
1593         char buffer[16];
1594         void *sqc = param->sqc;
1595         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1596         int err;
1597
1598         /* Create DMA descriptor TAG */
1599         if ((err = -bus_dma_tag_create(
1600             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1601             1,                          /* any alignment */
1602             0,                          /* no boundary */
1603             BUS_SPACE_MAXADDR,          /* lowaddr */
1604             BUS_SPACE_MAXADDR,          /* highaddr */
1605             NULL, NULL,                 /* filter, filterarg */
1606             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1607             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1608             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1609             0,                          /* flags */
1610             NULL, NULL,                 /* lockfunc, lockfuncarg */
1611             &sq->dma_tag)))
1612                 goto done;
1613
1614         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1615         if (err)
1616                 goto err_free_dma_tag;
1617
1618         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1619             &sq->wq_ctrl);
1620         if (err)
1621                 goto err_unmap_free_uar;
1622
1623         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1624         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1625
1626         err = mlx5e_alloc_sq_db(sq);
1627         if (err)
1628                 goto err_sq_wq_destroy;
1629
1630         sq->mkey_be = cpu_to_be32(priv->mr.key);
1631         sq->ifp = priv->ifp;
1632         sq->priv = priv;
1633         sq->tc = tc;
1634
1635         mlx5e_update_sq_inline(sq);
1636
1637         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1638         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1639             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1640             sq->stats.arg);
1641
1642         return (0);
1643
1644 err_sq_wq_destroy:
1645         mlx5_wq_destroy(&sq->wq_ctrl);
1646
1647 err_unmap_free_uar:
1648         mlx5_unmap_free_uar(mdev, &sq->uar);
1649
1650 err_free_dma_tag:
1651         bus_dma_tag_destroy(sq->dma_tag);
1652 done:
1653         return (err);
1654 }
1655
1656 static void
1657 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1658 {
1659         /* destroy all sysctl nodes */
1660         sysctl_ctx_free(&sq->stats.ctx);
1661
1662         mlx5e_free_sq_db(sq);
1663         mlx5_wq_destroy(&sq->wq_ctrl);
1664         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1665         bus_dma_tag_destroy(sq->dma_tag);
1666 }
1667
1668 int
1669 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1670     int tis_num)
1671 {
1672         void *in;
1673         void *sqc;
1674         void *wq;
1675         int inlen;
1676         int err;
1677
1678         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1679             sizeof(u64) * sq->wq_ctrl.buf.npages;
1680         in = mlx5_vzalloc(inlen);
1681         if (in == NULL)
1682                 return (-ENOMEM);
1683
1684         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1685         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1686
1687         memcpy(sqc, param->sqc, sizeof(param->sqc));
1688
1689         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1690         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1691         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1692         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1693         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1694
1695         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1696         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1697         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1698             PAGE_SHIFT);
1699         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1700
1701         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1702             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1703
1704         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1705
1706         kvfree(in);
1707
1708         return (err);
1709 }
1710
1711 int
1712 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1713 {
1714         void *in;
1715         void *sqc;
1716         int inlen;
1717         int err;
1718
1719         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1720         in = mlx5_vzalloc(inlen);
1721         if (in == NULL)
1722                 return (-ENOMEM);
1723
1724         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1725
1726         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1727         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1728         MLX5_SET(sqc, sqc, state, next_state);
1729
1730         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1731
1732         kvfree(in);
1733
1734         return (err);
1735 }
1736
1737 void
1738 mlx5e_disable_sq(struct mlx5e_sq *sq)
1739 {
1740
1741         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1742 }
1743
1744 static int
1745 mlx5e_open_sq(struct mlx5e_channel *c,
1746     int tc,
1747     struct mlx5e_sq_param *param,
1748     struct mlx5e_sq *sq)
1749 {
1750         int err;
1751
1752         sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1753
1754         /* ensure the TX completion event factor is not zero */
1755         if (sq->cev_factor == 0)
1756                 sq->cev_factor = 1;
1757
1758         err = mlx5e_create_sq(c, tc, param, sq);
1759         if (err)
1760                 return (err);
1761
1762         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1763         if (err)
1764                 goto err_destroy_sq;
1765
1766         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1767         if (err)
1768                 goto err_disable_sq;
1769
1770         WRITE_ONCE(sq->running, 1);
1771
1772         return (0);
1773
1774 err_disable_sq:
1775         mlx5e_disable_sq(sq);
1776 err_destroy_sq:
1777         mlx5e_destroy_sq(sq);
1778
1779         return (err);
1780 }
1781
1782 static void
1783 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1784 {
1785         /* fill up remainder with NOPs */
1786         while (sq->cev_counter != 0) {
1787                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1788                         if (can_sleep != 0) {
1789                                 mtx_unlock(&sq->lock);
1790                                 msleep(4);
1791                                 mtx_lock(&sq->lock);
1792                         } else {
1793                                 goto done;
1794                         }
1795                 }
1796                 /* send a single NOP */
1797                 mlx5e_send_nop(sq, 1);
1798                 atomic_thread_fence_rel();
1799         }
1800 done:
1801         /* Check if we need to write the doorbell */
1802         if (likely(sq->doorbell.d64 != 0)) {
1803                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1804                 sq->doorbell.d64 = 0;
1805         }
1806 }
1807
1808 void
1809 mlx5e_sq_cev_timeout(void *arg)
1810 {
1811         struct mlx5e_sq *sq = arg;
1812
1813         mtx_assert(&sq->lock, MA_OWNED);
1814
1815         /* check next state */
1816         switch (sq->cev_next_state) {
1817         case MLX5E_CEV_STATE_SEND_NOPS:
1818                 /* fill TX ring with NOPs, if any */
1819                 mlx5e_sq_send_nops_locked(sq, 0);
1820
1821                 /* check if completed */
1822                 if (sq->cev_counter == 0) {
1823                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1824                         return;
1825                 }
1826                 break;
1827         default:
1828                 /* send NOPs on next timeout */
1829                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1830                 break;
1831         }
1832
1833         /* restart timer */
1834         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1835 }
1836
1837 void
1838 mlx5e_drain_sq(struct mlx5e_sq *sq)
1839 {
1840         int error;
1841         struct mlx5_core_dev *mdev= sq->priv->mdev;
1842
1843         /*
1844          * Check if already stopped.
1845          *
1846          * NOTE: Serialization of this function is managed by the
1847          * caller ensuring the priv's state lock is locked or in case
1848          * of rate limit support, a single thread manages drain and
1849          * resume of SQs. The "running" variable can therefore safely
1850          * be read without any locks.
1851          */
1852         if (READ_ONCE(sq->running) == 0)
1853                 return;
1854
1855         /* don't put more packets into the SQ */
1856         WRITE_ONCE(sq->running, 0);
1857
1858         /* serialize access to DMA rings */
1859         mtx_lock(&sq->lock);
1860
1861         /* teardown event factor timer, if any */
1862         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1863         callout_stop(&sq->cev_callout);
1864
1865         /* send dummy NOPs in order to flush the transmit ring */
1866         mlx5e_sq_send_nops_locked(sq, 1);
1867         mtx_unlock(&sq->lock);
1868
1869         /* wait till SQ is empty or link is down */
1870         mtx_lock(&sq->lock);
1871         while (sq->cc != sq->pc &&
1872             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1873             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1874                 mtx_unlock(&sq->lock);
1875                 msleep(1);
1876                 sq->cq.mcq.comp(&sq->cq.mcq);
1877                 mtx_lock(&sq->lock);
1878         }
1879         mtx_unlock(&sq->lock);
1880
1881         /* error out remaining requests */
1882         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1883         if (error != 0) {
1884                 mlx5_en_err(sq->ifp,
1885                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1886         }
1887
1888         /* wait till SQ is empty */
1889         mtx_lock(&sq->lock);
1890         while (sq->cc != sq->pc &&
1891                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1892                 mtx_unlock(&sq->lock);
1893                 msleep(1);
1894                 sq->cq.mcq.comp(&sq->cq.mcq);
1895                 mtx_lock(&sq->lock);
1896         }
1897         mtx_unlock(&sq->lock);
1898 }
1899
1900 static void
1901 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1902 {
1903
1904         mlx5e_drain_sq(sq);
1905         mlx5e_disable_sq(sq);
1906         mlx5e_destroy_sq(sq);
1907 }
1908
1909 static int
1910 mlx5e_create_cq(struct mlx5e_priv *priv,
1911     struct mlx5e_cq_param *param,
1912     struct mlx5e_cq *cq,
1913     mlx5e_cq_comp_t *comp,
1914     int eq_ix)
1915 {
1916         struct mlx5_core_dev *mdev = priv->mdev;
1917         struct mlx5_core_cq *mcq = &cq->mcq;
1918         int eqn_not_used;
1919         int irqn;
1920         int err;
1921         u32 i;
1922
1923         param->wq.buf_numa_node = 0;
1924         param->wq.db_numa_node = 0;
1925
1926         err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1927         if (err)
1928                 return (err);
1929
1930         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1931             &cq->wq_ctrl);
1932         if (err)
1933                 return (err);
1934
1935         mcq->cqe_sz = 64;
1936         mcq->set_ci_db = cq->wq_ctrl.db.db;
1937         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1938         *mcq->set_ci_db = 0;
1939         *mcq->arm_db = 0;
1940         mcq->vector = eq_ix;
1941         mcq->comp = comp;
1942         mcq->event = mlx5e_cq_error_event;
1943         mcq->irqn = irqn;
1944         mcq->uar = &priv->cq_uar;
1945
1946         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1947                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1948
1949                 cqe->op_own = 0xf1;
1950         }
1951
1952         cq->priv = priv;
1953
1954         return (0);
1955 }
1956
1957 static void
1958 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1959 {
1960         mlx5_wq_destroy(&cq->wq_ctrl);
1961 }
1962
1963 static int
1964 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1965 {
1966         struct mlx5_core_cq *mcq = &cq->mcq;
1967         void *in;
1968         void *cqc;
1969         int inlen;
1970         int irqn_not_used;
1971         int eqn;
1972         int err;
1973
1974         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1975             sizeof(u64) * cq->wq_ctrl.buf.npages;
1976         in = mlx5_vzalloc(inlen);
1977         if (in == NULL)
1978                 return (-ENOMEM);
1979
1980         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1981
1982         memcpy(cqc, param->cqc, sizeof(param->cqc));
1983
1984         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1985             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1986
1987         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1988
1989         MLX5_SET(cqc, cqc, c_eqn, eqn);
1990         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1991         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1992             PAGE_SHIFT);
1993         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1994
1995         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1996
1997         kvfree(in);
1998
1999         if (err)
2000                 return (err);
2001
2002         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2003
2004         return (0);
2005 }
2006
2007 static void
2008 mlx5e_disable_cq(struct mlx5e_cq *cq)
2009 {
2010
2011         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2012 }
2013
2014 int
2015 mlx5e_open_cq(struct mlx5e_priv *priv,
2016     struct mlx5e_cq_param *param,
2017     struct mlx5e_cq *cq,
2018     mlx5e_cq_comp_t *comp,
2019     int eq_ix)
2020 {
2021         int err;
2022
2023         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2024         if (err)
2025                 return (err);
2026
2027         err = mlx5e_enable_cq(cq, param, eq_ix);
2028         if (err)
2029                 goto err_destroy_cq;
2030
2031         return (0);
2032
2033 err_destroy_cq:
2034         mlx5e_destroy_cq(cq);
2035
2036         return (err);
2037 }
2038
2039 void
2040 mlx5e_close_cq(struct mlx5e_cq *cq)
2041 {
2042         mlx5e_disable_cq(cq);
2043         mlx5e_destroy_cq(cq);
2044 }
2045
2046 static int
2047 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2048     struct mlx5e_channel_param *cparam)
2049 {
2050         int err;
2051         int tc;
2052
2053         for (tc = 0; tc < c->priv->num_tc; tc++) {
2054                 /* open completion queue */
2055                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2056                     &mlx5e_tx_cq_comp, c->ix);
2057                 if (err)
2058                         goto err_close_tx_cqs;
2059         }
2060         return (0);
2061
2062 err_close_tx_cqs:
2063         for (tc--; tc >= 0; tc--)
2064                 mlx5e_close_cq(&c->sq[tc].cq);
2065
2066         return (err);
2067 }
2068
2069 static void
2070 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2071 {
2072         int tc;
2073
2074         for (tc = 0; tc < c->priv->num_tc; tc++)
2075                 mlx5e_close_cq(&c->sq[tc].cq);
2076 }
2077
2078 static int
2079 mlx5e_open_sqs(struct mlx5e_channel *c,
2080     struct mlx5e_channel_param *cparam)
2081 {
2082         int err;
2083         int tc;
2084
2085         for (tc = 0; tc < c->priv->num_tc; tc++) {
2086                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2087                 if (err)
2088                         goto err_close_sqs;
2089         }
2090
2091         return (0);
2092
2093 err_close_sqs:
2094         for (tc--; tc >= 0; tc--)
2095                 mlx5e_close_sq_wait(&c->sq[tc]);
2096
2097         return (err);
2098 }
2099
2100 static void
2101 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2102 {
2103         int tc;
2104
2105         for (tc = 0; tc < c->priv->num_tc; tc++)
2106                 mlx5e_close_sq_wait(&c->sq[tc]);
2107 }
2108
2109 static void
2110 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2111 {
2112         int tc;
2113
2114         /* setup priv and channel number */
2115         c->priv = priv;
2116         c->ix = ix;
2117
2118         /* setup send tag */
2119         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2120         m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2121
2122         init_completion(&c->completion);
2123
2124         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2125
2126         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2127
2128         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2129                 struct mlx5e_sq *sq = c->sq + tc;
2130
2131                 mtx_init(&sq->lock, "mlx5tx",
2132                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2133                 mtx_init(&sq->comp_lock, "mlx5comp",
2134                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2135
2136                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2137         }
2138 }
2139
2140 static void
2141 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2142 {
2143
2144         m_snd_tag_rele(&c->tag.m_snd_tag);
2145         wait_for_completion(&c->completion);
2146 }
2147
2148 static void
2149 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2150 {
2151         uint32_t x;
2152
2153         for (x = 0; x != channels; x++)
2154                 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2155 }
2156
2157 static void
2158 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2159 {
2160         int tc;
2161
2162         callout_drain(&c->rq.watchdog);
2163
2164         mtx_destroy(&c->rq.mtx);
2165
2166         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2167                 callout_drain(&c->sq[tc].cev_callout);
2168                 mtx_destroy(&c->sq[tc].lock);
2169                 mtx_destroy(&c->sq[tc].comp_lock);
2170         }
2171 }
2172
2173 static int
2174 mlx5e_open_channel(struct mlx5e_priv *priv,
2175     struct mlx5e_channel_param *cparam,
2176     struct mlx5e_channel *c)
2177 {
2178         int i, err;
2179
2180         /* zero non-persistant data */
2181         MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2182         for (i = 0; i != priv->num_tc; i++)
2183                 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2184
2185         /* open transmit completion queue */
2186         err = mlx5e_open_tx_cqs(c, cparam);
2187         if (err)
2188                 goto err_free;
2189
2190         /* open receive completion queue */
2191         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2192             &mlx5e_rx_cq_comp, c->ix);
2193         if (err)
2194                 goto err_close_tx_cqs;
2195
2196         err = mlx5e_open_sqs(c, cparam);
2197         if (err)
2198                 goto err_close_rx_cq;
2199
2200         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2201         if (err)
2202                 goto err_close_sqs;
2203
2204         /* poll receive queue initially */
2205         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2206
2207         return (0);
2208
2209 err_close_sqs:
2210         mlx5e_close_sqs_wait(c);
2211
2212 err_close_rx_cq:
2213         mlx5e_close_cq(&c->rq.cq);
2214
2215 err_close_tx_cqs:
2216         mlx5e_close_tx_cqs(c);
2217
2218 err_free:
2219         return (err);
2220 }
2221
2222 static void
2223 mlx5e_close_channel(struct mlx5e_channel *c)
2224 {
2225         mlx5e_close_rq(&c->rq);
2226 }
2227
2228 static void
2229 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2230 {
2231         mlx5e_close_rq_wait(&c->rq);
2232         mlx5e_close_sqs_wait(c);
2233         mlx5e_close_tx_cqs(c);
2234 }
2235
2236 static int
2237 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2238 {
2239         u32 r, n;
2240
2241         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2242             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2243         if (r > MJUM16BYTES)
2244                 return (-ENOMEM);
2245
2246         if (r > MJUM9BYTES)
2247                 r = MJUM16BYTES;
2248         else if (r > MJUMPAGESIZE)
2249                 r = MJUM9BYTES;
2250         else if (r > MCLBYTES)
2251                 r = MJUMPAGESIZE;
2252         else
2253                 r = MCLBYTES;
2254
2255         /*
2256          * n + 1 must be a power of two, because stride size must be.
2257          * Stride size is 16 * (n + 1), as the first segment is
2258          * control.
2259          */
2260         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2261                 ;
2262
2263         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2264                 return (-ENOMEM);
2265
2266         *wqe_sz = r;
2267         *nsegs = n;
2268         return (0);
2269 }
2270
2271 static void
2272 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2273     struct mlx5e_rq_param *param)
2274 {
2275         void *rqc = param->rqc;
2276         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2277         u32 wqe_sz, nsegs;
2278
2279         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2280         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2281         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2282         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2283             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2284         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2285         MLX5_SET(wq, wq, pd, priv->pdn);
2286
2287         param->wq.buf_numa_node = 0;
2288         param->wq.db_numa_node = 0;
2289         param->wq.linear = 1;
2290 }
2291
2292 static void
2293 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2294     struct mlx5e_sq_param *param)
2295 {
2296         void *sqc = param->sqc;
2297         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2298
2299         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2300         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2301         MLX5_SET(wq, wq, pd, priv->pdn);
2302
2303         param->wq.buf_numa_node = 0;
2304         param->wq.db_numa_node = 0;
2305         param->wq.linear = 1;
2306 }
2307
2308 static void
2309 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2310     struct mlx5e_cq_param *param)
2311 {
2312         void *cqc = param->cqc;
2313
2314         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2315 }
2316
2317 static void
2318 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2319 {
2320
2321         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2322
2323         /* apply LRO restrictions */
2324         if (priv->params.hw_lro_en &&
2325             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2326                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2327         }
2328 }
2329
2330 static void
2331 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2332     struct mlx5e_cq_param *param)
2333 {
2334         struct net_dim_cq_moder curr;
2335         void *cqc = param->cqc;
2336
2337         /*
2338          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2339          * format is more beneficial for FreeBSD use case.
2340          *
2341          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2342          * in mlx5e_decompress_cqe.
2343          */
2344         if (priv->params.cqe_zipping_en) {
2345                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2346                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2347         }
2348
2349         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2350
2351         switch (priv->params.rx_cq_moderation_mode) {
2352         case 0:
2353                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2354                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2355                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2356                 break;
2357         case 1:
2358                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2359                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2360                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2361                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2362                 else
2363                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2364                 break;
2365         case 2:
2366                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2367                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2368                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2369                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2370                 break;
2371         case 3:
2372                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2373                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2374                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2375                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2376                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2377                 else
2378                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2379                 break;
2380         default:
2381                 break;
2382         }
2383
2384         mlx5e_dim_build_cq_param(priv, param);
2385
2386         mlx5e_build_common_cq_param(priv, param);
2387 }
2388
2389 static void
2390 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2391     struct mlx5e_cq_param *param)
2392 {
2393         void *cqc = param->cqc;
2394
2395         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2396         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2397         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2398
2399         switch (priv->params.tx_cq_moderation_mode) {
2400         case 0:
2401                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2402                 break;
2403         default:
2404                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2405                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2406                 else
2407                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2408                 break;
2409         }
2410
2411         mlx5e_build_common_cq_param(priv, param);
2412 }
2413
2414 static void
2415 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2416     struct mlx5e_channel_param *cparam)
2417 {
2418         memset(cparam, 0, sizeof(*cparam));
2419
2420         mlx5e_build_rq_param(priv, &cparam->rq);
2421         mlx5e_build_sq_param(priv, &cparam->sq);
2422         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2423         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2424 }
2425
2426 static int
2427 mlx5e_open_channels(struct mlx5e_priv *priv)
2428 {
2429         struct mlx5e_channel_param *cparam;
2430         int err;
2431         int i;
2432         int j;
2433
2434         cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2435
2436         mlx5e_build_channel_param(priv, cparam);
2437         for (i = 0; i < priv->params.num_channels; i++) {
2438                 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2439                 if (err)
2440                         goto err_close_channels;
2441         }
2442
2443         for (j = 0; j < priv->params.num_channels; j++) {
2444                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2445                 if (err)
2446                         goto err_close_channels;
2447         }
2448         free(cparam, M_MLX5EN);
2449         return (0);
2450
2451 err_close_channels:
2452         while (i--) {
2453                 mlx5e_close_channel(&priv->channel[i]);
2454                 mlx5e_close_channel_wait(&priv->channel[i]);
2455         }
2456         free(cparam, M_MLX5EN);
2457         return (err);
2458 }
2459
2460 static void
2461 mlx5e_close_channels(struct mlx5e_priv *priv)
2462 {
2463         int i;
2464
2465         for (i = 0; i < priv->params.num_channels; i++)
2466                 mlx5e_close_channel(&priv->channel[i]);
2467         for (i = 0; i < priv->params.num_channels; i++)
2468                 mlx5e_close_channel_wait(&priv->channel[i]);
2469 }
2470
2471 static int
2472 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2473 {
2474
2475         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2476                 uint8_t cq_mode;
2477
2478                 switch (priv->params.tx_cq_moderation_mode) {
2479                 case 0:
2480                 case 2:
2481                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2482                         break;
2483                 default:
2484                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2485                         break;
2486                 }
2487
2488                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2489                     priv->params.tx_cq_moderation_usec,
2490                     priv->params.tx_cq_moderation_pkts,
2491                     cq_mode));
2492         }
2493
2494         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2495             priv->params.tx_cq_moderation_usec,
2496             priv->params.tx_cq_moderation_pkts));
2497 }
2498
2499 static int
2500 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2501 {
2502
2503         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2504                 uint8_t cq_mode;
2505                 uint8_t dim_mode;
2506                 int retval;
2507
2508                 switch (priv->params.rx_cq_moderation_mode) {
2509                 case 0:
2510                 case 2:
2511                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2512                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2513                         break;
2514                 default:
2515                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2516                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2517                         break;
2518                 }
2519
2520                 /* tear down dynamic interrupt moderation */
2521                 mtx_lock(&rq->mtx);
2522                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2523                 mtx_unlock(&rq->mtx);
2524
2525                 /* wait for dynamic interrupt moderation work task, if any */
2526                 cancel_work_sync(&rq->dim.work);
2527
2528                 if (priv->params.rx_cq_moderation_mode >= 2) {
2529                         struct net_dim_cq_moder curr;
2530
2531                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2532
2533                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2534                             curr.usec, curr.pkts, cq_mode);
2535
2536                         /* set dynamic interrupt moderation mode and zero defaults */
2537                         mtx_lock(&rq->mtx);
2538                         rq->dim.mode = dim_mode;
2539                         rq->dim.state = 0;
2540                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2541                         mtx_unlock(&rq->mtx);
2542                 } else {
2543                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2544                             priv->params.rx_cq_moderation_usec,
2545                             priv->params.rx_cq_moderation_pkts,
2546                             cq_mode);
2547                 }
2548                 return (retval);
2549         }
2550
2551         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2552             priv->params.rx_cq_moderation_usec,
2553             priv->params.rx_cq_moderation_pkts));
2554 }
2555
2556 static int
2557 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2558 {
2559         int err;
2560         int i;
2561
2562         err = mlx5e_refresh_rq_params(priv, &c->rq);
2563         if (err)
2564                 goto done;
2565
2566         for (i = 0; i != priv->num_tc; i++) {
2567                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2568                 if (err)
2569                         goto done;
2570         }
2571 done:
2572         return (err);
2573 }
2574
2575 int
2576 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2577 {
2578         int i;
2579
2580         /* check if channels are closed */
2581         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2582                 return (EINVAL);
2583
2584         for (i = 0; i < priv->params.num_channels; i++) {
2585                 int err;
2586
2587                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2588                 if (err)
2589                         return (err);
2590         }
2591         return (0);
2592 }
2593
2594 static int
2595 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2596 {
2597         struct mlx5_core_dev *mdev = priv->mdev;
2598         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2599         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2600
2601         memset(in, 0, sizeof(in));
2602
2603         MLX5_SET(tisc, tisc, prio, tc);
2604         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2605
2606         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2607 }
2608
2609 static void
2610 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2611 {
2612         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2613 }
2614
2615 static int
2616 mlx5e_open_tises(struct mlx5e_priv *priv)
2617 {
2618         int num_tc = priv->num_tc;
2619         int err;
2620         int tc;
2621
2622         for (tc = 0; tc < num_tc; tc++) {
2623                 err = mlx5e_open_tis(priv, tc);
2624                 if (err)
2625                         goto err_close_tises;
2626         }
2627
2628         return (0);
2629
2630 err_close_tises:
2631         for (tc--; tc >= 0; tc--)
2632                 mlx5e_close_tis(priv, tc);
2633
2634         return (err);
2635 }
2636
2637 static void
2638 mlx5e_close_tises(struct mlx5e_priv *priv)
2639 {
2640         int num_tc = priv->num_tc;
2641         int tc;
2642
2643         for (tc = 0; tc < num_tc; tc++)
2644                 mlx5e_close_tis(priv, tc);
2645 }
2646
2647 static int
2648 mlx5e_open_rqt(struct mlx5e_priv *priv)
2649 {
2650         struct mlx5_core_dev *mdev = priv->mdev;
2651         u32 *in;
2652         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2653         void *rqtc;
2654         int inlen;
2655         int err;
2656         int sz;
2657         int i;
2658
2659         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2660
2661         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2662         in = mlx5_vzalloc(inlen);
2663         if (in == NULL)
2664                 return (-ENOMEM);
2665         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2666
2667         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2668         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2669
2670         for (i = 0; i < sz; i++) {
2671                 int ix = i;
2672 #ifdef RSS
2673                 ix = rss_get_indirection_to_bucket(ix);
2674 #endif
2675                 /* ensure we don't overflow */
2676                 ix %= priv->params.num_channels;
2677
2678                 /* apply receive side scaling stride, if any */
2679                 ix -= ix % (int)priv->params.channels_rsss;
2680
2681                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2682         }
2683
2684         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2685
2686         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2687         if (!err)
2688                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2689
2690         kvfree(in);
2691
2692         return (err);
2693 }
2694
2695 static void
2696 mlx5e_close_rqt(struct mlx5e_priv *priv)
2697 {
2698         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2699         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2700
2701         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2702         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2703
2704         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2705 }
2706
2707 static void
2708 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2709 {
2710         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2711         __be32 *hkey;
2712
2713         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2714
2715 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2716
2717 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2718                           MLX5_HASH_FIELD_SEL_DST_IP)
2719
2720 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2721                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2722                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2723                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2724
2725 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2726                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2727                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2728
2729         if (priv->params.hw_lro_en) {
2730                 MLX5_SET(tirc, tirc, lro_enable_mask,
2731                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2732                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2733                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2734                     (priv->params.lro_wqe_sz -
2735                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2736                 /* TODO: add the option to choose timer value dynamically */
2737                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2738                     MLX5_CAP_ETH(priv->mdev,
2739                     lro_timer_supported_periods[2]));
2740         }
2741
2742         /* setup parameters for hashing TIR type, if any */
2743         switch (tt) {
2744         case MLX5E_TT_ANY:
2745                 MLX5_SET(tirc, tirc, disp_type,
2746                     MLX5_TIRC_DISP_TYPE_DIRECT);
2747                 MLX5_SET(tirc, tirc, inline_rqn,
2748                     priv->channel[0].rq.rqn);
2749                 break;
2750         default:
2751                 MLX5_SET(tirc, tirc, disp_type,
2752                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2753                 MLX5_SET(tirc, tirc, indirect_table,
2754                     priv->rqtn);
2755                 MLX5_SET(tirc, tirc, rx_hash_fn,
2756                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2757                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2758 #ifdef RSS
2759                 /*
2760                  * The FreeBSD RSS implementation does currently not
2761                  * support symmetric Toeplitz hashes:
2762                  */
2763                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2764                 rss_getkey((uint8_t *)hkey);
2765 #else
2766                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2767                 hkey[0] = cpu_to_be32(0xD181C62C);
2768                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2769                 hkey[2] = cpu_to_be32(0x1983A2FC);
2770                 hkey[3] = cpu_to_be32(0x943E1ADB);
2771                 hkey[4] = cpu_to_be32(0xD9389E6B);
2772                 hkey[5] = cpu_to_be32(0xD1039C2C);
2773                 hkey[6] = cpu_to_be32(0xA74499AD);
2774                 hkey[7] = cpu_to_be32(0x593D56D9);
2775                 hkey[8] = cpu_to_be32(0xF3253C06);
2776                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2777 #endif
2778                 break;
2779         }
2780
2781         switch (tt) {
2782         case MLX5E_TT_IPV4_TCP:
2783                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2784                     MLX5_L3_PROT_TYPE_IPV4);
2785                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2786                     MLX5_L4_PROT_TYPE_TCP);
2787 #ifdef RSS
2788                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2789                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2790                             MLX5_HASH_IP);
2791                 } else
2792 #endif
2793                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2794                     MLX5_HASH_ALL);
2795                 break;
2796
2797         case MLX5E_TT_IPV6_TCP:
2798                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2799                     MLX5_L3_PROT_TYPE_IPV6);
2800                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2801                     MLX5_L4_PROT_TYPE_TCP);
2802 #ifdef RSS
2803                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2804                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2805                             MLX5_HASH_IP);
2806                 } else
2807 #endif
2808                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2809                     MLX5_HASH_ALL);
2810                 break;
2811
2812         case MLX5E_TT_IPV4_UDP:
2813                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2814                     MLX5_L3_PROT_TYPE_IPV4);
2815                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2816                     MLX5_L4_PROT_TYPE_UDP);
2817 #ifdef RSS
2818                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2819                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2820                             MLX5_HASH_IP);
2821                 } else
2822 #endif
2823                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2824                     MLX5_HASH_ALL);
2825                 break;
2826
2827         case MLX5E_TT_IPV6_UDP:
2828                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2829                     MLX5_L3_PROT_TYPE_IPV6);
2830                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2831                     MLX5_L4_PROT_TYPE_UDP);
2832 #ifdef RSS
2833                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2834                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2835                             MLX5_HASH_IP);
2836                 } else
2837 #endif
2838                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2839                     MLX5_HASH_ALL);
2840                 break;
2841
2842         case MLX5E_TT_IPV4_IPSEC_AH:
2843                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2844                     MLX5_L3_PROT_TYPE_IPV4);
2845                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2846                     MLX5_HASH_IP_IPSEC_SPI);
2847                 break;
2848
2849         case MLX5E_TT_IPV6_IPSEC_AH:
2850                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2851                     MLX5_L3_PROT_TYPE_IPV6);
2852                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2853                     MLX5_HASH_IP_IPSEC_SPI);
2854                 break;
2855
2856         case MLX5E_TT_IPV4_IPSEC_ESP:
2857                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2858                     MLX5_L3_PROT_TYPE_IPV4);
2859                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2860                     MLX5_HASH_IP_IPSEC_SPI);
2861                 break;
2862
2863         case MLX5E_TT_IPV6_IPSEC_ESP:
2864                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2865                     MLX5_L3_PROT_TYPE_IPV6);
2866                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2867                     MLX5_HASH_IP_IPSEC_SPI);
2868                 break;
2869
2870         case MLX5E_TT_IPV4:
2871                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2872                     MLX5_L3_PROT_TYPE_IPV4);
2873                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2874                     MLX5_HASH_IP);
2875                 break;
2876
2877         case MLX5E_TT_IPV6:
2878                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2879                     MLX5_L3_PROT_TYPE_IPV6);
2880                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2881                     MLX5_HASH_IP);
2882                 break;
2883
2884         default:
2885                 break;
2886         }
2887 }
2888
2889 static int
2890 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2891 {
2892         struct mlx5_core_dev *mdev = priv->mdev;
2893         u32 *in;
2894         void *tirc;
2895         int inlen;
2896         int err;
2897
2898         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2899         in = mlx5_vzalloc(inlen);
2900         if (in == NULL)
2901                 return (-ENOMEM);
2902         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2903
2904         mlx5e_build_tir_ctx(priv, tirc, tt);
2905
2906         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2907
2908         kvfree(in);
2909
2910         return (err);
2911 }
2912
2913 static void
2914 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2915 {
2916         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2917 }
2918
2919 static int
2920 mlx5e_open_tirs(struct mlx5e_priv *priv)
2921 {
2922         int err;
2923         int i;
2924
2925         for (i = 0; i < MLX5E_NUM_TT; i++) {
2926                 err = mlx5e_open_tir(priv, i);
2927                 if (err)
2928                         goto err_close_tirs;
2929         }
2930
2931         return (0);
2932
2933 err_close_tirs:
2934         for (i--; i >= 0; i--)
2935                 mlx5e_close_tir(priv, i);
2936
2937         return (err);
2938 }
2939
2940 static void
2941 mlx5e_close_tirs(struct mlx5e_priv *priv)
2942 {
2943         int i;
2944
2945         for (i = 0; i < MLX5E_NUM_TT; i++)
2946                 mlx5e_close_tir(priv, i);
2947 }
2948
2949 /*
2950  * SW MTU does not include headers,
2951  * HW MTU includes all headers and checksums.
2952  */
2953 static int
2954 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2955 {
2956         struct mlx5e_priv *priv = ifp->if_softc;
2957         struct mlx5_core_dev *mdev = priv->mdev;
2958         int hw_mtu;
2959         int err;
2960
2961         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2962
2963         err = mlx5_set_port_mtu(mdev, hw_mtu);
2964         if (err) {
2965                 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2966                     sw_mtu, err);
2967                 return (err);
2968         }
2969
2970         /* Update vport context MTU */
2971         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2972         if (err) {
2973                 mlx5_en_err(ifp,
2974                     "Failed updating vport context with MTU size, err=%d\n",
2975                     err);
2976         }
2977
2978         ifp->if_mtu = sw_mtu;
2979
2980         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2981         if (err || !hw_mtu) {
2982                 /* fallback to port oper mtu */
2983                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2984         }
2985         if (err) {
2986                 mlx5_en_err(ifp,
2987                     "Query port MTU, after setting new MTU value, failed\n");
2988                 return (err);
2989         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2990                 err = -E2BIG,
2991                 mlx5_en_err(ifp,
2992                     "Port MTU %d is smaller than ifp mtu %d\n",
2993                     hw_mtu, sw_mtu);
2994         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2995                 err = -EINVAL;
2996                 mlx5_en_err(ifp,
2997                     "Port MTU %d is bigger than ifp mtu %d\n",
2998                     hw_mtu, sw_mtu);
2999         }
3000         priv->params_ethtool.hw_mtu = hw_mtu;
3001
3002         return (err);
3003 }
3004
3005 int
3006 mlx5e_open_locked(struct ifnet *ifp)
3007 {
3008         struct mlx5e_priv *priv = ifp->if_softc;
3009         int err;
3010         u16 set_id;
3011
3012         /* check if already opened */
3013         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3014                 return (0);
3015
3016 #ifdef RSS
3017         if (rss_getnumbuckets() > priv->params.num_channels) {
3018                 mlx5_en_info(ifp,
3019                     "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3020                     rss_getnumbuckets(), priv->params.num_channels);
3021         }
3022 #endif
3023         err = mlx5e_open_tises(priv);
3024         if (err) {
3025                 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3026                 return (err);
3027         }
3028         err = mlx5_vport_alloc_q_counter(priv->mdev,
3029             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3030         if (err) {
3031                 mlx5_en_err(priv->ifp,
3032                     "mlx5_vport_alloc_q_counter failed: %d\n", err);
3033                 goto err_close_tises;
3034         }
3035         /* store counter set ID */
3036         priv->counter_set_id = set_id;
3037
3038         err = mlx5e_open_channels(priv);
3039         if (err) {
3040                 mlx5_en_err(ifp,
3041                     "mlx5e_open_channels failed, %d\n", err);
3042                 goto err_dalloc_q_counter;
3043         }
3044         err = mlx5e_open_rqt(priv);
3045         if (err) {
3046                 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3047                 goto err_close_channels;
3048         }
3049         err = mlx5e_open_tirs(priv);
3050         if (err) {
3051                 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3052                 goto err_close_rqls;
3053         }
3054         err = mlx5e_open_flow_table(priv);
3055         if (err) {
3056                 mlx5_en_err(ifp,
3057                     "mlx5e_open_flow_table failed, %d\n", err);
3058                 goto err_close_tirs;
3059         }
3060         err = mlx5e_add_all_vlan_rules(priv);
3061         if (err) {
3062                 mlx5_en_err(ifp,
3063                     "mlx5e_add_all_vlan_rules failed, %d\n", err);
3064                 goto err_close_flow_table;
3065         }
3066         set_bit(MLX5E_STATE_OPENED, &priv->state);
3067
3068         mlx5e_update_carrier(priv);
3069         mlx5e_set_rx_mode_core(priv);
3070
3071         return (0);
3072
3073 err_close_flow_table:
3074         mlx5e_close_flow_table(priv);
3075
3076 err_close_tirs:
3077         mlx5e_close_tirs(priv);
3078
3079 err_close_rqls:
3080         mlx5e_close_rqt(priv);
3081
3082 err_close_channels:
3083         mlx5e_close_channels(priv);
3084
3085 err_dalloc_q_counter:
3086         mlx5_vport_dealloc_q_counter(priv->mdev,
3087             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3088
3089 err_close_tises:
3090         mlx5e_close_tises(priv);
3091
3092         return (err);
3093 }
3094
3095 static void
3096 mlx5e_open(void *arg)
3097 {
3098         struct mlx5e_priv *priv = arg;
3099
3100         PRIV_LOCK(priv);
3101         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3102                 mlx5_en_err(priv->ifp,
3103                     "Setting port status to up failed\n");
3104
3105         mlx5e_open_locked(priv->ifp);
3106         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3107         PRIV_UNLOCK(priv);
3108 }
3109
3110 int
3111 mlx5e_close_locked(struct ifnet *ifp)
3112 {
3113         struct mlx5e_priv *priv = ifp->if_softc;
3114
3115         /* check if already closed */
3116         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3117                 return (0);
3118
3119         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3120
3121         mlx5e_set_rx_mode_core(priv);
3122         mlx5e_del_all_vlan_rules(priv);
3123         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3124         mlx5e_close_flow_table(priv);
3125         mlx5e_close_tirs(priv);
3126         mlx5e_close_rqt(priv);
3127         mlx5e_close_channels(priv);
3128         mlx5_vport_dealloc_q_counter(priv->mdev,
3129             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3130         mlx5e_close_tises(priv);
3131
3132         return (0);
3133 }
3134
3135 #if (__FreeBSD_version >= 1100000)
3136 static uint64_t
3137 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3138 {
3139         struct mlx5e_priv *priv = ifp->if_softc;
3140         u64 retval;
3141
3142         /* PRIV_LOCK(priv); XXX not allowed */
3143         switch (cnt) {
3144         case IFCOUNTER_IPACKETS:
3145                 retval = priv->stats.vport.rx_packets;
3146                 break;
3147         case IFCOUNTER_IERRORS:
3148                 retval = priv->stats.pport.in_range_len_errors +
3149                     priv->stats.pport.out_of_range_len +
3150                     priv->stats.pport.too_long_errors +
3151                     priv->stats.pport.check_seq_err +
3152                     priv->stats.pport.alignment_err;
3153                 break;
3154         case IFCOUNTER_IQDROPS:
3155                 retval = priv->stats.vport.rx_out_of_buffer;
3156                 break;
3157         case IFCOUNTER_OPACKETS:
3158                 retval = priv->stats.vport.tx_packets;
3159                 break;
3160         case IFCOUNTER_OERRORS:
3161                 retval = priv->stats.port_stats_debug.out_discards;
3162                 break;
3163         case IFCOUNTER_IBYTES:
3164                 retval = priv->stats.vport.rx_bytes;
3165                 break;
3166         case IFCOUNTER_OBYTES:
3167                 retval = priv->stats.vport.tx_bytes;
3168                 break;
3169         case IFCOUNTER_IMCASTS:
3170                 retval = priv->stats.vport.rx_multicast_packets;
3171                 break;
3172         case IFCOUNTER_OMCASTS:
3173                 retval = priv->stats.vport.tx_multicast_packets;
3174                 break;
3175         case IFCOUNTER_OQDROPS:
3176                 retval = priv->stats.vport.tx_queue_dropped;
3177                 break;
3178         case IFCOUNTER_COLLISIONS:
3179                 retval = priv->stats.pport.collisions;
3180                 break;
3181         default:
3182                 retval = if_get_counter_default(ifp, cnt);
3183                 break;
3184         }
3185         /* PRIV_UNLOCK(priv); XXX not allowed */
3186         return (retval);
3187 }
3188 #endif
3189
3190 static void
3191 mlx5e_set_rx_mode(struct ifnet *ifp)
3192 {
3193         struct mlx5e_priv *priv = ifp->if_softc;
3194
3195         queue_work(priv->wq, &priv->set_rx_mode_work);
3196 }
3197
3198 static int
3199 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3200 {
3201         struct mlx5e_priv *priv;
3202         struct ifreq *ifr;
3203         struct ifi2creq i2c;
3204         int error = 0;
3205         int mask = 0;
3206         int size_read = 0;
3207         int module_status;
3208         int module_num;
3209         int max_mtu;
3210         uint8_t read_addr;
3211
3212         priv = ifp->if_softc;
3213
3214         /* check if detaching */
3215         if (priv == NULL || priv->gone != 0)
3216                 return (ENXIO);
3217
3218         switch (command) {
3219         case SIOCSIFMTU:
3220                 ifr = (struct ifreq *)data;
3221
3222                 PRIV_LOCK(priv);
3223                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3224
3225                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3226                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3227                         int was_opened;
3228
3229                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3230                         if (was_opened)
3231                                 mlx5e_close_locked(ifp);
3232
3233                         /* set new MTU */
3234                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3235
3236                         if (was_opened)
3237                                 mlx5e_open_locked(ifp);
3238                 } else {
3239                         error = EINVAL;
3240                         mlx5_en_err(ifp,
3241                             "Invalid MTU value. Min val: %d, Max val: %d\n",
3242                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3243                 }
3244                 PRIV_UNLOCK(priv);
3245                 break;
3246         case SIOCSIFFLAGS:
3247                 if ((ifp->if_flags & IFF_UP) &&
3248                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3249                         mlx5e_set_rx_mode(ifp);
3250                         break;
3251                 }
3252                 PRIV_LOCK(priv);
3253                 if (ifp->if_flags & IFF_UP) {
3254                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3255                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3256                                         mlx5e_open_locked(ifp);
3257                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3258                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3259                         }
3260                 } else {
3261                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3262                                 mlx5_set_port_status(priv->mdev,
3263                                     MLX5_PORT_DOWN);
3264                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3265                                         mlx5e_close_locked(ifp);
3266                                 mlx5e_update_carrier(priv);
3267                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3268                         }
3269                 }
3270                 PRIV_UNLOCK(priv);
3271                 break;
3272         case SIOCADDMULTI:
3273         case SIOCDELMULTI:
3274                 mlx5e_set_rx_mode(ifp);
3275                 break;
3276         case SIOCSIFMEDIA:
3277         case SIOCGIFMEDIA:
3278         case SIOCGIFXMEDIA:
3279                 ifr = (struct ifreq *)data;
3280                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3281                 break;
3282         case SIOCSIFCAP:
3283                 ifr = (struct ifreq *)data;
3284                 PRIV_LOCK(priv);
3285                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3286
3287                 if (mask & IFCAP_TXCSUM) {
3288                         ifp->if_capenable ^= IFCAP_TXCSUM;
3289                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3290
3291                         if (IFCAP_TSO4 & ifp->if_capenable &&
3292                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3293                                 ifp->if_capenable &= ~IFCAP_TSO4;
3294                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3295                                 mlx5_en_err(ifp,
3296                                     "tso4 disabled due to -txcsum.\n");
3297                         }
3298                 }
3299                 if (mask & IFCAP_TXCSUM_IPV6) {
3300                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3301                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3302
3303                         if (IFCAP_TSO6 & ifp->if_capenable &&
3304                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3305                                 ifp->if_capenable &= ~IFCAP_TSO6;
3306                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3307                                 mlx5_en_err(ifp,
3308                                     "tso6 disabled due to -txcsum6.\n");
3309                         }
3310                 }
3311                 if (mask & IFCAP_NOMAP)
3312                         ifp->if_capenable ^= IFCAP_NOMAP;
3313                 if (mask & IFCAP_RXCSUM)
3314                         ifp->if_capenable ^= IFCAP_RXCSUM;
3315                 if (mask & IFCAP_RXCSUM_IPV6)
3316                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3317                 if (mask & IFCAP_TSO4) {
3318                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3319                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3320                                 mlx5_en_err(ifp, "enable txcsum first.\n");
3321                                 error = EAGAIN;
3322                                 goto out;
3323                         }
3324                         ifp->if_capenable ^= IFCAP_TSO4;
3325                         ifp->if_hwassist ^= CSUM_IP_TSO;
3326                 }
3327                 if (mask & IFCAP_TSO6) {
3328                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3329                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3330                                 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3331                                 error = EAGAIN;
3332                                 goto out;
3333                         }
3334                         ifp->if_capenable ^= IFCAP_TSO6;
3335                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3336                 }
3337                 if (mask & IFCAP_VLAN_HWFILTER) {
3338                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3339                                 mlx5e_disable_vlan_filter(priv);
3340                         else
3341                                 mlx5e_enable_vlan_filter(priv);
3342
3343                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3344                 }
3345                 if (mask & IFCAP_VLAN_HWTAGGING)
3346                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3347                 if (mask & IFCAP_WOL_MAGIC)
3348                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3349
3350                 VLAN_CAPABILITIES(ifp);
3351                 /* turn off LRO means also turn of HW LRO - if it's on */
3352                 if (mask & IFCAP_LRO) {
3353                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3354                         bool need_restart = false;
3355
3356                         ifp->if_capenable ^= IFCAP_LRO;
3357
3358                         /* figure out if updating HW LRO is needed */
3359                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3360                                 if (priv->params.hw_lro_en) {
3361                                         priv->params.hw_lro_en = false;
3362                                         need_restart = true;
3363                                 }
3364                         } else {
3365                                 if (priv->params.hw_lro_en == false &&
3366                                     priv->params_ethtool.hw_lro != 0) {
3367                                         priv->params.hw_lro_en = true;
3368                                         need_restart = true;
3369                                 }
3370                         }
3371                         if (was_opened && need_restart) {
3372                                 mlx5e_close_locked(ifp);
3373                                 mlx5e_open_locked(ifp);
3374                         }
3375                 }
3376                 if (mask & IFCAP_HWRXTSTMP) {
3377                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3378                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3379                                 if (priv->clbr_done == 0)
3380                                         mlx5e_reset_calibration_callout(priv);
3381                         } else {
3382                                 callout_drain(&priv->tstmp_clbr);
3383                                 priv->clbr_done = 0;
3384                         }
3385                 }
3386 out:
3387                 PRIV_UNLOCK(priv);
3388                 break;
3389
3390         case SIOCGI2C:
3391                 ifr = (struct ifreq *)data;
3392
3393                 /*
3394                  * Copy from the user-space address ifr_data to the
3395                  * kernel-space address i2c
3396                  */
3397                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3398                 if (error)
3399                         break;
3400
3401                 if (i2c.len > sizeof(i2c.data)) {
3402                         error = EINVAL;
3403                         break;
3404                 }
3405
3406                 PRIV_LOCK(priv);
3407                 /* Get module_num which is required for the query_eeprom */
3408                 error = mlx5_query_module_num(priv->mdev, &module_num);
3409                 if (error) {
3410                         mlx5_en_err(ifp,
3411                             "Query module num failed, eeprom reading is not supported\n");
3412                         error = EINVAL;
3413                         goto err_i2c;
3414                 }
3415                 /* Check if module is present before doing an access */
3416                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3417                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3418                         error = EINVAL;
3419                         goto err_i2c;
3420                 }
3421                 /*
3422                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3423                  * The internal conversion is as follows:
3424                  */
3425                 if (i2c.dev_addr == 0xA0)
3426                         read_addr = MLX5_I2C_ADDR_LOW;
3427                 else if (i2c.dev_addr == 0xA2)
3428                         read_addr = MLX5_I2C_ADDR_HIGH;
3429                 else {
3430                         mlx5_en_err(ifp,
3431                             "Query eeprom failed, Invalid Address: %X\n",
3432                             i2c.dev_addr);
3433                         error = EINVAL;
3434                         goto err_i2c;
3435                 }
3436                 error = mlx5_query_eeprom(priv->mdev,
3437                     read_addr, MLX5_EEPROM_LOW_PAGE,
3438                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3439                     (uint32_t *)i2c.data, &size_read);
3440                 if (error) {
3441                         mlx5_en_err(ifp,
3442                             "Query eeprom failed, eeprom reading is not supported\n");
3443                         error = EINVAL;
3444                         goto err_i2c;
3445                 }
3446
3447                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3448                         error = mlx5_query_eeprom(priv->mdev,
3449                             read_addr, MLX5_EEPROM_LOW_PAGE,
3450                             (uint32_t)(i2c.offset + size_read),
3451                             (uint32_t)(i2c.len - size_read), module_num,
3452                             (uint32_t *)(i2c.data + size_read), &size_read);
3453                 }
3454                 if (error) {
3455                         mlx5_en_err(ifp,
3456                             "Query eeprom failed, eeprom reading is not supported\n");
3457                         error = EINVAL;
3458                         goto err_i2c;
3459                 }
3460
3461                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3462 err_i2c:
3463                 PRIV_UNLOCK(priv);
3464                 break;
3465
3466         default:
3467                 error = ether_ioctl(ifp, command, data);
3468                 break;
3469         }
3470         return (error);
3471 }
3472
3473 static int
3474 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3475 {
3476         /*
3477          * TODO: uncoment once FW really sets all these bits if
3478          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3479          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3480          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3481          * -ENOTSUPP;
3482          */
3483
3484         /* TODO: add more must-to-have features */
3485
3486         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3487                 return (-ENODEV);
3488
3489         return (0);
3490 }
3491
3492 static u16
3493 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3494 {
3495         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3496
3497         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3498
3499         /* verify against driver hardware limit */
3500         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3501                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3502
3503         return (bf_buf_size);
3504 }
3505
3506 static int
3507 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3508     struct mlx5e_priv *priv,
3509     int num_comp_vectors)
3510 {
3511         int err;
3512
3513         /*
3514          * TODO: Consider link speed for setting "log_sq_size",
3515          * "log_rq_size" and "cq_moderation_xxx":
3516          */
3517         priv->params.log_sq_size =
3518             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3519         priv->params.log_rq_size =
3520             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3521         priv->params.rx_cq_moderation_usec =
3522             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3523             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3524             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3525         priv->params.rx_cq_moderation_mode =
3526             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3527         priv->params.rx_cq_moderation_pkts =
3528             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3529         priv->params.tx_cq_moderation_usec =
3530             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3531         priv->params.tx_cq_moderation_pkts =
3532             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3533         priv->params.min_rx_wqes =
3534             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3535         priv->params.rx_hash_log_tbl_sz =
3536             (order_base_2(num_comp_vectors) >
3537             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3538             order_base_2(num_comp_vectors) :
3539             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3540         priv->params.num_tc = 1;
3541         priv->params.default_vlan_prio = 0;
3542         priv->counter_set_id = -1;
3543         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3544
3545         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3546         if (err)
3547                 return (err);
3548
3549         /*
3550          * hw lro is currently defaulted to off. when it won't anymore we
3551          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3552          */
3553         priv->params.hw_lro_en = false;
3554         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3555
3556         /*
3557          * CQE zipping is currently defaulted to off. when it won't
3558          * anymore we will consider the HW capability:
3559          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3560          */
3561         priv->params.cqe_zipping_en = false;
3562
3563         priv->mdev = mdev;
3564         priv->params.num_channels = num_comp_vectors;
3565         priv->params.channels_rsss = 1;
3566         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3567         priv->queue_mapping_channel_mask =
3568             roundup_pow_of_two(num_comp_vectors) - 1;
3569         priv->num_tc = priv->params.num_tc;
3570         priv->default_vlan_prio = priv->params.default_vlan_prio;
3571
3572         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3573         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3574         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3575
3576         return (0);
3577 }
3578
3579 static int
3580 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3581                   struct mlx5_core_mr *mkey)
3582 {
3583         struct ifnet *ifp = priv->ifp;
3584         struct mlx5_core_dev *mdev = priv->mdev;
3585         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3586         void *mkc;
3587         u32 *in;
3588         int err;
3589
3590         in = mlx5_vzalloc(inlen);
3591         if (in == NULL) {
3592                 mlx5_en_err(ifp, "failed to allocate inbox\n");
3593                 return (-ENOMEM);
3594         }
3595
3596         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3597         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3598         MLX5_SET(mkc, mkc, lw, 1);
3599         MLX5_SET(mkc, mkc, lr, 1);
3600
3601         MLX5_SET(mkc, mkc, pd, pdn);
3602         MLX5_SET(mkc, mkc, length64, 1);
3603         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3604
3605         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3606         if (err)
3607                 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3608                     err);
3609
3610         kvfree(in);
3611         return (err);
3612 }
3613
3614 static const char *mlx5e_vport_stats_desc[] = {
3615         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3616 };
3617
3618 static const char *mlx5e_pport_stats_desc[] = {
3619         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3620 };
3621
3622 static void
3623 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3624 {
3625         uint32_t x;
3626
3627         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3628         sx_init(&priv->state_lock, "mlx5state");
3629         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3630         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3631         for (x = 0; x != channels; x++)
3632                 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3633 }
3634
3635 static void
3636 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3637 {
3638         uint32_t x;
3639
3640         for (x = 0; x != channels; x++)
3641                 mlx5e_chan_static_destroy(&priv->channel[x]);
3642         callout_drain(&priv->watchdog);
3643         mtx_destroy(&priv->async_events_mtx);
3644         sx_destroy(&priv->state_lock);
3645 }
3646
3647 static int
3648 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3649 {
3650         /*
3651          * %d.%d%.d the string format.
3652          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3653          * We need at most 5 chars to store that.
3654          * It also has: two "." and NULL at the end, which means we need 18
3655          * (5*3 + 3) chars at most.
3656          */
3657         char fw[18];
3658         struct mlx5e_priv *priv = arg1;
3659         int error;
3660
3661         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3662             fw_rev_sub(priv->mdev));
3663         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3664         return (error);
3665 }
3666
3667 static void
3668 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3669 {
3670         int i;
3671
3672         for (i = 0; i < ch->priv->num_tc; i++)
3673                 mlx5e_drain_sq(&ch->sq[i]);
3674 }
3675
3676 static void
3677 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3678 {
3679
3680         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3681         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3682         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3683         sq->doorbell.d64 = 0;
3684 }
3685
3686 void
3687 mlx5e_resume_sq(struct mlx5e_sq *sq)
3688 {
3689         int err;
3690
3691         /* check if already enabled */
3692         if (READ_ONCE(sq->running) != 0)
3693                 return;
3694
3695         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3696             MLX5_SQC_STATE_RST);
3697         if (err != 0) {
3698                 mlx5_en_err(sq->ifp,
3699                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3700         }
3701
3702         sq->cc = 0;
3703         sq->pc = 0;
3704
3705         /* reset doorbell prior to moving from RST to RDY */
3706         mlx5e_reset_sq_doorbell_record(sq);
3707
3708         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3709             MLX5_SQC_STATE_RDY);
3710         if (err != 0) {
3711                 mlx5_en_err(sq->ifp,
3712                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3713         }
3714
3715         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3716         WRITE_ONCE(sq->running, 1);
3717 }
3718
3719 static void
3720 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3721 {
3722         int i;
3723
3724         for (i = 0; i < ch->priv->num_tc; i++)
3725                 mlx5e_resume_sq(&ch->sq[i]);
3726 }
3727
3728 static void
3729 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3730 {
3731         struct mlx5e_rq *rq = &ch->rq;
3732         int err;
3733
3734         mtx_lock(&rq->mtx);
3735         rq->enabled = 0;
3736         callout_stop(&rq->watchdog);
3737         mtx_unlock(&rq->mtx);
3738
3739         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3740         if (err != 0) {
3741                 mlx5_en_err(rq->ifp,
3742                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3743         }
3744
3745         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3746                 msleep(1);
3747                 rq->cq.mcq.comp(&rq->cq.mcq);
3748         }
3749
3750         /*
3751          * Transitioning into RST state will allow the FW to track less ERR state queues,
3752          * thus reducing the recv queue flushing time
3753          */
3754         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3755         if (err != 0) {
3756                 mlx5_en_err(rq->ifp,
3757                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3758         }
3759 }
3760
3761 static void
3762 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3763 {
3764         struct mlx5e_rq *rq = &ch->rq;
3765         int err;
3766
3767         rq->wq.wqe_ctr = 0;
3768         mlx5_wq_ll_update_db_record(&rq->wq);
3769         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3770         if (err != 0) {
3771                 mlx5_en_err(rq->ifp,
3772                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3773         }
3774
3775         rq->enabled = 1;
3776
3777         rq->cq.mcq.comp(&rq->cq.mcq);
3778 }
3779
3780 void
3781 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3782 {
3783         int i;
3784
3785         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3786                 return;
3787
3788         for (i = 0; i < priv->params.num_channels; i++) {
3789                 if (value)
3790                         mlx5e_disable_tx_dma(&priv->channel[i]);
3791                 else
3792                         mlx5e_enable_tx_dma(&priv->channel[i]);
3793         }
3794 }
3795
3796 void
3797 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3798 {
3799         int i;
3800
3801         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3802                 return;
3803
3804         for (i = 0; i < priv->params.num_channels; i++) {
3805                 if (value)
3806                         mlx5e_disable_rx_dma(&priv->channel[i]);
3807                 else
3808                         mlx5e_enable_rx_dma(&priv->channel[i]);
3809         }
3810 }
3811
3812 static void
3813 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3814 {
3815         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3816             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3817             sysctl_firmware, "A", "HCA firmware version");
3818
3819         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3820             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3821             "Board ID");
3822 }
3823
3824 static int
3825 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3826 {
3827         struct mlx5e_priv *priv = arg1;
3828         uint8_t temp[MLX5E_MAX_PRIORITY];
3829         uint32_t tx_pfc;
3830         int err;
3831         int i;
3832
3833         PRIV_LOCK(priv);
3834
3835         tx_pfc = priv->params.tx_priority_flow_control;
3836
3837         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3838                 temp[i] = (tx_pfc >> i) & 1;
3839
3840         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3841         if (err || !req->newptr)
3842                 goto done;
3843         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3844         if (err)
3845                 goto done;
3846
3847         priv->params.tx_priority_flow_control = 0;
3848
3849         /* range check input value */
3850         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3851                 if (temp[i] > 1) {
3852                         err = ERANGE;
3853                         goto done;
3854                 }
3855                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3856         }
3857
3858         /* check if update is required */
3859         if (tx_pfc != priv->params.tx_priority_flow_control)
3860                 err = -mlx5e_set_port_pfc(priv);
3861 done:
3862         if (err != 0)
3863                 priv->params.tx_priority_flow_control= tx_pfc;
3864         PRIV_UNLOCK(priv);
3865
3866         return (err);
3867 }
3868
3869 static int
3870 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3871 {
3872         struct mlx5e_priv *priv = arg1;
3873         uint8_t temp[MLX5E_MAX_PRIORITY];
3874         uint32_t rx_pfc;
3875         int err;
3876         int i;
3877
3878         PRIV_LOCK(priv);
3879
3880         rx_pfc = priv->params.rx_priority_flow_control;
3881
3882         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3883                 temp[i] = (rx_pfc >> i) & 1;
3884
3885         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3886         if (err || !req->newptr)
3887                 goto done;
3888         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3889         if (err)
3890                 goto done;
3891
3892         priv->params.rx_priority_flow_control = 0;
3893
3894         /* range check input value */
3895         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3896                 if (temp[i] > 1) {
3897                         err = ERANGE;
3898                         goto done;
3899                 }
3900                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3901         }
3902
3903         /* check if update is required */
3904         if (rx_pfc != priv->params.rx_priority_flow_control) {
3905                 err = -mlx5e_set_port_pfc(priv);
3906                 if (err == 0 && priv->sw_is_port_buf_owner)
3907                         err = mlx5e_update_buf_lossy(priv);
3908         }
3909 done:
3910         if (err != 0)
3911                 priv->params.rx_priority_flow_control= rx_pfc;
3912         PRIV_UNLOCK(priv);
3913
3914         return (err);
3915 }
3916
3917 static void
3918 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3919 {
3920 #if (__FreeBSD_version < 1100000)
3921         char path[96];
3922 #endif
3923         int error;
3924
3925         /* enable pauseframes by default */
3926         priv->params.tx_pauseframe_control = 1;
3927         priv->params.rx_pauseframe_control = 1;
3928
3929         /* disable ports flow control, PFC, by default */
3930         priv->params.tx_priority_flow_control = 0;
3931         priv->params.rx_priority_flow_control = 0;
3932
3933 #if (__FreeBSD_version < 1100000)
3934         /* compute path for sysctl */
3935         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3936             device_get_unit(priv->mdev->pdev->dev.bsddev));
3937
3938         /* try to fetch tunable, if any */
3939         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3940
3941         /* compute path for sysctl */
3942         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3943             device_get_unit(priv->mdev->pdev->dev.bsddev));
3944
3945         /* try to fetch tunable, if any */
3946         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3947 #endif
3948
3949         /* register pauseframe SYSCTLs */
3950         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3951             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3952             &priv->params.tx_pauseframe_control, 0,
3953             "Set to enable TX pause frames. Clear to disable.");
3954
3955         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3956             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3957             &priv->params.rx_pauseframe_control, 0,
3958             "Set to enable RX pause frames. Clear to disable.");
3959
3960         /* register priority flow control, PFC, SYSCTLs */
3961         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3962             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3963             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3964             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3965
3966         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3967             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3968             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3969             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3970
3971         PRIV_LOCK(priv);
3972
3973         /* range check */
3974         priv->params.tx_pauseframe_control =
3975             priv->params.tx_pauseframe_control ? 1 : 0;
3976         priv->params.rx_pauseframe_control =
3977             priv->params.rx_pauseframe_control ? 1 : 0;
3978
3979         /* update firmware */
3980         error = mlx5e_set_port_pause_and_pfc(priv);
3981         if (error == -EINVAL) {
3982                 mlx5_en_err(priv->ifp,
3983                     "Global pauseframes must be disabled before enabling PFC.\n");
3984                 priv->params.rx_priority_flow_control = 0;
3985                 priv->params.tx_priority_flow_control = 0;
3986
3987                 /* update firmware */
3988                 (void) mlx5e_set_port_pause_and_pfc(priv);
3989         }
3990         PRIV_UNLOCK(priv);
3991 }
3992
3993 static int
3994 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3995     union if_snd_tag_alloc_params *params,
3996     struct m_snd_tag **ppmt)
3997 {
3998         struct mlx5e_priv *priv;
3999         struct mlx5e_channel *pch;
4000
4001         priv = ifp->if_softc;
4002
4003         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4004                 return (EOPNOTSUPP);
4005         } else {
4006                 /* keep this code synced with mlx5e_select_queue() */
4007                 u32 ch = priv->params.num_channels;
4008 #ifdef RSS
4009                 u32 temp;
4010
4011                 if (rss_hash2bucket(params->hdr.flowid,
4012                     params->hdr.flowtype, &temp) == 0)
4013                         ch = temp % ch;
4014                 else
4015 #endif
4016                         ch = (params->hdr.flowid % 128) % ch;
4017
4018                 /*
4019                  * NOTE: The channels array is only freed at detach
4020                  * and it safe to return a pointer to the send tag
4021                  * inside the channels structure as long as we
4022                  * reference the priv.
4023                  */
4024                 pch = priv->channel + ch;
4025
4026                 /* check if send queue is not running */
4027                 if (unlikely(pch->sq[0].running == 0))
4028                         return (ENXIO);
4029                 m_snd_tag_ref(&pch->tag.m_snd_tag);
4030                 *ppmt = &pch->tag.m_snd_tag;
4031                 return (0);
4032         }
4033 }
4034
4035 static int
4036 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4037 {
4038         struct mlx5e_channel *pch =
4039             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4040
4041         params->unlimited.max_rate = -1ULL;
4042         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4043         return (0);
4044 }
4045
4046 static void
4047 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4048 {
4049         struct mlx5e_channel *pch =
4050             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4051
4052         complete(&pch->completion);
4053 }
4054
4055 static int
4056 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4057     union if_snd_tag_alloc_params *params,
4058     struct m_snd_tag **ppmt)
4059 {
4060
4061         switch (params->hdr.type) {
4062 #ifdef RATELIMIT
4063         case IF_SND_TAG_TYPE_RATE_LIMIT:
4064                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4065 #endif
4066         case IF_SND_TAG_TYPE_UNLIMITED:
4067                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4068         default:
4069                 return (EOPNOTSUPP);
4070         }
4071 }
4072
4073 static int
4074 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4075 {
4076         struct mlx5e_snd_tag *tag =
4077             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4078
4079         switch (tag->type) {
4080 #ifdef RATELIMIT
4081         case IF_SND_TAG_TYPE_RATE_LIMIT:
4082                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4083 #endif
4084         case IF_SND_TAG_TYPE_UNLIMITED:
4085         default:
4086                 return (EOPNOTSUPP);
4087         }
4088 }
4089
4090 static int
4091 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4092 {
4093         struct mlx5e_snd_tag *tag =
4094             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4095
4096         switch (tag->type) {
4097 #ifdef RATELIMIT
4098         case IF_SND_TAG_TYPE_RATE_LIMIT:
4099                 return (mlx5e_rl_snd_tag_query(pmt, params));
4100 #endif
4101         case IF_SND_TAG_TYPE_UNLIMITED:
4102                 return (mlx5e_ul_snd_tag_query(pmt, params));
4103         default:
4104                 return (EOPNOTSUPP);
4105         }
4106 }
4107
4108 #ifdef RATELIMIT
4109 #define NUM_HDWR_RATES_MLX 13
4110 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4111         135375,                 /* 1,083,000 */
4112         180500,                 /* 1,444,000 */
4113         270750,                 /* 2,166,000 */
4114         361000,                 /* 2,888,000 */
4115         541500,                 /* 4,332,000 */
4116         721875,                 /* 5,775,000 */
4117         1082875,                /* 8,663,000 */
4118         1443875,                /* 11,551,000 */
4119         2165750,                /* 17,326,000 */
4120         2887750,                /* 23,102,000 */
4121         4331625,                /* 34,653,000 */
4122         5775500,                /* 46,204,000 */
4123         8663125                 /* 69,305,000 */
4124 };
4125
4126 static void
4127 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4128 {
4129         /*
4130          * This function needs updating by the driver maintainer!
4131          * For the MLX card there are currently (ConectX-4?) 13
4132          * pre-set rates and others i.e. ConnectX-5, 6, 7??
4133          *
4134          * This will change based on later adapters
4135          * and this code should be updated to look at ifp
4136          * and figure out the specific adapter type
4137          * settings i.e. how many rates as well
4138          * as if they are fixed (as is shown here) or
4139          * if they are dynamic (example chelsio t4). Also if there
4140          * is a maximum number of flows that the adapter
4141          * can handle that too needs to be updated in
4142          * the max_flows field.
4143          */
4144         q->rate_table = adapter_rates_mlx;
4145         q->flags = RT_IS_FIXED_TABLE;
4146         q->max_flows = 0;       /* mlx has no limit */
4147         q->number_of_rates = NUM_HDWR_RATES_MLX;
4148         q->min_segment_burst = 1;
4149 }
4150 #endif
4151
4152 static void
4153 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4154 {
4155         struct mlx5e_snd_tag *tag =
4156             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4157
4158         switch (tag->type) {
4159 #ifdef RATELIMIT
4160         case IF_SND_TAG_TYPE_RATE_LIMIT:
4161                 mlx5e_rl_snd_tag_free(pmt);
4162                 break;
4163 #endif
4164         case IF_SND_TAG_TYPE_UNLIMITED:
4165                 mlx5e_ul_snd_tag_free(pmt);
4166                 break;
4167         default:
4168                 break;
4169         }
4170 }
4171
4172 static void *
4173 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4174 {
4175         struct ifnet *ifp;
4176         struct mlx5e_priv *priv;
4177         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4178         u8 connector_type;
4179         struct sysctl_oid_list *child;
4180         int ncv = mdev->priv.eq_table.num_comp_vectors;
4181         char unit[16];
4182         struct pfil_head_args pa;
4183         int err;
4184         int i,j;
4185         u32 eth_proto_cap;
4186         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4187         bool ext = 0;
4188         u32 speeds_num;
4189         struct media media_entry = {};
4190
4191         if (mlx5e_check_required_hca_cap(mdev)) {
4192                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4193                 return (NULL);
4194         }
4195         /*
4196          * Try to allocate the priv and make room for worst-case
4197          * number of channel structures:
4198          */
4199         priv = malloc(sizeof(*priv) +
4200             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4201             M_MLX5EN, M_WAITOK | M_ZERO);
4202
4203         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4204         if (ifp == NULL) {
4205                 mlx5_core_err(mdev, "if_alloc() failed\n");
4206                 goto err_free_priv;
4207         }
4208         /* setup all static fields */
4209         mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4210
4211         ifp->if_softc = priv;
4212         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4213         ifp->if_mtu = ETHERMTU;
4214         ifp->if_init = mlx5e_open;
4215         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4216         ifp->if_ioctl = mlx5e_ioctl;
4217         ifp->if_transmit = mlx5e_xmit;
4218         ifp->if_qflush = if_qflush;
4219 #if (__FreeBSD_version >= 1100000)
4220         ifp->if_get_counter = mlx5e_get_counter;
4221 #endif
4222         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4223         /*
4224          * Set driver features
4225          */
4226         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4227         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4228         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4229         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4230         ifp->if_capabilities |= IFCAP_LRO;
4231         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4232         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4233         ifp->if_capabilities |= IFCAP_NOMAP;
4234         ifp->if_capabilities |= IFCAP_TXRTLMT;
4235         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4236         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4237         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4238         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4239 #ifdef RATELIMIT
4240         ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4241 #endif
4242         /* set TSO limits so that we don't have to drop TX packets */
4243         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4244         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4245         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4246
4247         ifp->if_capenable = ifp->if_capabilities;
4248         ifp->if_hwassist = 0;
4249         if (ifp->if_capenable & IFCAP_TSO)
4250                 ifp->if_hwassist |= CSUM_TSO;
4251         if (ifp->if_capenable & IFCAP_TXCSUM)
4252                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4253         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4254                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4255
4256         /* ifnet sysctl tree */
4257         sysctl_ctx_init(&priv->sysctl_ctx);
4258         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4259             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4260         if (priv->sysctl_ifnet == NULL) {
4261                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4262                 goto err_free_sysctl;
4263         }
4264         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4265         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4266             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4267         if (priv->sysctl_ifnet == NULL) {
4268                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4269                 goto err_free_sysctl;
4270         }
4271
4272         /* HW sysctl tree */
4273         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4274         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4275             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4276         if (priv->sysctl_hw == NULL) {
4277                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4278                 goto err_free_sysctl;
4279         }
4280
4281         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4282         if (err) {
4283                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4284                 goto err_free_sysctl;
4285         }
4286
4287         /* reuse mlx5core's watchdog workqueue */
4288         priv->wq = mdev->priv.health.wq_watchdog;
4289
4290         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4291         if (err) {
4292                 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4293                 goto err_free_wq;
4294         }
4295         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4296         if (err) {
4297                 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4298                 goto err_unmap_free_uar;
4299         }
4300         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4301         if (err) {
4302                 mlx5_en_err(ifp,
4303                     "mlx5_alloc_transport_domain failed, %d\n", err);
4304                 goto err_dealloc_pd;
4305         }
4306         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4307         if (err) {
4308                 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4309                 goto err_dealloc_transport_domain;
4310         }
4311         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4312
4313         /* check if we should generate a random MAC address */
4314         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4315             is_zero_ether_addr(dev_addr)) {
4316                 random_ether_addr(dev_addr);
4317                 mlx5_en_err(ifp, "Assigned random MAC address\n");
4318         }
4319 #ifdef RATELIMIT
4320         err = mlx5e_rl_init(priv);
4321         if (err) {
4322                 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4323                 goto err_create_mkey;
4324         }
4325 #endif
4326
4327         /* set default MTU */
4328         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4329
4330         /* Set default media status */
4331         priv->media_status_last = IFM_AVALID;
4332         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4333             IFM_ETH_RXPAUSE | IFM_FDX;
4334
4335         /* setup default pauseframes configuration */
4336         mlx5e_setup_pauseframes(priv);
4337
4338         /* Setup supported medias */
4339         //TODO: If we failed to query ptys is it ok to proceed??
4340         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4341                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4342                     ptys_extended_ethernet);
4343                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4344                     eth_proto_capability);
4345                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4346                         connector_type = MLX5_GET(ptys_reg, out,
4347                             connector_type);
4348         } else {
4349                 eth_proto_cap = 0;
4350                 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4351         }
4352
4353         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4354             mlx5e_media_change, mlx5e_media_status);
4355
4356         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4357         for (i = 0; i != speeds_num; i++) {
4358                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4359                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4360                             mlx5e_mode_table[i][j];
4361                         if (media_entry.baudrate == 0)
4362                                 continue;
4363                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4364                                 ifmedia_add(&priv->media,
4365                                     media_entry.subtype |
4366                                     IFM_ETHER, 0, NULL);
4367                                 ifmedia_add(&priv->media,
4368                                     media_entry.subtype |
4369                                     IFM_ETHER | IFM_FDX |
4370                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4371                         }
4372                 }
4373         }
4374
4375         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4376         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4377             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4378
4379         /* Set autoselect by default */
4380         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4381             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4382         ether_ifattach(ifp, dev_addr);
4383
4384         /* Register for VLAN events */
4385         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4386             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4387         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4388             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4389
4390         /* Link is down by default */
4391         if_link_state_change(ifp, LINK_STATE_DOWN);
4392
4393         mlx5e_enable_async_events(priv);
4394
4395         mlx5e_add_hw_stats(priv);
4396
4397         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4398             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4399             priv->stats.vport.arg);
4400
4401         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4402             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4403             priv->stats.pport.arg);
4404
4405         mlx5e_create_ethtool(priv);
4406
4407         mtx_lock(&priv->async_events_mtx);
4408         mlx5e_update_stats(priv);
4409         mtx_unlock(&priv->async_events_mtx);
4410
4411         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4412             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4413             &priv->clbr_done, 0,
4414             "RX timestamps calibration state");
4415         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4416         mlx5e_reset_calibration_callout(priv);
4417
4418         pa.pa_version = PFIL_VERSION;
4419         pa.pa_flags = PFIL_IN;
4420         pa.pa_type = PFIL_TYPE_ETHERNET;
4421         pa.pa_headname = ifp->if_xname;
4422         priv->pfil = pfil_head_register(&pa);
4423
4424         return (priv);
4425
4426 #ifdef RATELIMIT
4427 err_create_mkey:
4428         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4429 #endif
4430 err_dealloc_transport_domain:
4431         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4432
4433 err_dealloc_pd:
4434         mlx5_core_dealloc_pd(mdev, priv->pdn);
4435
4436 err_unmap_free_uar:
4437         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4438
4439 err_free_wq:
4440         flush_workqueue(priv->wq);
4441
4442 err_free_sysctl:
4443         sysctl_ctx_free(&priv->sysctl_ctx);
4444         if (priv->sysctl_debug)
4445                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4446         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4447         if_free(ifp);
4448
4449 err_free_priv:
4450         free(priv, M_MLX5EN);
4451         return (NULL);
4452 }
4453
4454 static void
4455 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4456 {
4457         struct mlx5e_priv *priv = vpriv;
4458         struct ifnet *ifp = priv->ifp;
4459
4460         /* don't allow more IOCTLs */
4461         priv->gone = 1;
4462
4463         /* XXX wait a bit to allow IOCTL handlers to complete */
4464         pause("W", hz);
4465
4466 #ifdef RATELIMIT
4467         /*
4468          * The kernel can have reference(s) via the m_snd_tag's into
4469          * the ratelimit channels, and these must go away before
4470          * detaching:
4471          */
4472         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4473                 mlx5_en_err(priv->ifp,
4474                     "Waiting for all ratelimit connections to terminate\n");
4475                 pause("W", hz);
4476         }
4477 #endif
4478         /* wait for all unlimited send tags to complete */
4479         mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4480
4481         /* stop watchdog timer */
4482         callout_drain(&priv->watchdog);
4483
4484         callout_drain(&priv->tstmp_clbr);
4485
4486         if (priv->vlan_attach != NULL)
4487                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4488         if (priv->vlan_detach != NULL)
4489                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4490
4491         /* make sure device gets closed */
4492         PRIV_LOCK(priv);
4493         mlx5e_close_locked(ifp);
4494         PRIV_UNLOCK(priv);
4495
4496         /* deregister pfil */
4497         if (priv->pfil != NULL) {
4498                 pfil_head_unregister(priv->pfil);
4499                 priv->pfil = NULL;
4500         }
4501
4502         /* unregister device */
4503         ifmedia_removeall(&priv->media);
4504         ether_ifdetach(ifp);
4505
4506 #ifdef RATELIMIT
4507         mlx5e_rl_cleanup(priv);
4508 #endif
4509         /* destroy all remaining sysctl nodes */
4510         sysctl_ctx_free(&priv->stats.vport.ctx);
4511         sysctl_ctx_free(&priv->stats.pport.ctx);
4512         if (priv->sysctl_debug)
4513                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4514         sysctl_ctx_free(&priv->sysctl_ctx);
4515
4516         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4517         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4518         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4519         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4520         mlx5e_disable_async_events(priv);
4521         flush_workqueue(priv->wq);
4522         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4523         if_free(ifp);
4524         free(priv, M_MLX5EN);
4525 }
4526
4527 static void *
4528 mlx5e_get_ifp(void *vpriv)
4529 {
4530         struct mlx5e_priv *priv = vpriv;
4531
4532         return (priv->ifp);
4533 }
4534
4535 static struct mlx5_interface mlx5e_interface = {
4536         .add = mlx5e_create_ifp,
4537         .remove = mlx5e_destroy_ifp,
4538         .event = mlx5e_async_event,
4539         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4540         .get_dev = mlx5e_get_ifp,
4541 };
4542
4543 void
4544 mlx5e_init(void)
4545 {
4546         mlx5_register_interface(&mlx5e_interface);
4547 }
4548
4549 void
4550 mlx5e_cleanup(void)
4551 {
4552         mlx5_unregister_interface(&mlx5e_interface);
4553 }
4554
4555 static void
4556 mlx5e_show_version(void __unused *arg)
4557 {
4558
4559         printf("%s", mlx5e_version);
4560 }
4561 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4562
4563 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4564 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4565
4566 #if (__FreeBSD_version >= 1100000)
4567 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4568 #endif
4569 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4570 MODULE_VERSION(mlx5en, 1);