sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.4.2"
  35 #endif
  36
  37 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  38         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  39
  40 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  41
  42 struct mlx5e_channel_param {
  43         struct mlx5e_rq_param rq;
  44         struct mlx5e_sq_param sq;
  45         struct mlx5e_cq_param rx_cq;
  46         struct mlx5e_cq_param tx_cq;
  47 };
  48
  49 static const struct {
  50         u32     subtype;
  51         u64     baudrate;
  52 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  53
  54         [MLX5E_1000BASE_CX_SGMII] = {
  55                 .subtype = IFM_1000_CX_SGMII,
  56                 .baudrate = IF_Mbps(1000ULL),
  57         },
  58         [MLX5E_1000BASE_KX] = {
  59                 .subtype = IFM_1000_KX,
  60                 .baudrate = IF_Mbps(1000ULL),
  61         },
  62         [MLX5E_10GBASE_CX4] = {
  63                 .subtype = IFM_10G_CX4,
  64                 .baudrate = IF_Gbps(10ULL),
  65         },
  66         [MLX5E_10GBASE_KX4] = {
  67                 .subtype = IFM_10G_KX4,
  68                 .baudrate = IF_Gbps(10ULL),
  69         },
  70         [MLX5E_10GBASE_KR] = {
  71                 .subtype = IFM_10G_KR,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_20GBASE_KR2] = {
  75                 .subtype = IFM_20G_KR2,
  76                 .baudrate = IF_Gbps(20ULL),
  77         },
  78         [MLX5E_40GBASE_CR4] = {
  79                 .subtype = IFM_40G_CR4,
  80                 .baudrate = IF_Gbps(40ULL),
  81         },
  82         [MLX5E_40GBASE_KR4] = {
  83                 .subtype = IFM_40G_KR4,
  84                 .baudrate = IF_Gbps(40ULL),
  85         },
  86         [MLX5E_56GBASE_R4] = {
  87                 .subtype = IFM_56G_R4,
  88                 .baudrate = IF_Gbps(56ULL),
  89         },
  90         [MLX5E_10GBASE_CR] = {
  91                 .subtype = IFM_10G_CR1,
  92                 .baudrate = IF_Gbps(10ULL),
  93         },
  94         [MLX5E_10GBASE_SR] = {
  95                 .subtype = IFM_10G_SR,
  96                 .baudrate = IF_Gbps(10ULL),
  97         },
  98         [MLX5E_10GBASE_ER] = {
  99                 .subtype = IFM_10G_ER,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_40GBASE_SR4] = {
 103                 .subtype = IFM_40G_SR4,
 104                 .baudrate = IF_Gbps(40ULL),
 105         },
 106         [MLX5E_40GBASE_LR4] = {
 107                 .subtype = IFM_40G_LR4,
 108                 .baudrate = IF_Gbps(40ULL),
 109         },
 110         [MLX5E_100GBASE_CR4] = {
 111                 .subtype = IFM_100G_CR4,
 112                 .baudrate = IF_Gbps(100ULL),
 113         },
 114         [MLX5E_100GBASE_SR4] = {
 115                 .subtype = IFM_100G_SR4,
 116                 .baudrate = IF_Gbps(100ULL),
 117         },
 118         [MLX5E_100GBASE_KR4] = {
 119                 .subtype = IFM_100G_KR4,
 120                 .baudrate = IF_Gbps(100ULL),
 121         },
 122         [MLX5E_100GBASE_LR4] = {
 123                 .subtype = IFM_100G_LR4,
 124                 .baudrate = IF_Gbps(100ULL),
 125         },
 126         [MLX5E_100BASE_TX] = {
 127                 .subtype = IFM_100_TX,
 128                 .baudrate = IF_Mbps(100ULL),
 129         },
 130         [MLX5E_1000BASE_T] = {
 131                 .subtype = IFM_1000_T,
 132                 .baudrate = IF_Mbps(1000ULL),
 133         },
 134         [MLX5E_10GBASE_T] = {
 135                 .subtype = IFM_10G_T,
 136                 .baudrate = IF_Gbps(10ULL),
 137         },
 138         [MLX5E_25GBASE_CR] = {
 139                 .subtype = IFM_25G_CR,
 140                 .baudrate = IF_Gbps(25ULL),
 141         },
 142         [MLX5E_25GBASE_KR] = {
 143                 .subtype = IFM_25G_KR,
 144                 .baudrate = IF_Gbps(25ULL),
 145         },
 146         [MLX5E_25GBASE_SR] = {
 147                 .subtype = IFM_25G_SR,
 148                 .baudrate = IF_Gbps(25ULL),
 149         },
 150         [MLX5E_50GBASE_CR2] = {
 151                 .subtype = IFM_50G_CR2,
 152                 .baudrate = IF_Gbps(50ULL),
 153         },
 154         [MLX5E_50GBASE_KR2] = {
 155                 .subtype = IFM_50G_KR2,
 156                 .baudrate = IF_Gbps(50ULL),
 157         },
 158 };
 159
 160 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 161
 162 static void
 163 mlx5e_update_carrier(struct mlx5e_priv *priv)
 164 {
 165         struct mlx5_core_dev *mdev = priv->mdev;
 166         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 167         u32 eth_proto_oper;
 168         int error;
 169         u8 port_state;
 170         u8 is_er_type;
 171         u8 i;
 172
 173         port_state = mlx5_query_vport_state(mdev,
 174             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 175
 176         if (port_state == VPORT_STATE_UP) {
 177                 priv->media_status_last |= IFM_ACTIVE;
 178         } else {
 179                 priv->media_status_last &= ~IFM_ACTIVE;
 180                 priv->media_active_last = IFM_ETHER;
 181                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 182                 return;
 183         }
 184
 185         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 186         if (error) {
 187                 priv->media_active_last = IFM_ETHER;
 188                 priv->ifp->if_baudrate = 1;
 189                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 190                     __func__, error);
 191                 return;
 192         }
 193         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 194
 195         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 196                 if (mlx5e_mode_table[i].baudrate == 0)
 197                         continue;
 198                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 199                         u32 subtype = mlx5e_mode_table[i].subtype;
 200
 201                         priv->ifp->if_baudrate =
 202                             mlx5e_mode_table[i].baudrate;
 203
 204                         switch (subtype) {
 205                         case IFM_10G_ER:
 206                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 207                                 if (error != 0) {
 208                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 209                                             __func__, error);
 210                                 }
 211                                 if (error != 0 || is_er_type == 0)
 212                                         subtype = IFM_10G_LR;
 213                                 break;
 214                         case IFM_40G_LR4:
 215                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 216                                 if (error != 0) {
 217                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 218                                             __func__, error);
 219                                 }
 220                                 if (error == 0 && is_er_type != 0)
 221                                         subtype = IFM_40G_ER4;
 222                                 break;
 223                         }
 224                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 225                         break;
 226                 }
 227         }
 228         if_link_state_change(priv->ifp, LINK_STATE_UP);
 229 }
 230
 231 static void
 232 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 233 {
 234         struct mlx5e_priv *priv = dev->if_softc;
 235
 236         ifmr->ifm_status = priv->media_status_last;
 237         ifmr->ifm_active = priv->media_active_last |
 238             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 239             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 240
 241 }
 242
 243 static u32
 244 mlx5e_find_link_mode(u32 subtype)
 245 {
 246         u32 i;
 247         u32 link_mode = 0;
 248
 249         switch (subtype) {
 250         case IFM_10G_LR:
 251                 subtype = IFM_10G_ER;
 252                 break;
 253         case IFM_40G_ER4:
 254                 subtype = IFM_40G_LR4;
 255                 break;
 256         }
 257
 258         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 259                 if (mlx5e_mode_table[i].baudrate == 0)
 260                         continue;
 261                 if (mlx5e_mode_table[i].subtype == subtype)
 262                         link_mode |= MLX5E_PROT_MASK(i);
 263         }
 264
 265         return (link_mode);
 266 }
 267
 268 static int
 269 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 270 {
 271         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 272             priv->params.rx_pauseframe_control,
 273             priv->params.tx_pauseframe_control,
 274             priv->params.rx_priority_flow_control,
 275             priv->params.tx_priority_flow_control));
 276 }
 277
 278 static int
 279 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 280 {
 281         int error;
 282
 283         if (priv->params.rx_pauseframe_control ||
 284             priv->params.tx_pauseframe_control) {
 285                 if_printf(priv->ifp,
 286                     "Global pauseframes must be disabled before enabling PFC.\n");
 287                 error = -EINVAL;
 288         } else {
 289                 error = mlx5e_set_port_pause_and_pfc(priv);
 290         }
 291         return (error);
 292 }
 293
 294 static int
 295 mlx5e_media_change(struct ifnet *dev)
 296 {
 297         struct mlx5e_priv *priv = dev->if_softc;
 298         struct mlx5_core_dev *mdev = priv->mdev;
 299         u32 eth_proto_cap;
 300         u32 link_mode;
 301         int was_opened;
 302         int locked;
 303         int error;
 304
 305         locked = PRIV_LOCKED(priv);
 306         if (!locked)
 307                 PRIV_LOCK(priv);
 308
 309         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 310                 error = EINVAL;
 311                 goto done;
 312         }
 313         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 314
 315         /* query supported capabilities */
 316         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 317         if (error != 0) {
 318                 if_printf(dev, "Query port media capability failed\n");
 319                 goto done;
 320         }
 321         /* check for autoselect */
 322         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 323                 link_mode = eth_proto_cap;
 324                 if (link_mode == 0) {
 325                         if_printf(dev, "Port media capability is zero\n");
 326                         error = EINVAL;
 327                         goto done;
 328                 }
 329         } else {
 330                 link_mode = link_mode & eth_proto_cap;
 331                 if (link_mode == 0) {
 332                         if_printf(dev, "Not supported link mode requested\n");
 333                         error = EINVAL;
 334                         goto done;
 335                 }
 336         }
 337         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 338                 /* check if PFC is enabled */
 339                 if (priv->params.rx_priority_flow_control ||
 340                     priv->params.tx_priority_flow_control) {
 341                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 342                         error = EINVAL;
 343                         goto done;
 344                 }
 345         }
 346         /* update pauseframe control bits */
 347         priv->params.rx_pauseframe_control =
 348             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 349         priv->params.tx_pauseframe_control =
 350             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 351
 352         /* check if device is opened */
 353         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 354
 355         /* reconfigure the hardware */
 356         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 357         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 358         error = -mlx5e_set_port_pause_and_pfc(priv);
 359         if (was_opened)
 360                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 361
 362 done:
 363         if (!locked)
 364                 PRIV_UNLOCK(priv);
 365         return (error);
 366 }
 367
 368 static void
 369 mlx5e_update_carrier_work(struct work_struct *work)
 370 {
 371         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 372             update_carrier_work);
 373
 374         PRIV_LOCK(priv);
 375         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 376                 mlx5e_update_carrier(priv);
 377         PRIV_UNLOCK(priv);
 378 }
 379
 380 /*
 381  * This function reads the physical port counters from the firmware
 382  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 383  * macros. The output is converted from big-endian 64-bit values into
 384  * host endian ones and stored in the "priv->stats.pport" structure.
 385  */
 386 static void
 387 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 388 {
 389         struct mlx5_core_dev *mdev = priv->mdev;
 390         struct mlx5e_pport_stats *s = &priv->stats.pport;
 391         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 392         u32 *in;
 393         u32 *out;
 394         const u64 *ptr;
 395         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 396         unsigned x;
 397         unsigned y;
 398         unsigned z;
 399
 400         /* allocate firmware request structures */
 401         in = mlx5_vzalloc(sz);
 402         out = mlx5_vzalloc(sz);
 403         if (in == NULL || out == NULL)
 404                 goto free_out;
 405
 406         /*
 407          * Get pointer to the 64-bit counter set which is located at a
 408          * fixed offset in the output firmware request structure:
 409          */
 410         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 411
 412         MLX5_SET(ppcnt_reg, in, local_port, 1);
 413
 414         /* read IEEE802_3 counter group using predefined counter layout */
 415         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 416         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 417         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 418              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 419                 s->arg[y] = be64toh(ptr[x]);
 420
 421         /* read RFC2819 counter group using predefined counter layout */
 422         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 423         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 424         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 425                 s->arg[y] = be64toh(ptr[x]);
 426         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 427             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 428                 s_debug->arg[y] = be64toh(ptr[x]);
 429
 430         /* read RFC2863 counter group using predefined counter layout */
 431         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 432         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 433         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 434                 s_debug->arg[y] = be64toh(ptr[x]);
 435
 436         /* read physical layer stats counter group using predefined counter layout */
 437         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 438         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 439         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 440                 s_debug->arg[y] = be64toh(ptr[x]);
 441
 442         /* read per-priority counters */
 443         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 444
 445         /* iterate all the priorities */
 446         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 447                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 448                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 449
 450                 /* read per priority stats counter group using predefined counter layout */
 451                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 452                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 453                         s->arg[y] = be64toh(ptr[x]);
 454         }
 455 free_out:
 456         /* free firmware request structures */
 457         kvfree(in);
 458         kvfree(out);
 459 }
 460
 461 /*
 462  * This function is called regularly to collect all statistics
 463  * counters from the firmware. The values can be viewed through the
 464  * sysctl interface. Execution is serialized using the priv's global
 465  * configuration lock.
 466  */
 467 static void
 468 mlx5e_update_stats_work(struct work_struct *work)
 469 {
 470         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 471             update_stats_work);
 472         struct mlx5_core_dev *mdev = priv->mdev;
 473         struct mlx5e_vport_stats *s = &priv->stats.vport;
 474         struct mlx5e_sq_stats *sq_stats;
 475         struct buf_ring *sq_br;
 476 #if (__FreeBSD_version < 1100000)
 477         struct ifnet *ifp = priv->ifp;
 478 #endif
 479
 480         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 481         u32 *out;
 482         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 483         u64 tso_packets = 0;
 484         u64 tso_bytes = 0;
 485         u64 tx_queue_dropped = 0;
 486         u64 tx_defragged = 0;
 487         u64 tx_offload_none = 0;
 488         u64 lro_packets = 0;
 489         u64 lro_bytes = 0;
 490         u64 sw_lro_queued = 0;
 491         u64 sw_lro_flushed = 0;
 492         u64 rx_csum_none = 0;
 493         u64 rx_wqe_err = 0;
 494         u32 rx_out_of_buffer = 0;
 495         int i;
 496         int j;
 497
 498         PRIV_LOCK(priv);
 499         out = mlx5_vzalloc(outlen);
 500         if (out == NULL)
 501                 goto free_out;
 502         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 503                 goto free_out;
 504
 505         /* Collect firts the SW counters and then HW for consistency */
 506         for (i = 0; i < priv->params.num_channels; i++) {
 507                 struct mlx5e_channel *pch = priv->channel + i;
 508                 struct mlx5e_rq *rq = &pch->rq;
 509                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 510
 511                 /* collect stats from LRO */
 512                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 513                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 514                 sw_lro_queued += rq_stats->sw_lro_queued;
 515                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 516                 lro_packets += rq_stats->lro_packets;
 517                 lro_bytes += rq_stats->lro_bytes;
 518                 rx_csum_none += rq_stats->csum_none;
 519                 rx_wqe_err += rq_stats->wqe_err;
 520
 521                 for (j = 0; j < priv->num_tc; j++) {
 522                         sq_stats = &pch->sq[j].stats;
 523                         sq_br = pch->sq[j].br;
 524
 525                         tso_packets += sq_stats->tso_packets;
 526                         tso_bytes += sq_stats->tso_bytes;
 527                         tx_queue_dropped += sq_stats->dropped;
 528                         if (sq_br != NULL)
 529                                 tx_queue_dropped += sq_br->br_drops;
 530                         tx_defragged += sq_stats->defragged;
 531                         tx_offload_none += sq_stats->csum_offload_none;
 532                 }
 533         }
 534
 535         s->tx_jumbo_packets =
 536             priv->stats.port_stats_debug.p1519to2047octets +
 537             priv->stats.port_stats_debug.p2048to4095octets +
 538             priv->stats.port_stats_debug.p4096to8191octets +
 539             priv->stats.port_stats_debug.p8192to10239octets;
 540
 541         /* update counters */
 542         s->tso_packets = tso_packets;
 543         s->tso_bytes = tso_bytes;
 544         s->tx_queue_dropped = tx_queue_dropped;
 545         s->tx_defragged = tx_defragged;
 546         s->lro_packets = lro_packets;
 547         s->lro_bytes = lro_bytes;
 548         s->sw_lro_queued = sw_lro_queued;
 549         s->sw_lro_flushed = sw_lro_flushed;
 550         s->rx_csum_none = rx_csum_none;
 551         s->rx_wqe_err = rx_wqe_err;
 552
 553         /* HW counters */
 554         memset(in, 0, sizeof(in));
 555
 556         MLX5_SET(query_vport_counter_in, in, opcode,
 557             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 558         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 559         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 560
 561         memset(out, 0, outlen);
 562
 563         /* get number of out-of-buffer drops first */
 564         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 565             &rx_out_of_buffer))
 566                 goto free_out;
 567
 568         /* accumulate difference into a 64-bit counter */
 569         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 570         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 571
 572         /* get port statistics */
 573         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 574                 goto free_out;
 575
 576 #define MLX5_GET_CTR(out, x) \
 577         MLX5_GET64(query_vport_counter_out, out, x)
 578
 579         s->rx_error_packets =
 580             MLX5_GET_CTR(out, received_errors.packets);
 581         s->rx_error_bytes =
 582             MLX5_GET_CTR(out, received_errors.octets);
 583         s->tx_error_packets =
 584             MLX5_GET_CTR(out, transmit_errors.packets);
 585         s->tx_error_bytes =
 586             MLX5_GET_CTR(out, transmit_errors.octets);
 587
 588         s->rx_unicast_packets =
 589             MLX5_GET_CTR(out, received_eth_unicast.packets);
 590         s->rx_unicast_bytes =
 591             MLX5_GET_CTR(out, received_eth_unicast.octets);
 592         s->tx_unicast_packets =
 593             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 594         s->tx_unicast_bytes =
 595             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 596
 597         s->rx_multicast_packets =
 598             MLX5_GET_CTR(out, received_eth_multicast.packets);
 599         s->rx_multicast_bytes =
 600             MLX5_GET_CTR(out, received_eth_multicast.octets);
 601         s->tx_multicast_packets =
 602             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 603         s->tx_multicast_bytes =
 604             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 605
 606         s->rx_broadcast_packets =
 607             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 608         s->rx_broadcast_bytes =
 609             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 610         s->tx_broadcast_packets =
 611             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 612         s->tx_broadcast_bytes =
 613             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 614
 615         s->rx_packets =
 616             s->rx_unicast_packets +
 617             s->rx_multicast_packets +
 618             s->rx_broadcast_packets -
 619             s->rx_out_of_buffer;
 620         s->rx_bytes =
 621             s->rx_unicast_bytes +
 622             s->rx_multicast_bytes +
 623             s->rx_broadcast_bytes;
 624         s->tx_packets =
 625             s->tx_unicast_packets +
 626             s->tx_multicast_packets +
 627             s->tx_broadcast_packets;
 628         s->tx_bytes =
 629             s->tx_unicast_bytes +
 630             s->tx_multicast_bytes +
 631             s->tx_broadcast_bytes;
 632
 633         /* Update calculated offload counters */
 634         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 635         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 636
 637         /* Get physical port counters */
 638         mlx5e_update_pport_counters(priv);
 639
 640 #if (__FreeBSD_version < 1100000)
 641         /* no get_counters interface in fbsd 10 */
 642         ifp->if_ipackets = s->rx_packets;
 643         ifp->if_ierrors = s->rx_error_packets +
 644             priv->stats.pport.alignment_err +
 645             priv->stats.pport.check_seq_err +
 646             priv->stats.pport.crc_align_errors +
 647             priv->stats.pport.in_range_len_errors +
 648             priv->stats.pport.jabbers +
 649             priv->stats.pport.out_of_range_len +
 650             priv->stats.pport.oversize_pkts +
 651             priv->stats.pport.symbol_err +
 652             priv->stats.pport.too_long_errors +
 653             priv->stats.pport.undersize_pkts +
 654             priv->stats.pport.unsupported_op_rx;
 655         ifp->if_iqdrops = s->rx_out_of_buffer +
 656             priv->stats.pport.drop_events;
 657         ifp->if_opackets = s->tx_packets;
 658         ifp->if_oerrors = s->tx_error_packets;
 659         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 660         ifp->if_ibytes = s->rx_bytes;
 661         ifp->if_obytes = s->tx_bytes;
 662         ifp->if_collisions =
 663             priv->stats.pport.collisions;
 664 #endif
 665
 666 free_out:
 667         kvfree(out);
 668
 669         /* Update diagnostics, if any */
 670         if (priv->params_ethtool.diag_pci_enable ||
 671             priv->params_ethtool.diag_general_enable) {
 672                 int error = mlx5_core_get_diagnostics_full(mdev,
 673                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 674                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 675                 if (error != 0)
 676                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 677         }
 678         PRIV_UNLOCK(priv);
 679 }
 680
 681 static void
 682 mlx5e_update_stats(void *arg)
 683 {
 684         struct mlx5e_priv *priv = arg;
 685
 686         queue_work(priv->wq, &priv->update_stats_work);
 687
 688         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 689 }
 690
 691 static void
 692 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 693     enum mlx5_dev_event event)
 694 {
 695         switch (event) {
 696         case MLX5_DEV_EVENT_PORT_UP:
 697         case MLX5_DEV_EVENT_PORT_DOWN:
 698                 queue_work(priv->wq, &priv->update_carrier_work);
 699                 break;
 700
 701         default:
 702                 break;
 703         }
 704 }
 705
 706 static void
 707 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 708     enum mlx5_dev_event event, unsigned long param)
 709 {
 710         struct mlx5e_priv *priv = vpriv;
 711
 712         mtx_lock(&priv->async_events_mtx);
 713         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 714                 mlx5e_async_event_sub(priv, event);
 715         mtx_unlock(&priv->async_events_mtx);
 716 }
 717
 718 static void
 719 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 720 {
 721         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 722 }
 723
 724 static void
 725 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 726 {
 727         mtx_lock(&priv->async_events_mtx);
 728         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 729         mtx_unlock(&priv->async_events_mtx);
 730 }
 731
 732 static const char *mlx5e_rq_stats_desc[] = {
 733         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 734 };
 735
 736 static int
 737 mlx5e_create_rq(struct mlx5e_channel *c,
 738     struct mlx5e_rq_param *param,
 739     struct mlx5e_rq *rq)
 740 {
 741         struct mlx5e_priv *priv = c->priv;
 742         struct mlx5_core_dev *mdev = priv->mdev;
 743         char buffer[16];
 744         void *rqc = param->rqc;
 745         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 746         int wq_sz;
 747         int err;
 748         int i;
 749         u32 nsegs, wqe_sz;
 750
 751         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 752         if (err != 0)
 753                 goto done;
 754
 755         /* Create DMA descriptor TAG */
 756         if ((err = -bus_dma_tag_create(
 757             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 758             1,                          /* any alignment */
 759             0,                          /* no boundary */
 760             BUS_SPACE_MAXADDR,          /* lowaddr */
 761             BUS_SPACE_MAXADDR,          /* highaddr */
 762             NULL, NULL,                 /* filter, filterarg */
 763             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 764             nsegs,                      /* nsegments */
 765             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 766             0,                          /* flags */
 767             NULL, NULL,                 /* lockfunc, lockfuncarg */
 768             &rq->dma_tag)))
 769                 goto done;
 770
 771         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 772             &rq->wq_ctrl);
 773         if (err)
 774                 goto err_free_dma_tag;
 775
 776         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 777
 778         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 779         if (err != 0)
 780                 goto err_rq_wq_destroy;
 781
 782         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 783
 784         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 785         if (err)
 786                 goto err_rq_wq_destroy;
 787
 788         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 789         for (i = 0; i != wq_sz; i++) {
 790                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 791 #if (MLX5E_MAX_RX_SEGS == 1)
 792                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 793 #else
 794                 int j;
 795 #endif
 796
 797                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 798                 if (err != 0) {
 799                         while (i--)
 800                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 801                         goto err_rq_mbuf_free;
 802                 }
 803
 804                 /* set value for constant fields */
 805 #if (MLX5E_MAX_RX_SEGS == 1)
 806                 wqe->data[0].lkey = c->mkey_be;
 807                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 808 #else
 809                 for (j = 0; j < rq->nsegs; j++)
 810                         wqe->data[j].lkey = c->mkey_be;
 811 #endif
 812         }
 813
 814         rq->ifp = c->ifp;
 815         rq->channel = c;
 816         rq->ix = c->ix;
 817
 818         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 819         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 820             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 821             rq->stats.arg);
 822         return (0);
 823
 824 err_rq_mbuf_free:
 825         free(rq->mbuf, M_MLX5EN);
 826         tcp_lro_free(&rq->lro);
 827 err_rq_wq_destroy:
 828         mlx5_wq_destroy(&rq->wq_ctrl);
 829 err_free_dma_tag:
 830         bus_dma_tag_destroy(rq->dma_tag);
 831 done:
 832         return (err);
 833 }
 834
 835 static void
 836 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 837 {
 838         int wq_sz;
 839         int i;
 840
 841         /* destroy all sysctl nodes */
 842         sysctl_ctx_free(&rq->stats.ctx);
 843
 844         /* free leftover LRO packets, if any */
 845         tcp_lro_free(&rq->lro);
 846
 847         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 848         for (i = 0; i != wq_sz; i++) {
 849                 if (rq->mbuf[i].mbuf != NULL) {
 850                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 851                         m_freem(rq->mbuf[i].mbuf);
 852                 }
 853                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 854         }
 855         free(rq->mbuf, M_MLX5EN);
 856         mlx5_wq_destroy(&rq->wq_ctrl);
 857 }
 858
 859 static int
 860 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 861 {
 862         struct mlx5e_channel *c = rq->channel;
 863         struct mlx5e_priv *priv = c->priv;
 864         struct mlx5_core_dev *mdev = priv->mdev;
 865
 866         void *in;
 867         void *rqc;
 868         void *wq;
 869         int inlen;
 870         int err;
 871
 872         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 873             sizeof(u64) * rq->wq_ctrl.buf.npages;
 874         in = mlx5_vzalloc(inlen);
 875         if (in == NULL)
 876                 return (-ENOMEM);
 877
 878         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 879         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 880
 881         memcpy(rqc, param->rqc, sizeof(param->rqc));
 882
 883         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 884         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 885         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 886         if (priv->counter_set_id >= 0)
 887                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 888         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 889             PAGE_SHIFT);
 890         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 891
 892         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 893             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 894
 895         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 896
 897         kvfree(in);
 898
 899         return (err);
 900 }
 901
 902 static int
 903 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 904 {
 905         struct mlx5e_channel *c = rq->channel;
 906         struct mlx5e_priv *priv = c->priv;
 907         struct mlx5_core_dev *mdev = priv->mdev;
 908
 909         void *in;
 910         void *rqc;
 911         int inlen;
 912         int err;
 913
 914         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 915         in = mlx5_vzalloc(inlen);
 916         if (in == NULL)
 917                 return (-ENOMEM);
 918
 919         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 920
 921         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 922         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 923         MLX5_SET(rqc, rqc, state, next_state);
 924
 925         err = mlx5_core_modify_rq(mdev, in, inlen);
 926
 927         kvfree(in);
 928
 929         return (err);
 930 }
 931
 932 static void
 933 mlx5e_disable_rq(struct mlx5e_rq *rq)
 934 {
 935         struct mlx5e_channel *c = rq->channel;
 936         struct mlx5e_priv *priv = c->priv;
 937         struct mlx5_core_dev *mdev = priv->mdev;
 938
 939         mlx5_core_destroy_rq(mdev, rq->rqn);
 940 }
 941
 942 static int
 943 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 944 {
 945         struct mlx5e_channel *c = rq->channel;
 946         struct mlx5e_priv *priv = c->priv;
 947         struct mlx5_wq_ll *wq = &rq->wq;
 948         int i;
 949
 950         for (i = 0; i < 1000; i++) {
 951                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 952                         return (0);
 953
 954                 msleep(4);
 955         }
 956         return (-ETIMEDOUT);
 957 }
 958
 959 static int
 960 mlx5e_open_rq(struct mlx5e_channel *c,
 961     struct mlx5e_rq_param *param,
 962     struct mlx5e_rq *rq)
 963 {
 964         int err;
 965
 966         err = mlx5e_create_rq(c, param, rq);
 967         if (err)
 968                 return (err);
 969
 970         err = mlx5e_enable_rq(rq, param);
 971         if (err)
 972                 goto err_destroy_rq;
 973
 974         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 975         if (err)
 976                 goto err_disable_rq;
 977
 978         c->rq.enabled = 1;
 979
 980         return (0);
 981
 982 err_disable_rq:
 983         mlx5e_disable_rq(rq);
 984 err_destroy_rq:
 985         mlx5e_destroy_rq(rq);
 986
 987         return (err);
 988 }
 989
 990 static void
 991 mlx5e_close_rq(struct mlx5e_rq *rq)
 992 {
 993         mtx_lock(&rq->mtx);
 994         rq->enabled = 0;
 995         callout_stop(&rq->watchdog);
 996         mtx_unlock(&rq->mtx);
 997
 998         callout_drain(&rq->watchdog);
 999
1000         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1001 }
1002
1003 static void
1004 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1005 {
1006         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1007
1008         /* wait till RQ is empty */
1009         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1010                (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1011                 msleep(4);
1012                 rq->cq.mcq.comp(&rq->cq.mcq);
1013         }
1014
1015         mlx5e_disable_rq(rq);
1016         mlx5e_destroy_rq(rq);
1017 }
1018
1019 void
1020 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1021 {
1022         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1023         int x;
1024
1025         for (x = 0; x != wq_sz; x++)
1026                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1027         free(sq->mbuf, M_MLX5EN);
1028 }
1029
1030 int
1031 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1032 {
1033         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1034         int err;
1035         int x;
1036
1037         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1038
1039         /* Create DMA descriptor MAPs */
1040         for (x = 0; x != wq_sz; x++) {
1041                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1042                 if (err != 0) {
1043                         while (x--)
1044                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1045                         free(sq->mbuf, M_MLX5EN);
1046                         return (err);
1047                 }
1048         }
1049         return (0);
1050 }
1051
1052 static const char *mlx5e_sq_stats_desc[] = {
1053         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1054 };
1055
1056 void
1057 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1058 {
1059         sq->max_inline = sq->priv->params.tx_max_inline;
1060         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1061
1062         /*
1063          * Check if trust state is DSCP or if inline mode is NONE which
1064          * indicates CX-5 or newer hardware.
1065          */
1066         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1067             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1068                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1069                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1070                 else
1071                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1072         } else {
1073                 sq->min_insert_caps = 0;
1074         }
1075 }
1076
1077 static void
1078 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1079 {
1080         int i;
1081
1082         for (i = 0; i != c->num_tc; i++) {
1083                 mtx_lock(&c->sq[i].lock);
1084                 mlx5e_update_sq_inline(&c->sq[i]);
1085                 mtx_unlock(&c->sq[i].lock);
1086         }
1087 }
1088
1089 void
1090 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1091 {
1092         int i;
1093
1094         /* check if channels are closed */
1095         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1096                 return;
1097
1098         for (i = 0; i < priv->params.num_channels; i++)
1099                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1100 }
1101
1102 static int
1103 mlx5e_create_sq(struct mlx5e_channel *c,
1104     int tc,
1105     struct mlx5e_sq_param *param,
1106     struct mlx5e_sq *sq)
1107 {
1108         struct mlx5e_priv *priv = c->priv;
1109         struct mlx5_core_dev *mdev = priv->mdev;
1110         char buffer[16];
1111         void *sqc = param->sqc;
1112         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1113         int err;
1114
1115         /* Create DMA descriptor TAG */
1116         if ((err = -bus_dma_tag_create(
1117             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1118             1,                          /* any alignment */
1119             0,                          /* no boundary */
1120             BUS_SPACE_MAXADDR,          /* lowaddr */
1121             BUS_SPACE_MAXADDR,          /* highaddr */
1122             NULL, NULL,                 /* filter, filterarg */
1123             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1124             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1125             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1126             0,                          /* flags */
1127             NULL, NULL,                 /* lockfunc, lockfuncarg */
1128             &sq->dma_tag)))
1129                 goto done;
1130
1131         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1132         if (err)
1133                 goto err_free_dma_tag;
1134
1135         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1136             &sq->wq_ctrl);
1137         if (err)
1138                 goto err_unmap_free_uar;
1139
1140         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1141         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1142
1143         err = mlx5e_alloc_sq_db(sq);
1144         if (err)
1145                 goto err_sq_wq_destroy;
1146
1147         sq->mkey_be = c->mkey_be;
1148         sq->ifp = priv->ifp;
1149         sq->priv = priv;
1150         sq->tc = tc;
1151
1152         mlx5e_update_sq_inline(sq);
1153
1154         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1155         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1156             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1157             sq->stats.arg);
1158
1159         return (0);
1160
1161 err_sq_wq_destroy:
1162         mlx5_wq_destroy(&sq->wq_ctrl);
1163
1164 err_unmap_free_uar:
1165         mlx5_unmap_free_uar(mdev, &sq->uar);
1166
1167 err_free_dma_tag:
1168         bus_dma_tag_destroy(sq->dma_tag);
1169 done:
1170         return (err);
1171 }
1172
1173 static void
1174 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1175 {
1176         /* destroy all sysctl nodes */
1177         sysctl_ctx_free(&sq->stats.ctx);
1178
1179         mlx5e_free_sq_db(sq);
1180         mlx5_wq_destroy(&sq->wq_ctrl);
1181         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1182 }
1183
1184 int
1185 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1186     int tis_num)
1187 {
1188         void *in;
1189         void *sqc;
1190         void *wq;
1191         int inlen;
1192         int err;
1193
1194         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1195             sizeof(u64) * sq->wq_ctrl.buf.npages;
1196         in = mlx5_vzalloc(inlen);
1197         if (in == NULL)
1198                 return (-ENOMEM);
1199
1200         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1201         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1202
1203         memcpy(sqc, param->sqc, sizeof(param->sqc));
1204
1205         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1206         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1207         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1208         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1209         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1210
1211         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1212         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1213         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1214             PAGE_SHIFT);
1215         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1216
1217         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1218             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1219
1220         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1221
1222         kvfree(in);
1223
1224         return (err);
1225 }
1226
1227 int
1228 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1229 {
1230         void *in;
1231         void *sqc;
1232         int inlen;
1233         int err;
1234
1235         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1236         in = mlx5_vzalloc(inlen);
1237         if (in == NULL)
1238                 return (-ENOMEM);
1239
1240         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1241
1242         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1243         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1244         MLX5_SET(sqc, sqc, state, next_state);
1245
1246         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1247
1248         kvfree(in);
1249
1250         return (err);
1251 }
1252
1253 void
1254 mlx5e_disable_sq(struct mlx5e_sq *sq)
1255 {
1256
1257         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1258 }
1259
1260 static int
1261 mlx5e_open_sq(struct mlx5e_channel *c,
1262     int tc,
1263     struct mlx5e_sq_param *param,
1264     struct mlx5e_sq *sq)
1265 {
1266         int err;
1267
1268         err = mlx5e_create_sq(c, tc, param, sq);
1269         if (err)
1270                 return (err);
1271
1272         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1273         if (err)
1274                 goto err_destroy_sq;
1275
1276         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1277         if (err)
1278                 goto err_disable_sq;
1279
1280         WRITE_ONCE(sq->running, 1);
1281
1282         return (0);
1283
1284 err_disable_sq:
1285         mlx5e_disable_sq(sq);
1286 err_destroy_sq:
1287         mlx5e_destroy_sq(sq);
1288
1289         return (err);
1290 }
1291
1292 static void
1293 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1294 {
1295         /* fill up remainder with NOPs */
1296         while (sq->cev_counter != 0) {
1297                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1298                         if (can_sleep != 0) {
1299                                 mtx_unlock(&sq->lock);
1300                                 msleep(4);
1301                                 mtx_lock(&sq->lock);
1302                         } else {
1303                                 goto done;
1304                         }
1305                 }
1306                 /* send a single NOP */
1307                 mlx5e_send_nop(sq, 1);
1308                 atomic_thread_fence_rel();
1309         }
1310 done:
1311         /* Check if we need to write the doorbell */
1312         if (likely(sq->doorbell.d64 != 0)) {
1313                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1314                 sq->doorbell.d64 = 0;
1315         }
1316 }
1317
1318 void
1319 mlx5e_sq_cev_timeout(void *arg)
1320 {
1321         struct mlx5e_sq *sq = arg;
1322
1323         mtx_assert(&sq->lock, MA_OWNED);
1324
1325         /* check next state */
1326         switch (sq->cev_next_state) {
1327         case MLX5E_CEV_STATE_SEND_NOPS:
1328                 /* fill TX ring with NOPs, if any */
1329                 mlx5e_sq_send_nops_locked(sq, 0);
1330
1331                 /* check if completed */
1332                 if (sq->cev_counter == 0) {
1333                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1334                         return;
1335                 }
1336                 break;
1337         default:
1338                 /* send NOPs on next timeout */
1339                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1340                 break;
1341         }
1342
1343         /* restart timer */
1344         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1345 }
1346
1347 void
1348 mlx5e_drain_sq(struct mlx5e_sq *sq)
1349 {
1350         int error;
1351         struct mlx5_core_dev *mdev= sq->priv->mdev;
1352
1353         /*
1354          * Check if already stopped.
1355          *
1356          * NOTE: Serialization of this function is managed by the
1357          * caller ensuring the priv's state lock is locked or in case
1358          * of rate limit support, a single thread manages drain and
1359          * resume of SQs. The "running" variable can therefore safely
1360          * be read without any locks.
1361          */
1362         if (READ_ONCE(sq->running) == 0)
1363                 return;
1364
1365         /* don't put more packets into the SQ */
1366         WRITE_ONCE(sq->running, 0);
1367
1368         /* serialize access to DMA rings */
1369         mtx_lock(&sq->lock);
1370
1371         /* teardown event factor timer, if any */
1372         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1373         callout_stop(&sq->cev_callout);
1374
1375         /* send dummy NOPs in order to flush the transmit ring */
1376         mlx5e_sq_send_nops_locked(sq, 1);
1377         mtx_unlock(&sq->lock);
1378
1379         /* make sure it is safe to free the callout */
1380         callout_drain(&sq->cev_callout);
1381
1382         /* wait till SQ is empty or link is down */
1383         mtx_lock(&sq->lock);
1384         while (sq->cc != sq->pc &&
1385             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1386             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1387                 mtx_unlock(&sq->lock);
1388                 msleep(1);
1389                 sq->cq.mcq.comp(&sq->cq.mcq);
1390                 mtx_lock(&sq->lock);
1391         }
1392         mtx_unlock(&sq->lock);
1393
1394         /* error out remaining requests */
1395         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1396         if (error != 0) {
1397                 if_printf(sq->ifp,
1398                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1399         }
1400
1401         /* wait till SQ is empty */
1402         mtx_lock(&sq->lock);
1403         while (sq->cc != sq->pc &&
1404                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1405                 mtx_unlock(&sq->lock);
1406                 msleep(1);
1407                 sq->cq.mcq.comp(&sq->cq.mcq);
1408                 mtx_lock(&sq->lock);
1409         }
1410         mtx_unlock(&sq->lock);
1411 }
1412
1413 static void
1414 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1415 {
1416
1417         mlx5e_drain_sq(sq);
1418         mlx5e_disable_sq(sq);
1419         mlx5e_destroy_sq(sq);
1420 }
1421
1422 static int
1423 mlx5e_create_cq(struct mlx5e_priv *priv,
1424     struct mlx5e_cq_param *param,
1425     struct mlx5e_cq *cq,
1426     mlx5e_cq_comp_t *comp,
1427     int eq_ix)
1428 {
1429         struct mlx5_core_dev *mdev = priv->mdev;
1430         struct mlx5_core_cq *mcq = &cq->mcq;
1431         int eqn_not_used;
1432         int irqn;
1433         int err;
1434         u32 i;
1435
1436         param->wq.buf_numa_node = 0;
1437         param->wq.db_numa_node = 0;
1438
1439         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1440             &cq->wq_ctrl);
1441         if (err)
1442                 return (err);
1443
1444         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1445
1446         mcq->cqe_sz = 64;
1447         mcq->set_ci_db = cq->wq_ctrl.db.db;
1448         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1449         *mcq->set_ci_db = 0;
1450         *mcq->arm_db = 0;
1451         mcq->vector = eq_ix;
1452         mcq->comp = comp;
1453         mcq->event = mlx5e_cq_error_event;
1454         mcq->irqn = irqn;
1455         mcq->uar = &priv->cq_uar;
1456
1457         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1458                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1459
1460                 cqe->op_own = 0xf1;
1461         }
1462
1463         cq->priv = priv;
1464
1465         return (0);
1466 }
1467
1468 static void
1469 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1470 {
1471         mlx5_wq_destroy(&cq->wq_ctrl);
1472 }
1473
1474 static int
1475 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1476 {
1477         struct mlx5_core_cq *mcq = &cq->mcq;
1478         void *in;
1479         void *cqc;
1480         int inlen;
1481         int irqn_not_used;
1482         int eqn;
1483         int err;
1484
1485         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1486             sizeof(u64) * cq->wq_ctrl.buf.npages;
1487         in = mlx5_vzalloc(inlen);
1488         if (in == NULL)
1489                 return (-ENOMEM);
1490
1491         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1492
1493         memcpy(cqc, param->cqc, sizeof(param->cqc));
1494
1495         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1496             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1497
1498         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1499
1500         MLX5_SET(cqc, cqc, c_eqn, eqn);
1501         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1502         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1503             PAGE_SHIFT);
1504         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1505
1506         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1507
1508         kvfree(in);
1509
1510         if (err)
1511                 return (err);
1512
1513         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1514
1515         return (0);
1516 }
1517
1518 static void
1519 mlx5e_disable_cq(struct mlx5e_cq *cq)
1520 {
1521
1522         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1523 }
1524
1525 int
1526 mlx5e_open_cq(struct mlx5e_priv *priv,
1527     struct mlx5e_cq_param *param,
1528     struct mlx5e_cq *cq,
1529     mlx5e_cq_comp_t *comp,
1530     int eq_ix)
1531 {
1532         int err;
1533
1534         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1535         if (err)
1536                 return (err);
1537
1538         err = mlx5e_enable_cq(cq, param, eq_ix);
1539         if (err)
1540                 goto err_destroy_cq;
1541
1542         return (0);
1543
1544 err_destroy_cq:
1545         mlx5e_destroy_cq(cq);
1546
1547         return (err);
1548 }
1549
1550 void
1551 mlx5e_close_cq(struct mlx5e_cq *cq)
1552 {
1553         mlx5e_disable_cq(cq);
1554         mlx5e_destroy_cq(cq);
1555 }
1556
1557 static int
1558 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1559     struct mlx5e_channel_param *cparam)
1560 {
1561         int err;
1562         int tc;
1563
1564         for (tc = 0; tc < c->num_tc; tc++) {
1565                 /* open completion queue */
1566                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1567                     &mlx5e_tx_cq_comp, c->ix);
1568                 if (err)
1569                         goto err_close_tx_cqs;
1570         }
1571         return (0);
1572
1573 err_close_tx_cqs:
1574         for (tc--; tc >= 0; tc--)
1575                 mlx5e_close_cq(&c->sq[tc].cq);
1576
1577         return (err);
1578 }
1579
1580 static void
1581 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1582 {
1583         int tc;
1584
1585         for (tc = 0; tc < c->num_tc; tc++)
1586                 mlx5e_close_cq(&c->sq[tc].cq);
1587 }
1588
1589 static int
1590 mlx5e_open_sqs(struct mlx5e_channel *c,
1591     struct mlx5e_channel_param *cparam)
1592 {
1593         int err;
1594         int tc;
1595
1596         for (tc = 0; tc < c->num_tc; tc++) {
1597                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1598                 if (err)
1599                         goto err_close_sqs;
1600         }
1601
1602         return (0);
1603
1604 err_close_sqs:
1605         for (tc--; tc >= 0; tc--)
1606                 mlx5e_close_sq_wait(&c->sq[tc]);
1607
1608         return (err);
1609 }
1610
1611 static void
1612 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1613 {
1614         int tc;
1615
1616         for (tc = 0; tc < c->num_tc; tc++)
1617                 mlx5e_close_sq_wait(&c->sq[tc]);
1618 }
1619
1620 static void
1621 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1622 {
1623         int tc;
1624
1625         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1626
1627         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1628
1629         for (tc = 0; tc < c->num_tc; tc++) {
1630                 struct mlx5e_sq *sq = c->sq + tc;
1631
1632                 mtx_init(&sq->lock, "mlx5tx",
1633                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1634                 mtx_init(&sq->comp_lock, "mlx5comp",
1635                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1636
1637                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1638
1639                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1640
1641                 /* ensure the TX completion event factor is not zero */
1642                 if (sq->cev_factor == 0)
1643                         sq->cev_factor = 1;
1644         }
1645 }
1646
1647 static void
1648 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1649 {
1650         int tc;
1651
1652         mtx_destroy(&c->rq.mtx);
1653
1654         for (tc = 0; tc < c->num_tc; tc++) {
1655                 mtx_destroy(&c->sq[tc].lock);
1656                 mtx_destroy(&c->sq[tc].comp_lock);
1657         }
1658 }
1659
1660 static int
1661 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1662     struct mlx5e_channel_param *cparam,
1663     struct mlx5e_channel *c)
1664 {
1665         int err;
1666
1667         memset(c, 0, sizeof(*c));
1668
1669         c->priv = priv;
1670         c->ix = ix;
1671         c->ifp = priv->ifp;
1672         c->mkey_be = cpu_to_be32(priv->mr.key);
1673         c->num_tc = priv->num_tc;
1674
1675         /* init mutexes */
1676         mlx5e_chan_mtx_init(c);
1677
1678         /* open transmit completion queue */
1679         err = mlx5e_open_tx_cqs(c, cparam);
1680         if (err)
1681                 goto err_free;
1682
1683         /* open receive completion queue */
1684         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1685             &mlx5e_rx_cq_comp, c->ix);
1686         if (err)
1687                 goto err_close_tx_cqs;
1688
1689         err = mlx5e_open_sqs(c, cparam);
1690         if (err)
1691                 goto err_close_rx_cq;
1692
1693         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1694         if (err)
1695                 goto err_close_sqs;
1696
1697         /* poll receive queue initially */
1698         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1699
1700         return (0);
1701
1702 err_close_sqs:
1703         mlx5e_close_sqs_wait(c);
1704
1705 err_close_rx_cq:
1706         mlx5e_close_cq(&c->rq.cq);
1707
1708 err_close_tx_cqs:
1709         mlx5e_close_tx_cqs(c);
1710
1711 err_free:
1712         /* destroy mutexes */
1713         mlx5e_chan_mtx_destroy(c);
1714         return (err);
1715 }
1716
1717 static void
1718 mlx5e_close_channel(struct mlx5e_channel *c)
1719 {
1720         mlx5e_close_rq(&c->rq);
1721 }
1722
1723 static void
1724 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1725 {
1726         mlx5e_close_rq_wait(&c->rq);
1727         mlx5e_close_sqs_wait(c);
1728         mlx5e_close_cq(&c->rq.cq);
1729         mlx5e_close_tx_cqs(c);
1730         /* destroy mutexes */
1731         mlx5e_chan_mtx_destroy(c);
1732 }
1733
1734 static int
1735 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1736 {
1737         u32 r, n;
1738
1739         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1740             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1741         if (r > MJUM16BYTES)
1742                 return (-ENOMEM);
1743
1744         if (r > MJUM9BYTES)
1745                 r = MJUM16BYTES;
1746         else if (r > MJUMPAGESIZE)
1747                 r = MJUM9BYTES;
1748         else if (r > MCLBYTES)
1749                 r = MJUMPAGESIZE;
1750         else
1751                 r = MCLBYTES;
1752
1753         /*
1754          * n + 1 must be a power of two, because stride size must be.
1755          * Stride size is 16 * (n + 1), as the first segment is
1756          * control.
1757          */
1758         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1759                 ;
1760
1761         *wqe_sz = r;
1762         *nsegs = n;
1763         return (0);
1764 }
1765
1766 static void
1767 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1768     struct mlx5e_rq_param *param)
1769 {
1770         void *rqc = param->rqc;
1771         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1772         u32 wqe_sz, nsegs;
1773
1774         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1775         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1776         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1777         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1778             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1779         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1780         MLX5_SET(wq, wq, pd, priv->pdn);
1781
1782         param->wq.buf_numa_node = 0;
1783         param->wq.db_numa_node = 0;
1784         param->wq.linear = 1;
1785 }
1786
1787 static void
1788 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1789     struct mlx5e_sq_param *param)
1790 {
1791         void *sqc = param->sqc;
1792         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1793
1794         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1795         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1796         MLX5_SET(wq, wq, pd, priv->pdn);
1797
1798         param->wq.buf_numa_node = 0;
1799         param->wq.db_numa_node = 0;
1800         param->wq.linear = 1;
1801 }
1802
1803 static void
1804 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1805     struct mlx5e_cq_param *param)
1806 {
1807         void *cqc = param->cqc;
1808
1809         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1810 }
1811
1812 static void
1813 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1814     struct mlx5e_cq_param *param)
1815 {
1816         void *cqc = param->cqc;
1817
1818
1819         /*
1820          * TODO The sysctl to control on/off is a bool value for now, which means
1821          * we only support CSUM, once HASH is implemnted we'll need to address that.
1822          */
1823         if (priv->params.cqe_zipping_en) {
1824                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1825                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1826         }
1827
1828         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1829         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1830         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1831
1832         switch (priv->params.rx_cq_moderation_mode) {
1833         case 0:
1834                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1835                 break;
1836         default:
1837                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1838                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1839                 else
1840                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1841                 break;
1842         }
1843
1844         mlx5e_build_common_cq_param(priv, param);
1845 }
1846
1847 static void
1848 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1849     struct mlx5e_cq_param *param)
1850 {
1851         void *cqc = param->cqc;
1852
1853         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1854         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1855         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1856
1857         switch (priv->params.tx_cq_moderation_mode) {
1858         case 0:
1859                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1860                 break;
1861         default:
1862                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1863                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1864                 else
1865                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1866                 break;
1867         }
1868
1869         mlx5e_build_common_cq_param(priv, param);
1870 }
1871
1872 static void
1873 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1874     struct mlx5e_channel_param *cparam)
1875 {
1876         memset(cparam, 0, sizeof(*cparam));
1877
1878         mlx5e_build_rq_param(priv, &cparam->rq);
1879         mlx5e_build_sq_param(priv, &cparam->sq);
1880         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1881         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1882 }
1883
1884 static int
1885 mlx5e_open_channels(struct mlx5e_priv *priv)
1886 {
1887         struct mlx5e_channel_param cparam;
1888         int err;
1889         int i;
1890         int j;
1891
1892         mlx5e_build_channel_param(priv, &cparam);
1893         for (i = 0; i < priv->params.num_channels; i++) {
1894                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1895                 if (err)
1896                         goto err_close_channels;
1897         }
1898
1899         for (j = 0; j < priv->params.num_channels; j++) {
1900                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
1901                 if (err)
1902                         goto err_close_channels;
1903         }
1904
1905         return (0);
1906
1907 err_close_channels:
1908         while (i--) {
1909                 mlx5e_close_channel(&priv->channel[i]);
1910                 mlx5e_close_channel_wait(&priv->channel[i]);
1911         }
1912         return (err);
1913 }
1914
1915 static void
1916 mlx5e_close_channels(struct mlx5e_priv *priv)
1917 {
1918         int i;
1919
1920         for (i = 0; i < priv->params.num_channels; i++)
1921                 mlx5e_close_channel(&priv->channel[i]);
1922         for (i = 0; i < priv->params.num_channels; i++)
1923                 mlx5e_close_channel_wait(&priv->channel[i]);
1924 }
1925
1926 static int
1927 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1928 {
1929
1930         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1931                 uint8_t cq_mode;
1932
1933                 switch (priv->params.tx_cq_moderation_mode) {
1934                 case 0:
1935                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1936                         break;
1937                 default:
1938                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1939                         break;
1940                 }
1941
1942                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1943                     priv->params.tx_cq_moderation_usec,
1944                     priv->params.tx_cq_moderation_pkts,
1945                     cq_mode));
1946         }
1947
1948         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1949             priv->params.tx_cq_moderation_usec,
1950             priv->params.tx_cq_moderation_pkts));
1951 }
1952
1953 static int
1954 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1955 {
1956
1957         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1958                 uint8_t cq_mode;
1959                 int retval;
1960
1961                 switch (priv->params.rx_cq_moderation_mode) {
1962                 case 0:
1963                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1964                         break;
1965                 default:
1966                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1967                         break;
1968                 }
1969
1970                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1971                     priv->params.rx_cq_moderation_usec,
1972                     priv->params.rx_cq_moderation_pkts,
1973                     cq_mode);
1974
1975                 return (retval);
1976         }
1977
1978         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1979             priv->params.rx_cq_moderation_usec,
1980             priv->params.rx_cq_moderation_pkts));
1981 }
1982
1983 static int
1984 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1985 {
1986         int err;
1987         int i;
1988
1989         err = mlx5e_refresh_rq_params(priv, &c->rq);
1990         if (err)
1991                 goto done;
1992
1993         for (i = 0; i != c->num_tc; i++) {
1994                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1995                 if (err)
1996                         goto done;
1997         }
1998 done:
1999         return (err);
2000 }
2001
2002 int
2003 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2004 {
2005         int i;
2006
2007         /* check if channels are closed */
2008         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2009                 return (EINVAL);
2010
2011         for (i = 0; i < priv->params.num_channels; i++) {
2012                 int err;
2013
2014                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2015                 if (err)
2016                         return (err);
2017         }
2018         return (0);
2019 }
2020
2021 static int
2022 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2023 {
2024         struct mlx5_core_dev *mdev = priv->mdev;
2025         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2026         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2027
2028         memset(in, 0, sizeof(in));
2029
2030         MLX5_SET(tisc, tisc, prio, tc);
2031         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2032
2033         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2034 }
2035
2036 static void
2037 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2038 {
2039         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2040 }
2041
2042 static int
2043 mlx5e_open_tises(struct mlx5e_priv *priv)
2044 {
2045         int num_tc = priv->num_tc;
2046         int err;
2047         int tc;
2048
2049         for (tc = 0; tc < num_tc; tc++) {
2050                 err = mlx5e_open_tis(priv, tc);
2051                 if (err)
2052                         goto err_close_tises;
2053         }
2054
2055         return (0);
2056
2057 err_close_tises:
2058         for (tc--; tc >= 0; tc--)
2059                 mlx5e_close_tis(priv, tc);
2060
2061         return (err);
2062 }
2063
2064 static void
2065 mlx5e_close_tises(struct mlx5e_priv *priv)
2066 {
2067         int num_tc = priv->num_tc;
2068         int tc;
2069
2070         for (tc = 0; tc < num_tc; tc++)
2071                 mlx5e_close_tis(priv, tc);
2072 }
2073
2074 static int
2075 mlx5e_open_rqt(struct mlx5e_priv *priv)
2076 {
2077         struct mlx5_core_dev *mdev = priv->mdev;
2078         u32 *in;
2079         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2080         void *rqtc;
2081         int inlen;
2082         int err;
2083         int sz;
2084         int i;
2085
2086         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2087
2088         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2089         in = mlx5_vzalloc(inlen);
2090         if (in == NULL)
2091                 return (-ENOMEM);
2092         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2093
2094         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2095         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2096
2097         for (i = 0; i < sz; i++) {
2098                 int ix = i;
2099 #ifdef RSS
2100                 ix = rss_get_indirection_to_bucket(ix);
2101 #endif
2102                 /* ensure we don't overflow */
2103                 ix %= priv->params.num_channels;
2104
2105                 /* apply receive side scaling stride, if any */
2106                 ix -= ix % (int)priv->params.channels_rsss;
2107
2108                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2109         }
2110
2111         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2112
2113         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2114         if (!err)
2115                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2116
2117         kvfree(in);
2118
2119         return (err);
2120 }
2121
2122 static void
2123 mlx5e_close_rqt(struct mlx5e_priv *priv)
2124 {
2125         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2126         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2127
2128         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2129         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2130
2131         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2132 }
2133
2134 static void
2135 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2136 {
2137         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2138         __be32 *hkey;
2139
2140         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2141
2142 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2143
2144 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2145                           MLX5_HASH_FIELD_SEL_DST_IP)
2146
2147 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2148                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2149                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2150                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2151
2152 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2153                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2154                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2155
2156         if (priv->params.hw_lro_en) {
2157                 MLX5_SET(tirc, tirc, lro_enable_mask,
2158                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2159                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2160                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2161                     (priv->params.lro_wqe_sz -
2162                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2163                 /* TODO: add the option to choose timer value dynamically */
2164                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2165                     MLX5_CAP_ETH(priv->mdev,
2166                     lro_timer_supported_periods[2]));
2167         }
2168
2169         /* setup parameters for hashing TIR type, if any */
2170         switch (tt) {
2171         case MLX5E_TT_ANY:
2172                 MLX5_SET(tirc, tirc, disp_type,
2173                     MLX5_TIRC_DISP_TYPE_DIRECT);
2174                 MLX5_SET(tirc, tirc, inline_rqn,
2175                     priv->channel[0].rq.rqn);
2176                 break;
2177         default:
2178                 MLX5_SET(tirc, tirc, disp_type,
2179                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2180                 MLX5_SET(tirc, tirc, indirect_table,
2181                     priv->rqtn);
2182                 MLX5_SET(tirc, tirc, rx_hash_fn,
2183                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2184                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2185 #ifdef RSS
2186                 /*
2187                  * The FreeBSD RSS implementation does currently not
2188                  * support symmetric Toeplitz hashes:
2189                  */
2190                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2191                 rss_getkey((uint8_t *)hkey);
2192 #else
2193                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2194                 hkey[0] = cpu_to_be32(0xD181C62C);
2195                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2196                 hkey[2] = cpu_to_be32(0x1983A2FC);
2197                 hkey[3] = cpu_to_be32(0x943E1ADB);
2198                 hkey[4] = cpu_to_be32(0xD9389E6B);
2199                 hkey[5] = cpu_to_be32(0xD1039C2C);
2200                 hkey[6] = cpu_to_be32(0xA74499AD);
2201                 hkey[7] = cpu_to_be32(0x593D56D9);
2202                 hkey[8] = cpu_to_be32(0xF3253C06);
2203                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2204 #endif
2205                 break;
2206         }
2207
2208         switch (tt) {
2209         case MLX5E_TT_IPV4_TCP:
2210                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2211                     MLX5_L3_PROT_TYPE_IPV4);
2212                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2213                     MLX5_L4_PROT_TYPE_TCP);
2214 #ifdef RSS
2215                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2216                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2217                             MLX5_HASH_IP);
2218                 } else
2219 #endif
2220                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2221                     MLX5_HASH_ALL);
2222                 break;
2223
2224         case MLX5E_TT_IPV6_TCP:
2225                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2226                     MLX5_L3_PROT_TYPE_IPV6);
2227                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2228                     MLX5_L4_PROT_TYPE_TCP);
2229 #ifdef RSS
2230                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2231                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2232                             MLX5_HASH_IP);
2233                 } else
2234 #endif
2235                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2236                     MLX5_HASH_ALL);
2237                 break;
2238
2239         case MLX5E_TT_IPV4_UDP:
2240                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2241                     MLX5_L3_PROT_TYPE_IPV4);
2242                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2243                     MLX5_L4_PROT_TYPE_UDP);
2244 #ifdef RSS
2245                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2246                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2247                             MLX5_HASH_IP);
2248                 } else
2249 #endif
2250                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2251                     MLX5_HASH_ALL);
2252                 break;
2253
2254         case MLX5E_TT_IPV6_UDP:
2255                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2256                     MLX5_L3_PROT_TYPE_IPV6);
2257                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2258                     MLX5_L4_PROT_TYPE_UDP);
2259 #ifdef RSS
2260                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2261                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2262                             MLX5_HASH_IP);
2263                 } else
2264 #endif
2265                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2266                     MLX5_HASH_ALL);
2267                 break;
2268
2269         case MLX5E_TT_IPV4_IPSEC_AH:
2270                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2271                     MLX5_L3_PROT_TYPE_IPV4);
2272                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2273                     MLX5_HASH_IP_IPSEC_SPI);
2274                 break;
2275
2276         case MLX5E_TT_IPV6_IPSEC_AH:
2277                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2278                     MLX5_L3_PROT_TYPE_IPV6);
2279                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2280                     MLX5_HASH_IP_IPSEC_SPI);
2281                 break;
2282
2283         case MLX5E_TT_IPV4_IPSEC_ESP:
2284                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2285                     MLX5_L3_PROT_TYPE_IPV4);
2286                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2287                     MLX5_HASH_IP_IPSEC_SPI);
2288                 break;
2289
2290         case MLX5E_TT_IPV6_IPSEC_ESP:
2291                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2292                     MLX5_L3_PROT_TYPE_IPV6);
2293                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2294                     MLX5_HASH_IP_IPSEC_SPI);
2295                 break;
2296
2297         case MLX5E_TT_IPV4:
2298                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2299                     MLX5_L3_PROT_TYPE_IPV4);
2300                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301                     MLX5_HASH_IP);
2302                 break;
2303
2304         case MLX5E_TT_IPV6:
2305                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2306                     MLX5_L3_PROT_TYPE_IPV6);
2307                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2308                     MLX5_HASH_IP);
2309                 break;
2310
2311         default:
2312                 break;
2313         }
2314 }
2315
2316 static int
2317 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2318 {
2319         struct mlx5_core_dev *mdev = priv->mdev;
2320         u32 *in;
2321         void *tirc;
2322         int inlen;
2323         int err;
2324
2325         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2326         in = mlx5_vzalloc(inlen);
2327         if (in == NULL)
2328                 return (-ENOMEM);
2329         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2330
2331         mlx5e_build_tir_ctx(priv, tirc, tt);
2332
2333         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2334
2335         kvfree(in);
2336
2337         return (err);
2338 }
2339
2340 static void
2341 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2342 {
2343         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2344 }
2345
2346 static int
2347 mlx5e_open_tirs(struct mlx5e_priv *priv)
2348 {
2349         int err;
2350         int i;
2351
2352         for (i = 0; i < MLX5E_NUM_TT; i++) {
2353                 err = mlx5e_open_tir(priv, i);
2354                 if (err)
2355                         goto err_close_tirs;
2356         }
2357
2358         return (0);
2359
2360 err_close_tirs:
2361         for (i--; i >= 0; i--)
2362                 mlx5e_close_tir(priv, i);
2363
2364         return (err);
2365 }
2366
2367 static void
2368 mlx5e_close_tirs(struct mlx5e_priv *priv)
2369 {
2370         int i;
2371
2372         for (i = 0; i < MLX5E_NUM_TT; i++)
2373                 mlx5e_close_tir(priv, i);
2374 }
2375
2376 /*
2377  * SW MTU does not include headers,
2378  * HW MTU includes all headers and checksums.
2379  */
2380 static int
2381 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2382 {
2383         struct mlx5e_priv *priv = ifp->if_softc;
2384         struct mlx5_core_dev *mdev = priv->mdev;
2385         int hw_mtu;
2386         int err;
2387
2388         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2389
2390         err = mlx5_set_port_mtu(mdev, hw_mtu);
2391         if (err) {
2392                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2393                     __func__, sw_mtu, err);
2394                 return (err);
2395         }
2396
2397         /* Update vport context MTU */
2398         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2399         if (err) {
2400                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2401                     __func__, err);
2402         }
2403
2404         ifp->if_mtu = sw_mtu;
2405
2406         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2407         if (err || !hw_mtu) {
2408                 /* fallback to port oper mtu */
2409                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2410         }
2411         if (err) {
2412                 if_printf(ifp, "Query port MTU, after setting new "
2413                     "MTU value, failed\n");
2414                 return (err);
2415         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2416                 err = -E2BIG,
2417                 if_printf(ifp, "Port MTU %d is smaller than "
2418                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2419         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2420                 err = -EINVAL;
2421                 if_printf(ifp, "Port MTU %d is bigger than "
2422                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2423         }
2424         priv->params_ethtool.hw_mtu = hw_mtu;
2425
2426         return (err);
2427 }
2428
2429 int
2430 mlx5e_open_locked(struct ifnet *ifp)
2431 {
2432         struct mlx5e_priv *priv = ifp->if_softc;
2433         int err;
2434         u16 set_id;
2435
2436         /* check if already opened */
2437         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2438                 return (0);
2439
2440 #ifdef RSS
2441         if (rss_getnumbuckets() > priv->params.num_channels) {
2442                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2443                     "channels(%u) available\n", rss_getnumbuckets(),
2444                     priv->params.num_channels);
2445         }
2446 #endif
2447         err = mlx5e_open_tises(priv);
2448         if (err) {
2449                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2450                     __func__, err);
2451                 return (err);
2452         }
2453         err = mlx5_vport_alloc_q_counter(priv->mdev,
2454             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2455         if (err) {
2456                 if_printf(priv->ifp,
2457                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2458                     __func__, err);
2459                 goto err_close_tises;
2460         }
2461         /* store counter set ID */
2462         priv->counter_set_id = set_id;
2463
2464         err = mlx5e_open_channels(priv);
2465         if (err) {
2466                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2467                     __func__, err);
2468                 goto err_dalloc_q_counter;
2469         }
2470         err = mlx5e_open_rqt(priv);
2471         if (err) {
2472                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2473                     __func__, err);
2474                 goto err_close_channels;
2475         }
2476         err = mlx5e_open_tirs(priv);
2477         if (err) {
2478                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2479                     __func__, err);
2480                 goto err_close_rqls;
2481         }
2482         err = mlx5e_open_flow_table(priv);
2483         if (err) {
2484                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2485                     __func__, err);
2486                 goto err_close_tirs;
2487         }
2488         err = mlx5e_add_all_vlan_rules(priv);
2489         if (err) {
2490                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2491                     __func__, err);
2492                 goto err_close_flow_table;
2493         }
2494         set_bit(MLX5E_STATE_OPENED, &priv->state);
2495
2496         mlx5e_update_carrier(priv);
2497         mlx5e_set_rx_mode_core(priv);
2498
2499         return (0);
2500
2501 err_close_flow_table:
2502         mlx5e_close_flow_table(priv);
2503
2504 err_close_tirs:
2505         mlx5e_close_tirs(priv);
2506
2507 err_close_rqls:
2508         mlx5e_close_rqt(priv);
2509
2510 err_close_channels:
2511         mlx5e_close_channels(priv);
2512
2513 err_dalloc_q_counter:
2514         mlx5_vport_dealloc_q_counter(priv->mdev,
2515             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2516
2517 err_close_tises:
2518         mlx5e_close_tises(priv);
2519
2520         return (err);
2521 }
2522
2523 static void
2524 mlx5e_open(void *arg)
2525 {
2526         struct mlx5e_priv *priv = arg;
2527
2528         PRIV_LOCK(priv);
2529         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2530                 if_printf(priv->ifp,
2531                     "%s: Setting port status to up failed\n",
2532                     __func__);
2533
2534         mlx5e_open_locked(priv->ifp);
2535         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2536         PRIV_UNLOCK(priv);
2537 }
2538
2539 int
2540 mlx5e_close_locked(struct ifnet *ifp)
2541 {
2542         struct mlx5e_priv *priv = ifp->if_softc;
2543
2544         /* check if already closed */
2545         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2546                 return (0);
2547
2548         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2549
2550         mlx5e_set_rx_mode_core(priv);
2551         mlx5e_del_all_vlan_rules(priv);
2552         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2553         mlx5e_close_flow_table(priv);
2554         mlx5e_close_tirs(priv);
2555         mlx5e_close_rqt(priv);
2556         mlx5e_close_channels(priv);
2557         mlx5_vport_dealloc_q_counter(priv->mdev,
2558             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2559         mlx5e_close_tises(priv);
2560
2561         return (0);
2562 }
2563
2564 #if (__FreeBSD_version >= 1100000)
2565 static uint64_t
2566 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2567 {
2568         struct mlx5e_priv *priv = ifp->if_softc;
2569         u64 retval;
2570
2571         /* PRIV_LOCK(priv); XXX not allowed */
2572         switch (cnt) {
2573         case IFCOUNTER_IPACKETS:
2574                 retval = priv->stats.vport.rx_packets;
2575                 break;
2576         case IFCOUNTER_IERRORS:
2577                 retval = priv->stats.vport.rx_error_packets +
2578                     priv->stats.pport.alignment_err +
2579                     priv->stats.pport.check_seq_err +
2580                     priv->stats.pport.crc_align_errors +
2581                     priv->stats.pport.in_range_len_errors +
2582                     priv->stats.pport.jabbers +
2583                     priv->stats.pport.out_of_range_len +
2584                     priv->stats.pport.oversize_pkts +
2585                     priv->stats.pport.symbol_err +
2586                     priv->stats.pport.too_long_errors +
2587                     priv->stats.pport.undersize_pkts +
2588                     priv->stats.pport.unsupported_op_rx;
2589                 break;
2590         case IFCOUNTER_IQDROPS:
2591                 retval = priv->stats.vport.rx_out_of_buffer +
2592                     priv->stats.pport.drop_events;
2593                 break;
2594         case IFCOUNTER_OPACKETS:
2595                 retval = priv->stats.vport.tx_packets;
2596                 break;
2597         case IFCOUNTER_OERRORS:
2598                 retval = priv->stats.vport.tx_error_packets;
2599                 break;
2600         case IFCOUNTER_IBYTES:
2601                 retval = priv->stats.vport.rx_bytes;
2602                 break;
2603         case IFCOUNTER_OBYTES:
2604                 retval = priv->stats.vport.tx_bytes;
2605                 break;
2606         case IFCOUNTER_IMCASTS:
2607                 retval = priv->stats.vport.rx_multicast_packets;
2608                 break;
2609         case IFCOUNTER_OMCASTS:
2610                 retval = priv->stats.vport.tx_multicast_packets;
2611                 break;
2612         case IFCOUNTER_OQDROPS:
2613                 retval = priv->stats.vport.tx_queue_dropped;
2614                 break;
2615         case IFCOUNTER_COLLISIONS:
2616                 retval = priv->stats.pport.collisions;
2617                 break;
2618         default:
2619                 retval = if_get_counter_default(ifp, cnt);
2620                 break;
2621         }
2622         /* PRIV_UNLOCK(priv); XXX not allowed */
2623         return (retval);
2624 }
2625 #endif
2626
2627 static void
2628 mlx5e_set_rx_mode(struct ifnet *ifp)
2629 {
2630         struct mlx5e_priv *priv = ifp->if_softc;
2631
2632         queue_work(priv->wq, &priv->set_rx_mode_work);
2633 }
2634
2635 static int
2636 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2637 {
2638         struct mlx5e_priv *priv;
2639         struct ifreq *ifr;
2640         struct ifi2creq i2c;
2641         int error = 0;
2642         int mask = 0;
2643         int size_read = 0;
2644         int module_status;
2645         int module_num;
2646         int max_mtu;
2647         uint8_t read_addr;
2648
2649         priv = ifp->if_softc;
2650
2651         /* check if detaching */
2652         if (priv == NULL || priv->gone != 0)
2653                 return (ENXIO);
2654
2655         switch (command) {
2656         case SIOCSIFMTU:
2657                 ifr = (struct ifreq *)data;
2658
2659                 PRIV_LOCK(priv);
2660                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2661
2662                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2663                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2664                         int was_opened;
2665
2666                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2667                         if (was_opened)
2668                                 mlx5e_close_locked(ifp);
2669
2670                         /* set new MTU */
2671                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2672
2673                         if (was_opened)
2674                                 mlx5e_open_locked(ifp);
2675                 } else {
2676                         error = EINVAL;
2677                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2678                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2679                 }
2680                 PRIV_UNLOCK(priv);
2681                 break;
2682         case SIOCSIFFLAGS:
2683                 if ((ifp->if_flags & IFF_UP) &&
2684                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2685                         mlx5e_set_rx_mode(ifp);
2686                         break;
2687                 }
2688                 PRIV_LOCK(priv);
2689                 if (ifp->if_flags & IFF_UP) {
2690                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2691                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2692                                         mlx5e_open_locked(ifp);
2693                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2694                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2695                         }
2696                 } else {
2697                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2698                                 mlx5_set_port_status(priv->mdev,
2699                                     MLX5_PORT_DOWN);
2700                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2701                                         mlx5e_close_locked(ifp);
2702                                 mlx5e_update_carrier(priv);
2703                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2704                         }
2705                 }
2706                 PRIV_UNLOCK(priv);
2707                 break;
2708         case SIOCADDMULTI:
2709         case SIOCDELMULTI:
2710                 mlx5e_set_rx_mode(ifp);
2711                 break;
2712         case SIOCSIFMEDIA:
2713         case SIOCGIFMEDIA:
2714         case SIOCGIFXMEDIA:
2715                 ifr = (struct ifreq *)data;
2716                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2717                 break;
2718         case SIOCSIFCAP:
2719                 ifr = (struct ifreq *)data;
2720                 PRIV_LOCK(priv);
2721                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2722
2723                 if (mask & IFCAP_TXCSUM) {
2724                         ifp->if_capenable ^= IFCAP_TXCSUM;
2725                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2726
2727                         if (IFCAP_TSO4 & ifp->if_capenable &&
2728                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2729                                 ifp->if_capenable &= ~IFCAP_TSO4;
2730                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2731                                 if_printf(ifp,
2732                                     "tso4 disabled due to -txcsum.\n");
2733                         }
2734                 }
2735                 if (mask & IFCAP_TXCSUM_IPV6) {
2736                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2737                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2738
2739                         if (IFCAP_TSO6 & ifp->if_capenable &&
2740                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2741                                 ifp->if_capenable &= ~IFCAP_TSO6;
2742                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2743                                 if_printf(ifp,
2744                                     "tso6 disabled due to -txcsum6.\n");
2745                         }
2746                 }
2747                 if (mask & IFCAP_RXCSUM)
2748                         ifp->if_capenable ^= IFCAP_RXCSUM;
2749                 if (mask & IFCAP_RXCSUM_IPV6)
2750                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2751                 if (mask & IFCAP_TSO4) {
2752                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2753                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2754                                 if_printf(ifp, "enable txcsum first.\n");
2755                                 error = EAGAIN;
2756                                 goto out;
2757                         }
2758                         ifp->if_capenable ^= IFCAP_TSO4;
2759                         ifp->if_hwassist ^= CSUM_IP_TSO;
2760                 }
2761                 if (mask & IFCAP_TSO6) {
2762                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2763                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2764                                 if_printf(ifp, "enable txcsum6 first.\n");
2765                                 error = EAGAIN;
2766                                 goto out;
2767                         }
2768                         ifp->if_capenable ^= IFCAP_TSO6;
2769                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2770                 }
2771                 if (mask & IFCAP_VLAN_HWFILTER) {
2772                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2773                                 mlx5e_disable_vlan_filter(priv);
2774                         else
2775                                 mlx5e_enable_vlan_filter(priv);
2776
2777                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2778                 }
2779                 if (mask & IFCAP_VLAN_HWTAGGING)
2780                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2781                 if (mask & IFCAP_WOL_MAGIC)
2782                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2783
2784                 VLAN_CAPABILITIES(ifp);
2785                 /* turn off LRO means also turn of HW LRO - if it's on */
2786                 if (mask & IFCAP_LRO) {
2787                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2788                         bool need_restart = false;
2789
2790                         ifp->if_capenable ^= IFCAP_LRO;
2791
2792                         /* figure out if updating HW LRO is needed */
2793                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2794                                 if (priv->params.hw_lro_en) {
2795                                         priv->params.hw_lro_en = false;
2796                                         need_restart = true;
2797                                 }
2798                         } else {
2799                                 if (priv->params.hw_lro_en == false &&
2800                                     priv->params_ethtool.hw_lro != 0) {
2801                                         priv->params.hw_lro_en = true;
2802                                         need_restart = true;
2803                                 }
2804                         }
2805                         if (was_opened && need_restart) {
2806                                 mlx5e_close_locked(ifp);
2807                                 mlx5e_open_locked(ifp);
2808                         }
2809                 }
2810 out:
2811                 PRIV_UNLOCK(priv);
2812                 break;
2813
2814         case SIOCGI2C:
2815                 ifr = (struct ifreq *)data;
2816
2817                 /*
2818                  * Copy from the user-space address ifr_data to the
2819                  * kernel-space address i2c
2820                  */
2821                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2822                 if (error)
2823                         break;
2824
2825                 if (i2c.len > sizeof(i2c.data)) {
2826                         error = EINVAL;
2827                         break;
2828                 }
2829
2830                 PRIV_LOCK(priv);
2831                 /* Get module_num which is required for the query_eeprom */
2832                 error = mlx5_query_module_num(priv->mdev, &module_num);
2833                 if (error) {
2834                         if_printf(ifp, "Query module num failed, eeprom "
2835                             "reading is not supported\n");
2836                         error = EINVAL;
2837                         goto err_i2c;
2838                 }
2839                 /* Check if module is present before doing an access */
2840                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2841                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2842                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2843                         error = EINVAL;
2844                         goto err_i2c;
2845                 }
2846                 /*
2847                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2848                  * The internal conversion is as follows:
2849                  */
2850                 if (i2c.dev_addr == 0xA0)
2851                         read_addr = MLX5E_I2C_ADDR_LOW;
2852                 else if (i2c.dev_addr == 0xA2)
2853                         read_addr = MLX5E_I2C_ADDR_HIGH;
2854                 else {
2855                         if_printf(ifp, "Query eeprom failed, "
2856                             "Invalid Address: %X\n", i2c.dev_addr);
2857                         error = EINVAL;
2858                         goto err_i2c;
2859                 }
2860                 error = mlx5_query_eeprom(priv->mdev,
2861                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2862                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2863                     (uint32_t *)i2c.data, &size_read);
2864                 if (error) {
2865                         if_printf(ifp, "Query eeprom failed, eeprom "
2866                             "reading is not supported\n");
2867                         error = EINVAL;
2868                         goto err_i2c;
2869                 }
2870
2871                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2872                         error = mlx5_query_eeprom(priv->mdev,
2873                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2874                             (uint32_t)(i2c.offset + size_read),
2875                             (uint32_t)(i2c.len - size_read), module_num,
2876                             (uint32_t *)(i2c.data + size_read), &size_read);
2877                 }
2878                 if (error) {
2879                         if_printf(ifp, "Query eeprom failed, eeprom "
2880                             "reading is not supported\n");
2881                         error = EINVAL;
2882                         goto err_i2c;
2883                 }
2884
2885                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2886 err_i2c:
2887                 PRIV_UNLOCK(priv);
2888                 break;
2889
2890         default:
2891                 error = ether_ioctl(ifp, command, data);
2892                 break;
2893         }
2894         return (error);
2895 }
2896
2897 static int
2898 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2899 {
2900         /*
2901          * TODO: uncoment once FW really sets all these bits if
2902          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2903          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2904          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2905          * -ENOTSUPP;
2906          */
2907
2908         /* TODO: add more must-to-have features */
2909
2910         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2911                 return (-ENODEV);
2912
2913         return (0);
2914 }
2915
2916 static u16
2917 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2918 {
2919         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
2920
2921         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
2922
2923         /* verify against driver hardware limit */
2924         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
2925                 bf_buf_size = MLX5E_MAX_TX_INLINE;
2926
2927         return (bf_buf_size);
2928 }
2929
2930 static int
2931 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2932     struct mlx5e_priv *priv,
2933     int num_comp_vectors)
2934 {
2935         int err;
2936
2937         /*
2938          * TODO: Consider link speed for setting "log_sq_size",
2939          * "log_rq_size" and "cq_moderation_xxx":
2940          */
2941         priv->params.log_sq_size =
2942             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2943         priv->params.log_rq_size =
2944             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2945         priv->params.rx_cq_moderation_usec =
2946             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2947             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2948             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2949         priv->params.rx_cq_moderation_mode =
2950             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2951         priv->params.rx_cq_moderation_pkts =
2952             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2953         priv->params.tx_cq_moderation_usec =
2954             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2955         priv->params.tx_cq_moderation_pkts =
2956             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2957         priv->params.min_rx_wqes =
2958             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2959         priv->params.rx_hash_log_tbl_sz =
2960             (order_base_2(num_comp_vectors) >
2961             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2962             order_base_2(num_comp_vectors) :
2963             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2964         priv->params.num_tc = 1;
2965         priv->params.default_vlan_prio = 0;
2966         priv->counter_set_id = -1;
2967         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2968
2969         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
2970         if (err)
2971                 return (err);
2972
2973         /*
2974          * hw lro is currently defaulted to off. when it won't anymore we
2975          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2976          */
2977         priv->params.hw_lro_en = false;
2978         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2979
2980         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2981
2982         priv->mdev = mdev;
2983         priv->params.num_channels = num_comp_vectors;
2984         priv->params.channels_rsss = 1;
2985         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2986         priv->queue_mapping_channel_mask =
2987             roundup_pow_of_two(num_comp_vectors) - 1;
2988         priv->num_tc = priv->params.num_tc;
2989         priv->default_vlan_prio = priv->params.default_vlan_prio;
2990
2991         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2992         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2993         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2994
2995         return (0);
2996 }
2997
2998 static int
2999 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3000                   struct mlx5_core_mr *mkey)
3001 {
3002         struct ifnet *ifp = priv->ifp;
3003         struct mlx5_core_dev *mdev = priv->mdev;
3004         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3005         void *mkc;
3006         u32 *in;
3007         int err;
3008
3009         in = mlx5_vzalloc(inlen);
3010         if (in == NULL) {
3011                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3012                 return (-ENOMEM);
3013         }
3014
3015         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3016         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3017         MLX5_SET(mkc, mkc, lw, 1);
3018         MLX5_SET(mkc, mkc, lr, 1);
3019
3020         MLX5_SET(mkc, mkc, pd, pdn);
3021         MLX5_SET(mkc, mkc, length64, 1);
3022         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3023
3024         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3025         if (err)
3026                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3027                     __func__, err);
3028
3029         kvfree(in);
3030         return (err);
3031 }
3032
3033 static const char *mlx5e_vport_stats_desc[] = {
3034         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3035 };
3036
3037 static const char *mlx5e_pport_stats_desc[] = {
3038         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3039 };
3040
3041 static void
3042 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3043 {
3044         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3045         sx_init(&priv->state_lock, "mlx5state");
3046         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3047         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3048 }
3049
3050 static void
3051 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3052 {
3053         mtx_destroy(&priv->async_events_mtx);
3054         sx_destroy(&priv->state_lock);
3055 }
3056
3057 static int
3058 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3059 {
3060         /*
3061          * %d.%d%.d the string format.
3062          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3063          * We need at most 5 chars to store that.
3064          * It also has: two "." and NULL at the end, which means we need 18
3065          * (5*3 + 3) chars at most.
3066          */
3067         char fw[18];
3068         struct mlx5e_priv *priv = arg1;
3069         int error;
3070
3071         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3072             fw_rev_sub(priv->mdev));
3073         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3074         return (error);
3075 }
3076
3077 static void
3078 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3079 {
3080         int i;
3081
3082         for (i = 0; i < ch->num_tc; i++)
3083                 mlx5e_drain_sq(&ch->sq[i]);
3084 }
3085
3086 static void
3087 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3088 {
3089
3090         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3091         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3092         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3093         sq->doorbell.d64 = 0;
3094 }
3095
3096 void
3097 mlx5e_resume_sq(struct mlx5e_sq *sq)
3098 {
3099         int err;
3100
3101         /* check if already enabled */
3102         if (READ_ONCE(sq->running) != 0)
3103                 return;
3104
3105         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3106             MLX5_SQC_STATE_RST);
3107         if (err != 0) {
3108                 if_printf(sq->ifp,
3109                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3110         }
3111
3112         sq->cc = 0;
3113         sq->pc = 0;
3114
3115         /* reset doorbell prior to moving from RST to RDY */
3116         mlx5e_reset_sq_doorbell_record(sq);
3117
3118         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3119             MLX5_SQC_STATE_RDY);
3120         if (err != 0) {
3121                 if_printf(sq->ifp,
3122                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3123         }
3124
3125         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3126         WRITE_ONCE(sq->running, 1);
3127 }
3128
3129 static void
3130 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3131 {
3132         int i;
3133
3134         for (i = 0; i < ch->num_tc; i++)
3135                 mlx5e_resume_sq(&ch->sq[i]);
3136 }
3137
3138 static void
3139 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3140 {
3141         struct mlx5e_rq *rq = &ch->rq;
3142         int err;
3143
3144         mtx_lock(&rq->mtx);
3145         rq->enabled = 0;
3146         callout_stop(&rq->watchdog);
3147         mtx_unlock(&rq->mtx);
3148
3149         callout_drain(&rq->watchdog);
3150
3151         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3152         if (err != 0) {
3153                 if_printf(rq->ifp,
3154                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3155         }
3156
3157         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3158                 msleep(1);
3159                 rq->cq.mcq.comp(&rq->cq.mcq);
3160         }
3161
3162         /*
3163          * Transitioning into RST state will allow the FW to track less ERR state queues,
3164          * thus reducing the recv queue flushing time
3165          */
3166         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3167         if (err != 0) {
3168                 if_printf(rq->ifp,
3169                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3170         }
3171 }
3172
3173 static void
3174 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3175 {
3176         struct mlx5e_rq *rq = &ch->rq;
3177         int err;
3178
3179         rq->wq.wqe_ctr = 0;
3180         mlx5_wq_ll_update_db_record(&rq->wq);
3181         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3182         if (err != 0) {
3183                 if_printf(rq->ifp,
3184                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3185         }
3186
3187         rq->enabled = 1;
3188
3189         rq->cq.mcq.comp(&rq->cq.mcq);
3190 }
3191
3192 void
3193 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3194 {
3195         int i;
3196
3197         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3198                 return;
3199
3200         for (i = 0; i < priv->params.num_channels; i++) {
3201                 if (value)
3202                         mlx5e_disable_tx_dma(&priv->channel[i]);
3203                 else
3204                         mlx5e_enable_tx_dma(&priv->channel[i]);
3205         }
3206 }
3207
3208 void
3209 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3210 {
3211         int i;
3212
3213         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3214                 return;
3215
3216         for (i = 0; i < priv->params.num_channels; i++) {
3217                 if (value)
3218                         mlx5e_disable_rx_dma(&priv->channel[i]);
3219                 else
3220                         mlx5e_enable_rx_dma(&priv->channel[i]);
3221         }
3222 }
3223
3224 static void
3225 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3226 {
3227         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3228             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3229             sysctl_firmware, "A", "HCA firmware version");
3230
3231         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3232             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3233             "Board ID");
3234 }
3235
3236 static int
3237 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3238 {
3239         struct mlx5e_priv *priv = arg1;
3240         uint32_t tx_pfc;
3241         uint32_t value;
3242         int error;
3243
3244         PRIV_LOCK(priv);
3245
3246         tx_pfc = priv->params.tx_priority_flow_control;
3247
3248         /* get current value */
3249         value = (tx_pfc >> arg2) & 1;
3250
3251         error = sysctl_handle_32(oidp, &value, 0, req);
3252
3253         /* range check value */
3254         if (value != 0)
3255                 priv->params.tx_priority_flow_control |= (1 << arg2);
3256         else
3257                 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3258
3259         /* check if update is required */
3260         if (error == 0 && priv->gone == 0 &&
3261             tx_pfc != priv->params.tx_priority_flow_control) {
3262                 error = -mlx5e_set_port_pfc(priv);
3263                 /* restore previous value */
3264                 if (error != 0)
3265                         priv->params.tx_priority_flow_control= tx_pfc;
3266         }
3267         PRIV_UNLOCK(priv);
3268
3269         return (error);
3270 }
3271
3272 static int
3273 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3274 {
3275         struct mlx5e_priv *priv = arg1;
3276         uint32_t rx_pfc;
3277         uint32_t value;
3278         int error;
3279
3280         PRIV_LOCK(priv);
3281
3282         rx_pfc = priv->params.rx_priority_flow_control;
3283
3284         /* get current value */
3285         value = (rx_pfc >> arg2) & 1;
3286
3287         error = sysctl_handle_32(oidp, &value, 0, req);
3288
3289         /* range check value */
3290         if (value != 0)
3291                 priv->params.rx_priority_flow_control |= (1 << arg2);
3292         else
3293                 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3294
3295         /* check if update is required */
3296         if (error == 0 && priv->gone == 0 &&
3297             rx_pfc != priv->params.rx_priority_flow_control) {
3298                 error = -mlx5e_set_port_pfc(priv);
3299                 /* restore previous value */
3300                 if (error != 0)
3301                         priv->params.rx_priority_flow_control= rx_pfc;
3302         }
3303         PRIV_UNLOCK(priv);
3304
3305         return (error);
3306 }
3307
3308 static void
3309 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3310 {
3311         unsigned int x;
3312         char path[96];
3313         int error;
3314
3315         /* enable pauseframes by default */
3316         priv->params.tx_pauseframe_control = 1;
3317         priv->params.rx_pauseframe_control = 1;
3318
3319         /* disable ports flow control, PFC, by default */
3320         priv->params.tx_priority_flow_control = 0;
3321         priv->params.rx_priority_flow_control = 0;
3322
3323 #if (__FreeBSD_version < 1100000)
3324         /* compute path for sysctl */
3325         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3326             device_get_unit(priv->mdev->pdev->dev.bsddev));
3327
3328         /* try to fetch tunable, if any */
3329         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3330
3331         /* compute path for sysctl */
3332         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3333             device_get_unit(priv->mdev->pdev->dev.bsddev));
3334
3335         /* try to fetch tunable, if any */
3336         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3337
3338         for (x = 0; x != 8; x++) {
3339
3340                 /* compute path for sysctl */
3341                 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3342                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3343
3344                 /* try to fetch tunable, if any */
3345                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3346                         priv->params.tx_priority_flow_control |= 1 << x;
3347
3348                 /* compute path for sysctl */
3349                 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3350                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3351
3352                 /* try to fetch tunable, if any */
3353                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3354                         priv->params.rx_priority_flow_control |= 1 << x;
3355         }
3356 #endif
3357
3358         /* register pauseframe SYSCTLs */
3359         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3360             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3361             &priv->params.tx_pauseframe_control, 0,
3362             "Set to enable TX pause frames. Clear to disable.");
3363
3364         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3365             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3366             &priv->params.rx_pauseframe_control, 0,
3367             "Set to enable RX pause frames. Clear to disable.");
3368
3369         /* register priority_flow control, PFC, SYSCTLs */
3370         for (x = 0; x != 8; x++) {
3371                 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3372
3373                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3374                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3375                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3376                     "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3377
3378                 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3379
3380                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3381                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3382                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3383                     "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3384         }
3385
3386         PRIV_LOCK(priv);
3387
3388         /* range check */
3389         priv->params.tx_pauseframe_control =
3390             priv->params.tx_pauseframe_control ? 1 : 0;
3391         priv->params.rx_pauseframe_control =
3392             priv->params.rx_pauseframe_control ? 1 : 0;
3393
3394         /* update firmware */
3395         error = mlx5e_set_port_pause_and_pfc(priv);
3396         if (error == -EINVAL) {
3397                 if_printf(priv->ifp,
3398                     "Global pauseframes must be disabled before enabling PFC.\n");
3399                 priv->params.rx_priority_flow_control = 0;
3400                 priv->params.tx_priority_flow_control = 0;
3401
3402                 /* update firmware */
3403                 (void) mlx5e_set_port_pause_and_pfc(priv);
3404         }
3405         PRIV_UNLOCK(priv);
3406 }
3407
3408 static void *
3409 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3410 {
3411         struct ifnet *ifp;
3412         struct mlx5e_priv *priv;
3413         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3414         struct sysctl_oid_list *child;
3415         int ncv = mdev->priv.eq_table.num_comp_vectors;
3416         char unit[16];
3417         int err;
3418         int i;
3419         u32 eth_proto_cap;
3420
3421         if (mlx5e_check_required_hca_cap(mdev)) {
3422                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3423                 return (NULL);
3424         }
3425         /*
3426          * Try to allocate the priv and make room for worst-case
3427          * number of channel structures:
3428          */
3429         priv = malloc(sizeof(*priv) +
3430             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3431             M_MLX5EN, M_WAITOK | M_ZERO);
3432         mlx5e_priv_mtx_init(priv);
3433
3434         ifp = priv->ifp = if_alloc(IFT_ETHER);
3435         if (ifp == NULL) {
3436                 mlx5_core_err(mdev, "if_alloc() failed\n");
3437                 goto err_free_priv;
3438         }
3439         ifp->if_softc = priv;
3440         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3441         ifp->if_mtu = ETHERMTU;
3442         ifp->if_init = mlx5e_open;
3443         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3444         ifp->if_ioctl = mlx5e_ioctl;
3445         ifp->if_transmit = mlx5e_xmit;
3446         ifp->if_qflush = if_qflush;
3447 #if (__FreeBSD_version >= 1100000)
3448         ifp->if_get_counter = mlx5e_get_counter;
3449 #endif
3450         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3451         /*
3452          * Set driver features
3453          */
3454         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3455         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3456         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3457         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3458         ifp->if_capabilities |= IFCAP_LRO;
3459         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3460         ifp->if_capabilities |= IFCAP_HWSTATS;
3461
3462         /* set TSO limits so that we don't have to drop TX packets */
3463         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3464         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3465         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3466
3467         ifp->if_capenable = ifp->if_capabilities;
3468         ifp->if_hwassist = 0;
3469         if (ifp->if_capenable & IFCAP_TSO)
3470                 ifp->if_hwassist |= CSUM_TSO;
3471         if (ifp->if_capenable & IFCAP_TXCSUM)
3472                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3473         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3474                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3475
3476         /* ifnet sysctl tree */
3477         sysctl_ctx_init(&priv->sysctl_ctx);
3478         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3479             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3480         if (priv->sysctl_ifnet == NULL) {
3481                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3482                 goto err_free_sysctl;
3483         }
3484         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3485         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3486             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3487         if (priv->sysctl_ifnet == NULL) {
3488                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3489                 goto err_free_sysctl;
3490         }
3491
3492         /* HW sysctl tree */
3493         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3494         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3495             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3496         if (priv->sysctl_hw == NULL) {
3497                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3498                 goto err_free_sysctl;
3499         }
3500
3501         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3502         if (err) {
3503                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3504                 goto err_free_sysctl;
3505         }
3506
3507         snprintf(unit, sizeof(unit), "mce%u_wq",
3508             device_get_unit(mdev->pdev->dev.bsddev));
3509         priv->wq = alloc_workqueue(unit, 0, 1);
3510         if (priv->wq == NULL) {
3511                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3512                 goto err_free_sysctl;
3513         }
3514
3515         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3516         if (err) {
3517                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3518                     __func__, err);
3519                 goto err_free_wq;
3520         }
3521         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3522         if (err) {
3523                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3524                     __func__, err);
3525                 goto err_unmap_free_uar;
3526         }
3527         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3528         if (err) {
3529                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3530                     __func__, err);
3531                 goto err_dealloc_pd;
3532         }
3533         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3534         if (err) {
3535                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3536                     __func__, err);
3537                 goto err_dealloc_transport_domain;
3538         }
3539         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3540
3541         /* check if we should generate a random MAC address */
3542         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3543             is_zero_ether_addr(dev_addr)) {
3544                 random_ether_addr(dev_addr);
3545                 if_printf(ifp, "Assigned random MAC address\n");
3546         }
3547
3548         /* set default MTU */
3549         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3550
3551         /* Set default media status */
3552         priv->media_status_last = IFM_AVALID;
3553         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3554             IFM_ETH_RXPAUSE | IFM_FDX;
3555
3556         /* setup default pauseframes configuration */
3557         mlx5e_setup_pauseframes(priv);
3558
3559         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3560         if (err) {
3561                 eth_proto_cap = 0;
3562                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3563                     __func__, err);
3564         }
3565
3566         /* Setup supported medias */
3567         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3568             mlx5e_media_change, mlx5e_media_status);
3569
3570         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3571                 if (mlx5e_mode_table[i].baudrate == 0)
3572                         continue;
3573                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3574                         ifmedia_add(&priv->media,
3575                             mlx5e_mode_table[i].subtype |
3576                             IFM_ETHER, 0, NULL);
3577                         ifmedia_add(&priv->media,
3578                             mlx5e_mode_table[i].subtype |
3579                             IFM_ETHER | IFM_FDX |
3580                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3581                 }
3582         }
3583
3584         /* Additional supported medias */
3585         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3586         ifmedia_add(&priv->media, IFM_10G_LR |
3587             IFM_ETHER | IFM_FDX |
3588             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3589
3590         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3591         ifmedia_add(&priv->media, IFM_40G_ER4 |
3592             IFM_ETHER | IFM_FDX |
3593             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3594
3595         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3596         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3597             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3598
3599         /* Set autoselect by default */
3600         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3601             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3602         ether_ifattach(ifp, dev_addr);
3603
3604         /* Register for VLAN events */
3605         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3606             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3607         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3608             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3609
3610         /* Link is down by default */
3611         if_link_state_change(ifp, LINK_STATE_DOWN);
3612
3613         mlx5e_enable_async_events(priv);
3614
3615         mlx5e_add_hw_stats(priv);
3616
3617         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3618             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3619             priv->stats.vport.arg);
3620
3621         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3622             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3623             priv->stats.pport.arg);
3624
3625         mlx5e_create_ethtool(priv);
3626
3627         mtx_lock(&priv->async_events_mtx);
3628         mlx5e_update_stats(priv);
3629         mtx_unlock(&priv->async_events_mtx);
3630
3631         return (priv);
3632
3633 err_dealloc_transport_domain:
3634         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3635
3636 err_dealloc_pd:
3637         mlx5_core_dealloc_pd(mdev, priv->pdn);
3638
3639 err_unmap_free_uar:
3640         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3641
3642 err_free_wq:
3643         destroy_workqueue(priv->wq);
3644
3645 err_free_sysctl:
3646         sysctl_ctx_free(&priv->sysctl_ctx);
3647         if (priv->sysctl_debug)
3648                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3649         if_free(ifp);
3650
3651 err_free_priv:
3652         mlx5e_priv_mtx_destroy(priv);
3653         free(priv, M_MLX5EN);
3654         return (NULL);
3655 }
3656
3657 static void
3658 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3659 {
3660         struct mlx5e_priv *priv = vpriv;
3661         struct ifnet *ifp = priv->ifp;
3662
3663         /* don't allow more IOCTLs */
3664         priv->gone = 1;
3665
3666         /* XXX wait a bit to allow IOCTL handlers to complete */
3667         pause("W", hz);
3668
3669         /* stop watchdog timer */
3670         callout_drain(&priv->watchdog);
3671
3672         if (priv->vlan_attach != NULL)
3673                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3674         if (priv->vlan_detach != NULL)
3675                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3676
3677         /* make sure device gets closed */
3678         PRIV_LOCK(priv);
3679         mlx5e_close_locked(ifp);
3680         PRIV_UNLOCK(priv);
3681
3682         /* unregister device */
3683         ifmedia_removeall(&priv->media);
3684         ether_ifdetach(ifp);
3685         if_free(ifp);
3686
3687         /* destroy all remaining sysctl nodes */
3688         sysctl_ctx_free(&priv->stats.vport.ctx);
3689         sysctl_ctx_free(&priv->stats.pport.ctx);
3690         sysctl_ctx_free(&priv->sysctl_ctx);
3691         if (priv->sysctl_debug)
3692                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3693
3694         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3695         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3696         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3697         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3698         mlx5e_disable_async_events(priv);
3699         destroy_workqueue(priv->wq);
3700         mlx5e_priv_mtx_destroy(priv);
3701         free(priv, M_MLX5EN);
3702 }
3703
3704 static void *
3705 mlx5e_get_ifp(void *vpriv)
3706 {
3707         struct mlx5e_priv *priv = vpriv;
3708
3709         return (priv->ifp);
3710 }
3711
3712 static struct mlx5_interface mlx5e_interface = {
3713         .add = mlx5e_create_ifp,
3714         .remove = mlx5e_destroy_ifp,
3715         .event = mlx5e_async_event,
3716         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3717         .get_dev = mlx5e_get_ifp,
3718 };
3719
3720 void
3721 mlx5e_init(void)
3722 {
3723         mlx5_register_interface(&mlx5e_interface);
3724 }
3725
3726 void
3727 mlx5e_cleanup(void)
3728 {
3729         mlx5_unregister_interface(&mlx5e_interface);
3730 }
3731
3732 static void
3733 mlx5e_show_version(void __unused *arg)
3734 {
3735
3736         printf("%s", mlx5e_version);
3737 }
3738 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
3739
3740 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3741 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3742
3743 #if (__FreeBSD_version >= 1100000)
3744 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3745 #endif
3746 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3747 MODULE_VERSION(mlx5en, 1);