sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "opt_kern_tls.h"
  29
  30 #include "en.h"
  31
  32 #include <sys/eventhandler.h>
  33 #include <sys/sockio.h>
  34 #include <machine/atomic.h>
  35
  36 #include <net/debugnet.h>
  37
  38 #ifndef ETH_DRIVER_VERSION
  39 #define ETH_DRIVER_VERSION      "3.5.2"
  40 #endif
  41 #define DRIVER_RELDATE  "September 2019"
  42
  43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  44         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  45
  46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  47
  48 struct mlx5e_channel_param {
  49         struct mlx5e_rq_param rq;
  50         struct mlx5e_sq_param sq;
  51         struct mlx5e_cq_param rx_cq;
  52         struct mlx5e_cq_param tx_cq;
  53 };
  54
  55 struct media {
  56         u32     subtype;
  57         u64     baudrate;
  58 };
  59
  60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  61
  62         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  63                 .subtype = IFM_1000_CX_SGMII,
  64                 .baudrate = IF_Mbps(1000ULL),
  65         },
  66         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  67                 .subtype = IFM_1000_KX,
  68                 .baudrate = IF_Mbps(1000ULL),
  69         },
  70         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  71                 .subtype = IFM_10G_CX4,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  75                 .subtype = IFM_10G_KX4,
  76                 .baudrate = IF_Gbps(10ULL),
  77         },
  78         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  79                 .subtype = IFM_10G_KR,
  80                 .baudrate = IF_Gbps(10ULL),
  81         },
  82         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  83                 .subtype = IFM_20G_KR2,
  84                 .baudrate = IF_Gbps(20ULL),
  85         },
  86         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  87                 .subtype = IFM_40G_CR4,
  88                 .baudrate = IF_Gbps(40ULL),
  89         },
  90         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  91                 .subtype = IFM_40G_KR4,
  92                 .baudrate = IF_Gbps(40ULL),
  93         },
  94         [MLX5E_56GBASE_R4][MLX5E_R] = {
  95                 .subtype = IFM_56G_R4,
  96                 .baudrate = IF_Gbps(56ULL),
  97         },
  98         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  99                 .subtype = IFM_10G_CR1,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_10GBASE_SR][MLX5E_SR] = {
 103                 .subtype = IFM_10G_SR,
 104                 .baudrate = IF_Gbps(10ULL),
 105         },
 106         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 107                 .subtype = IFM_10G_ER,
 108                 .baudrate = IF_Gbps(10ULL),
 109         },
 110         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 111                 .subtype = IFM_10G_LR,
 112                 .baudrate = IF_Gbps(10ULL),
 113         },
 114         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 115                 .subtype = IFM_40G_SR4,
 116                 .baudrate = IF_Gbps(40ULL),
 117         },
 118         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 119                 .subtype = IFM_40G_LR4,
 120                 .baudrate = IF_Gbps(40ULL),
 121         },
 122         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 123                 .subtype = IFM_40G_ER4,
 124                 .baudrate = IF_Gbps(40ULL),
 125         },
 126         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 127                 .subtype = IFM_100G_CR4,
 128                 .baudrate = IF_Gbps(100ULL),
 129         },
 130         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 131                 .subtype = IFM_100G_SR4,
 132                 .baudrate = IF_Gbps(100ULL),
 133         },
 134         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 135                 .subtype = IFM_100G_KR4,
 136                 .baudrate = IF_Gbps(100ULL),
 137         },
 138         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 139                 .subtype = IFM_100G_LR4,
 140                 .baudrate = IF_Gbps(100ULL),
 141         },
 142         [MLX5E_100BASE_TX][MLX5E_TX] = {
 143                 .subtype = IFM_100_TX,
 144                 .baudrate = IF_Mbps(100ULL),
 145         },
 146         [MLX5E_1000BASE_T][MLX5E_T] = {
 147                 .subtype = IFM_1000_T,
 148                 .baudrate = IF_Mbps(1000ULL),
 149         },
 150         [MLX5E_10GBASE_T][MLX5E_T] = {
 151                 .subtype = IFM_10G_T,
 152                 .baudrate = IF_Gbps(10ULL),
 153         },
 154         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 155                 .subtype = IFM_25G_CR,
 156                 .baudrate = IF_Gbps(25ULL),
 157         },
 158         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 159                 .subtype = IFM_25G_KR,
 160                 .baudrate = IF_Gbps(25ULL),
 161         },
 162         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 163                 .subtype = IFM_25G_SR,
 164                 .baudrate = IF_Gbps(25ULL),
 165         },
 166         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 167                 .subtype = IFM_50G_CR2,
 168                 .baudrate = IF_Gbps(50ULL),
 169         },
 170         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 171                 .subtype = IFM_50G_KR2,
 172                 .baudrate = IF_Gbps(50ULL),
 173         },
 174         [MLX5E_50GBASE_KR4][MLX5E_KR4] = {
 175                 .subtype = IFM_50G_KR4,
 176                 .baudrate = IF_Gbps(50ULL),
 177         },
 178 };
 179
 180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 181         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 182                 .subtype = IFM_100_SGMII,
 183                 .baudrate = IF_Mbps(100),
 184         },
 185         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 186                 .subtype = IFM_1000_KX,
 187                 .baudrate = IF_Mbps(1000),
 188         },
 189         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 190                 .subtype = IFM_1000_CX_SGMII,
 191                 .baudrate = IF_Mbps(1000),
 192         },
 193         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 194                 .subtype = IFM_1000_CX,
 195                 .baudrate = IF_Mbps(1000),
 196         },
 197         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 198                 .subtype = IFM_1000_LX,
 199                 .baudrate = IF_Mbps(1000),
 200         },
 201         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 202                 .subtype = IFM_1000_SX,
 203                 .baudrate = IF_Mbps(1000),
 204         },
 205         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 206                 .subtype = IFM_1000_T,
 207                 .baudrate = IF_Mbps(1000),
 208         },
 209         [MLX5E_5GBASE_R][MLX5E_T] = {
 210                 .subtype = IFM_5000_T,
 211                 .baudrate = IF_Mbps(5000),
 212         },
 213         [MLX5E_5GBASE_R][MLX5E_KR] = {
 214                 .subtype = IFM_5000_KR,
 215                 .baudrate = IF_Mbps(5000),
 216         },
 217         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 218                 .subtype = IFM_5000_KR1,
 219                 .baudrate = IF_Mbps(5000),
 220         },
 221         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 222                 .subtype = IFM_5000_KR_S,
 223                 .baudrate = IF_Mbps(5000),
 224         },
 225         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 226                 .subtype = IFM_10G_ER,
 227                 .baudrate = IF_Gbps(10ULL),
 228         },
 229         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 230                 .subtype = IFM_10G_KR,
 231                 .baudrate = IF_Gbps(10ULL),
 232         },
 233         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 234                 .subtype = IFM_10G_LR,
 235                 .baudrate = IF_Gbps(10ULL),
 236         },
 237         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 238                 .subtype = IFM_10G_SR,
 239                 .baudrate = IF_Gbps(10ULL),
 240         },
 241         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 242                 .subtype = IFM_10G_T,
 243                 .baudrate = IF_Gbps(10ULL),
 244         },
 245         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 246                 .subtype = IFM_10G_AOC,
 247                 .baudrate = IF_Gbps(10ULL),
 248         },
 249         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 250                 .subtype = IFM_10G_CR1,
 251                 .baudrate = IF_Gbps(10ULL),
 252         },
 253         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 254                 .subtype = IFM_40G_CR4,
 255                 .baudrate = IF_Gbps(40ULL),
 256         },
 257         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 258                 .subtype = IFM_40G_KR4,
 259                 .baudrate = IF_Gbps(40ULL),
 260         },
 261         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 262                 .subtype = IFM_40G_LR4,
 263                 .baudrate = IF_Gbps(40ULL),
 264         },
 265         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 266                 .subtype = IFM_40G_SR4,
 267                 .baudrate = IF_Gbps(40ULL),
 268         },
 269         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 270                 .subtype = IFM_40G_ER4,
 271                 .baudrate = IF_Gbps(40ULL),
 272         },
 273
 274         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 275                 .subtype = IFM_25G_CR,
 276                 .baudrate = IF_Gbps(25ULL),
 277         },
 278         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 279                 .subtype = IFM_25G_KR,
 280                 .baudrate = IF_Gbps(25ULL),
 281         },
 282         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 283                 .subtype = IFM_25G_SR,
 284                 .baudrate = IF_Gbps(25ULL),
 285         },
 286         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 287                 .subtype = IFM_25G_ACC,
 288                 .baudrate = IF_Gbps(25ULL),
 289         },
 290         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 291                 .subtype = IFM_25G_AOC,
 292                 .baudrate = IF_Gbps(25ULL),
 293         },
 294         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 295                 .subtype = IFM_25G_CR1,
 296                 .baudrate = IF_Gbps(25ULL),
 297         },
 298         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 299                 .subtype = IFM_25G_CR_S,
 300                 .baudrate = IF_Gbps(25ULL),
 301         },
 302         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 303                 .subtype = IFM_5000_KR1,
 304                 .baudrate = IF_Gbps(25ULL),
 305         },
 306         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 307                 .subtype = IFM_25G_KR_S,
 308                 .baudrate = IF_Gbps(25ULL),
 309         },
 310         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 311                 .subtype = IFM_25G_LR,
 312                 .baudrate = IF_Gbps(25ULL),
 313         },
 314         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 315                 .subtype = IFM_25G_T,
 316                 .baudrate = IF_Gbps(25ULL),
 317         },
 318         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 319                 .subtype = IFM_50G_CR2,
 320                 .baudrate = IF_Gbps(50ULL),
 321         },
 322         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 323                 .subtype = IFM_50G_KR2,
 324                 .baudrate = IF_Gbps(50ULL),
 325         },
 326         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = {
 327                 .subtype = IFM_50G_KR4,
 328                 .baudrate = IF_Gbps(50ULL),
 329         },
 330         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 331                 .subtype = IFM_50G_SR2,
 332                 .baudrate = IF_Gbps(50ULL),
 333         },
 334         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 335                 .subtype = IFM_50G_LR2,
 336                 .baudrate = IF_Gbps(50ULL),
 337         },
 338         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 339                 .subtype = IFM_50G_LR,
 340                 .baudrate = IF_Gbps(50ULL),
 341         },
 342         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 343                 .subtype = IFM_50G_SR,
 344                 .baudrate = IF_Gbps(50ULL),
 345         },
 346         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 347                 .subtype = IFM_50G_CP,
 348                 .baudrate = IF_Gbps(50ULL),
 349         },
 350         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 351                 .subtype = IFM_50G_FR,
 352                 .baudrate = IF_Gbps(50ULL),
 353         },
 354         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 355                 .subtype = IFM_50G_KR_PAM4,
 356                 .baudrate = IF_Gbps(50ULL),
 357         },
 358         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 359                 .subtype = IFM_100G_CR4,
 360                 .baudrate = IF_Gbps(100ULL),
 361         },
 362         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 363                 .subtype = IFM_100G_KR4,
 364                 .baudrate = IF_Gbps(100ULL),
 365         },
 366         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 367                 .subtype = IFM_100G_LR4,
 368                 .baudrate = IF_Gbps(100ULL),
 369         },
 370         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 371                 .subtype = IFM_100G_SR4,
 372                 .baudrate = IF_Gbps(100ULL),
 373         },
 374         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 375                 .subtype = IFM_100G_SR2,
 376                 .baudrate = IF_Gbps(100ULL),
 377         },
 378         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 379                 .subtype = IFM_100G_CP2,
 380                 .baudrate = IF_Gbps(100ULL),
 381         },
 382         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 383                 .subtype = IFM_100G_KR2_PAM4,
 384                 .baudrate = IF_Gbps(100ULL),
 385         },
 386         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 387                 .subtype = IFM_200G_DR4,
 388                 .baudrate = IF_Gbps(200ULL),
 389         },
 390         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 391                 .subtype = IFM_200G_LR4,
 392                 .baudrate = IF_Gbps(200ULL),
 393         },
 394         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 395                 .subtype = IFM_200G_SR4,
 396                 .baudrate = IF_Gbps(200ULL),
 397         },
 398         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 399                 .subtype = IFM_200G_FR4,
 400                 .baudrate = IF_Gbps(200ULL),
 401         },
 402         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 403                 .subtype = IFM_200G_CR4_PAM4,
 404                 .baudrate = IF_Gbps(200ULL),
 405         },
 406         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 407                 .subtype = IFM_200G_KR4_PAM4,
 408                 .baudrate = IF_Gbps(200ULL),
 409         },
 410 };
 411
 412 DEBUGNET_DEFINE(mlx5_en);
 413
 414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 415
 416 static void
 417 mlx5e_update_carrier(struct mlx5e_priv *priv)
 418 {
 419         struct mlx5_core_dev *mdev = priv->mdev;
 420         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 421         u32 eth_proto_oper;
 422         int error;
 423         u8 port_state;
 424         u8 is_er_type;
 425         u8 i, j;
 426         bool ext;
 427         struct media media_entry = {};
 428
 429         port_state = mlx5_query_vport_state(mdev,
 430             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 431
 432         if (port_state == VPORT_STATE_UP) {
 433                 priv->media_status_last |= IFM_ACTIVE;
 434         } else {
 435                 priv->media_status_last &= ~IFM_ACTIVE;
 436                 priv->media_active_last = IFM_ETHER;
 437                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 438                 return;
 439         }
 440
 441         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 442             MLX5_PTYS_EN, 1);
 443         if (error) {
 444                 priv->media_active_last = IFM_ETHER;
 445                 priv->ifp->if_baudrate = 1;
 446                 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
 447                     error);
 448                 return;
 449         }
 450
 451         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 452         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 453             eth_proto_oper);
 454
 455         i = ilog2(eth_proto_oper);
 456
 457         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 458                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 459                     mlx5e_mode_table[i][j];
 460                 if (media_entry.baudrate != 0)
 461                         break;
 462         }
 463
 464         if (media_entry.subtype == 0) {
 465                 mlx5_en_err(priv->ifp,
 466                     "Could not find operational media subtype\n");
 467                 return;
 468         }
 469
 470         switch (media_entry.subtype) {
 471         case IFM_10G_ER:
 472                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 473                 if (error != 0) {
 474                         mlx5_en_err(priv->ifp,
 475                             "query port pddr failed: %d\n", error);
 476                 }
 477                 if (error != 0 || is_er_type == 0)
 478                         media_entry.subtype = IFM_10G_LR;
 479                 break;
 480         case IFM_40G_LR4:
 481                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 482                 if (error != 0) {
 483                         mlx5_en_err(priv->ifp,
 484                             "query port pddr failed: %d\n", error);
 485                 }
 486                 if (error == 0 && is_er_type != 0)
 487                         media_entry.subtype = IFM_40G_ER4;
 488                 break;
 489         }
 490         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 491         priv->ifp->if_baudrate = media_entry.baudrate;
 492
 493         if_link_state_change(priv->ifp, LINK_STATE_UP);
 494 }
 495
 496 static void
 497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 498 {
 499         struct mlx5e_priv *priv = dev->if_softc;
 500
 501         ifmr->ifm_status = priv->media_status_last;
 502         ifmr->ifm_active = priv->media_active_last |
 503             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 504             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 505
 506 }
 507
 508 static u32
 509 mlx5e_find_link_mode(u32 subtype, bool ext)
 510 {
 511         u32 i;
 512         u32 j;
 513         u32 link_mode = 0;
 514         u32 speeds_num = 0;
 515         struct media media_entry = {};
 516
 517         switch (subtype) {
 518         case IFM_10G_LR:
 519                 subtype = IFM_10G_ER;
 520                 break;
 521         case IFM_40G_ER4:
 522                 subtype = IFM_40G_LR4;
 523                 break;
 524         }
 525
 526         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 527             MLX5E_LINK_SPEEDS_NUMBER;
 528
 529         for (i = 0; i != speeds_num; i++) {
 530                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 531                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 532                             mlx5e_mode_table[i][j];
 533                         if (media_entry.baudrate == 0)
 534                                 continue;
 535                         if (media_entry.subtype == subtype) {
 536                                 link_mode |= MLX5E_PROT_MASK(i);
 537                         }
 538                 }
 539         }
 540
 541         return (link_mode);
 542 }
 543
 544 static int
 545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 546 {
 547         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 548             priv->params.rx_pauseframe_control,
 549             priv->params.tx_pauseframe_control,
 550             priv->params.rx_priority_flow_control,
 551             priv->params.tx_priority_flow_control));
 552 }
 553
 554 static int
 555 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 556 {
 557         int error;
 558
 559         if (priv->gone != 0) {
 560                 error = -ENXIO;
 561         } else if (priv->params.rx_pauseframe_control ||
 562             priv->params.tx_pauseframe_control) {
 563                 mlx5_en_err(priv->ifp,
 564                     "Global pauseframes must be disabled before enabling PFC.\n");
 565                 error = -EINVAL;
 566         } else {
 567                 error = mlx5e_set_port_pause_and_pfc(priv);
 568         }
 569         return (error);
 570 }
 571
 572 static int
 573 mlx5e_media_change(struct ifnet *dev)
 574 {
 575         struct mlx5e_priv *priv = dev->if_softc;
 576         struct mlx5_core_dev *mdev = priv->mdev;
 577         u32 eth_proto_cap;
 578         u32 link_mode;
 579         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 580         int was_opened;
 581         int locked;
 582         int error;
 583         bool ext;
 584
 585         locked = PRIV_LOCKED(priv);
 586         if (!locked)
 587                 PRIV_LOCK(priv);
 588
 589         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 590                 error = EINVAL;
 591                 goto done;
 592         }
 593
 594         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 595             MLX5_PTYS_EN, 1);
 596         if (error != 0) {
 597                 mlx5_en_err(dev, "Query port media capability failed\n");
 598                 goto done;
 599         }
 600
 601         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 602         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 603
 604         /* query supported capabilities */
 605         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 606             eth_proto_capability);
 607
 608         /* check for autoselect */
 609         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 610                 link_mode = eth_proto_cap;
 611                 if (link_mode == 0) {
 612                         mlx5_en_err(dev, "Port media capability is zero\n");
 613                         error = EINVAL;
 614                         goto done;
 615                 }
 616         } else {
 617                 link_mode = link_mode & eth_proto_cap;
 618                 if (link_mode == 0) {
 619                         mlx5_en_err(dev, "Not supported link mode requested\n");
 620                         error = EINVAL;
 621                         goto done;
 622                 }
 623         }
 624         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 625                 /* check if PFC is enabled */
 626                 if (priv->params.rx_priority_flow_control ||
 627                     priv->params.tx_priority_flow_control) {
 628                         mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
 629                         error = EINVAL;
 630                         goto done;
 631                 }
 632         }
 633         /* update pauseframe control bits */
 634         priv->params.rx_pauseframe_control =
 635             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 636         priv->params.tx_pauseframe_control =
 637             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 638
 639         /* check if device is opened */
 640         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 641
 642         /* reconfigure the hardware */
 643         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 644         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 645         error = -mlx5e_set_port_pause_and_pfc(priv);
 646         if (was_opened)
 647                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 648
 649 done:
 650         if (!locked)
 651                 PRIV_UNLOCK(priv);
 652         return (error);
 653 }
 654
 655 static void
 656 mlx5e_update_carrier_work(struct work_struct *work)
 657 {
 658         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 659             update_carrier_work);
 660
 661         PRIV_LOCK(priv);
 662         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 663                 mlx5e_update_carrier(priv);
 664         PRIV_UNLOCK(priv);
 665 }
 666
 667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 668         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 669
 670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 671         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 672
 673 static void
 674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 675 {
 676         struct mlx5_core_dev *mdev = priv->mdev;
 677         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 678         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 679         void *out;
 680         void *in;
 681         int err;
 682
 683         /* allocate firmware request structures */
 684         in = mlx5_vzalloc(sz);
 685         out = mlx5_vzalloc(sz);
 686         if (in == NULL || out == NULL)
 687                 goto free_out;
 688
 689         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 690         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 691         if (err != 0)
 692                 goto free_out;
 693
 694         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 695         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 698         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 699         if (err != 0)
 700                 goto free_out;
 701
 702         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 703
 704         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 705         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 706         if (err != 0)
 707                 goto free_out;
 708
 709         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 710
 711 free_out:
 712         /* free firmware request structures */
 713         kvfree(in);
 714         kvfree(out);
 715 }
 716
 717 /*
 718  * This function reads the physical port counters from the firmware
 719  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 720  * macros. The output is converted from big-endian 64-bit values into
 721  * host endian ones and stored in the "priv->stats.pport" structure.
 722  */
 723 static void
 724 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 725 {
 726         struct mlx5_core_dev *mdev = priv->mdev;
 727         struct mlx5e_pport_stats *s = &priv->stats.pport;
 728         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 729         u32 *in;
 730         u32 *out;
 731         const u64 *ptr;
 732         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 733         unsigned x;
 734         unsigned y;
 735         unsigned z;
 736
 737         /* allocate firmware request structures */
 738         in = mlx5_vzalloc(sz);
 739         out = mlx5_vzalloc(sz);
 740         if (in == NULL || out == NULL)
 741                 goto free_out;
 742
 743         /*
 744          * Get pointer to the 64-bit counter set which is located at a
 745          * fixed offset in the output firmware request structure:
 746          */
 747         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 748
 749         MLX5_SET(ppcnt_reg, in, local_port, 1);
 750
 751         /* read IEEE802_3 counter group using predefined counter layout */
 752         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 753         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 754         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 755              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 756                 s->arg[y] = be64toh(ptr[x]);
 757
 758         /* read RFC2819 counter group using predefined counter layout */
 759         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 760         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 761         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 762                 s->arg[y] = be64toh(ptr[x]);
 763
 764         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 765             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 766                 s_debug->arg[y] = be64toh(ptr[x]);
 767
 768         /* read RFC2863 counter group using predefined counter layout */
 769         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 770         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 771         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 772                 s_debug->arg[y] = be64toh(ptr[x]);
 773
 774         /* read physical layer stats counter group using predefined counter layout */
 775         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 776         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 777         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 778                 s_debug->arg[y] = be64toh(ptr[x]);
 779
 780         /* read Extended Ethernet counter group using predefined counter layout */
 781         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 782         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 783         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 784                 s_debug->arg[y] = be64toh(ptr[x]);
 785
 786         /* read Extended Statistical Group */
 787         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 788             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 789             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 790                 /* read Extended Statistical counter group using predefined counter layout */
 791                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 792                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 793
 794                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 795                         s_debug->arg[y] = be64toh(ptr[x]);
 796         }
 797
 798         /* read PCIE counters */
 799         mlx5e_update_pcie_counters(priv);
 800
 801         /* read per-priority counters */
 802         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 803
 804         /* iterate all the priorities */
 805         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 806                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 807                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 808
 809                 /* read per priority stats counter group using predefined counter layout */
 810                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 811                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 812                         s->arg[y] = be64toh(ptr[x]);
 813         }
 814
 815 free_out:
 816         /* free firmware request structures */
 817         kvfree(in);
 818         kvfree(out);
 819 }
 820
 821 static void
 822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 823 {
 824         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 825         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 826
 827         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 828                 return;
 829
 830         MLX5_SET(query_vnic_env_in, in, opcode,
 831             MLX5_CMD_OP_QUERY_VNIC_ENV);
 832         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 833         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 834
 835         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 836                 return;
 837
 838         priv->stats.vport.rx_steer_missed_packets =
 839             MLX5_GET64(query_vnic_env_out, out,
 840             vport_env.nic_receive_steering_discard);
 841 }
 842
 843 /*
 844  * This function is called regularly to collect all statistics
 845  * counters from the firmware. The values can be viewed through the
 846  * sysctl interface. Execution is serialized using the priv's global
 847  * configuration lock.
 848  */
 849 static void
 850 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 851 {
 852         struct mlx5_core_dev *mdev = priv->mdev;
 853         struct mlx5e_vport_stats *s = &priv->stats.vport;
 854         struct mlx5e_sq_stats *sq_stats;
 855 #if (__FreeBSD_version < 1100000)
 856         struct ifnet *ifp = priv->ifp;
 857 #endif
 858
 859         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 860         u32 *out;
 861         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 862         u64 tso_packets = 0;
 863         u64 tso_bytes = 0;
 864         u64 tx_queue_dropped = 0;
 865         u64 tx_defragged = 0;
 866         u64 tx_offload_none = 0;
 867         u64 lro_packets = 0;
 868         u64 lro_bytes = 0;
 869         u64 sw_lro_queued = 0;
 870         u64 sw_lro_flushed = 0;
 871         u64 rx_csum_none = 0;
 872         u64 rx_wqe_err = 0;
 873         u64 rx_packets = 0;
 874         u64 rx_bytes = 0;
 875         u32 rx_out_of_buffer = 0;
 876         int error;
 877         int i;
 878         int j;
 879
 880         out = mlx5_vzalloc(outlen);
 881         if (out == NULL)
 882                 goto free_out;
 883
 884         /* Collect firts the SW counters and then HW for consistency */
 885         for (i = 0; i < priv->params.num_channels; i++) {
 886                 struct mlx5e_channel *pch = priv->channel + i;
 887                 struct mlx5e_rq *rq = &pch->rq;
 888                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 889
 890                 /* collect stats from LRO */
 891                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 892                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 893                 sw_lro_queued += rq_stats->sw_lro_queued;
 894                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 895                 lro_packets += rq_stats->lro_packets;
 896                 lro_bytes += rq_stats->lro_bytes;
 897                 rx_csum_none += rq_stats->csum_none;
 898                 rx_wqe_err += rq_stats->wqe_err;
 899                 rx_packets += rq_stats->packets;
 900                 rx_bytes += rq_stats->bytes;
 901
 902                 for (j = 0; j < priv->num_tc; j++) {
 903                         sq_stats = &pch->sq[j].stats;
 904
 905                         tso_packets += sq_stats->tso_packets;
 906                         tso_bytes += sq_stats->tso_bytes;
 907                         tx_queue_dropped += sq_stats->dropped;
 908                         tx_queue_dropped += sq_stats->enobuf;
 909                         tx_defragged += sq_stats->defragged;
 910                         tx_offload_none += sq_stats->csum_offload_none;
 911                 }
 912         }
 913
 914         /* update counters */
 915         s->tso_packets = tso_packets;
 916         s->tso_bytes = tso_bytes;
 917         s->tx_queue_dropped = tx_queue_dropped;
 918         s->tx_defragged = tx_defragged;
 919         s->lro_packets = lro_packets;
 920         s->lro_bytes = lro_bytes;
 921         s->sw_lro_queued = sw_lro_queued;
 922         s->sw_lro_flushed = sw_lro_flushed;
 923         s->rx_csum_none = rx_csum_none;
 924         s->rx_wqe_err = rx_wqe_err;
 925         s->rx_packets = rx_packets;
 926         s->rx_bytes = rx_bytes;
 927
 928         mlx5e_grp_vnic_env_update_stats(priv);
 929
 930         /* HW counters */
 931         memset(in, 0, sizeof(in));
 932
 933         MLX5_SET(query_vport_counter_in, in, opcode,
 934             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 935         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 936         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 937
 938         memset(out, 0, outlen);
 939
 940         /* get number of out-of-buffer drops first */
 941         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 942             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 943             &rx_out_of_buffer) == 0) {
 944                 s->rx_out_of_buffer = rx_out_of_buffer;
 945         }
 946
 947         /* get port statistics */
 948         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 949 #define MLX5_GET_CTR(out, x) \
 950         MLX5_GET64(query_vport_counter_out, out, x)
 951
 952                 s->rx_error_packets =
 953                     MLX5_GET_CTR(out, received_errors.packets);
 954                 s->rx_error_bytes =
 955                     MLX5_GET_CTR(out, received_errors.octets);
 956                 s->tx_error_packets =
 957                     MLX5_GET_CTR(out, transmit_errors.packets);
 958                 s->tx_error_bytes =
 959                     MLX5_GET_CTR(out, transmit_errors.octets);
 960
 961                 s->rx_unicast_packets =
 962                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 963                 s->rx_unicast_bytes =
 964                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 965                 s->tx_unicast_packets =
 966                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 967                 s->tx_unicast_bytes =
 968                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 969
 970                 s->rx_multicast_packets =
 971                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 972                 s->rx_multicast_bytes =
 973                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 974                 s->tx_multicast_packets =
 975                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 976                 s->tx_multicast_bytes =
 977                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 978
 979                 s->rx_broadcast_packets =
 980                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 981                 s->rx_broadcast_bytes =
 982                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 983                 s->tx_broadcast_packets =
 984                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 985                 s->tx_broadcast_bytes =
 986                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 987
 988                 s->tx_packets = s->tx_unicast_packets +
 989                     s->tx_multicast_packets + s->tx_broadcast_packets;
 990                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 991                     s->tx_broadcast_bytes;
 992
 993                 /* Update calculated offload counters */
 994                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 995                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 996         }
 997
 998         /* Get physical port counters */
 999         mlx5e_update_pport_counters(priv);
1000
1001         s->tx_jumbo_packets =
1002             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1003             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1004             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1005             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1006
1007 #if (__FreeBSD_version < 1100000)
1008         /* no get_counters interface in fbsd 10 */
1009         ifp->if_ipackets = s->rx_packets;
1010         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1011             priv->stats.pport.out_of_range_len +
1012             priv->stats.pport.too_long_errors +
1013             priv->stats.pport.check_seq_err +
1014             priv->stats.pport.alignment_err;
1015         ifp->if_iqdrops = s->rx_out_of_buffer;
1016         ifp->if_opackets = s->tx_packets;
1017         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1018         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1019         ifp->if_ibytes = s->rx_bytes;
1020         ifp->if_obytes = s->tx_bytes;
1021         ifp->if_collisions =
1022             priv->stats.pport.collisions;
1023 #endif
1024
1025 free_out:
1026         kvfree(out);
1027
1028         /* Update diagnostics, if any */
1029         if (priv->params_ethtool.diag_pci_enable ||
1030             priv->params_ethtool.diag_general_enable) {
1031                 error = mlx5_core_get_diagnostics_full(mdev,
1032                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1033                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1034                 if (error != 0)
1035                         mlx5_en_err(priv->ifp,
1036                             "Failed reading diagnostics: %d\n", error);
1037         }
1038
1039         /* Update FEC, if any */
1040         error = mlx5e_fec_update(priv);
1041         if (error != 0 && error != EOPNOTSUPP) {
1042                 mlx5_en_err(priv->ifp,
1043                     "Updating FEC failed: %d\n", error);
1044         }
1045 }
1046
1047 static void
1048 mlx5e_update_stats_work(struct work_struct *work)
1049 {
1050         struct mlx5e_priv *priv;
1051
1052         priv = container_of(work, struct mlx5e_priv, update_stats_work);
1053         PRIV_LOCK(priv);
1054         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1055             !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1056                 mlx5e_update_stats_locked(priv);
1057         PRIV_UNLOCK(priv);
1058 }
1059
1060 static void
1061 mlx5e_update_stats(void *arg)
1062 {
1063         struct mlx5e_priv *priv = arg;
1064
1065         queue_work(priv->wq, &priv->update_stats_work);
1066
1067         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1068 }
1069
1070 static void
1071 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1072     enum mlx5_dev_event event)
1073 {
1074         switch (event) {
1075         case MLX5_DEV_EVENT_PORT_UP:
1076         case MLX5_DEV_EVENT_PORT_DOWN:
1077                 queue_work(priv->wq, &priv->update_carrier_work);
1078                 break;
1079
1080         default:
1081                 break;
1082         }
1083 }
1084
1085 static void
1086 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1087     enum mlx5_dev_event event, unsigned long param)
1088 {
1089         struct mlx5e_priv *priv = vpriv;
1090
1091         mtx_lock(&priv->async_events_mtx);
1092         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1093                 mlx5e_async_event_sub(priv, event);
1094         mtx_unlock(&priv->async_events_mtx);
1095 }
1096
1097 static void
1098 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1099 {
1100         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1101 }
1102
1103 static void
1104 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1105 {
1106         mtx_lock(&priv->async_events_mtx);
1107         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1108         mtx_unlock(&priv->async_events_mtx);
1109 }
1110
1111 static void mlx5e_calibration_callout(void *arg);
1112 static int mlx5e_calibration_duration = 20;
1113 static int mlx5e_fast_calibration = 1;
1114 static int mlx5e_normal_calibration = 30;
1115
1116 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1117     "MLX5 timestamp calibration parameteres");
1118
1119 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1120     &mlx5e_calibration_duration, 0,
1121     "Duration of initial calibration");
1122 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1123     &mlx5e_fast_calibration, 0,
1124     "Recalibration interval during initial calibration");
1125 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1126     &mlx5e_normal_calibration, 0,
1127     "Recalibration interval during normal operations");
1128
1129 /*
1130  * Ignites the calibration process.
1131  */
1132 static void
1133 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1134 {
1135
1136         if (priv->clbr_done == 0)
1137                 mlx5e_calibration_callout(priv);
1138         else
1139                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1140                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1141                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1142                     priv);
1143 }
1144
1145 static uint64_t
1146 mlx5e_timespec2usec(const struct timespec *ts)
1147 {
1148
1149         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1150 }
1151
1152 static uint64_t
1153 mlx5e_hw_clock(struct mlx5e_priv *priv)
1154 {
1155         struct mlx5_init_seg *iseg;
1156         uint32_t hw_h, hw_h1, hw_l;
1157
1158         iseg = priv->mdev->iseg;
1159         do {
1160                 hw_h = ioread32be(&iseg->internal_timer_h);
1161                 hw_l = ioread32be(&iseg->internal_timer_l);
1162                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1163         } while (hw_h1 != hw_h);
1164         return (((uint64_t)hw_h << 32) | hw_l);
1165 }
1166
1167 /*
1168  * The calibration callout, it runs either in the context of the
1169  * thread which enables calibration, or in callout.  It takes the
1170  * snapshot of system and adapter clocks, then advances the pointers to
1171  * the calibration point to allow rx path to read the consistent data
1172  * lockless.
1173  */
1174 static void
1175 mlx5e_calibration_callout(void *arg)
1176 {
1177         struct mlx5e_priv *priv;
1178         struct mlx5e_clbr_point *next, *curr;
1179         struct timespec ts;
1180         int clbr_curr_next;
1181
1182         priv = arg;
1183         curr = &priv->clbr_points[priv->clbr_curr];
1184         clbr_curr_next = priv->clbr_curr + 1;
1185         if (clbr_curr_next >= nitems(priv->clbr_points))
1186                 clbr_curr_next = 0;
1187         next = &priv->clbr_points[clbr_curr_next];
1188
1189         next->base_prev = curr->base_curr;
1190         next->clbr_hw_prev = curr->clbr_hw_curr;
1191
1192         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1193         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1194             0) {
1195                 if (priv->clbr_done != 0) {
1196                         mlx5_en_err(priv->ifp,
1197                             "HW failed tstmp frozen %#jx %#jx, disabling\n",
1198                              next->clbr_hw_curr, curr->clbr_hw_prev);
1199                         priv->clbr_done = 0;
1200                 }
1201                 atomic_store_rel_int(&curr->clbr_gen, 0);
1202                 return;
1203         }
1204
1205         nanouptime(&ts);
1206         next->base_curr = mlx5e_timespec2usec(&ts);
1207
1208         curr->clbr_gen = 0;
1209         atomic_thread_fence_rel();
1210         priv->clbr_curr = clbr_curr_next;
1211         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1212
1213         if (priv->clbr_done < mlx5e_calibration_duration)
1214                 priv->clbr_done++;
1215         mlx5e_reset_calibration_callout(priv);
1216 }
1217
1218 static const char *mlx5e_rq_stats_desc[] = {
1219         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1220 };
1221
1222 static int
1223 mlx5e_create_rq(struct mlx5e_channel *c,
1224     struct mlx5e_rq_param *param,
1225     struct mlx5e_rq *rq)
1226 {
1227         struct mlx5e_priv *priv = c->priv;
1228         struct mlx5_core_dev *mdev = priv->mdev;
1229         char buffer[16];
1230         void *rqc = param->rqc;
1231         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1232         int wq_sz;
1233         int err;
1234         int i;
1235         u32 nsegs, wqe_sz;
1236
1237         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1238         if (err != 0)
1239                 goto done;
1240
1241         /* Create DMA descriptor TAG */
1242         if ((err = -bus_dma_tag_create(
1243             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1244             1,                          /* any alignment */
1245             0,                          /* no boundary */
1246             BUS_SPACE_MAXADDR,          /* lowaddr */
1247             BUS_SPACE_MAXADDR,          /* highaddr */
1248             NULL, NULL,                 /* filter, filterarg */
1249             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1250             nsegs,                      /* nsegments */
1251             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1252             0,                          /* flags */
1253             NULL, NULL,                 /* lockfunc, lockfuncarg */
1254             &rq->dma_tag)))
1255                 goto done;
1256
1257         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1258             &rq->wq_ctrl);
1259         if (err)
1260                 goto err_free_dma_tag;
1261
1262         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1263
1264         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1265         if (err != 0)
1266                 goto err_rq_wq_destroy;
1267
1268         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1269
1270         err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1271         if (err)
1272                 goto err_rq_wq_destroy;
1273
1274         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1275         for (i = 0; i != wq_sz; i++) {
1276                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1277                 int j;
1278
1279                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1280                 if (err != 0) {
1281                         while (i--)
1282                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1283                         goto err_rq_mbuf_free;
1284                 }
1285
1286                 /* set value for constant fields */
1287                 for (j = 0; j < rq->nsegs; j++)
1288                         wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1289         }
1290
1291         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1292         if (priv->params.rx_cq_moderation_mode < 2) {
1293                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1294         } else {
1295                 void *cqc = container_of(param,
1296                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1297
1298                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1299                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1300                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1301                         break;
1302                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1303                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1304                         break;
1305                 default:
1306                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1307                         break;
1308                 }
1309         }
1310
1311         rq->ifp = priv->ifp;
1312         rq->channel = c;
1313         rq->ix = c->ix;
1314
1315         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1316         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1317             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1318             rq->stats.arg);
1319         return (0);
1320
1321 err_rq_mbuf_free:
1322         free(rq->mbuf, M_MLX5EN);
1323         tcp_lro_free(&rq->lro);
1324 err_rq_wq_destroy:
1325         mlx5_wq_destroy(&rq->wq_ctrl);
1326 err_free_dma_tag:
1327         bus_dma_tag_destroy(rq->dma_tag);
1328 done:
1329         return (err);
1330 }
1331
1332 static void
1333 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1334 {
1335         int wq_sz;
1336         int i;
1337
1338         /* destroy all sysctl nodes */
1339         sysctl_ctx_free(&rq->stats.ctx);
1340
1341         /* free leftover LRO packets, if any */
1342         tcp_lro_free(&rq->lro);
1343
1344         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1345         for (i = 0; i != wq_sz; i++) {
1346                 if (rq->mbuf[i].mbuf != NULL) {
1347                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1348                         m_freem(rq->mbuf[i].mbuf);
1349                 }
1350                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1351         }
1352         free(rq->mbuf, M_MLX5EN);
1353         mlx5_wq_destroy(&rq->wq_ctrl);
1354         bus_dma_tag_destroy(rq->dma_tag);
1355 }
1356
1357 static int
1358 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1359 {
1360         struct mlx5e_channel *c = rq->channel;
1361         struct mlx5e_priv *priv = c->priv;
1362         struct mlx5_core_dev *mdev = priv->mdev;
1363
1364         void *in;
1365         void *rqc;
1366         void *wq;
1367         int inlen;
1368         int err;
1369
1370         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1371             sizeof(u64) * rq->wq_ctrl.buf.npages;
1372         in = mlx5_vzalloc(inlen);
1373         if (in == NULL)
1374                 return (-ENOMEM);
1375
1376         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1377         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1378
1379         memcpy(rqc, param->rqc, sizeof(param->rqc));
1380
1381         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1382         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1383         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1384         if (priv->counter_set_id >= 0)
1385                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1386         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1387             PAGE_SHIFT);
1388         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1389
1390         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1391             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1392
1393         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1394
1395         kvfree(in);
1396
1397         return (err);
1398 }
1399
1400 static int
1401 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1402 {
1403         struct mlx5e_channel *c = rq->channel;
1404         struct mlx5e_priv *priv = c->priv;
1405         struct mlx5_core_dev *mdev = priv->mdev;
1406
1407         void *in;
1408         void *rqc;
1409         int inlen;
1410         int err;
1411
1412         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1413         in = mlx5_vzalloc(inlen);
1414         if (in == NULL)
1415                 return (-ENOMEM);
1416
1417         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1418
1419         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1420         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1421         MLX5_SET(rqc, rqc, state, next_state);
1422
1423         err = mlx5_core_modify_rq(mdev, in, inlen);
1424
1425         kvfree(in);
1426
1427         return (err);
1428 }
1429
1430 static void
1431 mlx5e_disable_rq(struct mlx5e_rq *rq)
1432 {
1433         struct mlx5e_channel *c = rq->channel;
1434         struct mlx5e_priv *priv = c->priv;
1435         struct mlx5_core_dev *mdev = priv->mdev;
1436
1437         mlx5_core_destroy_rq(mdev, rq->rqn);
1438 }
1439
1440 static int
1441 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1442 {
1443         struct mlx5e_channel *c = rq->channel;
1444         struct mlx5e_priv *priv = c->priv;
1445         struct mlx5_wq_ll *wq = &rq->wq;
1446         int i;
1447
1448         for (i = 0; i < 1000; i++) {
1449                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1450                         return (0);
1451
1452                 msleep(4);
1453         }
1454         return (-ETIMEDOUT);
1455 }
1456
1457 static int
1458 mlx5e_open_rq(struct mlx5e_channel *c,
1459     struct mlx5e_rq_param *param,
1460     struct mlx5e_rq *rq)
1461 {
1462         int err;
1463
1464         err = mlx5e_create_rq(c, param, rq);
1465         if (err)
1466                 return (err);
1467
1468         err = mlx5e_enable_rq(rq, param);
1469         if (err)
1470                 goto err_destroy_rq;
1471
1472         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1473         if (err)
1474                 goto err_disable_rq;
1475
1476         c->rq.enabled = 1;
1477
1478         return (0);
1479
1480 err_disable_rq:
1481         mlx5e_disable_rq(rq);
1482 err_destroy_rq:
1483         mlx5e_destroy_rq(rq);
1484
1485         return (err);
1486 }
1487
1488 static void
1489 mlx5e_close_rq(struct mlx5e_rq *rq)
1490 {
1491         mtx_lock(&rq->mtx);
1492         rq->enabled = 0;
1493         callout_stop(&rq->watchdog);
1494         mtx_unlock(&rq->mtx);
1495
1496         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1497 }
1498
1499 static void
1500 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1501 {
1502
1503         mlx5e_disable_rq(rq);
1504         mlx5e_close_cq(&rq->cq);
1505         cancel_work_sync(&rq->dim.work);
1506         mlx5e_destroy_rq(rq);
1507 }
1508
1509 void
1510 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1511 {
1512         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1513         int x;
1514
1515         for (x = 0; x != wq_sz; x++) {
1516                 if (unlikely(sq->mbuf[x].p_refcount != NULL)) {
1517                         atomic_add_int(sq->mbuf[x].p_refcount, -1);
1518                         sq->mbuf[x].p_refcount = NULL;
1519                 }
1520                 if (sq->mbuf[x].mbuf != NULL) {
1521                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1522                         m_freem(sq->mbuf[x].mbuf);
1523                 }
1524                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1525         }
1526         free(sq->mbuf, M_MLX5EN);
1527 }
1528
1529 int
1530 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1531 {
1532         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1533         int err;
1534         int x;
1535
1536         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1537
1538         /* Create DMA descriptor MAPs */
1539         for (x = 0; x != wq_sz; x++) {
1540                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1541                 if (err != 0) {
1542                         while (x--)
1543                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1544                         free(sq->mbuf, M_MLX5EN);
1545                         return (err);
1546                 }
1547         }
1548         return (0);
1549 }
1550
1551 static const char *mlx5e_sq_stats_desc[] = {
1552         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1553 };
1554
1555 void
1556 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1557 {
1558         sq->max_inline = sq->priv->params.tx_max_inline;
1559         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1560
1561         /*
1562          * Check if trust state is DSCP or if inline mode is NONE which
1563          * indicates CX-5 or newer hardware.
1564          */
1565         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1566             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1567                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1568                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1569                 else
1570                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1571         } else {
1572                 sq->min_insert_caps = 0;
1573         }
1574 }
1575
1576 static void
1577 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1578 {
1579         int i;
1580
1581         for (i = 0; i != priv->num_tc; i++) {
1582                 mtx_lock(&c->sq[i].lock);
1583                 mlx5e_update_sq_inline(&c->sq[i]);
1584                 mtx_unlock(&c->sq[i].lock);
1585         }
1586 }
1587
1588 void
1589 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1590 {
1591         int i;
1592
1593         /* check if channels are closed */
1594         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1595                 return;
1596
1597         for (i = 0; i < priv->params.num_channels; i++)
1598                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1599 }
1600
1601 static int
1602 mlx5e_create_sq(struct mlx5e_channel *c,
1603     int tc,
1604     struct mlx5e_sq_param *param,
1605     struct mlx5e_sq *sq)
1606 {
1607         struct mlx5e_priv *priv = c->priv;
1608         struct mlx5_core_dev *mdev = priv->mdev;
1609         char buffer[16];
1610         void *sqc = param->sqc;
1611         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1612         int err;
1613
1614         /* Create DMA descriptor TAG */
1615         if ((err = -bus_dma_tag_create(
1616             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1617             1,                          /* any alignment */
1618             0,                          /* no boundary */
1619             BUS_SPACE_MAXADDR,          /* lowaddr */
1620             BUS_SPACE_MAXADDR,          /* highaddr */
1621             NULL, NULL,                 /* filter, filterarg */
1622             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1623             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1624             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1625             0,                          /* flags */
1626             NULL, NULL,                 /* lockfunc, lockfuncarg */
1627             &sq->dma_tag)))
1628                 goto done;
1629
1630         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1631         if (err)
1632                 goto err_free_dma_tag;
1633
1634         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1635             &sq->wq_ctrl);
1636         if (err)
1637                 goto err_unmap_free_uar;
1638
1639         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1640         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1641
1642         err = mlx5e_alloc_sq_db(sq);
1643         if (err)
1644                 goto err_sq_wq_destroy;
1645
1646         sq->mkey_be = cpu_to_be32(priv->mr.key);
1647         sq->ifp = priv->ifp;
1648         sq->priv = priv;
1649         sq->tc = tc;
1650
1651         mlx5e_update_sq_inline(sq);
1652
1653         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1654         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1655             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1656             sq->stats.arg);
1657
1658         return (0);
1659
1660 err_sq_wq_destroy:
1661         mlx5_wq_destroy(&sq->wq_ctrl);
1662
1663 err_unmap_free_uar:
1664         mlx5_unmap_free_uar(mdev, &sq->uar);
1665
1666 err_free_dma_tag:
1667         bus_dma_tag_destroy(sq->dma_tag);
1668 done:
1669         return (err);
1670 }
1671
1672 static void
1673 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1674 {
1675         /* destroy all sysctl nodes */
1676         sysctl_ctx_free(&sq->stats.ctx);
1677
1678         mlx5e_free_sq_db(sq);
1679         mlx5_wq_destroy(&sq->wq_ctrl);
1680         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1681         bus_dma_tag_destroy(sq->dma_tag);
1682 }
1683
1684 int
1685 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1686     int tis_num)
1687 {
1688         void *in;
1689         void *sqc;
1690         void *wq;
1691         int inlen;
1692         int err;
1693
1694         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1695             sizeof(u64) * sq->wq_ctrl.buf.npages;
1696         in = mlx5_vzalloc(inlen);
1697         if (in == NULL)
1698                 return (-ENOMEM);
1699
1700         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1701         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1702
1703         memcpy(sqc, param->sqc, sizeof(param->sqc));
1704
1705         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1706         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1707         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1708         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1709         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1710
1711         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1712         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1713         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1714             PAGE_SHIFT);
1715         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1716
1717         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1718             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1719
1720         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1721
1722         kvfree(in);
1723
1724         return (err);
1725 }
1726
1727 int
1728 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1729 {
1730         void *in;
1731         void *sqc;
1732         int inlen;
1733         int err;
1734
1735         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1736         in = mlx5_vzalloc(inlen);
1737         if (in == NULL)
1738                 return (-ENOMEM);
1739
1740         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1741
1742         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1743         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1744         MLX5_SET(sqc, sqc, state, next_state);
1745
1746         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1747
1748         kvfree(in);
1749
1750         return (err);
1751 }
1752
1753 void
1754 mlx5e_disable_sq(struct mlx5e_sq *sq)
1755 {
1756
1757         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1758 }
1759
1760 static int
1761 mlx5e_open_sq(struct mlx5e_channel *c,
1762     int tc,
1763     struct mlx5e_sq_param *param,
1764     struct mlx5e_sq *sq)
1765 {
1766         int err;
1767
1768         sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1769
1770         /* ensure the TX completion event factor is not zero */
1771         if (sq->cev_factor == 0)
1772                 sq->cev_factor = 1;
1773
1774         err = mlx5e_create_sq(c, tc, param, sq);
1775         if (err)
1776                 return (err);
1777
1778         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1779         if (err)
1780                 goto err_destroy_sq;
1781
1782         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1783         if (err)
1784                 goto err_disable_sq;
1785
1786         WRITE_ONCE(sq->running, 1);
1787
1788         return (0);
1789
1790 err_disable_sq:
1791         mlx5e_disable_sq(sq);
1792 err_destroy_sq:
1793         mlx5e_destroy_sq(sq);
1794
1795         return (err);
1796 }
1797
1798 static void
1799 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1800 {
1801         /* fill up remainder with NOPs */
1802         while (sq->cev_counter != 0) {
1803                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1804                         if (can_sleep != 0) {
1805                                 mtx_unlock(&sq->lock);
1806                                 msleep(4);
1807                                 mtx_lock(&sq->lock);
1808                         } else {
1809                                 goto done;
1810                         }
1811                 }
1812                 /* send a single NOP */
1813                 mlx5e_send_nop(sq, 1);
1814                 atomic_thread_fence_rel();
1815         }
1816 done:
1817         /* Check if we need to write the doorbell */
1818         if (likely(sq->doorbell.d64 != 0)) {
1819                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1820                 sq->doorbell.d64 = 0;
1821         }
1822 }
1823
1824 void
1825 mlx5e_sq_cev_timeout(void *arg)
1826 {
1827         struct mlx5e_sq *sq = arg;
1828
1829         mtx_assert(&sq->lock, MA_OWNED);
1830
1831         /* check next state */
1832         switch (sq->cev_next_state) {
1833         case MLX5E_CEV_STATE_SEND_NOPS:
1834                 /* fill TX ring with NOPs, if any */
1835                 mlx5e_sq_send_nops_locked(sq, 0);
1836
1837                 /* check if completed */
1838                 if (sq->cev_counter == 0) {
1839                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1840                         return;
1841                 }
1842                 break;
1843         default:
1844                 /* send NOPs on next timeout */
1845                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1846                 break;
1847         }
1848
1849         /* restart timer */
1850         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1851 }
1852
1853 void
1854 mlx5e_drain_sq(struct mlx5e_sq *sq)
1855 {
1856         int error;
1857         struct mlx5_core_dev *mdev= sq->priv->mdev;
1858
1859         /*
1860          * Check if already stopped.
1861          *
1862          * NOTE: Serialization of this function is managed by the
1863          * caller ensuring the priv's state lock is locked or in case
1864          * of rate limit support, a single thread manages drain and
1865          * resume of SQs. The "running" variable can therefore safely
1866          * be read without any locks.
1867          */
1868         if (READ_ONCE(sq->running) == 0)
1869                 return;
1870
1871         /* don't put more packets into the SQ */
1872         WRITE_ONCE(sq->running, 0);
1873
1874         /* serialize access to DMA rings */
1875         mtx_lock(&sq->lock);
1876
1877         /* teardown event factor timer, if any */
1878         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1879         callout_stop(&sq->cev_callout);
1880
1881         /* send dummy NOPs in order to flush the transmit ring */
1882         mlx5e_sq_send_nops_locked(sq, 1);
1883         mtx_unlock(&sq->lock);
1884
1885         /* wait till SQ is empty or link is down */
1886         mtx_lock(&sq->lock);
1887         while (sq->cc != sq->pc &&
1888             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1889             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1890                 mtx_unlock(&sq->lock);
1891                 msleep(1);
1892                 sq->cq.mcq.comp(&sq->cq.mcq);
1893                 mtx_lock(&sq->lock);
1894         }
1895         mtx_unlock(&sq->lock);
1896
1897         /* error out remaining requests */
1898         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1899         if (error != 0) {
1900                 mlx5_en_err(sq->ifp,
1901                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1902         }
1903
1904         /* wait till SQ is empty */
1905         mtx_lock(&sq->lock);
1906         while (sq->cc != sq->pc &&
1907                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1908                 mtx_unlock(&sq->lock);
1909                 msleep(1);
1910                 sq->cq.mcq.comp(&sq->cq.mcq);
1911                 mtx_lock(&sq->lock);
1912         }
1913         mtx_unlock(&sq->lock);
1914 }
1915
1916 static void
1917 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1918 {
1919
1920         mlx5e_drain_sq(sq);
1921         mlx5e_disable_sq(sq);
1922         mlx5e_destroy_sq(sq);
1923 }
1924
1925 static int
1926 mlx5e_create_cq(struct mlx5e_priv *priv,
1927     struct mlx5e_cq_param *param,
1928     struct mlx5e_cq *cq,
1929     mlx5e_cq_comp_t *comp,
1930     int eq_ix)
1931 {
1932         struct mlx5_core_dev *mdev = priv->mdev;
1933         struct mlx5_core_cq *mcq = &cq->mcq;
1934         int eqn_not_used;
1935         int irqn;
1936         int err;
1937         u32 i;
1938
1939         param->wq.buf_numa_node = 0;
1940         param->wq.db_numa_node = 0;
1941
1942         err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1943         if (err)
1944                 return (err);
1945
1946         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1947             &cq->wq_ctrl);
1948         if (err)
1949                 return (err);
1950
1951         mcq->cqe_sz = 64;
1952         mcq->set_ci_db = cq->wq_ctrl.db.db;
1953         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1954         *mcq->set_ci_db = 0;
1955         *mcq->arm_db = 0;
1956         mcq->vector = eq_ix;
1957         mcq->comp = comp;
1958         mcq->event = mlx5e_cq_error_event;
1959         mcq->irqn = irqn;
1960         mcq->uar = &priv->cq_uar;
1961
1962         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1963                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1964
1965                 cqe->op_own = 0xf1;
1966         }
1967
1968         cq->priv = priv;
1969
1970         return (0);
1971 }
1972
1973 static void
1974 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1975 {
1976         mlx5_wq_destroy(&cq->wq_ctrl);
1977 }
1978
1979 static int
1980 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1981 {
1982         struct mlx5_core_cq *mcq = &cq->mcq;
1983         void *in;
1984         void *cqc;
1985         int inlen;
1986         int irqn_not_used;
1987         int eqn;
1988         int err;
1989
1990         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1991             sizeof(u64) * cq->wq_ctrl.buf.npages;
1992         in = mlx5_vzalloc(inlen);
1993         if (in == NULL)
1994                 return (-ENOMEM);
1995
1996         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1997
1998         memcpy(cqc, param->cqc, sizeof(param->cqc));
1999
2000         mlx5_fill_page_array(&cq->wq_ctrl.buf,
2001             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2002
2003         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2004
2005         MLX5_SET(cqc, cqc, c_eqn, eqn);
2006         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2007         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2008             PAGE_SHIFT);
2009         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2010
2011         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2012
2013         kvfree(in);
2014
2015         if (err)
2016                 return (err);
2017
2018         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2019
2020         return (0);
2021 }
2022
2023 static void
2024 mlx5e_disable_cq(struct mlx5e_cq *cq)
2025 {
2026
2027         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2028 }
2029
2030 int
2031 mlx5e_open_cq(struct mlx5e_priv *priv,
2032     struct mlx5e_cq_param *param,
2033     struct mlx5e_cq *cq,
2034     mlx5e_cq_comp_t *comp,
2035     int eq_ix)
2036 {
2037         int err;
2038
2039         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2040         if (err)
2041                 return (err);
2042
2043         err = mlx5e_enable_cq(cq, param, eq_ix);
2044         if (err)
2045                 goto err_destroy_cq;
2046
2047         return (0);
2048
2049 err_destroy_cq:
2050         mlx5e_destroy_cq(cq);
2051
2052         return (err);
2053 }
2054
2055 void
2056 mlx5e_close_cq(struct mlx5e_cq *cq)
2057 {
2058         mlx5e_disable_cq(cq);
2059         mlx5e_destroy_cq(cq);
2060 }
2061
2062 static int
2063 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2064     struct mlx5e_channel_param *cparam)
2065 {
2066         int err;
2067         int tc;
2068
2069         for (tc = 0; tc < c->priv->num_tc; tc++) {
2070                 /* open completion queue */
2071                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2072                     &mlx5e_tx_cq_comp, c->ix);
2073                 if (err)
2074                         goto err_close_tx_cqs;
2075         }
2076         return (0);
2077
2078 err_close_tx_cqs:
2079         for (tc--; tc >= 0; tc--)
2080                 mlx5e_close_cq(&c->sq[tc].cq);
2081
2082         return (err);
2083 }
2084
2085 static void
2086 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2087 {
2088         int tc;
2089
2090         for (tc = 0; tc < c->priv->num_tc; tc++)
2091                 mlx5e_close_cq(&c->sq[tc].cq);
2092 }
2093
2094 static int
2095 mlx5e_open_sqs(struct mlx5e_channel *c,
2096     struct mlx5e_channel_param *cparam)
2097 {
2098         int err;
2099         int tc;
2100
2101         for (tc = 0; tc < c->priv->num_tc; tc++) {
2102                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2103                 if (err)
2104                         goto err_close_sqs;
2105         }
2106
2107         return (0);
2108
2109 err_close_sqs:
2110         for (tc--; tc >= 0; tc--)
2111                 mlx5e_close_sq_wait(&c->sq[tc]);
2112
2113         return (err);
2114 }
2115
2116 static void
2117 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2118 {
2119         int tc;
2120
2121         for (tc = 0; tc < c->priv->num_tc; tc++)
2122                 mlx5e_close_sq_wait(&c->sq[tc]);
2123 }
2124
2125 static void
2126 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2127 {
2128         int tc;
2129
2130         /* setup priv and channel number */
2131         c->priv = priv;
2132         c->ix = ix;
2133
2134         /* setup send tag */
2135         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2136         m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2137
2138         init_completion(&c->completion);
2139
2140         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2141
2142         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2143
2144         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2145                 struct mlx5e_sq *sq = c->sq + tc;
2146
2147                 mtx_init(&sq->lock, "mlx5tx",
2148                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2149                 mtx_init(&sq->comp_lock, "mlx5comp",
2150                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2151
2152                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2153         }
2154 }
2155
2156 static void
2157 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2158 {
2159
2160         m_snd_tag_rele(&c->tag.m_snd_tag);
2161         wait_for_completion(&c->completion);
2162 }
2163
2164 static void
2165 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2166 {
2167         uint32_t x;
2168
2169         for (x = 0; x != channels; x++)
2170                 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2171 }
2172
2173 static void
2174 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2175 {
2176         int tc;
2177
2178         callout_drain(&c->rq.watchdog);
2179
2180         mtx_destroy(&c->rq.mtx);
2181
2182         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2183                 callout_drain(&c->sq[tc].cev_callout);
2184                 mtx_destroy(&c->sq[tc].lock);
2185                 mtx_destroy(&c->sq[tc].comp_lock);
2186         }
2187 }
2188
2189 static int
2190 mlx5e_open_channel(struct mlx5e_priv *priv,
2191     struct mlx5e_channel_param *cparam,
2192     struct mlx5e_channel *c)
2193 {
2194         struct epoch_tracker et;
2195         int i, err;
2196
2197         /* zero non-persistant data */
2198         MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2199         for (i = 0; i != priv->num_tc; i++)
2200                 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2201
2202         /* open transmit completion queue */
2203         err = mlx5e_open_tx_cqs(c, cparam);
2204         if (err)
2205                 goto err_free;
2206
2207         /* open receive completion queue */
2208         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2209             &mlx5e_rx_cq_comp, c->ix);
2210         if (err)
2211                 goto err_close_tx_cqs;
2212
2213         err = mlx5e_open_sqs(c, cparam);
2214         if (err)
2215                 goto err_close_rx_cq;
2216
2217         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2218         if (err)
2219                 goto err_close_sqs;
2220
2221         /* poll receive queue initially */
2222         NET_EPOCH_ENTER(et);
2223         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2224         NET_EPOCH_EXIT(et);
2225
2226         return (0);
2227
2228 err_close_sqs:
2229         mlx5e_close_sqs_wait(c);
2230
2231 err_close_rx_cq:
2232         mlx5e_close_cq(&c->rq.cq);
2233
2234 err_close_tx_cqs:
2235         mlx5e_close_tx_cqs(c);
2236
2237 err_free:
2238         return (err);
2239 }
2240
2241 static void
2242 mlx5e_close_channel(struct mlx5e_channel *c)
2243 {
2244         mlx5e_close_rq(&c->rq);
2245 }
2246
2247 static void
2248 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2249 {
2250         mlx5e_close_rq_wait(&c->rq);
2251         mlx5e_close_sqs_wait(c);
2252         mlx5e_close_tx_cqs(c);
2253 }
2254
2255 static int
2256 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2257 {
2258         u32 r, n;
2259
2260         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2261             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2262         if (r > MJUM16BYTES)
2263                 return (-ENOMEM);
2264
2265         if (r > MJUM9BYTES)
2266                 r = MJUM16BYTES;
2267         else if (r > MJUMPAGESIZE)
2268                 r = MJUM9BYTES;
2269         else if (r > MCLBYTES)
2270                 r = MJUMPAGESIZE;
2271         else
2272                 r = MCLBYTES;
2273
2274         /*
2275          * n + 1 must be a power of two, because stride size must be.
2276          * Stride size is 16 * (n + 1), as the first segment is
2277          * control.
2278          */
2279         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2280                 ;
2281
2282         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2283                 return (-ENOMEM);
2284
2285         *wqe_sz = r;
2286         *nsegs = n;
2287         return (0);
2288 }
2289
2290 static void
2291 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2292     struct mlx5e_rq_param *param)
2293 {
2294         void *rqc = param->rqc;
2295         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2296         u32 wqe_sz, nsegs;
2297
2298         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2299         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2300         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2301         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2302             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2303         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2304         MLX5_SET(wq, wq, pd, priv->pdn);
2305
2306         param->wq.buf_numa_node = 0;
2307         param->wq.db_numa_node = 0;
2308         param->wq.linear = 1;
2309 }
2310
2311 static void
2312 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2313     struct mlx5e_sq_param *param)
2314 {
2315         void *sqc = param->sqc;
2316         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2317
2318         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2319         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2320         MLX5_SET(wq, wq, pd, priv->pdn);
2321
2322         param->wq.buf_numa_node = 0;
2323         param->wq.db_numa_node = 0;
2324         param->wq.linear = 1;
2325 }
2326
2327 static void
2328 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2329     struct mlx5e_cq_param *param)
2330 {
2331         void *cqc = param->cqc;
2332
2333         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2334 }
2335
2336 static void
2337 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2338 {
2339
2340         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2341
2342         /* apply LRO restrictions */
2343         if (priv->params.hw_lro_en &&
2344             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2345                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2346         }
2347 }
2348
2349 static void
2350 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2351     struct mlx5e_cq_param *param)
2352 {
2353         struct net_dim_cq_moder curr;
2354         void *cqc = param->cqc;
2355
2356         /*
2357          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2358          * format is more beneficial for FreeBSD use case.
2359          *
2360          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2361          * in mlx5e_decompress_cqe.
2362          */
2363         if (priv->params.cqe_zipping_en) {
2364                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2365                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2366         }
2367
2368         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2369
2370         switch (priv->params.rx_cq_moderation_mode) {
2371         case 0:
2372                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2373                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2374                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2375                 break;
2376         case 1:
2377                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2378                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2379                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2380                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2381                 else
2382                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2383                 break;
2384         case 2:
2385                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2386                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2387                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2388                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2389                 break;
2390         case 3:
2391                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2392                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2393                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2394                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2395                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2396                 else
2397                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2398                 break;
2399         default:
2400                 break;
2401         }
2402
2403         mlx5e_dim_build_cq_param(priv, param);
2404
2405         mlx5e_build_common_cq_param(priv, param);
2406 }
2407
2408 static void
2409 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2410     struct mlx5e_cq_param *param)
2411 {
2412         void *cqc = param->cqc;
2413
2414         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2415         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2416         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2417
2418         switch (priv->params.tx_cq_moderation_mode) {
2419         case 0:
2420                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2421                 break;
2422         default:
2423                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2424                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2425                 else
2426                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2427                 break;
2428         }
2429
2430         mlx5e_build_common_cq_param(priv, param);
2431 }
2432
2433 static void
2434 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2435     struct mlx5e_channel_param *cparam)
2436 {
2437         memset(cparam, 0, sizeof(*cparam));
2438
2439         mlx5e_build_rq_param(priv, &cparam->rq);
2440         mlx5e_build_sq_param(priv, &cparam->sq);
2441         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2442         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2443 }
2444
2445 static int
2446 mlx5e_open_channels(struct mlx5e_priv *priv)
2447 {
2448         struct mlx5e_channel_param *cparam;
2449         int err;
2450         int i;
2451         int j;
2452
2453         cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2454
2455         mlx5e_build_channel_param(priv, cparam);
2456         for (i = 0; i < priv->params.num_channels; i++) {
2457                 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2458                 if (err)
2459                         goto err_close_channels;
2460         }
2461
2462         for (j = 0; j < priv->params.num_channels; j++) {
2463                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2464                 if (err)
2465                         goto err_close_channels;
2466         }
2467         free(cparam, M_MLX5EN);
2468         return (0);
2469
2470 err_close_channels:
2471         while (i--) {
2472                 mlx5e_close_channel(&priv->channel[i]);
2473                 mlx5e_close_channel_wait(&priv->channel[i]);
2474         }
2475         free(cparam, M_MLX5EN);
2476         return (err);
2477 }
2478
2479 static void
2480 mlx5e_close_channels(struct mlx5e_priv *priv)
2481 {
2482         int i;
2483
2484         for (i = 0; i < priv->params.num_channels; i++)
2485                 mlx5e_close_channel(&priv->channel[i]);
2486         for (i = 0; i < priv->params.num_channels; i++)
2487                 mlx5e_close_channel_wait(&priv->channel[i]);
2488 }
2489
2490 static int
2491 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2492 {
2493
2494         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2495                 uint8_t cq_mode;
2496
2497                 switch (priv->params.tx_cq_moderation_mode) {
2498                 case 0:
2499                 case 2:
2500                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2501                         break;
2502                 default:
2503                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2504                         break;
2505                 }
2506
2507                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2508                     priv->params.tx_cq_moderation_usec,
2509                     priv->params.tx_cq_moderation_pkts,
2510                     cq_mode));
2511         }
2512
2513         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2514             priv->params.tx_cq_moderation_usec,
2515             priv->params.tx_cq_moderation_pkts));
2516 }
2517
2518 static int
2519 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2520 {
2521
2522         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2523                 uint8_t cq_mode;
2524                 uint8_t dim_mode;
2525                 int retval;
2526
2527                 switch (priv->params.rx_cq_moderation_mode) {
2528                 case 0:
2529                 case 2:
2530                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2531                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2532                         break;
2533                 default:
2534                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2535                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2536                         break;
2537                 }
2538
2539                 /* tear down dynamic interrupt moderation */
2540                 mtx_lock(&rq->mtx);
2541                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2542                 mtx_unlock(&rq->mtx);
2543
2544                 /* wait for dynamic interrupt moderation work task, if any */
2545                 cancel_work_sync(&rq->dim.work);
2546
2547                 if (priv->params.rx_cq_moderation_mode >= 2) {
2548                         struct net_dim_cq_moder curr;
2549
2550                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2551
2552                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2553                             curr.usec, curr.pkts, cq_mode);
2554
2555                         /* set dynamic interrupt moderation mode and zero defaults */
2556                         mtx_lock(&rq->mtx);
2557                         rq->dim.mode = dim_mode;
2558                         rq->dim.state = 0;
2559                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2560                         mtx_unlock(&rq->mtx);
2561                 } else {
2562                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2563                             priv->params.rx_cq_moderation_usec,
2564                             priv->params.rx_cq_moderation_pkts,
2565                             cq_mode);
2566                 }
2567                 return (retval);
2568         }
2569
2570         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2571             priv->params.rx_cq_moderation_usec,
2572             priv->params.rx_cq_moderation_pkts));
2573 }
2574
2575 static int
2576 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2577 {
2578         int err;
2579         int i;
2580
2581         err = mlx5e_refresh_rq_params(priv, &c->rq);
2582         if (err)
2583                 goto done;
2584
2585         for (i = 0; i != priv->num_tc; i++) {
2586                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2587                 if (err)
2588                         goto done;
2589         }
2590 done:
2591         return (err);
2592 }
2593
2594 int
2595 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2596 {
2597         int i;
2598
2599         /* check if channels are closed */
2600         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2601                 return (EINVAL);
2602
2603         for (i = 0; i < priv->params.num_channels; i++) {
2604                 int err;
2605
2606                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2607                 if (err)
2608                         return (err);
2609         }
2610         return (0);
2611 }
2612
2613 static int
2614 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2615 {
2616         struct mlx5_core_dev *mdev = priv->mdev;
2617         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2618         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2619
2620         memset(in, 0, sizeof(in));
2621
2622         MLX5_SET(tisc, tisc, prio, tc);
2623         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2624
2625         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2626 }
2627
2628 static void
2629 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2630 {
2631         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2632 }
2633
2634 static int
2635 mlx5e_open_tises(struct mlx5e_priv *priv)
2636 {
2637         int num_tc = priv->num_tc;
2638         int err;
2639         int tc;
2640
2641         for (tc = 0; tc < num_tc; tc++) {
2642                 err = mlx5e_open_tis(priv, tc);
2643                 if (err)
2644                         goto err_close_tises;
2645         }
2646
2647         return (0);
2648
2649 err_close_tises:
2650         for (tc--; tc >= 0; tc--)
2651                 mlx5e_close_tis(priv, tc);
2652
2653         return (err);
2654 }
2655
2656 static void
2657 mlx5e_close_tises(struct mlx5e_priv *priv)
2658 {
2659         int num_tc = priv->num_tc;
2660         int tc;
2661
2662         for (tc = 0; tc < num_tc; tc++)
2663                 mlx5e_close_tis(priv, tc);
2664 }
2665
2666 static int
2667 mlx5e_open_rqt(struct mlx5e_priv *priv)
2668 {
2669         struct mlx5_core_dev *mdev = priv->mdev;
2670         u32 *in;
2671         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2672         void *rqtc;
2673         int inlen;
2674         int err;
2675         int sz;
2676         int i;
2677
2678         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2679
2680         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2681         in = mlx5_vzalloc(inlen);
2682         if (in == NULL)
2683                 return (-ENOMEM);
2684         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2685
2686         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2687         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2688
2689         for (i = 0; i < sz; i++) {
2690                 int ix = i;
2691 #ifdef RSS
2692                 ix = rss_get_indirection_to_bucket(ix);
2693 #endif
2694                 /* ensure we don't overflow */
2695                 ix %= priv->params.num_channels;
2696
2697                 /* apply receive side scaling stride, if any */
2698                 ix -= ix % (int)priv->params.channels_rsss;
2699
2700                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2701         }
2702
2703         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2704
2705         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2706         if (!err)
2707                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2708
2709         kvfree(in);
2710
2711         return (err);
2712 }
2713
2714 static void
2715 mlx5e_close_rqt(struct mlx5e_priv *priv)
2716 {
2717         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2718         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2719
2720         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2721         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2722
2723         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2724 }
2725
2726 static void
2727 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2728 {
2729         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2730         __be32 *hkey;
2731
2732         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2733
2734 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2735
2736 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2737                           MLX5_HASH_FIELD_SEL_DST_IP)
2738
2739 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2740                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2741                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2742                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2743
2744 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2745                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2746                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2747
2748         if (priv->params.hw_lro_en) {
2749                 MLX5_SET(tirc, tirc, lro_enable_mask,
2750                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2751                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2752                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2753                     (priv->params.lro_wqe_sz -
2754                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2755                 /* TODO: add the option to choose timer value dynamically */
2756                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2757                     MLX5_CAP_ETH(priv->mdev,
2758                     lro_timer_supported_periods[2]));
2759         }
2760
2761         /* setup parameters for hashing TIR type, if any */
2762         switch (tt) {
2763         case MLX5E_TT_ANY:
2764                 MLX5_SET(tirc, tirc, disp_type,
2765                     MLX5_TIRC_DISP_TYPE_DIRECT);
2766                 MLX5_SET(tirc, tirc, inline_rqn,
2767                     priv->channel[0].rq.rqn);
2768                 break;
2769         default:
2770                 MLX5_SET(tirc, tirc, disp_type,
2771                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2772                 MLX5_SET(tirc, tirc, indirect_table,
2773                     priv->rqtn);
2774                 MLX5_SET(tirc, tirc, rx_hash_fn,
2775                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2776                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2777 #ifdef RSS
2778                 /*
2779                  * The FreeBSD RSS implementation does currently not
2780                  * support symmetric Toeplitz hashes:
2781                  */
2782                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2783                 rss_getkey((uint8_t *)hkey);
2784 #else
2785                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2786                 hkey[0] = cpu_to_be32(0xD181C62C);
2787                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2788                 hkey[2] = cpu_to_be32(0x1983A2FC);
2789                 hkey[3] = cpu_to_be32(0x943E1ADB);
2790                 hkey[4] = cpu_to_be32(0xD9389E6B);
2791                 hkey[5] = cpu_to_be32(0xD1039C2C);
2792                 hkey[6] = cpu_to_be32(0xA74499AD);
2793                 hkey[7] = cpu_to_be32(0x593D56D9);
2794                 hkey[8] = cpu_to_be32(0xF3253C06);
2795                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2796 #endif
2797                 break;
2798         }
2799
2800         switch (tt) {
2801         case MLX5E_TT_IPV4_TCP:
2802                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2803                     MLX5_L3_PROT_TYPE_IPV4);
2804                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2805                     MLX5_L4_PROT_TYPE_TCP);
2806 #ifdef RSS
2807                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2808                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2809                             MLX5_HASH_IP);
2810                 } else
2811 #endif
2812                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2813                     MLX5_HASH_ALL);
2814                 break;
2815
2816         case MLX5E_TT_IPV6_TCP:
2817                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2818                     MLX5_L3_PROT_TYPE_IPV6);
2819                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2820                     MLX5_L4_PROT_TYPE_TCP);
2821 #ifdef RSS
2822                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2823                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2824                             MLX5_HASH_IP);
2825                 } else
2826 #endif
2827                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2828                     MLX5_HASH_ALL);
2829                 break;
2830
2831         case MLX5E_TT_IPV4_UDP:
2832                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2833                     MLX5_L3_PROT_TYPE_IPV4);
2834                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2835                     MLX5_L4_PROT_TYPE_UDP);
2836 #ifdef RSS
2837                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2838                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2839                             MLX5_HASH_IP);
2840                 } else
2841 #endif
2842                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2843                     MLX5_HASH_ALL);
2844                 break;
2845
2846         case MLX5E_TT_IPV6_UDP:
2847                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2848                     MLX5_L3_PROT_TYPE_IPV6);
2849                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2850                     MLX5_L4_PROT_TYPE_UDP);
2851 #ifdef RSS
2852                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2853                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2854                             MLX5_HASH_IP);
2855                 } else
2856 #endif
2857                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2858                     MLX5_HASH_ALL);
2859                 break;
2860
2861         case MLX5E_TT_IPV4_IPSEC_AH:
2862                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2863                     MLX5_L3_PROT_TYPE_IPV4);
2864                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2865                     MLX5_HASH_IP_IPSEC_SPI);
2866                 break;
2867
2868         case MLX5E_TT_IPV6_IPSEC_AH:
2869                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2870                     MLX5_L3_PROT_TYPE_IPV6);
2871                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2872                     MLX5_HASH_IP_IPSEC_SPI);
2873                 break;
2874
2875         case MLX5E_TT_IPV4_IPSEC_ESP:
2876                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2877                     MLX5_L3_PROT_TYPE_IPV4);
2878                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2879                     MLX5_HASH_IP_IPSEC_SPI);
2880                 break;
2881
2882         case MLX5E_TT_IPV6_IPSEC_ESP:
2883                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2884                     MLX5_L3_PROT_TYPE_IPV6);
2885                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2886                     MLX5_HASH_IP_IPSEC_SPI);
2887                 break;
2888
2889         case MLX5E_TT_IPV4:
2890                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2891                     MLX5_L3_PROT_TYPE_IPV4);
2892                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2893                     MLX5_HASH_IP);
2894                 break;
2895
2896         case MLX5E_TT_IPV6:
2897                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2898                     MLX5_L3_PROT_TYPE_IPV6);
2899                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2900                     MLX5_HASH_IP);
2901                 break;
2902
2903         default:
2904                 break;
2905         }
2906 }
2907
2908 static int
2909 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2910 {
2911         struct mlx5_core_dev *mdev = priv->mdev;
2912         u32 *in;
2913         void *tirc;
2914         int inlen;
2915         int err;
2916
2917         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2918         in = mlx5_vzalloc(inlen);
2919         if (in == NULL)
2920                 return (-ENOMEM);
2921         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2922
2923         mlx5e_build_tir_ctx(priv, tirc, tt);
2924
2925         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2926
2927         kvfree(in);
2928
2929         return (err);
2930 }
2931
2932 static void
2933 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2934 {
2935         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2936 }
2937
2938 static int
2939 mlx5e_open_tirs(struct mlx5e_priv *priv)
2940 {
2941         int err;
2942         int i;
2943
2944         for (i = 0; i < MLX5E_NUM_TT; i++) {
2945                 err = mlx5e_open_tir(priv, i);
2946                 if (err)
2947                         goto err_close_tirs;
2948         }
2949
2950         return (0);
2951
2952 err_close_tirs:
2953         for (i--; i >= 0; i--)
2954                 mlx5e_close_tir(priv, i);
2955
2956         return (err);
2957 }
2958
2959 static void
2960 mlx5e_close_tirs(struct mlx5e_priv *priv)
2961 {
2962         int i;
2963
2964         for (i = 0; i < MLX5E_NUM_TT; i++)
2965                 mlx5e_close_tir(priv, i);
2966 }
2967
2968 /*
2969  * SW MTU does not include headers,
2970  * HW MTU includes all headers and checksums.
2971  */
2972 static int
2973 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2974 {
2975         struct mlx5e_priv *priv = ifp->if_softc;
2976         struct mlx5_core_dev *mdev = priv->mdev;
2977         int hw_mtu;
2978         int err;
2979
2980         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2981
2982         err = mlx5_set_port_mtu(mdev, hw_mtu);
2983         if (err) {
2984                 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2985                     sw_mtu, err);
2986                 return (err);
2987         }
2988
2989         /* Update vport context MTU */
2990         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2991         if (err) {
2992                 mlx5_en_err(ifp,
2993                     "Failed updating vport context with MTU size, err=%d\n",
2994                     err);
2995         }
2996
2997         ifp->if_mtu = sw_mtu;
2998
2999         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3000         if (err || !hw_mtu) {
3001                 /* fallback to port oper mtu */
3002                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3003         }
3004         if (err) {
3005                 mlx5_en_err(ifp,
3006                     "Query port MTU, after setting new MTU value, failed\n");
3007                 return (err);
3008         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3009                 err = -E2BIG,
3010                 mlx5_en_err(ifp,
3011                     "Port MTU %d is smaller than ifp mtu %d\n",
3012                     hw_mtu, sw_mtu);
3013         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3014                 err = -EINVAL;
3015                 mlx5_en_err(ifp,
3016                     "Port MTU %d is bigger than ifp mtu %d\n",
3017                     hw_mtu, sw_mtu);
3018         }
3019         priv->params_ethtool.hw_mtu = hw_mtu;
3020
3021         /* compute MSB */
3022         while (hw_mtu & (hw_mtu - 1))
3023                 hw_mtu &= (hw_mtu - 1);
3024         priv->params_ethtool.hw_mtu_msb = hw_mtu;
3025
3026         return (err);
3027 }
3028
3029 int
3030 mlx5e_open_locked(struct ifnet *ifp)
3031 {
3032         struct mlx5e_priv *priv = ifp->if_softc;
3033         int err;
3034         u16 set_id;
3035
3036         /* check if already opened */
3037         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3038                 return (0);
3039
3040 #ifdef RSS
3041         if (rss_getnumbuckets() > priv->params.num_channels) {
3042                 mlx5_en_info(ifp,
3043                     "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3044                     rss_getnumbuckets(), priv->params.num_channels);
3045         }
3046 #endif
3047         err = mlx5e_open_tises(priv);
3048         if (err) {
3049                 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3050                 return (err);
3051         }
3052         err = mlx5_vport_alloc_q_counter(priv->mdev,
3053             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3054         if (err) {
3055                 mlx5_en_err(priv->ifp,
3056                     "mlx5_vport_alloc_q_counter failed: %d\n", err);
3057                 goto err_close_tises;
3058         }
3059         /* store counter set ID */
3060         priv->counter_set_id = set_id;
3061
3062         err = mlx5e_open_channels(priv);
3063         if (err) {
3064                 mlx5_en_err(ifp,
3065                     "mlx5e_open_channels failed, %d\n", err);
3066                 goto err_dalloc_q_counter;
3067         }
3068         err = mlx5e_open_rqt(priv);
3069         if (err) {
3070                 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3071                 goto err_close_channels;
3072         }
3073         err = mlx5e_open_tirs(priv);
3074         if (err) {
3075                 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3076                 goto err_close_rqls;
3077         }
3078         err = mlx5e_open_flow_table(priv);
3079         if (err) {
3080                 mlx5_en_err(ifp,
3081                     "mlx5e_open_flow_table failed, %d\n", err);
3082                 goto err_close_tirs;
3083         }
3084         err = mlx5e_add_all_vlan_rules(priv);
3085         if (err) {
3086                 mlx5_en_err(ifp,
3087                     "mlx5e_add_all_vlan_rules failed, %d\n", err);
3088                 goto err_close_flow_table;
3089         }
3090         set_bit(MLX5E_STATE_OPENED, &priv->state);
3091
3092         mlx5e_update_carrier(priv);
3093         mlx5e_set_rx_mode_core(priv);
3094
3095         return (0);
3096
3097 err_close_flow_table:
3098         mlx5e_close_flow_table(priv);
3099
3100 err_close_tirs:
3101         mlx5e_close_tirs(priv);
3102
3103 err_close_rqls:
3104         mlx5e_close_rqt(priv);
3105
3106 err_close_channels:
3107         mlx5e_close_channels(priv);
3108
3109 err_dalloc_q_counter:
3110         mlx5_vport_dealloc_q_counter(priv->mdev,
3111             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3112
3113 err_close_tises:
3114         mlx5e_close_tises(priv);
3115
3116         return (err);
3117 }
3118
3119 static void
3120 mlx5e_open(void *arg)
3121 {
3122         struct mlx5e_priv *priv = arg;
3123
3124         PRIV_LOCK(priv);
3125         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3126                 mlx5_en_err(priv->ifp,
3127                     "Setting port status to up failed\n");
3128
3129         mlx5e_open_locked(priv->ifp);
3130         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3131         PRIV_UNLOCK(priv);
3132 }
3133
3134 int
3135 mlx5e_close_locked(struct ifnet *ifp)
3136 {
3137         struct mlx5e_priv *priv = ifp->if_softc;
3138
3139         /* check if already closed */
3140         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3141                 return (0);
3142
3143         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3144
3145         mlx5e_set_rx_mode_core(priv);
3146         mlx5e_del_all_vlan_rules(priv);
3147         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3148         mlx5e_close_flow_table(priv);
3149         mlx5e_close_tirs(priv);
3150         mlx5e_close_rqt(priv);
3151         mlx5e_close_channels(priv);
3152         mlx5_vport_dealloc_q_counter(priv->mdev,
3153             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3154         mlx5e_close_tises(priv);
3155
3156         return (0);
3157 }
3158
3159 #if (__FreeBSD_version >= 1100000)
3160 static uint64_t
3161 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3162 {
3163         struct mlx5e_priv *priv = ifp->if_softc;
3164         u64 retval;
3165
3166         /* PRIV_LOCK(priv); XXX not allowed */
3167         switch (cnt) {
3168         case IFCOUNTER_IPACKETS:
3169                 retval = priv->stats.vport.rx_packets;
3170                 break;
3171         case IFCOUNTER_IERRORS:
3172                 retval = priv->stats.pport.in_range_len_errors +
3173                     priv->stats.pport.out_of_range_len +
3174                     priv->stats.pport.too_long_errors +
3175                     priv->stats.pport.check_seq_err +
3176                     priv->stats.pport.alignment_err;
3177                 break;
3178         case IFCOUNTER_IQDROPS:
3179                 retval = priv->stats.vport.rx_out_of_buffer;
3180                 break;
3181         case IFCOUNTER_OPACKETS:
3182                 retval = priv->stats.vport.tx_packets;
3183                 break;
3184         case IFCOUNTER_OERRORS:
3185                 retval = priv->stats.port_stats_debug.out_discards;
3186                 break;
3187         case IFCOUNTER_IBYTES:
3188                 retval = priv->stats.vport.rx_bytes;
3189                 break;
3190         case IFCOUNTER_OBYTES:
3191                 retval = priv->stats.vport.tx_bytes;
3192                 break;
3193         case IFCOUNTER_IMCASTS:
3194                 retval = priv->stats.vport.rx_multicast_packets;
3195                 break;
3196         case IFCOUNTER_OMCASTS:
3197                 retval = priv->stats.vport.tx_multicast_packets;
3198                 break;
3199         case IFCOUNTER_OQDROPS:
3200                 retval = priv->stats.vport.tx_queue_dropped;
3201                 break;
3202         case IFCOUNTER_COLLISIONS:
3203                 retval = priv->stats.pport.collisions;
3204                 break;
3205         default:
3206                 retval = if_get_counter_default(ifp, cnt);
3207                 break;
3208         }
3209         /* PRIV_UNLOCK(priv); XXX not allowed */
3210         return (retval);
3211 }
3212 #endif
3213
3214 static void
3215 mlx5e_set_rx_mode(struct ifnet *ifp)
3216 {
3217         struct mlx5e_priv *priv = ifp->if_softc;
3218
3219         queue_work(priv->wq, &priv->set_rx_mode_work);
3220 }
3221
3222 static int
3223 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3224 {
3225         struct mlx5e_priv *priv;
3226         struct ifreq *ifr;
3227         struct ifi2creq i2c;
3228         int error = 0;
3229         int mask = 0;
3230         int size_read = 0;
3231         int module_status;
3232         int module_num;
3233         int max_mtu;
3234         uint8_t read_addr;
3235
3236         priv = ifp->if_softc;
3237
3238         /* check if detaching */
3239         if (priv == NULL || priv->gone != 0)
3240                 return (ENXIO);
3241
3242         switch (command) {
3243         case SIOCSIFMTU:
3244                 ifr = (struct ifreq *)data;
3245
3246                 PRIV_LOCK(priv);
3247                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3248
3249                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3250                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3251                         int was_opened;
3252
3253                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3254                         if (was_opened)
3255                                 mlx5e_close_locked(ifp);
3256
3257                         /* set new MTU */
3258                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3259
3260                         if (was_opened)
3261                                 mlx5e_open_locked(ifp);
3262                 } else {
3263                         error = EINVAL;
3264                         mlx5_en_err(ifp,
3265                             "Invalid MTU value. Min val: %d, Max val: %d\n",
3266                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3267                 }
3268                 PRIV_UNLOCK(priv);
3269                 break;
3270         case SIOCSIFFLAGS:
3271                 if ((ifp->if_flags & IFF_UP) &&
3272                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3273                         mlx5e_set_rx_mode(ifp);
3274                         break;
3275                 }
3276                 PRIV_LOCK(priv);
3277                 if (ifp->if_flags & IFF_UP) {
3278                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3279                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3280                                         mlx5e_open_locked(ifp);
3281                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3282                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3283                         }
3284                 } else {
3285                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3286                                 mlx5_set_port_status(priv->mdev,
3287                                     MLX5_PORT_DOWN);
3288                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3289                                         mlx5e_close_locked(ifp);
3290                                 mlx5e_update_carrier(priv);
3291                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3292                         }
3293                 }
3294                 PRIV_UNLOCK(priv);
3295                 break;
3296         case SIOCADDMULTI:
3297         case SIOCDELMULTI:
3298                 mlx5e_set_rx_mode(ifp);
3299                 break;
3300         case SIOCSIFMEDIA:
3301         case SIOCGIFMEDIA:
3302         case SIOCGIFXMEDIA:
3303                 ifr = (struct ifreq *)data;
3304                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3305                 break;
3306         case SIOCSIFCAP:
3307                 ifr = (struct ifreq *)data;
3308                 PRIV_LOCK(priv);
3309                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3310
3311                 if (mask & IFCAP_TXCSUM) {
3312                         ifp->if_capenable ^= IFCAP_TXCSUM;
3313                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3314
3315                         if (IFCAP_TSO4 & ifp->if_capenable &&
3316                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3317                                 ifp->if_capenable &= ~IFCAP_TSO4;
3318                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3319                                 mlx5_en_err(ifp,
3320                                     "tso4 disabled due to -txcsum.\n");
3321                         }
3322                 }
3323                 if (mask & IFCAP_TXCSUM_IPV6) {
3324                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3325                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3326
3327                         if (IFCAP_TSO6 & ifp->if_capenable &&
3328                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3329                                 ifp->if_capenable &= ~IFCAP_TSO6;
3330                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3331                                 mlx5_en_err(ifp,
3332                                     "tso6 disabled due to -txcsum6.\n");
3333                         }
3334                 }
3335                 if (mask & IFCAP_NOMAP)
3336                         ifp->if_capenable ^= IFCAP_NOMAP;
3337                 if (mask & IFCAP_TXTLS4)
3338                         ifp->if_capenable ^= IFCAP_TXTLS4;
3339                 if (mask & IFCAP_TXTLS6)
3340                         ifp->if_capenable ^= IFCAP_TXTLS6;
3341                 if (mask & IFCAP_RXCSUM)
3342                         ifp->if_capenable ^= IFCAP_RXCSUM;
3343                 if (mask & IFCAP_RXCSUM_IPV6)
3344                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3345                 if (mask & IFCAP_TSO4) {
3346                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3347                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3348                                 mlx5_en_err(ifp, "enable txcsum first.\n");
3349                                 error = EAGAIN;
3350                                 goto out;
3351                         }
3352                         ifp->if_capenable ^= IFCAP_TSO4;
3353                         ifp->if_hwassist ^= CSUM_IP_TSO;
3354                 }
3355                 if (mask & IFCAP_TSO6) {
3356                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3357                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3358                                 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3359                                 error = EAGAIN;
3360                                 goto out;
3361                         }
3362                         ifp->if_capenable ^= IFCAP_TSO6;
3363                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3364                 }
3365                 if (mask & IFCAP_VLAN_HWFILTER) {
3366                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3367                                 mlx5e_disable_vlan_filter(priv);
3368                         else
3369                                 mlx5e_enable_vlan_filter(priv);
3370
3371                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3372                 }
3373                 if (mask & IFCAP_VLAN_HWTAGGING)
3374                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3375                 if (mask & IFCAP_WOL_MAGIC)
3376                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3377
3378                 VLAN_CAPABILITIES(ifp);
3379                 /* turn off LRO means also turn of HW LRO - if it's on */
3380                 if (mask & IFCAP_LRO) {
3381                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3382                         bool need_restart = false;
3383
3384                         ifp->if_capenable ^= IFCAP_LRO;
3385
3386                         /* figure out if updating HW LRO is needed */
3387                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3388                                 if (priv->params.hw_lro_en) {
3389                                         priv->params.hw_lro_en = false;
3390                                         need_restart = true;
3391                                 }
3392                         } else {
3393                                 if (priv->params.hw_lro_en == false &&
3394                                     priv->params_ethtool.hw_lro != 0) {
3395                                         priv->params.hw_lro_en = true;
3396                                         need_restart = true;
3397                                 }
3398                         }
3399                         if (was_opened && need_restart) {
3400                                 mlx5e_close_locked(ifp);
3401                                 mlx5e_open_locked(ifp);
3402                         }
3403                 }
3404                 if (mask & IFCAP_HWRXTSTMP) {
3405                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3406                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3407                                 if (priv->clbr_done == 0)
3408                                         mlx5e_reset_calibration_callout(priv);
3409                         } else {
3410                                 callout_drain(&priv->tstmp_clbr);
3411                                 priv->clbr_done = 0;
3412                         }
3413                 }
3414 out:
3415                 PRIV_UNLOCK(priv);
3416                 break;
3417
3418         case SIOCGI2C:
3419                 ifr = (struct ifreq *)data;
3420
3421                 /*
3422                  * Copy from the user-space address ifr_data to the
3423                  * kernel-space address i2c
3424                  */
3425                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3426                 if (error)
3427                         break;
3428
3429                 if (i2c.len > sizeof(i2c.data)) {
3430                         error = EINVAL;
3431                         break;
3432                 }
3433
3434                 PRIV_LOCK(priv);
3435                 /* Get module_num which is required for the query_eeprom */
3436                 error = mlx5_query_module_num(priv->mdev, &module_num);
3437                 if (error) {
3438                         mlx5_en_err(ifp,
3439                             "Query module num failed, eeprom reading is not supported\n");
3440                         error = EINVAL;
3441                         goto err_i2c;
3442                 }
3443                 /* Check if module is present before doing an access */
3444                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3445                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3446                         error = EINVAL;
3447                         goto err_i2c;
3448                 }
3449                 /*
3450                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3451                  * The internal conversion is as follows:
3452                  */
3453                 if (i2c.dev_addr == 0xA0)
3454                         read_addr = MLX5_I2C_ADDR_LOW;
3455                 else if (i2c.dev_addr == 0xA2)
3456                         read_addr = MLX5_I2C_ADDR_HIGH;
3457                 else {
3458                         mlx5_en_err(ifp,
3459                             "Query eeprom failed, Invalid Address: %X\n",
3460                             i2c.dev_addr);
3461                         error = EINVAL;
3462                         goto err_i2c;
3463                 }
3464                 error = mlx5_query_eeprom(priv->mdev,
3465                     read_addr, MLX5_EEPROM_LOW_PAGE,
3466                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3467                     (uint32_t *)i2c.data, &size_read);
3468                 if (error) {
3469                         mlx5_en_err(ifp,
3470                             "Query eeprom failed, eeprom reading is not supported\n");
3471                         error = EINVAL;
3472                         goto err_i2c;
3473                 }
3474
3475                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3476                         error = mlx5_query_eeprom(priv->mdev,
3477                             read_addr, MLX5_EEPROM_LOW_PAGE,
3478                             (uint32_t)(i2c.offset + size_read),
3479                             (uint32_t)(i2c.len - size_read), module_num,
3480                             (uint32_t *)(i2c.data + size_read), &size_read);
3481                 }
3482                 if (error) {
3483                         mlx5_en_err(ifp,
3484                             "Query eeprom failed, eeprom reading is not supported\n");
3485                         error = EINVAL;
3486                         goto err_i2c;
3487                 }
3488
3489                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3490 err_i2c:
3491                 PRIV_UNLOCK(priv);
3492                 break;
3493
3494         default:
3495                 error = ether_ioctl(ifp, command, data);
3496                 break;
3497         }
3498         return (error);
3499 }
3500
3501 static int
3502 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3503 {
3504         /*
3505          * TODO: uncoment once FW really sets all these bits if
3506          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3507          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3508          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3509          * -ENOTSUPP;
3510          */
3511
3512         /* TODO: add more must-to-have features */
3513
3514         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3515                 return (-ENODEV);
3516
3517         return (0);
3518 }
3519
3520 static u16
3521 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3522 {
3523         const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3524         const int max_size = MLX5E_MAX_TX_INLINE;
3525         const int bf_buf_size =
3526             ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3527             (sizeof(struct mlx5e_tx_wqe) - 2);
3528
3529         /* verify against driver limits */
3530         if (bf_buf_size > max_size)
3531                 return (max_size);
3532         else if (bf_buf_size < min_size)
3533                 return (min_size);
3534         else
3535                 return (bf_buf_size);
3536 }
3537
3538 static int
3539 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3540     struct mlx5e_priv *priv,
3541     int num_comp_vectors)
3542 {
3543         int err;
3544
3545         /*
3546          * TODO: Consider link speed for setting "log_sq_size",
3547          * "log_rq_size" and "cq_moderation_xxx":
3548          */
3549         priv->params.log_sq_size =
3550             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3551         priv->params.log_rq_size =
3552             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3553         priv->params.rx_cq_moderation_usec =
3554             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3555             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3556             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3557         priv->params.rx_cq_moderation_mode =
3558             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3559         priv->params.rx_cq_moderation_pkts =
3560             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3561         priv->params.tx_cq_moderation_usec =
3562             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3563         priv->params.tx_cq_moderation_pkts =
3564             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3565         priv->params.min_rx_wqes =
3566             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3567         priv->params.rx_hash_log_tbl_sz =
3568             (order_base_2(num_comp_vectors) >
3569             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3570             order_base_2(num_comp_vectors) :
3571             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3572         priv->params.num_tc = 1;
3573         priv->params.default_vlan_prio = 0;
3574         priv->counter_set_id = -1;
3575         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3576
3577         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3578         if (err)
3579                 return (err);
3580
3581         /*
3582          * hw lro is currently defaulted to off. when it won't anymore we
3583          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3584          */
3585         priv->params.hw_lro_en = false;
3586         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3587
3588         /*
3589          * CQE zipping is currently defaulted to off. when it won't
3590          * anymore we will consider the HW capability:
3591          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3592          */
3593         priv->params.cqe_zipping_en = false;
3594
3595         priv->mdev = mdev;
3596         priv->params.num_channels = num_comp_vectors;
3597         priv->params.channels_rsss = 1;
3598         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3599         priv->queue_mapping_channel_mask =
3600             roundup_pow_of_two(num_comp_vectors) - 1;
3601         priv->num_tc = priv->params.num_tc;
3602         priv->default_vlan_prio = priv->params.default_vlan_prio;
3603
3604         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3605         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3606         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3607
3608         return (0);
3609 }
3610
3611 static int
3612 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3613                   struct mlx5_core_mr *mkey)
3614 {
3615         struct ifnet *ifp = priv->ifp;
3616         struct mlx5_core_dev *mdev = priv->mdev;
3617         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3618         void *mkc;
3619         u32 *in;
3620         int err;
3621
3622         in = mlx5_vzalloc(inlen);
3623         if (in == NULL) {
3624                 mlx5_en_err(ifp, "failed to allocate inbox\n");
3625                 return (-ENOMEM);
3626         }
3627
3628         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3629         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3630         MLX5_SET(mkc, mkc, umr_en, 1);  /* used by HW TLS */
3631         MLX5_SET(mkc, mkc, lw, 1);
3632         MLX5_SET(mkc, mkc, lr, 1);
3633
3634         MLX5_SET(mkc, mkc, pd, pdn);
3635         MLX5_SET(mkc, mkc, length64, 1);
3636         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3637
3638         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3639         if (err)
3640                 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3641                     err);
3642
3643         kvfree(in);
3644         return (err);
3645 }
3646
3647 static const char *mlx5e_vport_stats_desc[] = {
3648         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3649 };
3650
3651 static const char *mlx5e_pport_stats_desc[] = {
3652         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3653 };
3654
3655 static void
3656 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3657 {
3658         uint32_t x;
3659
3660         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3661         sx_init(&priv->state_lock, "mlx5state");
3662         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3663         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3664         for (x = 0; x != channels; x++)
3665                 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3666 }
3667
3668 static void
3669 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3670 {
3671         uint32_t x;
3672
3673         for (x = 0; x != channels; x++)
3674                 mlx5e_chan_static_destroy(&priv->channel[x]);
3675         callout_drain(&priv->watchdog);
3676         mtx_destroy(&priv->async_events_mtx);
3677         sx_destroy(&priv->state_lock);
3678 }
3679
3680 static int
3681 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3682 {
3683         /*
3684          * %d.%d%.d the string format.
3685          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3686          * We need at most 5 chars to store that.
3687          * It also has: two "." and NULL at the end, which means we need 18
3688          * (5*3 + 3) chars at most.
3689          */
3690         char fw[18];
3691         struct mlx5e_priv *priv = arg1;
3692         int error;
3693
3694         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3695             fw_rev_sub(priv->mdev));
3696         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3697         return (error);
3698 }
3699
3700 static void
3701 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3702 {
3703         int i;
3704
3705         for (i = 0; i < ch->priv->num_tc; i++)
3706                 mlx5e_drain_sq(&ch->sq[i]);
3707 }
3708
3709 static void
3710 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3711 {
3712
3713         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3714         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3715         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3716         sq->doorbell.d64 = 0;
3717 }
3718
3719 void
3720 mlx5e_resume_sq(struct mlx5e_sq *sq)
3721 {
3722         int err;
3723
3724         /* check if already enabled */
3725         if (READ_ONCE(sq->running) != 0)
3726                 return;
3727
3728         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3729             MLX5_SQC_STATE_RST);
3730         if (err != 0) {
3731                 mlx5_en_err(sq->ifp,
3732                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3733         }
3734
3735         sq->cc = 0;
3736         sq->pc = 0;
3737
3738         /* reset doorbell prior to moving from RST to RDY */
3739         mlx5e_reset_sq_doorbell_record(sq);
3740
3741         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3742             MLX5_SQC_STATE_RDY);
3743         if (err != 0) {
3744                 mlx5_en_err(sq->ifp,
3745                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3746         }
3747
3748         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3749         WRITE_ONCE(sq->running, 1);
3750 }
3751
3752 static void
3753 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3754 {
3755         int i;
3756
3757         for (i = 0; i < ch->priv->num_tc; i++)
3758                 mlx5e_resume_sq(&ch->sq[i]);
3759 }
3760
3761 static void
3762 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3763 {
3764         struct mlx5e_rq *rq = &ch->rq;
3765         struct epoch_tracker et;
3766         int err;
3767
3768         mtx_lock(&rq->mtx);
3769         rq->enabled = 0;
3770         callout_stop(&rq->watchdog);
3771         mtx_unlock(&rq->mtx);
3772
3773         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3774         if (err != 0) {
3775                 mlx5_en_err(rq->ifp,
3776                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3777         }
3778
3779         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3780                 msleep(1);
3781                 NET_EPOCH_ENTER(et);
3782                 rq->cq.mcq.comp(&rq->cq.mcq);
3783                 NET_EPOCH_EXIT(et);
3784         }
3785
3786         /*
3787          * Transitioning into RST state will allow the FW to track less ERR state queues,
3788          * thus reducing the recv queue flushing time
3789          */
3790         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3791         if (err != 0) {
3792                 mlx5_en_err(rq->ifp,
3793                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3794         }
3795 }
3796
3797 static void
3798 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3799 {
3800         struct mlx5e_rq *rq = &ch->rq;
3801         struct epoch_tracker et;
3802         int err;
3803
3804         rq->wq.wqe_ctr = 0;
3805         mlx5_wq_ll_update_db_record(&rq->wq);
3806         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3807         if (err != 0) {
3808                 mlx5_en_err(rq->ifp,
3809                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3810         }
3811
3812         rq->enabled = 1;
3813
3814         NET_EPOCH_ENTER(et);
3815         rq->cq.mcq.comp(&rq->cq.mcq);
3816         NET_EPOCH_EXIT(et);
3817 }
3818
3819 void
3820 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3821 {
3822         int i;
3823
3824         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3825                 return;
3826
3827         for (i = 0; i < priv->params.num_channels; i++) {
3828                 if (value)
3829                         mlx5e_disable_tx_dma(&priv->channel[i]);
3830                 else
3831                         mlx5e_enable_tx_dma(&priv->channel[i]);
3832         }
3833 }
3834
3835 void
3836 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3837 {
3838         int i;
3839
3840         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3841                 return;
3842
3843         for (i = 0; i < priv->params.num_channels; i++) {
3844                 if (value)
3845                         mlx5e_disable_rx_dma(&priv->channel[i]);
3846                 else
3847                         mlx5e_enable_rx_dma(&priv->channel[i]);
3848         }
3849 }
3850
3851 static void
3852 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3853 {
3854         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3855             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
3856             priv, 0, sysctl_firmware, "A", "HCA firmware version");
3857
3858         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3859             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3860             "Board ID");
3861 }
3862
3863 static int
3864 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3865 {
3866         struct mlx5e_priv *priv = arg1;
3867         uint8_t temp[MLX5E_MAX_PRIORITY];
3868         uint32_t tx_pfc;
3869         int err;
3870         int i;
3871
3872         PRIV_LOCK(priv);
3873
3874         tx_pfc = priv->params.tx_priority_flow_control;
3875
3876         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3877                 temp[i] = (tx_pfc >> i) & 1;
3878
3879         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3880         if (err || !req->newptr)
3881                 goto done;
3882         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3883         if (err)
3884                 goto done;
3885
3886         priv->params.tx_priority_flow_control = 0;
3887
3888         /* range check input value */
3889         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3890                 if (temp[i] > 1) {
3891                         err = ERANGE;
3892                         goto done;
3893                 }
3894                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3895         }
3896
3897         /* check if update is required */
3898         if (tx_pfc != priv->params.tx_priority_flow_control)
3899                 err = -mlx5e_set_port_pfc(priv);
3900 done:
3901         if (err != 0)
3902                 priv->params.tx_priority_flow_control= tx_pfc;
3903         PRIV_UNLOCK(priv);
3904
3905         return (err);
3906 }
3907
3908 static int
3909 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3910 {
3911         struct mlx5e_priv *priv = arg1;
3912         uint8_t temp[MLX5E_MAX_PRIORITY];
3913         uint32_t rx_pfc;
3914         int err;
3915         int i;
3916
3917         PRIV_LOCK(priv);
3918
3919         rx_pfc = priv->params.rx_priority_flow_control;
3920
3921         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3922                 temp[i] = (rx_pfc >> i) & 1;
3923
3924         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3925         if (err || !req->newptr)
3926                 goto done;
3927         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3928         if (err)
3929                 goto done;
3930
3931         priv->params.rx_priority_flow_control = 0;
3932
3933         /* range check input value */
3934         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3935                 if (temp[i] > 1) {
3936                         err = ERANGE;
3937                         goto done;
3938                 }
3939                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3940         }
3941
3942         /* check if update is required */
3943         if (rx_pfc != priv->params.rx_priority_flow_control) {
3944                 err = -mlx5e_set_port_pfc(priv);
3945                 if (err == 0 && priv->sw_is_port_buf_owner)
3946                         err = mlx5e_update_buf_lossy(priv);
3947         }
3948 done:
3949         if (err != 0)
3950                 priv->params.rx_priority_flow_control= rx_pfc;
3951         PRIV_UNLOCK(priv);
3952
3953         return (err);
3954 }
3955
3956 static void
3957 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3958 {
3959 #if (__FreeBSD_version < 1100000)
3960         char path[96];
3961 #endif
3962         int error;
3963
3964         /* enable pauseframes by default */
3965         priv->params.tx_pauseframe_control = 1;
3966         priv->params.rx_pauseframe_control = 1;
3967
3968         /* disable ports flow control, PFC, by default */
3969         priv->params.tx_priority_flow_control = 0;
3970         priv->params.rx_priority_flow_control = 0;
3971
3972 #if (__FreeBSD_version < 1100000)
3973         /* compute path for sysctl */
3974         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3975             device_get_unit(priv->mdev->pdev->dev.bsddev));
3976
3977         /* try to fetch tunable, if any */
3978         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3979
3980         /* compute path for sysctl */
3981         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3982             device_get_unit(priv->mdev->pdev->dev.bsddev));
3983
3984         /* try to fetch tunable, if any */
3985         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3986 #endif
3987
3988         /* register pauseframe SYSCTLs */
3989         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3990             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3991             &priv->params.tx_pauseframe_control, 0,
3992             "Set to enable TX pause frames. Clear to disable.");
3993
3994         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3995             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3996             &priv->params.rx_pauseframe_control, 0,
3997             "Set to enable RX pause frames. Clear to disable.");
3998
3999         /* register priority flow control, PFC, SYSCTLs */
4000         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4001             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4002             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4003             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4004
4005         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4006             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4007             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4008             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4009
4010         PRIV_LOCK(priv);
4011
4012         /* range check */
4013         priv->params.tx_pauseframe_control =
4014             priv->params.tx_pauseframe_control ? 1 : 0;
4015         priv->params.rx_pauseframe_control =
4016             priv->params.rx_pauseframe_control ? 1 : 0;
4017
4018         /* update firmware */
4019         error = mlx5e_set_port_pause_and_pfc(priv);
4020         if (error == -EINVAL) {
4021                 mlx5_en_err(priv->ifp,
4022                     "Global pauseframes must be disabled before enabling PFC.\n");
4023                 priv->params.rx_priority_flow_control = 0;
4024                 priv->params.tx_priority_flow_control = 0;
4025
4026                 /* update firmware */
4027                 (void) mlx5e_set_port_pause_and_pfc(priv);
4028         }
4029         PRIV_UNLOCK(priv);
4030 }
4031
4032 int
4033 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4034     union if_snd_tag_alloc_params *params,
4035     struct m_snd_tag **ppmt)
4036 {
4037         struct mlx5e_priv *priv;
4038         struct mlx5e_channel *pch;
4039
4040         priv = ifp->if_softc;
4041
4042         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4043                 return (EOPNOTSUPP);
4044         } else {
4045                 /* keep this code synced with mlx5e_select_queue() */
4046                 u32 ch = priv->params.num_channels;
4047 #ifdef RSS
4048                 u32 temp;
4049
4050                 if (rss_hash2bucket(params->hdr.flowid,
4051                     params->hdr.flowtype, &temp) == 0)
4052                         ch = temp % ch;
4053                 else
4054 #endif
4055                         ch = (params->hdr.flowid % 128) % ch;
4056
4057                 /*
4058                  * NOTE: The channels array is only freed at detach
4059                  * and it safe to return a pointer to the send tag
4060                  * inside the channels structure as long as we
4061                  * reference the priv.
4062                  */
4063                 pch = priv->channel + ch;
4064
4065                 /* check if send queue is not running */
4066                 if (unlikely(pch->sq[0].running == 0))
4067                         return (ENXIO);
4068                 m_snd_tag_ref(&pch->tag.m_snd_tag);
4069                 *ppmt = &pch->tag.m_snd_tag;
4070                 return (0);
4071         }
4072 }
4073
4074 int
4075 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4076 {
4077         struct mlx5e_channel *pch =
4078             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4079
4080         params->unlimited.max_rate = -1ULL;
4081         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4082         return (0);
4083 }
4084
4085 void
4086 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4087 {
4088         struct mlx5e_channel *pch =
4089             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4090
4091         complete(&pch->completion);
4092 }
4093
4094 static int
4095 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4096     union if_snd_tag_alloc_params *params,
4097     struct m_snd_tag **ppmt)
4098 {
4099
4100         switch (params->hdr.type) {
4101 #ifdef RATELIMIT
4102         case IF_SND_TAG_TYPE_RATE_LIMIT:
4103                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4104 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4105         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4106                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4107 #endif
4108 #endif
4109         case IF_SND_TAG_TYPE_UNLIMITED:
4110                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4111 #ifdef KERN_TLS
4112         case IF_SND_TAG_TYPE_TLS:
4113                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4114 #endif
4115         default:
4116                 return (EOPNOTSUPP);
4117         }
4118 }
4119
4120 static int
4121 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4122 {
4123         struct mlx5e_snd_tag *tag =
4124             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4125
4126         switch (tag->type) {
4127 #ifdef RATELIMIT
4128         case IF_SND_TAG_TYPE_RATE_LIMIT:
4129                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4130 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4131         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4132                 return (mlx5e_tls_snd_tag_modify(pmt, params));
4133 #endif
4134 #endif
4135         case IF_SND_TAG_TYPE_UNLIMITED:
4136 #ifdef KERN_TLS
4137         case IF_SND_TAG_TYPE_TLS:
4138 #endif
4139         default:
4140                 return (EOPNOTSUPP);
4141         }
4142 }
4143
4144 static int
4145 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4146 {
4147         struct mlx5e_snd_tag *tag =
4148             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4149
4150         switch (tag->type) {
4151 #ifdef RATELIMIT
4152         case IF_SND_TAG_TYPE_RATE_LIMIT:
4153                 return (mlx5e_rl_snd_tag_query(pmt, params));
4154 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4155         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4156                 return (mlx5e_tls_snd_tag_query(pmt, params));
4157 #endif
4158 #endif
4159         case IF_SND_TAG_TYPE_UNLIMITED:
4160                 return (mlx5e_ul_snd_tag_query(pmt, params));
4161 #ifdef KERN_TLS
4162         case IF_SND_TAG_TYPE_TLS:
4163                 return (mlx5e_tls_snd_tag_query(pmt, params));
4164 #endif
4165         default:
4166                 return (EOPNOTSUPP);
4167         }
4168 }
4169
4170 #ifdef RATELIMIT
4171 #define NUM_HDWR_RATES_MLX 13
4172 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4173         135375,                 /* 1,083,000 */
4174         180500,                 /* 1,444,000 */
4175         270750,                 /* 2,166,000 */
4176         361000,                 /* 2,888,000 */
4177         541500,                 /* 4,332,000 */
4178         721875,                 /* 5,775,000 */
4179         1082875,                /* 8,663,000 */
4180         1443875,                /* 11,551,000 */
4181         2165750,                /* 17,326,000 */
4182         2887750,                /* 23,102,000 */
4183         4331625,                /* 34,653,000 */
4184         5775500,                /* 46,204,000 */
4185         8663125                 /* 69,305,000 */
4186 };
4187
4188 static void
4189 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4190 {
4191         /*
4192          * This function needs updating by the driver maintainer!
4193          * For the MLX card there are currently (ConectX-4?) 13
4194          * pre-set rates and others i.e. ConnectX-5, 6, 7??
4195          *
4196          * This will change based on later adapters
4197          * and this code should be updated to look at ifp
4198          * and figure out the specific adapter type
4199          * settings i.e. how many rates as well
4200          * as if they are fixed (as is shown here) or
4201          * if they are dynamic (example chelsio t4). Also if there
4202          * is a maximum number of flows that the adapter
4203          * can handle that too needs to be updated in
4204          * the max_flows field.
4205          */
4206         q->rate_table = adapter_rates_mlx;
4207         q->flags = RT_IS_FIXED_TABLE;
4208         q->max_flows = 0;       /* mlx has no limit */
4209         q->number_of_rates = NUM_HDWR_RATES_MLX;
4210         q->min_segment_burst = 1;
4211 }
4212 #endif
4213
4214 static void
4215 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4216 {
4217         struct mlx5e_snd_tag *tag =
4218             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4219
4220         switch (tag->type) {
4221 #ifdef RATELIMIT
4222         case IF_SND_TAG_TYPE_RATE_LIMIT:
4223                 mlx5e_rl_snd_tag_free(pmt);
4224                 break;
4225 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4226         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4227                 mlx5e_tls_snd_tag_free(pmt);
4228                 break;
4229 #endif
4230 #endif
4231         case IF_SND_TAG_TYPE_UNLIMITED:
4232                 mlx5e_ul_snd_tag_free(pmt);
4233                 break;
4234 #ifdef KERN_TLS
4235         case IF_SND_TAG_TYPE_TLS:
4236                 mlx5e_tls_snd_tag_free(pmt);
4237                 break;
4238 #endif
4239         default:
4240                 break;
4241         }
4242 }
4243
4244 static void *
4245 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4246 {
4247         struct ifnet *ifp;
4248         struct mlx5e_priv *priv;
4249         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4250         u8 connector_type;
4251         struct sysctl_oid_list *child;
4252         int ncv = mdev->priv.eq_table.num_comp_vectors;
4253         char unit[16];
4254         struct pfil_head_args pa;
4255         int err;
4256         int i,j;
4257         u32 eth_proto_cap;
4258         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4259         bool ext = 0;
4260         u32 speeds_num;
4261         struct media media_entry = {};
4262
4263         if (mlx5e_check_required_hca_cap(mdev)) {
4264                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4265                 return (NULL);
4266         }
4267         /*
4268          * Try to allocate the priv and make room for worst-case
4269          * number of channel structures:
4270          */
4271         priv = malloc(sizeof(*priv) +
4272             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4273             M_MLX5EN, M_WAITOK | M_ZERO);
4274
4275         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4276         if (ifp == NULL) {
4277                 mlx5_core_err(mdev, "if_alloc() failed\n");
4278                 goto err_free_priv;
4279         }
4280         /* setup all static fields */
4281         mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4282
4283         ifp->if_softc = priv;
4284         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4285         ifp->if_mtu = ETHERMTU;
4286         ifp->if_init = mlx5e_open;
4287         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
4288             IFF_KNOWSEPOCH;
4289         ifp->if_ioctl = mlx5e_ioctl;
4290         ifp->if_transmit = mlx5e_xmit;
4291         ifp->if_qflush = if_qflush;
4292 #if (__FreeBSD_version >= 1100000)
4293         ifp->if_get_counter = mlx5e_get_counter;
4294 #endif
4295         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4296         /*
4297          * Set driver features
4298          */
4299         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4300         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4301         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4302         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4303         ifp->if_capabilities |= IFCAP_LRO;
4304         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4305         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4306         ifp->if_capabilities |= IFCAP_NOMAP;
4307         ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4308         ifp->if_capabilities |= IFCAP_TXRTLMT;
4309         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4310         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4311         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4312         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4313 #ifdef RATELIMIT
4314         ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4315 #endif
4316         /* set TSO limits so that we don't have to drop TX packets */
4317         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4318         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4319         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4320
4321         ifp->if_capenable = ifp->if_capabilities;
4322         ifp->if_hwassist = 0;
4323         if (ifp->if_capenable & IFCAP_TSO)
4324                 ifp->if_hwassist |= CSUM_TSO;
4325         if (ifp->if_capenable & IFCAP_TXCSUM)
4326                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4327         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4328                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4329
4330         /* ifnet sysctl tree */
4331         sysctl_ctx_init(&priv->sysctl_ctx);
4332         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4333             OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4334             "MLX5 ethernet - interface name");
4335         if (priv->sysctl_ifnet == NULL) {
4336                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4337                 goto err_free_sysctl;
4338         }
4339         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4340         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4341             OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4342             "MLX5 ethernet - interface unit");
4343         if (priv->sysctl_ifnet == NULL) {
4344                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4345                 goto err_free_sysctl;
4346         }
4347
4348         /* HW sysctl tree */
4349         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4350         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4351             OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4352             "MLX5 ethernet dev hw");
4353         if (priv->sysctl_hw == NULL) {
4354                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4355                 goto err_free_sysctl;
4356         }
4357
4358         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4359         if (err) {
4360                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4361                 goto err_free_sysctl;
4362         }
4363
4364         /* reuse mlx5core's watchdog workqueue */
4365         priv->wq = mdev->priv.health.wq_watchdog;
4366
4367         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4368         if (err) {
4369                 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4370                 goto err_free_wq;
4371         }
4372         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4373         if (err) {
4374                 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4375                 goto err_unmap_free_uar;
4376         }
4377         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4378         if (err) {
4379                 mlx5_en_err(ifp,
4380                     "mlx5_alloc_transport_domain failed, %d\n", err);
4381                 goto err_dealloc_pd;
4382         }
4383         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4384         if (err) {
4385                 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4386                 goto err_dealloc_transport_domain;
4387         }
4388         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4389
4390         /* check if we should generate a random MAC address */
4391         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4392             is_zero_ether_addr(dev_addr)) {
4393                 random_ether_addr(dev_addr);
4394                 mlx5_en_err(ifp, "Assigned random MAC address\n");
4395         }
4396
4397         err = mlx5e_rl_init(priv);
4398         if (err) {
4399                 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4400                 goto err_create_mkey;
4401         }
4402
4403         err = mlx5e_tls_init(priv);
4404         if (err) {
4405                 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4406                 goto err_rl_init;
4407         }
4408
4409         /* set default MTU */
4410         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4411
4412         /* Set default media status */
4413         priv->media_status_last = IFM_AVALID;
4414         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4415             IFM_ETH_RXPAUSE | IFM_FDX;
4416
4417         /* setup default pauseframes configuration */
4418         mlx5e_setup_pauseframes(priv);
4419
4420         /* Setup supported medias */
4421         //TODO: If we failed to query ptys is it ok to proceed??
4422         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4423                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4424                     ptys_extended_ethernet);
4425                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4426                     eth_proto_capability);
4427                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4428                         connector_type = MLX5_GET(ptys_reg, out,
4429                             connector_type);
4430         } else {
4431                 eth_proto_cap = 0;
4432                 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4433         }
4434
4435         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4436             mlx5e_media_change, mlx5e_media_status);
4437
4438         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4439         for (i = 0; i != speeds_num; i++) {
4440                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4441                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4442                             mlx5e_mode_table[i][j];
4443                         if (media_entry.baudrate == 0)
4444                                 continue;
4445                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4446                                 ifmedia_add(&priv->media,
4447                                     media_entry.subtype |
4448                                     IFM_ETHER, 0, NULL);
4449                                 ifmedia_add(&priv->media,
4450                                     media_entry.subtype |
4451                                     IFM_ETHER | IFM_FDX |
4452                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4453                         }
4454                 }
4455         }
4456
4457         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4458         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4459             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4460
4461         /* Set autoselect by default */
4462         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4463             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4464
4465         DEBUGNET_SET(ifp, mlx5_en);
4466
4467         ether_ifattach(ifp, dev_addr);
4468
4469         /* Register for VLAN events */
4470         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4471             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4472         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4473             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4474
4475         /* Link is down by default */
4476         if_link_state_change(ifp, LINK_STATE_DOWN);
4477
4478         mlx5e_enable_async_events(priv);
4479
4480         mlx5e_add_hw_stats(priv);
4481
4482         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4483             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4484             priv->stats.vport.arg);
4485
4486         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4487             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4488             priv->stats.pport.arg);
4489
4490         mlx5e_create_ethtool(priv);
4491
4492         mtx_lock(&priv->async_events_mtx);
4493         mlx5e_update_stats(priv);
4494         mtx_unlock(&priv->async_events_mtx);
4495
4496         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4497             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4498             &priv->clbr_done, 0,
4499             "RX timestamps calibration state");
4500         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4501         mlx5e_reset_calibration_callout(priv);
4502
4503         pa.pa_version = PFIL_VERSION;
4504         pa.pa_flags = PFIL_IN;
4505         pa.pa_type = PFIL_TYPE_ETHERNET;
4506         pa.pa_headname = ifp->if_xname;
4507         priv->pfil = pfil_head_register(&pa);
4508
4509         return (priv);
4510
4511 err_rl_init:
4512         mlx5e_rl_cleanup(priv);
4513
4514 err_create_mkey:
4515         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4516
4517 err_dealloc_transport_domain:
4518         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4519
4520 err_dealloc_pd:
4521         mlx5_core_dealloc_pd(mdev, priv->pdn);
4522
4523 err_unmap_free_uar:
4524         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4525
4526 err_free_wq:
4527         flush_workqueue(priv->wq);
4528
4529 err_free_sysctl:
4530         sysctl_ctx_free(&priv->sysctl_ctx);
4531         if (priv->sysctl_debug)
4532                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4533         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4534         if_free(ifp);
4535
4536 err_free_priv:
4537         free(priv, M_MLX5EN);
4538         return (NULL);
4539 }
4540
4541 static void
4542 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4543 {
4544         struct mlx5e_priv *priv = vpriv;
4545         struct ifnet *ifp = priv->ifp;
4546
4547         /* don't allow more IOCTLs */
4548         priv->gone = 1;
4549
4550         /* XXX wait a bit to allow IOCTL handlers to complete */
4551         pause("W", hz);
4552
4553 #ifdef RATELIMIT
4554         /*
4555          * The kernel can have reference(s) via the m_snd_tag's into
4556          * the ratelimit channels, and these must go away before
4557          * detaching:
4558          */
4559         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4560                 mlx5_en_err(priv->ifp,
4561                     "Waiting for all ratelimit connections to terminate\n");
4562                 pause("W", hz);
4563         }
4564 #endif
4565         /* wait for all unlimited send tags to complete */
4566         mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4567
4568         /* stop watchdog timer */
4569         callout_drain(&priv->watchdog);
4570
4571         callout_drain(&priv->tstmp_clbr);
4572
4573         if (priv->vlan_attach != NULL)
4574                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4575         if (priv->vlan_detach != NULL)
4576                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4577
4578         /* make sure device gets closed */
4579         PRIV_LOCK(priv);
4580         mlx5e_close_locked(ifp);
4581         PRIV_UNLOCK(priv);
4582
4583         /* deregister pfil */
4584         if (priv->pfil != NULL) {
4585                 pfil_head_unregister(priv->pfil);
4586                 priv->pfil = NULL;
4587         }
4588
4589         /* unregister device */
4590         ifmedia_removeall(&priv->media);
4591         ether_ifdetach(ifp);
4592
4593         mlx5e_tls_cleanup(priv);
4594         mlx5e_rl_cleanup(priv);
4595
4596         /* destroy all remaining sysctl nodes */
4597         sysctl_ctx_free(&priv->stats.vport.ctx);
4598         sysctl_ctx_free(&priv->stats.pport.ctx);
4599         if (priv->sysctl_debug)
4600                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4601         sysctl_ctx_free(&priv->sysctl_ctx);
4602
4603         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4604         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4605         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4606         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4607         mlx5e_disable_async_events(priv);
4608         flush_workqueue(priv->wq);
4609         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4610         if_free(ifp);
4611         free(priv, M_MLX5EN);
4612 }
4613
4614 #ifdef DEBUGNET
4615 static void
4616 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4617 {
4618         struct mlx5e_priv *priv = if_getsoftc(dev);
4619
4620         PRIV_LOCK(priv);
4621         *nrxr = priv->params.num_channels;
4622         *ncl = DEBUGNET_MAX_IN_FLIGHT;
4623         *clsize = MLX5E_MAX_RX_BYTES;
4624         PRIV_UNLOCK(priv);
4625 }
4626
4627 static void
4628 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4629 {
4630 }
4631
4632 static int
4633 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
4634 {
4635         struct mlx5e_priv *priv = if_getsoftc(dev);
4636         struct mlx5e_sq *sq;
4637         int err;
4638
4639         if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4640             IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
4641                 return (ENOENT);
4642
4643         sq = &priv->channel[0].sq[0];
4644
4645         if (sq->running == 0) {
4646                 m_freem(m);
4647                 return (ENOENT);
4648         }
4649
4650         if (mlx5e_sq_xmit(sq, &m) != 0) {
4651                 m_freem(m);
4652                 err = ENOBUFS;
4653         } else {
4654                 err = 0;
4655         }
4656
4657         if (likely(sq->doorbell.d64 != 0)) {
4658                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
4659                 sq->doorbell.d64 = 0;
4660         }
4661         return (err);
4662 }
4663
4664 static int
4665 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
4666 {
4667         struct mlx5e_priv *priv = if_getsoftc(dev);
4668
4669         if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
4670             (priv->media_status_last & IFM_ACTIVE) == 0)
4671                 return (ENOENT);
4672
4673         mlx5_poll_interrupts(priv->mdev);
4674
4675         return (0);
4676 }
4677 #endif /* DEBUGNET */
4678
4679 static void *
4680 mlx5e_get_ifp(void *vpriv)
4681 {
4682         struct mlx5e_priv *priv = vpriv;
4683
4684         return (priv->ifp);
4685 }
4686
4687 static struct mlx5_interface mlx5e_interface = {
4688         .add = mlx5e_create_ifp,
4689         .remove = mlx5e_destroy_ifp,
4690         .event = mlx5e_async_event,
4691         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4692         .get_dev = mlx5e_get_ifp,
4693 };
4694
4695 void
4696 mlx5e_init(void)
4697 {
4698         mlx5_register_interface(&mlx5e_interface);
4699 }
4700
4701 void
4702 mlx5e_cleanup(void)
4703 {
4704         mlx5_unregister_interface(&mlx5e_interface);
4705 }
4706
4707 static void
4708 mlx5e_show_version(void __unused *arg)
4709 {
4710
4711         printf("%s", mlx5e_version);
4712 }
4713 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4714
4715 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4716 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4717
4718 #if (__FreeBSD_version >= 1100000)
4719 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4720 #endif
4721 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4722 MODULE_VERSION(mlx5en, 1);