2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #ifndef ETH_DRIVER_VERSION
34 #define ETH_DRIVER_VERSION "3.4.1"
36 char mlx5e_version[] = "Mellanox Ethernet driver"
37 " (" ETH_DRIVER_VERSION ")";
39 struct mlx5e_channel_param {
40 struct mlx5e_rq_param rq;
41 struct mlx5e_sq_param sq;
42 struct mlx5e_cq_param rx_cq;
43 struct mlx5e_cq_param tx_cq;
49 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
51 [MLX5E_1000BASE_CX_SGMII] = {
52 .subtype = IFM_1000_CX_SGMII,
53 .baudrate = IF_Mbps(1000ULL),
55 [MLX5E_1000BASE_KX] = {
56 .subtype = IFM_1000_KX,
57 .baudrate = IF_Mbps(1000ULL),
59 [MLX5E_10GBASE_CX4] = {
60 .subtype = IFM_10G_CX4,
61 .baudrate = IF_Gbps(10ULL),
63 [MLX5E_10GBASE_KX4] = {
64 .subtype = IFM_10G_KX4,
65 .baudrate = IF_Gbps(10ULL),
67 [MLX5E_10GBASE_KR] = {
68 .subtype = IFM_10G_KR,
69 .baudrate = IF_Gbps(10ULL),
71 [MLX5E_20GBASE_KR2] = {
72 .subtype = IFM_20G_KR2,
73 .baudrate = IF_Gbps(20ULL),
75 [MLX5E_40GBASE_CR4] = {
76 .subtype = IFM_40G_CR4,
77 .baudrate = IF_Gbps(40ULL),
79 [MLX5E_40GBASE_KR4] = {
80 .subtype = IFM_40G_KR4,
81 .baudrate = IF_Gbps(40ULL),
83 [MLX5E_56GBASE_R4] = {
84 .subtype = IFM_56G_R4,
85 .baudrate = IF_Gbps(56ULL),
87 [MLX5E_10GBASE_CR] = {
88 .subtype = IFM_10G_CR1,
89 .baudrate = IF_Gbps(10ULL),
91 [MLX5E_10GBASE_SR] = {
92 .subtype = IFM_10G_SR,
93 .baudrate = IF_Gbps(10ULL),
95 [MLX5E_10GBASE_ER] = {
96 .subtype = IFM_10G_ER,
97 .baudrate = IF_Gbps(10ULL),
99 [MLX5E_40GBASE_SR4] = {
100 .subtype = IFM_40G_SR4,
101 .baudrate = IF_Gbps(40ULL),
103 [MLX5E_40GBASE_LR4] = {
104 .subtype = IFM_40G_LR4,
105 .baudrate = IF_Gbps(40ULL),
107 [MLX5E_100GBASE_CR4] = {
108 .subtype = IFM_100G_CR4,
109 .baudrate = IF_Gbps(100ULL),
111 [MLX5E_100GBASE_SR4] = {
112 .subtype = IFM_100G_SR4,
113 .baudrate = IF_Gbps(100ULL),
115 [MLX5E_100GBASE_KR4] = {
116 .subtype = IFM_100G_KR4,
117 .baudrate = IF_Gbps(100ULL),
119 [MLX5E_100GBASE_LR4] = {
120 .subtype = IFM_100G_LR4,
121 .baudrate = IF_Gbps(100ULL),
123 [MLX5E_100BASE_TX] = {
124 .subtype = IFM_100_TX,
125 .baudrate = IF_Mbps(100ULL),
127 [MLX5E_1000BASE_T] = {
128 .subtype = IFM_1000_T,
129 .baudrate = IF_Mbps(1000ULL),
131 [MLX5E_10GBASE_T] = {
132 .subtype = IFM_10G_T,
133 .baudrate = IF_Gbps(10ULL),
135 [MLX5E_25GBASE_CR] = {
136 .subtype = IFM_25G_CR,
137 .baudrate = IF_Gbps(25ULL),
139 [MLX5E_25GBASE_KR] = {
140 .subtype = IFM_25G_KR,
141 .baudrate = IF_Gbps(25ULL),
143 [MLX5E_25GBASE_SR] = {
144 .subtype = IFM_25G_SR,
145 .baudrate = IF_Gbps(25ULL),
147 [MLX5E_50GBASE_CR2] = {
148 .subtype = IFM_50G_CR2,
149 .baudrate = IF_Gbps(50ULL),
151 [MLX5E_50GBASE_KR2] = {
152 .subtype = IFM_50G_KR2,
153 .baudrate = IF_Gbps(50ULL),
157 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
159 static SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "MLX5 driver parameters");
162 mlx5e_update_carrier(struct mlx5e_priv *priv)
164 struct mlx5_core_dev *mdev = priv->mdev;
165 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
171 port_state = mlx5_query_vport_state(mdev,
172 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
174 if (port_state == VPORT_STATE_UP) {
175 priv->media_status_last |= IFM_ACTIVE;
177 priv->media_status_last &= ~IFM_ACTIVE;
178 priv->media_active_last = IFM_ETHER;
179 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
183 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
185 priv->media_active_last = IFM_ETHER;
186 priv->ifp->if_baudrate = 1;
187 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
191 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
193 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
194 if (mlx5e_mode_table[i].baudrate == 0)
196 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
197 priv->ifp->if_baudrate =
198 mlx5e_mode_table[i].baudrate;
199 priv->media_active_last =
200 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
203 if_link_state_change(priv->ifp, LINK_STATE_UP);
207 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
209 struct mlx5e_priv *priv = dev->if_softc;
211 ifmr->ifm_status = priv->media_status_last;
212 ifmr->ifm_active = priv->media_active_last |
213 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
214 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
219 mlx5e_find_link_mode(u32 subtype)
224 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
225 if (mlx5e_mode_table[i].baudrate == 0)
227 if (mlx5e_mode_table[i].subtype == subtype)
228 link_mode |= MLX5E_PROT_MASK(i);
235 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
237 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
238 priv->params.rx_pauseframe_control,
239 priv->params.tx_pauseframe_control,
240 priv->params.rx_priority_flow_control,
241 priv->params.tx_priority_flow_control));
245 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
249 if (priv->params.rx_pauseframe_control ||
250 priv->params.tx_pauseframe_control) {
252 "Global pauseframes must be disabled before enabling PFC.\n");
255 error = mlx5e_set_port_pause_and_pfc(priv);
261 mlx5e_media_change(struct ifnet *dev)
263 struct mlx5e_priv *priv = dev->if_softc;
264 struct mlx5_core_dev *mdev = priv->mdev;
271 locked = PRIV_LOCKED(priv);
275 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
279 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
281 /* query supported capabilities */
282 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
284 if_printf(dev, "Query port media capability failed\n");
287 /* check for autoselect */
288 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
289 link_mode = eth_proto_cap;
290 if (link_mode == 0) {
291 if_printf(dev, "Port media capability is zero\n");
296 link_mode = link_mode & eth_proto_cap;
297 if (link_mode == 0) {
298 if_printf(dev, "Not supported link mode requested\n");
303 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
304 /* check if PFC is enabled */
305 if (priv->params.rx_priority_flow_control ||
306 priv->params.tx_priority_flow_control) {
307 if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
312 /* update pauseframe control bits */
313 priv->params.rx_pauseframe_control =
314 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
315 priv->params.tx_pauseframe_control =
316 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
318 /* check if device is opened */
319 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
321 /* reconfigure the hardware */
322 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
323 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
324 error = -mlx5e_set_port_pause_and_pfc(priv);
326 mlx5_set_port_status(mdev, MLX5_PORT_UP);
335 mlx5e_update_carrier_work(struct work_struct *work)
337 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
338 update_carrier_work);
341 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
342 mlx5e_update_carrier(priv);
347 * This function reads the physical port counters from the firmware
348 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
349 * macros. The output is converted from big-endian 64-bit values into
350 * host endian ones and stored in the "priv->stats.pport" structure.
353 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
355 struct mlx5_core_dev *mdev = priv->mdev;
356 struct mlx5e_pport_stats *s = &priv->stats.pport;
357 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
361 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
366 /* allocate firmware request structures */
367 in = mlx5_vzalloc(sz);
368 out = mlx5_vzalloc(sz);
369 if (in == NULL || out == NULL)
373 * Get pointer to the 64-bit counter set which is located at a
374 * fixed offset in the output firmware request structure:
376 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
378 MLX5_SET(ppcnt_reg, in, local_port, 1);
380 /* read IEEE802_3 counter group using predefined counter layout */
381 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
382 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
383 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
384 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
385 s->arg[y] = be64toh(ptr[x]);
387 /* read RFC2819 counter group using predefined counter layout */
388 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
389 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
390 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
391 s->arg[y] = be64toh(ptr[x]);
392 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
393 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
394 s_debug->arg[y] = be64toh(ptr[x]);
396 /* read RFC2863 counter group using predefined counter layout */
397 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
398 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
399 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
400 s_debug->arg[y] = be64toh(ptr[x]);
402 /* read physical layer stats counter group using predefined counter layout */
403 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
404 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
405 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
406 s_debug->arg[y] = be64toh(ptr[x]);
408 /* read per-priority counters */
409 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
411 /* iterate all the priorities */
412 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
413 MLX5_SET(ppcnt_reg, in, prio_tc, z);
414 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
416 /* read per priority stats counter group using predefined counter layout */
417 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
418 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
419 s->arg[y] = be64toh(ptr[x]);
422 /* free firmware request structures */
428 * This function is called regularly to collect all statistics
429 * counters from the firmware. The values can be viewed through the
430 * sysctl interface. Execution is serialized using the priv's global
431 * configuration lock.
434 mlx5e_update_stats_work(struct work_struct *work)
436 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
438 struct mlx5_core_dev *mdev = priv->mdev;
439 struct mlx5e_vport_stats *s = &priv->stats.vport;
440 struct mlx5e_rq_stats *rq_stats;
441 struct mlx5e_sq_stats *sq_stats;
442 struct buf_ring *sq_br;
443 #if (__FreeBSD_version < 1100000)
444 struct ifnet *ifp = priv->ifp;
447 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
449 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
452 u64 tx_queue_dropped = 0;
453 u64 tx_defragged = 0;
454 u64 tx_offload_none = 0;
457 u64 sw_lro_queued = 0;
458 u64 sw_lro_flushed = 0;
459 u64 rx_csum_none = 0;
461 u32 rx_out_of_buffer = 0;
466 out = mlx5_vzalloc(outlen);
469 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
472 /* Collect firts the SW counters and then HW for consistency */
473 for (i = 0; i < priv->params.num_channels; i++) {
474 struct mlx5e_rq *rq = &priv->channel[i]->rq;
476 rq_stats = &priv->channel[i]->rq.stats;
478 /* collect stats from LRO */
479 rq_stats->sw_lro_queued = rq->lro.lro_queued;
480 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
481 sw_lro_queued += rq_stats->sw_lro_queued;
482 sw_lro_flushed += rq_stats->sw_lro_flushed;
483 lro_packets += rq_stats->lro_packets;
484 lro_bytes += rq_stats->lro_bytes;
485 rx_csum_none += rq_stats->csum_none;
486 rx_wqe_err += rq_stats->wqe_err;
488 for (j = 0; j < priv->num_tc; j++) {
489 sq_stats = &priv->channel[i]->sq[j].stats;
490 sq_br = priv->channel[i]->sq[j].br;
492 tso_packets += sq_stats->tso_packets;
493 tso_bytes += sq_stats->tso_bytes;
494 tx_queue_dropped += sq_stats->dropped;
496 tx_queue_dropped += sq_br->br_drops;
497 tx_defragged += sq_stats->defragged;
498 tx_offload_none += sq_stats->csum_offload_none;
502 /* update counters */
503 s->tso_packets = tso_packets;
504 s->tso_bytes = tso_bytes;
505 s->tx_queue_dropped = tx_queue_dropped;
506 s->tx_defragged = tx_defragged;
507 s->lro_packets = lro_packets;
508 s->lro_bytes = lro_bytes;
509 s->sw_lro_queued = sw_lro_queued;
510 s->sw_lro_flushed = sw_lro_flushed;
511 s->rx_csum_none = rx_csum_none;
512 s->rx_wqe_err = rx_wqe_err;
515 memset(in, 0, sizeof(in));
517 MLX5_SET(query_vport_counter_in, in, opcode,
518 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
519 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
520 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
522 memset(out, 0, outlen);
524 /* get number of out-of-buffer drops first */
525 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
529 /* accumulate difference into a 64-bit counter */
530 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
531 s->rx_out_of_buffer_prev = rx_out_of_buffer;
533 /* get port statistics */
534 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
537 #define MLX5_GET_CTR(out, x) \
538 MLX5_GET64(query_vport_counter_out, out, x)
540 s->rx_error_packets =
541 MLX5_GET_CTR(out, received_errors.packets);
543 MLX5_GET_CTR(out, received_errors.octets);
544 s->tx_error_packets =
545 MLX5_GET_CTR(out, transmit_errors.packets);
547 MLX5_GET_CTR(out, transmit_errors.octets);
549 s->rx_unicast_packets =
550 MLX5_GET_CTR(out, received_eth_unicast.packets);
551 s->rx_unicast_bytes =
552 MLX5_GET_CTR(out, received_eth_unicast.octets);
553 s->tx_unicast_packets =
554 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
555 s->tx_unicast_bytes =
556 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
558 s->rx_multicast_packets =
559 MLX5_GET_CTR(out, received_eth_multicast.packets);
560 s->rx_multicast_bytes =
561 MLX5_GET_CTR(out, received_eth_multicast.octets);
562 s->tx_multicast_packets =
563 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
564 s->tx_multicast_bytes =
565 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
567 s->rx_broadcast_packets =
568 MLX5_GET_CTR(out, received_eth_broadcast.packets);
569 s->rx_broadcast_bytes =
570 MLX5_GET_CTR(out, received_eth_broadcast.octets);
571 s->tx_broadcast_packets =
572 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
573 s->tx_broadcast_bytes =
574 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
577 s->rx_unicast_packets +
578 s->rx_multicast_packets +
579 s->rx_broadcast_packets -
582 s->rx_unicast_bytes +
583 s->rx_multicast_bytes +
584 s->rx_broadcast_bytes;
586 s->tx_unicast_packets +
587 s->tx_multicast_packets +
588 s->tx_broadcast_packets;
590 s->tx_unicast_bytes +
591 s->tx_multicast_bytes +
592 s->tx_broadcast_bytes;
594 /* Update calculated offload counters */
595 s->tx_csum_offload = s->tx_packets - tx_offload_none;
596 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
598 /* Get physical port counters */
599 mlx5e_update_pport_counters(priv);
601 #if (__FreeBSD_version < 1100000)
602 /* no get_counters interface in fbsd 10 */
603 ifp->if_ipackets = s->rx_packets;
604 ifp->if_ierrors = s->rx_error_packets +
605 priv->stats.pport.alignment_err +
606 priv->stats.pport.check_seq_err +
607 priv->stats.pport.crc_align_errors +
608 priv->stats.pport.in_range_len_errors +
609 priv->stats.pport.jabbers +
610 priv->stats.pport.out_of_range_len +
611 priv->stats.pport.oversize_pkts +
612 priv->stats.pport.symbol_err +
613 priv->stats.pport.too_long_errors +
614 priv->stats.pport.undersize_pkts +
615 priv->stats.pport.unsupported_op_rx;
616 ifp->if_iqdrops = s->rx_out_of_buffer +
617 priv->stats.pport.drop_events;
618 ifp->if_opackets = s->tx_packets;
619 ifp->if_oerrors = s->tx_error_packets;
620 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
621 ifp->if_ibytes = s->rx_bytes;
622 ifp->if_obytes = s->tx_bytes;
624 priv->stats.pport.collisions;
630 /* Update diagnostics, if any */
631 if (priv->params_ethtool.diag_pci_enable ||
632 priv->params_ethtool.diag_general_enable) {
633 int error = mlx5_core_get_diagnostics_full(mdev,
634 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
635 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
637 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
643 mlx5e_update_stats(void *arg)
645 struct mlx5e_priv *priv = arg;
647 queue_work(priv->wq, &priv->update_stats_work);
649 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
653 mlx5e_async_event_sub(struct mlx5e_priv *priv,
654 enum mlx5_dev_event event)
657 case MLX5_DEV_EVENT_PORT_UP:
658 case MLX5_DEV_EVENT_PORT_DOWN:
659 queue_work(priv->wq, &priv->update_carrier_work);
668 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
669 enum mlx5_dev_event event, unsigned long param)
671 struct mlx5e_priv *priv = vpriv;
673 mtx_lock(&priv->async_events_mtx);
674 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
675 mlx5e_async_event_sub(priv, event);
676 mtx_unlock(&priv->async_events_mtx);
680 mlx5e_enable_async_events(struct mlx5e_priv *priv)
682 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
686 mlx5e_disable_async_events(struct mlx5e_priv *priv)
688 mtx_lock(&priv->async_events_mtx);
689 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
690 mtx_unlock(&priv->async_events_mtx);
693 static void mlx5e_calibration_callout(void *arg);
694 static int mlx5e_calibration_duration = 20;
695 static int mlx5e_fast_calibration = 1;
696 static int mlx5e_normal_calibration = 30;
698 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
699 "MLX5 timestamp calibration parameteres");
701 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
702 &mlx5e_calibration_duration, 0,
703 "Duration of initial calibration");
704 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
705 &mlx5e_fast_calibration, 0,
706 "Recalibration interval during initial calibration");
707 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
708 &mlx5e_normal_calibration, 0,
709 "Recalibration interval during normal operations");
712 * Ignites the calibration process.
715 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
718 if (priv->clbr_done == 0)
719 mlx5e_calibration_callout(priv);
721 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
722 mlx5e_calibration_duration ? mlx5e_fast_calibration :
723 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
728 mlx5e_timespec2usec(const struct timespec *ts)
731 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
735 mlx5e_hw_clock(struct mlx5e_priv *priv)
737 struct mlx5_init_seg *iseg;
738 uint32_t hw_h, hw_h1, hw_l;
740 iseg = priv->mdev->iseg;
742 hw_h = ioread32be(&iseg->internal_timer_h);
743 hw_l = ioread32be(&iseg->internal_timer_l);
744 hw_h1 = ioread32be(&iseg->internal_timer_h);
745 } while (hw_h1 != hw_h);
746 return (((uint64_t)hw_h << 32) | hw_l);
750 * The calibration callout, it runs either in the context of the
751 * thread which enables calibration, or in callout. It takes the
752 * snapshot of system and adapter clocks, then advances the pointers to
753 * the calibration point to allow rx path to read the consistent data
757 mlx5e_calibration_callout(void *arg)
759 struct mlx5e_priv *priv;
760 struct mlx5e_clbr_point *next, *curr;
765 curr = &priv->clbr_points[priv->clbr_curr];
766 clbr_curr_next = priv->clbr_curr + 1;
767 if (clbr_curr_next >= nitems(priv->clbr_points))
769 next = &priv->clbr_points[clbr_curr_next];
771 next->base_prev = curr->base_curr;
772 next->clbr_hw_prev = curr->clbr_hw_curr;
774 next->clbr_hw_curr = mlx5e_hw_clock(priv);
775 if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
777 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
778 "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
784 next->base_curr = mlx5e_timespec2usec(&ts);
787 atomic_thread_fence_rel();
788 priv->clbr_curr = clbr_curr_next;
789 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
791 if (priv->clbr_done < mlx5e_calibration_duration)
793 mlx5e_reset_calibration_callout(priv);
796 static const char *mlx5e_rq_stats_desc[] = {
797 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
801 mlx5e_create_rq(struct mlx5e_channel *c,
802 struct mlx5e_rq_param *param,
805 struct mlx5e_priv *priv = c->priv;
806 struct mlx5_core_dev *mdev = priv->mdev;
808 void *rqc = param->rqc;
809 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
814 /* Create DMA descriptor TAG */
815 if ((err = -bus_dma_tag_create(
816 bus_get_dma_tag(mdev->pdev->dev.bsddev),
817 1, /* any alignment */
819 BUS_SPACE_MAXADDR, /* lowaddr */
820 BUS_SPACE_MAXADDR, /* highaddr */
821 NULL, NULL, /* filter, filterarg */
822 MJUM16BYTES, /* maxsize */
824 MJUM16BYTES, /* maxsegsize */
826 NULL, NULL, /* lockfunc, lockfuncarg */
830 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
833 goto err_free_dma_tag;
835 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
837 if (priv->params.hw_lro_en) {
838 rq->wqe_sz = priv->params.lro_wqe_sz;
840 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
842 if (rq->wqe_sz > MJUM16BYTES) {
844 goto err_rq_wq_destroy;
845 } else if (rq->wqe_sz > MJUM9BYTES) {
846 rq->wqe_sz = MJUM16BYTES;
847 } else if (rq->wqe_sz > MJUMPAGESIZE) {
848 rq->wqe_sz = MJUM9BYTES;
849 } else if (rq->wqe_sz > MCLBYTES) {
850 rq->wqe_sz = MJUMPAGESIZE;
852 rq->wqe_sz = MCLBYTES;
855 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
857 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
859 goto err_rq_wq_destroy;
861 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
862 for (i = 0; i != wq_sz; i++) {
863 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
864 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
866 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
869 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
870 goto err_rq_mbuf_free;
872 wqe->data.lkey = c->mkey_be;
873 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
880 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
881 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
882 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
887 free(rq->mbuf, M_MLX5EN);
888 tcp_lro_free(&rq->lro);
890 mlx5_wq_destroy(&rq->wq_ctrl);
892 bus_dma_tag_destroy(rq->dma_tag);
898 mlx5e_destroy_rq(struct mlx5e_rq *rq)
903 /* destroy all sysctl nodes */
904 sysctl_ctx_free(&rq->stats.ctx);
906 /* free leftover LRO packets, if any */
907 tcp_lro_free(&rq->lro);
909 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
910 for (i = 0; i != wq_sz; i++) {
911 if (rq->mbuf[i].mbuf != NULL) {
912 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
913 m_freem(rq->mbuf[i].mbuf);
915 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
917 free(rq->mbuf, M_MLX5EN);
918 mlx5_wq_destroy(&rq->wq_ctrl);
922 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
924 struct mlx5e_channel *c = rq->channel;
925 struct mlx5e_priv *priv = c->priv;
926 struct mlx5_core_dev *mdev = priv->mdev;
934 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
935 sizeof(u64) * rq->wq_ctrl.buf.npages;
936 in = mlx5_vzalloc(inlen);
940 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
941 wq = MLX5_ADDR_OF(rqc, rqc, wq);
943 memcpy(rqc, param->rqc, sizeof(param->rqc));
945 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
946 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
947 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
948 if (priv->counter_set_id >= 0)
949 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
950 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
952 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
954 mlx5_fill_page_array(&rq->wq_ctrl.buf,
955 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
957 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
965 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
967 struct mlx5e_channel *c = rq->channel;
968 struct mlx5e_priv *priv = c->priv;
969 struct mlx5_core_dev *mdev = priv->mdev;
976 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
977 in = mlx5_vzalloc(inlen);
981 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
983 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
984 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
985 MLX5_SET(rqc, rqc, state, next_state);
987 err = mlx5_core_modify_rq(mdev, in, inlen);
995 mlx5e_disable_rq(struct mlx5e_rq *rq)
997 struct mlx5e_channel *c = rq->channel;
998 struct mlx5e_priv *priv = c->priv;
999 struct mlx5_core_dev *mdev = priv->mdev;
1001 mlx5_core_destroy_rq(mdev, rq->rqn);
1005 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1007 struct mlx5e_channel *c = rq->channel;
1008 struct mlx5e_priv *priv = c->priv;
1009 struct mlx5_wq_ll *wq = &rq->wq;
1012 for (i = 0; i < 1000; i++) {
1013 if (wq->cur_sz >= priv->params.min_rx_wqes)
1018 return (-ETIMEDOUT);
1022 mlx5e_open_rq(struct mlx5e_channel *c,
1023 struct mlx5e_rq_param *param,
1024 struct mlx5e_rq *rq)
1028 err = mlx5e_create_rq(c, param, rq);
1032 err = mlx5e_enable_rq(rq, param);
1034 goto err_destroy_rq;
1036 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1038 goto err_disable_rq;
1045 mlx5e_disable_rq(rq);
1047 mlx5e_destroy_rq(rq);
1053 mlx5e_close_rq(struct mlx5e_rq *rq)
1057 callout_stop(&rq->watchdog);
1058 mtx_unlock(&rq->mtx);
1060 callout_drain(&rq->watchdog);
1062 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1066 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1068 struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1070 /* wait till RQ is empty */
1071 while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1072 (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1074 rq->cq.mcq.comp(&rq->cq.mcq);
1077 mlx5e_disable_rq(rq);
1078 mlx5e_destroy_rq(rq);
1082 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1084 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1087 for (x = 0; x != wq_sz; x++)
1088 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1089 free(sq->mbuf, M_MLX5EN);
1093 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1095 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1099 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1101 /* Create DMA descriptor MAPs */
1102 for (x = 0; x != wq_sz; x++) {
1103 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1106 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1107 free(sq->mbuf, M_MLX5EN);
1114 static const char *mlx5e_sq_stats_desc[] = {
1115 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1119 mlx5e_create_sq(struct mlx5e_channel *c,
1121 struct mlx5e_sq_param *param,
1122 struct mlx5e_sq *sq)
1124 struct mlx5e_priv *priv = c->priv;
1125 struct mlx5_core_dev *mdev = priv->mdev;
1128 void *sqc = param->sqc;
1129 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1136 /* Create DMA descriptor TAG */
1137 if ((err = -bus_dma_tag_create(
1138 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1139 1, /* any alignment */
1140 0, /* no boundary */
1141 BUS_SPACE_MAXADDR, /* lowaddr */
1142 BUS_SPACE_MAXADDR, /* highaddr */
1143 NULL, NULL, /* filter, filterarg */
1144 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1145 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1146 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1148 NULL, NULL, /* lockfunc, lockfuncarg */
1152 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1154 goto err_free_dma_tag;
1156 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1159 goto err_unmap_free_uar;
1161 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1162 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1164 err = mlx5e_alloc_sq_db(sq);
1166 goto err_sq_wq_destroy;
1168 sq->mkey_be = c->mkey_be;
1169 sq->ifp = priv->ifp;
1173 /* check if we should allocate a second packet buffer */
1174 if (priv->params_ethtool.tx_bufring_disable == 0) {
1175 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1176 M_WAITOK, &sq->lock);
1177 if (sq->br == NULL) {
1178 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1181 goto err_free_sq_db;
1184 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1185 taskqueue_thread_enqueue, &sq->sq_tq);
1186 if (sq->sq_tq == NULL) {
1187 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1193 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1195 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1196 CPU_SETOF(cpu_id, &cpu_mask);
1197 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1198 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1200 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1201 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1204 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1205 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1206 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1212 buf_ring_free(sq->br, M_MLX5EN);
1214 mlx5e_free_sq_db(sq);
1216 mlx5_wq_destroy(&sq->wq_ctrl);
1219 mlx5_unmap_free_uar(mdev, &sq->uar);
1222 bus_dma_tag_destroy(sq->dma_tag);
1228 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1230 /* destroy all sysctl nodes */
1231 sysctl_ctx_free(&sq->stats.ctx);
1233 mlx5e_free_sq_db(sq);
1234 mlx5_wq_destroy(&sq->wq_ctrl);
1235 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1236 if (sq->sq_tq != NULL) {
1237 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1238 taskqueue_free(sq->sq_tq);
1241 buf_ring_free(sq->br, M_MLX5EN);
1245 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1254 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1255 sizeof(u64) * sq->wq_ctrl.buf.npages;
1256 in = mlx5_vzalloc(inlen);
1260 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1261 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1263 memcpy(sqc, param->sqc, sizeof(param->sqc));
1265 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1266 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1267 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1268 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1269 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1271 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1272 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1273 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1275 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1277 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1278 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1280 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1288 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1295 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1296 in = mlx5_vzalloc(inlen);
1300 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1302 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1303 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1304 MLX5_SET(sqc, sqc, state, next_state);
1306 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1314 mlx5e_disable_sq(struct mlx5e_sq *sq)
1317 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1321 mlx5e_open_sq(struct mlx5e_channel *c,
1323 struct mlx5e_sq_param *param,
1324 struct mlx5e_sq *sq)
1328 err = mlx5e_create_sq(c, tc, param, sq);
1332 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1334 goto err_destroy_sq;
1336 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1338 goto err_disable_sq;
1340 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1345 mlx5e_disable_sq(sq);
1347 mlx5e_destroy_sq(sq);
1353 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1355 /* fill up remainder with NOPs */
1356 while (sq->cev_counter != 0) {
1357 while (!mlx5e_sq_has_room_for(sq, 1)) {
1358 if (can_sleep != 0) {
1359 mtx_unlock(&sq->lock);
1361 mtx_lock(&sq->lock);
1366 /* send a single NOP */
1367 mlx5e_send_nop(sq, 1);
1368 atomic_thread_fence_rel();
1371 /* Check if we need to write the doorbell */
1372 if (likely(sq->doorbell.d64 != 0)) {
1373 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1374 sq->doorbell.d64 = 0;
1379 mlx5e_sq_cev_timeout(void *arg)
1381 struct mlx5e_sq *sq = arg;
1383 mtx_assert(&sq->lock, MA_OWNED);
1385 /* check next state */
1386 switch (sq->cev_next_state) {
1387 case MLX5E_CEV_STATE_SEND_NOPS:
1388 /* fill TX ring with NOPs, if any */
1389 mlx5e_sq_send_nops_locked(sq, 0);
1391 /* check if completed */
1392 if (sq->cev_counter == 0) {
1393 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1398 /* send NOPs on next timeout */
1399 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1404 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1408 mlx5e_drain_sq(struct mlx5e_sq *sq)
1411 struct mlx5_core_dev *mdev= sq->priv->mdev;
1414 * Check if already stopped.
1416 * NOTE: The "stopped" variable is only written when both the
1417 * priv's configuration lock and the SQ's lock is locked. It
1418 * can therefore safely be read when only one of the two locks
1419 * is locked. This function is always called when the priv's
1420 * configuration lock is locked.
1422 if (sq->stopped != 0)
1425 mtx_lock(&sq->lock);
1427 /* don't put more packets into the SQ */
1430 /* teardown event factor timer, if any */
1431 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1432 callout_stop(&sq->cev_callout);
1434 /* send dummy NOPs in order to flush the transmit ring */
1435 mlx5e_sq_send_nops_locked(sq, 1);
1436 mtx_unlock(&sq->lock);
1438 /* make sure it is safe to free the callout */
1439 callout_drain(&sq->cev_callout);
1441 /* wait till SQ is empty or link is down */
1442 mtx_lock(&sq->lock);
1443 while (sq->cc != sq->pc &&
1444 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1445 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1446 mtx_unlock(&sq->lock);
1448 sq->cq.mcq.comp(&sq->cq.mcq);
1449 mtx_lock(&sq->lock);
1451 mtx_unlock(&sq->lock);
1453 /* error out remaining requests */
1454 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1457 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1460 /* wait till SQ is empty */
1461 mtx_lock(&sq->lock);
1462 while (sq->cc != sq->pc &&
1463 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1464 mtx_unlock(&sq->lock);
1466 sq->cq.mcq.comp(&sq->cq.mcq);
1467 mtx_lock(&sq->lock);
1469 mtx_unlock(&sq->lock);
1473 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1477 mlx5e_disable_sq(sq);
1478 mlx5e_destroy_sq(sq);
1482 mlx5e_create_cq(struct mlx5e_priv *priv,
1483 struct mlx5e_cq_param *param,
1484 struct mlx5e_cq *cq,
1485 mlx5e_cq_comp_t *comp,
1488 struct mlx5_core_dev *mdev = priv->mdev;
1489 struct mlx5_core_cq *mcq = &cq->mcq;
1495 param->wq.buf_numa_node = 0;
1496 param->wq.db_numa_node = 0;
1498 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1503 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1506 mcq->set_ci_db = cq->wq_ctrl.db.db;
1507 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1508 *mcq->set_ci_db = 0;
1510 mcq->vector = eq_ix;
1512 mcq->event = mlx5e_cq_error_event;
1514 mcq->uar = &priv->cq_uar;
1516 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1517 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1528 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1530 mlx5_wq_destroy(&cq->wq_ctrl);
1534 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1536 struct mlx5_core_cq *mcq = &cq->mcq;
1544 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1545 sizeof(u64) * cq->wq_ctrl.buf.npages;
1546 in = mlx5_vzalloc(inlen);
1550 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1552 memcpy(cqc, param->cqc, sizeof(param->cqc));
1554 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1555 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1557 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1559 MLX5_SET(cqc, cqc, c_eqn, eqn);
1560 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1561 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1563 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1565 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1572 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1578 mlx5e_disable_cq(struct mlx5e_cq *cq)
1581 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1585 mlx5e_open_cq(struct mlx5e_priv *priv,
1586 struct mlx5e_cq_param *param,
1587 struct mlx5e_cq *cq,
1588 mlx5e_cq_comp_t *comp,
1593 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1597 err = mlx5e_enable_cq(cq, param, eq_ix);
1599 goto err_destroy_cq;
1604 mlx5e_destroy_cq(cq);
1610 mlx5e_close_cq(struct mlx5e_cq *cq)
1612 mlx5e_disable_cq(cq);
1613 mlx5e_destroy_cq(cq);
1617 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1618 struct mlx5e_channel_param *cparam)
1623 for (tc = 0; tc < c->num_tc; tc++) {
1624 /* open completion queue */
1625 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1626 &mlx5e_tx_cq_comp, c->ix);
1628 goto err_close_tx_cqs;
1633 for (tc--; tc >= 0; tc--)
1634 mlx5e_close_cq(&c->sq[tc].cq);
1640 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1644 for (tc = 0; tc < c->num_tc; tc++)
1645 mlx5e_close_cq(&c->sq[tc].cq);
1649 mlx5e_open_sqs(struct mlx5e_channel *c,
1650 struct mlx5e_channel_param *cparam)
1655 for (tc = 0; tc < c->num_tc; tc++) {
1656 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1664 for (tc--; tc >= 0; tc--)
1665 mlx5e_close_sq_wait(&c->sq[tc]);
1671 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1675 for (tc = 0; tc < c->num_tc; tc++)
1676 mlx5e_close_sq_wait(&c->sq[tc]);
1680 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1684 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1686 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1688 for (tc = 0; tc < c->num_tc; tc++) {
1689 struct mlx5e_sq *sq = c->sq + tc;
1691 mtx_init(&sq->lock, "mlx5tx",
1692 MTX_NETWORK_LOCK " TX", MTX_DEF);
1693 mtx_init(&sq->comp_lock, "mlx5comp",
1694 MTX_NETWORK_LOCK " TX", MTX_DEF);
1696 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1698 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1700 /* ensure the TX completion event factor is not zero */
1701 if (sq->cev_factor == 0)
1707 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1711 mtx_destroy(&c->rq.mtx);
1713 for (tc = 0; tc < c->num_tc; tc++) {
1714 mtx_destroy(&c->sq[tc].lock);
1715 mtx_destroy(&c->sq[tc].comp_lock);
1720 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1721 struct mlx5e_channel_param *cparam,
1722 struct mlx5e_channel *volatile *cp)
1724 struct mlx5e_channel *c;
1727 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1732 c->mkey_be = cpu_to_be32(priv->mr.key);
1733 c->num_tc = priv->num_tc;
1736 mlx5e_chan_mtx_init(c);
1738 /* open transmit completion queue */
1739 err = mlx5e_open_tx_cqs(c, cparam);
1743 /* open receive completion queue */
1744 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1745 &mlx5e_rx_cq_comp, c->ix);
1747 goto err_close_tx_cqs;
1749 err = mlx5e_open_sqs(c, cparam);
1751 goto err_close_rx_cq;
1753 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1757 /* store channel pointer */
1760 /* poll receive queue initially */
1761 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1766 mlx5e_close_sqs_wait(c);
1769 mlx5e_close_cq(&c->rq.cq);
1772 mlx5e_close_tx_cqs(c);
1775 /* destroy mutexes */
1776 mlx5e_chan_mtx_destroy(c);
1782 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1784 struct mlx5e_channel *c = *pp;
1786 /* check if channel is already closed */
1789 mlx5e_close_rq(&c->rq);
1793 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1795 struct mlx5e_channel *c = *pp;
1797 /* check if channel is already closed */
1800 /* ensure channel pointer is no longer used */
1803 mlx5e_close_rq_wait(&c->rq);
1804 mlx5e_close_sqs_wait(c);
1805 mlx5e_close_cq(&c->rq.cq);
1806 mlx5e_close_tx_cqs(c);
1807 /* destroy mutexes */
1808 mlx5e_chan_mtx_destroy(c);
1813 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1814 struct mlx5e_rq_param *param)
1816 void *rqc = param->rqc;
1817 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1819 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1820 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1821 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1822 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1823 MLX5_SET(wq, wq, pd, priv->pdn);
1825 param->wq.buf_numa_node = 0;
1826 param->wq.db_numa_node = 0;
1827 param->wq.linear = 1;
1831 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1832 struct mlx5e_sq_param *param)
1834 void *sqc = param->sqc;
1835 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1837 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1838 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1839 MLX5_SET(wq, wq, pd, priv->pdn);
1841 param->wq.buf_numa_node = 0;
1842 param->wq.db_numa_node = 0;
1843 param->wq.linear = 1;
1847 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1848 struct mlx5e_cq_param *param)
1850 void *cqc = param->cqc;
1852 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1856 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1857 struct mlx5e_cq_param *param)
1859 void *cqc = param->cqc;
1863 * TODO The sysctl to control on/off is a bool value for now, which means
1864 * we only support CSUM, once HASH is implemnted we'll need to address that.
1866 if (priv->params.cqe_zipping_en) {
1867 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1868 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1871 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1872 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1873 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1875 switch (priv->params.rx_cq_moderation_mode) {
1877 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1880 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1881 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1883 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1887 mlx5e_build_common_cq_param(priv, param);
1891 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1892 struct mlx5e_cq_param *param)
1894 void *cqc = param->cqc;
1896 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1897 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1898 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1900 switch (priv->params.tx_cq_moderation_mode) {
1902 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1905 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1906 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1908 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1912 mlx5e_build_common_cq_param(priv, param);
1916 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1917 struct mlx5e_channel_param *cparam)
1919 memset(cparam, 0, sizeof(*cparam));
1921 mlx5e_build_rq_param(priv, &cparam->rq);
1922 mlx5e_build_sq_param(priv, &cparam->sq);
1923 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1924 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1928 mlx5e_open_channels(struct mlx5e_priv *priv)
1930 struct mlx5e_channel_param cparam;
1936 priv->channel = malloc(priv->params.num_channels *
1937 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1939 mlx5e_build_channel_param(priv, &cparam);
1940 for (i = 0; i < priv->params.num_channels; i++) {
1941 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1943 goto err_close_channels;
1946 for (j = 0; j < priv->params.num_channels; j++) {
1947 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1949 goto err_close_channels;
1955 for (i--; i >= 0; i--) {
1956 mlx5e_close_channel(&priv->channel[i]);
1957 mlx5e_close_channel_wait(&priv->channel[i]);
1960 /* remove "volatile" attribute from "channel" pointer */
1961 ptr = __DECONST(void *, priv->channel);
1962 priv->channel = NULL;
1964 free(ptr, M_MLX5EN);
1970 mlx5e_close_channels(struct mlx5e_priv *priv)
1975 if (priv->channel == NULL)
1978 for (i = 0; i < priv->params.num_channels; i++)
1979 mlx5e_close_channel(&priv->channel[i]);
1980 for (i = 0; i < priv->params.num_channels; i++)
1981 mlx5e_close_channel_wait(&priv->channel[i]);
1983 /* remove "volatile" attribute from "channel" pointer */
1984 ptr = __DECONST(void *, priv->channel);
1985 priv->channel = NULL;
1987 free(ptr, M_MLX5EN);
1991 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1994 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1997 switch (priv->params.tx_cq_moderation_mode) {
1999 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2002 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2006 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2007 priv->params.tx_cq_moderation_usec,
2008 priv->params.tx_cq_moderation_pkts,
2012 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2013 priv->params.tx_cq_moderation_usec,
2014 priv->params.tx_cq_moderation_pkts));
2018 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2021 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2025 switch (priv->params.rx_cq_moderation_mode) {
2027 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2030 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2034 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2035 priv->params.rx_cq_moderation_usec,
2036 priv->params.rx_cq_moderation_pkts,
2042 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2043 priv->params.rx_cq_moderation_usec,
2044 priv->params.rx_cq_moderation_pkts));
2048 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2056 err = mlx5e_refresh_rq_params(priv, &c->rq);
2060 for (i = 0; i != c->num_tc; i++) {
2061 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2070 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2074 if (priv->channel == NULL)
2077 for (i = 0; i < priv->params.num_channels; i++) {
2080 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
2088 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2090 struct mlx5_core_dev *mdev = priv->mdev;
2091 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2092 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2094 memset(in, 0, sizeof(in));
2096 MLX5_SET(tisc, tisc, prio, tc);
2097 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2099 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2103 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2105 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2109 mlx5e_open_tises(struct mlx5e_priv *priv)
2111 int num_tc = priv->num_tc;
2115 for (tc = 0; tc < num_tc; tc++) {
2116 err = mlx5e_open_tis(priv, tc);
2118 goto err_close_tises;
2124 for (tc--; tc >= 0; tc--)
2125 mlx5e_close_tis(priv, tc);
2131 mlx5e_close_tises(struct mlx5e_priv *priv)
2133 int num_tc = priv->num_tc;
2136 for (tc = 0; tc < num_tc; tc++)
2137 mlx5e_close_tis(priv, tc);
2141 mlx5e_open_rqt(struct mlx5e_priv *priv)
2143 struct mlx5_core_dev *mdev = priv->mdev;
2145 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2152 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2154 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2155 in = mlx5_vzalloc(inlen);
2158 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2160 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2161 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2163 for (i = 0; i < sz; i++) {
2166 ix = rss_get_indirection_to_bucket(i);
2170 /* ensure we don't overflow */
2171 ix %= priv->params.num_channels;
2172 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2175 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2177 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2179 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2187 mlx5e_close_rqt(struct mlx5e_priv *priv)
2189 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2190 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2192 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2193 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2195 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2199 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2201 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2204 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2206 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2208 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2209 MLX5_HASH_FIELD_SEL_DST_IP)
2211 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2212 MLX5_HASH_FIELD_SEL_DST_IP |\
2213 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2214 MLX5_HASH_FIELD_SEL_L4_DPORT)
2216 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2217 MLX5_HASH_FIELD_SEL_DST_IP |\
2218 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2220 if (priv->params.hw_lro_en) {
2221 MLX5_SET(tirc, tirc, lro_enable_mask,
2222 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2223 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2224 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2225 (priv->params.lro_wqe_sz -
2226 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2227 /* TODO: add the option to choose timer value dynamically */
2228 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2229 MLX5_CAP_ETH(priv->mdev,
2230 lro_timer_supported_periods[2]));
2233 /* setup parameters for hashing TIR type, if any */
2236 MLX5_SET(tirc, tirc, disp_type,
2237 MLX5_TIRC_DISP_TYPE_DIRECT);
2238 MLX5_SET(tirc, tirc, inline_rqn,
2239 priv->channel[0]->rq.rqn);
2242 MLX5_SET(tirc, tirc, disp_type,
2243 MLX5_TIRC_DISP_TYPE_INDIRECT);
2244 MLX5_SET(tirc, tirc, indirect_table,
2246 MLX5_SET(tirc, tirc, rx_hash_fn,
2247 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2248 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2251 * The FreeBSD RSS implementation does currently not
2252 * support symmetric Toeplitz hashes:
2254 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2255 rss_getkey((uint8_t *)hkey);
2257 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2258 hkey[0] = cpu_to_be32(0xD181C62C);
2259 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2260 hkey[2] = cpu_to_be32(0x1983A2FC);
2261 hkey[3] = cpu_to_be32(0x943E1ADB);
2262 hkey[4] = cpu_to_be32(0xD9389E6B);
2263 hkey[5] = cpu_to_be32(0xD1039C2C);
2264 hkey[6] = cpu_to_be32(0xA74499AD);
2265 hkey[7] = cpu_to_be32(0x593D56D9);
2266 hkey[8] = cpu_to_be32(0xF3253C06);
2267 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2273 case MLX5E_TT_IPV4_TCP:
2274 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2275 MLX5_L3_PROT_TYPE_IPV4);
2276 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2277 MLX5_L4_PROT_TYPE_TCP);
2279 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2280 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2284 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2288 case MLX5E_TT_IPV6_TCP:
2289 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2290 MLX5_L3_PROT_TYPE_IPV6);
2291 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2292 MLX5_L4_PROT_TYPE_TCP);
2294 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2295 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2299 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2303 case MLX5E_TT_IPV4_UDP:
2304 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2305 MLX5_L3_PROT_TYPE_IPV4);
2306 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2307 MLX5_L4_PROT_TYPE_UDP);
2309 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2310 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2314 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2318 case MLX5E_TT_IPV6_UDP:
2319 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2320 MLX5_L3_PROT_TYPE_IPV6);
2321 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2322 MLX5_L4_PROT_TYPE_UDP);
2324 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2325 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2329 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2333 case MLX5E_TT_IPV4_IPSEC_AH:
2334 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2335 MLX5_L3_PROT_TYPE_IPV4);
2336 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2337 MLX5_HASH_IP_IPSEC_SPI);
2340 case MLX5E_TT_IPV6_IPSEC_AH:
2341 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2342 MLX5_L3_PROT_TYPE_IPV6);
2343 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2344 MLX5_HASH_IP_IPSEC_SPI);
2347 case MLX5E_TT_IPV4_IPSEC_ESP:
2348 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2349 MLX5_L3_PROT_TYPE_IPV4);
2350 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2351 MLX5_HASH_IP_IPSEC_SPI);
2354 case MLX5E_TT_IPV6_IPSEC_ESP:
2355 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2356 MLX5_L3_PROT_TYPE_IPV6);
2357 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2358 MLX5_HASH_IP_IPSEC_SPI);
2362 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2363 MLX5_L3_PROT_TYPE_IPV4);
2364 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2369 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2370 MLX5_L3_PROT_TYPE_IPV6);
2371 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2381 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2383 struct mlx5_core_dev *mdev = priv->mdev;
2389 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2390 in = mlx5_vzalloc(inlen);
2393 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2395 mlx5e_build_tir_ctx(priv, tirc, tt);
2397 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2405 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2407 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2411 mlx5e_open_tirs(struct mlx5e_priv *priv)
2416 for (i = 0; i < MLX5E_NUM_TT; i++) {
2417 err = mlx5e_open_tir(priv, i);
2419 goto err_close_tirs;
2425 for (i--; i >= 0; i--)
2426 mlx5e_close_tir(priv, i);
2432 mlx5e_close_tirs(struct mlx5e_priv *priv)
2436 for (i = 0; i < MLX5E_NUM_TT; i++)
2437 mlx5e_close_tir(priv, i);
2441 * SW MTU does not include headers,
2442 * HW MTU includes all headers and checksums.
2445 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2447 struct mlx5e_priv *priv = ifp->if_softc;
2448 struct mlx5_core_dev *mdev = priv->mdev;
2452 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2454 err = mlx5_set_port_mtu(mdev, hw_mtu);
2456 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2457 __func__, sw_mtu, err);
2461 /* Update vport context MTU */
2462 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2464 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2468 ifp->if_mtu = sw_mtu;
2470 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2471 if (err || !hw_mtu) {
2472 /* fallback to port oper mtu */
2473 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2476 if_printf(ifp, "Query port MTU, after setting new "
2477 "MTU value, failed\n");
2479 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2481 if_printf(ifp, "Port MTU %d is smaller than "
2482 "ifp mtu %d\n", hw_mtu, sw_mtu);
2483 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2485 if_printf(ifp, "Port MTU %d is bigger than "
2486 "ifp mtu %d\n", hw_mtu, sw_mtu);
2488 priv->params_ethtool.hw_mtu = hw_mtu;
2494 mlx5e_open_locked(struct ifnet *ifp)
2496 struct mlx5e_priv *priv = ifp->if_softc;
2500 /* check if already opened */
2501 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2505 if (rss_getnumbuckets() > priv->params.num_channels) {
2506 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2507 "channels(%u) available\n", rss_getnumbuckets(),
2508 priv->params.num_channels);
2511 err = mlx5e_open_tises(priv);
2513 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2517 err = mlx5_vport_alloc_q_counter(priv->mdev,
2518 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2520 if_printf(priv->ifp,
2521 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2523 goto err_close_tises;
2525 /* store counter set ID */
2526 priv->counter_set_id = set_id;
2528 err = mlx5e_open_channels(priv);
2530 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2532 goto err_dalloc_q_counter;
2534 err = mlx5e_open_rqt(priv);
2536 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2538 goto err_close_channels;
2540 err = mlx5e_open_tirs(priv);
2542 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2544 goto err_close_rqls;
2546 err = mlx5e_open_flow_table(priv);
2548 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2550 goto err_close_tirs;
2552 err = mlx5e_add_all_vlan_rules(priv);
2554 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2556 goto err_close_flow_table;
2558 set_bit(MLX5E_STATE_OPENED, &priv->state);
2560 mlx5e_update_carrier(priv);
2561 mlx5e_set_rx_mode_core(priv);
2565 err_close_flow_table:
2566 mlx5e_close_flow_table(priv);
2569 mlx5e_close_tirs(priv);
2572 mlx5e_close_rqt(priv);
2575 mlx5e_close_channels(priv);
2577 err_dalloc_q_counter:
2578 mlx5_vport_dealloc_q_counter(priv->mdev,
2579 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2582 mlx5e_close_tises(priv);
2588 mlx5e_open(void *arg)
2590 struct mlx5e_priv *priv = arg;
2593 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2594 if_printf(priv->ifp,
2595 "%s: Setting port status to up failed\n",
2598 mlx5e_open_locked(priv->ifp);
2599 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2604 mlx5e_close_locked(struct ifnet *ifp)
2606 struct mlx5e_priv *priv = ifp->if_softc;
2608 /* check if already closed */
2609 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2612 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2614 mlx5e_set_rx_mode_core(priv);
2615 mlx5e_del_all_vlan_rules(priv);
2616 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2617 mlx5e_close_flow_table(priv);
2618 mlx5e_close_tirs(priv);
2619 mlx5e_close_rqt(priv);
2620 mlx5e_close_channels(priv);
2621 mlx5_vport_dealloc_q_counter(priv->mdev,
2622 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2623 mlx5e_close_tises(priv);
2628 #if (__FreeBSD_version >= 1100000)
2630 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2632 struct mlx5e_priv *priv = ifp->if_softc;
2635 /* PRIV_LOCK(priv); XXX not allowed */
2637 case IFCOUNTER_IPACKETS:
2638 retval = priv->stats.vport.rx_packets;
2640 case IFCOUNTER_IERRORS:
2641 retval = priv->stats.vport.rx_error_packets +
2642 priv->stats.pport.alignment_err +
2643 priv->stats.pport.check_seq_err +
2644 priv->stats.pport.crc_align_errors +
2645 priv->stats.pport.in_range_len_errors +
2646 priv->stats.pport.jabbers +
2647 priv->stats.pport.out_of_range_len +
2648 priv->stats.pport.oversize_pkts +
2649 priv->stats.pport.symbol_err +
2650 priv->stats.pport.too_long_errors +
2651 priv->stats.pport.undersize_pkts +
2652 priv->stats.pport.unsupported_op_rx;
2654 case IFCOUNTER_IQDROPS:
2655 retval = priv->stats.vport.rx_out_of_buffer +
2656 priv->stats.pport.drop_events;
2658 case IFCOUNTER_OPACKETS:
2659 retval = priv->stats.vport.tx_packets;
2661 case IFCOUNTER_OERRORS:
2662 retval = priv->stats.vport.tx_error_packets;
2664 case IFCOUNTER_IBYTES:
2665 retval = priv->stats.vport.rx_bytes;
2667 case IFCOUNTER_OBYTES:
2668 retval = priv->stats.vport.tx_bytes;
2670 case IFCOUNTER_IMCASTS:
2671 retval = priv->stats.vport.rx_multicast_packets;
2673 case IFCOUNTER_OMCASTS:
2674 retval = priv->stats.vport.tx_multicast_packets;
2676 case IFCOUNTER_OQDROPS:
2677 retval = priv->stats.vport.tx_queue_dropped;
2679 case IFCOUNTER_COLLISIONS:
2680 retval = priv->stats.pport.collisions;
2683 retval = if_get_counter_default(ifp, cnt);
2686 /* PRIV_UNLOCK(priv); XXX not allowed */
2692 mlx5e_set_rx_mode(struct ifnet *ifp)
2694 struct mlx5e_priv *priv = ifp->if_softc;
2696 queue_work(priv->wq, &priv->set_rx_mode_work);
2700 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2702 struct mlx5e_priv *priv;
2704 struct ifi2creq i2c;
2713 priv = ifp->if_softc;
2715 /* check if detaching */
2716 if (priv == NULL || priv->gone != 0)
2721 ifr = (struct ifreq *)data;
2724 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2726 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2727 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2730 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2732 mlx5e_close_locked(ifp);
2735 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2738 mlx5e_open_locked(ifp);
2741 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2742 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2747 if ((ifp->if_flags & IFF_UP) &&
2748 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2749 mlx5e_set_rx_mode(ifp);
2753 if (ifp->if_flags & IFF_UP) {
2754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2755 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2756 mlx5e_open_locked(ifp);
2757 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2758 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2761 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2762 mlx5_set_port_status(priv->mdev,
2764 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2765 mlx5e_close_locked(ifp);
2766 mlx5e_update_carrier(priv);
2767 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2774 mlx5e_set_rx_mode(ifp);
2779 ifr = (struct ifreq *)data;
2780 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2783 ifr = (struct ifreq *)data;
2785 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2787 if (mask & IFCAP_TXCSUM) {
2788 ifp->if_capenable ^= IFCAP_TXCSUM;
2789 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2791 if (IFCAP_TSO4 & ifp->if_capenable &&
2792 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2793 ifp->if_capenable &= ~IFCAP_TSO4;
2794 ifp->if_hwassist &= ~CSUM_IP_TSO;
2796 "tso4 disabled due to -txcsum.\n");
2799 if (mask & IFCAP_TXCSUM_IPV6) {
2800 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2801 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2803 if (IFCAP_TSO6 & ifp->if_capenable &&
2804 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2805 ifp->if_capenable &= ~IFCAP_TSO6;
2806 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2808 "tso6 disabled due to -txcsum6.\n");
2811 if (mask & IFCAP_RXCSUM)
2812 ifp->if_capenable ^= IFCAP_RXCSUM;
2813 if (mask & IFCAP_RXCSUM_IPV6)
2814 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2815 if (mask & IFCAP_TSO4) {
2816 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2817 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2818 if_printf(ifp, "enable txcsum first.\n");
2822 ifp->if_capenable ^= IFCAP_TSO4;
2823 ifp->if_hwassist ^= CSUM_IP_TSO;
2825 if (mask & IFCAP_TSO6) {
2826 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2827 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2828 if_printf(ifp, "enable txcsum6 first.\n");
2832 ifp->if_capenable ^= IFCAP_TSO6;
2833 ifp->if_hwassist ^= CSUM_IP6_TSO;
2835 if (mask & IFCAP_VLAN_HWFILTER) {
2836 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2837 mlx5e_disable_vlan_filter(priv);
2839 mlx5e_enable_vlan_filter(priv);
2841 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2843 if (mask & IFCAP_VLAN_HWTAGGING)
2844 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2845 if (mask & IFCAP_WOL_MAGIC)
2846 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2848 VLAN_CAPABILITIES(ifp);
2849 /* turn off LRO means also turn of HW LRO - if it's on */
2850 if (mask & IFCAP_LRO) {
2851 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2852 bool need_restart = false;
2854 ifp->if_capenable ^= IFCAP_LRO;
2855 if (!(ifp->if_capenable & IFCAP_LRO)) {
2856 if (priv->params.hw_lro_en) {
2857 priv->params.hw_lro_en = false;
2858 need_restart = true;
2859 /* Not sure this is the correct way */
2860 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2863 if (was_opened && need_restart) {
2864 mlx5e_close_locked(ifp);
2865 mlx5e_open_locked(ifp);
2868 if (mask & IFCAP_HWRXTSTMP) {
2869 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2870 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
2871 if (priv->clbr_done == 0)
2872 mlx5e_reset_calibration_callout(priv);
2874 callout_drain(&priv->tstmp_clbr);
2875 priv->clbr_done = 0;
2883 ifr = (struct ifreq *)data;
2886 * Copy from the user-space address ifr_data to the
2887 * kernel-space address i2c
2889 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2893 if (i2c.len > sizeof(i2c.data)) {
2899 /* Get module_num which is required for the query_eeprom */
2900 error = mlx5_query_module_num(priv->mdev, &module_num);
2902 if_printf(ifp, "Query module num failed, eeprom "
2903 "reading is not supported\n");
2907 /* Check if module is present before doing an access */
2908 module_status = mlx5_query_module_status(priv->mdev, module_num);
2909 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2910 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2915 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2916 * The internal conversion is as follows:
2918 if (i2c.dev_addr == 0xA0)
2919 read_addr = MLX5E_I2C_ADDR_LOW;
2920 else if (i2c.dev_addr == 0xA2)
2921 read_addr = MLX5E_I2C_ADDR_HIGH;
2923 if_printf(ifp, "Query eeprom failed, "
2924 "Invalid Address: %X\n", i2c.dev_addr);
2928 error = mlx5_query_eeprom(priv->mdev,
2929 read_addr, MLX5E_EEPROM_LOW_PAGE,
2930 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2931 (uint32_t *)i2c.data, &size_read);
2933 if_printf(ifp, "Query eeprom failed, eeprom "
2934 "reading is not supported\n");
2939 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2940 error = mlx5_query_eeprom(priv->mdev,
2941 read_addr, MLX5E_EEPROM_LOW_PAGE,
2942 (uint32_t)(i2c.offset + size_read),
2943 (uint32_t)(i2c.len - size_read), module_num,
2944 (uint32_t *)(i2c.data + size_read), &size_read);
2947 if_printf(ifp, "Query eeprom failed, eeprom "
2948 "reading is not supported\n");
2953 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2959 error = ether_ioctl(ifp, command, data);
2966 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2969 * TODO: uncoment once FW really sets all these bits if
2970 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2971 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2972 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2976 /* TODO: add more must-to-have features */
2978 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2985 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2986 struct mlx5e_priv *priv,
2987 int num_comp_vectors)
2990 * TODO: Consider link speed for setting "log_sq_size",
2991 * "log_rq_size" and "cq_moderation_xxx":
2993 priv->params.log_sq_size =
2994 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2995 priv->params.log_rq_size =
2996 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2997 priv->params.rx_cq_moderation_usec =
2998 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2999 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3000 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3001 priv->params.rx_cq_moderation_mode =
3002 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3003 priv->params.rx_cq_moderation_pkts =
3004 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3005 priv->params.tx_cq_moderation_usec =
3006 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3007 priv->params.tx_cq_moderation_pkts =
3008 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3009 priv->params.min_rx_wqes =
3010 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3011 priv->params.rx_hash_log_tbl_sz =
3012 (order_base_2(num_comp_vectors) >
3013 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3014 order_base_2(num_comp_vectors) :
3015 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3016 priv->params.num_tc = 1;
3017 priv->params.default_vlan_prio = 0;
3018 priv->counter_set_id = -1;
3021 * hw lro is currently defaulted to off. when it won't anymore we
3022 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3024 priv->params.hw_lro_en = false;
3025 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3027 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3030 priv->params.num_channels = num_comp_vectors;
3031 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3032 priv->queue_mapping_channel_mask =
3033 roundup_pow_of_two(num_comp_vectors) - 1;
3034 priv->num_tc = priv->params.num_tc;
3035 priv->default_vlan_prio = priv->params.default_vlan_prio;
3037 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3038 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3039 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3043 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3044 struct mlx5_core_mr *mkey)
3046 struct ifnet *ifp = priv->ifp;
3047 struct mlx5_core_dev *mdev = priv->mdev;
3048 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3053 in = mlx5_vzalloc(inlen);
3055 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3059 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3060 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3061 MLX5_SET(mkc, mkc, lw, 1);
3062 MLX5_SET(mkc, mkc, lr, 1);
3064 MLX5_SET(mkc, mkc, pd, pdn);
3065 MLX5_SET(mkc, mkc, length64, 1);
3066 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3068 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3070 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3077 static const char *mlx5e_vport_stats_desc[] = {
3078 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3081 static const char *mlx5e_pport_stats_desc[] = {
3082 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3086 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3088 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3089 sx_init(&priv->state_lock, "mlx5state");
3090 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3091 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3095 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3097 mtx_destroy(&priv->async_events_mtx);
3098 sx_destroy(&priv->state_lock);
3102 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3105 * %d.%d%.d the string format.
3106 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3107 * We need at most 5 chars to store that.
3108 * It also has: two "." and NULL at the end, which means we need 18
3109 * (5*3 + 3) chars at most.
3112 struct mlx5e_priv *priv = arg1;
3115 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3116 fw_rev_sub(priv->mdev));
3117 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3122 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3126 for (i = 0; i < ch->num_tc; i++)
3127 mlx5e_drain_sq(&ch->sq[i]);
3131 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3134 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3135 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3136 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3137 sq->doorbell.d64 = 0;
3141 mlx5e_resume_sq(struct mlx5e_sq *sq)
3145 /* check if already enabled */
3146 if (sq->stopped == 0)
3149 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3150 MLX5_SQC_STATE_RST);
3153 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3159 /* reset doorbell prior to moving from RST to RDY */
3160 mlx5e_reset_sq_doorbell_record(sq);
3162 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3163 MLX5_SQC_STATE_RDY);
3166 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3169 mtx_lock(&sq->lock);
3170 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3172 mtx_unlock(&sq->lock);
3177 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3181 for (i = 0; i < ch->num_tc; i++)
3182 mlx5e_resume_sq(&ch->sq[i]);
3186 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3188 struct mlx5e_rq *rq = &ch->rq;
3193 callout_stop(&rq->watchdog);
3194 mtx_unlock(&rq->mtx);
3196 callout_drain(&rq->watchdog);
3198 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3201 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3204 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3206 rq->cq.mcq.comp(&rq->cq.mcq);
3210 * Transitioning into RST state will allow the FW to track less ERR state queues,
3211 * thus reducing the recv queue flushing time
3213 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3216 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3221 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3223 struct mlx5e_rq *rq = &ch->rq;
3227 mlx5_wq_ll_update_db_record(&rq->wq);
3228 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3231 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3236 rq->cq.mcq.comp(&rq->cq.mcq);
3240 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3244 if (priv->channel == NULL)
3247 for (i = 0; i < priv->params.num_channels; i++) {
3249 if (!priv->channel[i])
3253 mlx5e_disable_tx_dma(priv->channel[i]);
3255 mlx5e_enable_tx_dma(priv->channel[i]);
3260 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3264 if (priv->channel == NULL)
3267 for (i = 0; i < priv->params.num_channels; i++) {
3269 if (!priv->channel[i])
3273 mlx5e_disable_rx_dma(priv->channel[i]);
3275 mlx5e_enable_rx_dma(priv->channel[i]);
3280 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3282 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3283 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3284 sysctl_firmware, "A", "HCA firmware version");
3286 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3287 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3292 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3294 struct mlx5e_priv *priv = arg1;
3301 tx_pfc = priv->params.tx_priority_flow_control;
3303 /* get current value */
3304 value = (tx_pfc >> arg2) & 1;
3306 error = sysctl_handle_32(oidp, &value, 0, req);
3308 /* range check value */
3310 priv->params.tx_priority_flow_control |= (1 << arg2);
3312 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3314 /* check if update is required */
3315 if (error == 0 && priv->gone == 0 &&
3316 tx_pfc != priv->params.tx_priority_flow_control) {
3317 error = -mlx5e_set_port_pfc(priv);
3318 /* restore previous value */
3320 priv->params.tx_priority_flow_control= tx_pfc;
3328 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3330 struct mlx5e_priv *priv = arg1;
3337 rx_pfc = priv->params.rx_priority_flow_control;
3339 /* get current value */
3340 value = (rx_pfc >> arg2) & 1;
3342 error = sysctl_handle_32(oidp, &value, 0, req);
3344 /* range check value */
3346 priv->params.rx_priority_flow_control |= (1 << arg2);
3348 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3350 /* check if update is required */
3351 if (error == 0 && priv->gone == 0 &&
3352 rx_pfc != priv->params.rx_priority_flow_control) {
3353 error = -mlx5e_set_port_pfc(priv);
3354 /* restore previous value */
3356 priv->params.rx_priority_flow_control= rx_pfc;
3364 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3370 /* Only receiving pauseframes is enabled by default */
3371 priv->params.tx_pauseframe_control = 0;
3372 priv->params.rx_pauseframe_control = 1;
3374 /* disable ports flow control, PFC, by default */
3375 priv->params.tx_priority_flow_control = 0;
3376 priv->params.rx_priority_flow_control = 0;
3378 #if (__FreeBSD_version < 1100000)
3379 /* compute path for sysctl */
3380 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3381 device_get_unit(priv->mdev->pdev->dev.bsddev));
3383 /* try to fetch tunable, if any */
3384 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3386 /* compute path for sysctl */
3387 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3388 device_get_unit(priv->mdev->pdev->dev.bsddev));
3390 /* try to fetch tunable, if any */
3391 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3393 for (x = 0; x != 8; x++) {
3395 /* compute path for sysctl */
3396 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3397 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3399 /* try to fetch tunable, if any */
3400 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3401 priv->params.tx_priority_flow_control |= 1 << x;
3403 /* compute path for sysctl */
3404 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3405 device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3407 /* try to fetch tunable, if any */
3408 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3409 priv->params.rx_priority_flow_control |= 1 << x;
3413 /* register pauseframe SYSCTLs */
3414 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3415 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3416 &priv->params.tx_pauseframe_control, 0,
3417 "Set to enable TX pause frames. Clear to disable.");
3419 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3420 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3421 &priv->params.rx_pauseframe_control, 0,
3422 "Set to enable RX pause frames. Clear to disable.");
3424 /* register priority_flow control, PFC, SYSCTLs */
3425 for (x = 0; x != 8; x++) {
3426 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3428 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3429 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3430 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3431 "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3433 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3435 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3436 OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3437 CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3438 "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3444 priv->params.tx_pauseframe_control =
3445 priv->params.tx_pauseframe_control ? 1 : 0;
3446 priv->params.rx_pauseframe_control =
3447 priv->params.rx_pauseframe_control ? 1 : 0;
3449 /* update firmware */
3450 error = mlx5e_set_port_pause_and_pfc(priv);
3451 if (error == -EINVAL) {
3452 if_printf(priv->ifp,
3453 "Global pauseframes must be disabled before enabling PFC.\n");
3454 priv->params.rx_priority_flow_control = 0;
3455 priv->params.tx_priority_flow_control = 0;
3457 /* update firmware */
3458 (void) mlx5e_set_port_pause_and_pfc(priv);
3464 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3467 struct mlx5e_priv *priv;
3468 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3469 struct sysctl_oid_list *child;
3470 int ncv = mdev->priv.eq_table.num_comp_vectors;
3476 if (mlx5e_check_required_hca_cap(mdev)) {
3477 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3480 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3481 mlx5e_priv_mtx_init(priv);
3483 ifp = priv->ifp = if_alloc(IFT_ETHER);
3485 mlx5_core_err(mdev, "if_alloc() failed\n");
3488 ifp->if_softc = priv;
3489 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3490 ifp->if_mtu = ETHERMTU;
3491 ifp->if_init = mlx5e_open;
3492 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3493 ifp->if_ioctl = mlx5e_ioctl;
3494 ifp->if_transmit = mlx5e_xmit;
3495 ifp->if_qflush = if_qflush;
3496 #if (__FreeBSD_version >= 1100000)
3497 ifp->if_get_counter = mlx5e_get_counter;
3499 ifp->if_snd.ifq_maxlen = ifqmaxlen;
3501 * Set driver features
3503 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3504 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3505 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3506 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3507 ifp->if_capabilities |= IFCAP_LRO;
3508 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3509 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3511 /* set TSO limits so that we don't have to drop TX packets */
3512 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3513 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3514 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3516 ifp->if_capenable = ifp->if_capabilities;
3517 ifp->if_hwassist = 0;
3518 if (ifp->if_capenable & IFCAP_TSO)
3519 ifp->if_hwassist |= CSUM_TSO;
3520 if (ifp->if_capenable & IFCAP_TXCSUM)
3521 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3522 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3523 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3525 /* ifnet sysctl tree */
3526 sysctl_ctx_init(&priv->sysctl_ctx);
3527 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3528 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3529 if (priv->sysctl_ifnet == NULL) {
3530 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3531 goto err_free_sysctl;
3533 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3534 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3535 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3536 if (priv->sysctl_ifnet == NULL) {
3537 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3538 goto err_free_sysctl;
3541 /* HW sysctl tree */
3542 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3543 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3544 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3545 if (priv->sysctl_hw == NULL) {
3546 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3547 goto err_free_sysctl;
3549 mlx5e_build_ifp_priv(mdev, priv, ncv);
3551 snprintf(unit, sizeof(unit), "mce%u_wq",
3552 device_get_unit(mdev->pdev->dev.bsddev));
3553 priv->wq = alloc_workqueue(unit, 0, 1);
3554 if (priv->wq == NULL) {
3555 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3556 goto err_free_sysctl;
3559 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3561 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3565 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3567 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3569 goto err_unmap_free_uar;
3571 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3573 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3575 goto err_dealloc_pd;
3577 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3579 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3581 goto err_dealloc_transport_domain;
3583 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3585 /* check if we should generate a random MAC address */
3586 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3587 is_zero_ether_addr(dev_addr)) {
3588 random_ether_addr(dev_addr);
3589 if_printf(ifp, "Assigned random MAC address\n");
3592 /* set default MTU */
3593 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3596 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3598 /* Set default media status */
3599 priv->media_status_last = IFM_AVALID;
3600 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3601 IFM_ETH_RXPAUSE | IFM_FDX;
3603 /* setup default pauseframes configuration */
3604 mlx5e_setup_pauseframes(priv);
3606 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3609 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3613 /* Setup supported medias */
3614 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3615 mlx5e_media_change, mlx5e_media_status);
3617 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3618 if (mlx5e_mode_table[i].baudrate == 0)
3620 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3621 ifmedia_add(&priv->media,
3622 mlx5e_mode_table[i].subtype |
3623 IFM_ETHER, 0, NULL);
3624 ifmedia_add(&priv->media,
3625 mlx5e_mode_table[i].subtype |
3626 IFM_ETHER | IFM_FDX |
3627 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3631 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3632 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3633 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3635 /* Set autoselect by default */
3636 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3637 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3638 ether_ifattach(ifp, dev_addr);
3640 /* Register for VLAN events */
3641 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3642 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3643 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3644 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3646 /* Link is down by default */
3647 if_link_state_change(ifp, LINK_STATE_DOWN);
3649 mlx5e_enable_async_events(priv);
3651 mlx5e_add_hw_stats(priv);
3653 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3654 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3655 priv->stats.vport.arg);
3657 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3658 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3659 priv->stats.pport.arg);
3661 mlx5e_create_ethtool(priv);
3663 mtx_lock(&priv->async_events_mtx);
3664 mlx5e_update_stats(priv);
3665 mtx_unlock(&priv->async_events_mtx);
3667 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3668 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3669 &priv->clbr_done, 0,
3670 "RX timestamps calibration state");
3671 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3672 mlx5e_reset_calibration_callout(priv);
3676 err_dealloc_transport_domain:
3677 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3680 mlx5_core_dealloc_pd(mdev, priv->pdn);
3683 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3686 destroy_workqueue(priv->wq);
3689 sysctl_ctx_free(&priv->sysctl_ctx);
3694 mlx5e_priv_mtx_destroy(priv);
3695 free(priv, M_MLX5EN);
3700 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3702 struct mlx5e_priv *priv = vpriv;
3703 struct ifnet *ifp = priv->ifp;
3705 /* don't allow more IOCTLs */
3709 * Clear the device description to avoid use after free,
3710 * because the bsddev is not destroyed when this module is
3713 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3715 /* XXX wait a bit to allow IOCTL handlers to complete */
3718 /* stop watchdog timer */
3719 callout_drain(&priv->watchdog);
3721 callout_drain(&priv->tstmp_clbr);
3723 if (priv->vlan_attach != NULL)
3724 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3725 if (priv->vlan_detach != NULL)
3726 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3728 /* make sure device gets closed */
3730 mlx5e_close_locked(ifp);
3733 /* unregister device */
3734 ifmedia_removeall(&priv->media);
3735 ether_ifdetach(ifp);
3738 /* destroy all remaining sysctl nodes */
3739 if (priv->sysctl_debug)
3740 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3741 sysctl_ctx_free(&priv->stats.vport.ctx);
3742 sysctl_ctx_free(&priv->stats.pport.ctx);
3743 sysctl_ctx_free(&priv->sysctl_ctx);
3745 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3746 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3747 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3748 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3749 mlx5e_disable_async_events(priv);
3750 destroy_workqueue(priv->wq);
3751 mlx5e_priv_mtx_destroy(priv);
3752 free(priv, M_MLX5EN);
3756 mlx5e_get_ifp(void *vpriv)
3758 struct mlx5e_priv *priv = vpriv;
3763 static struct mlx5_interface mlx5e_interface = {
3764 .add = mlx5e_create_ifp,
3765 .remove = mlx5e_destroy_ifp,
3766 .event = mlx5e_async_event,
3767 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3768 .get_dev = mlx5e_get_ifp,
3774 mlx5_register_interface(&mlx5e_interface);
3780 mlx5_unregister_interface(&mlx5e_interface);
3783 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3784 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3786 #if (__FreeBSD_version >= 1100000)
3787 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3789 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3790 MODULE_VERSION(mlx5en, 1);