sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.1"
  35 #endif
  36 #define DRIVER_RELDATE  "April 2019"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 struct media {
  51         u32     subtype;
  52         u64     baudrate;
  53 };
  54
  55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  56
  57         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  58                 .subtype = IFM_1000_CX_SGMII,
  59                 .baudrate = IF_Mbps(1000ULL),
  60         },
  61         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  62                 .subtype = IFM_1000_KX,
  63                 .baudrate = IF_Mbps(1000ULL),
  64         },
  65         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  66                 .subtype = IFM_10G_CX4,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  70                 .subtype = IFM_10G_KX4,
  71                 .baudrate = IF_Gbps(10ULL),
  72         },
  73         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  74                 .subtype = IFM_10G_KR,
  75                 .baudrate = IF_Gbps(10ULL),
  76         },
  77         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  78                 .subtype = IFM_20G_KR2,
  79                 .baudrate = IF_Gbps(20ULL),
  80         },
  81         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  82                 .subtype = IFM_40G_CR4,
  83                 .baudrate = IF_Gbps(40ULL),
  84         },
  85         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  86                 .subtype = IFM_40G_KR4,
  87                 .baudrate = IF_Gbps(40ULL),
  88         },
  89         [MLX5E_56GBASE_R4][MLX5E_R] = {
  90                 .subtype = IFM_56G_R4,
  91                 .baudrate = IF_Gbps(56ULL),
  92         },
  93         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  94                 .subtype = IFM_10G_CR1,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_10GBASE_SR][MLX5E_SR] = {
  98                 .subtype = IFM_10G_SR,
  99                 .baudrate = IF_Gbps(10ULL),
 100         },
 101         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 102                 .subtype = IFM_10G_ER,
 103                 .baudrate = IF_Gbps(10ULL),
 104         },
 105         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 106                 .subtype = IFM_10G_LR,
 107                 .baudrate = IF_Gbps(10ULL),
 108         },
 109         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 110                 .subtype = IFM_40G_SR4,
 111                 .baudrate = IF_Gbps(40ULL),
 112         },
 113         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 114                 .subtype = IFM_40G_LR4,
 115                 .baudrate = IF_Gbps(40ULL),
 116         },
 117         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 118                 .subtype = IFM_40G_ER4,
 119                 .baudrate = IF_Gbps(40ULL),
 120         },
 121         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 122                 .subtype = IFM_100G_CR4,
 123                 .baudrate = IF_Gbps(100ULL),
 124         },
 125         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 126                 .subtype = IFM_100G_SR4,
 127                 .baudrate = IF_Gbps(100ULL),
 128         },
 129         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 130                 .subtype = IFM_100G_KR4,
 131                 .baudrate = IF_Gbps(100ULL),
 132         },
 133         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 134                 .subtype = IFM_100G_LR4,
 135                 .baudrate = IF_Gbps(100ULL),
 136         },
 137         [MLX5E_100BASE_TX][MLX5E_TX] = {
 138                 .subtype = IFM_100_TX,
 139                 .baudrate = IF_Mbps(100ULL),
 140         },
 141         [MLX5E_1000BASE_T][MLX5E_T] = {
 142                 .subtype = IFM_1000_T,
 143                 .baudrate = IF_Mbps(1000ULL),
 144         },
 145         [MLX5E_10GBASE_T][MLX5E_T] = {
 146                 .subtype = IFM_10G_T,
 147                 .baudrate = IF_Gbps(10ULL),
 148         },
 149         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 150                 .subtype = IFM_25G_CR,
 151                 .baudrate = IF_Gbps(25ULL),
 152         },
 153         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 154                 .subtype = IFM_25G_KR,
 155                 .baudrate = IF_Gbps(25ULL),
 156         },
 157         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 158                 .subtype = IFM_25G_SR,
 159                 .baudrate = IF_Gbps(25ULL),
 160         },
 161         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 162                 .subtype = IFM_50G_CR2,
 163                 .baudrate = IF_Gbps(50ULL),
 164         },
 165         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 166                 .subtype = IFM_50G_KR2,
 167                 .baudrate = IF_Gbps(50ULL),
 168         },
 169 };
 170
 171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 172         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 173                 .subtype = IFM_100_SGMII,
 174                 .baudrate = IF_Mbps(100),
 175         },
 176         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 177                 .subtype = IFM_1000_KX,
 178                 .baudrate = IF_Mbps(1000),
 179         },
 180         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 181                 .subtype = IFM_1000_CX_SGMII,
 182                 .baudrate = IF_Mbps(1000),
 183         },
 184         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 185                 .subtype = IFM_1000_CX,
 186                 .baudrate = IF_Mbps(1000),
 187         },
 188         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 189                 .subtype = IFM_1000_LX,
 190                 .baudrate = IF_Mbps(1000),
 191         },
 192         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 193                 .subtype = IFM_1000_SX,
 194                 .baudrate = IF_Mbps(1000),
 195         },
 196         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 197                 .subtype = IFM_1000_T,
 198                 .baudrate = IF_Mbps(1000),
 199         },
 200         [MLX5E_5GBASE_R][MLX5E_T] = {
 201                 .subtype = IFM_5000_T,
 202                 .baudrate = IF_Mbps(5000),
 203         },
 204         [MLX5E_5GBASE_R][MLX5E_KR] = {
 205                 .subtype = IFM_5000_KR,
 206                 .baudrate = IF_Mbps(5000),
 207         },
 208         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 209                 .subtype = IFM_5000_KR1,
 210                 .baudrate = IF_Mbps(5000),
 211         },
 212         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 213                 .subtype = IFM_5000_KR_S,
 214                 .baudrate = IF_Mbps(5000),
 215         },
 216         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 217                 .subtype = IFM_10G_ER,
 218                 .baudrate = IF_Gbps(10ULL),
 219         },
 220         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 221                 .subtype = IFM_10G_KR,
 222                 .baudrate = IF_Gbps(10ULL),
 223         },
 224         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 225                 .subtype = IFM_10G_LR,
 226                 .baudrate = IF_Gbps(10ULL),
 227         },
 228         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 229                 .subtype = IFM_10G_SR,
 230                 .baudrate = IF_Gbps(10ULL),
 231         },
 232         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 233                 .subtype = IFM_10G_T,
 234                 .baudrate = IF_Gbps(10ULL),
 235         },
 236         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 237                 .subtype = IFM_10G_AOC,
 238                 .baudrate = IF_Gbps(10ULL),
 239         },
 240         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 241                 .subtype = IFM_10G_CR1,
 242                 .baudrate = IF_Gbps(10ULL),
 243         },
 244         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 245                 .subtype = IFM_40G_CR4,
 246                 .baudrate = IF_Gbps(40ULL),
 247         },
 248         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 249                 .subtype = IFM_40G_KR4,
 250                 .baudrate = IF_Gbps(40ULL),
 251         },
 252         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 253                 .subtype = IFM_40G_LR4,
 254                 .baudrate = IF_Gbps(40ULL),
 255         },
 256         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 257                 .subtype = IFM_40G_SR4,
 258                 .baudrate = IF_Gbps(40ULL),
 259         },
 260         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 261                 .subtype = IFM_40G_ER4,
 262                 .baudrate = IF_Gbps(40ULL),
 263         },
 264
 265         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 266                 .subtype = IFM_25G_CR,
 267                 .baudrate = IF_Gbps(25ULL),
 268         },
 269         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 270                 .subtype = IFM_25G_KR,
 271                 .baudrate = IF_Gbps(25ULL),
 272         },
 273         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 274                 .subtype = IFM_25G_SR,
 275                 .baudrate = IF_Gbps(25ULL),
 276         },
 277         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 278                 .subtype = IFM_25G_ACC,
 279                 .baudrate = IF_Gbps(25ULL),
 280         },
 281         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 282                 .subtype = IFM_25G_AOC,
 283                 .baudrate = IF_Gbps(25ULL),
 284         },
 285         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 286                 .subtype = IFM_25G_CR1,
 287                 .baudrate = IF_Gbps(25ULL),
 288         },
 289         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 290                 .subtype = IFM_25G_CR_S,
 291                 .baudrate = IF_Gbps(25ULL),
 292         },
 293         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 294                 .subtype = IFM_5000_KR1,
 295                 .baudrate = IF_Gbps(25ULL),
 296         },
 297         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 298                 .subtype = IFM_25G_KR_S,
 299                 .baudrate = IF_Gbps(25ULL),
 300         },
 301         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 302                 .subtype = IFM_25G_LR,
 303                 .baudrate = IF_Gbps(25ULL),
 304         },
 305         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 306                 .subtype = IFM_25G_T,
 307                 .baudrate = IF_Gbps(25ULL),
 308         },
 309         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 310                 .subtype = IFM_50G_CR2,
 311                 .baudrate = IF_Gbps(50ULL),
 312         },
 313         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 314                 .subtype = IFM_50G_KR2,
 315                 .baudrate = IF_Gbps(50ULL),
 316         },
 317         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 318                 .subtype = IFM_50G_SR2,
 319                 .baudrate = IF_Gbps(50ULL),
 320         },
 321         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 322                 .subtype = IFM_50G_LR2,
 323                 .baudrate = IF_Gbps(50ULL),
 324         },
 325         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 326                 .subtype = IFM_50G_LR,
 327                 .baudrate = IF_Gbps(50ULL),
 328         },
 329         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 330                 .subtype = IFM_50G_SR,
 331                 .baudrate = IF_Gbps(50ULL),
 332         },
 333         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 334                 .subtype = IFM_50G_CP,
 335                 .baudrate = IF_Gbps(50ULL),
 336         },
 337         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 338                 .subtype = IFM_50G_FR,
 339                 .baudrate = IF_Gbps(50ULL),
 340         },
 341         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 342                 .subtype = IFM_50G_KR_PAM4,
 343                 .baudrate = IF_Gbps(50ULL),
 344         },
 345         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 346                 .subtype = IFM_100G_CR4,
 347                 .baudrate = IF_Gbps(100ULL),
 348         },
 349         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 350                 .subtype = IFM_100G_KR4,
 351                 .baudrate = IF_Gbps(100ULL),
 352         },
 353         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 354                 .subtype = IFM_100G_LR4,
 355                 .baudrate = IF_Gbps(100ULL),
 356         },
 357         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 358                 .subtype = IFM_100G_SR4,
 359                 .baudrate = IF_Gbps(100ULL),
 360         },
 361         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 362                 .subtype = IFM_100G_SR2,
 363                 .baudrate = IF_Gbps(100ULL),
 364         },
 365         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 366                 .subtype = IFM_100G_CP2,
 367                 .baudrate = IF_Gbps(100ULL),
 368         },
 369         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 370                 .subtype = IFM_100G_KR2_PAM4,
 371                 .baudrate = IF_Gbps(100ULL),
 372         },
 373         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 374                 .subtype = IFM_200G_DR4,
 375                 .baudrate = IF_Gbps(200ULL),
 376         },
 377         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 378                 .subtype = IFM_200G_LR4,
 379                 .baudrate = IF_Gbps(200ULL),
 380         },
 381         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 382                 .subtype = IFM_200G_SR4,
 383                 .baudrate = IF_Gbps(200ULL),
 384         },
 385         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 386                 .subtype = IFM_200G_FR4,
 387                 .baudrate = IF_Gbps(200ULL),
 388         },
 389         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 390                 .subtype = IFM_200G_CR4_PAM4,
 391                 .baudrate = IF_Gbps(200ULL),
 392         },
 393         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 394                 .subtype = IFM_200G_KR4_PAM4,
 395                 .baudrate = IF_Gbps(200ULL),
 396         },
 397 };
 398
 399 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 400
 401 static void
 402 mlx5e_update_carrier(struct mlx5e_priv *priv)
 403 {
 404         struct mlx5_core_dev *mdev = priv->mdev;
 405         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 406         u32 eth_proto_oper;
 407         int error;
 408         u8 port_state;
 409         u8 is_er_type;
 410         u8 i, j;
 411         bool ext;
 412         struct media media_entry = {};
 413
 414         port_state = mlx5_query_vport_state(mdev,
 415             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 416
 417         if (port_state == VPORT_STATE_UP) {
 418                 priv->media_status_last |= IFM_ACTIVE;
 419         } else {
 420                 priv->media_status_last &= ~IFM_ACTIVE;
 421                 priv->media_active_last = IFM_ETHER;
 422                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 423                 return;
 424         }
 425
 426         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 427             MLX5_PTYS_EN, 1);
 428         if (error) {
 429                 priv->media_active_last = IFM_ETHER;
 430                 priv->ifp->if_baudrate = 1;
 431                 if_printf(priv->ifp, "%s: query port ptys failed: "
 432                     "0x%x\n", __func__, error);
 433                 return;
 434         }
 435
 436         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 437         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 438             eth_proto_oper);
 439
 440         i = ilog2(eth_proto_oper);
 441
 442         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 443                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 444                     mlx5e_mode_table[i][j];
 445                 if (media_entry.baudrate != 0)
 446                         break;
 447         }
 448
 449         if (media_entry.subtype == 0) {
 450                 if_printf(priv->ifp, "%s: Could not find operational "
 451                     "media subtype\n", __func__);
 452                 return;
 453         }
 454
 455         switch (media_entry.subtype) {
 456         case IFM_10G_ER:
 457                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 458                 if (error != 0) {
 459                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 460                                   __func__, error);
 461                 }
 462                 if (error != 0 || is_er_type == 0)
 463                         media_entry.subtype = IFM_10G_LR;
 464                 break;
 465         case IFM_40G_LR4:
 466                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 467                 if (error != 0) {
 468                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 469                                   __func__, error);
 470                 }
 471                 if (error == 0 && is_er_type != 0)
 472                         media_entry.subtype = IFM_40G_ER4;
 473                 break;
 474         }
 475         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 476         priv->ifp->if_baudrate = media_entry.baudrate;
 477
 478         if_link_state_change(priv->ifp, LINK_STATE_UP);
 479 }
 480
 481 static void
 482 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 483 {
 484         struct mlx5e_priv *priv = dev->if_softc;
 485
 486         ifmr->ifm_status = priv->media_status_last;
 487         ifmr->ifm_active = priv->media_active_last |
 488             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 489             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 490
 491 }
 492
 493 static u32
 494 mlx5e_find_link_mode(u32 subtype, bool ext)
 495 {
 496         u32 i;
 497         u32 j;
 498         u32 link_mode = 0;
 499         u32 speeds_num = 0;
 500         struct media media_entry = {};
 501
 502         switch (subtype) {
 503         case IFM_10G_LR:
 504                 subtype = IFM_10G_ER;
 505                 break;
 506         case IFM_40G_ER4:
 507                 subtype = IFM_40G_LR4;
 508                 break;
 509         }
 510
 511         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 512             MLX5E_LINK_SPEEDS_NUMBER;
 513
 514         for (i = 0; i != speeds_num; i++) {
 515                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 516                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 517                             mlx5e_mode_table[i][j];
 518                         if (media_entry.baudrate == 0)
 519                                 continue;
 520                         if (media_entry.subtype == subtype) {
 521                                 link_mode |= MLX5E_PROT_MASK(i);
 522                         }
 523                 }
 524         }
 525
 526         return (link_mode);
 527 }
 528
 529 static int
 530 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 531 {
 532         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 533             priv->params.rx_pauseframe_control,
 534             priv->params.tx_pauseframe_control,
 535             priv->params.rx_priority_flow_control,
 536             priv->params.tx_priority_flow_control));
 537 }
 538
 539 static int
 540 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 541 {
 542         int error;
 543
 544         if (priv->gone != 0) {
 545                 error = -ENXIO;
 546         } else if (priv->params.rx_pauseframe_control ||
 547             priv->params.tx_pauseframe_control) {
 548                 if_printf(priv->ifp,
 549                     "Global pauseframes must be disabled before "
 550                     "enabling PFC.\n");
 551                 error = -EINVAL;
 552         } else {
 553                 error = mlx5e_set_port_pause_and_pfc(priv);
 554         }
 555         return (error);
 556 }
 557
 558 static int
 559 mlx5e_media_change(struct ifnet *dev)
 560 {
 561         struct mlx5e_priv *priv = dev->if_softc;
 562         struct mlx5_core_dev *mdev = priv->mdev;
 563         u32 eth_proto_cap;
 564         u32 link_mode;
 565         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 566         int was_opened;
 567         int locked;
 568         int error;
 569         bool ext;
 570
 571         locked = PRIV_LOCKED(priv);
 572         if (!locked)
 573                 PRIV_LOCK(priv);
 574
 575         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 576                 error = EINVAL;
 577                 goto done;
 578         }
 579
 580         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 581             MLX5_PTYS_EN, 1);
 582         if (error != 0) {
 583                 if_printf(dev, "Query port media capability failed\n");
 584                 goto done;
 585         }
 586
 587         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 588         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 589
 590         /* query supported capabilities */
 591         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 592             eth_proto_capability);
 593
 594         /* check for autoselect */
 595         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 596                 link_mode = eth_proto_cap;
 597                 if (link_mode == 0) {
 598                         if_printf(dev, "Port media capability is zero\n");
 599                         error = EINVAL;
 600                         goto done;
 601                 }
 602         } else {
 603                 link_mode = link_mode & eth_proto_cap;
 604                 if (link_mode == 0) {
 605                         if_printf(dev, "Not supported link mode requested\n");
 606                         error = EINVAL;
 607                         goto done;
 608                 }
 609         }
 610         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 611                 /* check if PFC is enabled */
 612                 if (priv->params.rx_priority_flow_control ||
 613                     priv->params.tx_priority_flow_control) {
 614                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 615                         error = EINVAL;
 616                         goto done;
 617                 }
 618         }
 619         /* update pauseframe control bits */
 620         priv->params.rx_pauseframe_control =
 621             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 622         priv->params.tx_pauseframe_control =
 623             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 624
 625         /* check if device is opened */
 626         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 627
 628         /* reconfigure the hardware */
 629         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 630         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 631         error = -mlx5e_set_port_pause_and_pfc(priv);
 632         if (was_opened)
 633                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 634
 635 done:
 636         if (!locked)
 637                 PRIV_UNLOCK(priv);
 638         return (error);
 639 }
 640
 641 static void
 642 mlx5e_update_carrier_work(struct work_struct *work)
 643 {
 644         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 645             update_carrier_work);
 646
 647         PRIV_LOCK(priv);
 648         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 649                 mlx5e_update_carrier(priv);
 650         PRIV_UNLOCK(priv);
 651 }
 652
 653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 654         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 655
 656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 657         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 658
 659 static void
 660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 661 {
 662         struct mlx5_core_dev *mdev = priv->mdev;
 663         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 664         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 665         void *out;
 666         void *in;
 667         int err;
 668
 669         /* allocate firmware request structures */
 670         in = mlx5_vzalloc(sz);
 671         out = mlx5_vzalloc(sz);
 672         if (in == NULL || out == NULL)
 673                 goto free_out;
 674
 675         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 676         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 677         if (err != 0)
 678                 goto free_out;
 679
 680         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 681         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 682
 683         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 684         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 685         if (err != 0)
 686                 goto free_out;
 687
 688         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 689
 690         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 691         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 692         if (err != 0)
 693                 goto free_out;
 694
 695         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697 free_out:
 698         /* free firmware request structures */
 699         kvfree(in);
 700         kvfree(out);
 701 }
 702
 703 /*
 704  * This function reads the physical port counters from the firmware
 705  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 706  * macros. The output is converted from big-endian 64-bit values into
 707  * host endian ones and stored in the "priv->stats.pport" structure.
 708  */
 709 static void
 710 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 711 {
 712         struct mlx5_core_dev *mdev = priv->mdev;
 713         struct mlx5e_pport_stats *s = &priv->stats.pport;
 714         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 715         u32 *in;
 716         u32 *out;
 717         const u64 *ptr;
 718         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 719         unsigned x;
 720         unsigned y;
 721         unsigned z;
 722
 723         /* allocate firmware request structures */
 724         in = mlx5_vzalloc(sz);
 725         out = mlx5_vzalloc(sz);
 726         if (in == NULL || out == NULL)
 727                 goto free_out;
 728
 729         /*
 730          * Get pointer to the 64-bit counter set which is located at a
 731          * fixed offset in the output firmware request structure:
 732          */
 733         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 734
 735         MLX5_SET(ppcnt_reg, in, local_port, 1);
 736
 737         /* read IEEE802_3 counter group using predefined counter layout */
 738         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 739         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 740         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 741              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 742                 s->arg[y] = be64toh(ptr[x]);
 743
 744         /* read RFC2819 counter group using predefined counter layout */
 745         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 746         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 747         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 748                 s->arg[y] = be64toh(ptr[x]);
 749
 750         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 751             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 752                 s_debug->arg[y] = be64toh(ptr[x]);
 753
 754         /* read RFC2863 counter group using predefined counter layout */
 755         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 756         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 757         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 758                 s_debug->arg[y] = be64toh(ptr[x]);
 759
 760         /* read physical layer stats counter group using predefined counter layout */
 761         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 762         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 763         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 764                 s_debug->arg[y] = be64toh(ptr[x]);
 765
 766         /* read Extended Ethernet counter group using predefined counter layout */
 767         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 768         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 769         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 770                 s_debug->arg[y] = be64toh(ptr[x]);
 771
 772         /* read Extended Statistical Group */
 773         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 774             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 775             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 776                 /* read Extended Statistical counter group using predefined counter layout */
 777                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 778                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 779
 780                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 781                         s_debug->arg[y] = be64toh(ptr[x]);
 782         }
 783
 784         /* read PCIE counters */
 785         mlx5e_update_pcie_counters(priv);
 786
 787         /* read per-priority counters */
 788         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 789
 790         /* iterate all the priorities */
 791         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 792                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 793                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 794
 795                 /* read per priority stats counter group using predefined counter layout */
 796                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 797                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 798                         s->arg[y] = be64toh(ptr[x]);
 799         }
 800
 801 free_out:
 802         /* free firmware request structures */
 803         kvfree(in);
 804         kvfree(out);
 805 }
 806
 807 static void
 808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 809 {
 810         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 811         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 812
 813         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 814                 return;
 815
 816         MLX5_SET(query_vnic_env_in, in, opcode,
 817             MLX5_CMD_OP_QUERY_VNIC_ENV);
 818         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 819         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 820
 821         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 822                 return;
 823
 824         priv->stats.vport.rx_steer_missed_packets =
 825             MLX5_GET64(query_vnic_env_out, out,
 826             vport_env.nic_receive_steering_discard);
 827 }
 828
 829 /*
 830  * This function is called regularly to collect all statistics
 831  * counters from the firmware. The values can be viewed through the
 832  * sysctl interface. Execution is serialized using the priv's global
 833  * configuration lock.
 834  */
 835 static void
 836 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 837 {
 838         struct mlx5_core_dev *mdev = priv->mdev;
 839         struct mlx5e_vport_stats *s = &priv->stats.vport;
 840         struct mlx5e_sq_stats *sq_stats;
 841         struct buf_ring *sq_br;
 842 #if (__FreeBSD_version < 1100000)
 843         struct ifnet *ifp = priv->ifp;
 844 #endif
 845
 846         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 847         u32 *out;
 848         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 849         u64 tso_packets = 0;
 850         u64 tso_bytes = 0;
 851         u64 tx_queue_dropped = 0;
 852         u64 tx_defragged = 0;
 853         u64 tx_offload_none = 0;
 854         u64 lro_packets = 0;
 855         u64 lro_bytes = 0;
 856         u64 sw_lro_queued = 0;
 857         u64 sw_lro_flushed = 0;
 858         u64 rx_csum_none = 0;
 859         u64 rx_wqe_err = 0;
 860         u64 rx_packets = 0;
 861         u64 rx_bytes = 0;
 862         u32 rx_out_of_buffer = 0;
 863         int i;
 864         int j;
 865
 866         out = mlx5_vzalloc(outlen);
 867         if (out == NULL)
 868                 goto free_out;
 869
 870         /* Collect firts the SW counters and then HW for consistency */
 871         for (i = 0; i < priv->params.num_channels; i++) {
 872                 struct mlx5e_channel *pch = priv->channel + i;
 873                 struct mlx5e_rq *rq = &pch->rq;
 874                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 875
 876                 /* collect stats from LRO */
 877                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 878                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 879                 sw_lro_queued += rq_stats->sw_lro_queued;
 880                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 881                 lro_packets += rq_stats->lro_packets;
 882                 lro_bytes += rq_stats->lro_bytes;
 883                 rx_csum_none += rq_stats->csum_none;
 884                 rx_wqe_err += rq_stats->wqe_err;
 885                 rx_packets += rq_stats->packets;
 886                 rx_bytes += rq_stats->bytes;
 887
 888                 for (j = 0; j < priv->num_tc; j++) {
 889                         sq_stats = &pch->sq[j].stats;
 890                         sq_br = pch->sq[j].br;
 891
 892                         tso_packets += sq_stats->tso_packets;
 893                         tso_bytes += sq_stats->tso_bytes;
 894                         tx_queue_dropped += sq_stats->dropped;
 895                         if (sq_br != NULL)
 896                                 tx_queue_dropped += sq_br->br_drops;
 897                         tx_defragged += sq_stats->defragged;
 898                         tx_offload_none += sq_stats->csum_offload_none;
 899                 }
 900         }
 901
 902         /* update counters */
 903         s->tso_packets = tso_packets;
 904         s->tso_bytes = tso_bytes;
 905         s->tx_queue_dropped = tx_queue_dropped;
 906         s->tx_defragged = tx_defragged;
 907         s->lro_packets = lro_packets;
 908         s->lro_bytes = lro_bytes;
 909         s->sw_lro_queued = sw_lro_queued;
 910         s->sw_lro_flushed = sw_lro_flushed;
 911         s->rx_csum_none = rx_csum_none;
 912         s->rx_wqe_err = rx_wqe_err;
 913         s->rx_packets = rx_packets;
 914         s->rx_bytes = rx_bytes;
 915
 916         mlx5e_grp_vnic_env_update_stats(priv);
 917
 918         /* HW counters */
 919         memset(in, 0, sizeof(in));
 920
 921         MLX5_SET(query_vport_counter_in, in, opcode,
 922             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 923         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 924         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 925
 926         memset(out, 0, outlen);
 927
 928         /* get number of out-of-buffer drops first */
 929         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 930             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 931             &rx_out_of_buffer) == 0) {
 932                 s->rx_out_of_buffer = rx_out_of_buffer;
 933         }
 934
 935         /* get port statistics */
 936         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 937 #define MLX5_GET_CTR(out, x) \
 938         MLX5_GET64(query_vport_counter_out, out, x)
 939
 940                 s->rx_error_packets =
 941                     MLX5_GET_CTR(out, received_errors.packets);
 942                 s->rx_error_bytes =
 943                     MLX5_GET_CTR(out, received_errors.octets);
 944                 s->tx_error_packets =
 945                     MLX5_GET_CTR(out, transmit_errors.packets);
 946                 s->tx_error_bytes =
 947                     MLX5_GET_CTR(out, transmit_errors.octets);
 948
 949                 s->rx_unicast_packets =
 950                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 951                 s->rx_unicast_bytes =
 952                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 953                 s->tx_unicast_packets =
 954                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 955                 s->tx_unicast_bytes =
 956                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 957
 958                 s->rx_multicast_packets =
 959                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 960                 s->rx_multicast_bytes =
 961                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 962                 s->tx_multicast_packets =
 963                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 964                 s->tx_multicast_bytes =
 965                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 966
 967                 s->rx_broadcast_packets =
 968                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 969                 s->rx_broadcast_bytes =
 970                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 971                 s->tx_broadcast_packets =
 972                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 973                 s->tx_broadcast_bytes =
 974                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 975
 976                 s->tx_packets = s->tx_unicast_packets +
 977                     s->tx_multicast_packets + s->tx_broadcast_packets;
 978                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 979                     s->tx_broadcast_bytes;
 980
 981                 /* Update calculated offload counters */
 982                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 983                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 984         }
 985
 986         /* Get physical port counters */
 987         mlx5e_update_pport_counters(priv);
 988
 989         s->tx_jumbo_packets =
 990             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 991             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 992             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 993             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 994
 995 #if (__FreeBSD_version < 1100000)
 996         /* no get_counters interface in fbsd 10 */
 997         ifp->if_ipackets = s->rx_packets;
 998         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
 999             priv->stats.pport.out_of_range_len +
1000             priv->stats.pport.too_long_errors +
1001             priv->stats.pport.check_seq_err +
1002             priv->stats.pport.alignment_err;
1003         ifp->if_iqdrops = s->rx_out_of_buffer;
1004         ifp->if_opackets = s->tx_packets;
1005         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1006         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1007         ifp->if_ibytes = s->rx_bytes;
1008         ifp->if_obytes = s->tx_bytes;
1009         ifp->if_collisions =
1010             priv->stats.pport.collisions;
1011 #endif
1012
1013 free_out:
1014         kvfree(out);
1015
1016         /* Update diagnostics, if any */
1017         if (priv->params_ethtool.diag_pci_enable ||
1018             priv->params_ethtool.diag_general_enable) {
1019                 int error = mlx5_core_get_diagnostics_full(mdev,
1020                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1021                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1022                 if (error != 0)
1023                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
1024         }
1025 }
1026
1027 static void
1028 mlx5e_update_stats_work(struct work_struct *work)
1029 {
1030         struct mlx5e_priv *priv;
1031
1032         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
1033         PRIV_LOCK(priv);
1034         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1035                 mlx5e_update_stats_locked(priv);
1036         PRIV_UNLOCK(priv);
1037 }
1038
1039 static void
1040 mlx5e_update_stats(void *arg)
1041 {
1042         struct mlx5e_priv *priv = arg;
1043
1044         queue_work(priv->wq, &priv->update_stats_work);
1045
1046         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1047 }
1048
1049 static void
1050 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1051     enum mlx5_dev_event event)
1052 {
1053         switch (event) {
1054         case MLX5_DEV_EVENT_PORT_UP:
1055         case MLX5_DEV_EVENT_PORT_DOWN:
1056                 queue_work(priv->wq, &priv->update_carrier_work);
1057                 break;
1058
1059         default:
1060                 break;
1061         }
1062 }
1063
1064 static void
1065 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1066     enum mlx5_dev_event event, unsigned long param)
1067 {
1068         struct mlx5e_priv *priv = vpriv;
1069
1070         mtx_lock(&priv->async_events_mtx);
1071         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1072                 mlx5e_async_event_sub(priv, event);
1073         mtx_unlock(&priv->async_events_mtx);
1074 }
1075
1076 static void
1077 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1078 {
1079         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1080 }
1081
1082 static void
1083 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1084 {
1085         mtx_lock(&priv->async_events_mtx);
1086         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1087         mtx_unlock(&priv->async_events_mtx);
1088 }
1089
1090 static const char *mlx5e_rq_stats_desc[] = {
1091         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1092 };
1093
1094 static int
1095 mlx5e_create_rq(struct mlx5e_channel *c,
1096     struct mlx5e_rq_param *param,
1097     struct mlx5e_rq *rq)
1098 {
1099         struct mlx5e_priv *priv = c->priv;
1100         struct mlx5_core_dev *mdev = priv->mdev;
1101         char buffer[16];
1102         void *rqc = param->rqc;
1103         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1104         int wq_sz;
1105         int err;
1106         int i;
1107         u32 nsegs, wqe_sz;
1108
1109         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1110         if (err != 0)
1111                 goto done;
1112
1113         /* Create DMA descriptor TAG */
1114         if ((err = -bus_dma_tag_create(
1115             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1116             1,                          /* any alignment */
1117             0,                          /* no boundary */
1118             BUS_SPACE_MAXADDR,          /* lowaddr */
1119             BUS_SPACE_MAXADDR,          /* highaddr */
1120             NULL, NULL,                 /* filter, filterarg */
1121             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1122             nsegs,                      /* nsegments */
1123             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1124             0,                          /* flags */
1125             NULL, NULL,                 /* lockfunc, lockfuncarg */
1126             &rq->dma_tag)))
1127                 goto done;
1128
1129         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1130             &rq->wq_ctrl);
1131         if (err)
1132                 goto err_free_dma_tag;
1133
1134         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1135
1136         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1137         if (err != 0)
1138                 goto err_rq_wq_destroy;
1139
1140         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1141
1142         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
1143         if (err)
1144                 goto err_rq_wq_destroy;
1145
1146         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1147         for (i = 0; i != wq_sz; i++) {
1148                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1149                 int j;
1150
1151                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1152                 if (err != 0) {
1153                         while (i--)
1154                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1155                         goto err_rq_mbuf_free;
1156                 }
1157
1158                 /* set value for constant fields */
1159                 for (j = 0; j < rq->nsegs; j++)
1160                         wqe->data[j].lkey = c->mkey_be;
1161         }
1162
1163         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1164         if (priv->params.rx_cq_moderation_mode < 2) {
1165                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1166         } else {
1167                 void *cqc = container_of(param,
1168                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1169
1170                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1171                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1172                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1173                         break;
1174                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1175                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1176                         break;
1177                 default:
1178                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1179                         break;
1180                 }
1181         }
1182
1183         rq->ifp = c->ifp;
1184         rq->channel = c;
1185         rq->ix = c->ix;
1186
1187         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1188         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1189             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1190             rq->stats.arg);
1191         return (0);
1192
1193 err_rq_mbuf_free:
1194         free(rq->mbuf, M_MLX5EN);
1195         tcp_lro_free(&rq->lro);
1196 err_rq_wq_destroy:
1197         mlx5_wq_destroy(&rq->wq_ctrl);
1198 err_free_dma_tag:
1199         bus_dma_tag_destroy(rq->dma_tag);
1200 done:
1201         return (err);
1202 }
1203
1204 static void
1205 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1206 {
1207         int wq_sz;
1208         int i;
1209
1210         /* destroy all sysctl nodes */
1211         sysctl_ctx_free(&rq->stats.ctx);
1212
1213         /* free leftover LRO packets, if any */
1214         tcp_lro_free(&rq->lro);
1215
1216         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1217         for (i = 0; i != wq_sz; i++) {
1218                 if (rq->mbuf[i].mbuf != NULL) {
1219                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1220                         m_freem(rq->mbuf[i].mbuf);
1221                 }
1222                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1223         }
1224         free(rq->mbuf, M_MLX5EN);
1225         mlx5_wq_destroy(&rq->wq_ctrl);
1226 }
1227
1228 static int
1229 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1230 {
1231         struct mlx5e_channel *c = rq->channel;
1232         struct mlx5e_priv *priv = c->priv;
1233         struct mlx5_core_dev *mdev = priv->mdev;
1234
1235         void *in;
1236         void *rqc;
1237         void *wq;
1238         int inlen;
1239         int err;
1240
1241         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1242             sizeof(u64) * rq->wq_ctrl.buf.npages;
1243         in = mlx5_vzalloc(inlen);
1244         if (in == NULL)
1245                 return (-ENOMEM);
1246
1247         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1248         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1249
1250         memcpy(rqc, param->rqc, sizeof(param->rqc));
1251
1252         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1253         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1254         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1255         if (priv->counter_set_id >= 0)
1256                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1257         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1258             PAGE_SHIFT);
1259         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1260
1261         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1262             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1263
1264         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1265
1266         kvfree(in);
1267
1268         return (err);
1269 }
1270
1271 static int
1272 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1273 {
1274         struct mlx5e_channel *c = rq->channel;
1275         struct mlx5e_priv *priv = c->priv;
1276         struct mlx5_core_dev *mdev = priv->mdev;
1277
1278         void *in;
1279         void *rqc;
1280         int inlen;
1281         int err;
1282
1283         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1284         in = mlx5_vzalloc(inlen);
1285         if (in == NULL)
1286                 return (-ENOMEM);
1287
1288         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1289
1290         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1291         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1292         MLX5_SET(rqc, rqc, state, next_state);
1293
1294         err = mlx5_core_modify_rq(mdev, in, inlen);
1295
1296         kvfree(in);
1297
1298         return (err);
1299 }
1300
1301 static void
1302 mlx5e_disable_rq(struct mlx5e_rq *rq)
1303 {
1304         struct mlx5e_channel *c = rq->channel;
1305         struct mlx5e_priv *priv = c->priv;
1306         struct mlx5_core_dev *mdev = priv->mdev;
1307
1308         mlx5_core_destroy_rq(mdev, rq->rqn);
1309 }
1310
1311 static int
1312 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1313 {
1314         struct mlx5e_channel *c = rq->channel;
1315         struct mlx5e_priv *priv = c->priv;
1316         struct mlx5_wq_ll *wq = &rq->wq;
1317         int i;
1318
1319         for (i = 0; i < 1000; i++) {
1320                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1321                         return (0);
1322
1323                 msleep(4);
1324         }
1325         return (-ETIMEDOUT);
1326 }
1327
1328 static int
1329 mlx5e_open_rq(struct mlx5e_channel *c,
1330     struct mlx5e_rq_param *param,
1331     struct mlx5e_rq *rq)
1332 {
1333         int err;
1334
1335         err = mlx5e_create_rq(c, param, rq);
1336         if (err)
1337                 return (err);
1338
1339         err = mlx5e_enable_rq(rq, param);
1340         if (err)
1341                 goto err_destroy_rq;
1342
1343         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1344         if (err)
1345                 goto err_disable_rq;
1346
1347         c->rq.enabled = 1;
1348
1349         return (0);
1350
1351 err_disable_rq:
1352         mlx5e_disable_rq(rq);
1353 err_destroy_rq:
1354         mlx5e_destroy_rq(rq);
1355
1356         return (err);
1357 }
1358
1359 static void
1360 mlx5e_close_rq(struct mlx5e_rq *rq)
1361 {
1362         mtx_lock(&rq->mtx);
1363         rq->enabled = 0;
1364         callout_stop(&rq->watchdog);
1365         mtx_unlock(&rq->mtx);
1366
1367         callout_drain(&rq->watchdog);
1368
1369         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1370 }
1371
1372 static void
1373 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1374 {
1375
1376         mlx5e_disable_rq(rq);
1377         mlx5e_close_cq(&rq->cq);
1378         cancel_work_sync(&rq->dim.work);
1379         mlx5e_destroy_rq(rq);
1380 }
1381
1382 void
1383 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1384 {
1385         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1386         int x;
1387
1388         for (x = 0; x != wq_sz; x++) {
1389                 if (sq->mbuf[x].mbuf != NULL) {
1390                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1391                         m_freem(sq->mbuf[x].mbuf);
1392                 }
1393                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1394         }
1395         free(sq->mbuf, M_MLX5EN);
1396 }
1397
1398 int
1399 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1400 {
1401         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1402         int err;
1403         int x;
1404
1405         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1406
1407         /* Create DMA descriptor MAPs */
1408         for (x = 0; x != wq_sz; x++) {
1409                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1410                 if (err != 0) {
1411                         while (x--)
1412                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1413                         free(sq->mbuf, M_MLX5EN);
1414                         return (err);
1415                 }
1416         }
1417         return (0);
1418 }
1419
1420 static const char *mlx5e_sq_stats_desc[] = {
1421         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1422 };
1423
1424 void
1425 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1426 {
1427         sq->max_inline = sq->priv->params.tx_max_inline;
1428         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1429
1430         /*
1431          * Check if trust state is DSCP or if inline mode is NONE which
1432          * indicates CX-5 or newer hardware.
1433          */
1434         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1435             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1436                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1437                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1438                 else
1439                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1440         } else {
1441                 sq->min_insert_caps = 0;
1442         }
1443 }
1444
1445 static void
1446 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1447 {
1448         int i;
1449
1450         for (i = 0; i != c->num_tc; i++) {
1451                 mtx_lock(&c->sq[i].lock);
1452                 mlx5e_update_sq_inline(&c->sq[i]);
1453                 mtx_unlock(&c->sq[i].lock);
1454         }
1455 }
1456
1457 void
1458 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1459 {
1460         int i;
1461
1462         /* check if channels are closed */
1463         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1464                 return;
1465
1466         for (i = 0; i < priv->params.num_channels; i++)
1467                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1468 }
1469
1470 static int
1471 mlx5e_create_sq(struct mlx5e_channel *c,
1472     int tc,
1473     struct mlx5e_sq_param *param,
1474     struct mlx5e_sq *sq)
1475 {
1476         struct mlx5e_priv *priv = c->priv;
1477         struct mlx5_core_dev *mdev = priv->mdev;
1478         char buffer[16];
1479         void *sqc = param->sqc;
1480         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1481         int err;
1482
1483         /* Create DMA descriptor TAG */
1484         if ((err = -bus_dma_tag_create(
1485             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1486             1,                          /* any alignment */
1487             0,                          /* no boundary */
1488             BUS_SPACE_MAXADDR,          /* lowaddr */
1489             BUS_SPACE_MAXADDR,          /* highaddr */
1490             NULL, NULL,                 /* filter, filterarg */
1491             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1492             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1493             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1494             0,                          /* flags */
1495             NULL, NULL,                 /* lockfunc, lockfuncarg */
1496             &sq->dma_tag)))
1497                 goto done;
1498
1499         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1500         if (err)
1501                 goto err_free_dma_tag;
1502
1503         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1504             &sq->wq_ctrl);
1505         if (err)
1506                 goto err_unmap_free_uar;
1507
1508         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1509         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1510
1511         err = mlx5e_alloc_sq_db(sq);
1512         if (err)
1513                 goto err_sq_wq_destroy;
1514
1515         sq->mkey_be = c->mkey_be;
1516         sq->ifp = priv->ifp;
1517         sq->priv = priv;
1518         sq->tc = tc;
1519
1520         mlx5e_update_sq_inline(sq);
1521
1522         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1523         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1524             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1525             sq->stats.arg);
1526
1527         return (0);
1528
1529 err_sq_wq_destroy:
1530         mlx5_wq_destroy(&sq->wq_ctrl);
1531
1532 err_unmap_free_uar:
1533         mlx5_unmap_free_uar(mdev, &sq->uar);
1534
1535 err_free_dma_tag:
1536         bus_dma_tag_destroy(sq->dma_tag);
1537 done:
1538         return (err);
1539 }
1540
1541 static void
1542 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1543 {
1544         /* destroy all sysctl nodes */
1545         sysctl_ctx_free(&sq->stats.ctx);
1546
1547         mlx5e_free_sq_db(sq);
1548         mlx5_wq_destroy(&sq->wq_ctrl);
1549         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1550 }
1551
1552 int
1553 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1554     int tis_num)
1555 {
1556         void *in;
1557         void *sqc;
1558         void *wq;
1559         int inlen;
1560         int err;
1561
1562         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1563             sizeof(u64) * sq->wq_ctrl.buf.npages;
1564         in = mlx5_vzalloc(inlen);
1565         if (in == NULL)
1566                 return (-ENOMEM);
1567
1568         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1569         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1570
1571         memcpy(sqc, param->sqc, sizeof(param->sqc));
1572
1573         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1574         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1575         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1576         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1577         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1578
1579         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1580         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1581         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1582             PAGE_SHIFT);
1583         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1584
1585         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1586             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1587
1588         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1589
1590         kvfree(in);
1591
1592         return (err);
1593 }
1594
1595 int
1596 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1597 {
1598         void *in;
1599         void *sqc;
1600         int inlen;
1601         int err;
1602
1603         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1604         in = mlx5_vzalloc(inlen);
1605         if (in == NULL)
1606                 return (-ENOMEM);
1607
1608         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1609
1610         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1611         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1612         MLX5_SET(sqc, sqc, state, next_state);
1613
1614         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1615
1616         kvfree(in);
1617
1618         return (err);
1619 }
1620
1621 void
1622 mlx5e_disable_sq(struct mlx5e_sq *sq)
1623 {
1624
1625         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1626 }
1627
1628 static int
1629 mlx5e_open_sq(struct mlx5e_channel *c,
1630     int tc,
1631     struct mlx5e_sq_param *param,
1632     struct mlx5e_sq *sq)
1633 {
1634         int err;
1635
1636         err = mlx5e_create_sq(c, tc, param, sq);
1637         if (err)
1638                 return (err);
1639
1640         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1641         if (err)
1642                 goto err_destroy_sq;
1643
1644         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1645         if (err)
1646                 goto err_disable_sq;
1647
1648         WRITE_ONCE(sq->running, 1);
1649
1650         return (0);
1651
1652 err_disable_sq:
1653         mlx5e_disable_sq(sq);
1654 err_destroy_sq:
1655         mlx5e_destroy_sq(sq);
1656
1657         return (err);
1658 }
1659
1660 static void
1661 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1662 {
1663         /* fill up remainder with NOPs */
1664         while (sq->cev_counter != 0) {
1665                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1666                         if (can_sleep != 0) {
1667                                 mtx_unlock(&sq->lock);
1668                                 msleep(4);
1669                                 mtx_lock(&sq->lock);
1670                         } else {
1671                                 goto done;
1672                         }
1673                 }
1674                 /* send a single NOP */
1675                 mlx5e_send_nop(sq, 1);
1676                 atomic_thread_fence_rel();
1677         }
1678 done:
1679         /* Check if we need to write the doorbell */
1680         if (likely(sq->doorbell.d64 != 0)) {
1681                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1682                 sq->doorbell.d64 = 0;
1683         }
1684 }
1685
1686 void
1687 mlx5e_sq_cev_timeout(void *arg)
1688 {
1689         struct mlx5e_sq *sq = arg;
1690
1691         mtx_assert(&sq->lock, MA_OWNED);
1692
1693         /* check next state */
1694         switch (sq->cev_next_state) {
1695         case MLX5E_CEV_STATE_SEND_NOPS:
1696                 /* fill TX ring with NOPs, if any */
1697                 mlx5e_sq_send_nops_locked(sq, 0);
1698
1699                 /* check if completed */
1700                 if (sq->cev_counter == 0) {
1701                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1702                         return;
1703                 }
1704                 break;
1705         default:
1706                 /* send NOPs on next timeout */
1707                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1708                 break;
1709         }
1710
1711         /* restart timer */
1712         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1713 }
1714
1715 void
1716 mlx5e_drain_sq(struct mlx5e_sq *sq)
1717 {
1718         int error;
1719         struct mlx5_core_dev *mdev= sq->priv->mdev;
1720
1721         /*
1722          * Check if already stopped.
1723          *
1724          * NOTE: Serialization of this function is managed by the
1725          * caller ensuring the priv's state lock is locked or in case
1726          * of rate limit support, a single thread manages drain and
1727          * resume of SQs. The "running" variable can therefore safely
1728          * be read without any locks.
1729          */
1730         if (READ_ONCE(sq->running) == 0)
1731                 return;
1732
1733         /* don't put more packets into the SQ */
1734         WRITE_ONCE(sq->running, 0);
1735
1736         /* serialize access to DMA rings */
1737         mtx_lock(&sq->lock);
1738
1739         /* teardown event factor timer, if any */
1740         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1741         callout_stop(&sq->cev_callout);
1742
1743         /* send dummy NOPs in order to flush the transmit ring */
1744         mlx5e_sq_send_nops_locked(sq, 1);
1745         mtx_unlock(&sq->lock);
1746
1747         /* make sure it is safe to free the callout */
1748         callout_drain(&sq->cev_callout);
1749
1750         /* wait till SQ is empty or link is down */
1751         mtx_lock(&sq->lock);
1752         while (sq->cc != sq->pc &&
1753             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1754             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1755                 mtx_unlock(&sq->lock);
1756                 msleep(1);
1757                 sq->cq.mcq.comp(&sq->cq.mcq);
1758                 mtx_lock(&sq->lock);
1759         }
1760         mtx_unlock(&sq->lock);
1761
1762         /* error out remaining requests */
1763         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1764         if (error != 0) {
1765                 if_printf(sq->ifp,
1766                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1767         }
1768
1769         /* wait till SQ is empty */
1770         mtx_lock(&sq->lock);
1771         while (sq->cc != sq->pc &&
1772                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1773                 mtx_unlock(&sq->lock);
1774                 msleep(1);
1775                 sq->cq.mcq.comp(&sq->cq.mcq);
1776                 mtx_lock(&sq->lock);
1777         }
1778         mtx_unlock(&sq->lock);
1779 }
1780
1781 static void
1782 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1783 {
1784
1785         mlx5e_drain_sq(sq);
1786         mlx5e_disable_sq(sq);
1787         mlx5e_destroy_sq(sq);
1788 }
1789
1790 static int
1791 mlx5e_create_cq(struct mlx5e_priv *priv,
1792     struct mlx5e_cq_param *param,
1793     struct mlx5e_cq *cq,
1794     mlx5e_cq_comp_t *comp,
1795     int eq_ix)
1796 {
1797         struct mlx5_core_dev *mdev = priv->mdev;
1798         struct mlx5_core_cq *mcq = &cq->mcq;
1799         int eqn_not_used;
1800         int irqn;
1801         int err;
1802         u32 i;
1803
1804         param->wq.buf_numa_node = 0;
1805         param->wq.db_numa_node = 0;
1806
1807         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1808             &cq->wq_ctrl);
1809         if (err)
1810                 return (err);
1811
1812         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1813
1814         mcq->cqe_sz = 64;
1815         mcq->set_ci_db = cq->wq_ctrl.db.db;
1816         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1817         *mcq->set_ci_db = 0;
1818         *mcq->arm_db = 0;
1819         mcq->vector = eq_ix;
1820         mcq->comp = comp;
1821         mcq->event = mlx5e_cq_error_event;
1822         mcq->irqn = irqn;
1823         mcq->uar = &priv->cq_uar;
1824
1825         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1826                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1827
1828                 cqe->op_own = 0xf1;
1829         }
1830
1831         cq->priv = priv;
1832
1833         return (0);
1834 }
1835
1836 static void
1837 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1838 {
1839         mlx5_wq_destroy(&cq->wq_ctrl);
1840 }
1841
1842 static int
1843 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1844 {
1845         struct mlx5_core_cq *mcq = &cq->mcq;
1846         void *in;
1847         void *cqc;
1848         int inlen;
1849         int irqn_not_used;
1850         int eqn;
1851         int err;
1852
1853         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1854             sizeof(u64) * cq->wq_ctrl.buf.npages;
1855         in = mlx5_vzalloc(inlen);
1856         if (in == NULL)
1857                 return (-ENOMEM);
1858
1859         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1860
1861         memcpy(cqc, param->cqc, sizeof(param->cqc));
1862
1863         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1864             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1865
1866         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1867
1868         MLX5_SET(cqc, cqc, c_eqn, eqn);
1869         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1870         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1871             PAGE_SHIFT);
1872         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1873
1874         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1875
1876         kvfree(in);
1877
1878         if (err)
1879                 return (err);
1880
1881         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1882
1883         return (0);
1884 }
1885
1886 static void
1887 mlx5e_disable_cq(struct mlx5e_cq *cq)
1888 {
1889
1890         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1891 }
1892
1893 int
1894 mlx5e_open_cq(struct mlx5e_priv *priv,
1895     struct mlx5e_cq_param *param,
1896     struct mlx5e_cq *cq,
1897     mlx5e_cq_comp_t *comp,
1898     int eq_ix)
1899 {
1900         int err;
1901
1902         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1903         if (err)
1904                 return (err);
1905
1906         err = mlx5e_enable_cq(cq, param, eq_ix);
1907         if (err)
1908                 goto err_destroy_cq;
1909
1910         return (0);
1911
1912 err_destroy_cq:
1913         mlx5e_destroy_cq(cq);
1914
1915         return (err);
1916 }
1917
1918 void
1919 mlx5e_close_cq(struct mlx5e_cq *cq)
1920 {
1921         mlx5e_disable_cq(cq);
1922         mlx5e_destroy_cq(cq);
1923 }
1924
1925 static int
1926 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1927     struct mlx5e_channel_param *cparam)
1928 {
1929         int err;
1930         int tc;
1931
1932         for (tc = 0; tc < c->num_tc; tc++) {
1933                 /* open completion queue */
1934                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1935                     &mlx5e_tx_cq_comp, c->ix);
1936                 if (err)
1937                         goto err_close_tx_cqs;
1938         }
1939         return (0);
1940
1941 err_close_tx_cqs:
1942         for (tc--; tc >= 0; tc--)
1943                 mlx5e_close_cq(&c->sq[tc].cq);
1944
1945         return (err);
1946 }
1947
1948 static void
1949 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1950 {
1951         int tc;
1952
1953         for (tc = 0; tc < c->num_tc; tc++)
1954                 mlx5e_close_cq(&c->sq[tc].cq);
1955 }
1956
1957 static int
1958 mlx5e_open_sqs(struct mlx5e_channel *c,
1959     struct mlx5e_channel_param *cparam)
1960 {
1961         int err;
1962         int tc;
1963
1964         for (tc = 0; tc < c->num_tc; tc++) {
1965                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1966                 if (err)
1967                         goto err_close_sqs;
1968         }
1969
1970         return (0);
1971
1972 err_close_sqs:
1973         for (tc--; tc >= 0; tc--)
1974                 mlx5e_close_sq_wait(&c->sq[tc]);
1975
1976         return (err);
1977 }
1978
1979 static void
1980 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1981 {
1982         int tc;
1983
1984         for (tc = 0; tc < c->num_tc; tc++)
1985                 mlx5e_close_sq_wait(&c->sq[tc]);
1986 }
1987
1988 static void
1989 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1990 {
1991         int tc;
1992
1993         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1994
1995         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1996
1997         for (tc = 0; tc < c->num_tc; tc++) {
1998                 struct mlx5e_sq *sq = c->sq + tc;
1999
2000                 mtx_init(&sq->lock, "mlx5tx",
2001                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2002                 mtx_init(&sq->comp_lock, "mlx5comp",
2003                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2004
2005                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2006
2007                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
2008
2009                 /* ensure the TX completion event factor is not zero */
2010                 if (sq->cev_factor == 0)
2011                         sq->cev_factor = 1;
2012         }
2013 }
2014
2015 static void
2016 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
2017 {
2018         int tc;
2019
2020         mtx_destroy(&c->rq.mtx);
2021
2022         for (tc = 0; tc < c->num_tc; tc++) {
2023                 mtx_destroy(&c->sq[tc].lock);
2024                 mtx_destroy(&c->sq[tc].comp_lock);
2025         }
2026 }
2027
2028 static int
2029 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2030     struct mlx5e_channel_param *cparam,
2031     struct mlx5e_channel *c)
2032 {
2033         int err;
2034
2035         memset(c, 0, sizeof(*c));
2036
2037         c->priv = priv;
2038         c->ix = ix;
2039         c->ifp = priv->ifp;
2040         c->mkey_be = cpu_to_be32(priv->mr.key);
2041         c->num_tc = priv->num_tc;
2042
2043         /* init mutexes */
2044         mlx5e_chan_mtx_init(c);
2045
2046         /* open transmit completion queue */
2047         err = mlx5e_open_tx_cqs(c, cparam);
2048         if (err)
2049                 goto err_free;
2050
2051         /* open receive completion queue */
2052         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2053             &mlx5e_rx_cq_comp, c->ix);
2054         if (err)
2055                 goto err_close_tx_cqs;
2056
2057         err = mlx5e_open_sqs(c, cparam);
2058         if (err)
2059                 goto err_close_rx_cq;
2060
2061         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2062         if (err)
2063                 goto err_close_sqs;
2064
2065         /* poll receive queue initially */
2066         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2067
2068         return (0);
2069
2070 err_close_sqs:
2071         mlx5e_close_sqs_wait(c);
2072
2073 err_close_rx_cq:
2074         mlx5e_close_cq(&c->rq.cq);
2075
2076 err_close_tx_cqs:
2077         mlx5e_close_tx_cqs(c);
2078
2079 err_free:
2080         /* destroy mutexes */
2081         mlx5e_chan_mtx_destroy(c);
2082         return (err);
2083 }
2084
2085 static void
2086 mlx5e_close_channel(struct mlx5e_channel *c)
2087 {
2088         mlx5e_close_rq(&c->rq);
2089 }
2090
2091 static void
2092 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2093 {
2094         mlx5e_close_rq_wait(&c->rq);
2095         mlx5e_close_sqs_wait(c);
2096         mlx5e_close_tx_cqs(c);
2097         /* destroy mutexes */
2098         mlx5e_chan_mtx_destroy(c);
2099 }
2100
2101 static int
2102 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2103 {
2104         u32 r, n;
2105
2106         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2107             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2108         if (r > MJUM16BYTES)
2109                 return (-ENOMEM);
2110
2111         if (r > MJUM9BYTES)
2112                 r = MJUM16BYTES;
2113         else if (r > MJUMPAGESIZE)
2114                 r = MJUM9BYTES;
2115         else if (r > MCLBYTES)
2116                 r = MJUMPAGESIZE;
2117         else
2118                 r = MCLBYTES;
2119
2120         /*
2121          * n + 1 must be a power of two, because stride size must be.
2122          * Stride size is 16 * (n + 1), as the first segment is
2123          * control.
2124          */
2125         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2126                 ;
2127
2128         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2129                 return (-ENOMEM);
2130
2131         *wqe_sz = r;
2132         *nsegs = n;
2133         return (0);
2134 }
2135
2136 static void
2137 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2138     struct mlx5e_rq_param *param)
2139 {
2140         void *rqc = param->rqc;
2141         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2142         u32 wqe_sz, nsegs;
2143
2144         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2145         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2146         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2147         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2148             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2149         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2150         MLX5_SET(wq, wq, pd, priv->pdn);
2151
2152         param->wq.buf_numa_node = 0;
2153         param->wq.db_numa_node = 0;
2154         param->wq.linear = 1;
2155 }
2156
2157 static void
2158 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2159     struct mlx5e_sq_param *param)
2160 {
2161         void *sqc = param->sqc;
2162         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2163
2164         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2165         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2166         MLX5_SET(wq, wq, pd, priv->pdn);
2167
2168         param->wq.buf_numa_node = 0;
2169         param->wq.db_numa_node = 0;
2170         param->wq.linear = 1;
2171 }
2172
2173 static void
2174 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2175     struct mlx5e_cq_param *param)
2176 {
2177         void *cqc = param->cqc;
2178
2179         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2180 }
2181
2182 static void
2183 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2184 {
2185
2186         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2187
2188         /* apply LRO restrictions */
2189         if (priv->params.hw_lro_en &&
2190             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2191                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2192         }
2193 }
2194
2195 static void
2196 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2197     struct mlx5e_cq_param *param)
2198 {
2199         struct net_dim_cq_moder curr;
2200         void *cqc = param->cqc;
2201
2202         /*
2203          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2204          * format is more beneficial for FreeBSD use case.
2205          *
2206          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2207          * in mlx5e_decompress_cqe.
2208          */
2209         if (priv->params.cqe_zipping_en) {
2210                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2211                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2212         }
2213
2214         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2215
2216         switch (priv->params.rx_cq_moderation_mode) {
2217         case 0:
2218                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2219                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2220                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2221                 break;
2222         case 1:
2223                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2224                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2225                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2226                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2227                 else
2228                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2229                 break;
2230         case 2:
2231                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2232                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2233                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2234                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2235                 break;
2236         case 3:
2237                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2238                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2239                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2240                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2241                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2242                 else
2243                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2244                 break;
2245         default:
2246                 break;
2247         }
2248
2249         mlx5e_dim_build_cq_param(priv, param);
2250
2251         mlx5e_build_common_cq_param(priv, param);
2252 }
2253
2254 static void
2255 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2256     struct mlx5e_cq_param *param)
2257 {
2258         void *cqc = param->cqc;
2259
2260         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2261         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2262         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2263
2264         switch (priv->params.tx_cq_moderation_mode) {
2265         case 0:
2266                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2267                 break;
2268         default:
2269                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2270                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2271                 else
2272                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2273                 break;
2274         }
2275
2276         mlx5e_build_common_cq_param(priv, param);
2277 }
2278
2279 static void
2280 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2281     struct mlx5e_channel_param *cparam)
2282 {
2283         memset(cparam, 0, sizeof(*cparam));
2284
2285         mlx5e_build_rq_param(priv, &cparam->rq);
2286         mlx5e_build_sq_param(priv, &cparam->sq);
2287         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2288         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2289 }
2290
2291 static int
2292 mlx5e_open_channels(struct mlx5e_priv *priv)
2293 {
2294         struct mlx5e_channel_param cparam;
2295         int err;
2296         int i;
2297         int j;
2298
2299         mlx5e_build_channel_param(priv, &cparam);
2300         for (i = 0; i < priv->params.num_channels; i++) {
2301                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2302                 if (err)
2303                         goto err_close_channels;
2304         }
2305
2306         for (j = 0; j < priv->params.num_channels; j++) {
2307                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2308                 if (err)
2309                         goto err_close_channels;
2310         }
2311
2312         return (0);
2313
2314 err_close_channels:
2315         while (i--) {
2316                 mlx5e_close_channel(&priv->channel[i]);
2317                 mlx5e_close_channel_wait(&priv->channel[i]);
2318         }
2319         return (err);
2320 }
2321
2322 static void
2323 mlx5e_close_channels(struct mlx5e_priv *priv)
2324 {
2325         int i;
2326
2327         for (i = 0; i < priv->params.num_channels; i++)
2328                 mlx5e_close_channel(&priv->channel[i]);
2329         for (i = 0; i < priv->params.num_channels; i++)
2330                 mlx5e_close_channel_wait(&priv->channel[i]);
2331 }
2332
2333 static int
2334 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2335 {
2336
2337         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2338                 uint8_t cq_mode;
2339
2340                 switch (priv->params.tx_cq_moderation_mode) {
2341                 case 0:
2342                 case 2:
2343                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2344                         break;
2345                 default:
2346                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2347                         break;
2348                 }
2349
2350                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2351                     priv->params.tx_cq_moderation_usec,
2352                     priv->params.tx_cq_moderation_pkts,
2353                     cq_mode));
2354         }
2355
2356         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2357             priv->params.tx_cq_moderation_usec,
2358             priv->params.tx_cq_moderation_pkts));
2359 }
2360
2361 static int
2362 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2363 {
2364
2365         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2366                 uint8_t cq_mode;
2367                 uint8_t dim_mode;
2368                 int retval;
2369
2370                 switch (priv->params.rx_cq_moderation_mode) {
2371                 case 0:
2372                 case 2:
2373                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2374                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2375                         break;
2376                 default:
2377                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2378                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2379                         break;
2380                 }
2381
2382                 /* tear down dynamic interrupt moderation */
2383                 mtx_lock(&rq->mtx);
2384                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2385                 mtx_unlock(&rq->mtx);
2386
2387                 /* wait for dynamic interrupt moderation work task, if any */
2388                 cancel_work_sync(&rq->dim.work);
2389
2390                 if (priv->params.rx_cq_moderation_mode >= 2) {
2391                         struct net_dim_cq_moder curr;
2392
2393                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2394
2395                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2396                             curr.usec, curr.pkts, cq_mode);
2397
2398                         /* set dynamic interrupt moderation mode and zero defaults */
2399                         mtx_lock(&rq->mtx);
2400                         rq->dim.mode = dim_mode;
2401                         rq->dim.state = 0;
2402                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2403                         mtx_unlock(&rq->mtx);
2404                 } else {
2405                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2406                             priv->params.rx_cq_moderation_usec,
2407                             priv->params.rx_cq_moderation_pkts,
2408                             cq_mode);
2409                 }
2410                 return (retval);
2411         }
2412
2413         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2414             priv->params.rx_cq_moderation_usec,
2415             priv->params.rx_cq_moderation_pkts));
2416 }
2417
2418 static int
2419 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2420 {
2421         int err;
2422         int i;
2423
2424         err = mlx5e_refresh_rq_params(priv, &c->rq);
2425         if (err)
2426                 goto done;
2427
2428         for (i = 0; i != c->num_tc; i++) {
2429                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2430                 if (err)
2431                         goto done;
2432         }
2433 done:
2434         return (err);
2435 }
2436
2437 int
2438 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2439 {
2440         int i;
2441
2442         /* check if channels are closed */
2443         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2444                 return (EINVAL);
2445
2446         for (i = 0; i < priv->params.num_channels; i++) {
2447                 int err;
2448
2449                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2450                 if (err)
2451                         return (err);
2452         }
2453         return (0);
2454 }
2455
2456 static int
2457 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2458 {
2459         struct mlx5_core_dev *mdev = priv->mdev;
2460         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2461         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2462
2463         memset(in, 0, sizeof(in));
2464
2465         MLX5_SET(tisc, tisc, prio, tc);
2466         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2467
2468         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2469 }
2470
2471 static void
2472 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2473 {
2474         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2475 }
2476
2477 static int
2478 mlx5e_open_tises(struct mlx5e_priv *priv)
2479 {
2480         int num_tc = priv->num_tc;
2481         int err;
2482         int tc;
2483
2484         for (tc = 0; tc < num_tc; tc++) {
2485                 err = mlx5e_open_tis(priv, tc);
2486                 if (err)
2487                         goto err_close_tises;
2488         }
2489
2490         return (0);
2491
2492 err_close_tises:
2493         for (tc--; tc >= 0; tc--)
2494                 mlx5e_close_tis(priv, tc);
2495
2496         return (err);
2497 }
2498
2499 static void
2500 mlx5e_close_tises(struct mlx5e_priv *priv)
2501 {
2502         int num_tc = priv->num_tc;
2503         int tc;
2504
2505         for (tc = 0; tc < num_tc; tc++)
2506                 mlx5e_close_tis(priv, tc);
2507 }
2508
2509 static int
2510 mlx5e_open_rqt(struct mlx5e_priv *priv)
2511 {
2512         struct mlx5_core_dev *mdev = priv->mdev;
2513         u32 *in;
2514         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2515         void *rqtc;
2516         int inlen;
2517         int err;
2518         int sz;
2519         int i;
2520
2521         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2522
2523         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2524         in = mlx5_vzalloc(inlen);
2525         if (in == NULL)
2526                 return (-ENOMEM);
2527         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2528
2529         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2530         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2531
2532         for (i = 0; i < sz; i++) {
2533                 int ix = i;
2534 #ifdef RSS
2535                 ix = rss_get_indirection_to_bucket(ix);
2536 #endif
2537                 /* ensure we don't overflow */
2538                 ix %= priv->params.num_channels;
2539
2540                 /* apply receive side scaling stride, if any */
2541                 ix -= ix % (int)priv->params.channels_rsss;
2542
2543                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2544         }
2545
2546         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2547
2548         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2549         if (!err)
2550                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2551
2552         kvfree(in);
2553
2554         return (err);
2555 }
2556
2557 static void
2558 mlx5e_close_rqt(struct mlx5e_priv *priv)
2559 {
2560         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2561         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2562
2563         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2564         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2565
2566         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2567 }
2568
2569 static void
2570 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2571 {
2572         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2573         __be32 *hkey;
2574
2575         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2576
2577 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2578
2579 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2580                           MLX5_HASH_FIELD_SEL_DST_IP)
2581
2582 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2583                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2584                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2585                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2586
2587 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2588                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2589                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2590
2591         if (priv->params.hw_lro_en) {
2592                 MLX5_SET(tirc, tirc, lro_enable_mask,
2593                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2594                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2595                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2596                     (priv->params.lro_wqe_sz -
2597                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2598                 /* TODO: add the option to choose timer value dynamically */
2599                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2600                     MLX5_CAP_ETH(priv->mdev,
2601                     lro_timer_supported_periods[2]));
2602         }
2603
2604         /* setup parameters for hashing TIR type, if any */
2605         switch (tt) {
2606         case MLX5E_TT_ANY:
2607                 MLX5_SET(tirc, tirc, disp_type,
2608                     MLX5_TIRC_DISP_TYPE_DIRECT);
2609                 MLX5_SET(tirc, tirc, inline_rqn,
2610                     priv->channel[0].rq.rqn);
2611                 break;
2612         default:
2613                 MLX5_SET(tirc, tirc, disp_type,
2614                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2615                 MLX5_SET(tirc, tirc, indirect_table,
2616                     priv->rqtn);
2617                 MLX5_SET(tirc, tirc, rx_hash_fn,
2618                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2619                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2620 #ifdef RSS
2621                 /*
2622                  * The FreeBSD RSS implementation does currently not
2623                  * support symmetric Toeplitz hashes:
2624                  */
2625                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2626                 rss_getkey((uint8_t *)hkey);
2627 #else
2628                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2629                 hkey[0] = cpu_to_be32(0xD181C62C);
2630                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2631                 hkey[2] = cpu_to_be32(0x1983A2FC);
2632                 hkey[3] = cpu_to_be32(0x943E1ADB);
2633                 hkey[4] = cpu_to_be32(0xD9389E6B);
2634                 hkey[5] = cpu_to_be32(0xD1039C2C);
2635                 hkey[6] = cpu_to_be32(0xA74499AD);
2636                 hkey[7] = cpu_to_be32(0x593D56D9);
2637                 hkey[8] = cpu_to_be32(0xF3253C06);
2638                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2639 #endif
2640                 break;
2641         }
2642
2643         switch (tt) {
2644         case MLX5E_TT_IPV4_TCP:
2645                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2646                     MLX5_L3_PROT_TYPE_IPV4);
2647                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2648                     MLX5_L4_PROT_TYPE_TCP);
2649 #ifdef RSS
2650                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2651                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2652                             MLX5_HASH_IP);
2653                 } else
2654 #endif
2655                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2656                     MLX5_HASH_ALL);
2657                 break;
2658
2659         case MLX5E_TT_IPV6_TCP:
2660                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2661                     MLX5_L3_PROT_TYPE_IPV6);
2662                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2663                     MLX5_L4_PROT_TYPE_TCP);
2664 #ifdef RSS
2665                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2666                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2667                             MLX5_HASH_IP);
2668                 } else
2669 #endif
2670                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671                     MLX5_HASH_ALL);
2672                 break;
2673
2674         case MLX5E_TT_IPV4_UDP:
2675                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676                     MLX5_L3_PROT_TYPE_IPV4);
2677                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2678                     MLX5_L4_PROT_TYPE_UDP);
2679 #ifdef RSS
2680                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2681                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2682                             MLX5_HASH_IP);
2683                 } else
2684 #endif
2685                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2686                     MLX5_HASH_ALL);
2687                 break;
2688
2689         case MLX5E_TT_IPV6_UDP:
2690                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2691                     MLX5_L3_PROT_TYPE_IPV6);
2692                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2693                     MLX5_L4_PROT_TYPE_UDP);
2694 #ifdef RSS
2695                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2696                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2697                             MLX5_HASH_IP);
2698                 } else
2699 #endif
2700                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2701                     MLX5_HASH_ALL);
2702                 break;
2703
2704         case MLX5E_TT_IPV4_IPSEC_AH:
2705                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2706                     MLX5_L3_PROT_TYPE_IPV4);
2707                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2708                     MLX5_HASH_IP_IPSEC_SPI);
2709                 break;
2710
2711         case MLX5E_TT_IPV6_IPSEC_AH:
2712                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2713                     MLX5_L3_PROT_TYPE_IPV6);
2714                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2715                     MLX5_HASH_IP_IPSEC_SPI);
2716                 break;
2717
2718         case MLX5E_TT_IPV4_IPSEC_ESP:
2719                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2720                     MLX5_L3_PROT_TYPE_IPV4);
2721                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2722                     MLX5_HASH_IP_IPSEC_SPI);
2723                 break;
2724
2725         case MLX5E_TT_IPV6_IPSEC_ESP:
2726                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2727                     MLX5_L3_PROT_TYPE_IPV6);
2728                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2729                     MLX5_HASH_IP_IPSEC_SPI);
2730                 break;
2731
2732         case MLX5E_TT_IPV4:
2733                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2734                     MLX5_L3_PROT_TYPE_IPV4);
2735                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2736                     MLX5_HASH_IP);
2737                 break;
2738
2739         case MLX5E_TT_IPV6:
2740                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2741                     MLX5_L3_PROT_TYPE_IPV6);
2742                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2743                     MLX5_HASH_IP);
2744                 break;
2745
2746         default:
2747                 break;
2748         }
2749 }
2750
2751 static int
2752 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2753 {
2754         struct mlx5_core_dev *mdev = priv->mdev;
2755         u32 *in;
2756         void *tirc;
2757         int inlen;
2758         int err;
2759
2760         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2761         in = mlx5_vzalloc(inlen);
2762         if (in == NULL)
2763                 return (-ENOMEM);
2764         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2765
2766         mlx5e_build_tir_ctx(priv, tirc, tt);
2767
2768         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2769
2770         kvfree(in);
2771
2772         return (err);
2773 }
2774
2775 static void
2776 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2777 {
2778         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2779 }
2780
2781 static int
2782 mlx5e_open_tirs(struct mlx5e_priv *priv)
2783 {
2784         int err;
2785         int i;
2786
2787         for (i = 0; i < MLX5E_NUM_TT; i++) {
2788                 err = mlx5e_open_tir(priv, i);
2789                 if (err)
2790                         goto err_close_tirs;
2791         }
2792
2793         return (0);
2794
2795 err_close_tirs:
2796         for (i--; i >= 0; i--)
2797                 mlx5e_close_tir(priv, i);
2798
2799         return (err);
2800 }
2801
2802 static void
2803 mlx5e_close_tirs(struct mlx5e_priv *priv)
2804 {
2805         int i;
2806
2807         for (i = 0; i < MLX5E_NUM_TT; i++)
2808                 mlx5e_close_tir(priv, i);
2809 }
2810
2811 /*
2812  * SW MTU does not include headers,
2813  * HW MTU includes all headers and checksums.
2814  */
2815 static int
2816 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2817 {
2818         struct mlx5e_priv *priv = ifp->if_softc;
2819         struct mlx5_core_dev *mdev = priv->mdev;
2820         int hw_mtu;
2821         int err;
2822
2823         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2824
2825         err = mlx5_set_port_mtu(mdev, hw_mtu);
2826         if (err) {
2827                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2828                     __func__, sw_mtu, err);
2829                 return (err);
2830         }
2831
2832         /* Update vport context MTU */
2833         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2834         if (err) {
2835                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2836                     __func__, err);
2837         }
2838
2839         ifp->if_mtu = sw_mtu;
2840
2841         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2842         if (err || !hw_mtu) {
2843                 /* fallback to port oper mtu */
2844                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2845         }
2846         if (err) {
2847                 if_printf(ifp, "Query port MTU, after setting new "
2848                     "MTU value, failed\n");
2849                 return (err);
2850         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2851                 err = -E2BIG,
2852                 if_printf(ifp, "Port MTU %d is smaller than "
2853                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2854         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2855                 err = -EINVAL;
2856                 if_printf(ifp, "Port MTU %d is bigger than "
2857                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2858         }
2859         priv->params_ethtool.hw_mtu = hw_mtu;
2860
2861         return (err);
2862 }
2863
2864 int
2865 mlx5e_open_locked(struct ifnet *ifp)
2866 {
2867         struct mlx5e_priv *priv = ifp->if_softc;
2868         int err;
2869         u16 set_id;
2870
2871         /* check if already opened */
2872         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2873                 return (0);
2874
2875 #ifdef RSS
2876         if (rss_getnumbuckets() > priv->params.num_channels) {
2877                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2878                     "channels(%u) available\n", rss_getnumbuckets(),
2879                     priv->params.num_channels);
2880         }
2881 #endif
2882         err = mlx5e_open_tises(priv);
2883         if (err) {
2884                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2885                     __func__, err);
2886                 return (err);
2887         }
2888         err = mlx5_vport_alloc_q_counter(priv->mdev,
2889             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2890         if (err) {
2891                 if_printf(priv->ifp,
2892                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2893                     __func__, err);
2894                 goto err_close_tises;
2895         }
2896         /* store counter set ID */
2897         priv->counter_set_id = set_id;
2898
2899         err = mlx5e_open_channels(priv);
2900         if (err) {
2901                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2902                     __func__, err);
2903                 goto err_dalloc_q_counter;
2904         }
2905         err = mlx5e_open_rqt(priv);
2906         if (err) {
2907                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2908                     __func__, err);
2909                 goto err_close_channels;
2910         }
2911         err = mlx5e_open_tirs(priv);
2912         if (err) {
2913                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2914                     __func__, err);
2915                 goto err_close_rqls;
2916         }
2917         err = mlx5e_open_flow_table(priv);
2918         if (err) {
2919                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2920                     __func__, err);
2921                 goto err_close_tirs;
2922         }
2923         err = mlx5e_add_all_vlan_rules(priv);
2924         if (err) {
2925                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2926                     __func__, err);
2927                 goto err_close_flow_table;
2928         }
2929         set_bit(MLX5E_STATE_OPENED, &priv->state);
2930
2931         mlx5e_update_carrier(priv);
2932         mlx5e_set_rx_mode_core(priv);
2933
2934         return (0);
2935
2936 err_close_flow_table:
2937         mlx5e_close_flow_table(priv);
2938
2939 err_close_tirs:
2940         mlx5e_close_tirs(priv);
2941
2942 err_close_rqls:
2943         mlx5e_close_rqt(priv);
2944
2945 err_close_channels:
2946         mlx5e_close_channels(priv);
2947
2948 err_dalloc_q_counter:
2949         mlx5_vport_dealloc_q_counter(priv->mdev,
2950             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2951
2952 err_close_tises:
2953         mlx5e_close_tises(priv);
2954
2955         return (err);
2956 }
2957
2958 static void
2959 mlx5e_open(void *arg)
2960 {
2961         struct mlx5e_priv *priv = arg;
2962
2963         PRIV_LOCK(priv);
2964         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2965                 if_printf(priv->ifp,
2966                     "%s: Setting port status to up failed\n",
2967                     __func__);
2968
2969         mlx5e_open_locked(priv->ifp);
2970         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2971         PRIV_UNLOCK(priv);
2972 }
2973
2974 int
2975 mlx5e_close_locked(struct ifnet *ifp)
2976 {
2977         struct mlx5e_priv *priv = ifp->if_softc;
2978
2979         /* check if already closed */
2980         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2981                 return (0);
2982
2983         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2984
2985         mlx5e_set_rx_mode_core(priv);
2986         mlx5e_del_all_vlan_rules(priv);
2987         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2988         mlx5e_close_flow_table(priv);
2989         mlx5e_close_tirs(priv);
2990         mlx5e_close_rqt(priv);
2991         mlx5e_close_channels(priv);
2992         mlx5_vport_dealloc_q_counter(priv->mdev,
2993             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2994         mlx5e_close_tises(priv);
2995
2996         return (0);
2997 }
2998
2999 #if (__FreeBSD_version >= 1100000)
3000 static uint64_t
3001 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3002 {
3003         struct mlx5e_priv *priv = ifp->if_softc;
3004         u64 retval;
3005
3006         /* PRIV_LOCK(priv); XXX not allowed */
3007         switch (cnt) {
3008         case IFCOUNTER_IPACKETS:
3009                 retval = priv->stats.vport.rx_packets;
3010                 break;
3011         case IFCOUNTER_IERRORS:
3012                 retval = priv->stats.pport.in_range_len_errors +
3013                     priv->stats.pport.out_of_range_len +
3014                     priv->stats.pport.too_long_errors +
3015                     priv->stats.pport.check_seq_err +
3016                     priv->stats.pport.alignment_err;
3017                 break;
3018         case IFCOUNTER_IQDROPS:
3019                 retval = priv->stats.vport.rx_out_of_buffer;
3020                 break;
3021         case IFCOUNTER_OPACKETS:
3022                 retval = priv->stats.vport.tx_packets;
3023                 break;
3024         case IFCOUNTER_OERRORS:
3025                 retval = priv->stats.port_stats_debug.out_discards;
3026                 break;
3027         case IFCOUNTER_IBYTES:
3028                 retval = priv->stats.vport.rx_bytes;
3029                 break;
3030         case IFCOUNTER_OBYTES:
3031                 retval = priv->stats.vport.tx_bytes;
3032                 break;
3033         case IFCOUNTER_IMCASTS:
3034                 retval = priv->stats.vport.rx_multicast_packets;
3035                 break;
3036         case IFCOUNTER_OMCASTS:
3037                 retval = priv->stats.vport.tx_multicast_packets;
3038                 break;
3039         case IFCOUNTER_OQDROPS:
3040                 retval = priv->stats.vport.tx_queue_dropped;
3041                 break;
3042         case IFCOUNTER_COLLISIONS:
3043                 retval = priv->stats.pport.collisions;
3044                 break;
3045         default:
3046                 retval = if_get_counter_default(ifp, cnt);
3047                 break;
3048         }
3049         /* PRIV_UNLOCK(priv); XXX not allowed */
3050         return (retval);
3051 }
3052 #endif
3053
3054 static void
3055 mlx5e_set_rx_mode(struct ifnet *ifp)
3056 {
3057         struct mlx5e_priv *priv = ifp->if_softc;
3058
3059         queue_work(priv->wq, &priv->set_rx_mode_work);
3060 }
3061
3062 static int
3063 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3064 {
3065         struct mlx5e_priv *priv;
3066         struct ifreq *ifr;
3067         struct ifi2creq i2c;
3068         int error = 0;
3069         int mask = 0;
3070         int size_read = 0;
3071         int module_status;
3072         int module_num;
3073         int max_mtu;
3074         uint8_t read_addr;
3075
3076         priv = ifp->if_softc;
3077
3078         /* check if detaching */
3079         if (priv == NULL || priv->gone != 0)
3080                 return (ENXIO);
3081
3082         switch (command) {
3083         case SIOCSIFMTU:
3084                 ifr = (struct ifreq *)data;
3085
3086                 PRIV_LOCK(priv);
3087                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3088
3089                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3090                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3091                         int was_opened;
3092
3093                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3094                         if (was_opened)
3095                                 mlx5e_close_locked(ifp);
3096
3097                         /* set new MTU */
3098                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3099
3100                         if (was_opened)
3101                                 mlx5e_open_locked(ifp);
3102                 } else {
3103                         error = EINVAL;
3104                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
3105                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3106                 }
3107                 PRIV_UNLOCK(priv);
3108                 break;
3109         case SIOCSIFFLAGS:
3110                 if ((ifp->if_flags & IFF_UP) &&
3111                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3112                         mlx5e_set_rx_mode(ifp);
3113                         break;
3114                 }
3115                 PRIV_LOCK(priv);
3116                 if (ifp->if_flags & IFF_UP) {
3117                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3118                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3119                                         mlx5e_open_locked(ifp);
3120                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3121                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3122                         }
3123                 } else {
3124                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3125                                 mlx5_set_port_status(priv->mdev,
3126                                     MLX5_PORT_DOWN);
3127                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3128                                         mlx5e_close_locked(ifp);
3129                                 mlx5e_update_carrier(priv);
3130                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3131                         }
3132                 }
3133                 PRIV_UNLOCK(priv);
3134                 break;
3135         case SIOCADDMULTI:
3136         case SIOCDELMULTI:
3137                 mlx5e_set_rx_mode(ifp);
3138                 break;
3139         case SIOCSIFMEDIA:
3140         case SIOCGIFMEDIA:
3141         case SIOCGIFXMEDIA:
3142                 ifr = (struct ifreq *)data;
3143                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3144                 break;
3145         case SIOCSIFCAP:
3146                 ifr = (struct ifreq *)data;
3147                 PRIV_LOCK(priv);
3148                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3149
3150                 if (mask & IFCAP_TXCSUM) {
3151                         ifp->if_capenable ^= IFCAP_TXCSUM;
3152                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3153
3154                         if (IFCAP_TSO4 & ifp->if_capenable &&
3155                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3156                                 ifp->if_capenable &= ~IFCAP_TSO4;
3157                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3158                                 if_printf(ifp,
3159                                     "tso4 disabled due to -txcsum.\n");
3160                         }
3161                 }
3162                 if (mask & IFCAP_TXCSUM_IPV6) {
3163                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3164                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3165
3166                         if (IFCAP_TSO6 & ifp->if_capenable &&
3167                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3168                                 ifp->if_capenable &= ~IFCAP_TSO6;
3169                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3170                                 if_printf(ifp,
3171                                     "tso6 disabled due to -txcsum6.\n");
3172                         }
3173                 }
3174                 if (mask & IFCAP_RXCSUM)
3175                         ifp->if_capenable ^= IFCAP_RXCSUM;
3176                 if (mask & IFCAP_RXCSUM_IPV6)
3177                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3178                 if (mask & IFCAP_TSO4) {
3179                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3180                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3181                                 if_printf(ifp, "enable txcsum first.\n");
3182                                 error = EAGAIN;
3183                                 goto out;
3184                         }
3185                         ifp->if_capenable ^= IFCAP_TSO4;
3186                         ifp->if_hwassist ^= CSUM_IP_TSO;
3187                 }
3188                 if (mask & IFCAP_TSO6) {
3189                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3190                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3191                                 if_printf(ifp, "enable txcsum6 first.\n");
3192                                 error = EAGAIN;
3193                                 goto out;
3194                         }
3195                         ifp->if_capenable ^= IFCAP_TSO6;
3196                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3197                 }
3198                 if (mask & IFCAP_VLAN_HWFILTER) {
3199                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3200                                 mlx5e_disable_vlan_filter(priv);
3201                         else
3202                                 mlx5e_enable_vlan_filter(priv);
3203
3204                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3205                 }
3206                 if (mask & IFCAP_VLAN_HWTAGGING)
3207                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3208                 if (mask & IFCAP_WOL_MAGIC)
3209                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3210
3211                 VLAN_CAPABILITIES(ifp);
3212                 /* turn off LRO means also turn of HW LRO - if it's on */
3213                 if (mask & IFCAP_LRO) {
3214                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3215                         bool need_restart = false;
3216
3217                         ifp->if_capenable ^= IFCAP_LRO;
3218
3219                         /* figure out if updating HW LRO is needed */
3220                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3221                                 if (priv->params.hw_lro_en) {
3222                                         priv->params.hw_lro_en = false;
3223                                         need_restart = true;
3224                                 }
3225                         } else {
3226                                 if (priv->params.hw_lro_en == false &&
3227                                     priv->params_ethtool.hw_lro != 0) {
3228                                         priv->params.hw_lro_en = true;
3229                                         need_restart = true;
3230                                 }
3231                         }
3232                         if (was_opened && need_restart) {
3233                                 mlx5e_close_locked(ifp);
3234                                 mlx5e_open_locked(ifp);
3235                         }
3236                 }
3237 out:
3238                 PRIV_UNLOCK(priv);
3239                 break;
3240
3241         case SIOCGI2C:
3242                 ifr = (struct ifreq *)data;
3243
3244                 /*
3245                  * Copy from the user-space address ifr_data to the
3246                  * kernel-space address i2c
3247                  */
3248                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3249                 if (error)
3250                         break;
3251
3252                 if (i2c.len > sizeof(i2c.data)) {
3253                         error = EINVAL;
3254                         break;
3255                 }
3256
3257                 PRIV_LOCK(priv);
3258                 /* Get module_num which is required for the query_eeprom */
3259                 error = mlx5_query_module_num(priv->mdev, &module_num);
3260                 if (error) {
3261                         if_printf(ifp, "Query module num failed, eeprom "
3262                             "reading is not supported\n");
3263                         error = EINVAL;
3264                         goto err_i2c;
3265                 }
3266                 /* Check if module is present before doing an access */
3267                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3268                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3269                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3270                         error = EINVAL;
3271                         goto err_i2c;
3272                 }
3273                 /*
3274                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3275                  * The internal conversion is as follows:
3276                  */
3277                 if (i2c.dev_addr == 0xA0)
3278                         read_addr = MLX5E_I2C_ADDR_LOW;
3279                 else if (i2c.dev_addr == 0xA2)
3280                         read_addr = MLX5E_I2C_ADDR_HIGH;
3281                 else {
3282                         if_printf(ifp, "Query eeprom failed, "
3283                             "Invalid Address: %X\n", i2c.dev_addr);
3284                         error = EINVAL;
3285                         goto err_i2c;
3286                 }
3287                 error = mlx5_query_eeprom(priv->mdev,
3288                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3289                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3290                     (uint32_t *)i2c.data, &size_read);
3291                 if (error) {
3292                         if_printf(ifp, "Query eeprom failed, eeprom "
3293                             "reading is not supported\n");
3294                         error = EINVAL;
3295                         goto err_i2c;
3296                 }
3297
3298                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3299                         error = mlx5_query_eeprom(priv->mdev,
3300                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3301                             (uint32_t)(i2c.offset + size_read),
3302                             (uint32_t)(i2c.len - size_read), module_num,
3303                             (uint32_t *)(i2c.data + size_read), &size_read);
3304                 }
3305                 if (error) {
3306                         if_printf(ifp, "Query eeprom failed, eeprom "
3307                             "reading is not supported\n");
3308                         error = EINVAL;
3309                         goto err_i2c;
3310                 }
3311
3312                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3313 err_i2c:
3314                 PRIV_UNLOCK(priv);
3315                 break;
3316
3317         default:
3318                 error = ether_ioctl(ifp, command, data);
3319                 break;
3320         }
3321         return (error);
3322 }
3323
3324 static int
3325 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3326 {
3327         /*
3328          * TODO: uncoment once FW really sets all these bits if
3329          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3330          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3331          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3332          * -ENOTSUPP;
3333          */
3334
3335         /* TODO: add more must-to-have features */
3336
3337         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3338                 return (-ENODEV);
3339
3340         return (0);
3341 }
3342
3343 static u16
3344 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3345 {
3346         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3347
3348         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3349
3350         /* verify against driver hardware limit */
3351         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3352                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3353
3354         return (bf_buf_size);
3355 }
3356
3357 static int
3358 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3359     struct mlx5e_priv *priv,
3360     int num_comp_vectors)
3361 {
3362         int err;
3363
3364         /*
3365          * TODO: Consider link speed for setting "log_sq_size",
3366          * "log_rq_size" and "cq_moderation_xxx":
3367          */
3368         priv->params.log_sq_size =
3369             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3370         priv->params.log_rq_size =
3371             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3372         priv->params.rx_cq_moderation_usec =
3373             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3374             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3375             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3376         priv->params.rx_cq_moderation_mode =
3377             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3378         priv->params.rx_cq_moderation_pkts =
3379             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3380         priv->params.tx_cq_moderation_usec =
3381             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3382         priv->params.tx_cq_moderation_pkts =
3383             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3384         priv->params.min_rx_wqes =
3385             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3386         priv->params.rx_hash_log_tbl_sz =
3387             (order_base_2(num_comp_vectors) >
3388             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3389             order_base_2(num_comp_vectors) :
3390             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3391         priv->params.num_tc = 1;
3392         priv->params.default_vlan_prio = 0;
3393         priv->counter_set_id = -1;
3394         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3395
3396         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3397         if (err)
3398                 return (err);
3399
3400         /*
3401          * hw lro is currently defaulted to off. when it won't anymore we
3402          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3403          */
3404         priv->params.hw_lro_en = false;
3405         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3406
3407         /*
3408          * CQE zipping is currently defaulted to off. when it won't
3409          * anymore we will consider the HW capability:
3410          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3411          */
3412         priv->params.cqe_zipping_en = false;
3413
3414         priv->mdev = mdev;
3415         priv->params.num_channels = num_comp_vectors;
3416         priv->params.channels_rsss = 1;
3417         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3418         priv->queue_mapping_channel_mask =
3419             roundup_pow_of_two(num_comp_vectors) - 1;
3420         priv->num_tc = priv->params.num_tc;
3421         priv->default_vlan_prio = priv->params.default_vlan_prio;
3422
3423         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3424         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3425         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3426
3427         return (0);
3428 }
3429
3430 static int
3431 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3432                   struct mlx5_core_mr *mkey)
3433 {
3434         struct ifnet *ifp = priv->ifp;
3435         struct mlx5_core_dev *mdev = priv->mdev;
3436         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3437         void *mkc;
3438         u32 *in;
3439         int err;
3440
3441         in = mlx5_vzalloc(inlen);
3442         if (in == NULL) {
3443                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3444                 return (-ENOMEM);
3445         }
3446
3447         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3448         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3449         MLX5_SET(mkc, mkc, lw, 1);
3450         MLX5_SET(mkc, mkc, lr, 1);
3451
3452         MLX5_SET(mkc, mkc, pd, pdn);
3453         MLX5_SET(mkc, mkc, length64, 1);
3454         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3455
3456         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3457         if (err)
3458                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3459                     __func__, err);
3460
3461         kvfree(in);
3462         return (err);
3463 }
3464
3465 static const char *mlx5e_vport_stats_desc[] = {
3466         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3467 };
3468
3469 static const char *mlx5e_pport_stats_desc[] = {
3470         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3471 };
3472
3473 static void
3474 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3475 {
3476         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3477         sx_init(&priv->state_lock, "mlx5state");
3478         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3479         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3480 }
3481
3482 static void
3483 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3484 {
3485         mtx_destroy(&priv->async_events_mtx);
3486         sx_destroy(&priv->state_lock);
3487 }
3488
3489 static int
3490 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3491 {
3492         /*
3493          * %d.%d%.d the string format.
3494          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3495          * We need at most 5 chars to store that.
3496          * It also has: two "." and NULL at the end, which means we need 18
3497          * (5*3 + 3) chars at most.
3498          */
3499         char fw[18];
3500         struct mlx5e_priv *priv = arg1;
3501         int error;
3502
3503         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3504             fw_rev_sub(priv->mdev));
3505         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3506         return (error);
3507 }
3508
3509 static void
3510 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3511 {
3512         int i;
3513
3514         for (i = 0; i < ch->num_tc; i++)
3515                 mlx5e_drain_sq(&ch->sq[i]);
3516 }
3517
3518 static void
3519 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3520 {
3521
3522         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3523         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3524         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3525         sq->doorbell.d64 = 0;
3526 }
3527
3528 void
3529 mlx5e_resume_sq(struct mlx5e_sq *sq)
3530 {
3531         int err;
3532
3533         /* check if already enabled */
3534         if (READ_ONCE(sq->running) != 0)
3535                 return;
3536
3537         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3538             MLX5_SQC_STATE_RST);
3539         if (err != 0) {
3540                 if_printf(sq->ifp,
3541                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3542         }
3543
3544         sq->cc = 0;
3545         sq->pc = 0;
3546
3547         /* reset doorbell prior to moving from RST to RDY */
3548         mlx5e_reset_sq_doorbell_record(sq);
3549
3550         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3551             MLX5_SQC_STATE_RDY);
3552         if (err != 0) {
3553                 if_printf(sq->ifp,
3554                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3555         }
3556
3557         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3558         WRITE_ONCE(sq->running, 1);
3559 }
3560
3561 static void
3562 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3563 {
3564         int i;
3565
3566         for (i = 0; i < ch->num_tc; i++)
3567                 mlx5e_resume_sq(&ch->sq[i]);
3568 }
3569
3570 static void
3571 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3572 {
3573         struct mlx5e_rq *rq = &ch->rq;
3574         int err;
3575
3576         mtx_lock(&rq->mtx);
3577         rq->enabled = 0;
3578         callout_stop(&rq->watchdog);
3579         mtx_unlock(&rq->mtx);
3580
3581         callout_drain(&rq->watchdog);
3582
3583         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3584         if (err != 0) {
3585                 if_printf(rq->ifp,
3586                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3587         }
3588
3589         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3590                 msleep(1);
3591                 rq->cq.mcq.comp(&rq->cq.mcq);
3592         }
3593
3594         /*
3595          * Transitioning into RST state will allow the FW to track less ERR state queues,
3596          * thus reducing the recv queue flushing time
3597          */
3598         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3599         if (err != 0) {
3600                 if_printf(rq->ifp,
3601                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3602         }
3603 }
3604
3605 static void
3606 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3607 {
3608         struct mlx5e_rq *rq = &ch->rq;
3609         int err;
3610
3611         rq->wq.wqe_ctr = 0;
3612         mlx5_wq_ll_update_db_record(&rq->wq);
3613         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3614         if (err != 0) {
3615                 if_printf(rq->ifp,
3616                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3617         }
3618
3619         rq->enabled = 1;
3620
3621         rq->cq.mcq.comp(&rq->cq.mcq);
3622 }
3623
3624 void
3625 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3626 {
3627         int i;
3628
3629         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3630                 return;
3631
3632         for (i = 0; i < priv->params.num_channels; i++) {
3633                 if (value)
3634                         mlx5e_disable_tx_dma(&priv->channel[i]);
3635                 else
3636                         mlx5e_enable_tx_dma(&priv->channel[i]);
3637         }
3638 }
3639
3640 void
3641 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3642 {
3643         int i;
3644
3645         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3646                 return;
3647
3648         for (i = 0; i < priv->params.num_channels; i++) {
3649                 if (value)
3650                         mlx5e_disable_rx_dma(&priv->channel[i]);
3651                 else
3652                         mlx5e_enable_rx_dma(&priv->channel[i]);
3653         }
3654 }
3655
3656 static void
3657 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3658 {
3659         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3660             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3661             sysctl_firmware, "A", "HCA firmware version");
3662
3663         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3664             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3665             "Board ID");
3666 }
3667
3668 static int
3669 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3670 {
3671         struct mlx5e_priv *priv = arg1;
3672         uint8_t temp[MLX5E_MAX_PRIORITY];
3673         uint32_t tx_pfc;
3674         int err;
3675         int i;
3676
3677         PRIV_LOCK(priv);
3678
3679         tx_pfc = priv->params.tx_priority_flow_control;
3680
3681         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3682                 temp[i] = (tx_pfc >> i) & 1;
3683
3684         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3685         if (err || !req->newptr)
3686                 goto done;
3687         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3688         if (err)
3689                 goto done;
3690
3691         priv->params.tx_priority_flow_control = 0;
3692
3693         /* range check input value */
3694         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3695                 if (temp[i] > 1) {
3696                         err = ERANGE;
3697                         goto done;
3698                 }
3699                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3700         }
3701
3702         /* check if update is required */
3703         if (tx_pfc != priv->params.tx_priority_flow_control)
3704                 err = -mlx5e_set_port_pfc(priv);
3705 done:
3706         if (err != 0)
3707                 priv->params.tx_priority_flow_control= tx_pfc;
3708         PRIV_UNLOCK(priv);
3709
3710         return (err);
3711 }
3712
3713 static int
3714 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3715 {
3716         struct mlx5e_priv *priv = arg1;
3717         uint8_t temp[MLX5E_MAX_PRIORITY];
3718         uint32_t rx_pfc;
3719         int err;
3720         int i;
3721
3722         PRIV_LOCK(priv);
3723
3724         rx_pfc = priv->params.rx_priority_flow_control;
3725
3726         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3727                 temp[i] = (rx_pfc >> i) & 1;
3728
3729         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3730         if (err || !req->newptr)
3731                 goto done;
3732         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3733         if (err)
3734                 goto done;
3735
3736         priv->params.rx_priority_flow_control = 0;
3737
3738         /* range check input value */
3739         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3740                 if (temp[i] > 1) {
3741                         err = ERANGE;
3742                         goto done;
3743                 }
3744                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3745         }
3746
3747         /* check if update is required */
3748         if (rx_pfc != priv->params.rx_priority_flow_control)
3749                 err = -mlx5e_set_port_pfc(priv);
3750 done:
3751         if (err != 0)
3752                 priv->params.rx_priority_flow_control= rx_pfc;
3753         PRIV_UNLOCK(priv);
3754
3755         return (err);
3756 }
3757
3758 static void
3759 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3760 {
3761 #if (__FreeBSD_version < 1100000)
3762         char path[96];
3763 #endif
3764         int error;
3765
3766         /* enable pauseframes by default */
3767         priv->params.tx_pauseframe_control = 1;
3768         priv->params.rx_pauseframe_control = 1;
3769
3770         /* disable ports flow control, PFC, by default */
3771         priv->params.tx_priority_flow_control = 0;
3772         priv->params.rx_priority_flow_control = 0;
3773
3774 #if (__FreeBSD_version < 1100000)
3775         /* compute path for sysctl */
3776         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3777             device_get_unit(priv->mdev->pdev->dev.bsddev));
3778
3779         /* try to fetch tunable, if any */
3780         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3781
3782         /* compute path for sysctl */
3783         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3784             device_get_unit(priv->mdev->pdev->dev.bsddev));
3785
3786         /* try to fetch tunable, if any */
3787         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3788 #endif
3789
3790         /* register pauseframe SYSCTLs */
3791         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3792             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3793             &priv->params.tx_pauseframe_control, 0,
3794             "Set to enable TX pause frames. Clear to disable.");
3795
3796         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3797             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3798             &priv->params.rx_pauseframe_control, 0,
3799             "Set to enable RX pause frames. Clear to disable.");
3800
3801         /* register priority flow control, PFC, SYSCTLs */
3802         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3803             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3804             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3805             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3806
3807         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3808             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3809             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3810             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3811
3812         PRIV_LOCK(priv);
3813
3814         /* range check */
3815         priv->params.tx_pauseframe_control =
3816             priv->params.tx_pauseframe_control ? 1 : 0;
3817         priv->params.rx_pauseframe_control =
3818             priv->params.rx_pauseframe_control ? 1 : 0;
3819
3820         /* update firmware */
3821         error = mlx5e_set_port_pause_and_pfc(priv);
3822         if (error == -EINVAL) {
3823                 if_printf(priv->ifp,
3824                     "Global pauseframes must be disabled before enabling PFC.\n");
3825                 priv->params.rx_priority_flow_control = 0;
3826                 priv->params.tx_priority_flow_control = 0;
3827
3828                 /* update firmware */
3829                 (void) mlx5e_set_port_pause_and_pfc(priv);
3830         }
3831         PRIV_UNLOCK(priv);
3832 }
3833
3834 static void *
3835 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3836 {
3837         struct ifnet *ifp;
3838         struct mlx5e_priv *priv;
3839         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3840         u8 connector_type;
3841         struct sysctl_oid_list *child;
3842         int ncv = mdev->priv.eq_table.num_comp_vectors;
3843         char unit[16];
3844         int err;
3845         int i,j;
3846         u32 eth_proto_cap;
3847         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
3848         bool ext = 0;
3849         u32 speeds_num;
3850         struct media media_entry = {};
3851
3852         if (mlx5e_check_required_hca_cap(mdev)) {
3853                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3854                 return (NULL);
3855         }
3856         /*
3857          * Try to allocate the priv and make room for worst-case
3858          * number of channel structures:
3859          */
3860         priv = malloc(sizeof(*priv) +
3861             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3862             M_MLX5EN, M_WAITOK | M_ZERO);
3863         mlx5e_priv_mtx_init(priv);
3864
3865         ifp = priv->ifp = if_alloc(IFT_ETHER);
3866         if (ifp == NULL) {
3867                 mlx5_core_err(mdev, "if_alloc() failed\n");
3868                 goto err_free_priv;
3869         }
3870         ifp->if_softc = priv;
3871         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3872         ifp->if_mtu = ETHERMTU;
3873         ifp->if_init = mlx5e_open;
3874         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3875         ifp->if_ioctl = mlx5e_ioctl;
3876         ifp->if_transmit = mlx5e_xmit;
3877         ifp->if_qflush = if_qflush;
3878 #if (__FreeBSD_version >= 1100000)
3879         ifp->if_get_counter = mlx5e_get_counter;
3880 #endif
3881         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3882         /*
3883          * Set driver features
3884          */
3885         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3886         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3887         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3888         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3889         ifp->if_capabilities |= IFCAP_LRO;
3890         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3891         ifp->if_capabilities |= IFCAP_HWSTATS;
3892
3893         /* set TSO limits so that we don't have to drop TX packets */
3894         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3895         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3896         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3897
3898         ifp->if_capenable = ifp->if_capabilities;
3899         ifp->if_hwassist = 0;
3900         if (ifp->if_capenable & IFCAP_TSO)
3901                 ifp->if_hwassist |= CSUM_TSO;
3902         if (ifp->if_capenable & IFCAP_TXCSUM)
3903                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3904         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3905                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3906
3907         /* ifnet sysctl tree */
3908         sysctl_ctx_init(&priv->sysctl_ctx);
3909         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3910             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3911         if (priv->sysctl_ifnet == NULL) {
3912                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3913                 goto err_free_sysctl;
3914         }
3915         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3916         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3917             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3918         if (priv->sysctl_ifnet == NULL) {
3919                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3920                 goto err_free_sysctl;
3921         }
3922
3923         /* HW sysctl tree */
3924         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3925         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3926             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3927         if (priv->sysctl_hw == NULL) {
3928                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3929                 goto err_free_sysctl;
3930         }
3931
3932         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3933         if (err) {
3934                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3935                 goto err_free_sysctl;
3936         }
3937
3938         /* reuse mlx5core's watchdog workqueue */
3939         priv->wq = mdev->priv.health.wq_watchdog;
3940
3941         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3942         if (err) {
3943                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3944                     __func__, err);
3945                 goto err_free_wq;
3946         }
3947         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3948         if (err) {
3949                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3950                     __func__, err);
3951                 goto err_unmap_free_uar;
3952         }
3953         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3954         if (err) {
3955                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3956                     __func__, err);
3957                 goto err_dealloc_pd;
3958         }
3959         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3960         if (err) {
3961                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3962                     __func__, err);
3963                 goto err_dealloc_transport_domain;
3964         }
3965         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3966
3967         /* check if we should generate a random MAC address */
3968         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3969             is_zero_ether_addr(dev_addr)) {
3970                 random_ether_addr(dev_addr);
3971                 if_printf(ifp, "Assigned random MAC address\n");
3972         }
3973
3974         /* set default MTU */
3975         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3976
3977         /* Set default media status */
3978         priv->media_status_last = IFM_AVALID;
3979         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3980             IFM_ETH_RXPAUSE | IFM_FDX;
3981
3982         /* setup default pauseframes configuration */
3983         mlx5e_setup_pauseframes(priv);
3984
3985         /* Setup supported medias */
3986         //TODO: If we failed to query ptys is it ok to proceed??
3987         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
3988                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
3989                     ptys_extended_ethernet);
3990                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
3991                     eth_proto_capability);
3992                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
3993                         connector_type = MLX5_GET(ptys_reg, out,
3994                             connector_type);
3995         } else {
3996                 eth_proto_cap = 0;
3997                 if_printf(ifp, "%s: Query port media capability failed,"
3998                     " %d\n", __func__, err);
3999         }
4000
4001         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4002             mlx5e_media_change, mlx5e_media_status);
4003
4004         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4005         for (i = 0; i != speeds_num; i++) {
4006                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4007                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4008                             mlx5e_mode_table[i][j];
4009                         if (media_entry.baudrate == 0)
4010                                 continue;
4011                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4012                                 ifmedia_add(&priv->media,
4013                                     media_entry.subtype |
4014                                     IFM_ETHER, 0, NULL);
4015                                 ifmedia_add(&priv->media,
4016                                     media_entry.subtype |
4017                                     IFM_ETHER | IFM_FDX |
4018                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4019                         }
4020                 }
4021         }
4022
4023         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4024         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4025             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4026
4027         /* Set autoselect by default */
4028         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4029             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4030         ether_ifattach(ifp, dev_addr);
4031
4032         /* Register for VLAN events */
4033         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4034             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4035         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4036             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4037
4038         /* Link is down by default */
4039         if_link_state_change(ifp, LINK_STATE_DOWN);
4040
4041         mlx5e_enable_async_events(priv);
4042
4043         mlx5e_add_hw_stats(priv);
4044
4045         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4046             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4047             priv->stats.vport.arg);
4048
4049         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4050             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4051             priv->stats.pport.arg);
4052
4053         mlx5e_create_ethtool(priv);
4054
4055         mtx_lock(&priv->async_events_mtx);
4056         mlx5e_update_stats(priv);
4057         mtx_unlock(&priv->async_events_mtx);
4058
4059         return (priv);
4060
4061 err_dealloc_transport_domain:
4062         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4063
4064 err_dealloc_pd:
4065         mlx5_core_dealloc_pd(mdev, priv->pdn);
4066
4067 err_unmap_free_uar:
4068         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4069
4070 err_free_wq:
4071         flush_workqueue(priv->wq);
4072
4073 err_free_sysctl:
4074         sysctl_ctx_free(&priv->sysctl_ctx);
4075         if (priv->sysctl_debug)
4076                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4077         if_free(ifp);
4078
4079 err_free_priv:
4080         mlx5e_priv_mtx_destroy(priv);
4081         free(priv, M_MLX5EN);
4082         return (NULL);
4083 }
4084
4085 static void
4086 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4087 {
4088         struct mlx5e_priv *priv = vpriv;
4089         struct ifnet *ifp = priv->ifp;
4090
4091         /* don't allow more IOCTLs */
4092         priv->gone = 1;
4093
4094         /* XXX wait a bit to allow IOCTL handlers to complete */
4095         pause("W", hz);
4096
4097         /* stop watchdog timer */
4098         callout_drain(&priv->watchdog);
4099
4100         if (priv->vlan_attach != NULL)
4101                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4102         if (priv->vlan_detach != NULL)
4103                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4104
4105         /* make sure device gets closed */
4106         PRIV_LOCK(priv);
4107         mlx5e_close_locked(ifp);
4108         PRIV_UNLOCK(priv);
4109
4110         /* unregister device */
4111         ifmedia_removeall(&priv->media);
4112         ether_ifdetach(ifp);
4113         if_free(ifp);
4114
4115         /* destroy all remaining sysctl nodes */
4116         sysctl_ctx_free(&priv->stats.vport.ctx);
4117         sysctl_ctx_free(&priv->stats.pport.ctx);
4118         if (priv->sysctl_debug)
4119                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4120         sysctl_ctx_free(&priv->sysctl_ctx);
4121
4122         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4123         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4124         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4125         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4126         mlx5e_disable_async_events(priv);
4127         flush_workqueue(priv->wq);
4128         mlx5e_priv_mtx_destroy(priv);
4129         free(priv, M_MLX5EN);
4130 }
4131
4132 static void *
4133 mlx5e_get_ifp(void *vpriv)
4134 {
4135         struct mlx5e_priv *priv = vpriv;
4136
4137         return (priv->ifp);
4138 }
4139
4140 static struct mlx5_interface mlx5e_interface = {
4141         .add = mlx5e_create_ifp,
4142         .remove = mlx5e_destroy_ifp,
4143         .event = mlx5e_async_event,
4144         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4145         .get_dev = mlx5e_get_ifp,
4146 };
4147
4148 void
4149 mlx5e_init(void)
4150 {
4151         mlx5_register_interface(&mlx5e_interface);
4152 }
4153
4154 void
4155 mlx5e_cleanup(void)
4156 {
4157         mlx5_unregister_interface(&mlx5e_interface);
4158 }
4159
4160 static void
4161 mlx5e_show_version(void __unused *arg)
4162 {
4163
4164         printf("%s", mlx5e_version);
4165 }
4166 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4167
4168 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4169 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4170
4171 #if (__FreeBSD_version >= 1100000)
4172 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4173 #endif
4174 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4175 MODULE_VERSION(mlx5en, 1);