sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 struct media {
  51         u32     subtype;
  52         u64     baudrate;
  53 };
  54
  55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  56
  57         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  58                 .subtype = IFM_1000_CX_SGMII,
  59                 .baudrate = IF_Mbps(1000ULL),
  60         },
  61         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  62                 .subtype = IFM_1000_KX,
  63                 .baudrate = IF_Mbps(1000ULL),
  64         },
  65         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  66                 .subtype = IFM_10G_CX4,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  70                 .subtype = IFM_10G_KX4,
  71                 .baudrate = IF_Gbps(10ULL),
  72         },
  73         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  74                 .subtype = IFM_10G_KR,
  75                 .baudrate = IF_Gbps(10ULL),
  76         },
  77         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  78                 .subtype = IFM_20G_KR2,
  79                 .baudrate = IF_Gbps(20ULL),
  80         },
  81         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  82                 .subtype = IFM_40G_CR4,
  83                 .baudrate = IF_Gbps(40ULL),
  84         },
  85         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  86                 .subtype = IFM_40G_KR4,
  87                 .baudrate = IF_Gbps(40ULL),
  88         },
  89         [MLX5E_56GBASE_R4][MLX5E_R] = {
  90                 .subtype = IFM_56G_R4,
  91                 .baudrate = IF_Gbps(56ULL),
  92         },
  93         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  94                 .subtype = IFM_10G_CR1,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_10GBASE_SR][MLX5E_SR] = {
  98                 .subtype = IFM_10G_SR,
  99                 .baudrate = IF_Gbps(10ULL),
 100         },
 101         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 102                 .subtype = IFM_10G_ER,
 103                 .baudrate = IF_Gbps(10ULL),
 104         },
 105         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 106                 .subtype = IFM_10G_LR,
 107                 .baudrate = IF_Gbps(10ULL),
 108         },
 109         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 110                 .subtype = IFM_40G_SR4,
 111                 .baudrate = IF_Gbps(40ULL),
 112         },
 113         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 114                 .subtype = IFM_40G_LR4,
 115                 .baudrate = IF_Gbps(40ULL),
 116         },
 117         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 118                 .subtype = IFM_40G_ER4,
 119                 .baudrate = IF_Gbps(40ULL),
 120         },
 121         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 122                 .subtype = IFM_100G_CR4,
 123                 .baudrate = IF_Gbps(100ULL),
 124         },
 125         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 126                 .subtype = IFM_100G_SR4,
 127                 .baudrate = IF_Gbps(100ULL),
 128         },
 129         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 130                 .subtype = IFM_100G_KR4,
 131                 .baudrate = IF_Gbps(100ULL),
 132         },
 133         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 134                 .subtype = IFM_100G_LR4,
 135                 .baudrate = IF_Gbps(100ULL),
 136         },
 137         [MLX5E_100BASE_TX][MLX5E_TX] = {
 138                 .subtype = IFM_100_TX,
 139                 .baudrate = IF_Mbps(100ULL),
 140         },
 141         [MLX5E_1000BASE_T][MLX5E_T] = {
 142                 .subtype = IFM_1000_T,
 143                 .baudrate = IF_Mbps(1000ULL),
 144         },
 145         [MLX5E_10GBASE_T][MLX5E_T] = {
 146                 .subtype = IFM_10G_T,
 147                 .baudrate = IF_Gbps(10ULL),
 148         },
 149         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 150                 .subtype = IFM_25G_CR,
 151                 .baudrate = IF_Gbps(25ULL),
 152         },
 153         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 154                 .subtype = IFM_25G_KR,
 155                 .baudrate = IF_Gbps(25ULL),
 156         },
 157         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 158                 .subtype = IFM_25G_SR,
 159                 .baudrate = IF_Gbps(25ULL),
 160         },
 161         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 162                 .subtype = IFM_50G_CR2,
 163                 .baudrate = IF_Gbps(50ULL),
 164         },
 165         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 166                 .subtype = IFM_50G_KR2,
 167                 .baudrate = IF_Gbps(50ULL),
 168         },
 169 };
 170
 171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 172         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 173                 .subtype = IFM_100_SGMII,
 174                 .baudrate = IF_Mbps(100),
 175         },
 176         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 177                 .subtype = IFM_1000_KX,
 178                 .baudrate = IF_Mbps(1000),
 179         },
 180         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 181                 .subtype = IFM_1000_CX_SGMII,
 182                 .baudrate = IF_Mbps(1000),
 183         },
 184         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 185                 .subtype = IFM_1000_CX,
 186                 .baudrate = IF_Mbps(1000),
 187         },
 188         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 189                 .subtype = IFM_1000_LX,
 190                 .baudrate = IF_Mbps(1000),
 191         },
 192         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 193                 .subtype = IFM_1000_SX,
 194                 .baudrate = IF_Mbps(1000),
 195         },
 196         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 197                 .subtype = IFM_1000_T,
 198                 .baudrate = IF_Mbps(1000),
 199         },
 200         [MLX5E_5GBASE_R][MLX5E_T] = {
 201                 .subtype = IFM_5000_T,
 202                 .baudrate = IF_Mbps(5000),
 203         },
 204         [MLX5E_5GBASE_R][MLX5E_KR] = {
 205                 .subtype = IFM_5000_KR,
 206                 .baudrate = IF_Mbps(5000),
 207         },
 208         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 209                 .subtype = IFM_5000_KR1,
 210                 .baudrate = IF_Mbps(5000),
 211         },
 212         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 213                 .subtype = IFM_5000_KR_S,
 214                 .baudrate = IF_Mbps(5000),
 215         },
 216         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 217                 .subtype = IFM_10G_ER,
 218                 .baudrate = IF_Gbps(10ULL),
 219         },
 220         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 221                 .subtype = IFM_10G_KR,
 222                 .baudrate = IF_Gbps(10ULL),
 223         },
 224         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 225                 .subtype = IFM_10G_LR,
 226                 .baudrate = IF_Gbps(10ULL),
 227         },
 228         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 229                 .subtype = IFM_10G_SR,
 230                 .baudrate = IF_Gbps(10ULL),
 231         },
 232         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 233                 .subtype = IFM_10G_T,
 234                 .baudrate = IF_Gbps(10ULL),
 235         },
 236         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 237                 .subtype = IFM_10G_AOC,
 238                 .baudrate = IF_Gbps(10ULL),
 239         },
 240         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 241                 .subtype = IFM_10G_CR1,
 242                 .baudrate = IF_Gbps(10ULL),
 243         },
 244         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 245                 .subtype = IFM_40G_CR4,
 246                 .baudrate = IF_Gbps(40ULL),
 247         },
 248         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 249                 .subtype = IFM_40G_KR4,
 250                 .baudrate = IF_Gbps(40ULL),
 251         },
 252         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 253                 .subtype = IFM_40G_LR4,
 254                 .baudrate = IF_Gbps(40ULL),
 255         },
 256         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 257                 .subtype = IFM_40G_SR4,
 258                 .baudrate = IF_Gbps(40ULL),
 259         },
 260         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 261                 .subtype = IFM_40G_ER4,
 262                 .baudrate = IF_Gbps(40ULL),
 263         },
 264
 265         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 266                 .subtype = IFM_25G_CR,
 267                 .baudrate = IF_Gbps(25ULL),
 268         },
 269         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 270                 .subtype = IFM_25G_KR,
 271                 .baudrate = IF_Gbps(25ULL),
 272         },
 273         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 274                 .subtype = IFM_25G_SR,
 275                 .baudrate = IF_Gbps(25ULL),
 276         },
 277         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 278                 .subtype = IFM_25G_ACC,
 279                 .baudrate = IF_Gbps(25ULL),
 280         },
 281         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 282                 .subtype = IFM_25G_AOC,
 283                 .baudrate = IF_Gbps(25ULL),
 284         },
 285         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 286                 .subtype = IFM_25G_CR1,
 287                 .baudrate = IF_Gbps(25ULL),
 288         },
 289         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 290                 .subtype = IFM_25G_CR_S,
 291                 .baudrate = IF_Gbps(25ULL),
 292         },
 293         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 294                 .subtype = IFM_5000_KR1,
 295                 .baudrate = IF_Gbps(25ULL),
 296         },
 297         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 298                 .subtype = IFM_25G_KR_S,
 299                 .baudrate = IF_Gbps(25ULL),
 300         },
 301         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 302                 .subtype = IFM_25G_LR,
 303                 .baudrate = IF_Gbps(25ULL),
 304         },
 305         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 306                 .subtype = IFM_25G_T,
 307                 .baudrate = IF_Gbps(25ULL),
 308         },
 309         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 310                 .subtype = IFM_50G_CR2,
 311                 .baudrate = IF_Gbps(50ULL),
 312         },
 313         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 314                 .subtype = IFM_50G_KR2,
 315                 .baudrate = IF_Gbps(50ULL),
 316         },
 317         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 318                 .subtype = IFM_50G_SR2,
 319                 .baudrate = IF_Gbps(50ULL),
 320         },
 321         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 322                 .subtype = IFM_50G_LR2,
 323                 .baudrate = IF_Gbps(50ULL),
 324         },
 325         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 326                 .subtype = IFM_50G_LR,
 327                 .baudrate = IF_Gbps(50ULL),
 328         },
 329         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 330                 .subtype = IFM_50G_SR,
 331                 .baudrate = IF_Gbps(50ULL),
 332         },
 333         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 334                 .subtype = IFM_50G_CP,
 335                 .baudrate = IF_Gbps(50ULL),
 336         },
 337         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 338                 .subtype = IFM_50G_FR,
 339                 .baudrate = IF_Gbps(50ULL),
 340         },
 341         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 342                 .subtype = IFM_50G_KR_PAM4,
 343                 .baudrate = IF_Gbps(50ULL),
 344         },
 345         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 346                 .subtype = IFM_100G_CR4,
 347                 .baudrate = IF_Gbps(100ULL),
 348         },
 349         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 350                 .subtype = IFM_100G_KR4,
 351                 .baudrate = IF_Gbps(100ULL),
 352         },
 353         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 354                 .subtype = IFM_100G_LR4,
 355                 .baudrate = IF_Gbps(100ULL),
 356         },
 357         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 358                 .subtype = IFM_100G_SR4,
 359                 .baudrate = IF_Gbps(100ULL),
 360         },
 361         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 362                 .subtype = IFM_100G_SR2,
 363                 .baudrate = IF_Gbps(100ULL),
 364         },
 365         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 366                 .subtype = IFM_100G_CP2,
 367                 .baudrate = IF_Gbps(100ULL),
 368         },
 369         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 370                 .subtype = IFM_100G_KR2_PAM4,
 371                 .baudrate = IF_Gbps(100ULL),
 372         },
 373         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 374                 .subtype = IFM_200G_DR4,
 375                 .baudrate = IF_Gbps(200ULL),
 376         },
 377         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 378                 .subtype = IFM_200G_LR4,
 379                 .baudrate = IF_Gbps(200ULL),
 380         },
 381         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 382                 .subtype = IFM_200G_SR4,
 383                 .baudrate = IF_Gbps(200ULL),
 384         },
 385         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 386                 .subtype = IFM_200G_FR4,
 387                 .baudrate = IF_Gbps(200ULL),
 388         },
 389         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 390                 .subtype = IFM_200G_CR4_PAM4,
 391                 .baudrate = IF_Gbps(200ULL),
 392         },
 393         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 394                 .subtype = IFM_200G_KR4_PAM4,
 395                 .baudrate = IF_Gbps(200ULL),
 396         },
 397 };
 398
 399 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 400
 401 static void
 402 mlx5e_update_carrier(struct mlx5e_priv *priv)
 403 {
 404         struct mlx5_core_dev *mdev = priv->mdev;
 405         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 406         u32 eth_proto_oper;
 407         int error;
 408         u8 port_state;
 409         u8 is_er_type;
 410         u8 i, j;
 411         bool ext;
 412         struct media media_entry = {};
 413
 414         port_state = mlx5_query_vport_state(mdev,
 415             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 416
 417         if (port_state == VPORT_STATE_UP) {
 418                 priv->media_status_last |= IFM_ACTIVE;
 419         } else {
 420                 priv->media_status_last &= ~IFM_ACTIVE;
 421                 priv->media_active_last = IFM_ETHER;
 422                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 423                 return;
 424         }
 425
 426         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 427             MLX5_PTYS_EN, 1);
 428         if (error) {
 429                 priv->media_active_last = IFM_ETHER;
 430                 priv->ifp->if_baudrate = 1;
 431                 if_printf(priv->ifp, "%s: query port ptys failed: "
 432                     "0x%x\n", __func__, error);
 433                 return;
 434         }
 435
 436         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 437         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 438             eth_proto_oper);
 439
 440         i = ilog2(eth_proto_oper);
 441
 442         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 443                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 444                     mlx5e_mode_table[i][j];
 445                 if (media_entry.baudrate != 0)
 446                         break;
 447         }
 448
 449         if (media_entry.subtype == 0) {
 450                 if_printf(priv->ifp, "%s: Could not find operational "
 451                     "media subtype\n", __func__);
 452                 return;
 453         }
 454
 455         switch (media_entry.subtype) {
 456         case IFM_10G_ER:
 457                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 458                 if (error != 0) {
 459                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 460                                   __func__, error);
 461                 }
 462                 if (error != 0 || is_er_type == 0)
 463                         media_entry.subtype = IFM_10G_LR;
 464                 break;
 465         case IFM_40G_LR4:
 466                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 467                 if (error != 0) {
 468                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 469                                   __func__, error);
 470                 }
 471                 if (error == 0 && is_er_type != 0)
 472                         media_entry.subtype = IFM_40G_ER4;
 473                 break;
 474         }
 475         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 476         priv->ifp->if_baudrate = media_entry.baudrate;
 477
 478         if_link_state_change(priv->ifp, LINK_STATE_UP);
 479 }
 480
 481 static void
 482 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 483 {
 484         struct mlx5e_priv *priv = dev->if_softc;
 485
 486         ifmr->ifm_status = priv->media_status_last;
 487         ifmr->ifm_active = priv->media_active_last |
 488             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 489             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 490
 491 }
 492
 493 static u32
 494 mlx5e_find_link_mode(u32 subtype, bool ext)
 495 {
 496         u32 i;
 497         u32 j;
 498         u32 link_mode = 0;
 499         u32 speeds_num = 0;
 500         struct media media_entry = {};
 501
 502         switch (subtype) {
 503         case IFM_10G_LR:
 504                 subtype = IFM_10G_ER;
 505                 break;
 506         case IFM_40G_ER4:
 507                 subtype = IFM_40G_LR4;
 508                 break;
 509         }
 510
 511         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 512             MLX5E_LINK_SPEEDS_NUMBER;
 513
 514         for (i = 0; i != speeds_num; i++) {
 515                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 516                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 517                             mlx5e_mode_table[i][j];
 518                         if (media_entry.baudrate == 0)
 519                                 continue;
 520                         if (media_entry.subtype == subtype) {
 521                                 link_mode |= MLX5E_PROT_MASK(i);
 522                         }
 523                 }
 524         }
 525
 526         return (link_mode);
 527 }
 528
 529 static int
 530 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 531 {
 532         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 533             priv->params.rx_pauseframe_control,
 534             priv->params.tx_pauseframe_control,
 535             priv->params.rx_priority_flow_control,
 536             priv->params.tx_priority_flow_control));
 537 }
 538
 539 static int
 540 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 541 {
 542         int error;
 543
 544         if (priv->gone != 0) {
 545                 error = -ENXIO;
 546         } else if (priv->params.rx_pauseframe_control ||
 547             priv->params.tx_pauseframe_control) {
 548                 if_printf(priv->ifp,
 549                     "Global pauseframes must be disabled before "
 550                     "enabling PFC.\n");
 551                 error = -EINVAL;
 552         } else {
 553                 error = mlx5e_set_port_pause_and_pfc(priv);
 554         }
 555         return (error);
 556 }
 557
 558 static int
 559 mlx5e_media_change(struct ifnet *dev)
 560 {
 561         struct mlx5e_priv *priv = dev->if_softc;
 562         struct mlx5_core_dev *mdev = priv->mdev;
 563         u32 eth_proto_cap;
 564         u32 link_mode;
 565         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 566         int was_opened;
 567         int locked;
 568         int error;
 569         bool ext;
 570
 571         locked = PRIV_LOCKED(priv);
 572         if (!locked)
 573                 PRIV_LOCK(priv);
 574
 575         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 576                 error = EINVAL;
 577                 goto done;
 578         }
 579
 580         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 581             MLX5_PTYS_EN, 1);
 582         if (error != 0) {
 583                 if_printf(dev, "Query port media capability failed\n");
 584                 goto done;
 585         }
 586
 587         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 588         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 589
 590         /* query supported capabilities */
 591         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 592             eth_proto_capability);
 593
 594         /* check for autoselect */
 595         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 596                 link_mode = eth_proto_cap;
 597                 if (link_mode == 0) {
 598                         if_printf(dev, "Port media capability is zero\n");
 599                         error = EINVAL;
 600                         goto done;
 601                 }
 602         } else {
 603                 link_mode = link_mode & eth_proto_cap;
 604                 if (link_mode == 0) {
 605                         if_printf(dev, "Not supported link mode requested\n");
 606                         error = EINVAL;
 607                         goto done;
 608                 }
 609         }
 610         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 611                 /* check if PFC is enabled */
 612                 if (priv->params.rx_priority_flow_control ||
 613                     priv->params.tx_priority_flow_control) {
 614                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 615                         error = EINVAL;
 616                         goto done;
 617                 }
 618         }
 619         /* update pauseframe control bits */
 620         priv->params.rx_pauseframe_control =
 621             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 622         priv->params.tx_pauseframe_control =
 623             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 624
 625         /* check if device is opened */
 626         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 627
 628         /* reconfigure the hardware */
 629         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 630         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 631         error = -mlx5e_set_port_pause_and_pfc(priv);
 632         if (was_opened)
 633                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 634
 635 done:
 636         if (!locked)
 637                 PRIV_UNLOCK(priv);
 638         return (error);
 639 }
 640
 641 static void
 642 mlx5e_update_carrier_work(struct work_struct *work)
 643 {
 644         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 645             update_carrier_work);
 646
 647         PRIV_LOCK(priv);
 648         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 649                 mlx5e_update_carrier(priv);
 650         PRIV_UNLOCK(priv);
 651 }
 652
 653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 654         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 655
 656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 657         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 658
 659 static void
 660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 661 {
 662         struct mlx5_core_dev *mdev = priv->mdev;
 663         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 664         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 665         void *out;
 666         void *in;
 667         int err;
 668
 669         /* allocate firmware request structures */
 670         in = mlx5_vzalloc(sz);
 671         out = mlx5_vzalloc(sz);
 672         if (in == NULL || out == NULL)
 673                 goto free_out;
 674
 675         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 676         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 677         if (err != 0)
 678                 goto free_out;
 679
 680         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 681         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 682
 683         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 684         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 685         if (err != 0)
 686                 goto free_out;
 687
 688         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 689
 690         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 691         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 692         if (err != 0)
 693                 goto free_out;
 694
 695         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697 free_out:
 698         /* free firmware request structures */
 699         kvfree(in);
 700         kvfree(out);
 701 }
 702
 703 /*
 704  * This function reads the physical port counters from the firmware
 705  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 706  * macros. The output is converted from big-endian 64-bit values into
 707  * host endian ones and stored in the "priv->stats.pport" structure.
 708  */
 709 static void
 710 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 711 {
 712         struct mlx5_core_dev *mdev = priv->mdev;
 713         struct mlx5e_pport_stats *s = &priv->stats.pport;
 714         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 715         u32 *in;
 716         u32 *out;
 717         const u64 *ptr;
 718         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 719         unsigned x;
 720         unsigned y;
 721         unsigned z;
 722
 723         /* allocate firmware request structures */
 724         in = mlx5_vzalloc(sz);
 725         out = mlx5_vzalloc(sz);
 726         if (in == NULL || out == NULL)
 727                 goto free_out;
 728
 729         /*
 730          * Get pointer to the 64-bit counter set which is located at a
 731          * fixed offset in the output firmware request structure:
 732          */
 733         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 734
 735         MLX5_SET(ppcnt_reg, in, local_port, 1);
 736
 737         /* read IEEE802_3 counter group using predefined counter layout */
 738         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 739         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 740         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 741              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 742                 s->arg[y] = be64toh(ptr[x]);
 743
 744         /* read RFC2819 counter group using predefined counter layout */
 745         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 746         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 747         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 748                 s->arg[y] = be64toh(ptr[x]);
 749
 750         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 751             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 752                 s_debug->arg[y] = be64toh(ptr[x]);
 753
 754         /* read RFC2863 counter group using predefined counter layout */
 755         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 756         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 757         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 758                 s_debug->arg[y] = be64toh(ptr[x]);
 759
 760         /* read physical layer stats counter group using predefined counter layout */
 761         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 762         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 763         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 764                 s_debug->arg[y] = be64toh(ptr[x]);
 765
 766         /* read Extended Ethernet counter group using predefined counter layout */
 767         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 768         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 769         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 770                 s_debug->arg[y] = be64toh(ptr[x]);
 771
 772         /* read Extended Statistical Group */
 773         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 774             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 775             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 776                 /* read Extended Statistical counter group using predefined counter layout */
 777                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 778                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 779
 780                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 781                         s_debug->arg[y] = be64toh(ptr[x]);
 782         }
 783
 784         /* read PCIE counters */
 785         mlx5e_update_pcie_counters(priv);
 786
 787         /* read per-priority counters */
 788         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 789
 790         /* iterate all the priorities */
 791         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 792                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 793                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 794
 795                 /* read per priority stats counter group using predefined counter layout */
 796                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 797                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 798                         s->arg[y] = be64toh(ptr[x]);
 799         }
 800
 801 free_out:
 802         /* free firmware request structures */
 803         kvfree(in);
 804         kvfree(out);
 805 }
 806
 807 static void
 808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 809 {
 810         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 811         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 812
 813         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 814                 return;
 815
 816         MLX5_SET(query_vnic_env_in, in, opcode,
 817             MLX5_CMD_OP_QUERY_VNIC_ENV);
 818         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 819         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 820
 821         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 822                 return;
 823
 824         priv->stats.vport.rx_steer_missed_packets =
 825             MLX5_GET64(query_vnic_env_out, out,
 826             vport_env.nic_receive_steering_discard);
 827 }
 828
 829 /*
 830  * This function is called regularly to collect all statistics
 831  * counters from the firmware. The values can be viewed through the
 832  * sysctl interface. Execution is serialized using the priv's global
 833  * configuration lock.
 834  */
 835 static void
 836 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 837 {
 838         struct mlx5_core_dev *mdev = priv->mdev;
 839         struct mlx5e_vport_stats *s = &priv->stats.vport;
 840         struct mlx5e_sq_stats *sq_stats;
 841         struct buf_ring *sq_br;
 842 #if (__FreeBSD_version < 1100000)
 843         struct ifnet *ifp = priv->ifp;
 844 #endif
 845
 846         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 847         u32 *out;
 848         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 849         u64 tso_packets = 0;
 850         u64 tso_bytes = 0;
 851         u64 tx_queue_dropped = 0;
 852         u64 tx_defragged = 0;
 853         u64 tx_offload_none = 0;
 854         u64 lro_packets = 0;
 855         u64 lro_bytes = 0;
 856         u64 sw_lro_queued = 0;
 857         u64 sw_lro_flushed = 0;
 858         u64 rx_csum_none = 0;
 859         u64 rx_wqe_err = 0;
 860         u64 rx_packets = 0;
 861         u64 rx_bytes = 0;
 862         u32 rx_out_of_buffer = 0;
 863         int i;
 864         int j;
 865
 866         out = mlx5_vzalloc(outlen);
 867         if (out == NULL)
 868                 goto free_out;
 869
 870         /* Collect firts the SW counters and then HW for consistency */
 871         for (i = 0; i < priv->params.num_channels; i++) {
 872                 struct mlx5e_channel *pch = priv->channel + i;
 873                 struct mlx5e_rq *rq = &pch->rq;
 874                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 875
 876                 /* collect stats from LRO */
 877                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 878                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 879                 sw_lro_queued += rq_stats->sw_lro_queued;
 880                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 881                 lro_packets += rq_stats->lro_packets;
 882                 lro_bytes += rq_stats->lro_bytes;
 883                 rx_csum_none += rq_stats->csum_none;
 884                 rx_wqe_err += rq_stats->wqe_err;
 885                 rx_packets += rq_stats->packets;
 886                 rx_bytes += rq_stats->bytes;
 887
 888                 for (j = 0; j < priv->num_tc; j++) {
 889                         sq_stats = &pch->sq[j].stats;
 890                         sq_br = pch->sq[j].br;
 891
 892                         tso_packets += sq_stats->tso_packets;
 893                         tso_bytes += sq_stats->tso_bytes;
 894                         tx_queue_dropped += sq_stats->dropped;
 895                         if (sq_br != NULL)
 896                                 tx_queue_dropped += sq_br->br_drops;
 897                         tx_defragged += sq_stats->defragged;
 898                         tx_offload_none += sq_stats->csum_offload_none;
 899                 }
 900         }
 901
 902         /* update counters */
 903         s->tso_packets = tso_packets;
 904         s->tso_bytes = tso_bytes;
 905         s->tx_queue_dropped = tx_queue_dropped;
 906         s->tx_defragged = tx_defragged;
 907         s->lro_packets = lro_packets;
 908         s->lro_bytes = lro_bytes;
 909         s->sw_lro_queued = sw_lro_queued;
 910         s->sw_lro_flushed = sw_lro_flushed;
 911         s->rx_csum_none = rx_csum_none;
 912         s->rx_wqe_err = rx_wqe_err;
 913         s->rx_packets = rx_packets;
 914         s->rx_bytes = rx_bytes;
 915
 916         mlx5e_grp_vnic_env_update_stats(priv);
 917
 918         /* HW counters */
 919         memset(in, 0, sizeof(in));
 920
 921         MLX5_SET(query_vport_counter_in, in, opcode,
 922             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 923         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 924         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 925
 926         memset(out, 0, outlen);
 927
 928         /* get number of out-of-buffer drops first */
 929         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 930             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 931             &rx_out_of_buffer) == 0) {
 932                 s->rx_out_of_buffer = rx_out_of_buffer;
 933         }
 934
 935         /* get port statistics */
 936         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 937 #define MLX5_GET_CTR(out, x) \
 938         MLX5_GET64(query_vport_counter_out, out, x)
 939
 940                 s->rx_error_packets =
 941                     MLX5_GET_CTR(out, received_errors.packets);
 942                 s->rx_error_bytes =
 943                     MLX5_GET_CTR(out, received_errors.octets);
 944                 s->tx_error_packets =
 945                     MLX5_GET_CTR(out, transmit_errors.packets);
 946                 s->tx_error_bytes =
 947                     MLX5_GET_CTR(out, transmit_errors.octets);
 948
 949                 s->rx_unicast_packets =
 950                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 951                 s->rx_unicast_bytes =
 952                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 953                 s->tx_unicast_packets =
 954                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 955                 s->tx_unicast_bytes =
 956                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 957
 958                 s->rx_multicast_packets =
 959                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 960                 s->rx_multicast_bytes =
 961                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 962                 s->tx_multicast_packets =
 963                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 964                 s->tx_multicast_bytes =
 965                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 966
 967                 s->rx_broadcast_packets =
 968                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 969                 s->rx_broadcast_bytes =
 970                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 971                 s->tx_broadcast_packets =
 972                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 973                 s->tx_broadcast_bytes =
 974                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 975
 976                 s->tx_packets = s->tx_unicast_packets +
 977                     s->tx_multicast_packets + s->tx_broadcast_packets;
 978                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 979                     s->tx_broadcast_bytes;
 980
 981                 /* Update calculated offload counters */
 982                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 983                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 984         }
 985
 986         /* Get physical port counters */
 987         mlx5e_update_pport_counters(priv);
 988
 989         s->tx_jumbo_packets =
 990             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 991             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 992             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 993             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 994
 995 #if (__FreeBSD_version < 1100000)
 996         /* no get_counters interface in fbsd 10 */
 997         ifp->if_ipackets = s->rx_packets;
 998         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
 999             priv->stats.pport.out_of_range_len +
1000             priv->stats.pport.too_long_errors +
1001             priv->stats.pport.check_seq_err +
1002             priv->stats.pport.alignment_err;
1003         ifp->if_iqdrops = s->rx_out_of_buffer;
1004         ifp->if_opackets = s->tx_packets;
1005         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1006         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1007         ifp->if_ibytes = s->rx_bytes;
1008         ifp->if_obytes = s->tx_bytes;
1009         ifp->if_collisions =
1010             priv->stats.pport.collisions;
1011 #endif
1012
1013 free_out:
1014         kvfree(out);
1015
1016         /* Update diagnostics, if any */
1017         if (priv->params_ethtool.diag_pci_enable ||
1018             priv->params_ethtool.diag_general_enable) {
1019                 int error = mlx5_core_get_diagnostics_full(mdev,
1020                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1021                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1022                 if (error != 0)
1023                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
1024         }
1025 }
1026
1027 static void
1028 mlx5e_update_stats_work(struct work_struct *work)
1029 {
1030         struct mlx5e_priv *priv;
1031
1032         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
1033         PRIV_LOCK(priv);
1034         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1035                 mlx5e_update_stats_locked(priv);
1036         PRIV_UNLOCK(priv);
1037 }
1038
1039 static void
1040 mlx5e_update_stats(void *arg)
1041 {
1042         struct mlx5e_priv *priv = arg;
1043
1044         queue_work(priv->wq, &priv->update_stats_work);
1045
1046         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1047 }
1048
1049 static void
1050 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1051     enum mlx5_dev_event event)
1052 {
1053         switch (event) {
1054         case MLX5_DEV_EVENT_PORT_UP:
1055         case MLX5_DEV_EVENT_PORT_DOWN:
1056                 queue_work(priv->wq, &priv->update_carrier_work);
1057                 break;
1058
1059         default:
1060                 break;
1061         }
1062 }
1063
1064 static void
1065 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1066     enum mlx5_dev_event event, unsigned long param)
1067 {
1068         struct mlx5e_priv *priv = vpriv;
1069
1070         mtx_lock(&priv->async_events_mtx);
1071         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1072                 mlx5e_async_event_sub(priv, event);
1073         mtx_unlock(&priv->async_events_mtx);
1074 }
1075
1076 static void
1077 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1078 {
1079         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1080 }
1081
1082 static void
1083 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1084 {
1085         mtx_lock(&priv->async_events_mtx);
1086         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1087         mtx_unlock(&priv->async_events_mtx);
1088 }
1089
1090 static const char *mlx5e_rq_stats_desc[] = {
1091         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1092 };
1093
1094 static int
1095 mlx5e_create_rq(struct mlx5e_channel *c,
1096     struct mlx5e_rq_param *param,
1097     struct mlx5e_rq *rq)
1098 {
1099         struct mlx5e_priv *priv = c->priv;
1100         struct mlx5_core_dev *mdev = priv->mdev;
1101         char buffer[16];
1102         void *rqc = param->rqc;
1103         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1104         int wq_sz;
1105         int err;
1106         int i;
1107         u32 nsegs, wqe_sz;
1108
1109         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1110         if (err != 0)
1111                 goto done;
1112
1113         /* Create DMA descriptor TAG */
1114         if ((err = -bus_dma_tag_create(
1115             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1116             1,                          /* any alignment */
1117             0,                          /* no boundary */
1118             BUS_SPACE_MAXADDR,          /* lowaddr */
1119             BUS_SPACE_MAXADDR,          /* highaddr */
1120             NULL, NULL,                 /* filter, filterarg */
1121             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1122             nsegs,                      /* nsegments */
1123             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1124             0,                          /* flags */
1125             NULL, NULL,                 /* lockfunc, lockfuncarg */
1126             &rq->dma_tag)))
1127                 goto done;
1128
1129         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1130             &rq->wq_ctrl);
1131         if (err)
1132                 goto err_free_dma_tag;
1133
1134         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1135
1136         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1137         if (err != 0)
1138                 goto err_rq_wq_destroy;
1139
1140         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1141
1142         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
1143         if (err)
1144                 goto err_rq_wq_destroy;
1145
1146         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1147         for (i = 0; i != wq_sz; i++) {
1148                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1149 #if (MLX5E_MAX_RX_SEGS == 1)
1150                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
1151 #else
1152                 int j;
1153 #endif
1154
1155                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1156                 if (err != 0) {
1157                         while (i--)
1158                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1159                         goto err_rq_mbuf_free;
1160                 }
1161
1162                 /* set value for constant fields */
1163 #if (MLX5E_MAX_RX_SEGS == 1)
1164                 wqe->data[0].lkey = c->mkey_be;
1165                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
1166 #else
1167                 for (j = 0; j < rq->nsegs; j++)
1168                         wqe->data[j].lkey = c->mkey_be;
1169 #endif
1170         }
1171
1172         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1173         if (priv->params.rx_cq_moderation_mode < 2) {
1174                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1175         } else {
1176                 void *cqc = container_of(param,
1177                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1178
1179                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1180                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1181                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1182                         break;
1183                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1184                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1185                         break;
1186                 default:
1187                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1188                         break;
1189                 }
1190         }
1191
1192         rq->ifp = c->ifp;
1193         rq->channel = c;
1194         rq->ix = c->ix;
1195
1196         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1197         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1198             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1199             rq->stats.arg);
1200         return (0);
1201
1202 err_rq_mbuf_free:
1203         free(rq->mbuf, M_MLX5EN);
1204         tcp_lro_free(&rq->lro);
1205 err_rq_wq_destroy:
1206         mlx5_wq_destroy(&rq->wq_ctrl);
1207 err_free_dma_tag:
1208         bus_dma_tag_destroy(rq->dma_tag);
1209 done:
1210         return (err);
1211 }
1212
1213 static void
1214 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1215 {
1216         int wq_sz;
1217         int i;
1218
1219         /* destroy all sysctl nodes */
1220         sysctl_ctx_free(&rq->stats.ctx);
1221
1222         /* free leftover LRO packets, if any */
1223         tcp_lro_free(&rq->lro);
1224
1225         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1226         for (i = 0; i != wq_sz; i++) {
1227                 if (rq->mbuf[i].mbuf != NULL) {
1228                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1229                         m_freem(rq->mbuf[i].mbuf);
1230                 }
1231                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1232         }
1233         free(rq->mbuf, M_MLX5EN);
1234         mlx5_wq_destroy(&rq->wq_ctrl);
1235 }
1236
1237 static int
1238 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1239 {
1240         struct mlx5e_channel *c = rq->channel;
1241         struct mlx5e_priv *priv = c->priv;
1242         struct mlx5_core_dev *mdev = priv->mdev;
1243
1244         void *in;
1245         void *rqc;
1246         void *wq;
1247         int inlen;
1248         int err;
1249
1250         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1251             sizeof(u64) * rq->wq_ctrl.buf.npages;
1252         in = mlx5_vzalloc(inlen);
1253         if (in == NULL)
1254                 return (-ENOMEM);
1255
1256         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1257         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1258
1259         memcpy(rqc, param->rqc, sizeof(param->rqc));
1260
1261         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1262         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1263         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1264         if (priv->counter_set_id >= 0)
1265                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1266         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1267             PAGE_SHIFT);
1268         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1269
1270         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1271             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1272
1273         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1274
1275         kvfree(in);
1276
1277         return (err);
1278 }
1279
1280 static int
1281 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1282 {
1283         struct mlx5e_channel *c = rq->channel;
1284         struct mlx5e_priv *priv = c->priv;
1285         struct mlx5_core_dev *mdev = priv->mdev;
1286
1287         void *in;
1288         void *rqc;
1289         int inlen;
1290         int err;
1291
1292         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1293         in = mlx5_vzalloc(inlen);
1294         if (in == NULL)
1295                 return (-ENOMEM);
1296
1297         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1298
1299         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1300         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1301         MLX5_SET(rqc, rqc, state, next_state);
1302
1303         err = mlx5_core_modify_rq(mdev, in, inlen);
1304
1305         kvfree(in);
1306
1307         return (err);
1308 }
1309
1310 static void
1311 mlx5e_disable_rq(struct mlx5e_rq *rq)
1312 {
1313         struct mlx5e_channel *c = rq->channel;
1314         struct mlx5e_priv *priv = c->priv;
1315         struct mlx5_core_dev *mdev = priv->mdev;
1316
1317         mlx5_core_destroy_rq(mdev, rq->rqn);
1318 }
1319
1320 static int
1321 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1322 {
1323         struct mlx5e_channel *c = rq->channel;
1324         struct mlx5e_priv *priv = c->priv;
1325         struct mlx5_wq_ll *wq = &rq->wq;
1326         int i;
1327
1328         for (i = 0; i < 1000; i++) {
1329                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1330                         return (0);
1331
1332                 msleep(4);
1333         }
1334         return (-ETIMEDOUT);
1335 }
1336
1337 static int
1338 mlx5e_open_rq(struct mlx5e_channel *c,
1339     struct mlx5e_rq_param *param,
1340     struct mlx5e_rq *rq)
1341 {
1342         int err;
1343
1344         err = mlx5e_create_rq(c, param, rq);
1345         if (err)
1346                 return (err);
1347
1348         err = mlx5e_enable_rq(rq, param);
1349         if (err)
1350                 goto err_destroy_rq;
1351
1352         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1353         if (err)
1354                 goto err_disable_rq;
1355
1356         c->rq.enabled = 1;
1357
1358         return (0);
1359
1360 err_disable_rq:
1361         mlx5e_disable_rq(rq);
1362 err_destroy_rq:
1363         mlx5e_destroy_rq(rq);
1364
1365         return (err);
1366 }
1367
1368 static void
1369 mlx5e_close_rq(struct mlx5e_rq *rq)
1370 {
1371         mtx_lock(&rq->mtx);
1372         rq->enabled = 0;
1373         callout_stop(&rq->watchdog);
1374         mtx_unlock(&rq->mtx);
1375
1376         callout_drain(&rq->watchdog);
1377
1378         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1379 }
1380
1381 static void
1382 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1383 {
1384
1385         mlx5e_disable_rq(rq);
1386         mlx5e_close_cq(&rq->cq);
1387         cancel_work_sync(&rq->dim.work);
1388         mlx5e_destroy_rq(rq);
1389 }
1390
1391 void
1392 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1393 {
1394         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1395         int x;
1396
1397         for (x = 0; x != wq_sz; x++) {
1398                 if (sq->mbuf[x].mbuf != NULL) {
1399                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1400                         m_freem(sq->mbuf[x].mbuf);
1401                 }
1402                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1403         }
1404         free(sq->mbuf, M_MLX5EN);
1405 }
1406
1407 int
1408 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1409 {
1410         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1411         int err;
1412         int x;
1413
1414         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1415
1416         /* Create DMA descriptor MAPs */
1417         for (x = 0; x != wq_sz; x++) {
1418                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1419                 if (err != 0) {
1420                         while (x--)
1421                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1422                         free(sq->mbuf, M_MLX5EN);
1423                         return (err);
1424                 }
1425         }
1426         return (0);
1427 }
1428
1429 static const char *mlx5e_sq_stats_desc[] = {
1430         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1431 };
1432
1433 void
1434 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1435 {
1436         sq->max_inline = sq->priv->params.tx_max_inline;
1437         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1438
1439         /*
1440          * Check if trust state is DSCP or if inline mode is NONE which
1441          * indicates CX-5 or newer hardware.
1442          */
1443         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1444             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1445                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1446                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1447                 else
1448                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1449         } else {
1450                 sq->min_insert_caps = 0;
1451         }
1452 }
1453
1454 static void
1455 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1456 {
1457         int i;
1458
1459         for (i = 0; i != c->num_tc; i++) {
1460                 mtx_lock(&c->sq[i].lock);
1461                 mlx5e_update_sq_inline(&c->sq[i]);
1462                 mtx_unlock(&c->sq[i].lock);
1463         }
1464 }
1465
1466 void
1467 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1468 {
1469         int i;
1470
1471         /* check if channels are closed */
1472         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1473                 return;
1474
1475         for (i = 0; i < priv->params.num_channels; i++)
1476                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1477 }
1478
1479 static int
1480 mlx5e_create_sq(struct mlx5e_channel *c,
1481     int tc,
1482     struct mlx5e_sq_param *param,
1483     struct mlx5e_sq *sq)
1484 {
1485         struct mlx5e_priv *priv = c->priv;
1486         struct mlx5_core_dev *mdev = priv->mdev;
1487         char buffer[16];
1488         void *sqc = param->sqc;
1489         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1490         int err;
1491
1492         /* Create DMA descriptor TAG */
1493         if ((err = -bus_dma_tag_create(
1494             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1495             1,                          /* any alignment */
1496             0,                          /* no boundary */
1497             BUS_SPACE_MAXADDR,          /* lowaddr */
1498             BUS_SPACE_MAXADDR,          /* highaddr */
1499             NULL, NULL,                 /* filter, filterarg */
1500             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1501             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1502             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1503             0,                          /* flags */
1504             NULL, NULL,                 /* lockfunc, lockfuncarg */
1505             &sq->dma_tag)))
1506                 goto done;
1507
1508         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1509         if (err)
1510                 goto err_free_dma_tag;
1511
1512         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1513             &sq->wq_ctrl);
1514         if (err)
1515                 goto err_unmap_free_uar;
1516
1517         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1518         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1519
1520         err = mlx5e_alloc_sq_db(sq);
1521         if (err)
1522                 goto err_sq_wq_destroy;
1523
1524         sq->mkey_be = c->mkey_be;
1525         sq->ifp = priv->ifp;
1526         sq->priv = priv;
1527         sq->tc = tc;
1528
1529         mlx5e_update_sq_inline(sq);
1530
1531         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1532         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1533             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1534             sq->stats.arg);
1535
1536         return (0);
1537
1538 err_sq_wq_destroy:
1539         mlx5_wq_destroy(&sq->wq_ctrl);
1540
1541 err_unmap_free_uar:
1542         mlx5_unmap_free_uar(mdev, &sq->uar);
1543
1544 err_free_dma_tag:
1545         bus_dma_tag_destroy(sq->dma_tag);
1546 done:
1547         return (err);
1548 }
1549
1550 static void
1551 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1552 {
1553         /* destroy all sysctl nodes */
1554         sysctl_ctx_free(&sq->stats.ctx);
1555
1556         mlx5e_free_sq_db(sq);
1557         mlx5_wq_destroy(&sq->wq_ctrl);
1558         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1559 }
1560
1561 int
1562 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1563     int tis_num)
1564 {
1565         void *in;
1566         void *sqc;
1567         void *wq;
1568         int inlen;
1569         int err;
1570
1571         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1572             sizeof(u64) * sq->wq_ctrl.buf.npages;
1573         in = mlx5_vzalloc(inlen);
1574         if (in == NULL)
1575                 return (-ENOMEM);
1576
1577         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1578         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1579
1580         memcpy(sqc, param->sqc, sizeof(param->sqc));
1581
1582         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1583         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1584         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1585         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1586         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1587
1588         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1589         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1590         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1591             PAGE_SHIFT);
1592         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1593
1594         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1595             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1596
1597         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1598
1599         kvfree(in);
1600
1601         return (err);
1602 }
1603
1604 int
1605 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1606 {
1607         void *in;
1608         void *sqc;
1609         int inlen;
1610         int err;
1611
1612         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1613         in = mlx5_vzalloc(inlen);
1614         if (in == NULL)
1615                 return (-ENOMEM);
1616
1617         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1618
1619         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1620         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1621         MLX5_SET(sqc, sqc, state, next_state);
1622
1623         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1624
1625         kvfree(in);
1626
1627         return (err);
1628 }
1629
1630 void
1631 mlx5e_disable_sq(struct mlx5e_sq *sq)
1632 {
1633
1634         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1635 }
1636
1637 static int
1638 mlx5e_open_sq(struct mlx5e_channel *c,
1639     int tc,
1640     struct mlx5e_sq_param *param,
1641     struct mlx5e_sq *sq)
1642 {
1643         int err;
1644
1645         err = mlx5e_create_sq(c, tc, param, sq);
1646         if (err)
1647                 return (err);
1648
1649         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1650         if (err)
1651                 goto err_destroy_sq;
1652
1653         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1654         if (err)
1655                 goto err_disable_sq;
1656
1657         WRITE_ONCE(sq->running, 1);
1658
1659         return (0);
1660
1661 err_disable_sq:
1662         mlx5e_disable_sq(sq);
1663 err_destroy_sq:
1664         mlx5e_destroy_sq(sq);
1665
1666         return (err);
1667 }
1668
1669 static void
1670 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1671 {
1672         /* fill up remainder with NOPs */
1673         while (sq->cev_counter != 0) {
1674                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1675                         if (can_sleep != 0) {
1676                                 mtx_unlock(&sq->lock);
1677                                 msleep(4);
1678                                 mtx_lock(&sq->lock);
1679                         } else {
1680                                 goto done;
1681                         }
1682                 }
1683                 /* send a single NOP */
1684                 mlx5e_send_nop(sq, 1);
1685                 atomic_thread_fence_rel();
1686         }
1687 done:
1688         /* Check if we need to write the doorbell */
1689         if (likely(sq->doorbell.d64 != 0)) {
1690                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1691                 sq->doorbell.d64 = 0;
1692         }
1693 }
1694
1695 void
1696 mlx5e_sq_cev_timeout(void *arg)
1697 {
1698         struct mlx5e_sq *sq = arg;
1699
1700         mtx_assert(&sq->lock, MA_OWNED);
1701
1702         /* check next state */
1703         switch (sq->cev_next_state) {
1704         case MLX5E_CEV_STATE_SEND_NOPS:
1705                 /* fill TX ring with NOPs, if any */
1706                 mlx5e_sq_send_nops_locked(sq, 0);
1707
1708                 /* check if completed */
1709                 if (sq->cev_counter == 0) {
1710                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1711                         return;
1712                 }
1713                 break;
1714         default:
1715                 /* send NOPs on next timeout */
1716                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1717                 break;
1718         }
1719
1720         /* restart timer */
1721         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1722 }
1723
1724 void
1725 mlx5e_drain_sq(struct mlx5e_sq *sq)
1726 {
1727         int error;
1728         struct mlx5_core_dev *mdev= sq->priv->mdev;
1729
1730         /*
1731          * Check if already stopped.
1732          *
1733          * NOTE: Serialization of this function is managed by the
1734          * caller ensuring the priv's state lock is locked or in case
1735          * of rate limit support, a single thread manages drain and
1736          * resume of SQs. The "running" variable can therefore safely
1737          * be read without any locks.
1738          */
1739         if (READ_ONCE(sq->running) == 0)
1740                 return;
1741
1742         /* don't put more packets into the SQ */
1743         WRITE_ONCE(sq->running, 0);
1744
1745         /* serialize access to DMA rings */
1746         mtx_lock(&sq->lock);
1747
1748         /* teardown event factor timer, if any */
1749         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1750         callout_stop(&sq->cev_callout);
1751
1752         /* send dummy NOPs in order to flush the transmit ring */
1753         mlx5e_sq_send_nops_locked(sq, 1);
1754         mtx_unlock(&sq->lock);
1755
1756         /* make sure it is safe to free the callout */
1757         callout_drain(&sq->cev_callout);
1758
1759         /* wait till SQ is empty or link is down */
1760         mtx_lock(&sq->lock);
1761         while (sq->cc != sq->pc &&
1762             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1763             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1764                 mtx_unlock(&sq->lock);
1765                 msleep(1);
1766                 sq->cq.mcq.comp(&sq->cq.mcq);
1767                 mtx_lock(&sq->lock);
1768         }
1769         mtx_unlock(&sq->lock);
1770
1771         /* error out remaining requests */
1772         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1773         if (error != 0) {
1774                 if_printf(sq->ifp,
1775                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1776         }
1777
1778         /* wait till SQ is empty */
1779         mtx_lock(&sq->lock);
1780         while (sq->cc != sq->pc &&
1781                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1782                 mtx_unlock(&sq->lock);
1783                 msleep(1);
1784                 sq->cq.mcq.comp(&sq->cq.mcq);
1785                 mtx_lock(&sq->lock);
1786         }
1787         mtx_unlock(&sq->lock);
1788 }
1789
1790 static void
1791 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1792 {
1793
1794         mlx5e_drain_sq(sq);
1795         mlx5e_disable_sq(sq);
1796         mlx5e_destroy_sq(sq);
1797 }
1798
1799 static int
1800 mlx5e_create_cq(struct mlx5e_priv *priv,
1801     struct mlx5e_cq_param *param,
1802     struct mlx5e_cq *cq,
1803     mlx5e_cq_comp_t *comp,
1804     int eq_ix)
1805 {
1806         struct mlx5_core_dev *mdev = priv->mdev;
1807         struct mlx5_core_cq *mcq = &cq->mcq;
1808         int eqn_not_used;
1809         int irqn;
1810         int err;
1811         u32 i;
1812
1813         param->wq.buf_numa_node = 0;
1814         param->wq.db_numa_node = 0;
1815
1816         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1817             &cq->wq_ctrl);
1818         if (err)
1819                 return (err);
1820
1821         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1822
1823         mcq->cqe_sz = 64;
1824         mcq->set_ci_db = cq->wq_ctrl.db.db;
1825         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1826         *mcq->set_ci_db = 0;
1827         *mcq->arm_db = 0;
1828         mcq->vector = eq_ix;
1829         mcq->comp = comp;
1830         mcq->event = mlx5e_cq_error_event;
1831         mcq->irqn = irqn;
1832         mcq->uar = &priv->cq_uar;
1833
1834         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1835                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1836
1837                 cqe->op_own = 0xf1;
1838         }
1839
1840         cq->priv = priv;
1841
1842         return (0);
1843 }
1844
1845 static void
1846 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1847 {
1848         mlx5_wq_destroy(&cq->wq_ctrl);
1849 }
1850
1851 static int
1852 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1853 {
1854         struct mlx5_core_cq *mcq = &cq->mcq;
1855         void *in;
1856         void *cqc;
1857         int inlen;
1858         int irqn_not_used;
1859         int eqn;
1860         int err;
1861
1862         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1863             sizeof(u64) * cq->wq_ctrl.buf.npages;
1864         in = mlx5_vzalloc(inlen);
1865         if (in == NULL)
1866                 return (-ENOMEM);
1867
1868         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1869
1870         memcpy(cqc, param->cqc, sizeof(param->cqc));
1871
1872         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1873             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1874
1875         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1876
1877         MLX5_SET(cqc, cqc, c_eqn, eqn);
1878         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1879         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1880             PAGE_SHIFT);
1881         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1882
1883         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1884
1885         kvfree(in);
1886
1887         if (err)
1888                 return (err);
1889
1890         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1891
1892         return (0);
1893 }
1894
1895 static void
1896 mlx5e_disable_cq(struct mlx5e_cq *cq)
1897 {
1898
1899         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1900 }
1901
1902 int
1903 mlx5e_open_cq(struct mlx5e_priv *priv,
1904     struct mlx5e_cq_param *param,
1905     struct mlx5e_cq *cq,
1906     mlx5e_cq_comp_t *comp,
1907     int eq_ix)
1908 {
1909         int err;
1910
1911         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1912         if (err)
1913                 return (err);
1914
1915         err = mlx5e_enable_cq(cq, param, eq_ix);
1916         if (err)
1917                 goto err_destroy_cq;
1918
1919         return (0);
1920
1921 err_destroy_cq:
1922         mlx5e_destroy_cq(cq);
1923
1924         return (err);
1925 }
1926
1927 void
1928 mlx5e_close_cq(struct mlx5e_cq *cq)
1929 {
1930         mlx5e_disable_cq(cq);
1931         mlx5e_destroy_cq(cq);
1932 }
1933
1934 static int
1935 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1936     struct mlx5e_channel_param *cparam)
1937 {
1938         int err;
1939         int tc;
1940
1941         for (tc = 0; tc < c->num_tc; tc++) {
1942                 /* open completion queue */
1943                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1944                     &mlx5e_tx_cq_comp, c->ix);
1945                 if (err)
1946                         goto err_close_tx_cqs;
1947         }
1948         return (0);
1949
1950 err_close_tx_cqs:
1951         for (tc--; tc >= 0; tc--)
1952                 mlx5e_close_cq(&c->sq[tc].cq);
1953
1954         return (err);
1955 }
1956
1957 static void
1958 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1959 {
1960         int tc;
1961
1962         for (tc = 0; tc < c->num_tc; tc++)
1963                 mlx5e_close_cq(&c->sq[tc].cq);
1964 }
1965
1966 static int
1967 mlx5e_open_sqs(struct mlx5e_channel *c,
1968     struct mlx5e_channel_param *cparam)
1969 {
1970         int err;
1971         int tc;
1972
1973         for (tc = 0; tc < c->num_tc; tc++) {
1974                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1975                 if (err)
1976                         goto err_close_sqs;
1977         }
1978
1979         return (0);
1980
1981 err_close_sqs:
1982         for (tc--; tc >= 0; tc--)
1983                 mlx5e_close_sq_wait(&c->sq[tc]);
1984
1985         return (err);
1986 }
1987
1988 static void
1989 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1990 {
1991         int tc;
1992
1993         for (tc = 0; tc < c->num_tc; tc++)
1994                 mlx5e_close_sq_wait(&c->sq[tc]);
1995 }
1996
1997 static void
1998 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1999 {
2000         int tc;
2001
2002         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2003
2004         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2005
2006         for (tc = 0; tc < c->num_tc; tc++) {
2007                 struct mlx5e_sq *sq = c->sq + tc;
2008
2009                 mtx_init(&sq->lock, "mlx5tx",
2010                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2011                 mtx_init(&sq->comp_lock, "mlx5comp",
2012                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2013
2014                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2015
2016                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
2017
2018                 /* ensure the TX completion event factor is not zero */
2019                 if (sq->cev_factor == 0)
2020                         sq->cev_factor = 1;
2021         }
2022 }
2023
2024 static void
2025 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
2026 {
2027         int tc;
2028
2029         mtx_destroy(&c->rq.mtx);
2030
2031         for (tc = 0; tc < c->num_tc; tc++) {
2032                 mtx_destroy(&c->sq[tc].lock);
2033                 mtx_destroy(&c->sq[tc].comp_lock);
2034         }
2035 }
2036
2037 static int
2038 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2039     struct mlx5e_channel_param *cparam,
2040     struct mlx5e_channel *c)
2041 {
2042         int err;
2043
2044         memset(c, 0, sizeof(*c));
2045
2046         c->priv = priv;
2047         c->ix = ix;
2048         c->ifp = priv->ifp;
2049         c->mkey_be = cpu_to_be32(priv->mr.key);
2050         c->num_tc = priv->num_tc;
2051
2052         /* init mutexes */
2053         mlx5e_chan_mtx_init(c);
2054
2055         /* open transmit completion queue */
2056         err = mlx5e_open_tx_cqs(c, cparam);
2057         if (err)
2058                 goto err_free;
2059
2060         /* open receive completion queue */
2061         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2062             &mlx5e_rx_cq_comp, c->ix);
2063         if (err)
2064                 goto err_close_tx_cqs;
2065
2066         err = mlx5e_open_sqs(c, cparam);
2067         if (err)
2068                 goto err_close_rx_cq;
2069
2070         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2071         if (err)
2072                 goto err_close_sqs;
2073
2074         /* poll receive queue initially */
2075         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2076
2077         return (0);
2078
2079 err_close_sqs:
2080         mlx5e_close_sqs_wait(c);
2081
2082 err_close_rx_cq:
2083         mlx5e_close_cq(&c->rq.cq);
2084
2085 err_close_tx_cqs:
2086         mlx5e_close_tx_cqs(c);
2087
2088 err_free:
2089         /* destroy mutexes */
2090         mlx5e_chan_mtx_destroy(c);
2091         return (err);
2092 }
2093
2094 static void
2095 mlx5e_close_channel(struct mlx5e_channel *c)
2096 {
2097         mlx5e_close_rq(&c->rq);
2098 }
2099
2100 static void
2101 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2102 {
2103         mlx5e_close_rq_wait(&c->rq);
2104         mlx5e_close_sqs_wait(c);
2105         mlx5e_close_tx_cqs(c);
2106         /* destroy mutexes */
2107         mlx5e_chan_mtx_destroy(c);
2108 }
2109
2110 static int
2111 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2112 {
2113         u32 r, n;
2114
2115         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2116             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2117         if (r > MJUM16BYTES)
2118                 return (-ENOMEM);
2119
2120         if (r > MJUM9BYTES)
2121                 r = MJUM16BYTES;
2122         else if (r > MJUMPAGESIZE)
2123                 r = MJUM9BYTES;
2124         else if (r > MCLBYTES)
2125                 r = MJUMPAGESIZE;
2126         else
2127                 r = MCLBYTES;
2128
2129         /*
2130          * n + 1 must be a power of two, because stride size must be.
2131          * Stride size is 16 * (n + 1), as the first segment is
2132          * control.
2133          */
2134         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2135                 ;
2136
2137         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2138                 return (-ENOMEM);
2139
2140         *wqe_sz = r;
2141         *nsegs = n;
2142         return (0);
2143 }
2144
2145 static void
2146 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2147     struct mlx5e_rq_param *param)
2148 {
2149         void *rqc = param->rqc;
2150         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2151         u32 wqe_sz, nsegs;
2152
2153         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2154         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2155         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2156         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2157             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2158         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2159         MLX5_SET(wq, wq, pd, priv->pdn);
2160
2161         param->wq.buf_numa_node = 0;
2162         param->wq.db_numa_node = 0;
2163         param->wq.linear = 1;
2164 }
2165
2166 static void
2167 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2168     struct mlx5e_sq_param *param)
2169 {
2170         void *sqc = param->sqc;
2171         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2172
2173         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2174         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2175         MLX5_SET(wq, wq, pd, priv->pdn);
2176
2177         param->wq.buf_numa_node = 0;
2178         param->wq.db_numa_node = 0;
2179         param->wq.linear = 1;
2180 }
2181
2182 static void
2183 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2184     struct mlx5e_cq_param *param)
2185 {
2186         void *cqc = param->cqc;
2187
2188         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2189 }
2190
2191 static void
2192 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2193 {
2194
2195         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2196
2197         /* apply LRO restrictions */
2198         if (priv->params.hw_lro_en &&
2199             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2200                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2201         }
2202 }
2203
2204 static void
2205 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2206     struct mlx5e_cq_param *param)
2207 {
2208         struct net_dim_cq_moder curr;
2209         void *cqc = param->cqc;
2210
2211         /*
2212          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2213          * format is more beneficial for FreeBSD use case.
2214          *
2215          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2216          * in mlx5e_decompress_cqe.
2217          */
2218         if (priv->params.cqe_zipping_en) {
2219                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2220                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2221         }
2222
2223         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2224
2225         switch (priv->params.rx_cq_moderation_mode) {
2226         case 0:
2227                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2228                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2229                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2230                 break;
2231         case 1:
2232                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2233                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2234                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2235                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2236                 else
2237                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2238                 break;
2239         case 2:
2240                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2241                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2242                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2243                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2244                 break;
2245         case 3:
2246                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2247                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2248                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2249                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2250                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2251                 else
2252                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2253                 break;
2254         default:
2255                 break;
2256         }
2257
2258         mlx5e_dim_build_cq_param(priv, param);
2259
2260         mlx5e_build_common_cq_param(priv, param);
2261 }
2262
2263 static void
2264 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2265     struct mlx5e_cq_param *param)
2266 {
2267         void *cqc = param->cqc;
2268
2269         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2270         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2271         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2272
2273         switch (priv->params.tx_cq_moderation_mode) {
2274         case 0:
2275                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2276                 break;
2277         default:
2278                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2279                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2280                 else
2281                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2282                 break;
2283         }
2284
2285         mlx5e_build_common_cq_param(priv, param);
2286 }
2287
2288 static void
2289 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2290     struct mlx5e_channel_param *cparam)
2291 {
2292         memset(cparam, 0, sizeof(*cparam));
2293
2294         mlx5e_build_rq_param(priv, &cparam->rq);
2295         mlx5e_build_sq_param(priv, &cparam->sq);
2296         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2297         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2298 }
2299
2300 static int
2301 mlx5e_open_channels(struct mlx5e_priv *priv)
2302 {
2303         struct mlx5e_channel_param cparam;
2304         int err;
2305         int i;
2306         int j;
2307
2308         mlx5e_build_channel_param(priv, &cparam);
2309         for (i = 0; i < priv->params.num_channels; i++) {
2310                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2311                 if (err)
2312                         goto err_close_channels;
2313         }
2314
2315         for (j = 0; j < priv->params.num_channels; j++) {
2316                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2317                 if (err)
2318                         goto err_close_channels;
2319         }
2320
2321         return (0);
2322
2323 err_close_channels:
2324         while (i--) {
2325                 mlx5e_close_channel(&priv->channel[i]);
2326                 mlx5e_close_channel_wait(&priv->channel[i]);
2327         }
2328         return (err);
2329 }
2330
2331 static void
2332 mlx5e_close_channels(struct mlx5e_priv *priv)
2333 {
2334         int i;
2335
2336         for (i = 0; i < priv->params.num_channels; i++)
2337                 mlx5e_close_channel(&priv->channel[i]);
2338         for (i = 0; i < priv->params.num_channels; i++)
2339                 mlx5e_close_channel_wait(&priv->channel[i]);
2340 }
2341
2342 static int
2343 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2344 {
2345
2346         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2347                 uint8_t cq_mode;
2348
2349                 switch (priv->params.tx_cq_moderation_mode) {
2350                 case 0:
2351                 case 2:
2352                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2353                         break;
2354                 default:
2355                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2356                         break;
2357                 }
2358
2359                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2360                     priv->params.tx_cq_moderation_usec,
2361                     priv->params.tx_cq_moderation_pkts,
2362                     cq_mode));
2363         }
2364
2365         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2366             priv->params.tx_cq_moderation_usec,
2367             priv->params.tx_cq_moderation_pkts));
2368 }
2369
2370 static int
2371 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2372 {
2373
2374         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2375                 uint8_t cq_mode;
2376                 uint8_t dim_mode;
2377                 int retval;
2378
2379                 switch (priv->params.rx_cq_moderation_mode) {
2380                 case 0:
2381                 case 2:
2382                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2383                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2384                         break;
2385                 default:
2386                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2387                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2388                         break;
2389                 }
2390
2391                 /* tear down dynamic interrupt moderation */
2392                 mtx_lock(&rq->mtx);
2393                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2394                 mtx_unlock(&rq->mtx);
2395
2396                 /* wait for dynamic interrupt moderation work task, if any */
2397                 cancel_work_sync(&rq->dim.work);
2398
2399                 if (priv->params.rx_cq_moderation_mode >= 2) {
2400                         struct net_dim_cq_moder curr;
2401
2402                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2403
2404                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2405                             curr.usec, curr.pkts, cq_mode);
2406
2407                         /* set dynamic interrupt moderation mode and zero defaults */
2408                         mtx_lock(&rq->mtx);
2409                         rq->dim.mode = dim_mode;
2410                         rq->dim.state = 0;
2411                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2412                         mtx_unlock(&rq->mtx);
2413                 } else {
2414                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2415                             priv->params.rx_cq_moderation_usec,
2416                             priv->params.rx_cq_moderation_pkts,
2417                             cq_mode);
2418                 }
2419                 return (retval);
2420         }
2421
2422         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2423             priv->params.rx_cq_moderation_usec,
2424             priv->params.rx_cq_moderation_pkts));
2425 }
2426
2427 static int
2428 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2429 {
2430         int err;
2431         int i;
2432
2433         err = mlx5e_refresh_rq_params(priv, &c->rq);
2434         if (err)
2435                 goto done;
2436
2437         for (i = 0; i != c->num_tc; i++) {
2438                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2439                 if (err)
2440                         goto done;
2441         }
2442 done:
2443         return (err);
2444 }
2445
2446 int
2447 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2448 {
2449         int i;
2450
2451         /* check if channels are closed */
2452         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2453                 return (EINVAL);
2454
2455         for (i = 0; i < priv->params.num_channels; i++) {
2456                 int err;
2457
2458                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2459                 if (err)
2460                         return (err);
2461         }
2462         return (0);
2463 }
2464
2465 static int
2466 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2467 {
2468         struct mlx5_core_dev *mdev = priv->mdev;
2469         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2470         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2471
2472         memset(in, 0, sizeof(in));
2473
2474         MLX5_SET(tisc, tisc, prio, tc);
2475         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2476
2477         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2478 }
2479
2480 static void
2481 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2482 {
2483         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2484 }
2485
2486 static int
2487 mlx5e_open_tises(struct mlx5e_priv *priv)
2488 {
2489         int num_tc = priv->num_tc;
2490         int err;
2491         int tc;
2492
2493         for (tc = 0; tc < num_tc; tc++) {
2494                 err = mlx5e_open_tis(priv, tc);
2495                 if (err)
2496                         goto err_close_tises;
2497         }
2498
2499         return (0);
2500
2501 err_close_tises:
2502         for (tc--; tc >= 0; tc--)
2503                 mlx5e_close_tis(priv, tc);
2504
2505         return (err);
2506 }
2507
2508 static void
2509 mlx5e_close_tises(struct mlx5e_priv *priv)
2510 {
2511         int num_tc = priv->num_tc;
2512         int tc;
2513
2514         for (tc = 0; tc < num_tc; tc++)
2515                 mlx5e_close_tis(priv, tc);
2516 }
2517
2518 static int
2519 mlx5e_open_rqt(struct mlx5e_priv *priv)
2520 {
2521         struct mlx5_core_dev *mdev = priv->mdev;
2522         u32 *in;
2523         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2524         void *rqtc;
2525         int inlen;
2526         int err;
2527         int sz;
2528         int i;
2529
2530         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2531
2532         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2533         in = mlx5_vzalloc(inlen);
2534         if (in == NULL)
2535                 return (-ENOMEM);
2536         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2537
2538         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2539         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2540
2541         for (i = 0; i < sz; i++) {
2542                 int ix = i;
2543 #ifdef RSS
2544                 ix = rss_get_indirection_to_bucket(ix);
2545 #endif
2546                 /* ensure we don't overflow */
2547                 ix %= priv->params.num_channels;
2548
2549                 /* apply receive side scaling stride, if any */
2550                 ix -= ix % (int)priv->params.channels_rsss;
2551
2552                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2553         }
2554
2555         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2556
2557         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2558         if (!err)
2559                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2560
2561         kvfree(in);
2562
2563         return (err);
2564 }
2565
2566 static void
2567 mlx5e_close_rqt(struct mlx5e_priv *priv)
2568 {
2569         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2570         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2571
2572         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2573         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2574
2575         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2576 }
2577
2578 static void
2579 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2580 {
2581         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2582         __be32 *hkey;
2583
2584         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2585
2586 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2587
2588 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2589                           MLX5_HASH_FIELD_SEL_DST_IP)
2590
2591 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2592                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2593                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2594                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2595
2596 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2597                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2598                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2599
2600         if (priv->params.hw_lro_en) {
2601                 MLX5_SET(tirc, tirc, lro_enable_mask,
2602                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2603                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2604                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2605                     (priv->params.lro_wqe_sz -
2606                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2607                 /* TODO: add the option to choose timer value dynamically */
2608                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2609                     MLX5_CAP_ETH(priv->mdev,
2610                     lro_timer_supported_periods[2]));
2611         }
2612
2613         /* setup parameters for hashing TIR type, if any */
2614         switch (tt) {
2615         case MLX5E_TT_ANY:
2616                 MLX5_SET(tirc, tirc, disp_type,
2617                     MLX5_TIRC_DISP_TYPE_DIRECT);
2618                 MLX5_SET(tirc, tirc, inline_rqn,
2619                     priv->channel[0].rq.rqn);
2620                 break;
2621         default:
2622                 MLX5_SET(tirc, tirc, disp_type,
2623                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2624                 MLX5_SET(tirc, tirc, indirect_table,
2625                     priv->rqtn);
2626                 MLX5_SET(tirc, tirc, rx_hash_fn,
2627                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2628                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2629 #ifdef RSS
2630                 /*
2631                  * The FreeBSD RSS implementation does currently not
2632                  * support symmetric Toeplitz hashes:
2633                  */
2634                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2635                 rss_getkey((uint8_t *)hkey);
2636 #else
2637                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2638                 hkey[0] = cpu_to_be32(0xD181C62C);
2639                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2640                 hkey[2] = cpu_to_be32(0x1983A2FC);
2641                 hkey[3] = cpu_to_be32(0x943E1ADB);
2642                 hkey[4] = cpu_to_be32(0xD9389E6B);
2643                 hkey[5] = cpu_to_be32(0xD1039C2C);
2644                 hkey[6] = cpu_to_be32(0xA74499AD);
2645                 hkey[7] = cpu_to_be32(0x593D56D9);
2646                 hkey[8] = cpu_to_be32(0xF3253C06);
2647                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2648 #endif
2649                 break;
2650         }
2651
2652         switch (tt) {
2653         case MLX5E_TT_IPV4_TCP:
2654                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2655                     MLX5_L3_PROT_TYPE_IPV4);
2656                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2657                     MLX5_L4_PROT_TYPE_TCP);
2658 #ifdef RSS
2659                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2660                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661                             MLX5_HASH_IP);
2662                 } else
2663 #endif
2664                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2665                     MLX5_HASH_ALL);
2666                 break;
2667
2668         case MLX5E_TT_IPV6_TCP:
2669                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2670                     MLX5_L3_PROT_TYPE_IPV6);
2671                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2672                     MLX5_L4_PROT_TYPE_TCP);
2673 #ifdef RSS
2674                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2675                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2676                             MLX5_HASH_IP);
2677                 } else
2678 #endif
2679                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2680                     MLX5_HASH_ALL);
2681                 break;
2682
2683         case MLX5E_TT_IPV4_UDP:
2684                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2685                     MLX5_L3_PROT_TYPE_IPV4);
2686                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2687                     MLX5_L4_PROT_TYPE_UDP);
2688 #ifdef RSS
2689                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2690                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2691                             MLX5_HASH_IP);
2692                 } else
2693 #endif
2694                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695                     MLX5_HASH_ALL);
2696                 break;
2697
2698         case MLX5E_TT_IPV6_UDP:
2699                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700                     MLX5_L3_PROT_TYPE_IPV6);
2701                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2702                     MLX5_L4_PROT_TYPE_UDP);
2703 #ifdef RSS
2704                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2705                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2706                             MLX5_HASH_IP);
2707                 } else
2708 #endif
2709                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710                     MLX5_HASH_ALL);
2711                 break;
2712
2713         case MLX5E_TT_IPV4_IPSEC_AH:
2714                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2715                     MLX5_L3_PROT_TYPE_IPV4);
2716                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2717                     MLX5_HASH_IP_IPSEC_SPI);
2718                 break;
2719
2720         case MLX5E_TT_IPV6_IPSEC_AH:
2721                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2722                     MLX5_L3_PROT_TYPE_IPV6);
2723                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2724                     MLX5_HASH_IP_IPSEC_SPI);
2725                 break;
2726
2727         case MLX5E_TT_IPV4_IPSEC_ESP:
2728                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2729                     MLX5_L3_PROT_TYPE_IPV4);
2730                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2731                     MLX5_HASH_IP_IPSEC_SPI);
2732                 break;
2733
2734         case MLX5E_TT_IPV6_IPSEC_ESP:
2735                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2736                     MLX5_L3_PROT_TYPE_IPV6);
2737                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2738                     MLX5_HASH_IP_IPSEC_SPI);
2739                 break;
2740
2741         case MLX5E_TT_IPV4:
2742                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2743                     MLX5_L3_PROT_TYPE_IPV4);
2744                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2745                     MLX5_HASH_IP);
2746                 break;
2747
2748         case MLX5E_TT_IPV6:
2749                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2750                     MLX5_L3_PROT_TYPE_IPV6);
2751                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2752                     MLX5_HASH_IP);
2753                 break;
2754
2755         default:
2756                 break;
2757         }
2758 }
2759
2760 static int
2761 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2762 {
2763         struct mlx5_core_dev *mdev = priv->mdev;
2764         u32 *in;
2765         void *tirc;
2766         int inlen;
2767         int err;
2768
2769         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2770         in = mlx5_vzalloc(inlen);
2771         if (in == NULL)
2772                 return (-ENOMEM);
2773         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2774
2775         mlx5e_build_tir_ctx(priv, tirc, tt);
2776
2777         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2778
2779         kvfree(in);
2780
2781         return (err);
2782 }
2783
2784 static void
2785 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2786 {
2787         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2788 }
2789
2790 static int
2791 mlx5e_open_tirs(struct mlx5e_priv *priv)
2792 {
2793         int err;
2794         int i;
2795
2796         for (i = 0; i < MLX5E_NUM_TT; i++) {
2797                 err = mlx5e_open_tir(priv, i);
2798                 if (err)
2799                         goto err_close_tirs;
2800         }
2801
2802         return (0);
2803
2804 err_close_tirs:
2805         for (i--; i >= 0; i--)
2806                 mlx5e_close_tir(priv, i);
2807
2808         return (err);
2809 }
2810
2811 static void
2812 mlx5e_close_tirs(struct mlx5e_priv *priv)
2813 {
2814         int i;
2815
2816         for (i = 0; i < MLX5E_NUM_TT; i++)
2817                 mlx5e_close_tir(priv, i);
2818 }
2819
2820 /*
2821  * SW MTU does not include headers,
2822  * HW MTU includes all headers and checksums.
2823  */
2824 static int
2825 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2826 {
2827         struct mlx5e_priv *priv = ifp->if_softc;
2828         struct mlx5_core_dev *mdev = priv->mdev;
2829         int hw_mtu;
2830         int err;
2831
2832         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2833
2834         err = mlx5_set_port_mtu(mdev, hw_mtu);
2835         if (err) {
2836                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2837                     __func__, sw_mtu, err);
2838                 return (err);
2839         }
2840
2841         /* Update vport context MTU */
2842         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2843         if (err) {
2844                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2845                     __func__, err);
2846         }
2847
2848         ifp->if_mtu = sw_mtu;
2849
2850         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2851         if (err || !hw_mtu) {
2852                 /* fallback to port oper mtu */
2853                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2854         }
2855         if (err) {
2856                 if_printf(ifp, "Query port MTU, after setting new "
2857                     "MTU value, failed\n");
2858                 return (err);
2859         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2860                 err = -E2BIG,
2861                 if_printf(ifp, "Port MTU %d is smaller than "
2862                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2863         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2864                 err = -EINVAL;
2865                 if_printf(ifp, "Port MTU %d is bigger than "
2866                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2867         }
2868         priv->params_ethtool.hw_mtu = hw_mtu;
2869
2870         return (err);
2871 }
2872
2873 int
2874 mlx5e_open_locked(struct ifnet *ifp)
2875 {
2876         struct mlx5e_priv *priv = ifp->if_softc;
2877         int err;
2878         u16 set_id;
2879
2880         /* check if already opened */
2881         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2882                 return (0);
2883
2884 #ifdef RSS
2885         if (rss_getnumbuckets() > priv->params.num_channels) {
2886                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2887                     "channels(%u) available\n", rss_getnumbuckets(),
2888                     priv->params.num_channels);
2889         }
2890 #endif
2891         err = mlx5e_open_tises(priv);
2892         if (err) {
2893                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2894                     __func__, err);
2895                 return (err);
2896         }
2897         err = mlx5_vport_alloc_q_counter(priv->mdev,
2898             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2899         if (err) {
2900                 if_printf(priv->ifp,
2901                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2902                     __func__, err);
2903                 goto err_close_tises;
2904         }
2905         /* store counter set ID */
2906         priv->counter_set_id = set_id;
2907
2908         err = mlx5e_open_channels(priv);
2909         if (err) {
2910                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2911                     __func__, err);
2912                 goto err_dalloc_q_counter;
2913         }
2914         err = mlx5e_open_rqt(priv);
2915         if (err) {
2916                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2917                     __func__, err);
2918                 goto err_close_channels;
2919         }
2920         err = mlx5e_open_tirs(priv);
2921         if (err) {
2922                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2923                     __func__, err);
2924                 goto err_close_rqls;
2925         }
2926         err = mlx5e_open_flow_table(priv);
2927         if (err) {
2928                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2929                     __func__, err);
2930                 goto err_close_tirs;
2931         }
2932         err = mlx5e_add_all_vlan_rules(priv);
2933         if (err) {
2934                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2935                     __func__, err);
2936                 goto err_close_flow_table;
2937         }
2938         set_bit(MLX5E_STATE_OPENED, &priv->state);
2939
2940         mlx5e_update_carrier(priv);
2941         mlx5e_set_rx_mode_core(priv);
2942
2943         return (0);
2944
2945 err_close_flow_table:
2946         mlx5e_close_flow_table(priv);
2947
2948 err_close_tirs:
2949         mlx5e_close_tirs(priv);
2950
2951 err_close_rqls:
2952         mlx5e_close_rqt(priv);
2953
2954 err_close_channels:
2955         mlx5e_close_channels(priv);
2956
2957 err_dalloc_q_counter:
2958         mlx5_vport_dealloc_q_counter(priv->mdev,
2959             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2960
2961 err_close_tises:
2962         mlx5e_close_tises(priv);
2963
2964         return (err);
2965 }
2966
2967 static void
2968 mlx5e_open(void *arg)
2969 {
2970         struct mlx5e_priv *priv = arg;
2971
2972         PRIV_LOCK(priv);
2973         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2974                 if_printf(priv->ifp,
2975                     "%s: Setting port status to up failed\n",
2976                     __func__);
2977
2978         mlx5e_open_locked(priv->ifp);
2979         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2980         PRIV_UNLOCK(priv);
2981 }
2982
2983 int
2984 mlx5e_close_locked(struct ifnet *ifp)
2985 {
2986         struct mlx5e_priv *priv = ifp->if_softc;
2987
2988         /* check if already closed */
2989         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2990                 return (0);
2991
2992         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2993
2994         mlx5e_set_rx_mode_core(priv);
2995         mlx5e_del_all_vlan_rules(priv);
2996         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2997         mlx5e_close_flow_table(priv);
2998         mlx5e_close_tirs(priv);
2999         mlx5e_close_rqt(priv);
3000         mlx5e_close_channels(priv);
3001         mlx5_vport_dealloc_q_counter(priv->mdev,
3002             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3003         mlx5e_close_tises(priv);
3004
3005         return (0);
3006 }
3007
3008 #if (__FreeBSD_version >= 1100000)
3009 static uint64_t
3010 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3011 {
3012         struct mlx5e_priv *priv = ifp->if_softc;
3013         u64 retval;
3014
3015         /* PRIV_LOCK(priv); XXX not allowed */
3016         switch (cnt) {
3017         case IFCOUNTER_IPACKETS:
3018                 retval = priv->stats.vport.rx_packets;
3019                 break;
3020         case IFCOUNTER_IERRORS:
3021                 retval = priv->stats.pport.in_range_len_errors +
3022                     priv->stats.pport.out_of_range_len +
3023                     priv->stats.pport.too_long_errors +
3024                     priv->stats.pport.check_seq_err +
3025                     priv->stats.pport.alignment_err;
3026                 break;
3027         case IFCOUNTER_IQDROPS:
3028                 retval = priv->stats.vport.rx_out_of_buffer;
3029                 break;
3030         case IFCOUNTER_OPACKETS:
3031                 retval = priv->stats.vport.tx_packets;
3032                 break;
3033         case IFCOUNTER_OERRORS:
3034                 retval = priv->stats.port_stats_debug.out_discards;
3035                 break;
3036         case IFCOUNTER_IBYTES:
3037                 retval = priv->stats.vport.rx_bytes;
3038                 break;
3039         case IFCOUNTER_OBYTES:
3040                 retval = priv->stats.vport.tx_bytes;
3041                 break;
3042         case IFCOUNTER_IMCASTS:
3043                 retval = priv->stats.vport.rx_multicast_packets;
3044                 break;
3045         case IFCOUNTER_OMCASTS:
3046                 retval = priv->stats.vport.tx_multicast_packets;
3047                 break;
3048         case IFCOUNTER_OQDROPS:
3049                 retval = priv->stats.vport.tx_queue_dropped;
3050                 break;
3051         case IFCOUNTER_COLLISIONS:
3052                 retval = priv->stats.pport.collisions;
3053                 break;
3054         default:
3055                 retval = if_get_counter_default(ifp, cnt);
3056                 break;
3057         }
3058         /* PRIV_UNLOCK(priv); XXX not allowed */
3059         return (retval);
3060 }
3061 #endif
3062
3063 static void
3064 mlx5e_set_rx_mode(struct ifnet *ifp)
3065 {
3066         struct mlx5e_priv *priv = ifp->if_softc;
3067
3068         queue_work(priv->wq, &priv->set_rx_mode_work);
3069 }
3070
3071 static int
3072 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3073 {
3074         struct mlx5e_priv *priv;
3075         struct ifreq *ifr;
3076         struct ifi2creq i2c;
3077         int error = 0;
3078         int mask = 0;
3079         int size_read = 0;
3080         int module_status;
3081         int module_num;
3082         int max_mtu;
3083         uint8_t read_addr;
3084
3085         priv = ifp->if_softc;
3086
3087         /* check if detaching */
3088         if (priv == NULL || priv->gone != 0)
3089                 return (ENXIO);
3090
3091         switch (command) {
3092         case SIOCSIFMTU:
3093                 ifr = (struct ifreq *)data;
3094
3095                 PRIV_LOCK(priv);
3096                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3097
3098                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3099                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3100                         int was_opened;
3101
3102                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3103                         if (was_opened)
3104                                 mlx5e_close_locked(ifp);
3105
3106                         /* set new MTU */
3107                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3108
3109                         if (was_opened)
3110                                 mlx5e_open_locked(ifp);
3111                 } else {
3112                         error = EINVAL;
3113                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
3114                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3115                 }
3116                 PRIV_UNLOCK(priv);
3117                 break;
3118         case SIOCSIFFLAGS:
3119                 if ((ifp->if_flags & IFF_UP) &&
3120                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3121                         mlx5e_set_rx_mode(ifp);
3122                         break;
3123                 }
3124                 PRIV_LOCK(priv);
3125                 if (ifp->if_flags & IFF_UP) {
3126                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3127                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3128                                         mlx5e_open_locked(ifp);
3129                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3130                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3131                         }
3132                 } else {
3133                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3134                                 mlx5_set_port_status(priv->mdev,
3135                                     MLX5_PORT_DOWN);
3136                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3137                                         mlx5e_close_locked(ifp);
3138                                 mlx5e_update_carrier(priv);
3139                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3140                         }
3141                 }
3142                 PRIV_UNLOCK(priv);
3143                 break;
3144         case SIOCADDMULTI:
3145         case SIOCDELMULTI:
3146                 mlx5e_set_rx_mode(ifp);
3147                 break;
3148         case SIOCSIFMEDIA:
3149         case SIOCGIFMEDIA:
3150         case SIOCGIFXMEDIA:
3151                 ifr = (struct ifreq *)data;
3152                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3153                 break;
3154         case SIOCSIFCAP:
3155                 ifr = (struct ifreq *)data;
3156                 PRIV_LOCK(priv);
3157                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3158
3159                 if (mask & IFCAP_TXCSUM) {
3160                         ifp->if_capenable ^= IFCAP_TXCSUM;
3161                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3162
3163                         if (IFCAP_TSO4 & ifp->if_capenable &&
3164                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3165                                 ifp->if_capenable &= ~IFCAP_TSO4;
3166                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3167                                 if_printf(ifp,
3168                                     "tso4 disabled due to -txcsum.\n");
3169                         }
3170                 }
3171                 if (mask & IFCAP_TXCSUM_IPV6) {
3172                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3173                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3174
3175                         if (IFCAP_TSO6 & ifp->if_capenable &&
3176                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3177                                 ifp->if_capenable &= ~IFCAP_TSO6;
3178                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3179                                 if_printf(ifp,
3180                                     "tso6 disabled due to -txcsum6.\n");
3181                         }
3182                 }
3183                 if (mask & IFCAP_RXCSUM)
3184                         ifp->if_capenable ^= IFCAP_RXCSUM;
3185                 if (mask & IFCAP_RXCSUM_IPV6)
3186                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3187                 if (mask & IFCAP_TSO4) {
3188                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3189                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3190                                 if_printf(ifp, "enable txcsum first.\n");
3191                                 error = EAGAIN;
3192                                 goto out;
3193                         }
3194                         ifp->if_capenable ^= IFCAP_TSO4;
3195                         ifp->if_hwassist ^= CSUM_IP_TSO;
3196                 }
3197                 if (mask & IFCAP_TSO6) {
3198                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3199                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3200                                 if_printf(ifp, "enable txcsum6 first.\n");
3201                                 error = EAGAIN;
3202                                 goto out;
3203                         }
3204                         ifp->if_capenable ^= IFCAP_TSO6;
3205                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3206                 }
3207                 if (mask & IFCAP_VLAN_HWFILTER) {
3208                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3209                                 mlx5e_disable_vlan_filter(priv);
3210                         else
3211                                 mlx5e_enable_vlan_filter(priv);
3212
3213                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3214                 }
3215                 if (mask & IFCAP_VLAN_HWTAGGING)
3216                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3217                 if (mask & IFCAP_WOL_MAGIC)
3218                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3219
3220                 VLAN_CAPABILITIES(ifp);
3221                 /* turn off LRO means also turn of HW LRO - if it's on */
3222                 if (mask & IFCAP_LRO) {
3223                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3224                         bool need_restart = false;
3225
3226                         ifp->if_capenable ^= IFCAP_LRO;
3227
3228                         /* figure out if updating HW LRO is needed */
3229                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3230                                 if (priv->params.hw_lro_en) {
3231                                         priv->params.hw_lro_en = false;
3232                                         need_restart = true;
3233                                 }
3234                         } else {
3235                                 if (priv->params.hw_lro_en == false &&
3236                                     priv->params_ethtool.hw_lro != 0) {
3237                                         priv->params.hw_lro_en = true;
3238                                         need_restart = true;
3239                                 }
3240                         }
3241                         if (was_opened && need_restart) {
3242                                 mlx5e_close_locked(ifp);
3243                                 mlx5e_open_locked(ifp);
3244                         }
3245                 }
3246 out:
3247                 PRIV_UNLOCK(priv);
3248                 break;
3249
3250         case SIOCGI2C:
3251                 ifr = (struct ifreq *)data;
3252
3253                 /*
3254                  * Copy from the user-space address ifr_data to the
3255                  * kernel-space address i2c
3256                  */
3257                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3258                 if (error)
3259                         break;
3260
3261                 if (i2c.len > sizeof(i2c.data)) {
3262                         error = EINVAL;
3263                         break;
3264                 }
3265
3266                 PRIV_LOCK(priv);
3267                 /* Get module_num which is required for the query_eeprom */
3268                 error = mlx5_query_module_num(priv->mdev, &module_num);
3269                 if (error) {
3270                         if_printf(ifp, "Query module num failed, eeprom "
3271                             "reading is not supported\n");
3272                         error = EINVAL;
3273                         goto err_i2c;
3274                 }
3275                 /* Check if module is present before doing an access */
3276                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3277                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3278                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3279                         error = EINVAL;
3280                         goto err_i2c;
3281                 }
3282                 /*
3283                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3284                  * The internal conversion is as follows:
3285                  */
3286                 if (i2c.dev_addr == 0xA0)
3287                         read_addr = MLX5E_I2C_ADDR_LOW;
3288                 else if (i2c.dev_addr == 0xA2)
3289                         read_addr = MLX5E_I2C_ADDR_HIGH;
3290                 else {
3291                         if_printf(ifp, "Query eeprom failed, "
3292                             "Invalid Address: %X\n", i2c.dev_addr);
3293                         error = EINVAL;
3294                         goto err_i2c;
3295                 }
3296                 error = mlx5_query_eeprom(priv->mdev,
3297                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3298                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3299                     (uint32_t *)i2c.data, &size_read);
3300                 if (error) {
3301                         if_printf(ifp, "Query eeprom failed, eeprom "
3302                             "reading is not supported\n");
3303                         error = EINVAL;
3304                         goto err_i2c;
3305                 }
3306
3307                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3308                         error = mlx5_query_eeprom(priv->mdev,
3309                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3310                             (uint32_t)(i2c.offset + size_read),
3311                             (uint32_t)(i2c.len - size_read), module_num,
3312                             (uint32_t *)(i2c.data + size_read), &size_read);
3313                 }
3314                 if (error) {
3315                         if_printf(ifp, "Query eeprom failed, eeprom "
3316                             "reading is not supported\n");
3317                         error = EINVAL;
3318                         goto err_i2c;
3319                 }
3320
3321                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3322 err_i2c:
3323                 PRIV_UNLOCK(priv);
3324                 break;
3325
3326         default:
3327                 error = ether_ioctl(ifp, command, data);
3328                 break;
3329         }
3330         return (error);
3331 }
3332
3333 static int
3334 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3335 {
3336         /*
3337          * TODO: uncoment once FW really sets all these bits if
3338          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3339          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3340          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3341          * -ENOTSUPP;
3342          */
3343
3344         /* TODO: add more must-to-have features */
3345
3346         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3347                 return (-ENODEV);
3348
3349         return (0);
3350 }
3351
3352 static u16
3353 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3354 {
3355         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3356
3357         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3358
3359         /* verify against driver hardware limit */
3360         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3361                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3362
3363         return (bf_buf_size);
3364 }
3365
3366 static int
3367 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3368     struct mlx5e_priv *priv,
3369     int num_comp_vectors)
3370 {
3371         int err;
3372
3373         /*
3374          * TODO: Consider link speed for setting "log_sq_size",
3375          * "log_rq_size" and "cq_moderation_xxx":
3376          */
3377         priv->params.log_sq_size =
3378             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3379         priv->params.log_rq_size =
3380             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3381         priv->params.rx_cq_moderation_usec =
3382             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3383             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3384             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3385         priv->params.rx_cq_moderation_mode =
3386             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3387         priv->params.rx_cq_moderation_pkts =
3388             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3389         priv->params.tx_cq_moderation_usec =
3390             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3391         priv->params.tx_cq_moderation_pkts =
3392             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3393         priv->params.min_rx_wqes =
3394             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3395         priv->params.rx_hash_log_tbl_sz =
3396             (order_base_2(num_comp_vectors) >
3397             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3398             order_base_2(num_comp_vectors) :
3399             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3400         priv->params.num_tc = 1;
3401         priv->params.default_vlan_prio = 0;
3402         priv->counter_set_id = -1;
3403         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3404
3405         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3406         if (err)
3407                 return (err);
3408
3409         /*
3410          * hw lro is currently defaulted to off. when it won't anymore we
3411          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3412          */
3413         priv->params.hw_lro_en = false;
3414         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3415
3416         /*
3417          * CQE zipping is currently defaulted to off. when it won't
3418          * anymore we will consider the HW capability:
3419          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3420          */
3421         priv->params.cqe_zipping_en = false;
3422
3423         priv->mdev = mdev;
3424         priv->params.num_channels = num_comp_vectors;
3425         priv->params.channels_rsss = 1;
3426         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3427         priv->queue_mapping_channel_mask =
3428             roundup_pow_of_two(num_comp_vectors) - 1;
3429         priv->num_tc = priv->params.num_tc;
3430         priv->default_vlan_prio = priv->params.default_vlan_prio;
3431
3432         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3433         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3434         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3435
3436         return (0);
3437 }
3438
3439 static int
3440 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3441                   struct mlx5_core_mr *mkey)
3442 {
3443         struct ifnet *ifp = priv->ifp;
3444         struct mlx5_core_dev *mdev = priv->mdev;
3445         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3446         void *mkc;
3447         u32 *in;
3448         int err;
3449
3450         in = mlx5_vzalloc(inlen);
3451         if (in == NULL) {
3452                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3453                 return (-ENOMEM);
3454         }
3455
3456         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3457         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3458         MLX5_SET(mkc, mkc, lw, 1);
3459         MLX5_SET(mkc, mkc, lr, 1);
3460
3461         MLX5_SET(mkc, mkc, pd, pdn);
3462         MLX5_SET(mkc, mkc, length64, 1);
3463         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3464
3465         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3466         if (err)
3467                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3468                     __func__, err);
3469
3470         kvfree(in);
3471         return (err);
3472 }
3473
3474 static const char *mlx5e_vport_stats_desc[] = {
3475         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3476 };
3477
3478 static const char *mlx5e_pport_stats_desc[] = {
3479         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3480 };
3481
3482 static void
3483 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3484 {
3485         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3486         sx_init(&priv->state_lock, "mlx5state");
3487         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3488         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3489 }
3490
3491 static void
3492 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3493 {
3494         mtx_destroy(&priv->async_events_mtx);
3495         sx_destroy(&priv->state_lock);
3496 }
3497
3498 static int
3499 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3500 {
3501         /*
3502          * %d.%d%.d the string format.
3503          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3504          * We need at most 5 chars to store that.
3505          * It also has: two "." and NULL at the end, which means we need 18
3506          * (5*3 + 3) chars at most.
3507          */
3508         char fw[18];
3509         struct mlx5e_priv *priv = arg1;
3510         int error;
3511
3512         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3513             fw_rev_sub(priv->mdev));
3514         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3515         return (error);
3516 }
3517
3518 static void
3519 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3520 {
3521         int i;
3522
3523         for (i = 0; i < ch->num_tc; i++)
3524                 mlx5e_drain_sq(&ch->sq[i]);
3525 }
3526
3527 static void
3528 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3529 {
3530
3531         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3532         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3533         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3534         sq->doorbell.d64 = 0;
3535 }
3536
3537 void
3538 mlx5e_resume_sq(struct mlx5e_sq *sq)
3539 {
3540         int err;
3541
3542         /* check if already enabled */
3543         if (READ_ONCE(sq->running) != 0)
3544                 return;
3545
3546         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3547             MLX5_SQC_STATE_RST);
3548         if (err != 0) {
3549                 if_printf(sq->ifp,
3550                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3551         }
3552
3553         sq->cc = 0;
3554         sq->pc = 0;
3555
3556         /* reset doorbell prior to moving from RST to RDY */
3557         mlx5e_reset_sq_doorbell_record(sq);
3558
3559         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3560             MLX5_SQC_STATE_RDY);
3561         if (err != 0) {
3562                 if_printf(sq->ifp,
3563                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3564         }
3565
3566         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3567         WRITE_ONCE(sq->running, 1);
3568 }
3569
3570 static void
3571 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3572 {
3573         int i;
3574
3575         for (i = 0; i < ch->num_tc; i++)
3576                 mlx5e_resume_sq(&ch->sq[i]);
3577 }
3578
3579 static void
3580 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3581 {
3582         struct mlx5e_rq *rq = &ch->rq;
3583         int err;
3584
3585         mtx_lock(&rq->mtx);
3586         rq->enabled = 0;
3587         callout_stop(&rq->watchdog);
3588         mtx_unlock(&rq->mtx);
3589
3590         callout_drain(&rq->watchdog);
3591
3592         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3593         if (err != 0) {
3594                 if_printf(rq->ifp,
3595                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3596         }
3597
3598         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3599                 msleep(1);
3600                 rq->cq.mcq.comp(&rq->cq.mcq);
3601         }
3602
3603         /*
3604          * Transitioning into RST state will allow the FW to track less ERR state queues,
3605          * thus reducing the recv queue flushing time
3606          */
3607         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3608         if (err != 0) {
3609                 if_printf(rq->ifp,
3610                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3611         }
3612 }
3613
3614 static void
3615 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3616 {
3617         struct mlx5e_rq *rq = &ch->rq;
3618         int err;
3619
3620         rq->wq.wqe_ctr = 0;
3621         mlx5_wq_ll_update_db_record(&rq->wq);
3622         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3623         if (err != 0) {
3624                 if_printf(rq->ifp,
3625                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3626         }
3627
3628         rq->enabled = 1;
3629
3630         rq->cq.mcq.comp(&rq->cq.mcq);
3631 }
3632
3633 void
3634 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3635 {
3636         int i;
3637
3638         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3639                 return;
3640
3641         for (i = 0; i < priv->params.num_channels; i++) {
3642                 if (value)
3643                         mlx5e_disable_tx_dma(&priv->channel[i]);
3644                 else
3645                         mlx5e_enable_tx_dma(&priv->channel[i]);
3646         }
3647 }
3648
3649 void
3650 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3651 {
3652         int i;
3653
3654         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3655                 return;
3656
3657         for (i = 0; i < priv->params.num_channels; i++) {
3658                 if (value)
3659                         mlx5e_disable_rx_dma(&priv->channel[i]);
3660                 else
3661                         mlx5e_enable_rx_dma(&priv->channel[i]);
3662         }
3663 }
3664
3665 static void
3666 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3667 {
3668         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3669             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3670             sysctl_firmware, "A", "HCA firmware version");
3671
3672         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3673             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3674             "Board ID");
3675 }
3676
3677 static int
3678 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3679 {
3680         struct mlx5e_priv *priv = arg1;
3681         uint8_t temp[MLX5E_MAX_PRIORITY];
3682         uint32_t tx_pfc;
3683         int err;
3684         int i;
3685
3686         PRIV_LOCK(priv);
3687
3688         tx_pfc = priv->params.tx_priority_flow_control;
3689
3690         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3691                 temp[i] = (tx_pfc >> i) & 1;
3692
3693         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3694         if (err || !req->newptr)
3695                 goto done;
3696         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3697         if (err)
3698                 goto done;
3699
3700         priv->params.tx_priority_flow_control = 0;
3701
3702         /* range check input value */
3703         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3704                 if (temp[i] > 1) {
3705                         err = ERANGE;
3706                         goto done;
3707                 }
3708                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3709         }
3710
3711         /* check if update is required */
3712         if (tx_pfc != priv->params.tx_priority_flow_control)
3713                 err = -mlx5e_set_port_pfc(priv);
3714 done:
3715         if (err != 0)
3716                 priv->params.tx_priority_flow_control= tx_pfc;
3717         PRIV_UNLOCK(priv);
3718
3719         return (err);
3720 }
3721
3722 static int
3723 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3724 {
3725         struct mlx5e_priv *priv = arg1;
3726         uint8_t temp[MLX5E_MAX_PRIORITY];
3727         uint32_t rx_pfc;
3728         int err;
3729         int i;
3730
3731         PRIV_LOCK(priv);
3732
3733         rx_pfc = priv->params.rx_priority_flow_control;
3734
3735         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3736                 temp[i] = (rx_pfc >> i) & 1;
3737
3738         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3739         if (err || !req->newptr)
3740                 goto done;
3741         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3742         if (err)
3743                 goto done;
3744
3745         priv->params.rx_priority_flow_control = 0;
3746
3747         /* range check input value */
3748         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3749                 if (temp[i] > 1) {
3750                         err = ERANGE;
3751                         goto done;
3752                 }
3753                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3754         }
3755
3756         /* check if update is required */
3757         if (rx_pfc != priv->params.rx_priority_flow_control)
3758                 err = -mlx5e_set_port_pfc(priv);
3759 done:
3760         if (err != 0)
3761                 priv->params.rx_priority_flow_control= rx_pfc;
3762         PRIV_UNLOCK(priv);
3763
3764         return (err);
3765 }
3766
3767 static void
3768 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3769 {
3770 #if (__FreeBSD_version < 1100000)
3771         char path[96];
3772 #endif
3773         int error;
3774
3775         /* enable pauseframes by default */
3776         priv->params.tx_pauseframe_control = 1;
3777         priv->params.rx_pauseframe_control = 1;
3778
3779         /* disable ports flow control, PFC, by default */
3780         priv->params.tx_priority_flow_control = 0;
3781         priv->params.rx_priority_flow_control = 0;
3782
3783 #if (__FreeBSD_version < 1100000)
3784         /* compute path for sysctl */
3785         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3786             device_get_unit(priv->mdev->pdev->dev.bsddev));
3787
3788         /* try to fetch tunable, if any */
3789         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3790
3791         /* compute path for sysctl */
3792         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3793             device_get_unit(priv->mdev->pdev->dev.bsddev));
3794
3795         /* try to fetch tunable, if any */
3796         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3797 #endif
3798
3799         /* register pauseframe SYSCTLs */
3800         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3801             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3802             &priv->params.tx_pauseframe_control, 0,
3803             "Set to enable TX pause frames. Clear to disable.");
3804
3805         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3806             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3807             &priv->params.rx_pauseframe_control, 0,
3808             "Set to enable RX pause frames. Clear to disable.");
3809
3810         /* register priority flow control, PFC, SYSCTLs */
3811         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3812             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3813             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3814             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3815
3816         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3817             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3818             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3819             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3820
3821         PRIV_LOCK(priv);
3822
3823         /* range check */
3824         priv->params.tx_pauseframe_control =
3825             priv->params.tx_pauseframe_control ? 1 : 0;
3826         priv->params.rx_pauseframe_control =
3827             priv->params.rx_pauseframe_control ? 1 : 0;
3828
3829         /* update firmware */
3830         error = mlx5e_set_port_pause_and_pfc(priv);
3831         if (error == -EINVAL) {
3832                 if_printf(priv->ifp,
3833                     "Global pauseframes must be disabled before enabling PFC.\n");
3834                 priv->params.rx_priority_flow_control = 0;
3835                 priv->params.tx_priority_flow_control = 0;
3836
3837                 /* update firmware */
3838                 (void) mlx5e_set_port_pause_and_pfc(priv);
3839         }
3840         PRIV_UNLOCK(priv);
3841 }
3842
3843 static void *
3844 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3845 {
3846         struct ifnet *ifp;
3847         struct mlx5e_priv *priv;
3848         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3849         u8 connector_type;
3850         struct sysctl_oid_list *child;
3851         int ncv = mdev->priv.eq_table.num_comp_vectors;
3852         char unit[16];
3853         int err;
3854         int i,j;
3855         u32 eth_proto_cap;
3856         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
3857         bool ext = 0;
3858         u32 speeds_num;
3859         struct media media_entry = {};
3860
3861         if (mlx5e_check_required_hca_cap(mdev)) {
3862                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3863                 return (NULL);
3864         }
3865         /*
3866          * Try to allocate the priv and make room for worst-case
3867          * number of channel structures:
3868          */
3869         priv = malloc(sizeof(*priv) +
3870             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3871             M_MLX5EN, M_WAITOK | M_ZERO);
3872         mlx5e_priv_mtx_init(priv);
3873
3874         ifp = priv->ifp = if_alloc(IFT_ETHER);
3875         if (ifp == NULL) {
3876                 mlx5_core_err(mdev, "if_alloc() failed\n");
3877                 goto err_free_priv;
3878         }
3879         ifp->if_softc = priv;
3880         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3881         ifp->if_mtu = ETHERMTU;
3882         ifp->if_init = mlx5e_open;
3883         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3884         ifp->if_ioctl = mlx5e_ioctl;
3885         ifp->if_transmit = mlx5e_xmit;
3886         ifp->if_qflush = if_qflush;
3887 #if (__FreeBSD_version >= 1100000)
3888         ifp->if_get_counter = mlx5e_get_counter;
3889 #endif
3890         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3891         /*
3892          * Set driver features
3893          */
3894         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3895         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3896         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3897         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3898         ifp->if_capabilities |= IFCAP_LRO;
3899         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3900         ifp->if_capabilities |= IFCAP_HWSTATS;
3901
3902         /* set TSO limits so that we don't have to drop TX packets */
3903         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3904         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3905         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3906
3907         ifp->if_capenable = ifp->if_capabilities;
3908         ifp->if_hwassist = 0;
3909         if (ifp->if_capenable & IFCAP_TSO)
3910                 ifp->if_hwassist |= CSUM_TSO;
3911         if (ifp->if_capenable & IFCAP_TXCSUM)
3912                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3913         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3914                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3915
3916         /* ifnet sysctl tree */
3917         sysctl_ctx_init(&priv->sysctl_ctx);
3918         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3919             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3920         if (priv->sysctl_ifnet == NULL) {
3921                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3922                 goto err_free_sysctl;
3923         }
3924         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3925         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3926             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3927         if (priv->sysctl_ifnet == NULL) {
3928                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3929                 goto err_free_sysctl;
3930         }
3931
3932         /* HW sysctl tree */
3933         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3934         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3935             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3936         if (priv->sysctl_hw == NULL) {
3937                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3938                 goto err_free_sysctl;
3939         }
3940
3941         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3942         if (err) {
3943                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3944                 goto err_free_sysctl;
3945         }
3946
3947         /* reuse mlx5core's watchdog workqueue */
3948         priv->wq = mdev->priv.health.wq_watchdog;
3949
3950         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3951         if (err) {
3952                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3953                     __func__, err);
3954                 goto err_free_wq;
3955         }
3956         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3957         if (err) {
3958                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3959                     __func__, err);
3960                 goto err_unmap_free_uar;
3961         }
3962         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3963         if (err) {
3964                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3965                     __func__, err);
3966                 goto err_dealloc_pd;
3967         }
3968         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3969         if (err) {
3970                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3971                     __func__, err);
3972                 goto err_dealloc_transport_domain;
3973         }
3974         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3975
3976         /* check if we should generate a random MAC address */
3977         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3978             is_zero_ether_addr(dev_addr)) {
3979                 random_ether_addr(dev_addr);
3980                 if_printf(ifp, "Assigned random MAC address\n");
3981         }
3982
3983         /* set default MTU */
3984         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3985
3986         /* Set default media status */
3987         priv->media_status_last = IFM_AVALID;
3988         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3989             IFM_ETH_RXPAUSE | IFM_FDX;
3990
3991         /* setup default pauseframes configuration */
3992         mlx5e_setup_pauseframes(priv);
3993
3994         /* Setup supported medias */
3995         //TODO: If we failed to query ptys is it ok to proceed??
3996         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
3997                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
3998                     ptys_extended_ethernet);
3999                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4000                     eth_proto_capability);
4001                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4002                         connector_type = MLX5_GET(ptys_reg, out,
4003                             connector_type);
4004         } else {
4005                 eth_proto_cap = 0;
4006                 if_printf(ifp, "%s: Query port media capability failed,"
4007                     " %d\n", __func__, err);
4008         }
4009
4010         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4011             mlx5e_media_change, mlx5e_media_status);
4012
4013         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4014         for (i = 0; i != speeds_num; i++) {
4015                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4016                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4017                             mlx5e_mode_table[i][j];
4018                         if (media_entry.baudrate == 0)
4019                                 continue;
4020                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4021                                 ifmedia_add(&priv->media,
4022                                     media_entry.subtype |
4023                                     IFM_ETHER, 0, NULL);
4024                                 ifmedia_add(&priv->media,
4025                                     media_entry.subtype |
4026                                     IFM_ETHER | IFM_FDX |
4027                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4028                         }
4029                 }
4030         }
4031
4032         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4033         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4034             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4035
4036         /* Set autoselect by default */
4037         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4038             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4039         ether_ifattach(ifp, dev_addr);
4040
4041         /* Register for VLAN events */
4042         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4043             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4044         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4045             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4046
4047         /* Link is down by default */
4048         if_link_state_change(ifp, LINK_STATE_DOWN);
4049
4050         mlx5e_enable_async_events(priv);
4051
4052         mlx5e_add_hw_stats(priv);
4053
4054         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4055             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4056             priv->stats.vport.arg);
4057
4058         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4059             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4060             priv->stats.pport.arg);
4061
4062         mlx5e_create_ethtool(priv);
4063
4064         mtx_lock(&priv->async_events_mtx);
4065         mlx5e_update_stats(priv);
4066         mtx_unlock(&priv->async_events_mtx);
4067
4068         return (priv);
4069
4070 err_dealloc_transport_domain:
4071         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4072
4073 err_dealloc_pd:
4074         mlx5_core_dealloc_pd(mdev, priv->pdn);
4075
4076 err_unmap_free_uar:
4077         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4078
4079 err_free_wq:
4080         flush_workqueue(priv->wq);
4081
4082 err_free_sysctl:
4083         sysctl_ctx_free(&priv->sysctl_ctx);
4084         if (priv->sysctl_debug)
4085                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4086         if_free(ifp);
4087
4088 err_free_priv:
4089         mlx5e_priv_mtx_destroy(priv);
4090         free(priv, M_MLX5EN);
4091         return (NULL);
4092 }
4093
4094 static void
4095 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4096 {
4097         struct mlx5e_priv *priv = vpriv;
4098         struct ifnet *ifp = priv->ifp;
4099
4100         /* don't allow more IOCTLs */
4101         priv->gone = 1;
4102
4103         /* XXX wait a bit to allow IOCTL handlers to complete */
4104         pause("W", hz);
4105
4106         /* stop watchdog timer */
4107         callout_drain(&priv->watchdog);
4108
4109         if (priv->vlan_attach != NULL)
4110                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4111         if (priv->vlan_detach != NULL)
4112                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4113
4114         /* make sure device gets closed */
4115         PRIV_LOCK(priv);
4116         mlx5e_close_locked(ifp);
4117         PRIV_UNLOCK(priv);
4118
4119         /* unregister device */
4120         ifmedia_removeall(&priv->media);
4121         ether_ifdetach(ifp);
4122         if_free(ifp);
4123
4124         /* destroy all remaining sysctl nodes */
4125         sysctl_ctx_free(&priv->stats.vport.ctx);
4126         sysctl_ctx_free(&priv->stats.pport.ctx);
4127         if (priv->sysctl_debug)
4128                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4129         sysctl_ctx_free(&priv->sysctl_ctx);
4130
4131         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4132         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4133         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4134         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4135         mlx5e_disable_async_events(priv);
4136         flush_workqueue(priv->wq);
4137         mlx5e_priv_mtx_destroy(priv);
4138         free(priv, M_MLX5EN);
4139 }
4140
4141 static void *
4142 mlx5e_get_ifp(void *vpriv)
4143 {
4144         struct mlx5e_priv *priv = vpriv;
4145
4146         return (priv->ifp);
4147 }
4148
4149 static struct mlx5_interface mlx5e_interface = {
4150         .add = mlx5e_create_ifp,
4151         .remove = mlx5e_destroy_ifp,
4152         .event = mlx5e_async_event,
4153         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4154         .get_dev = mlx5e_get_ifp,
4155 };
4156
4157 void
4158 mlx5e_init(void)
4159 {
4160         mlx5_register_interface(&mlx5e_interface);
4161 }
4162
4163 void
4164 mlx5e_cleanup(void)
4165 {
4166         mlx5_unregister_interface(&mlx5e_interface);
4167 }
4168
4169 static void
4170 mlx5e_show_version(void __unused *arg)
4171 {
4172
4173         printf("%s", mlx5e_version);
4174 }
4175 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4176
4177 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4178 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4179
4180 #if (__FreeBSD_version >= 1100000)
4181 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4182 #endif
4183 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4184 MODULE_VERSION(mlx5en, 1);