sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.4.1"
  35 #endif
  36
  37 char mlx5e_version[] = "Mellanox Ethernet driver"
  38     " (" ETH_DRIVER_VERSION ")";
  39
  40 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  41
  42 struct mlx5e_channel_param {
  43         struct mlx5e_rq_param rq;
  44         struct mlx5e_sq_param sq;
  45         struct mlx5e_cq_param rx_cq;
  46         struct mlx5e_cq_param tx_cq;
  47 };
  48
  49 static const struct {
  50         u32     subtype;
  51         u64     baudrate;
  52 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  53
  54         [MLX5E_1000BASE_CX_SGMII] = {
  55                 .subtype = IFM_1000_CX_SGMII,
  56                 .baudrate = IF_Mbps(1000ULL),
  57         },
  58         [MLX5E_1000BASE_KX] = {
  59                 .subtype = IFM_1000_KX,
  60                 .baudrate = IF_Mbps(1000ULL),
  61         },
  62         [MLX5E_10GBASE_CX4] = {
  63                 .subtype = IFM_10G_CX4,
  64                 .baudrate = IF_Gbps(10ULL),
  65         },
  66         [MLX5E_10GBASE_KX4] = {
  67                 .subtype = IFM_10G_KX4,
  68                 .baudrate = IF_Gbps(10ULL),
  69         },
  70         [MLX5E_10GBASE_KR] = {
  71                 .subtype = IFM_10G_KR,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_20GBASE_KR2] = {
  75                 .subtype = IFM_20G_KR2,
  76                 .baudrate = IF_Gbps(20ULL),
  77         },
  78         [MLX5E_40GBASE_CR4] = {
  79                 .subtype = IFM_40G_CR4,
  80                 .baudrate = IF_Gbps(40ULL),
  81         },
  82         [MLX5E_40GBASE_KR4] = {
  83                 .subtype = IFM_40G_KR4,
  84                 .baudrate = IF_Gbps(40ULL),
  85         },
  86         [MLX5E_56GBASE_R4] = {
  87                 .subtype = IFM_56G_R4,
  88                 .baudrate = IF_Gbps(56ULL),
  89         },
  90         [MLX5E_10GBASE_CR] = {
  91                 .subtype = IFM_10G_CR1,
  92                 .baudrate = IF_Gbps(10ULL),
  93         },
  94         [MLX5E_10GBASE_SR] = {
  95                 .subtype = IFM_10G_SR,
  96                 .baudrate = IF_Gbps(10ULL),
  97         },
  98         [MLX5E_10GBASE_ER] = {
  99                 .subtype = IFM_10G_ER,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_40GBASE_SR4] = {
 103                 .subtype = IFM_40G_SR4,
 104                 .baudrate = IF_Gbps(40ULL),
 105         },
 106         [MLX5E_40GBASE_LR4] = {
 107                 .subtype = IFM_40G_LR4,
 108                 .baudrate = IF_Gbps(40ULL),
 109         },
 110         [MLX5E_100GBASE_CR4] = {
 111                 .subtype = IFM_100G_CR4,
 112                 .baudrate = IF_Gbps(100ULL),
 113         },
 114         [MLX5E_100GBASE_SR4] = {
 115                 .subtype = IFM_100G_SR4,
 116                 .baudrate = IF_Gbps(100ULL),
 117         },
 118         [MLX5E_100GBASE_KR4] = {
 119                 .subtype = IFM_100G_KR4,
 120                 .baudrate = IF_Gbps(100ULL),
 121         },
 122         [MLX5E_100GBASE_LR4] = {
 123                 .subtype = IFM_100G_LR4,
 124                 .baudrate = IF_Gbps(100ULL),
 125         },
 126         [MLX5E_100BASE_TX] = {
 127                 .subtype = IFM_100_TX,
 128                 .baudrate = IF_Mbps(100ULL),
 129         },
 130         [MLX5E_1000BASE_T] = {
 131                 .subtype = IFM_1000_T,
 132                 .baudrate = IF_Mbps(1000ULL),
 133         },
 134         [MLX5E_10GBASE_T] = {
 135                 .subtype = IFM_10G_T,
 136                 .baudrate = IF_Gbps(10ULL),
 137         },
 138         [MLX5E_25GBASE_CR] = {
 139                 .subtype = IFM_25G_CR,
 140                 .baudrate = IF_Gbps(25ULL),
 141         },
 142         [MLX5E_25GBASE_KR] = {
 143                 .subtype = IFM_25G_KR,
 144                 .baudrate = IF_Gbps(25ULL),
 145         },
 146         [MLX5E_25GBASE_SR] = {
 147                 .subtype = IFM_25G_SR,
 148                 .baudrate = IF_Gbps(25ULL),
 149         },
 150         [MLX5E_50GBASE_CR2] = {
 151                 .subtype = IFM_50G_CR2,
 152                 .baudrate = IF_Gbps(50ULL),
 153         },
 154         [MLX5E_50GBASE_KR2] = {
 155                 .subtype = IFM_50G_KR2,
 156                 .baudrate = IF_Gbps(50ULL),
 157         },
 158 };
 159
 160 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 161
 162 static void
 163 mlx5e_update_carrier(struct mlx5e_priv *priv)
 164 {
 165         struct mlx5_core_dev *mdev = priv->mdev;
 166         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 167         u32 eth_proto_oper;
 168         int error;
 169         u8 port_state;
 170         u8 i;
 171
 172         port_state = mlx5_query_vport_state(mdev,
 173             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 174
 175         if (port_state == VPORT_STATE_UP) {
 176                 priv->media_status_last |= IFM_ACTIVE;
 177         } else {
 178                 priv->media_status_last &= ~IFM_ACTIVE;
 179                 priv->media_active_last = IFM_ETHER;
 180                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 181                 return;
 182         }
 183
 184         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 185         if (error) {
 186                 priv->media_active_last = IFM_ETHER;
 187                 priv->ifp->if_baudrate = 1;
 188                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 189                     __func__, error);
 190                 return;
 191         }
 192         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 193
 194         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 195                 if (mlx5e_mode_table[i].baudrate == 0)
 196                         continue;
 197                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 198                         priv->ifp->if_baudrate =
 199                             mlx5e_mode_table[i].baudrate;
 200                         priv->media_active_last =
 201                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 202                 }
 203         }
 204         if_link_state_change(priv->ifp, LINK_STATE_UP);
 205 }
 206
 207 static void
 208 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 209 {
 210         struct mlx5e_priv *priv = dev->if_softc;
 211
 212         ifmr->ifm_status = priv->media_status_last;
 213         ifmr->ifm_active = priv->media_active_last |
 214             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 215             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 216
 217 }
 218
 219 static u32
 220 mlx5e_find_link_mode(u32 subtype)
 221 {
 222         u32 i;
 223         u32 link_mode = 0;
 224
 225         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 226                 if (mlx5e_mode_table[i].baudrate == 0)
 227                         continue;
 228                 if (mlx5e_mode_table[i].subtype == subtype)
 229                         link_mode |= MLX5E_PROT_MASK(i);
 230         }
 231
 232         return (link_mode);
 233 }
 234
 235 static int
 236 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 237 {
 238         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 239             priv->params.rx_pauseframe_control,
 240             priv->params.tx_pauseframe_control,
 241             priv->params.rx_priority_flow_control,
 242             priv->params.tx_priority_flow_control));
 243 }
 244
 245 static int
 246 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 247 {
 248         int error;
 249
 250         if (priv->params.rx_pauseframe_control ||
 251             priv->params.tx_pauseframe_control) {
 252                 if_printf(priv->ifp,
 253                     "Global pauseframes must be disabled before enabling PFC.\n");
 254                 error = -EINVAL;
 255         } else {
 256                 error = mlx5e_set_port_pause_and_pfc(priv);
 257         }
 258         return (error);
 259 }
 260
 261 static int
 262 mlx5e_media_change(struct ifnet *dev)
 263 {
 264         struct mlx5e_priv *priv = dev->if_softc;
 265         struct mlx5_core_dev *mdev = priv->mdev;
 266         u32 eth_proto_cap;
 267         u32 link_mode;
 268         int was_opened;
 269         int locked;
 270         int error;
 271
 272         locked = PRIV_LOCKED(priv);
 273         if (!locked)
 274                 PRIV_LOCK(priv);
 275
 276         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 277                 error = EINVAL;
 278                 goto done;
 279         }
 280         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 281
 282         /* query supported capabilities */
 283         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 284         if (error != 0) {
 285                 if_printf(dev, "Query port media capability failed\n");
 286                 goto done;
 287         }
 288         /* check for autoselect */
 289         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 290                 link_mode = eth_proto_cap;
 291                 if (link_mode == 0) {
 292                         if_printf(dev, "Port media capability is zero\n");
 293                         error = EINVAL;
 294                         goto done;
 295                 }
 296         } else {
 297                 link_mode = link_mode & eth_proto_cap;
 298                 if (link_mode == 0) {
 299                         if_printf(dev, "Not supported link mode requested\n");
 300                         error = EINVAL;
 301                         goto done;
 302                 }
 303         }
 304         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 305                 /* check if PFC is enabled */
 306                 if (priv->params.rx_priority_flow_control ||
 307                     priv->params.tx_priority_flow_control) {
 308                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 309                         error = EINVAL;
 310                         goto done;
 311                 }
 312         }
 313         /* update pauseframe control bits */
 314         priv->params.rx_pauseframe_control =
 315             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 316         priv->params.tx_pauseframe_control =
 317             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 318
 319         /* check if device is opened */
 320         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 321
 322         /* reconfigure the hardware */
 323         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 324         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 325         error = -mlx5e_set_port_pause_and_pfc(priv);
 326         if (was_opened)
 327                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 328
 329 done:
 330         if (!locked)
 331                 PRIV_UNLOCK(priv);
 332         return (error);
 333 }
 334
 335 static void
 336 mlx5e_update_carrier_work(struct work_struct *work)
 337 {
 338         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 339             update_carrier_work);
 340
 341         PRIV_LOCK(priv);
 342         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 343                 mlx5e_update_carrier(priv);
 344         PRIV_UNLOCK(priv);
 345 }
 346
 347 /*
 348  * This function reads the physical port counters from the firmware
 349  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 350  * macros. The output is converted from big-endian 64-bit values into
 351  * host endian ones and stored in the "priv->stats.pport" structure.
 352  */
 353 static void
 354 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 355 {
 356         struct mlx5_core_dev *mdev = priv->mdev;
 357         struct mlx5e_pport_stats *s = &priv->stats.pport;
 358         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 359         u32 *in;
 360         u32 *out;
 361         const u64 *ptr;
 362         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 363         unsigned x;
 364         unsigned y;
 365         unsigned z;
 366
 367         /* allocate firmware request structures */
 368         in = mlx5_vzalloc(sz);
 369         out = mlx5_vzalloc(sz);
 370         if (in == NULL || out == NULL)
 371                 goto free_out;
 372
 373         /*
 374          * Get pointer to the 64-bit counter set which is located at a
 375          * fixed offset in the output firmware request structure:
 376          */
 377         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 378
 379         MLX5_SET(ppcnt_reg, in, local_port, 1);
 380
 381         /* read IEEE802_3 counter group using predefined counter layout */
 382         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 383         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 384         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 385              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 386                 s->arg[y] = be64toh(ptr[x]);
 387
 388         /* read RFC2819 counter group using predefined counter layout */
 389         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 390         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 391         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 392                 s->arg[y] = be64toh(ptr[x]);
 393         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 394             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 395                 s_debug->arg[y] = be64toh(ptr[x]);
 396
 397         /* read RFC2863 counter group using predefined counter layout */
 398         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 399         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 400         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 401                 s_debug->arg[y] = be64toh(ptr[x]);
 402
 403         /* read physical layer stats counter group using predefined counter layout */
 404         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 405         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 406         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 407                 s_debug->arg[y] = be64toh(ptr[x]);
 408
 409         /* read per-priority counters */
 410         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 411
 412         /* iterate all the priorities */
 413         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 414                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 415                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 416
 417                 /* read per priority stats counter group using predefined counter layout */
 418                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 419                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 420                         s->arg[y] = be64toh(ptr[x]);
 421         }
 422 free_out:
 423         /* free firmware request structures */
 424         kvfree(in);
 425         kvfree(out);
 426 }
 427
 428 /*
 429  * This function is called regularly to collect all statistics
 430  * counters from the firmware. The values can be viewed through the
 431  * sysctl interface. Execution is serialized using the priv's global
 432  * configuration lock.
 433  */
 434 static void
 435 mlx5e_update_stats_work(struct work_struct *work)
 436 {
 437         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 438             update_stats_work);
 439         struct mlx5_core_dev *mdev = priv->mdev;
 440         struct mlx5e_vport_stats *s = &priv->stats.vport;
 441         struct mlx5e_rq_stats *rq_stats;
 442         struct mlx5e_sq_stats *sq_stats;
 443         struct buf_ring *sq_br;
 444 #if (__FreeBSD_version < 1100000)
 445         struct ifnet *ifp = priv->ifp;
 446 #endif
 447
 448         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 449         u32 *out;
 450         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 451         u64 tso_packets = 0;
 452         u64 tso_bytes = 0;
 453         u64 tx_queue_dropped = 0;
 454         u64 tx_defragged = 0;
 455         u64 tx_offload_none = 0;
 456         u64 lro_packets = 0;
 457         u64 lro_bytes = 0;
 458         u64 sw_lro_queued = 0;
 459         u64 sw_lro_flushed = 0;
 460         u64 rx_csum_none = 0;
 461         u64 rx_wqe_err = 0;
 462         u32 rx_out_of_buffer = 0;
 463         int i;
 464         int j;
 465
 466         PRIV_LOCK(priv);
 467         out = mlx5_vzalloc(outlen);
 468         if (out == NULL)
 469                 goto free_out;
 470         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 471                 goto free_out;
 472
 473         /* Collect firts the SW counters and then HW for consistency */
 474         for (i = 0; i < priv->params.num_channels; i++) {
 475                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 476
 477                 rq_stats = &priv->channel[i]->rq.stats;
 478
 479                 /* collect stats from LRO */
 480                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 481                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 482                 sw_lro_queued += rq_stats->sw_lro_queued;
 483                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 484                 lro_packets += rq_stats->lro_packets;
 485                 lro_bytes += rq_stats->lro_bytes;
 486                 rx_csum_none += rq_stats->csum_none;
 487                 rx_wqe_err += rq_stats->wqe_err;
 488
 489                 for (j = 0; j < priv->num_tc; j++) {
 490                         sq_stats = &priv->channel[i]->sq[j].stats;
 491                         sq_br = priv->channel[i]->sq[j].br;
 492
 493                         tso_packets += sq_stats->tso_packets;
 494                         tso_bytes += sq_stats->tso_bytes;
 495                         tx_queue_dropped += sq_stats->dropped;
 496                         if (sq_br != NULL)
 497                                 tx_queue_dropped += sq_br->br_drops;
 498                         tx_defragged += sq_stats->defragged;
 499                         tx_offload_none += sq_stats->csum_offload_none;
 500                 }
 501         }
 502
 503         /* update counters */
 504         s->tso_packets = tso_packets;
 505         s->tso_bytes = tso_bytes;
 506         s->tx_queue_dropped = tx_queue_dropped;
 507         s->tx_defragged = tx_defragged;
 508         s->lro_packets = lro_packets;
 509         s->lro_bytes = lro_bytes;
 510         s->sw_lro_queued = sw_lro_queued;
 511         s->sw_lro_flushed = sw_lro_flushed;
 512         s->rx_csum_none = rx_csum_none;
 513         s->rx_wqe_err = rx_wqe_err;
 514
 515         /* HW counters */
 516         memset(in, 0, sizeof(in));
 517
 518         MLX5_SET(query_vport_counter_in, in, opcode,
 519             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 520         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 521         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 522
 523         memset(out, 0, outlen);
 524
 525         /* get number of out-of-buffer drops first */
 526         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 527             &rx_out_of_buffer))
 528                 goto free_out;
 529
 530         /* accumulate difference into a 64-bit counter */
 531         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 532         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 533
 534         /* get port statistics */
 535         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 536                 goto free_out;
 537
 538 #define MLX5_GET_CTR(out, x) \
 539         MLX5_GET64(query_vport_counter_out, out, x)
 540
 541         s->rx_error_packets =
 542             MLX5_GET_CTR(out, received_errors.packets);
 543         s->rx_error_bytes =
 544             MLX5_GET_CTR(out, received_errors.octets);
 545         s->tx_error_packets =
 546             MLX5_GET_CTR(out, transmit_errors.packets);
 547         s->tx_error_bytes =
 548             MLX5_GET_CTR(out, transmit_errors.octets);
 549
 550         s->rx_unicast_packets =
 551             MLX5_GET_CTR(out, received_eth_unicast.packets);
 552         s->rx_unicast_bytes =
 553             MLX5_GET_CTR(out, received_eth_unicast.octets);
 554         s->tx_unicast_packets =
 555             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 556         s->tx_unicast_bytes =
 557             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 558
 559         s->rx_multicast_packets =
 560             MLX5_GET_CTR(out, received_eth_multicast.packets);
 561         s->rx_multicast_bytes =
 562             MLX5_GET_CTR(out, received_eth_multicast.octets);
 563         s->tx_multicast_packets =
 564             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 565         s->tx_multicast_bytes =
 566             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 567
 568         s->rx_broadcast_packets =
 569             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 570         s->rx_broadcast_bytes =
 571             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 572         s->tx_broadcast_packets =
 573             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 574         s->tx_broadcast_bytes =
 575             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 576
 577         s->rx_packets =
 578             s->rx_unicast_packets +
 579             s->rx_multicast_packets +
 580             s->rx_broadcast_packets -
 581             s->rx_out_of_buffer;
 582         s->rx_bytes =
 583             s->rx_unicast_bytes +
 584             s->rx_multicast_bytes +
 585             s->rx_broadcast_bytes;
 586         s->tx_packets =
 587             s->tx_unicast_packets +
 588             s->tx_multicast_packets +
 589             s->tx_broadcast_packets;
 590         s->tx_bytes =
 591             s->tx_unicast_bytes +
 592             s->tx_multicast_bytes +
 593             s->tx_broadcast_bytes;
 594
 595         /* Update calculated offload counters */
 596         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 597         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 598
 599         /* Get physical port counters */
 600         mlx5e_update_pport_counters(priv);
 601
 602 #if (__FreeBSD_version < 1100000)
 603         /* no get_counters interface in fbsd 10 */
 604         ifp->if_ipackets = s->rx_packets;
 605         ifp->if_ierrors = s->rx_error_packets +
 606             priv->stats.pport.alignment_err +
 607             priv->stats.pport.check_seq_err +
 608             priv->stats.pport.crc_align_errors +
 609             priv->stats.pport.in_range_len_errors +
 610             priv->stats.pport.jabbers +
 611             priv->stats.pport.out_of_range_len +
 612             priv->stats.pport.oversize_pkts +
 613             priv->stats.pport.symbol_err +
 614             priv->stats.pport.too_long_errors +
 615             priv->stats.pport.undersize_pkts +
 616             priv->stats.pport.unsupported_op_rx;
 617         ifp->if_iqdrops = s->rx_out_of_buffer +
 618             priv->stats.pport.drop_events;
 619         ifp->if_opackets = s->tx_packets;
 620         ifp->if_oerrors = s->tx_error_packets;
 621         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 622         ifp->if_ibytes = s->rx_bytes;
 623         ifp->if_obytes = s->tx_bytes;
 624         ifp->if_collisions =
 625             priv->stats.pport.collisions;
 626 #endif
 627
 628 free_out:
 629         kvfree(out);
 630
 631         /* Update diagnostics, if any */
 632         if (priv->params_ethtool.diag_pci_enable ||
 633             priv->params_ethtool.diag_general_enable) {
 634                 int error = mlx5_core_get_diagnostics_full(mdev,
 635                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 636                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 637                 if (error != 0)
 638                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 639         }
 640         PRIV_UNLOCK(priv);
 641 }
 642
 643 static void
 644 mlx5e_update_stats(void *arg)
 645 {
 646         struct mlx5e_priv *priv = arg;
 647
 648         queue_work(priv->wq, &priv->update_stats_work);
 649
 650         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 651 }
 652
 653 static void
 654 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 655     enum mlx5_dev_event event)
 656 {
 657         switch (event) {
 658         case MLX5_DEV_EVENT_PORT_UP:
 659         case MLX5_DEV_EVENT_PORT_DOWN:
 660                 queue_work(priv->wq, &priv->update_carrier_work);
 661                 break;
 662
 663         default:
 664                 break;
 665         }
 666 }
 667
 668 static void
 669 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 670     enum mlx5_dev_event event, unsigned long param)
 671 {
 672         struct mlx5e_priv *priv = vpriv;
 673
 674         mtx_lock(&priv->async_events_mtx);
 675         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 676                 mlx5e_async_event_sub(priv, event);
 677         mtx_unlock(&priv->async_events_mtx);
 678 }
 679
 680 static void
 681 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 682 {
 683         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 684 }
 685
 686 static void
 687 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 688 {
 689         mtx_lock(&priv->async_events_mtx);
 690         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 691         mtx_unlock(&priv->async_events_mtx);
 692 }
 693
 694 static const char *mlx5e_rq_stats_desc[] = {
 695         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 696 };
 697
 698 static int
 699 mlx5e_create_rq(struct mlx5e_channel *c,
 700     struct mlx5e_rq_param *param,
 701     struct mlx5e_rq *rq)
 702 {
 703         struct mlx5e_priv *priv = c->priv;
 704         struct mlx5_core_dev *mdev = priv->mdev;
 705         char buffer[16];
 706         void *rqc = param->rqc;
 707         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 708         int wq_sz;
 709         int err;
 710         int i;
 711         u32 nsegs, wqe_sz;
 712
 713         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 714         if (err != 0)
 715                 goto done;
 716
 717         /* Create DMA descriptor TAG */
 718         if ((err = -bus_dma_tag_create(
 719             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 720             1,                          /* any alignment */
 721             0,                          /* no boundary */
 722             BUS_SPACE_MAXADDR,          /* lowaddr */
 723             BUS_SPACE_MAXADDR,          /* highaddr */
 724             NULL, NULL,                 /* filter, filterarg */
 725             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 726             nsegs,                      /* nsegments */
 727             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 728             0,                          /* flags */
 729             NULL, NULL,                 /* lockfunc, lockfuncarg */
 730             &rq->dma_tag)))
 731                 goto done;
 732
 733         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 734             &rq->wq_ctrl);
 735         if (err)
 736                 goto err_free_dma_tag;
 737
 738         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 739
 740         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 741         if (err != 0)
 742                 goto err_rq_wq_destroy;
 743
 744         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 745
 746         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 747         if (err)
 748                 goto err_rq_wq_destroy;
 749
 750         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 751         for (i = 0; i != wq_sz; i++) {
 752                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 753 #if (MLX5E_MAX_RX_SEGS == 1)
 754                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 755 #else
 756                 int j;
 757 #endif
 758
 759                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 760                 if (err != 0) {
 761                         while (i--)
 762                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 763                         goto err_rq_mbuf_free;
 764                 }
 765
 766                 /* set value for constant fields */
 767 #if (MLX5E_MAX_RX_SEGS == 1)
 768                 wqe->data[0].lkey = c->mkey_be;
 769                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 770 #else
 771                 for (j = 0; j < rq->nsegs; j++)
 772                         wqe->data[j].lkey = c->mkey_be;
 773 #endif
 774         }
 775
 776         rq->ifp = c->ifp;
 777         rq->channel = c;
 778         rq->ix = c->ix;
 779
 780         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 781         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 782             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 783             rq->stats.arg);
 784         return (0);
 785
 786 err_rq_mbuf_free:
 787         free(rq->mbuf, M_MLX5EN);
 788         tcp_lro_free(&rq->lro);
 789 err_rq_wq_destroy:
 790         mlx5_wq_destroy(&rq->wq_ctrl);
 791 err_free_dma_tag:
 792         bus_dma_tag_destroy(rq->dma_tag);
 793 done:
 794         return (err);
 795 }
 796
 797 static void
 798 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 799 {
 800         int wq_sz;
 801         int i;
 802
 803         /* destroy all sysctl nodes */
 804         sysctl_ctx_free(&rq->stats.ctx);
 805
 806         /* free leftover LRO packets, if any */
 807         tcp_lro_free(&rq->lro);
 808
 809         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 810         for (i = 0; i != wq_sz; i++) {
 811                 if (rq->mbuf[i].mbuf != NULL) {
 812                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 813                         m_freem(rq->mbuf[i].mbuf);
 814                 }
 815                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 816         }
 817         free(rq->mbuf, M_MLX5EN);
 818         mlx5_wq_destroy(&rq->wq_ctrl);
 819 }
 820
 821 static int
 822 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 823 {
 824         struct mlx5e_channel *c = rq->channel;
 825         struct mlx5e_priv *priv = c->priv;
 826         struct mlx5_core_dev *mdev = priv->mdev;
 827
 828         void *in;
 829         void *rqc;
 830         void *wq;
 831         int inlen;
 832         int err;
 833
 834         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 835             sizeof(u64) * rq->wq_ctrl.buf.npages;
 836         in = mlx5_vzalloc(inlen);
 837         if (in == NULL)
 838                 return (-ENOMEM);
 839
 840         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 841         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 842
 843         memcpy(rqc, param->rqc, sizeof(param->rqc));
 844
 845         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 846         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 847         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 848         if (priv->counter_set_id >= 0)
 849                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 850         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 851             PAGE_SHIFT);
 852         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 853
 854         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 855             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 856
 857         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 858
 859         kvfree(in);
 860
 861         return (err);
 862 }
 863
 864 static int
 865 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 866 {
 867         struct mlx5e_channel *c = rq->channel;
 868         struct mlx5e_priv *priv = c->priv;
 869         struct mlx5_core_dev *mdev = priv->mdev;
 870
 871         void *in;
 872         void *rqc;
 873         int inlen;
 874         int err;
 875
 876         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 877         in = mlx5_vzalloc(inlen);
 878         if (in == NULL)
 879                 return (-ENOMEM);
 880
 881         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 882
 883         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 884         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 885         MLX5_SET(rqc, rqc, state, next_state);
 886
 887         err = mlx5_core_modify_rq(mdev, in, inlen);
 888
 889         kvfree(in);
 890
 891         return (err);
 892 }
 893
 894 static void
 895 mlx5e_disable_rq(struct mlx5e_rq *rq)
 896 {
 897         struct mlx5e_channel *c = rq->channel;
 898         struct mlx5e_priv *priv = c->priv;
 899         struct mlx5_core_dev *mdev = priv->mdev;
 900
 901         mlx5_core_destroy_rq(mdev, rq->rqn);
 902 }
 903
 904 static int
 905 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 906 {
 907         struct mlx5e_channel *c = rq->channel;
 908         struct mlx5e_priv *priv = c->priv;
 909         struct mlx5_wq_ll *wq = &rq->wq;
 910         int i;
 911
 912         for (i = 0; i < 1000; i++) {
 913                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 914                         return (0);
 915
 916                 msleep(4);
 917         }
 918         return (-ETIMEDOUT);
 919 }
 920
 921 static int
 922 mlx5e_open_rq(struct mlx5e_channel *c,
 923     struct mlx5e_rq_param *param,
 924     struct mlx5e_rq *rq)
 925 {
 926         int err;
 927
 928         err = mlx5e_create_rq(c, param, rq);
 929         if (err)
 930                 return (err);
 931
 932         err = mlx5e_enable_rq(rq, param);
 933         if (err)
 934                 goto err_destroy_rq;
 935
 936         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 937         if (err)
 938                 goto err_disable_rq;
 939
 940         c->rq.enabled = 1;
 941
 942         return (0);
 943
 944 err_disable_rq:
 945         mlx5e_disable_rq(rq);
 946 err_destroy_rq:
 947         mlx5e_destroy_rq(rq);
 948
 949         return (err);
 950 }
 951
 952 static void
 953 mlx5e_close_rq(struct mlx5e_rq *rq)
 954 {
 955         mtx_lock(&rq->mtx);
 956         rq->enabled = 0;
 957         callout_stop(&rq->watchdog);
 958         mtx_unlock(&rq->mtx);
 959
 960         callout_drain(&rq->watchdog);
 961
 962         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 963 }
 964
 965 static void
 966 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 967 {
 968         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
 969
 970         /* wait till RQ is empty */
 971         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
 972                (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
 973                 msleep(4);
 974                 rq->cq.mcq.comp(&rq->cq.mcq);
 975         }
 976
 977         mlx5e_disable_rq(rq);
 978         mlx5e_destroy_rq(rq);
 979 }
 980
 981 void
 982 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 983 {
 984         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 985         int x;
 986
 987         for (x = 0; x != wq_sz; x++)
 988                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 989         free(sq->mbuf, M_MLX5EN);
 990 }
 991
 992 int
 993 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 994 {
 995         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 996         int err;
 997         int x;
 998
 999         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1000
1001         /* Create DMA descriptor MAPs */
1002         for (x = 0; x != wq_sz; x++) {
1003                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1004                 if (err != 0) {
1005                         while (x--)
1006                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1007                         free(sq->mbuf, M_MLX5EN);
1008                         return (err);
1009                 }
1010         }
1011         return (0);
1012 }
1013
1014 static const char *mlx5e_sq_stats_desc[] = {
1015         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1016 };
1017
1018 static int
1019 mlx5e_create_sq(struct mlx5e_channel *c,
1020     int tc,
1021     struct mlx5e_sq_param *param,
1022     struct mlx5e_sq *sq)
1023 {
1024         struct mlx5e_priv *priv = c->priv;
1025         struct mlx5_core_dev *mdev = priv->mdev;
1026         char buffer[16];
1027
1028         void *sqc = param->sqc;
1029         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1030 #ifdef RSS
1031         cpuset_t cpu_mask;
1032         int cpu_id;
1033 #endif
1034         int err;
1035
1036         /* Create DMA descriptor TAG */
1037         if ((err = -bus_dma_tag_create(
1038             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1039             1,                          /* any alignment */
1040             0,                          /* no boundary */
1041             BUS_SPACE_MAXADDR,          /* lowaddr */
1042             BUS_SPACE_MAXADDR,          /* highaddr */
1043             NULL, NULL,                 /* filter, filterarg */
1044             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1045             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1046             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1047             0,                          /* flags */
1048             NULL, NULL,                 /* lockfunc, lockfuncarg */
1049             &sq->dma_tag)))
1050                 goto done;
1051
1052         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1053         if (err)
1054                 goto err_free_dma_tag;
1055
1056         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1057             &sq->wq_ctrl);
1058         if (err)
1059                 goto err_unmap_free_uar;
1060
1061         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1062         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1063
1064         err = mlx5e_alloc_sq_db(sq);
1065         if (err)
1066                 goto err_sq_wq_destroy;
1067
1068         sq->mkey_be = c->mkey_be;
1069         sq->ifp = priv->ifp;
1070         sq->priv = priv;
1071         sq->tc = tc;
1072
1073         /* check if we should allocate a second packet buffer */
1074         if (priv->params_ethtool.tx_bufring_disable == 0) {
1075                 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1076                     M_WAITOK, &sq->lock);
1077                 if (sq->br == NULL) {
1078                         if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1079                             __func__);
1080                         err = -ENOMEM;
1081                         goto err_free_sq_db;
1082                 }
1083
1084                 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1085                     taskqueue_thread_enqueue, &sq->sq_tq);
1086                 if (sq->sq_tq == NULL) {
1087                         if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1088                             __func__);
1089                         err = -ENOMEM;
1090                         goto err_free_drbr;
1091                 }
1092
1093                 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1094 #ifdef RSS
1095                 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1096                 CPU_SETOF(cpu_id, &cpu_mask);
1097                 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1098                     "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1099 #else
1100                 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1101                     "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1102 #endif
1103         }
1104         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1105         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1106             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1107             sq->stats.arg);
1108
1109         return (0);
1110
1111 err_free_drbr:
1112         buf_ring_free(sq->br, M_MLX5EN);
1113 err_free_sq_db:
1114         mlx5e_free_sq_db(sq);
1115 err_sq_wq_destroy:
1116         mlx5_wq_destroy(&sq->wq_ctrl);
1117
1118 err_unmap_free_uar:
1119         mlx5_unmap_free_uar(mdev, &sq->uar);
1120
1121 err_free_dma_tag:
1122         bus_dma_tag_destroy(sq->dma_tag);
1123 done:
1124         return (err);
1125 }
1126
1127 static void
1128 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1129 {
1130         /* destroy all sysctl nodes */
1131         sysctl_ctx_free(&sq->stats.ctx);
1132
1133         mlx5e_free_sq_db(sq);
1134         mlx5_wq_destroy(&sq->wq_ctrl);
1135         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1136         if (sq->sq_tq != NULL) {
1137                 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1138                 taskqueue_free(sq->sq_tq);
1139         }
1140         if (sq->br != NULL)
1141                 buf_ring_free(sq->br, M_MLX5EN);
1142 }
1143
1144 int
1145 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1146     int tis_num)
1147 {
1148         void *in;
1149         void *sqc;
1150         void *wq;
1151         int inlen;
1152         int err;
1153
1154         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1155             sizeof(u64) * sq->wq_ctrl.buf.npages;
1156         in = mlx5_vzalloc(inlen);
1157         if (in == NULL)
1158                 return (-ENOMEM);
1159
1160         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1161         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1162
1163         memcpy(sqc, param->sqc, sizeof(param->sqc));
1164
1165         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1166         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1167         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1168         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1169         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1170
1171         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1172         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1173         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1174             PAGE_SHIFT);
1175         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1176
1177         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1178             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1179
1180         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1181
1182         kvfree(in);
1183
1184         return (err);
1185 }
1186
1187 int
1188 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1189 {
1190         void *in;
1191         void *sqc;
1192         int inlen;
1193         int err;
1194
1195         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1196         in = mlx5_vzalloc(inlen);
1197         if (in == NULL)
1198                 return (-ENOMEM);
1199
1200         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1201
1202         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1203         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1204         MLX5_SET(sqc, sqc, state, next_state);
1205
1206         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1207
1208         kvfree(in);
1209
1210         return (err);
1211 }
1212
1213 void
1214 mlx5e_disable_sq(struct mlx5e_sq *sq)
1215 {
1216
1217         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1218 }
1219
1220 static int
1221 mlx5e_open_sq(struct mlx5e_channel *c,
1222     int tc,
1223     struct mlx5e_sq_param *param,
1224     struct mlx5e_sq *sq)
1225 {
1226         int err;
1227
1228         err = mlx5e_create_sq(c, tc, param, sq);
1229         if (err)
1230                 return (err);
1231
1232         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1233         if (err)
1234                 goto err_destroy_sq;
1235
1236         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1237         if (err)
1238                 goto err_disable_sq;
1239
1240         WRITE_ONCE(sq->queue_state, MLX5E_SQ_READY);
1241
1242         return (0);
1243
1244 err_disable_sq:
1245         mlx5e_disable_sq(sq);
1246 err_destroy_sq:
1247         mlx5e_destroy_sq(sq);
1248
1249         return (err);
1250 }
1251
1252 static void
1253 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1254 {
1255         /* fill up remainder with NOPs */
1256         while (sq->cev_counter != 0) {
1257                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1258                         if (can_sleep != 0) {
1259                                 mtx_unlock(&sq->lock);
1260                                 msleep(4);
1261                                 mtx_lock(&sq->lock);
1262                         } else {
1263                                 goto done;
1264                         }
1265                 }
1266                 /* send a single NOP */
1267                 mlx5e_send_nop(sq, 1);
1268                 atomic_thread_fence_rel();
1269         }
1270 done:
1271         /* Check if we need to write the doorbell */
1272         if (likely(sq->doorbell.d64 != 0)) {
1273                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1274                 sq->doorbell.d64 = 0;
1275         }
1276 }
1277
1278 void
1279 mlx5e_sq_cev_timeout(void *arg)
1280 {
1281         struct mlx5e_sq *sq = arg;
1282
1283         mtx_assert(&sq->lock, MA_OWNED);
1284
1285         /* check next state */
1286         switch (sq->cev_next_state) {
1287         case MLX5E_CEV_STATE_SEND_NOPS:
1288                 /* fill TX ring with NOPs, if any */
1289                 mlx5e_sq_send_nops_locked(sq, 0);
1290
1291                 /* check if completed */
1292                 if (sq->cev_counter == 0) {
1293                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1294                         return;
1295                 }
1296                 break;
1297         default:
1298                 /* send NOPs on next timeout */
1299                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1300                 break;
1301         }
1302
1303         /* restart timer */
1304         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1305 }
1306
1307 void
1308 mlx5e_drain_sq(struct mlx5e_sq *sq)
1309 {
1310         int error;
1311         struct mlx5_core_dev *mdev= sq->priv->mdev;
1312
1313         /*
1314          * Check if already stopped.
1315          *
1316          * NOTE: The "stopped" variable is only written when both the
1317          * priv's configuration lock and the SQ's lock is locked. It
1318          * can therefore safely be read when only one of the two locks
1319          * is locked. This function is always called when the priv's
1320          * configuration lock is locked.
1321          */
1322         if (sq->stopped != 0)
1323                 return;
1324
1325         mtx_lock(&sq->lock);
1326
1327         /* don't put more packets into the SQ */
1328         sq->stopped = 1;
1329
1330         /* teardown event factor timer, if any */
1331         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1332         callout_stop(&sq->cev_callout);
1333
1334         /* send dummy NOPs in order to flush the transmit ring */
1335         mlx5e_sq_send_nops_locked(sq, 1);
1336         mtx_unlock(&sq->lock);
1337
1338         /* make sure it is safe to free the callout */
1339         callout_drain(&sq->cev_callout);
1340
1341         /* wait till SQ is empty or link is down */
1342         mtx_lock(&sq->lock);
1343         while (sq->cc != sq->pc &&
1344             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1345             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1346                 mtx_unlock(&sq->lock);
1347                 msleep(1);
1348                 sq->cq.mcq.comp(&sq->cq.mcq);
1349                 mtx_lock(&sq->lock);
1350         }
1351         mtx_unlock(&sq->lock);
1352
1353         /* error out remaining requests */
1354         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1355         if (error != 0) {
1356                 if_printf(sq->ifp,
1357                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1358         }
1359
1360         /* wait till SQ is empty */
1361         mtx_lock(&sq->lock);
1362         while (sq->cc != sq->pc &&
1363                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1364                 mtx_unlock(&sq->lock);
1365                 msleep(1);
1366                 sq->cq.mcq.comp(&sq->cq.mcq);
1367                 mtx_lock(&sq->lock);
1368         }
1369         mtx_unlock(&sq->lock);
1370 }
1371
1372 static void
1373 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1374 {
1375
1376         mlx5e_drain_sq(sq);
1377         mlx5e_disable_sq(sq);
1378         mlx5e_destroy_sq(sq);
1379 }
1380
1381 static int
1382 mlx5e_create_cq(struct mlx5e_priv *priv,
1383     struct mlx5e_cq_param *param,
1384     struct mlx5e_cq *cq,
1385     mlx5e_cq_comp_t *comp,
1386     int eq_ix)
1387 {
1388         struct mlx5_core_dev *mdev = priv->mdev;
1389         struct mlx5_core_cq *mcq = &cq->mcq;
1390         int eqn_not_used;
1391         int irqn;
1392         int err;
1393         u32 i;
1394
1395         param->wq.buf_numa_node = 0;
1396         param->wq.db_numa_node = 0;
1397
1398         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1399             &cq->wq_ctrl);
1400         if (err)
1401                 return (err);
1402
1403         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1404
1405         mcq->cqe_sz = 64;
1406         mcq->set_ci_db = cq->wq_ctrl.db.db;
1407         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1408         *mcq->set_ci_db = 0;
1409         *mcq->arm_db = 0;
1410         mcq->vector = eq_ix;
1411         mcq->comp = comp;
1412         mcq->event = mlx5e_cq_error_event;
1413         mcq->irqn = irqn;
1414         mcq->uar = &priv->cq_uar;
1415
1416         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1417                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1418
1419                 cqe->op_own = 0xf1;
1420         }
1421
1422         cq->priv = priv;
1423
1424         return (0);
1425 }
1426
1427 static void
1428 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1429 {
1430         mlx5_wq_destroy(&cq->wq_ctrl);
1431 }
1432
1433 static int
1434 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1435 {
1436         struct mlx5_core_cq *mcq = &cq->mcq;
1437         void *in;
1438         void *cqc;
1439         int inlen;
1440         int irqn_not_used;
1441         int eqn;
1442         int err;
1443
1444         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1445             sizeof(u64) * cq->wq_ctrl.buf.npages;
1446         in = mlx5_vzalloc(inlen);
1447         if (in == NULL)
1448                 return (-ENOMEM);
1449
1450         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1451
1452         memcpy(cqc, param->cqc, sizeof(param->cqc));
1453
1454         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1455             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1456
1457         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1458
1459         MLX5_SET(cqc, cqc, c_eqn, eqn);
1460         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1461         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1462             PAGE_SHIFT);
1463         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1464
1465         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1466
1467         kvfree(in);
1468
1469         if (err)
1470                 return (err);
1471
1472         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1473
1474         return (0);
1475 }
1476
1477 static void
1478 mlx5e_disable_cq(struct mlx5e_cq *cq)
1479 {
1480
1481         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1482 }
1483
1484 int
1485 mlx5e_open_cq(struct mlx5e_priv *priv,
1486     struct mlx5e_cq_param *param,
1487     struct mlx5e_cq *cq,
1488     mlx5e_cq_comp_t *comp,
1489     int eq_ix)
1490 {
1491         int err;
1492
1493         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1494         if (err)
1495                 return (err);
1496
1497         err = mlx5e_enable_cq(cq, param, eq_ix);
1498         if (err)
1499                 goto err_destroy_cq;
1500
1501         return (0);
1502
1503 err_destroy_cq:
1504         mlx5e_destroy_cq(cq);
1505
1506         return (err);
1507 }
1508
1509 void
1510 mlx5e_close_cq(struct mlx5e_cq *cq)
1511 {
1512         mlx5e_disable_cq(cq);
1513         mlx5e_destroy_cq(cq);
1514 }
1515
1516 static int
1517 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1518     struct mlx5e_channel_param *cparam)
1519 {
1520         int err;
1521         int tc;
1522
1523         for (tc = 0; tc < c->num_tc; tc++) {
1524                 /* open completion queue */
1525                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1526                     &mlx5e_tx_cq_comp, c->ix);
1527                 if (err)
1528                         goto err_close_tx_cqs;
1529         }
1530         return (0);
1531
1532 err_close_tx_cqs:
1533         for (tc--; tc >= 0; tc--)
1534                 mlx5e_close_cq(&c->sq[tc].cq);
1535
1536         return (err);
1537 }
1538
1539 static void
1540 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1541 {
1542         int tc;
1543
1544         for (tc = 0; tc < c->num_tc; tc++)
1545                 mlx5e_close_cq(&c->sq[tc].cq);
1546 }
1547
1548 static int
1549 mlx5e_open_sqs(struct mlx5e_channel *c,
1550     struct mlx5e_channel_param *cparam)
1551 {
1552         int err;
1553         int tc;
1554
1555         for (tc = 0; tc < c->num_tc; tc++) {
1556                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1557                 if (err)
1558                         goto err_close_sqs;
1559         }
1560
1561         return (0);
1562
1563 err_close_sqs:
1564         for (tc--; tc >= 0; tc--)
1565                 mlx5e_close_sq_wait(&c->sq[tc]);
1566
1567         return (err);
1568 }
1569
1570 static void
1571 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1572 {
1573         int tc;
1574
1575         for (tc = 0; tc < c->num_tc; tc++)
1576                 mlx5e_close_sq_wait(&c->sq[tc]);
1577 }
1578
1579 static void
1580 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1581 {
1582         int tc;
1583
1584         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1585
1586         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1587
1588         for (tc = 0; tc < c->num_tc; tc++) {
1589                 struct mlx5e_sq *sq = c->sq + tc;
1590
1591                 mtx_init(&sq->lock, "mlx5tx",
1592                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1593                 mtx_init(&sq->comp_lock, "mlx5comp",
1594                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1595
1596                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1597
1598                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1599
1600                 /* ensure the TX completion event factor is not zero */
1601                 if (sq->cev_factor == 0)
1602                         sq->cev_factor = 1;
1603         }
1604 }
1605
1606 static void
1607 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1608 {
1609         int tc;
1610
1611         mtx_destroy(&c->rq.mtx);
1612
1613         for (tc = 0; tc < c->num_tc; tc++) {
1614                 mtx_destroy(&c->sq[tc].lock);
1615                 mtx_destroy(&c->sq[tc].comp_lock);
1616         }
1617 }
1618
1619 static int
1620 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1621     struct mlx5e_channel_param *cparam,
1622     struct mlx5e_channel *volatile *cp)
1623 {
1624         struct mlx5e_channel *c;
1625         int err;
1626
1627         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1628         c->priv = priv;
1629         c->ix = ix;
1630         c->cpu = 0;
1631         c->ifp = priv->ifp;
1632         c->mkey_be = cpu_to_be32(priv->mr.key);
1633         c->num_tc = priv->num_tc;
1634
1635         /* init mutexes */
1636         mlx5e_chan_mtx_init(c);
1637
1638         /* open transmit completion queue */
1639         err = mlx5e_open_tx_cqs(c, cparam);
1640         if (err)
1641                 goto err_free;
1642
1643         /* open receive completion queue */
1644         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1645             &mlx5e_rx_cq_comp, c->ix);
1646         if (err)
1647                 goto err_close_tx_cqs;
1648
1649         err = mlx5e_open_sqs(c, cparam);
1650         if (err)
1651                 goto err_close_rx_cq;
1652
1653         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1654         if (err)
1655                 goto err_close_sqs;
1656
1657         /* store channel pointer */
1658         *cp = c;
1659
1660         /* poll receive queue initially */
1661         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1662
1663         return (0);
1664
1665 err_close_sqs:
1666         mlx5e_close_sqs_wait(c);
1667
1668 err_close_rx_cq:
1669         mlx5e_close_cq(&c->rq.cq);
1670
1671 err_close_tx_cqs:
1672         mlx5e_close_tx_cqs(c);
1673
1674 err_free:
1675         /* destroy mutexes */
1676         mlx5e_chan_mtx_destroy(c);
1677         free(c, M_MLX5EN);
1678         return (err);
1679 }
1680
1681 static void
1682 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1683 {
1684         struct mlx5e_channel *c = *pp;
1685
1686         /* check if channel is already closed */
1687         if (c == NULL)
1688                 return;
1689         mlx5e_close_rq(&c->rq);
1690 }
1691
1692 static void
1693 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1694 {
1695         struct mlx5e_channel *c = *pp;
1696
1697         /* check if channel is already closed */
1698         if (c == NULL)
1699                 return;
1700         /* ensure channel pointer is no longer used */
1701         *pp = NULL;
1702
1703         mlx5e_close_rq_wait(&c->rq);
1704         mlx5e_close_sqs_wait(c);
1705         mlx5e_close_cq(&c->rq.cq);
1706         mlx5e_close_tx_cqs(c);
1707         /* destroy mutexes */
1708         mlx5e_chan_mtx_destroy(c);
1709         free(c, M_MLX5EN);
1710 }
1711
1712 static int
1713 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1714 {
1715         u32 r, n;
1716
1717         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1718             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1719         if (r > MJUM16BYTES)
1720                 return (-ENOMEM);
1721
1722         if (r > MJUM9BYTES)
1723                 r = MJUM16BYTES;
1724         else if (r > MJUMPAGESIZE)
1725                 r = MJUM9BYTES;
1726         else if (r > MCLBYTES)
1727                 r = MJUMPAGESIZE;
1728         else
1729                 r = MCLBYTES;
1730
1731         /*
1732          * n + 1 must be a power of two, because stride size must be.
1733          * Stride size is 16 * (n + 1), as the first segment is
1734          * control.
1735          */
1736         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1737                 ;
1738
1739         *wqe_sz = r;
1740         *nsegs = n;
1741         return (0);
1742 }
1743
1744 static void
1745 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1746     struct mlx5e_rq_param *param)
1747 {
1748         void *rqc = param->rqc;
1749         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1750         u32 wqe_sz, nsegs;
1751
1752         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1753         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1754         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1755         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1756             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1757         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1758         MLX5_SET(wq, wq, pd, priv->pdn);
1759
1760         param->wq.buf_numa_node = 0;
1761         param->wq.db_numa_node = 0;
1762         param->wq.linear = 1;
1763 }
1764
1765 static void
1766 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1767     struct mlx5e_sq_param *param)
1768 {
1769         void *sqc = param->sqc;
1770         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1771
1772         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1773         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1774         MLX5_SET(wq, wq, pd, priv->pdn);
1775
1776         param->wq.buf_numa_node = 0;
1777         param->wq.db_numa_node = 0;
1778         param->wq.linear = 1;
1779 }
1780
1781 static void
1782 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1783     struct mlx5e_cq_param *param)
1784 {
1785         void *cqc = param->cqc;
1786
1787         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1788 }
1789
1790 static void
1791 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1792     struct mlx5e_cq_param *param)
1793 {
1794         void *cqc = param->cqc;
1795
1796
1797         /*
1798          * TODO The sysctl to control on/off is a bool value for now, which means
1799          * we only support CSUM, once HASH is implemnted we'll need to address that.
1800          */
1801         if (priv->params.cqe_zipping_en) {
1802                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1803                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1804         }
1805
1806         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1807         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1808         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1809
1810         switch (priv->params.rx_cq_moderation_mode) {
1811         case 0:
1812                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1813                 break;
1814         default:
1815                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1816                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1817                 else
1818                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1819                 break;
1820         }
1821
1822         mlx5e_build_common_cq_param(priv, param);
1823 }
1824
1825 static void
1826 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1827     struct mlx5e_cq_param *param)
1828 {
1829         void *cqc = param->cqc;
1830
1831         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1832         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1833         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1834
1835         switch (priv->params.tx_cq_moderation_mode) {
1836         case 0:
1837                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1838                 break;
1839         default:
1840                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1841                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1842                 else
1843                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1844                 break;
1845         }
1846
1847         mlx5e_build_common_cq_param(priv, param);
1848 }
1849
1850 static void
1851 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1852     struct mlx5e_channel_param *cparam)
1853 {
1854         memset(cparam, 0, sizeof(*cparam));
1855
1856         mlx5e_build_rq_param(priv, &cparam->rq);
1857         mlx5e_build_sq_param(priv, &cparam->sq);
1858         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1859         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1860 }
1861
1862 static int
1863 mlx5e_open_channels(struct mlx5e_priv *priv)
1864 {
1865         struct mlx5e_channel_param cparam;
1866         void *ptr;
1867         int err;
1868         int i;
1869         int j;
1870
1871         priv->channel = malloc(priv->params.num_channels *
1872             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1873
1874         mlx5e_build_channel_param(priv, &cparam);
1875         for (i = 0; i < priv->params.num_channels; i++) {
1876                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1877                 if (err)
1878                         goto err_close_channels;
1879         }
1880
1881         for (j = 0; j < priv->params.num_channels; j++) {
1882                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1883                 if (err)
1884                         goto err_close_channels;
1885         }
1886
1887         return (0);
1888
1889 err_close_channels:
1890         for (i--; i >= 0; i--) {
1891                 mlx5e_close_channel(&priv->channel[i]);
1892                 mlx5e_close_channel_wait(&priv->channel[i]);
1893         }
1894
1895         /* remove "volatile" attribute from "channel" pointer */
1896         ptr = __DECONST(void *, priv->channel);
1897         priv->channel = NULL;
1898
1899         free(ptr, M_MLX5EN);
1900
1901         return (err);
1902 }
1903
1904 static void
1905 mlx5e_close_channels(struct mlx5e_priv *priv)
1906 {
1907         void *ptr;
1908         int i;
1909
1910         if (priv->channel == NULL)
1911                 return;
1912
1913         for (i = 0; i < priv->params.num_channels; i++)
1914                 mlx5e_close_channel(&priv->channel[i]);
1915         for (i = 0; i < priv->params.num_channels; i++)
1916                 mlx5e_close_channel_wait(&priv->channel[i]);
1917
1918         /* remove "volatile" attribute from "channel" pointer */
1919         ptr = __DECONST(void *, priv->channel);
1920         priv->channel = NULL;
1921
1922         free(ptr, M_MLX5EN);
1923 }
1924
1925 static int
1926 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1927 {
1928
1929         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1930                 uint8_t cq_mode;
1931
1932                 switch (priv->params.tx_cq_moderation_mode) {
1933                 case 0:
1934                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1935                         break;
1936                 default:
1937                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1938                         break;
1939                 }
1940
1941                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1942                     priv->params.tx_cq_moderation_usec,
1943                     priv->params.tx_cq_moderation_pkts,
1944                     cq_mode));
1945         }
1946
1947         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1948             priv->params.tx_cq_moderation_usec,
1949             priv->params.tx_cq_moderation_pkts));
1950 }
1951
1952 static int
1953 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1954 {
1955
1956         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1957                 uint8_t cq_mode;
1958                 int retval;
1959
1960                 switch (priv->params.rx_cq_moderation_mode) {
1961                 case 0:
1962                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1963                         break;
1964                 default:
1965                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1966                         break;
1967                 }
1968
1969                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1970                     priv->params.rx_cq_moderation_usec,
1971                     priv->params.rx_cq_moderation_pkts,
1972                     cq_mode);
1973
1974                 return (retval);
1975         }
1976
1977         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1978             priv->params.rx_cq_moderation_usec,
1979             priv->params.rx_cq_moderation_pkts));
1980 }
1981
1982 static int
1983 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1984 {
1985         int err;
1986         int i;
1987
1988         if (c == NULL)
1989                 return (EINVAL);
1990
1991         err = mlx5e_refresh_rq_params(priv, &c->rq);
1992         if (err)
1993                 goto done;
1994
1995         for (i = 0; i != c->num_tc; i++) {
1996                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1997                 if (err)
1998                         goto done;
1999         }
2000 done:
2001         return (err);
2002 }
2003
2004 int
2005 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2006 {
2007         int i;
2008
2009         if (priv->channel == NULL)
2010                 return (EINVAL);
2011
2012         for (i = 0; i < priv->params.num_channels; i++) {
2013                 int err;
2014
2015                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
2016                 if (err)
2017                         return (err);
2018         }
2019         return (0);
2020 }
2021
2022 static int
2023 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2024 {
2025         struct mlx5_core_dev *mdev = priv->mdev;
2026         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2027         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2028
2029         memset(in, 0, sizeof(in));
2030
2031         MLX5_SET(tisc, tisc, prio, tc);
2032         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2033
2034         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2035 }
2036
2037 static void
2038 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2039 {
2040         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2041 }
2042
2043 static int
2044 mlx5e_open_tises(struct mlx5e_priv *priv)
2045 {
2046         int num_tc = priv->num_tc;
2047         int err;
2048         int tc;
2049
2050         for (tc = 0; tc < num_tc; tc++) {
2051                 err = mlx5e_open_tis(priv, tc);
2052                 if (err)
2053                         goto err_close_tises;
2054         }
2055
2056         return (0);
2057
2058 err_close_tises:
2059         for (tc--; tc >= 0; tc--)
2060                 mlx5e_close_tis(priv, tc);
2061
2062         return (err);
2063 }
2064
2065 static void
2066 mlx5e_close_tises(struct mlx5e_priv *priv)
2067 {
2068         int num_tc = priv->num_tc;
2069         int tc;
2070
2071         for (tc = 0; tc < num_tc; tc++)
2072                 mlx5e_close_tis(priv, tc);
2073 }
2074
2075 static int
2076 mlx5e_open_rqt(struct mlx5e_priv *priv)
2077 {
2078         struct mlx5_core_dev *mdev = priv->mdev;
2079         u32 *in;
2080         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2081         void *rqtc;
2082         int inlen;
2083         int err;
2084         int sz;
2085         int i;
2086
2087         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2088
2089         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2090         in = mlx5_vzalloc(inlen);
2091         if (in == NULL)
2092                 return (-ENOMEM);
2093         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2094
2095         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2096         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2097
2098         for (i = 0; i < sz; i++) {
2099                 int ix;
2100 #ifdef RSS
2101                 ix = rss_get_indirection_to_bucket(i);
2102 #else
2103                 ix = i;
2104 #endif
2105                 /* ensure we don't overflow */
2106                 ix %= priv->params.num_channels;
2107                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2108         }
2109
2110         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2111
2112         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2113         if (!err)
2114                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2115
2116         kvfree(in);
2117
2118         return (err);
2119 }
2120
2121 static void
2122 mlx5e_close_rqt(struct mlx5e_priv *priv)
2123 {
2124         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2125         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2126
2127         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2128         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2129
2130         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2131 }
2132
2133 static void
2134 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2135 {
2136         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2137         __be32 *hkey;
2138
2139         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2140
2141 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2142
2143 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2144                           MLX5_HASH_FIELD_SEL_DST_IP)
2145
2146 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2147                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2148                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2149                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2150
2151 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2152                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2153                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2154
2155         if (priv->params.hw_lro_en) {
2156                 MLX5_SET(tirc, tirc, lro_enable_mask,
2157                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2158                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2159                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2160                     (priv->params.lro_wqe_sz -
2161                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2162                 /* TODO: add the option to choose timer value dynamically */
2163                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2164                     MLX5_CAP_ETH(priv->mdev,
2165                     lro_timer_supported_periods[2]));
2166         }
2167
2168         /* setup parameters for hashing TIR type, if any */
2169         switch (tt) {
2170         case MLX5E_TT_ANY:
2171                 MLX5_SET(tirc, tirc, disp_type,
2172                     MLX5_TIRC_DISP_TYPE_DIRECT);
2173                 MLX5_SET(tirc, tirc, inline_rqn,
2174                     priv->channel[0]->rq.rqn);
2175                 break;
2176         default:
2177                 MLX5_SET(tirc, tirc, disp_type,
2178                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2179                 MLX5_SET(tirc, tirc, indirect_table,
2180                     priv->rqtn);
2181                 MLX5_SET(tirc, tirc, rx_hash_fn,
2182                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2183                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2184 #ifdef RSS
2185                 /*
2186                  * The FreeBSD RSS implementation does currently not
2187                  * support symmetric Toeplitz hashes:
2188                  */
2189                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2190                 rss_getkey((uint8_t *)hkey);
2191 #else
2192                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2193                 hkey[0] = cpu_to_be32(0xD181C62C);
2194                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2195                 hkey[2] = cpu_to_be32(0x1983A2FC);
2196                 hkey[3] = cpu_to_be32(0x943E1ADB);
2197                 hkey[4] = cpu_to_be32(0xD9389E6B);
2198                 hkey[5] = cpu_to_be32(0xD1039C2C);
2199                 hkey[6] = cpu_to_be32(0xA74499AD);
2200                 hkey[7] = cpu_to_be32(0x593D56D9);
2201                 hkey[8] = cpu_to_be32(0xF3253C06);
2202                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2203 #endif
2204                 break;
2205         }
2206
2207         switch (tt) {
2208         case MLX5E_TT_IPV4_TCP:
2209                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2210                     MLX5_L3_PROT_TYPE_IPV4);
2211                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2212                     MLX5_L4_PROT_TYPE_TCP);
2213 #ifdef RSS
2214                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2215                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2216                             MLX5_HASH_IP);
2217                 } else
2218 #endif
2219                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2220                     MLX5_HASH_ALL);
2221                 break;
2222
2223         case MLX5E_TT_IPV6_TCP:
2224                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2225                     MLX5_L3_PROT_TYPE_IPV6);
2226                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2227                     MLX5_L4_PROT_TYPE_TCP);
2228 #ifdef RSS
2229                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2230                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2231                             MLX5_HASH_IP);
2232                 } else
2233 #endif
2234                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2235                     MLX5_HASH_ALL);
2236                 break;
2237
2238         case MLX5E_TT_IPV4_UDP:
2239                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2240                     MLX5_L3_PROT_TYPE_IPV4);
2241                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2242                     MLX5_L4_PROT_TYPE_UDP);
2243 #ifdef RSS
2244                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2245                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2246                             MLX5_HASH_IP);
2247                 } else
2248 #endif
2249                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2250                     MLX5_HASH_ALL);
2251                 break;
2252
2253         case MLX5E_TT_IPV6_UDP:
2254                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2255                     MLX5_L3_PROT_TYPE_IPV6);
2256                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2257                     MLX5_L4_PROT_TYPE_UDP);
2258 #ifdef RSS
2259                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2260                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2261                             MLX5_HASH_IP);
2262                 } else
2263 #endif
2264                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2265                     MLX5_HASH_ALL);
2266                 break;
2267
2268         case MLX5E_TT_IPV4_IPSEC_AH:
2269                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2270                     MLX5_L3_PROT_TYPE_IPV4);
2271                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2272                     MLX5_HASH_IP_IPSEC_SPI);
2273                 break;
2274
2275         case MLX5E_TT_IPV6_IPSEC_AH:
2276                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2277                     MLX5_L3_PROT_TYPE_IPV6);
2278                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2279                     MLX5_HASH_IP_IPSEC_SPI);
2280                 break;
2281
2282         case MLX5E_TT_IPV4_IPSEC_ESP:
2283                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2284                     MLX5_L3_PROT_TYPE_IPV4);
2285                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2286                     MLX5_HASH_IP_IPSEC_SPI);
2287                 break;
2288
2289         case MLX5E_TT_IPV6_IPSEC_ESP:
2290                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2291                     MLX5_L3_PROT_TYPE_IPV6);
2292                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2293                     MLX5_HASH_IP_IPSEC_SPI);
2294                 break;
2295
2296         case MLX5E_TT_IPV4:
2297                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2298                     MLX5_L3_PROT_TYPE_IPV4);
2299                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2300                     MLX5_HASH_IP);
2301                 break;
2302
2303         case MLX5E_TT_IPV6:
2304                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2305                     MLX5_L3_PROT_TYPE_IPV6);
2306                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2307                     MLX5_HASH_IP);
2308                 break;
2309
2310         default:
2311                 break;
2312         }
2313 }
2314
2315 static int
2316 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2317 {
2318         struct mlx5_core_dev *mdev = priv->mdev;
2319         u32 *in;
2320         void *tirc;
2321         int inlen;
2322         int err;
2323
2324         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2325         in = mlx5_vzalloc(inlen);
2326         if (in == NULL)
2327                 return (-ENOMEM);
2328         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2329
2330         mlx5e_build_tir_ctx(priv, tirc, tt);
2331
2332         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2333
2334         kvfree(in);
2335
2336         return (err);
2337 }
2338
2339 static void
2340 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2341 {
2342         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2343 }
2344
2345 static int
2346 mlx5e_open_tirs(struct mlx5e_priv *priv)
2347 {
2348         int err;
2349         int i;
2350
2351         for (i = 0; i < MLX5E_NUM_TT; i++) {
2352                 err = mlx5e_open_tir(priv, i);
2353                 if (err)
2354                         goto err_close_tirs;
2355         }
2356
2357         return (0);
2358
2359 err_close_tirs:
2360         for (i--; i >= 0; i--)
2361                 mlx5e_close_tir(priv, i);
2362
2363         return (err);
2364 }
2365
2366 static void
2367 mlx5e_close_tirs(struct mlx5e_priv *priv)
2368 {
2369         int i;
2370
2371         for (i = 0; i < MLX5E_NUM_TT; i++)
2372                 mlx5e_close_tir(priv, i);
2373 }
2374
2375 /*
2376  * SW MTU does not include headers,
2377  * HW MTU includes all headers and checksums.
2378  */
2379 static int
2380 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2381 {
2382         struct mlx5e_priv *priv = ifp->if_softc;
2383         struct mlx5_core_dev *mdev = priv->mdev;
2384         int hw_mtu;
2385         int err;
2386
2387         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2388
2389         err = mlx5_set_port_mtu(mdev, hw_mtu);
2390         if (err) {
2391                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2392                     __func__, sw_mtu, err);
2393                 return (err);
2394         }
2395
2396         /* Update vport context MTU */
2397         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2398         if (err) {
2399                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2400                     __func__, err);
2401         }
2402
2403         ifp->if_mtu = sw_mtu;
2404
2405         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2406         if (err || !hw_mtu) {
2407                 /* fallback to port oper mtu */
2408                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2409         }
2410         if (err) {
2411                 if_printf(ifp, "Query port MTU, after setting new "
2412                     "MTU value, failed\n");
2413                 return (err);
2414         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2415                 err = -E2BIG,
2416                 if_printf(ifp, "Port MTU %d is smaller than "
2417                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2418         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2419                 err = -EINVAL;
2420                 if_printf(ifp, "Port MTU %d is bigger than "
2421                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2422         }
2423         priv->params_ethtool.hw_mtu = hw_mtu;
2424
2425         return (err);
2426 }
2427
2428 int
2429 mlx5e_open_locked(struct ifnet *ifp)
2430 {
2431         struct mlx5e_priv *priv = ifp->if_softc;
2432         int err;
2433         u16 set_id;
2434
2435         /* check if already opened */
2436         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2437                 return (0);
2438
2439 #ifdef RSS
2440         if (rss_getnumbuckets() > priv->params.num_channels) {
2441                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2442                     "channels(%u) available\n", rss_getnumbuckets(),
2443                     priv->params.num_channels);
2444         }
2445 #endif
2446         err = mlx5e_open_tises(priv);
2447         if (err) {
2448                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2449                     __func__, err);
2450                 return (err);
2451         }
2452         err = mlx5_vport_alloc_q_counter(priv->mdev,
2453             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2454         if (err) {
2455                 if_printf(priv->ifp,
2456                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2457                     __func__, err);
2458                 goto err_close_tises;
2459         }
2460         /* store counter set ID */
2461         priv->counter_set_id = set_id;
2462
2463         err = mlx5e_open_channels(priv);
2464         if (err) {
2465                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2466                     __func__, err);
2467                 goto err_dalloc_q_counter;
2468         }
2469         err = mlx5e_open_rqt(priv);
2470         if (err) {
2471                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2472                     __func__, err);
2473                 goto err_close_channels;
2474         }
2475         err = mlx5e_open_tirs(priv);
2476         if (err) {
2477                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2478                     __func__, err);
2479                 goto err_close_rqls;
2480         }
2481         err = mlx5e_open_flow_table(priv);
2482         if (err) {
2483                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2484                     __func__, err);
2485                 goto err_close_tirs;
2486         }
2487         err = mlx5e_add_all_vlan_rules(priv);
2488         if (err) {
2489                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2490                     __func__, err);
2491                 goto err_close_flow_table;
2492         }
2493         set_bit(MLX5E_STATE_OPENED, &priv->state);
2494
2495         mlx5e_update_carrier(priv);
2496         mlx5e_set_rx_mode_core(priv);
2497
2498         return (0);
2499
2500 err_close_flow_table:
2501         mlx5e_close_flow_table(priv);
2502
2503 err_close_tirs:
2504         mlx5e_close_tirs(priv);
2505
2506 err_close_rqls:
2507         mlx5e_close_rqt(priv);
2508
2509 err_close_channels:
2510         mlx5e_close_channels(priv);
2511
2512 err_dalloc_q_counter:
2513         mlx5_vport_dealloc_q_counter(priv->mdev,
2514             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2515
2516 err_close_tises:
2517         mlx5e_close_tises(priv);
2518
2519         return (err);
2520 }
2521
2522 static void
2523 mlx5e_open(void *arg)
2524 {
2525         struct mlx5e_priv *priv = arg;
2526
2527         PRIV_LOCK(priv);
2528         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2529                 if_printf(priv->ifp,
2530                     "%s: Setting port status to up failed\n",
2531                     __func__);
2532
2533         mlx5e_open_locked(priv->ifp);
2534         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2535         PRIV_UNLOCK(priv);
2536 }
2537
2538 int
2539 mlx5e_close_locked(struct ifnet *ifp)
2540 {
2541         struct mlx5e_priv *priv = ifp->if_softc;
2542
2543         /* check if already closed */
2544         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2545                 return (0);
2546
2547         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2548
2549         mlx5e_set_rx_mode_core(priv);
2550         mlx5e_del_all_vlan_rules(priv);
2551         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2552         mlx5e_close_flow_table(priv);
2553         mlx5e_close_tirs(priv);
2554         mlx5e_close_rqt(priv);
2555         mlx5e_close_channels(priv);
2556         mlx5_vport_dealloc_q_counter(priv->mdev,
2557             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2558         mlx5e_close_tises(priv);
2559
2560         return (0);
2561 }
2562
2563 #if (__FreeBSD_version >= 1100000)
2564 static uint64_t
2565 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2566 {
2567         struct mlx5e_priv *priv = ifp->if_softc;
2568         u64 retval;
2569
2570         /* PRIV_LOCK(priv); XXX not allowed */
2571         switch (cnt) {
2572         case IFCOUNTER_IPACKETS:
2573                 retval = priv->stats.vport.rx_packets;
2574                 break;
2575         case IFCOUNTER_IERRORS:
2576                 retval = priv->stats.vport.rx_error_packets +
2577                     priv->stats.pport.alignment_err +
2578                     priv->stats.pport.check_seq_err +
2579                     priv->stats.pport.crc_align_errors +
2580                     priv->stats.pport.in_range_len_errors +
2581                     priv->stats.pport.jabbers +
2582                     priv->stats.pport.out_of_range_len +
2583                     priv->stats.pport.oversize_pkts +
2584                     priv->stats.pport.symbol_err +
2585                     priv->stats.pport.too_long_errors +
2586                     priv->stats.pport.undersize_pkts +
2587                     priv->stats.pport.unsupported_op_rx;
2588                 break;
2589         case IFCOUNTER_IQDROPS:
2590                 retval = priv->stats.vport.rx_out_of_buffer +
2591                     priv->stats.pport.drop_events;
2592                 break;
2593         case IFCOUNTER_OPACKETS:
2594                 retval = priv->stats.vport.tx_packets;
2595                 break;
2596         case IFCOUNTER_OERRORS:
2597                 retval = priv->stats.vport.tx_error_packets;
2598                 break;
2599         case IFCOUNTER_IBYTES:
2600                 retval = priv->stats.vport.rx_bytes;
2601                 break;
2602         case IFCOUNTER_OBYTES:
2603                 retval = priv->stats.vport.tx_bytes;
2604                 break;
2605         case IFCOUNTER_IMCASTS:
2606                 retval = priv->stats.vport.rx_multicast_packets;
2607                 break;
2608         case IFCOUNTER_OMCASTS:
2609                 retval = priv->stats.vport.tx_multicast_packets;
2610                 break;
2611         case IFCOUNTER_OQDROPS:
2612                 retval = priv->stats.vport.tx_queue_dropped;
2613                 break;
2614         case IFCOUNTER_COLLISIONS:
2615                 retval = priv->stats.pport.collisions;
2616                 break;
2617         default:
2618                 retval = if_get_counter_default(ifp, cnt);
2619                 break;
2620         }
2621         /* PRIV_UNLOCK(priv); XXX not allowed */
2622         return (retval);
2623 }
2624 #endif
2625
2626 static void
2627 mlx5e_set_rx_mode(struct ifnet *ifp)
2628 {
2629         struct mlx5e_priv *priv = ifp->if_softc;
2630
2631         queue_work(priv->wq, &priv->set_rx_mode_work);
2632 }
2633
2634 static int
2635 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2636 {
2637         struct mlx5e_priv *priv;
2638         struct ifreq *ifr;
2639         struct ifi2creq i2c;
2640         int error = 0;
2641         int mask = 0;
2642         int size_read = 0;
2643         int module_status;
2644         int module_num;
2645         int max_mtu;
2646         uint8_t read_addr;
2647
2648         priv = ifp->if_softc;
2649
2650         /* check if detaching */
2651         if (priv == NULL || priv->gone != 0)
2652                 return (ENXIO);
2653
2654         switch (command) {
2655         case SIOCSIFMTU:
2656                 ifr = (struct ifreq *)data;
2657
2658                 PRIV_LOCK(priv);
2659                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2660
2661                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2662                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2663                         int was_opened;
2664
2665                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2666                         if (was_opened)
2667                                 mlx5e_close_locked(ifp);
2668
2669                         /* set new MTU */
2670                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2671
2672                         if (was_opened)
2673                                 mlx5e_open_locked(ifp);
2674                 } else {
2675                         error = EINVAL;
2676                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2677                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2678                 }
2679                 PRIV_UNLOCK(priv);
2680                 break;
2681         case SIOCSIFFLAGS:
2682                 if ((ifp->if_flags & IFF_UP) &&
2683                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2684                         mlx5e_set_rx_mode(ifp);
2685                         break;
2686                 }
2687                 PRIV_LOCK(priv);
2688                 if (ifp->if_flags & IFF_UP) {
2689                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2690                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2691                                         mlx5e_open_locked(ifp);
2692                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2693                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2694                         }
2695                 } else {
2696                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2697                                 mlx5_set_port_status(priv->mdev,
2698                                     MLX5_PORT_DOWN);
2699                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2700                                         mlx5e_close_locked(ifp);
2701                                 mlx5e_update_carrier(priv);
2702                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2703                         }
2704                 }
2705                 PRIV_UNLOCK(priv);
2706                 break;
2707         case SIOCADDMULTI:
2708         case SIOCDELMULTI:
2709                 mlx5e_set_rx_mode(ifp);
2710                 break;
2711         case SIOCSIFMEDIA:
2712         case SIOCGIFMEDIA:
2713         case SIOCGIFXMEDIA:
2714                 ifr = (struct ifreq *)data;
2715                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2716                 break;
2717         case SIOCSIFCAP:
2718                 ifr = (struct ifreq *)data;
2719                 PRIV_LOCK(priv);
2720                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2721
2722                 if (mask & IFCAP_TXCSUM) {
2723                         ifp->if_capenable ^= IFCAP_TXCSUM;
2724                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2725
2726                         if (IFCAP_TSO4 & ifp->if_capenable &&
2727                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2728                                 ifp->if_capenable &= ~IFCAP_TSO4;
2729                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2730                                 if_printf(ifp,
2731                                     "tso4 disabled due to -txcsum.\n");
2732                         }
2733                 }
2734                 if (mask & IFCAP_TXCSUM_IPV6) {
2735                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2736                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2737
2738                         if (IFCAP_TSO6 & ifp->if_capenable &&
2739                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2740                                 ifp->if_capenable &= ~IFCAP_TSO6;
2741                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2742                                 if_printf(ifp,
2743                                     "tso6 disabled due to -txcsum6.\n");
2744                         }
2745                 }
2746                 if (mask & IFCAP_RXCSUM)
2747                         ifp->if_capenable ^= IFCAP_RXCSUM;
2748                 if (mask & IFCAP_RXCSUM_IPV6)
2749                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2750                 if (mask & IFCAP_TSO4) {
2751                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2752                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2753                                 if_printf(ifp, "enable txcsum first.\n");
2754                                 error = EAGAIN;
2755                                 goto out;
2756                         }
2757                         ifp->if_capenable ^= IFCAP_TSO4;
2758                         ifp->if_hwassist ^= CSUM_IP_TSO;
2759                 }
2760                 if (mask & IFCAP_TSO6) {
2761                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2762                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2763                                 if_printf(ifp, "enable txcsum6 first.\n");
2764                                 error = EAGAIN;
2765                                 goto out;
2766                         }
2767                         ifp->if_capenable ^= IFCAP_TSO6;
2768                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2769                 }
2770                 if (mask & IFCAP_VLAN_HWFILTER) {
2771                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2772                                 mlx5e_disable_vlan_filter(priv);
2773                         else
2774                                 mlx5e_enable_vlan_filter(priv);
2775
2776                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2777                 }
2778                 if (mask & IFCAP_VLAN_HWTAGGING)
2779                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2780                 if (mask & IFCAP_WOL_MAGIC)
2781                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2782
2783                 VLAN_CAPABILITIES(ifp);
2784                 /* turn off LRO means also turn of HW LRO - if it's on */
2785                 if (mask & IFCAP_LRO) {
2786                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2787                         bool need_restart = false;
2788
2789                         ifp->if_capenable ^= IFCAP_LRO;
2790                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2791                                 if (priv->params.hw_lro_en) {
2792                                         priv->params.hw_lro_en = false;
2793                                         need_restart = true;
2794                                         /* Not sure this is the correct way */
2795                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2796                                 }
2797                         }
2798                         if (was_opened && need_restart) {
2799                                 mlx5e_close_locked(ifp);
2800                                 mlx5e_open_locked(ifp);
2801                         }
2802                 }
2803 out:
2804                 PRIV_UNLOCK(priv);
2805                 break;
2806
2807         case SIOCGI2C:
2808                 ifr = (struct ifreq *)data;
2809
2810                 /*
2811                  * Copy from the user-space address ifr_data to the
2812                  * kernel-space address i2c
2813                  */
2814                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2815                 if (error)
2816                         break;
2817
2818                 if (i2c.len > sizeof(i2c.data)) {
2819                         error = EINVAL;
2820                         break;
2821                 }
2822
2823                 PRIV_LOCK(priv);
2824                 /* Get module_num which is required for the query_eeprom */
2825                 error = mlx5_query_module_num(priv->mdev, &module_num);
2826                 if (error) {
2827                         if_printf(ifp, "Query module num failed, eeprom "
2828                             "reading is not supported\n");
2829                         error = EINVAL;
2830                         goto err_i2c;
2831                 }
2832                 /* Check if module is present before doing an access */
2833                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2834                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2835                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2836                         error = EINVAL;
2837                         goto err_i2c;
2838                 }
2839                 /*
2840                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2841                  * The internal conversion is as follows:
2842                  */
2843                 if (i2c.dev_addr == 0xA0)
2844                         read_addr = MLX5E_I2C_ADDR_LOW;
2845                 else if (i2c.dev_addr == 0xA2)
2846                         read_addr = MLX5E_I2C_ADDR_HIGH;
2847                 else {
2848                         if_printf(ifp, "Query eeprom failed, "
2849                             "Invalid Address: %X\n", i2c.dev_addr);
2850                         error = EINVAL;
2851                         goto err_i2c;
2852                 }
2853                 error = mlx5_query_eeprom(priv->mdev,
2854                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2855                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2856                     (uint32_t *)i2c.data, &size_read);
2857                 if (error) {
2858                         if_printf(ifp, "Query eeprom failed, eeprom "
2859                             "reading is not supported\n");
2860                         error = EINVAL;
2861                         goto err_i2c;
2862                 }
2863
2864                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2865                         error = mlx5_query_eeprom(priv->mdev,
2866                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2867                             (uint32_t)(i2c.offset + size_read),
2868                             (uint32_t)(i2c.len - size_read), module_num,
2869                             (uint32_t *)(i2c.data + size_read), &size_read);
2870                 }
2871                 if (error) {
2872                         if_printf(ifp, "Query eeprom failed, eeprom "
2873                             "reading is not supported\n");
2874                         error = EINVAL;
2875                         goto err_i2c;
2876                 }
2877
2878                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2879 err_i2c:
2880                 PRIV_UNLOCK(priv);
2881                 break;
2882
2883         default:
2884                 error = ether_ioctl(ifp, command, data);
2885                 break;
2886         }
2887         return (error);
2888 }
2889
2890 static int
2891 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2892 {
2893         /*
2894          * TODO: uncoment once FW really sets all these bits if
2895          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2896          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2897          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2898          * -ENOTSUPP;
2899          */
2900
2901         /* TODO: add more must-to-have features */
2902
2903         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2904                 return (-ENODEV);
2905
2906         return (0);
2907 }
2908
2909 static void
2910 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2911     struct mlx5e_priv *priv,
2912     int num_comp_vectors)
2913 {
2914         /*
2915          * TODO: Consider link speed for setting "log_sq_size",
2916          * "log_rq_size" and "cq_moderation_xxx":
2917          */
2918         priv->params.log_sq_size =
2919             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2920         priv->params.log_rq_size =
2921             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2922         priv->params.rx_cq_moderation_usec =
2923             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2924             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2925             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2926         priv->params.rx_cq_moderation_mode =
2927             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2928         priv->params.rx_cq_moderation_pkts =
2929             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2930         priv->params.tx_cq_moderation_usec =
2931             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2932         priv->params.tx_cq_moderation_pkts =
2933             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2934         priv->params.min_rx_wqes =
2935             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2936         priv->params.rx_hash_log_tbl_sz =
2937             (order_base_2(num_comp_vectors) >
2938             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2939             order_base_2(num_comp_vectors) :
2940             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2941         priv->params.num_tc = 1;
2942         priv->params.default_vlan_prio = 0;
2943         priv->counter_set_id = -1;
2944
2945         /*
2946          * hw lro is currently defaulted to off. when it won't anymore we
2947          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2948          */
2949         priv->params.hw_lro_en = false;
2950         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2951
2952         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2953
2954         priv->mdev = mdev;
2955         priv->params.num_channels = num_comp_vectors;
2956         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2957         priv->queue_mapping_channel_mask =
2958             roundup_pow_of_two(num_comp_vectors) - 1;
2959         priv->num_tc = priv->params.num_tc;
2960         priv->default_vlan_prio = priv->params.default_vlan_prio;
2961
2962         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2963         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2964         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2965 }
2966
2967 static int
2968 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2969                   struct mlx5_core_mr *mkey)
2970 {
2971         struct ifnet *ifp = priv->ifp;
2972         struct mlx5_core_dev *mdev = priv->mdev;
2973         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
2974         void *mkc;
2975         u32 *in;
2976         int err;
2977
2978         in = mlx5_vzalloc(inlen);
2979         if (in == NULL) {
2980                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2981                 return (-ENOMEM);
2982         }
2983
2984         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
2985         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
2986         MLX5_SET(mkc, mkc, lw, 1);
2987         MLX5_SET(mkc, mkc, lr, 1);
2988
2989         MLX5_SET(mkc, mkc, pd, pdn);
2990         MLX5_SET(mkc, mkc, length64, 1);
2991         MLX5_SET(mkc, mkc, qpn, 0xffffff);
2992
2993         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
2994         if (err)
2995                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2996                     __func__, err);
2997
2998         kvfree(in);
2999         return (err);
3000 }
3001
3002 static const char *mlx5e_vport_stats_desc[] = {
3003         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3004 };
3005
3006 static const char *mlx5e_pport_stats_desc[] = {
3007         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3008 };
3009
3010 static void
3011 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3012 {
3013         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3014         sx_init(&priv->state_lock, "mlx5state");
3015         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3016         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3017 }
3018
3019 static void
3020 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3021 {
3022         mtx_destroy(&priv->async_events_mtx);
3023         sx_destroy(&priv->state_lock);
3024 }
3025
3026 static int
3027 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3028 {
3029         /*
3030          * %d.%d%.d the string format.
3031          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3032          * We need at most 5 chars to store that.
3033          * It also has: two "." and NULL at the end, which means we need 18
3034          * (5*3 + 3) chars at most.
3035          */
3036         char fw[18];
3037         struct mlx5e_priv *priv = arg1;
3038         int error;
3039
3040         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3041             fw_rev_sub(priv->mdev));
3042         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3043         return (error);
3044 }
3045
3046 static void
3047 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3048 {
3049         int i;
3050
3051         for (i = 0; i < ch->num_tc; i++)
3052                 mlx5e_drain_sq(&ch->sq[i]);
3053 }
3054
3055 static void
3056 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3057 {
3058
3059         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3060         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3061         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3062         sq->doorbell.d64 = 0;
3063 }
3064
3065 void
3066 mlx5e_resume_sq(struct mlx5e_sq *sq)
3067 {
3068         int err;
3069
3070         /* check if already enabled */
3071         if (sq->stopped == 0)
3072                 return;
3073
3074         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3075             MLX5_SQC_STATE_RST);
3076         if (err != 0) {
3077                 if_printf(sq->ifp,
3078                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3079         }
3080
3081         sq->cc = 0;
3082         sq->pc = 0;
3083
3084         /* reset doorbell prior to moving from RST to RDY */
3085         mlx5e_reset_sq_doorbell_record(sq);
3086
3087         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3088             MLX5_SQC_STATE_RDY);
3089         if (err != 0) {
3090                 if_printf(sq->ifp,
3091                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3092         }
3093
3094         mtx_lock(&sq->lock);
3095         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3096         sq->stopped = 0;
3097         mtx_unlock(&sq->lock);
3098
3099 }
3100
3101 static void
3102 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3103 {
3104         int i;
3105
3106         for (i = 0; i < ch->num_tc; i++)
3107                 mlx5e_resume_sq(&ch->sq[i]);
3108 }
3109
3110 static void
3111 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3112 {
3113         struct mlx5e_rq *rq = &ch->rq;
3114         int err;
3115
3116         mtx_lock(&rq->mtx);
3117         rq->enabled = 0;
3118         callout_stop(&rq->watchdog);
3119         mtx_unlock(&rq->mtx);
3120
3121         callout_drain(&rq->watchdog);
3122
3123         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3124         if (err != 0) {
3125                 if_printf(rq->ifp,
3126                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3127         }
3128
3129         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3130                 msleep(1);
3131                 rq->cq.mcq.comp(&rq->cq.mcq);
3132         }
3133
3134         /*
3135          * Transitioning into RST state will allow the FW to track less ERR state queues,
3136          * thus reducing the recv queue flushing time
3137          */
3138         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3139         if (err != 0) {
3140                 if_printf(rq->ifp,
3141                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3142         }
3143 }
3144
3145 static void
3146 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3147 {
3148         struct mlx5e_rq *rq = &ch->rq;
3149         int err;
3150
3151         rq->wq.wqe_ctr = 0;
3152         mlx5_wq_ll_update_db_record(&rq->wq);
3153         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3154         if (err != 0) {
3155                 if_printf(rq->ifp,
3156                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3157         }
3158
3159         rq->enabled = 1;
3160
3161         rq->cq.mcq.comp(&rq->cq.mcq);
3162 }
3163
3164 void
3165 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3166 {
3167         int i;
3168
3169         if (priv->channel == NULL)
3170                 return;
3171
3172         for (i = 0; i < priv->params.num_channels; i++) {
3173
3174                 if (!priv->channel[i])
3175                         continue;
3176
3177                 if (value)
3178                         mlx5e_disable_tx_dma(priv->channel[i]);
3179                 else
3180                         mlx5e_enable_tx_dma(priv->channel[i]);
3181         }
3182 }
3183
3184 void
3185 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3186 {
3187         int i;
3188
3189         if (priv->channel == NULL)
3190                 return;
3191
3192         for (i = 0; i < priv->params.num_channels; i++) {
3193
3194                 if (!priv->channel[i])
3195                         continue;
3196
3197                 if (value)
3198                         mlx5e_disable_rx_dma(priv->channel[i]);
3199                 else
3200                         mlx5e_enable_rx_dma(priv->channel[i]);
3201         }
3202 }
3203
3204 static void
3205 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3206 {
3207         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3208             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3209             sysctl_firmware, "A", "HCA firmware version");
3210
3211         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3212             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3213             "Board ID");
3214 }
3215
3216 static int
3217 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3218 {
3219         struct mlx5e_priv *priv = arg1;
3220         uint32_t tx_pfc;
3221         uint32_t value;
3222         int error;
3223
3224         PRIV_LOCK(priv);
3225
3226         tx_pfc = priv->params.tx_priority_flow_control;
3227
3228         /* get current value */
3229         value = (tx_pfc >> arg2) & 1;
3230
3231         error = sysctl_handle_32(oidp, &value, 0, req);
3232
3233         /* range check value */
3234         if (value != 0)
3235                 priv->params.tx_priority_flow_control |= (1 << arg2);
3236         else
3237                 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3238
3239         /* check if update is required */
3240         if (error == 0 && priv->gone == 0 &&
3241             tx_pfc != priv->params.tx_priority_flow_control) {
3242                 error = -mlx5e_set_port_pfc(priv);
3243                 /* restore previous value */
3244                 if (error != 0)
3245                         priv->params.tx_priority_flow_control= tx_pfc;
3246         }
3247         PRIV_UNLOCK(priv);
3248
3249         return (error);
3250 }
3251
3252 static int
3253 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3254 {
3255         struct mlx5e_priv *priv = arg1;
3256         uint32_t rx_pfc;
3257         uint32_t value;
3258         int error;
3259
3260         PRIV_LOCK(priv);
3261
3262         rx_pfc = priv->params.rx_priority_flow_control;
3263
3264         /* get current value */
3265         value = (rx_pfc >> arg2) & 1;
3266
3267         error = sysctl_handle_32(oidp, &value, 0, req);
3268
3269         /* range check value */
3270         if (value != 0)
3271                 priv->params.rx_priority_flow_control |= (1 << arg2);
3272         else
3273                 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3274
3275         /* check if update is required */
3276         if (error == 0 && priv->gone == 0 &&
3277             rx_pfc != priv->params.rx_priority_flow_control) {
3278                 error = -mlx5e_set_port_pfc(priv);
3279                 /* restore previous value */
3280                 if (error != 0)
3281                         priv->params.rx_priority_flow_control= rx_pfc;
3282         }
3283         PRIV_UNLOCK(priv);
3284
3285         return (error);
3286 }
3287
3288 static void
3289 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3290 {
3291         unsigned int x;
3292         char path[96];
3293         int error;
3294
3295         /* enable pauseframes by default */
3296         priv->params.tx_pauseframe_control = 1;
3297         priv->params.rx_pauseframe_control = 1;
3298
3299         /* disable ports flow control, PFC, by default */
3300         priv->params.tx_priority_flow_control = 0;
3301         priv->params.rx_priority_flow_control = 0;
3302
3303 #if (__FreeBSD_version < 1100000)
3304         /* compute path for sysctl */
3305         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3306             device_get_unit(priv->mdev->pdev->dev.bsddev));
3307
3308         /* try to fetch tunable, if any */
3309         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3310
3311         /* compute path for sysctl */
3312         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3313             device_get_unit(priv->mdev->pdev->dev.bsddev));
3314
3315         /* try to fetch tunable, if any */
3316         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3317
3318         for (x = 0; x != 8; x++) {
3319
3320                 /* compute path for sysctl */
3321                 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3322                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3323
3324                 /* try to fetch tunable, if any */
3325                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3326                         priv->params.tx_priority_flow_control |= 1 << x;
3327
3328                 /* compute path for sysctl */
3329                 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3330                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3331
3332                 /* try to fetch tunable, if any */
3333                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3334                         priv->params.rx_priority_flow_control |= 1 << x;
3335         }
3336 #endif
3337
3338         /* register pauseframe SYSCTLs */
3339         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3340             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3341             &priv->params.tx_pauseframe_control, 0,
3342             "Set to enable TX pause frames. Clear to disable.");
3343
3344         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3345             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3346             &priv->params.rx_pauseframe_control, 0,
3347             "Set to enable RX pause frames. Clear to disable.");
3348
3349         /* register priority_flow control, PFC, SYSCTLs */
3350         for (x = 0; x != 8; x++) {
3351                 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3352
3353                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3354                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3355                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3356                     "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3357
3358                 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3359
3360                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3361                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3362                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3363                     "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3364         }
3365
3366         PRIV_LOCK(priv);
3367
3368         /* range check */
3369         priv->params.tx_pauseframe_control =
3370             priv->params.tx_pauseframe_control ? 1 : 0;
3371         priv->params.rx_pauseframe_control =
3372             priv->params.rx_pauseframe_control ? 1 : 0;
3373
3374         /* update firmware */
3375         error = mlx5e_set_port_pause_and_pfc(priv);
3376         if (error == -EINVAL) {
3377                 if_printf(priv->ifp,
3378                     "Global pauseframes must be disabled before enabling PFC.\n");
3379                 priv->params.rx_priority_flow_control = 0;
3380                 priv->params.tx_priority_flow_control = 0;
3381
3382                 /* update firmware */
3383                 (void) mlx5e_set_port_pause_and_pfc(priv);
3384         }
3385         PRIV_UNLOCK(priv);
3386 }
3387
3388 static void *
3389 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3390 {
3391         struct ifnet *ifp;
3392         struct mlx5e_priv *priv;
3393         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3394         struct sysctl_oid_list *child;
3395         int ncv = mdev->priv.eq_table.num_comp_vectors;
3396         char unit[16];
3397         int err;
3398         int i;
3399         u32 eth_proto_cap;
3400
3401         if (mlx5e_check_required_hca_cap(mdev)) {
3402                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3403                 return (NULL);
3404         }
3405         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3406         mlx5e_priv_mtx_init(priv);
3407
3408         ifp = priv->ifp = if_alloc(IFT_ETHER);
3409         if (ifp == NULL) {
3410                 mlx5_core_err(mdev, "if_alloc() failed\n");
3411                 goto err_free_priv;
3412         }
3413         ifp->if_softc = priv;
3414         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3415         ifp->if_mtu = ETHERMTU;
3416         ifp->if_init = mlx5e_open;
3417         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3418         ifp->if_ioctl = mlx5e_ioctl;
3419         ifp->if_transmit = mlx5e_xmit;
3420         ifp->if_qflush = if_qflush;
3421 #if (__FreeBSD_version >= 1100000)
3422         ifp->if_get_counter = mlx5e_get_counter;
3423 #endif
3424         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3425         /*
3426          * Set driver features
3427          */
3428         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3429         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3430         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3431         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3432         ifp->if_capabilities |= IFCAP_LRO;
3433         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3434         ifp->if_capabilities |= IFCAP_HWSTATS;
3435
3436         /* set TSO limits so that we don't have to drop TX packets */
3437         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3438         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3439         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3440
3441         ifp->if_capenable = ifp->if_capabilities;
3442         ifp->if_hwassist = 0;
3443         if (ifp->if_capenable & IFCAP_TSO)
3444                 ifp->if_hwassist |= CSUM_TSO;
3445         if (ifp->if_capenable & IFCAP_TXCSUM)
3446                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3447         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3448                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3449
3450         sysctl_ctx_init(&priv->sysctl_ctx_channel_debug);
3451
3452         /* ifnet sysctl tree */
3453         sysctl_ctx_init(&priv->sysctl_ctx);
3454         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3455             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3456         if (priv->sysctl_ifnet == NULL) {
3457                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3458                 goto err_free_sysctl;
3459         }
3460         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3461         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3462             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3463         if (priv->sysctl_ifnet == NULL) {
3464                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3465                 goto err_free_sysctl;
3466         }
3467
3468         /* HW sysctl tree */
3469         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3470         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3471             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3472         if (priv->sysctl_hw == NULL) {
3473                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3474                 goto err_free_sysctl;
3475         }
3476         mlx5e_build_ifp_priv(mdev, priv, ncv);
3477
3478         snprintf(unit, sizeof(unit), "mce%u_wq",
3479             device_get_unit(mdev->pdev->dev.bsddev));
3480         priv->wq = alloc_workqueue(unit, 0, 1);
3481         if (priv->wq == NULL) {
3482                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3483                 goto err_free_sysctl;
3484         }
3485
3486         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3487         if (err) {
3488                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3489                     __func__, err);
3490                 goto err_free_wq;
3491         }
3492         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3493         if (err) {
3494                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3495                     __func__, err);
3496                 goto err_unmap_free_uar;
3497         }
3498         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3499         if (err) {
3500                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3501                     __func__, err);
3502                 goto err_dealloc_pd;
3503         }
3504         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3505         if (err) {
3506                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3507                     __func__, err);
3508                 goto err_dealloc_transport_domain;
3509         }
3510         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3511
3512         /* check if we should generate a random MAC address */
3513         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3514             is_zero_ether_addr(dev_addr)) {
3515                 random_ether_addr(dev_addr);
3516                 if_printf(ifp, "Assigned random MAC address\n");
3517         }
3518
3519         /* set default MTU */
3520         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3521
3522         /* Set desc */
3523         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3524
3525         /* Set default media status */
3526         priv->media_status_last = IFM_AVALID;
3527         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3528             IFM_ETH_RXPAUSE | IFM_FDX;
3529
3530         /* setup default pauseframes configuration */
3531         mlx5e_setup_pauseframes(priv);
3532
3533         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3534         if (err) {
3535                 eth_proto_cap = 0;
3536                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3537                     __func__, err);
3538         }
3539
3540         /* Setup supported medias */
3541         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3542             mlx5e_media_change, mlx5e_media_status);
3543
3544         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3545                 if (mlx5e_mode_table[i].baudrate == 0)
3546                         continue;
3547                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3548                         ifmedia_add(&priv->media,
3549                             mlx5e_mode_table[i].subtype |
3550                             IFM_ETHER, 0, NULL);
3551                         ifmedia_add(&priv->media,
3552                             mlx5e_mode_table[i].subtype |
3553                             IFM_ETHER | IFM_FDX |
3554                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3555                 }
3556         }
3557
3558         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3559         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3560             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3561
3562         /* Set autoselect by default */
3563         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3564             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3565         ether_ifattach(ifp, dev_addr);
3566
3567         /* Register for VLAN events */
3568         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3569             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3570         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3571             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3572
3573         /* Link is down by default */
3574         if_link_state_change(ifp, LINK_STATE_DOWN);
3575
3576         mlx5e_enable_async_events(priv);
3577
3578         mlx5e_add_hw_stats(priv);
3579
3580         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3581             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3582             priv->stats.vport.arg);
3583
3584         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3585             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3586             priv->stats.pport.arg);
3587
3588         mlx5e_create_ethtool(priv);
3589
3590         mtx_lock(&priv->async_events_mtx);
3591         mlx5e_update_stats(priv);
3592         mtx_unlock(&priv->async_events_mtx);
3593
3594         return (priv);
3595
3596 err_dealloc_transport_domain:
3597         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3598
3599 err_dealloc_pd:
3600         mlx5_core_dealloc_pd(mdev, priv->pdn);
3601
3602 err_unmap_free_uar:
3603         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3604
3605 err_free_wq:
3606         destroy_workqueue(priv->wq);
3607
3608 err_free_sysctl:
3609         sysctl_ctx_free(&priv->sysctl_ctx);
3610         sysctl_ctx_free(&priv->sysctl_ctx_channel_debug);
3611
3612         if_free(ifp);
3613
3614 err_free_priv:
3615         mlx5e_priv_mtx_destroy(priv);
3616         free(priv, M_MLX5EN);
3617         return (NULL);
3618 }
3619
3620 static void
3621 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3622 {
3623         struct mlx5e_priv *priv = vpriv;
3624         struct ifnet *ifp = priv->ifp;
3625
3626         /* don't allow more IOCTLs */
3627         priv->gone = 1;
3628
3629         /*
3630          * Clear the device description to avoid use after free,
3631          * because the bsddev is not destroyed when this module is
3632          * unloaded:
3633          */
3634         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3635
3636         /* XXX wait a bit to allow IOCTL handlers to complete */
3637         pause("W", hz);
3638
3639         /* stop watchdog timer */
3640         callout_drain(&priv->watchdog);
3641
3642         if (priv->vlan_attach != NULL)
3643                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3644         if (priv->vlan_detach != NULL)
3645                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3646
3647         /* make sure device gets closed */
3648         PRIV_LOCK(priv);
3649         mlx5e_close_locked(ifp);
3650         PRIV_UNLOCK(priv);
3651
3652         /* unregister device */
3653         ifmedia_removeall(&priv->media);
3654         ether_ifdetach(ifp);
3655         if_free(ifp);
3656
3657         /* destroy all remaining sysctl nodes */
3658         if (priv->sysctl_debug) {
3659                 sysctl_ctx_free(&priv->sysctl_ctx_channel_debug);
3660                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3661         }
3662         sysctl_ctx_free(&priv->stats.vport.ctx);
3663         sysctl_ctx_free(&priv->stats.pport.ctx);
3664         sysctl_ctx_free(&priv->sysctl_ctx);
3665
3666         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3667         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3668         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3669         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3670         mlx5e_disable_async_events(priv);
3671         destroy_workqueue(priv->wq);
3672         mlx5e_priv_mtx_destroy(priv);
3673         free(priv, M_MLX5EN);
3674 }
3675
3676 static void *
3677 mlx5e_get_ifp(void *vpriv)
3678 {
3679         struct mlx5e_priv *priv = vpriv;
3680
3681         return (priv->ifp);
3682 }
3683
3684 static struct mlx5_interface mlx5e_interface = {
3685         .add = mlx5e_create_ifp,
3686         .remove = mlx5e_destroy_ifp,
3687         .event = mlx5e_async_event,
3688         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3689         .get_dev = mlx5e_get_ifp,
3690 };
3691
3692 void
3693 mlx5e_init(void)
3694 {
3695         mlx5_register_interface(&mlx5e_interface);
3696 }
3697
3698 void
3699 mlx5e_cleanup(void)
3700 {
3701         mlx5_unregister_interface(&mlx5e_interface);
3702 }
3703
3704 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3705 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3706
3707 #if (__FreeBSD_version >= 1100000)
3708 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3709 #endif
3710 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3711 MODULE_VERSION(mlx5en, 1);