2 * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 static int mlx5e_rl_open_workers(struct mlx5e_priv *);
33 static void mlx5e_rl_close_workers(struct mlx5e_priv *);
34 static int mlx5e_rl_sysctl_show_rate_table(SYSCTL_HANDLER_ARGS);
35 static void mlx5e_rl_sysctl_add_u64_oid(struct mlx5e_rl_priv_data *, unsigned x,
36 struct sysctl_oid *, const char *name, const char *desc);
37 static void mlx5e_rl_sysctl_add_stats_u64_oid(struct mlx5e_rl_priv_data *rl, unsigned x,
38 struct sysctl_oid *node, const char *name, const char *desc);
39 static int mlx5e_rl_tx_limit_add(struct mlx5e_rl_priv_data *, uint64_t value);
40 static int mlx5e_rl_tx_limit_clr(struct mlx5e_rl_priv_data *, uint64_t value);
43 mlx5e_rl_build_sq_param(struct mlx5e_rl_priv_data *rl,
44 struct mlx5e_sq_param *param)
46 void *sqc = param->sqc;
47 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
48 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size);
50 MLX5_SET(wq, wq, log_wq_sz, log_sq_size);
51 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
52 MLX5_SET(wq, wq, pd, rl->priv->pdn);
54 param->wq.buf_numa_node = 0;
55 param->wq.db_numa_node = 0;
60 mlx5e_rl_build_cq_param(struct mlx5e_rl_priv_data *rl,
61 struct mlx5e_cq_param *param)
63 void *cqc = param->cqc;
64 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size);
66 MLX5_SET(cqc, cqc, log_cq_size, log_sq_size);
67 MLX5_SET(cqc, cqc, cq_period, rl->param.tx_coalesce_usecs);
68 MLX5_SET(cqc, cqc, cq_max_count, rl->param.tx_coalesce_pkts);
70 switch (rl->param.tx_coalesce_mode) {
72 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
75 if (MLX5_CAP_GEN(rl->priv->mdev, cq_period_start_from_cqe))
76 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
78 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
84 mlx5e_rl_build_channel_param(struct mlx5e_rl_priv_data *rl,
85 struct mlx5e_rl_channel_param *cparam)
87 memset(cparam, 0, sizeof(*cparam));
89 mlx5e_rl_build_sq_param(rl, &cparam->sq);
90 mlx5e_rl_build_cq_param(rl, &cparam->cq);
94 mlx5e_rl_create_sq(struct mlx5e_priv *priv, struct mlx5e_sq *sq,
95 struct mlx5e_sq_param *param, int ix)
97 struct mlx5_core_dev *mdev = priv->mdev;
98 void *sqc = param->sqc;
99 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
102 /* Create DMA descriptor TAG */
103 if ((err = -bus_dma_tag_create(
104 bus_get_dma_tag(mdev->pdev->dev.bsddev),
105 1, /* any alignment */
107 BUS_SPACE_MAXADDR, /* lowaddr */
108 BUS_SPACE_MAXADDR, /* highaddr */
109 NULL, NULL, /* filter, filterarg */
110 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
111 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
112 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
114 NULL, NULL, /* lockfunc, lockfuncarg */
119 sq->uar = priv->rl.sq_uar;
121 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
124 goto err_free_dma_tag;
126 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
128 * The sq->bf_buf_size variable is intentionally left zero so
129 * that the doorbell writes will occur at the same memory
133 err = mlx5e_alloc_sq_db(sq);
135 goto err_sq_wq_destroy;
137 sq->mkey_be = cpu_to_be32(priv->mr.key);
140 sq->max_inline = priv->params.tx_max_inline;
141 sq->min_inline_mode = priv->params.tx_min_inline_mode;
142 sq->vlan_inline_cap = MLX5_CAP_ETH(mdev, wqe_vlan_insert);
147 mlx5_wq_destroy(&sq->wq_ctrl);
149 bus_dma_tag_destroy(sq->dma_tag);
155 mlx5e_rl_destroy_sq(struct mlx5e_sq *sq)
158 mlx5e_free_sq_db(sq);
159 mlx5_wq_destroy(&sq->wq_ctrl);
163 mlx5e_rl_open_sq(struct mlx5e_priv *priv, struct mlx5e_sq *sq,
164 struct mlx5e_sq_param *param, int ix)
168 err = mlx5e_rl_create_sq(priv, sq, param, ix);
172 err = mlx5e_enable_sq(sq, param, priv->rl.tisn);
176 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
183 mlx5e_disable_sq(sq);
185 mlx5e_rl_destroy_sq(sq);
191 mlx5e_rl_chan_mtx_init(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
193 mtx_init(&sq->lock, "mlx5tx-rl", NULL, MTX_DEF);
194 mtx_init(&sq->comp_lock, "mlx5comp-rl", NULL, MTX_DEF);
196 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
198 sq->cev_factor = priv->rl.param.tx_completion_fact;
200 /* ensure the TX completion event factor is not zero */
201 if (sq->cev_factor == 0)
206 mlx5e_rl_open_channel(struct mlx5e_rl_worker *rlw, int eq_ix,
207 struct mlx5e_rl_channel_param *cparam,
208 struct mlx5e_sq *volatile *ppsq)
210 struct mlx5e_priv *priv = rlw->priv;
214 sq = malloc(sizeof(*sq), M_MLX5EN, M_WAITOK | M_ZERO);
217 mlx5e_rl_chan_mtx_init(priv, sq);
219 /* open TX completion queue */
220 err = mlx5e_open_cq(priv, &cparam->cq, &sq->cq,
221 &mlx5e_tx_cq_comp, eq_ix);
225 err = mlx5e_rl_open_sq(priv, sq, &cparam->sq, eq_ix);
227 goto err_close_tx_cq;
229 /* store TX channel pointer */
232 /* poll TX queue initially */
233 sq->cq.mcq.comp(&sq->cq.mcq);
238 mlx5e_close_cq(&sq->cq);
241 /* destroy mutexes */
242 mtx_destroy(&sq->lock);
243 mtx_destroy(&sq->comp_lock);
245 atomic_add_64(&priv->rl.stats.tx_allocate_resource_failure, 1ULL);
250 mlx5e_rl_close_channel(struct mlx5e_sq *volatile *ppsq)
252 struct mlx5e_sq *sq = *ppsq;
254 /* check if channel is already closed */
257 /* ensure channel pointer is no longer used */
260 /* teardown and destroy SQ */
262 mlx5e_disable_sq(sq);
263 mlx5e_rl_destroy_sq(sq);
266 mlx5e_close_cq(&sq->cq);
268 /* destroy mutexes */
269 mtx_destroy(&sq->lock);
270 mtx_destroy(&sq->comp_lock);
276 mlx5e_rl_sync_tx_completion_fact(struct mlx5e_rl_priv_data *rl)
279 * Limit the maximum distance between completion events to
280 * half of the currently set TX queue size.
282 * The maximum number of queue entries a single IP packet can
283 * consume is given by MLX5_SEND_WQE_MAX_WQEBBS.
285 * The worst case max value is then given as below:
287 uint64_t max = rl->param.tx_queue_size /
288 (2 * MLX5_SEND_WQE_MAX_WQEBBS);
291 * Update the maximum completion factor value in case the
292 * tx_queue_size field changed. Ensure we don't overflow
297 else if (max > 65535)
299 rl->param.tx_completion_fact_max = max;
302 * Verify that the current TX completion factor is within the
305 if (rl->param.tx_completion_fact < 1)
306 rl->param.tx_completion_fact = 1;
307 else if (rl->param.tx_completion_fact > max)
308 rl->param.tx_completion_fact = max;
312 mlx5e_rl_modify_sq(struct mlx5e_sq *sq, uint16_t rl_index)
314 struct mlx5e_priv *priv = sq->priv;
315 struct mlx5_core_dev *mdev = priv->mdev;
322 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
323 in = mlx5_vzalloc(inlen);
327 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
329 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
330 MLX5_SET(modify_sq_in, in, sq_state, MLX5_SQC_STATE_RDY);
331 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
332 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RDY);
333 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
335 err = mlx5_core_modify_sq(mdev, in, inlen);
343 * This function will search the configured rate limit table for the
344 * best match to avoid that a single socket based application can
345 * allocate all the available hardware rates. If the user selected
346 * rate deviates too much from the closes rate available in the rate
347 * limit table, unlimited rate will be selected.
350 mlx5e_rl_find_best_rate_locked(struct mlx5e_rl_priv_data *rl, uint64_t user_rate)
352 uint64_t distance = -1ULL;
354 uint64_t retval = 0; /* unlimited */
357 /* search for closest rate */
358 for (x = 0; x != rl->param.tx_rates_def; x++) {
359 uint64_t rate = rl->rate_limit_table[x];
363 if (rate > user_rate)
364 diff = rate - user_rate;
366 diff = user_rate - rate;
368 /* check if distance is smaller than previous rate */
369 if (diff < distance) {
375 /* range check for multiplication below */
376 if (user_rate > rl->param.tx_limit_max)
377 user_rate = rl->param.tx_limit_max;
379 /* fallback to unlimited, if rate deviates too much */
380 if (distance > howmany(user_rate *
381 rl->param.tx_allowed_deviation, 1000ULL))
388 * This function sets the requested rate for a rate limit channel, in
389 * bits per second. The requested rate will be filtered through the
390 * find best rate function above.
393 mlx5e_rlw_channel_set_rate_locked(struct mlx5e_rl_worker *rlw,
394 struct mlx5e_rl_channel *channel, uint64_t rate)
396 struct mlx5e_rl_priv_data *rl = &rlw->priv->rl;
404 MLX5E_RL_WORKER_UNLOCK(rlw);
408 /* get current burst size in bytes */
409 temp = rl->param.tx_burst_size *
410 MLX5E_SW2HW_MTU(rlw->priv->ifp->if_mtu);
412 /* limit burst size to 64K currently */
418 rate = mlx5e_rl_find_best_rate_locked(rl, rate);
420 MLX5E_RL_RUNLOCK(rl);
423 /* rate doesn't exist, fallback to unlimited */
426 atomic_add_64(&rlw->priv->rl.stats.tx_modify_rate_failure, 1ULL);
428 /* get a reference on the new rate */
429 error = -mlx5_rl_add_rate(rlw->priv->mdev,
430 howmany(rate, 1000), burst, &index);
433 /* adding rate failed, fallback to unlimited */
436 atomic_add_64(&rlw->priv->rl.stats.tx_add_new_rate_failure, 1ULL);
439 MLX5E_RL_WORKER_LOCK(rlw);
442 burst = 0; /* default */
445 /* atomically swap rates */
446 temp = channel->last_rate;
447 channel->last_rate = rate;
450 /* atomically swap burst size */
451 temp = channel->last_burst;
452 channel->last_burst = burst;
455 MLX5E_RL_WORKER_UNLOCK(rlw);
456 /* put reference on the old rate, if any */
458 mlx5_rl_remove_rate(rlw->priv->mdev,
459 howmany(rate, 1000), burst);
465 error = mlx5e_rl_modify_sq(sq, index);
467 atomic_add_64(&rlw->priv->rl.stats.tx_modify_rate_failure, 1ULL);
470 MLX5E_RL_WORKER_LOCK(rlw);
476 mlx5e_rl_worker(void *arg)
479 struct mlx5e_rl_worker *rlw = arg;
480 struct mlx5e_rl_channel *channel;
481 struct mlx5e_priv *priv;
486 /* set thread priority */
490 sched_prio(td, PI_SWI(SWI_NET));
495 /* compute completion vector */
496 ix = (rlw - priv->rl.workers) %
497 priv->mdev->priv.eq_table.num_comp_vectors;
499 /* TODO bind to CPU */
501 /* open all the SQs */
502 MLX5E_RL_WORKER_LOCK(rlw);
503 for (x = 0; x < priv->rl.param.tx_channels_per_worker_def; x++) {
504 struct mlx5e_rl_channel *channel = rlw->channels + x;
506 #if !defined(HAVE_RL_PRE_ALLOCATE_CHANNELS)
507 if (channel->state == MLX5E_RL_ST_FREE)
510 MLX5E_RL_WORKER_UNLOCK(rlw);
512 MLX5E_RL_RLOCK(&priv->rl);
513 error = mlx5e_rl_open_channel(rlw, ix,
514 &priv->rl.chan_param, &channel->sq);
515 MLX5E_RL_RUNLOCK(&priv->rl);
517 MLX5E_RL_WORKER_LOCK(rlw);
520 "mlx5e_rl_open_channel failed: %d\n", error);
523 mlx5e_rlw_channel_set_rate_locked(rlw, channel, channel->init_rate);
526 if (STAILQ_FIRST(&rlw->process_head) == NULL) {
527 /* check if we are tearing down */
528 if (rlw->worker_done != 0)
530 cv_wait(&rlw->cv, &rlw->mtx);
532 /* check if we are tearing down */
533 if (rlw->worker_done != 0)
535 channel = STAILQ_FIRST(&rlw->process_head);
536 if (channel != NULL) {
537 STAILQ_REMOVE_HEAD(&rlw->process_head, entry);
539 switch (channel->state) {
540 case MLX5E_RL_ST_MODIFY:
541 channel->state = MLX5E_RL_ST_USED;
542 MLX5E_RL_WORKER_UNLOCK(rlw);
544 /* create channel by demand */
545 if (channel->sq == NULL) {
546 MLX5E_RL_RLOCK(&priv->rl);
547 error = mlx5e_rl_open_channel(rlw, ix,
548 &priv->rl.chan_param, &channel->sq);
549 MLX5E_RL_RUNLOCK(&priv->rl);
553 "mlx5e_rl_open_channel failed: %d\n", error);
555 atomic_add_64(&rlw->priv->rl.stats.tx_open_queues, 1ULL);
558 mlx5e_resume_sq(channel->sq);
561 MLX5E_RL_WORKER_LOCK(rlw);
562 /* convert from bytes/s to bits/s and set new rate */
563 error = mlx5e_rlw_channel_set_rate_locked(rlw, channel,
564 channel->new_rate * 8ULL);
567 "mlx5e_rlw_channel_set_rate_locked failed: %d\n",
572 case MLX5E_RL_ST_DESTROY:
573 error = mlx5e_rlw_channel_set_rate_locked(rlw, channel, 0);
576 "mlx5e_rlw_channel_set_rate_locked failed: %d\n",
579 if (channel->sq != NULL) {
581 * Make sure all packets are
582 * transmitted before SQ is
583 * returned to free list:
585 MLX5E_RL_WORKER_UNLOCK(rlw);
586 mlx5e_drain_sq(channel->sq);
587 MLX5E_RL_WORKER_LOCK(rlw);
589 /* put the channel back into the free list */
590 STAILQ_INSERT_HEAD(&rlw->index_list_head, channel, entry);
591 channel->state = MLX5E_RL_ST_FREE;
592 atomic_add_64(&priv->rl.stats.tx_active_connections, -1ULL);
601 /* close all the SQs */
602 for (x = 0; x < priv->rl.param.tx_channels_per_worker_def; x++) {
603 struct mlx5e_rl_channel *channel = rlw->channels + x;
605 /* update the initial rate */
606 channel->init_rate = channel->last_rate;
608 /* make sure we free up the rate resource */
609 mlx5e_rlw_channel_set_rate_locked(rlw, channel, 0);
611 if (channel->sq != NULL) {
612 MLX5E_RL_WORKER_UNLOCK(rlw);
613 mlx5e_rl_close_channel(&channel->sq);
614 atomic_add_64(&rlw->priv->rl.stats.tx_open_queues, -1ULL);
615 MLX5E_RL_WORKER_LOCK(rlw);
619 rlw->worker_done = 0;
620 cv_broadcast(&rlw->cv);
621 MLX5E_RL_WORKER_UNLOCK(rlw);
627 mlx5e_rl_open_tis(struct mlx5e_priv *priv)
629 struct mlx5_core_dev *mdev = priv->mdev;
630 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
631 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
633 memset(in, 0, sizeof(in));
635 MLX5_SET(tisc, tisc, prio, 0);
636 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
638 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->rl.tisn));
642 mlx5e_rl_close_tis(struct mlx5e_priv *priv)
644 mlx5_core_destroy_tis(priv->mdev, priv->rl.tisn);
648 mlx5e_rl_set_default_params(struct mlx5e_rl_params *param,
649 struct mlx5_core_dev *mdev)
651 /* ratelimit workers */
652 param->tx_worker_threads_def = mdev->priv.eq_table.num_comp_vectors;
653 param->tx_worker_threads_max = MLX5E_RL_MAX_WORKERS;
656 if (param->tx_worker_threads_def == 0 ||
657 param->tx_worker_threads_def > param->tx_worker_threads_max)
658 param->tx_worker_threads_def = param->tx_worker_threads_max;
660 /* ratelimit channels */
661 param->tx_channels_per_worker_def = MLX5E_RL_MAX_SQS /
662 param->tx_worker_threads_def;
663 param->tx_channels_per_worker_max = MLX5E_RL_MAX_SQS;
666 if (param->tx_channels_per_worker_def > MLX5E_RL_DEF_SQ_PER_WORKER)
667 param->tx_channels_per_worker_def = MLX5E_RL_DEF_SQ_PER_WORKER;
669 /* set default burst size */
670 param->tx_burst_size = 4; /* MTUs */
673 * Set maximum burst size
675 * The burst size is multiplied by the MTU and clamped to the
676 * range 0 ... 65535 bytes inclusivly before fed into the
679 * NOTE: If the burst size or MTU is changed only ratelimit
680 * connections made after the change will use the new burst
683 param->tx_burst_size_max = 255;
685 /* get firmware rate limits in 1000bit/s and convert them to bit/s */
686 param->tx_limit_min = mdev->priv.rl_table.min_rate * 1000ULL;
687 param->tx_limit_max = mdev->priv.rl_table.max_rate * 1000ULL;
689 /* ratelimit table size */
690 param->tx_rates_max = mdev->priv.rl_table.max_size;
693 if (param->tx_rates_max > MLX5E_RL_MAX_TX_RATES)
694 param->tx_rates_max = MLX5E_RL_MAX_TX_RATES;
696 /* set default number of rates */
697 param->tx_rates_def = param->tx_rates_max;
699 /* set maximum allowed rate deviation */
700 if (param->tx_limit_max != 0) {
702 * Make sure the deviation multiplication doesn't
703 * overflow unsigned 64-bit:
705 param->tx_allowed_deviation_max = -1ULL /
708 /* set default rate deviation */
709 param->tx_allowed_deviation = 50; /* 5.0% */
711 /* channel parameters */
712 param->tx_queue_size = (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
713 param->tx_coalesce_usecs = MLX5E_RL_TX_COAL_USEC_DEFAULT;
714 param->tx_coalesce_pkts = MLX5E_RL_TX_COAL_PKTS_DEFAULT;
715 param->tx_coalesce_mode = MLX5E_RL_TX_COAL_MODE_DEFAULT;
716 param->tx_completion_fact = MLX5E_RL_TX_COMP_FACT_DEFAULT;
719 static const char *mlx5e_rl_params_desc[] = {
720 MLX5E_RL_PARAMS(MLX5E_STATS_DESC)
723 static const char *mlx5e_rl_table_params_desc[] = {
724 MLX5E_RL_TABLE_PARAMS(MLX5E_STATS_DESC)
727 static const char *mlx5e_rl_stats_desc[] = {
728 MLX5E_RL_STATS(MLX5E_STATS_DESC)
732 mlx5e_rl_init(struct mlx5e_priv *priv)
734 struct mlx5e_rl_priv_data *rl = &priv->rl;
735 struct sysctl_oid *node;
736 struct sysctl_oid *stats;
742 /* check if there is support for packet pacing */
743 if (!MLX5_CAP_GEN(priv->mdev, qos) || !MLX5_CAP_QOS(priv->mdev, packet_pacing))
748 sysctl_ctx_init(&rl->ctx);
750 sx_init(&rl->rl_sxlock, "ratelimit-sxlock");
752 /* allocate shared UAR for SQs */
753 error = mlx5_alloc_map_uar(priv->mdev, &rl->sq_uar);
757 /* open own TIS domain for ratelimit SQs */
758 error = mlx5e_rl_open_tis(priv);
762 /* setup default value for parameters */
763 mlx5e_rl_set_default_params(&rl->param, priv->mdev);
765 /* update the completion factor */
766 mlx5e_rl_sync_tx_completion_fact(rl);
768 /* create root node */
769 node = SYSCTL_ADD_NODE(&rl->ctx,
770 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
771 "rate_limit", CTLFLAG_RW, NULL, "Rate limiting support");
775 for (i = 0; i != MLX5E_RL_PARAMS_NUM; i++) {
776 mlx5e_rl_sysctl_add_u64_oid(rl,
777 MLX5E_RL_PARAMS_INDEX(arg[i]),
778 node, mlx5e_rl_params_desc[2 * i],
779 mlx5e_rl_params_desc[2 * i + 1]);
782 stats = SYSCTL_ADD_NODE(&rl->ctx, SYSCTL_CHILDREN(node),
783 OID_AUTO, "stats", CTLFLAG_RD, NULL,
784 "Rate limiting statistics");
787 for (i = 0; i != MLX5E_RL_STATS_NUM; i++) {
788 mlx5e_rl_sysctl_add_stats_u64_oid(rl, i,
789 stats, mlx5e_rl_stats_desc[2 * i],
790 mlx5e_rl_stats_desc[2 * i + 1]);
795 /* allocate workers array */
796 rl->workers = malloc(sizeof(rl->workers[0]) *
797 rl->param.tx_worker_threads_def, M_MLX5EN, M_WAITOK | M_ZERO);
799 /* allocate rate limit array */
800 rl->rate_limit_table = malloc(sizeof(rl->rate_limit_table[0]) *
801 rl->param.tx_rates_def, M_MLX5EN, M_WAITOK | M_ZERO);
804 /* create more SYSCTls */
805 SYSCTL_ADD_PROC(&rl->ctx, SYSCTL_CHILDREN(node), OID_AUTO,
806 "tx_rate_show", CTLTYPE_STRING | CTLFLAG_RD |
807 CTLFLAG_MPSAFE, rl, 0, &mlx5e_rl_sysctl_show_rate_table,
808 "A", "Show table of all configured TX rates");
810 /* try to fetch rate table from kernel environment */
811 for (i = 0; i != rl->param.tx_rates_def; i++) {
812 /* compute path for tunable */
813 snprintf(buf, sizeof(buf), "dev.mce.%d.rate_limit.tx_rate_add_%d",
814 device_get_unit(priv->mdev->pdev->dev.bsddev), (int)i);
815 if (TUNABLE_QUAD_FETCH(buf, &j))
816 mlx5e_rl_tx_limit_add(rl, j);
819 /* setup rate table sysctls */
820 for (i = 0; i != MLX5E_RL_TABLE_PARAMS_NUM; i++) {
821 mlx5e_rl_sysctl_add_u64_oid(rl,
822 MLX5E_RL_PARAMS_INDEX(table_arg[i]),
823 node, mlx5e_rl_table_params_desc[2 * i],
824 mlx5e_rl_table_params_desc[2 * i + 1]);
828 for (j = 0; j < rl->param.tx_worker_threads_def; j++) {
829 struct mlx5e_rl_worker *rlw = rl->workers + j;
833 cv_init(&rlw->cv, "mlx5-worker-cv");
834 mtx_init(&rlw->mtx, "mlx5-worker-mtx", NULL, MTX_DEF);
835 STAILQ_INIT(&rlw->index_list_head);
836 STAILQ_INIT(&rlw->process_head);
838 rlw->channels = malloc(sizeof(rlw->channels[0]) *
839 rl->param.tx_channels_per_worker_def, M_MLX5EN, M_WAITOK | M_ZERO);
841 MLX5E_RL_WORKER_LOCK(rlw);
842 for (i = 0; i < rl->param.tx_channels_per_worker_def; i++) {
843 struct mlx5e_rl_channel *channel = rlw->channels + i;
844 channel->worker = rlw;
845 channel->m_snd_tag.ifp = priv->ifp;
846 STAILQ_INSERT_TAIL(&rlw->index_list_head, channel, entry);
848 MLX5E_RL_WORKER_UNLOCK(rlw);
852 error = mlx5e_rl_open_workers(priv);
857 "mlx5e_rl_open_workers failed: %d\n", error);
863 mlx5_unmap_free_uar(priv->mdev, &rl->sq_uar);
865 sysctl_ctx_free(&rl->ctx);
866 sx_destroy(&rl->rl_sxlock);
871 mlx5e_rl_open_workers(struct mlx5e_priv *priv)
873 struct mlx5e_rl_priv_data *rl = &priv->rl;
874 struct thread *rl_thread = NULL;
875 struct proc *rl_proc = NULL;
879 if (priv->gone || rl->opened)
883 /* compute channel parameters once */
884 mlx5e_rl_build_channel_param(rl, &rl->chan_param);
885 MLX5E_RL_WUNLOCK(rl);
887 for (j = 0; j < rl->param.tx_worker_threads_def; j++) {
888 struct mlx5e_rl_worker *rlw = rl->workers + j;
890 /* start worker thread */
891 error = kproc_kthread_add(mlx5e_rl_worker, rlw, &rl_proc, &rl_thread,
892 RFHIGHPID, 0, "mlx5-ratelimit", "mlx5-rl-worker-thread-%d", (int)j);
894 if_printf(rl->priv->ifp,
895 "kproc_kthread_add failed: %d\n", error);
896 rlw->worker_done = 1;
906 mlx5e_rl_close_workers(struct mlx5e_priv *priv)
908 struct mlx5e_rl_priv_data *rl = &priv->rl;
914 /* tear down worker threads simultaneously */
915 for (y = 0; y < rl->param.tx_worker_threads_def; y++) {
916 struct mlx5e_rl_worker *rlw = rl->workers + y;
918 /* tear down worker before freeing SQs */
919 MLX5E_RL_WORKER_LOCK(rlw);
920 if (rlw->worker_done == 0) {
921 rlw->worker_done = 1;
922 cv_broadcast(&rlw->cv);
924 /* XXX thread not started */
925 rlw->worker_done = 0;
927 MLX5E_RL_WORKER_UNLOCK(rlw);
930 /* wait for worker threads to exit */
931 for (y = 0; y < rl->param.tx_worker_threads_def; y++) {
932 struct mlx5e_rl_worker *rlw = rl->workers + y;
934 /* tear down worker before freeing SQs */
935 MLX5E_RL_WORKER_LOCK(rlw);
936 while (rlw->worker_done != 0)
937 cv_wait(&rlw->cv, &rlw->mtx);
938 MLX5E_RL_WORKER_UNLOCK(rlw);
945 mlx5e_rl_reset_rates(struct mlx5e_rl_priv_data *rl)
950 for (x = 0; x != rl->param.tx_rates_def; x++)
951 rl->rate_limit_table[x] = 0;
952 MLX5E_RL_WUNLOCK(rl);
956 mlx5e_rl_cleanup(struct mlx5e_priv *priv)
958 struct mlx5e_rl_priv_data *rl = &priv->rl;
961 /* check if there is support for packet pacing */
962 if (!MLX5_CAP_GEN(priv->mdev, qos) || !MLX5_CAP_QOS(priv->mdev, packet_pacing))
965 /* TODO check if there is support for packet pacing */
967 sysctl_ctx_free(&rl->ctx);
970 mlx5e_rl_close_workers(priv);
973 mlx5e_rl_reset_rates(rl);
975 /* free shared UAR for SQs */
976 mlx5_unmap_free_uar(priv->mdev, &rl->sq_uar);
978 /* close TIS domain */
979 mlx5e_rl_close_tis(priv);
981 for (y = 0; y < rl->param.tx_worker_threads_def; y++) {
982 struct mlx5e_rl_worker *rlw = rl->workers + y;
984 cv_destroy(&rlw->cv);
985 mtx_destroy(&rlw->mtx);
986 free(rlw->channels, M_MLX5EN);
988 free(rl->rate_limit_table, M_MLX5EN);
989 free(rl->workers, M_MLX5EN);
990 sx_destroy(&rl->rl_sxlock);
994 mlx5e_rlw_queue_channel_locked(struct mlx5e_rl_worker *rlw,
995 struct mlx5e_rl_channel *channel)
997 STAILQ_INSERT_TAIL(&rlw->process_head, channel, entry);
998 cv_broadcast(&rlw->cv);
1002 mlx5e_rl_free(struct mlx5e_rl_worker *rlw, struct mlx5e_rl_channel *channel)
1004 if (channel == NULL)
1007 MLX5E_RL_WORKER_LOCK(rlw);
1008 switch (channel->state) {
1009 case MLX5E_RL_ST_MODIFY:
1010 channel->state = MLX5E_RL_ST_DESTROY;
1012 case MLX5E_RL_ST_USED:
1013 channel->state = MLX5E_RL_ST_DESTROY;
1014 mlx5e_rlw_queue_channel_locked(rlw, channel);
1019 MLX5E_RL_WORKER_UNLOCK(rlw);
1023 mlx5e_rl_modify(struct mlx5e_rl_worker *rlw, struct mlx5e_rl_channel *channel, uint64_t rate)
1026 MLX5E_RL_WORKER_LOCK(rlw);
1027 channel->new_rate = rate;
1028 switch (channel->state) {
1029 case MLX5E_RL_ST_USED:
1030 channel->state = MLX5E_RL_ST_MODIFY;
1031 mlx5e_rlw_queue_channel_locked(rlw, channel);
1036 MLX5E_RL_WORKER_UNLOCK(rlw);
1042 mlx5e_rl_query(struct mlx5e_rl_worker *rlw, struct mlx5e_rl_channel *channel, uint64_t *prate)
1046 MLX5E_RL_WORKER_LOCK(rlw);
1047 switch (channel->state) {
1048 case MLX5E_RL_ST_USED:
1049 *prate = channel->last_rate;
1052 case MLX5E_RL_ST_MODIFY:
1059 MLX5E_RL_WORKER_UNLOCK(rlw);
1065 mlx5e_find_available_tx_ring_index(struct mlx5e_rl_worker *rlw,
1066 struct mlx5e_rl_channel **pchannel)
1068 struct mlx5e_rl_channel *channel;
1069 int retval = ENOMEM;
1071 MLX5E_RL_WORKER_LOCK(rlw);
1072 /* Check for available channel in free list */
1073 if ((channel = STAILQ_FIRST(&rlw->index_list_head)) != NULL) {
1075 /* Remove head index from available list */
1076 STAILQ_REMOVE_HEAD(&rlw->index_list_head, entry);
1077 channel->state = MLX5E_RL_ST_USED;
1078 atomic_add_64(&rlw->priv->rl.stats.tx_active_connections, 1ULL);
1080 atomic_add_64(&rlw->priv->rl.stats.tx_available_resource_failure, 1ULL);
1082 MLX5E_RL_WORKER_UNLOCK(rlw);
1084 *pchannel = channel;
1085 #ifdef RATELIMIT_DEBUG
1086 if_printf(rlw->priv->ifp, "Channel pointer for rate limit connection is %p\n", channel);
1092 mlx5e_rl_snd_tag_alloc(struct ifnet *ifp,
1093 union if_snd_tag_alloc_params *params,
1094 struct m_snd_tag **ppmt)
1096 struct mlx5e_rl_channel *channel;
1097 struct mlx5e_rl_worker *rlw;
1098 struct mlx5e_priv *priv;
1101 priv = ifp->if_softc;
1103 /* check if there is support for packet pacing or if device is going away */
1104 if (!MLX5_CAP_GEN(priv->mdev, qos) ||
1105 !MLX5_CAP_QOS(priv->mdev, packet_pacing) || priv->gone ||
1106 params->rate_limit.hdr.type != IF_SND_TAG_TYPE_RATE_LIMIT)
1107 return (EOPNOTSUPP);
1109 /* compute worker thread this TCP connection belongs to */
1110 rlw = priv->rl.workers + ((params->rate_limit.hdr.flowid % 128) %
1111 priv->rl.param.tx_worker_threads_def);
1113 error = mlx5e_find_available_tx_ring_index(rlw, &channel);
1117 error = mlx5e_rl_modify(rlw, channel, params->rate_limit.max_rate);
1119 mlx5e_rl_free(rlw, channel);
1123 /* store pointer to mbuf tag */
1124 *ppmt = &channel->m_snd_tag;
1131 mlx5e_rl_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
1133 struct mlx5e_rl_channel *channel =
1134 container_of(pmt, struct mlx5e_rl_channel, m_snd_tag);
1136 return (mlx5e_rl_modify(channel->worker, channel, params->rate_limit.max_rate));
1140 mlx5e_rl_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
1142 struct mlx5e_rl_channel *channel =
1143 container_of(pmt, struct mlx5e_rl_channel, m_snd_tag);
1145 return (mlx5e_rl_query(channel->worker, channel, ¶ms->rate_limit.max_rate));
1149 mlx5e_rl_snd_tag_free(struct m_snd_tag *pmt)
1151 struct mlx5e_rl_channel *channel =
1152 container_of(pmt, struct mlx5e_rl_channel, m_snd_tag);
1154 mlx5e_rl_free(channel->worker, channel);
1158 mlx5e_rl_sysctl_show_rate_table(SYSCTL_HANDLER_ARGS)
1160 struct mlx5e_rl_priv_data *rl = arg1;
1161 struct mlx5e_priv *priv = rl->priv;
1166 error = sysctl_wire_old_buffer(req, 0);
1172 sbuf_new_for_sysctl(&sbuf, NULL, 128 * rl->param.tx_rates_def, req);
1175 "\n\n" "\t" "ENTRY" "\t" "BURST" "\t" "RATE [bit/s]\n"
1176 "\t" "--------------------------------------------\n");
1179 for (x = 0; x != rl->param.tx_rates_def; x++) {
1180 if (rl->rate_limit_table[x] == 0)
1183 sbuf_printf(&sbuf, "\t" "%3u" "\t" "%3u" "\t" "%lld\n",
1184 x, (unsigned)rl->param.tx_burst_size,
1185 (long long)rl->rate_limit_table[x]);
1187 MLX5E_RL_RUNLOCK(rl);
1189 error = sbuf_finish(&sbuf);
1198 mlx5e_rl_refresh_channel_params(struct mlx5e_rl_priv_data *rl)
1204 /* compute channel parameters once */
1205 mlx5e_rl_build_channel_param(rl, &rl->chan_param);
1206 MLX5E_RL_WUNLOCK(rl);
1208 for (y = 0; y != rl->param.tx_worker_threads_def; y++) {
1209 struct mlx5e_rl_worker *rlw = rl->workers + y;
1211 for (x = 0; x != rl->param.tx_channels_per_worker_def; x++) {
1212 struct mlx5e_rl_channel *channel;
1213 struct mlx5e_sq *sq;
1215 channel = rlw->channels + x;
1221 if (MLX5_CAP_GEN(rl->priv->mdev, cq_period_mode_modify)) {
1222 mlx5_core_modify_cq_moderation_mode(rl->priv->mdev, &sq->cq.mcq,
1223 rl->param.tx_coalesce_usecs,
1224 rl->param.tx_coalesce_pkts,
1225 rl->param.tx_coalesce_mode);
1227 mlx5_core_modify_cq_moderation(rl->priv->mdev, &sq->cq.mcq,
1228 rl->param.tx_coalesce_usecs,
1229 rl->param.tx_coalesce_pkts);
1237 mlx5e_rl_tx_limit_add(struct mlx5e_rl_priv_data *rl, uint64_t value)
1243 mlx5_rl_is_in_range(rl->priv->mdev, howmany(value, 1000), 0) == 0)
1249 /* check if rate already exists */
1250 for (x = 0; x != rl->param.tx_rates_def; x++) {
1251 if (rl->rate_limit_table[x] != value)
1257 /* check if there is a free rate entry */
1258 if (x == rl->param.tx_rates_def) {
1259 for (x = 0; x != rl->param.tx_rates_def; x++) {
1260 if (rl->rate_limit_table[x] != 0)
1262 rl->rate_limit_table[x] = value;
1267 MLX5E_RL_WUNLOCK(rl);
1273 mlx5e_rl_tx_limit_clr(struct mlx5e_rl_priv_data *rl, uint64_t value)
1283 /* check if rate already exists */
1284 for (x = 0; x != rl->param.tx_rates_def; x++) {
1285 if (rl->rate_limit_table[x] != value)
1288 rl->rate_limit_table[x] = 0;
1292 /* check if there is a free rate entry */
1293 if (x == rl->param.tx_rates_def)
1297 MLX5E_RL_WUNLOCK(rl);
1303 mlx5e_rl_sysctl_handler(SYSCTL_HANDLER_ARGS)
1305 struct mlx5e_rl_priv_data *rl = arg1;
1306 struct mlx5e_priv *priv = rl->priv;
1307 unsigned mode_modify;
1308 unsigned was_opened;
1316 value = rl->param.arg[arg2];
1317 MLX5E_RL_RUNLOCK(rl);
1321 error = sysctl_handle_64(oidp, &value, 0, req);
1322 if (error || req->newptr == NULL ||
1323 value == rl->param.arg[arg2])
1330 /* check if device is gone */
1335 was_opened = rl->opened;
1336 mode_modify = MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify);
1338 switch (MLX5E_RL_PARAMS_INDEX(arg[arg2])) {
1339 case MLX5E_RL_PARAMS_INDEX(tx_worker_threads_def):
1340 if (value > rl->param.tx_worker_threads_max)
1341 value = rl->param.tx_worker_threads_max;
1345 /* store new value */
1346 rl->param.arg[arg2] = value;
1349 case MLX5E_RL_PARAMS_INDEX(tx_channels_per_worker_def):
1350 if (value > rl->param.tx_channels_per_worker_max)
1351 value = rl->param.tx_channels_per_worker_max;
1355 /* store new value */
1356 rl->param.arg[arg2] = value;
1359 case MLX5E_RL_PARAMS_INDEX(tx_rates_def):
1360 if (value > rl->param.tx_rates_max)
1361 value = rl->param.tx_rates_max;
1365 /* store new value */
1366 rl->param.arg[arg2] = value;
1369 case MLX5E_RL_PARAMS_INDEX(tx_coalesce_usecs):
1373 else if (value > MLX5E_FLD_MAX(cqc, cq_period))
1374 value = MLX5E_FLD_MAX(cqc, cq_period);
1376 /* store new value */
1377 rl->param.arg[arg2] = value;
1379 /* check to avoid down and up the network interface */
1381 error = mlx5e_rl_refresh_channel_params(rl);
1384 case MLX5E_RL_PARAMS_INDEX(tx_coalesce_pkts):
1385 /* import TX coal pkts */
1388 else if (value > MLX5E_FLD_MAX(cqc, cq_max_count))
1389 value = MLX5E_FLD_MAX(cqc, cq_max_count);
1391 /* store new value */
1392 rl->param.arg[arg2] = value;
1394 /* check to avoid down and up the network interface */
1396 error = mlx5e_rl_refresh_channel_params(rl);
1399 case MLX5E_RL_PARAMS_INDEX(tx_coalesce_mode):
1400 /* network interface must be down */
1401 if (was_opened != 0 && mode_modify == 0)
1402 mlx5e_rl_close_workers(priv);
1404 /* import TX coalesce mode */
1408 /* store new value */
1409 rl->param.arg[arg2] = value;
1411 /* restart network interface, if any */
1412 if (was_opened != 0) {
1413 if (mode_modify == 0)
1414 mlx5e_rl_open_workers(priv);
1416 error = mlx5e_rl_refresh_channel_params(rl);
1420 case MLX5E_RL_PARAMS_INDEX(tx_queue_size):
1421 /* network interface must be down */
1423 mlx5e_rl_close_workers(priv);
1425 /* import TX queue size */
1426 if (value < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE))
1427 value = (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
1428 else if (value > priv->params_ethtool.tx_queue_size_max)
1429 value = priv->params_ethtool.tx_queue_size_max;
1431 /* store actual TX queue size */
1432 value = 1ULL << order_base_2(value);
1434 /* store new value */
1435 rl->param.arg[arg2] = value;
1437 /* verify TX completion factor */
1438 mlx5e_rl_sync_tx_completion_fact(rl);
1440 /* restart network interface, if any */
1442 mlx5e_rl_open_workers(priv);
1445 case MLX5E_RL_PARAMS_INDEX(tx_completion_fact):
1446 /* network interface must be down */
1448 mlx5e_rl_close_workers(priv);
1450 /* store new value */
1451 rl->param.arg[arg2] = value;
1453 /* verify parameter */
1454 mlx5e_rl_sync_tx_completion_fact(rl);
1456 /* restart network interface, if any */
1458 mlx5e_rl_open_workers(priv);
1461 case MLX5E_RL_PARAMS_INDEX(tx_limit_add):
1462 error = mlx5e_rl_tx_limit_add(rl, value);
1465 case MLX5E_RL_PARAMS_INDEX(tx_limit_clr):
1466 error = mlx5e_rl_tx_limit_clr(rl, value);
1469 case MLX5E_RL_PARAMS_INDEX(tx_allowed_deviation):
1471 if (value > rl->param.tx_allowed_deviation_max)
1472 value = rl->param.tx_allowed_deviation_max;
1473 else if (value < rl->param.tx_allowed_deviation_min)
1474 value = rl->param.tx_allowed_deviation_min;
1477 rl->param.arg[arg2] = value;
1478 MLX5E_RL_WUNLOCK(rl);
1481 case MLX5E_RL_PARAMS_INDEX(tx_burst_size):
1483 if (value > rl->param.tx_burst_size_max)
1484 value = rl->param.tx_burst_size_max;
1485 else if (value < rl->param.tx_burst_size_min)
1486 value = rl->param.tx_burst_size_min;
1489 rl->param.arg[arg2] = value;
1490 MLX5E_RL_WUNLOCK(rl);
1502 mlx5e_rl_sysctl_add_u64_oid(struct mlx5e_rl_priv_data *rl, unsigned x,
1503 struct sysctl_oid *node, const char *name, const char *desc)
1506 * NOTE: In FreeBSD-11 and newer the CTLFLAG_RWTUN flag will
1507 * take care of loading default sysctl value from the kernel
1508 * environment, if any:
1510 if (strstr(name, "_max") != 0 || strstr(name, "_min") != 0) {
1511 /* read-only SYSCTLs */
1512 SYSCTL_ADD_PROC(&rl->ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1513 name, CTLTYPE_U64 | CTLFLAG_RD |
1514 CTLFLAG_MPSAFE, rl, x, &mlx5e_rl_sysctl_handler, "QU", desc);
1516 if (strstr(name, "_def") != 0) {
1517 #ifdef RATELIMIT_DEBUG
1518 /* tunable read-only advanced SYSCTLs */
1519 SYSCTL_ADD_PROC(&rl->ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1520 name, CTLTYPE_U64 | CTLFLAG_RDTUN |
1521 CTLFLAG_MPSAFE, rl, x, &mlx5e_rl_sysctl_handler, "QU", desc);
1524 /* read-write SYSCTLs */
1525 SYSCTL_ADD_PROC(&rl->ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1526 name, CTLTYPE_U64 | CTLFLAG_RWTUN |
1527 CTLFLAG_MPSAFE, rl, x, &mlx5e_rl_sysctl_handler, "QU", desc);
1533 mlx5e_rl_sysctl_add_stats_u64_oid(struct mlx5e_rl_priv_data *rl, unsigned x,
1534 struct sysctl_oid *node, const char *name, const char *desc)
1536 /* read-only SYSCTLs */
1537 SYSCTL_ADD_U64(&rl->ctx, SYSCTL_CHILDREN(node), OID_AUTO, name,
1538 CTLFLAG_RD, &rl->stats.arg[x], 0, desc);