2 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
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5 * modification, are permitted provided that the following conditions
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28 #ifndef __MLX5_EN_PORT_BUFFER_H__
29 #define __MLX5_EN_PORT_BUFFER_H__
32 #include <dev/mlx5/port.h>
34 #define MLX5E_MAX_BUFFER 8
35 #define MLX5E_BUFFER_CELL_SHIFT 7
36 #define MLX5E_DEFAULT_CABLE_LEN 7 /* 7 meters */
38 #define MLX5_BUFFER_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, pcam_reg) && \
39 MLX5_CAP_PCAM_REG(mdev, pbmc) && \
40 MLX5_CAP_PCAM_REG(mdev, pptb))
43 MLX5E_PORT_BUFFER_CABLE_LEN = BIT(0),
44 MLX5E_PORT_BUFFER_PFC = BIT(1),
45 MLX5E_PORT_BUFFER_PRIO2BUFFER = BIT(2),
46 MLX5E_PORT_BUFFER_SIZE = BIT(3),
49 struct mlx5e_bufferx_reg {
57 struct mlx5e_port_buffer {
59 u32 spare_buffer_size;
60 struct mlx5e_bufferx_reg buffer[MLX5E_MAX_BUFFER];
63 #define IEEE_8021QAZ_MAX_TCS 8
70 __u64 requests[IEEE_8021QAZ_MAX_TCS];
71 __u64 indications[IEEE_8021QAZ_MAX_TCS];
74 int mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv,
75 u32 change, unsigned int mtu,
80 int mlx5e_port_query_buffer(struct mlx5e_priv *priv,
81 struct mlx5e_port_buffer *port_buffer);