2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef __MLX5_FPGA_H__
36 #define __MLX5_FPGA_H__
38 #include <linux/in6.h>
39 #include <dev/mlx5/driver.h>
40 #include <dev/mlx5/mlx5io.h>
42 enum mlx5_fpga_qpc_field_select {
43 MLX5_FPGA_QPC_STATE = BIT(0),
46 struct mlx5_fpga_qp_counters {
54 struct mlx5_fpga_shell_counters {
55 u64 ddr_read_requests;
56 u64 ddr_write_requests;
61 int mlx5_fpga_caps(struct mlx5_core_dev *dev);
62 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
63 int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
64 struct mlx5_fpga_temperature *temp);
65 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
66 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
67 void *buf, bool write);
68 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
69 int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image);
70 int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
71 enum mlx5_fpga_image image);
72 int mlx5_fpga_ctrl_connect(struct mlx5_core_dev *dev,
73 enum mlx5_fpga_connect *connect);
74 int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
75 struct mlx5_fpga_shell_counters *data);
77 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
79 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
80 enum mlx5_fpga_qpc_field_select fields, void *fpga_qpc);
81 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev, u32 fpga_qpn, void *fpga_qpc);
82 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
83 bool clear, struct mlx5_fpga_qp_counters *data);
84 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn);
86 #endif /* __MLX5_FPGA_H__ */