2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef __MLX5_FPGA_CORE_H__
36 #define __MLX5_FPGA_CORE_H__
38 #ifdef CONFIG_MLX5_FPGA
40 #include <dev/mlx5/mlx5_fpga/cmd.h>
41 #include <dev/mlx5/mlx5_fpga/sdk.h>
43 /* Represents client-specific and Innova device-specific information */
44 struct mlx5_fpga_client_data {
45 struct list_head list;
46 struct mlx5_fpga_client *client;
51 enum mlx5_fdev_state {
52 MLX5_FDEV_STATE_SUCCESS = 0,
53 MLX5_FDEV_STATE_FAILURE = 1,
54 MLX5_FDEV_STATE_IN_PROGRESS = 2,
55 MLX5_FDEV_STATE_DISCONNECTED = 3,
56 MLX5_FDEV_STATE_NONE = 0xFFFF,
59 /* Represents an Innova device */
60 struct mlx5_fpga_device {
61 struct mlx5_core_dev *mdev;
62 struct completion load_event;
63 spinlock_t state_lock; /* Protects state transitions */
64 enum mlx5_fdev_state fdev_state;
65 enum mlx5_fpga_status image_status;
66 enum mlx5_fpga_image last_admin_image;
67 enum mlx5_fpga_image last_oper_image;
69 /* QP Connection resources */
72 struct mlx5_core_mkey mkey;
73 struct mlx5_uars_page *uar;
76 struct mlx5_fpga_ipsec *ipsec;
78 struct list_head list;
79 struct list_head client_data_list;
81 /* Shell Transactions state */
82 struct mlx5_fpga_conn *shell_conn;
83 struct mlx5_fpga_trans_device_state *trans;
86 #define mlx5_fpga_dbg(__adev, format, ...) \
87 dev_dbg(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
88 __func__, __LINE__, current->pid, ##__VA_ARGS__)
90 #define mlx5_fpga_err(__adev, format, ...) \
91 dev_err(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
92 __func__, __LINE__, current->pid, ##__VA_ARGS__)
94 #define mlx5_fpga_warn(__adev, format, ...) \
95 dev_warn(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
96 __func__, __LINE__, current->pid, ##__VA_ARGS__)
98 #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
99 dev_warn_ratelimited(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d: " \
100 format, __func__, __LINE__, ##__VA_ARGS__)
102 #define mlx5_fpga_notice(__adev, format, ...) \
103 dev_notice(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
105 #define mlx5_fpga_info(__adev, format, ...) \
106 dev_info(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
108 int mlx5_fpga_init(struct mlx5_core_dev *mdev);
109 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
110 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
111 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
112 void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event, void *data);
116 static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
121 static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
125 static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
130 static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
134 static inline void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event,
141 #endif /* __MLX5_FPGA_CORE_H__ */