2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef MLX5_IFC_FPGA_H
36 #define MLX5_IFC_FPGA_H
39 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
43 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_EXAMPLE = 0x1,
44 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
45 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3,
49 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SHELL_QP = 0x1,
50 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SANDBOX_QP = 0x2,
53 struct mlx5_ifc_fpga_shell_caps_bits {
55 u8 reserved_at_10[0x8];
56 u8 total_rcv_credits[0x8];
58 u8 reserved_at_20[0xe];
60 u8 reserved_at_30[0x5];
64 u8 reserved_at_38[0x4];
70 u8 reserved_at_40[0x1a];
73 u8 max_fpga_qp_msg_size[0x20];
75 u8 reserved_at_80[0x180];
78 struct mlx5_ifc_fpga_cap_bits {
82 u8 register_file_ver[0x20];
84 u8 fpga_ctrl_modify[0x1];
85 u8 reserved_at_41[0x5];
86 u8 access_reg_query_mode[0x2];
87 u8 reserved_at_48[0x6];
88 u8 access_reg_modify_mode[0x2];
89 u8 reserved_at_50[0x10];
91 u8 reserved_at_60[0x20];
93 u8 image_version[0x20];
99 u8 shell_version[0x20];
101 u8 reserved_at_100[0x80];
103 struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
105 u8 reserved_at_380[0x8];
106 u8 ieee_vendor_id[0x18];
108 u8 sandbox_product_version[0x10];
109 u8 sandbox_product_id[0x10];
111 u8 sandbox_basic_caps[0x20];
113 u8 reserved_at_3e0[0x10];
114 u8 sandbox_extended_caps_len[0x10];
116 u8 sandbox_extended_caps_addr[0x40];
118 u8 fpga_ddr_start_addr[0x40];
120 u8 fpga_cr_space_start_addr[0x40];
122 u8 fpga_ddr_size[0x20];
124 u8 fpga_cr_space_size[0x20];
126 u8 reserved_at_500[0x300];
130 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1,
131 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2,
132 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3,
133 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4,
134 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5,
135 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6,
136 MLX5_FPGA_CTRL_OPERATION_DISCONNECT = 0x9,
137 MLX5_FPGA_CTRL_OPERATION_CONNECT = 0xA,
138 MLX5_FPGA_CTRL_OPERATION_RELOAD = 0xB,
141 struct mlx5_ifc_fpga_ctrl_bits {
142 u8 reserved_at_0[0x8];
144 u8 reserved_at_10[0x8];
147 u8 reserved_at_20[0x8];
148 u8 flash_select_admin[0x8];
149 u8 reserved_at_30[0x8];
150 u8 flash_select_oper[0x8];
152 u8 reserved_at_40[0x40];
156 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1,
157 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2,
158 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3,
159 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4,
160 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5,
161 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6,
162 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
165 struct mlx5_ifc_fpga_error_event_bits {
166 u8 reserved_at_0[0x40];
168 u8 reserved_at_40[0x18];
171 u8 reserved_at_60[0x80];
174 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
176 struct mlx5_ifc_fpga_access_reg_bits {
177 u8 reserved_at_0[0x20];
179 u8 reserved_at_20[0x10];
187 enum mlx5_ifc_fpga_qp_state {
188 MLX5_FPGA_QPC_STATE_INIT = 0x0,
189 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1,
190 MLX5_FPGA_QPC_STATE_ERROR = 0x2,
193 enum mlx5_ifc_fpga_qp_type {
194 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0,
195 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1,
198 enum mlx5_ifc_fpga_qp_service_type {
199 MLX5_FPGA_QPC_ST_RC = 0x0,
202 struct mlx5_ifc_fpga_qpc_bits {
204 u8 reserved_at_4[0x1b];
207 u8 reserved_at_20[0x4];
209 u8 reserved_at_28[0x10];
210 u8 traffic_class[0x8];
217 u8 reserved_at_60[0x20];
219 u8 reserved_at_80[0x8];
220 u8 next_rcv_psn[0x18];
222 u8 reserved_at_a0[0x8];
223 u8 next_send_psn[0x18];
225 u8 reserved_at_c0[0x10];
228 u8 reserved_at_e0[0x8];
231 u8 reserved_at_100[0x15];
233 u8 reserved_at_118[0x5];
236 u8 reserved_at_120[0x20];
238 u8 reserved_at_140[0x10];
239 u8 remote_mac_47_32[0x10];
241 u8 remote_mac_31_0[0x20];
243 u8 remote_ip[16][0x8];
245 u8 reserved_at_200[0x40];
247 u8 reserved_at_240[0x10];
248 u8 fpga_mac_47_32[0x10];
250 u8 fpga_mac_31_0[0x20];
255 struct mlx5_ifc_fpga_create_qp_in_bits {
257 u8 reserved_at_10[0x10];
259 u8 reserved_at_20[0x10];
262 u8 reserved_at_40[0x40];
264 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
267 struct mlx5_ifc_fpga_create_qp_out_bits {
269 u8 reserved_at_8[0x18];
273 u8 reserved_at_40[0x8];
276 u8 reserved_at_60[0x20];
278 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
281 struct mlx5_ifc_fpga_modify_qp_in_bits {
283 u8 reserved_at_10[0x10];
285 u8 reserved_at_20[0x10];
288 u8 reserved_at_40[0x8];
291 u8 field_select[0x20];
293 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
296 struct mlx5_ifc_fpga_modify_qp_out_bits {
298 u8 reserved_at_8[0x18];
302 u8 reserved_at_40[0x40];
305 struct mlx5_ifc_fpga_query_qp_in_bits {
307 u8 reserved_at_10[0x10];
309 u8 reserved_at_20[0x10];
312 u8 reserved_at_40[0x8];
315 u8 reserved_at_60[0x20];
318 struct mlx5_ifc_fpga_query_qp_out_bits {
320 u8 reserved_at_8[0x18];
324 u8 reserved_at_40[0x40];
326 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
329 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
331 u8 reserved_at_10[0x10];
333 u8 reserved_at_20[0x10];
337 u8 reserved_at_41[0x7];
340 u8 reserved_at_60[0x20];
343 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
345 u8 reserved_at_8[0x18];
349 u8 reserved_at_40[0x40];
351 u8 rx_ack_packets[0x40];
353 u8 rx_send_packets[0x40];
355 u8 tx_ack_packets[0x40];
357 u8 tx_send_packets[0x40];
359 u8 rx_total_drop[0x40];
361 u8 reserved_at_1c0[0x1c0];
364 struct mlx5_ifc_fpga_destroy_qp_in_bits {
366 u8 reserved_at_10[0x10];
368 u8 reserved_at_20[0x10];
371 u8 reserved_at_40[0x8];
374 u8 reserved_at_60[0x20];
377 struct mlx5_ifc_fpga_destroy_qp_out_bits {
379 u8 reserved_at_8[0x18];
383 u8 reserved_at_40[0x40];
386 struct mlx5_ifc_ipsec_extended_cap_bits {
387 u8 encapsulation[0x20];
390 u8 ipv4_fragment[0x1];
394 u8 transport_and_tunnel_mode[0x1];
396 u8 transport_mode[0x1];
400 u8 ipv4_options[0x1];
409 u8 number_of_ipsec_counters[0x10];
411 u8 ipsec_counters_addr_low[0x20];
412 u8 ipsec_counters_addr_high[0x20];
415 struct mlx5_ifc_ipsec_counters_bits {
416 u8 dec_in_packets[0x40];
418 u8 dec_out_packets[0x40];
420 u8 dec_bypass_packets[0x40];
422 u8 enc_in_packets[0x40];
424 u8 enc_out_packets[0x40];
426 u8 enc_bypass_packets[0x40];
428 u8 drop_dec_packets[0x40];
430 u8 failed_auth_dec_packets[0x40];
432 u8 drop_enc_packets[0x40];
434 u8 success_add_sa[0x40];
436 u8 fail_add_sa[0x40];
438 u8 success_delete_sa[0x40];
440 u8 fail_delete_sa[0x40];
442 u8 dropped_cmd[0x40];
445 struct mlx5_ifc_fpga_shell_counters_bits {
453 u8 ddr_read_requests[0x40];
455 u8 ddr_write_requests[0x40];
457 u8 ddr_read_bytes[0x40];
459 u8 ddr_write_bytes[0x40];
461 u8 reserved_3[0x200];
465 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ = 0x0,
466 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE = 0x1,
467 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ_RESPONSE = 0x2,
468 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE = 0x3,
471 struct mlx5_ifc_fpga_shell_qp_packet_bits {
474 u8 reserved_at_8[0x4];
476 u8 reserved_at_10[0x8];
487 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1,
488 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2,
491 struct mlx5_ifc_fpga_qp_error_event_bits {
503 #endif /* MLX5_IFC_FPGA_H */