sys/dev/mlx5/mlx5_fpga/mlx5fpga_cmd.c

   1 /*-
   2  * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 #include <dev/mlx5/cmd.h>
  36 #include <dev/mlx5/driver.h>
  37 #include <dev/mlx5/device.h>
  38 #include <dev/mlx5/mlx5_core/mlx5_core.h>
  39 #include <dev/mlx5/mlx5_fpga/cmd.h>
  40
  41 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
  42                                  MLX5_FPGA_ACCESS_REG_SIZE_MAX)
  43
  44 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
  45                          void *buf, bool write)
  46 {
  47         u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
  48         u32 out[MLX5_FPGA_ACCESS_REG_SZ];
  49         int err;
  50
  51         if (size & 3)
  52                 return -EINVAL;
  53         if (addr & 3)
  54                 return -EINVAL;
  55         if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
  56                 return -EINVAL;
  57
  58         MLX5_SET(fpga_access_reg, in, size, size);
  59         MLX5_SET64(fpga_access_reg, in, address, addr);
  60         if (write)
  61                 memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
  62
  63         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
  64                                    MLX5_REG_FPGA_ACCESS_REG, 0, write);
  65         if (err)
  66                 return err;
  67
  68         if (!write)
  69                 memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
  70
  71         return 0;
  72 }
  73
  74 int mlx5_fpga_caps(struct mlx5_core_dev *dev)
  75 {
  76         u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
  77
  78         return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
  79                                     MLX5_ST_SZ_BYTES(fpga_cap),
  80                                     MLX5_REG_FPGA_CAP, 0, 0);
  81 }
  82
  83 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
  84 {
  85         u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
  86         u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
  87
  88         MLX5_SET(fpga_ctrl, in, operation, op);
  89
  90         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
  91                                     MLX5_REG_FPGA_CTRL, 0, true);
  92 }
  93
  94 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
  95 {
  96         unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
  97         u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
  98         unsigned int read;
  99         int ret = 0;
 100
 101         if (cap_size > size) {
 102                 mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
 103                                size, cap_size);
 104                 return -EINVAL;
 105         }
 106
 107         while (cap_size > 0) {
 108                 read = min_t(unsigned int, cap_size,
 109                              MLX5_FPGA_ACCESS_REG_SIZE_MAX);
 110
 111                 ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
 112                 if (ret) {
 113                         mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address %#jx: %d",
 114                                        read, (uintmax_t)addr, ret);
 115                         return ret;
 116                 }
 117
 118                 cap_size -= read;
 119                 addr += read;
 120                 caps += read;
 121         }
 122
 123         return ret;
 124 }
 125
 126 static int mlx5_fpga_ctrl_write(struct mlx5_core_dev *dev, u8 op,
 127                                 enum mlx5_fpga_image image)
 128 {
 129         u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 130         u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 131
 132         MLX5_SET(fpga_ctrl, in, operation, op);
 133         MLX5_SET(fpga_ctrl, in, flash_select_admin, image);
 134
 135         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 136                                     MLX5_REG_FPGA_CTRL, 0, true);
 137 }
 138
 139 int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image)
 140 {
 141         return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_LOAD, image);
 142 }
 143
 144 int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
 145                            enum mlx5_fpga_image image)
 146 {
 147         return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT, image);
 148 }
 149
 150 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
 151 {
 152         u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 153         u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 154         int err;
 155
 156         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 157                                    MLX5_REG_FPGA_CTRL, 0, false);
 158         if (err)
 159                 return err;
 160
 161         query->image_status = MLX5_GET(fpga_ctrl, out, status);
 162         query->admin_image = MLX5_GET(fpga_ctrl, out, flash_select_admin);
 163         query->oper_image = MLX5_GET(fpga_ctrl, out, flash_select_oper);
 164         return 0;
 165 }
 166
 167 int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
 168                          struct mlx5_fpga_temperature *temp)
 169 {
 170         u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
 171         u32 out[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
 172         int err;
 173
 174         MLX5_SET(mtmp_reg, in, sensor_index, temp->index);
 175         MLX5_SET(mtmp_reg, in, i,
 176                  ((temp->index < MLX5_FPGA_INTERNAL_SENSORS_LOW) ||
 177                  (temp->index > MLX5_FPGA_INTERNAL_SENSORS_HIGH)) ? 1 : 0);
 178
 179         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 180                                    MLX5_REG_MTMP, 0, false);
 181         if (err)
 182                 return err;
 183
 184         temp->index = MLX5_GET(mtmp_reg, out, sensor_index);
 185         temp->temperature = MLX5_GET(mtmp_reg, out, temperature);
 186         temp->mte = MLX5_GET(mtmp_reg, out, mte);
 187         temp->max_temperature = MLX5_GET(mtmp_reg, out, max_temperature);
 188         temp->tee = MLX5_GET(mtmp_reg, out, tee);
 189         temp->temperature_threshold_hi = MLX5_GET(mtmp_reg, out,
 190                 temperature_threshold_hi);
 191         temp->temperature_threshold_lo = MLX5_GET(mtmp_reg, out,
 192                 temperature_threshold_lo);
 193         memcpy(temp->sensor_name, MLX5_ADDR_OF(mtmp_reg, out, sensor_name),
 194                MLX5_FLD_SZ_BYTES(mtmp_reg, sensor_name));
 195
 196         return 0;
 197 }
 198
 199 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
 200                         u32 *fpga_qpn)
 201 {
 202         u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
 203         u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
 204         int ret;
 205
 206         MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
 207         memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
 208                MLX5_FLD_SZ_BYTES(fpga_create_qp_in, fpga_qpc));
 209
 210         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 211         if (ret)
 212                 return ret;
 213
 214         memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_create_qp_out, out, fpga_qpc),
 215                MLX5_FLD_SZ_BYTES(fpga_create_qp_out, fpga_qpc));
 216         *fpga_qpn = MLX5_GET(fpga_create_qp_out, out, fpga_qpn);
 217         return ret;
 218 }
 219
 220 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
 221                         enum mlx5_fpga_qpc_field_select fields,
 222                         void *fpga_qpc)
 223 {
 224         u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
 225         u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
 226
 227         MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
 228         MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
 229         MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
 230         memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
 231                MLX5_FLD_SZ_BYTES(fpga_modify_qp_in, fpga_qpc));
 232
 233         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 234 }
 235
 236 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev,
 237                        u32 fpga_qpn, void *fpga_qpc)
 238 {
 239         u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
 240         u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
 241         int ret;
 242
 243         MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
 244         MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
 245
 246         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 247         if (ret)
 248                 return ret;
 249
 250         memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_query_qp_out, out, fpga_qpc),
 251                MLX5_FLD_SZ_BYTES(fpga_query_qp_out, fpga_qpc));
 252         return ret;
 253 }
 254
 255 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn)
 256 {
 257         u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
 258         u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
 259
 260         MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
 261         MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
 262
 263         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 264 }
 265
 266 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
 267                                 bool clear, struct mlx5_fpga_qp_counters *data)
 268 {
 269         u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
 270         u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
 271         int ret;
 272
 273         MLX5_SET(fpga_query_qp_counters_in, in, opcode,
 274                  MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS);
 275         MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
 276         MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
 277
 278         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 279         if (ret)
 280                 return ret;
 281
 282         data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 283                                           rx_ack_packets);
 284         data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 285                                            rx_send_packets);
 286         data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 287                                           tx_ack_packets);
 288         data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 289                                            tx_send_packets);
 290         data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,
 291                                          rx_total_drop);
 292
 293         return ret;
 294 }
 295
 296 int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
 297                              struct mlx5_fpga_shell_counters *data)
 298 {
 299         u32 in[MLX5_ST_SZ_DW(fpga_shell_counters)] = {0};
 300         u32 out[MLX5_ST_SZ_DW(fpga_shell_counters)];
 301         int err;
 302
 303         MLX5_SET(fpga_shell_counters, in, clear, clear);
 304         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 305                                    MLX5_REG_FPGA_SHELL_CNTR, 0, false);
 306         if (err)
 307                 goto out;
 308         if (data) {
 309                 data->ddr_read_requests = MLX5_GET64(fpga_shell_counters, out,
 310                                                      ddr_read_requests);
 311                 data->ddr_write_requests = MLX5_GET64(fpga_shell_counters, out,
 312                                                       ddr_write_requests);
 313                 data->ddr_read_bytes = MLX5_GET64(fpga_shell_counters, out,
 314                                                   ddr_read_bytes);
 315                 data->ddr_write_bytes = MLX5_GET64(fpga_shell_counters, out,
 316                                                    ddr_write_bytes);
 317         }
 318
 319 out:
 320         return err;
 321 }