2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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35 #include <dev/mlx5/driver.h>
37 #include <dev/mlx5/mlx5_core/mlx5_core.h>
38 #include <dev/mlx5/mlx5_fpga/ipsec.h>
39 #include <dev/mlx5/mlx5_fpga/sdk.h>
40 #include <dev/mlx5/mlx5_fpga/core.h>
42 #define SBU_QP_QUEUE_SIZE 8
44 enum mlx5_ipsec_response_syndrome {
45 MLX5_IPSEC_RESPONSE_SUCCESS = 0,
46 MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,
47 MLX5_IPSEC_RESPONSE_SADB_ISSUE = 2,
48 MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3,
51 enum mlx5_fpga_ipsec_sacmd_status {
52 MLX5_FPGA_IPSEC_SACMD_PENDING,
53 MLX5_FPGA_IPSEC_SACMD_SEND_FAIL,
54 MLX5_FPGA_IPSEC_SACMD_COMPLETE,
57 struct mlx5_ipsec_command_context {
58 struct mlx5_fpga_dma_buf buf;
59 struct mlx5_accel_ipsec_sa sa;
60 enum mlx5_fpga_ipsec_sacmd_status status;
62 struct completion complete;
63 struct mlx5_fpga_device *dev;
64 struct list_head list; /* Item in pending_cmds */
67 struct mlx5_ipsec_sadb_resp {
73 struct mlx5_fpga_ipsec {
74 struct list_head pending_cmds;
75 spinlock_t pending_cmds_lock; /* Protects pending_cmds */
76 u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)];
77 struct mlx5_fpga_conn *conn;
80 static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev)
82 if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga))
85 if (MLX5_CAP_FPGA(mdev, ieee_vendor_id) !=
86 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX)
89 if (MLX5_CAP_FPGA(mdev, sandbox_product_id) !=
90 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC)
96 static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn,
97 struct mlx5_fpga_device *fdev,
98 struct mlx5_fpga_dma_buf *buf,
101 struct mlx5_ipsec_command_context *context;
104 context = container_of(buf, struct mlx5_ipsec_command_context,
106 mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n",
108 context->status = MLX5_FPGA_IPSEC_SACMD_SEND_FAIL;
109 complete(&context->complete);
113 static inline int syndrome_to_errno(enum mlx5_ipsec_response_syndrome syndrome)
116 case MLX5_IPSEC_RESPONSE_SUCCESS:
118 case MLX5_IPSEC_RESPONSE_SADB_ISSUE:
120 case MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST:
122 case MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE:
128 static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf)
130 struct mlx5_ipsec_sadb_resp *resp = buf->sg[0].data;
131 struct mlx5_ipsec_command_context *context;
132 enum mlx5_ipsec_response_syndrome syndrome;
133 struct mlx5_fpga_device *fdev = cb_arg;
136 if (buf->sg[0].size < sizeof(*resp)) {
137 mlx5_fpga_warn(fdev, "Short receive from FPGA IPSec: %u < %zu bytes\n",
138 buf->sg[0].size, sizeof(*resp));
142 mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x sa_id %x\n",
143 ntohl(resp->syndrome), ntohl(resp->sw_sa_handle));
145 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
146 context = list_first_entry_or_null(&fdev->ipsec->pending_cmds,
147 struct mlx5_ipsec_command_context,
150 list_del(&context->list);
151 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
154 mlx5_fpga_warn(fdev, "Received IPSec offload response without pending command request\n");
157 mlx5_fpga_dbg(fdev, "Handling response for %p\n", context);
159 if (context->sa.sw_sa_handle != resp->sw_sa_handle) {
160 mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n",
161 ntohl(context->sa.sw_sa_handle),
162 ntohl(resp->sw_sa_handle));
166 syndrome = ntohl(resp->syndrome);
167 context->status_code = syndrome_to_errno(syndrome);
168 context->status = MLX5_FPGA_IPSEC_SACMD_COMPLETE;
170 if (context->status_code)
171 mlx5_fpga_warn(fdev, "IPSec SADB command failed with syndrome %08x\n",
173 complete(&context->complete);
176 void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
177 struct mlx5_accel_ipsec_sa *cmd)
179 struct mlx5_ipsec_command_context *context;
180 struct mlx5_fpga_device *fdev = mdev->fpga;
184 BUILD_BUG_ON((sizeof(struct mlx5_accel_ipsec_sa) & 3) != 0);
185 if (!fdev || !fdev->ipsec)
186 return ERR_PTR(-EOPNOTSUPP);
188 context = kzalloc(sizeof(*context), GFP_ATOMIC);
190 return ERR_PTR(-ENOMEM);
192 memcpy(&context->sa, cmd, sizeof(*cmd));
193 context->buf.complete = mlx5_fpga_ipsec_send_complete;
194 context->buf.sg[0].size = sizeof(context->sa);
195 context->buf.sg[0].data = &context->sa;
196 init_completion(&context->complete);
198 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
199 list_add_tail(&context->list, &fdev->ipsec->pending_cmds);
200 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
202 context->status = MLX5_FPGA_IPSEC_SACMD_PENDING;
204 res = mlx5_fpga_sbu_conn_sendmsg(fdev->ipsec->conn, &context->buf);
206 mlx5_fpga_warn(fdev, "Failure sending IPSec command: %d\n",
208 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
209 list_del(&context->list);
210 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
214 /* Context will be freed by wait func after completion */
218 int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx)
220 struct mlx5_ipsec_command_context *context = ctx;
223 res = wait_for_completion/*_killable XXXKIB*/(&context->complete);
225 mlx5_fpga_warn(context->dev, "Failure waiting for IPSec command response\n");
229 if (context->status == MLX5_FPGA_IPSEC_SACMD_COMPLETE)
230 res = context->status_code;
238 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
240 struct mlx5_fpga_device *fdev = mdev->fpga;
243 if (mlx5_fpga_is_ipsec_device(mdev))
244 ret |= MLX5_ACCEL_IPSEC_DEVICE;
251 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp))
252 ret |= MLX5_ACCEL_IPSEC_ESP;
254 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6))
255 ret |= MLX5_ACCEL_IPSEC_IPV6;
257 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso))
258 ret |= MLX5_ACCEL_IPSEC_LSO;
263 unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
265 struct mlx5_fpga_device *fdev = mdev->fpga;
267 if (!fdev || !fdev->ipsec)
270 return MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
271 number_of_ipsec_counters);
274 int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
275 unsigned int counters_count)
277 struct mlx5_fpga_device *fdev = mdev->fpga;
284 if (!fdev || !fdev->ipsec)
287 addr = (u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
288 ipsec_counters_addr_low) +
289 ((u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
290 ipsec_counters_addr_high) << 32);
292 count = mlx5_fpga_ipsec_counters_count(mdev);
294 data = kzalloc(sizeof(*data) * count * 2, GFP_KERNEL);
300 ret = mlx5_fpga_mem_read(fdev, count * sizeof(u64), addr, data,
301 MLX5_FPGA_ACCESS_TYPE_DONTCARE);
303 mlx5_fpga_err(fdev, "Failed to read IPSec counters from HW: %d\n",
309 if (count > counters_count)
310 count = counters_count;
312 /* Each counter is low word, then high. But each word is big-endian */
313 for (i = 0; i < count; i++)
314 counters[i] = (u64)ntohl(data[i * 2]) |
315 ((u64)ntohl(data[i * 2 + 1]) << 32);
322 int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
324 struct mlx5_fpga_conn_attr init_attr = {0};
325 struct mlx5_fpga_device *fdev = mdev->fpga;
326 struct mlx5_fpga_conn *conn;
329 if (!mlx5_fpga_is_ipsec_device(mdev))
332 fdev->ipsec = kzalloc(sizeof(*fdev->ipsec), GFP_KERNEL);
336 err = mlx5_fpga_get_sbu_caps(fdev, sizeof(fdev->ipsec->caps),
339 mlx5_fpga_err(fdev, "Failed to retrieve IPSec extended capabilities: %d\n",
344 INIT_LIST_HEAD(&fdev->ipsec->pending_cmds);
345 spin_lock_init(&fdev->ipsec->pending_cmds_lock);
347 init_attr.rx_size = SBU_QP_QUEUE_SIZE;
348 init_attr.tx_size = SBU_QP_QUEUE_SIZE;
349 init_attr.recv_cb = mlx5_fpga_ipsec_recv;
350 init_attr.cb_arg = fdev;
351 conn = mlx5_fpga_sbu_conn_create(fdev, &init_attr);
354 mlx5_fpga_err(fdev, "Error creating IPSec command connection %d\n",
358 fdev->ipsec->conn = conn;
367 void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
369 struct mlx5_fpga_device *fdev = mdev->fpga;
371 if (!mlx5_fpga_is_ipsec_device(mdev))
374 mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn);