2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <dev/mlx5/mlx5_fpga/xfer.h>
36 #include <dev/mlx5/mlx5_fpga/conn.h>
39 const struct mlx5_fpga_transaction *xfer;
40 /* Total transactions */
41 unsigned int start_count;
42 unsigned int done_count;
43 unsigned int error_count;
45 /* Inflight transactions */
47 unsigned int inflight_count;
50 spinlock_t lock; /* Protects all members of this struct */
53 struct xfer_transaction {
54 struct xfer_state *xfer_state;
55 struct mlx5_fpga_transaction transaction;
58 static void trans_complete(const struct mlx5_fpga_transaction *complete,
61 static void xfer_complete(struct xfer_state *xfer_state)
63 const struct mlx5_fpga_transaction *xfer = xfer_state->xfer;
64 u8 status = xfer_state->status;
67 xfer->complete1(xfer, status);
70 /* Xfer state spin lock must be locked */
71 static int exec_more(struct xfer_state *xfer_state)
73 struct xfer_transaction *xfer_trans;
74 size_t left, cur_size, page_size;
75 u64 pos_addr, ddr_base;
79 ddr_base = mlx5_fpga_ddr_base_get(xfer_state->xfer->conn->fdev);
80 page_size = (xfer_state->xfer->addr + xfer_state->pos < ddr_base) ?
81 sizeof(u32) : (1 << MLX5_FPGA_TRANSACTION_SEND_PAGE_BITS);
84 if (xfer_state->status != IB_WC_SUCCESS) {
89 left = xfer_state->xfer->size - xfer_state->pos;
93 xfer_trans = kzalloc(sizeof(*xfer_trans), GFP_ATOMIC);
99 pos_addr = xfer_state->xfer->addr + xfer_state->pos;
100 pos_data = xfer_state->xfer->data + xfer_state->pos;
102 /* Determine largest possible transaction at this point */
103 cur_size = page_size - (pos_addr & (page_size - 1));
104 if (cur_size > MLX5_FPGA_TRANSACTION_MAX_SIZE)
105 cur_size = MLX5_FPGA_TRANSACTION_MAX_SIZE;
109 xfer_trans->xfer_state = xfer_state;
110 xfer_trans->transaction.addr = pos_addr;
111 xfer_trans->transaction.complete1 = trans_complete;
112 xfer_trans->transaction.conn = xfer_state->xfer->conn;
113 xfer_trans->transaction.data = pos_data;
114 xfer_trans->transaction.direction = xfer_state->xfer->direction;
115 xfer_trans->transaction.size = cur_size;
117 xfer_state->start_count++;
118 xfer_state->inflight_count++;
119 mlx5_fpga_dbg(xfer_state->xfer->conn->fdev, "Starting %zu bytes at %p done; %u started %u inflight %u done %u error\n",
120 xfer_trans->transaction.size,
121 xfer_trans->transaction.data,
122 xfer_state->start_count,
123 xfer_state->inflight_count,
124 xfer_state->done_count,
125 xfer_state->error_count);
126 ret = mlx5_fpga_trans_exec(&xfer_trans->transaction);
128 xfer_state->start_count--;
129 xfer_state->inflight_count--;
134 mlx5_fpga_warn(xfer_state->xfer->conn->fdev, "Transfer failed to start transaction: %d. %u started %u done %u error\n",
135 ret, xfer_state->start_count,
136 xfer_state->done_count,
137 xfer_state->error_count);
138 xfer_state->status = IB_WC_GENERAL_ERR;
143 xfer_state->pos += cur_size;
144 if (xfer_state->inflight_count >= xfer_state->budget)
146 } while (cur_size != left);
151 static void trans_complete(const struct mlx5_fpga_transaction *complete,
154 struct xfer_transaction *xfer_trans;
155 struct xfer_state *xfer_state;
160 xfer_trans = container_of(complete, struct xfer_transaction,
162 xfer_state = xfer_trans->xfer_state;
163 mlx5_fpga_dbg(complete->conn->fdev, "Transaction %zu bytes at %p done, status %u; %u started %u inflight %u done %u error\n",
164 xfer_trans->transaction.size,
165 xfer_trans->transaction.data, status,
166 xfer_state->start_count, xfer_state->inflight_count,
167 xfer_state->done_count, xfer_state->error_count);
170 spin_lock_irqsave(&xfer_state->lock, flags);
172 if (status != IB_WC_SUCCESS) {
173 xfer_state->error_count++;
174 mlx5_fpga_warn(complete->conn->fdev, "Transaction failed during transfer. %u started %u inflight %u done %u error\n",
175 xfer_state->start_count,
176 xfer_state->inflight_count,
177 xfer_state->done_count, xfer_state->error_count);
178 if (xfer_state->status == IB_WC_SUCCESS)
179 xfer_state->status = status;
181 xfer_state->done_count++;
183 ret = exec_more(xfer_state);
185 xfer_state->inflight_count--;
186 if (!xfer_state->inflight_count)
189 spin_unlock_irqrestore(&xfer_state->lock, flags);
192 xfer_complete(xfer_state);
195 int mlx5_fpga_xfer_exec(const struct mlx5_fpga_transaction *xfer)
197 u64 base = mlx5_fpga_ddr_base_get(xfer->conn->fdev);
198 u64 size = mlx5_fpga_ddr_size_get(xfer->conn->fdev);
199 struct xfer_state *xfer_state;
204 if (xfer->addr + xfer->size > base + size) {
205 mlx5_fpga_warn(xfer->conn->fdev, "Transfer ends at %jx outside of DDR range %jx\n",
206 (uintmax_t)(xfer->addr + xfer->size), (uintmax_t)(base + size));
210 if (xfer->addr & MLX5_FPGA_TRANSACTION_SEND_ALIGN_BITS) {
211 mlx5_fpga_warn(xfer->conn->fdev, "Transfer address %jx not aligned\n",
212 (uintmax_t)xfer->addr);
216 if (xfer->size & MLX5_FPGA_TRANSACTION_SEND_ALIGN_BITS) {
217 mlx5_fpga_warn(xfer->conn->fdev, "Transfer size %zu not aligned\n",
222 if (xfer->size < 1) {
223 mlx5_fpga_warn(xfer->conn->fdev, "Empty transfer size %zu not allowed\n",
228 xfer_state = kzalloc(sizeof(*xfer_state), GFP_KERNEL);
229 xfer_state->xfer = xfer;
230 xfer_state->status = IB_WC_SUCCESS;
231 xfer_state->budget = 7;
232 spin_lock_init(&xfer_state->lock);
233 spin_lock_irqsave(&xfer_state->lock, flags);
235 ret = exec_more(xfer_state);
236 if (ret && (xfer_state->start_count == 0))
239 spin_unlock_irqrestore(&xfer_state->lock, flags);
242 xfer_complete(xfer_state);