2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #if defined(CONFIG_X86)
36 #include <linux/sched.h>
37 #include <linux/delay.h>
40 #include <rdma/ib_user_verbs.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_cache.h>
43 #include <dev/mlx5/vport.h>
44 #include <linux/list.h>
45 #include <rdma/ib_smi.h>
46 #include <rdma/ib_umem.h>
48 #include <linux/etherdevice.h>
49 #include <dev/mlx5/fs.h>
52 #define DRIVER_NAME "mlx5_ib"
53 #define DRIVER_VERSION "3.4.1-BETA"
54 #define DRIVER_RELDATE "October 2017"
56 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
59 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
60 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
61 MODULE_VERSION(mlx5ib, 1);
63 static int deprecated_prof_sel = 2;
64 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
65 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
67 static char mlx5_version[] =
68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
75 static enum rdma_link_layer
76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
78 switch (port_type_cap) {
79 case MLX5_CAP_PORT_TYPE_IB:
80 return IB_LINK_LAYER_INFINIBAND;
81 case MLX5_CAP_PORT_TYPE_ETH:
82 return IB_LINK_LAYER_ETHERNET;
84 return IB_LINK_LAYER_UNSPECIFIED;
88 static enum rdma_link_layer
89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
91 struct mlx5_ib_dev *dev = to_mdev(device);
92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
97 static bool mlx5_netdev_match(struct net_device *ndev,
98 struct mlx5_core_dev *mdev,
101 return ndev->if_type == IFT_ETHER &&
102 ndev->if_dname != NULL &&
103 strcmp(ndev->if_dname, dname) == 0 &&
104 ndev->if_softc != NULL &&
105 *(struct mlx5_core_dev **)ndev->if_softc == mdev;
108 static int mlx5_netdev_event(struct notifier_block *this,
109 unsigned long event, void *ptr)
111 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
112 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
116 case NETDEV_REGISTER:
117 case NETDEV_UNREGISTER:
118 write_lock(&ibdev->roce.netdev_lock);
119 /* check if network interface belongs to mlx5en */
120 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
121 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
123 write_unlock(&ibdev->roce.netdev_lock);
128 struct net_device *upper = NULL;
130 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
131 && ibdev->ib_active) {
132 struct ib_event ibev = {0};
134 ibev.device = &ibdev->ib_dev;
135 ibev.event = (event == NETDEV_UP) ?
136 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
137 ibev.element.port_num = 1;
138 ib_dispatch_event(&ibev);
150 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
153 struct mlx5_ib_dev *ibdev = to_mdev(device);
154 struct net_device *ndev;
156 /* Ensure ndev does not disappear before we invoke dev_hold()
158 read_lock(&ibdev->roce.netdev_lock);
159 ndev = ibdev->roce.netdev;
162 read_unlock(&ibdev->roce.netdev_lock);
167 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
168 struct ib_port_attr *props)
170 struct mlx5_ib_dev *dev = to_mdev(device);
171 struct net_device *ndev;
172 enum ib_mtu ndev_ib_mtu;
175 memset(props, 0, sizeof(*props));
177 props->port_cap_flags |= IB_PORT_CM_SUP;
178 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
180 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
181 roce_address_table_size);
182 props->max_mtu = IB_MTU_4096;
183 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
184 props->pkey_tbl_len = 1;
185 props->state = IB_PORT_DOWN;
186 props->phys_state = 3;
188 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
189 props->qkey_viol_cntr = qkey_viol_cntr;
191 ndev = mlx5_ib_get_netdev(device, port_num);
195 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
196 props->state = IB_PORT_ACTIVE;
197 props->phys_state = 5;
200 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu);
204 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
206 props->active_width = IB_WIDTH_4X; /* TODO */
207 props->active_speed = IB_SPEED_QDR; /* TODO */
212 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
213 const struct ib_gid_attr *attr,
216 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
217 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
219 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
224 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev));
226 if (is_vlan_dev(attr->ndev)) {
227 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
228 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
231 switch (attr->gid_type) {
233 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
235 case IB_GID_TYPE_ROCE_UDP_ENCAP:
236 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
243 if (attr->gid_type != IB_GID_TYPE_IB) {
244 if (ipv6_addr_v4mapped((void *)gid))
245 MLX5_SET_RA(mlx5_addr, roce_l3_type,
246 MLX5_ROCE_L3_TYPE_IPV4);
248 MLX5_SET_RA(mlx5_addr, roce_l3_type,
249 MLX5_ROCE_L3_TYPE_IPV6);
252 if ((attr->gid_type == IB_GID_TYPE_IB) ||
253 !ipv6_addr_v4mapped((void *)gid))
254 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
256 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
259 static int set_roce_addr(struct ib_device *device, u8 port_num,
261 const union ib_gid *gid,
262 const struct ib_gid_attr *attr)
264 struct mlx5_ib_dev *dev = to_mdev(device);
265 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
266 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
267 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
270 if (ll != IB_LINK_LAYER_ETHERNET)
273 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
275 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
276 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
277 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
280 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
281 unsigned int index, const union ib_gid *gid,
282 const struct ib_gid_attr *attr,
283 __always_unused void **context)
285 return set_roce_addr(device, port_num, index, gid, attr);
288 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
289 unsigned int index, __always_unused void **context)
291 return set_roce_addr(device, port_num, index, NULL, NULL);
294 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
297 struct ib_gid_attr attr;
300 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
308 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
311 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
314 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
316 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
317 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
322 MLX5_VPORT_ACCESS_METHOD_MAD,
323 MLX5_VPORT_ACCESS_METHOD_HCA,
324 MLX5_VPORT_ACCESS_METHOD_NIC,
327 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
329 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
330 return MLX5_VPORT_ACCESS_METHOD_MAD;
332 if (mlx5_ib_port_link_layer(ibdev, 1) ==
333 IB_LINK_LAYER_ETHERNET)
334 return MLX5_VPORT_ACCESS_METHOD_NIC;
336 return MLX5_VPORT_ACCESS_METHOD_HCA;
339 static void get_atomic_caps(struct mlx5_ib_dev *dev,
340 struct ib_device_attr *props)
343 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
344 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
345 u8 atomic_req_8B_endianness_mode =
346 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
348 /* Check if HW supports 8 bytes standard atomic operations and capable
349 * of host endianness respond
351 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
352 if (((atomic_operations & tmp) == tmp) &&
353 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
354 (atomic_req_8B_endianness_mode)) {
355 props->atomic_cap = IB_ATOMIC_HCA;
357 props->atomic_cap = IB_ATOMIC_NONE;
361 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
362 __be64 *sys_image_guid)
364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
365 struct mlx5_core_dev *mdev = dev->mdev;
369 switch (mlx5_get_vport_access_method(ibdev)) {
370 case MLX5_VPORT_ACCESS_METHOD_MAD:
371 return mlx5_query_mad_ifc_system_image_guid(ibdev,
374 case MLX5_VPORT_ACCESS_METHOD_HCA:
375 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
378 case MLX5_VPORT_ACCESS_METHOD_NIC:
379 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
387 *sys_image_guid = cpu_to_be64(tmp);
393 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
396 struct mlx5_ib_dev *dev = to_mdev(ibdev);
397 struct mlx5_core_dev *mdev = dev->mdev;
399 switch (mlx5_get_vport_access_method(ibdev)) {
400 case MLX5_VPORT_ACCESS_METHOD_MAD:
401 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
403 case MLX5_VPORT_ACCESS_METHOD_HCA:
404 case MLX5_VPORT_ACCESS_METHOD_NIC:
405 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
414 static int mlx5_query_vendor_id(struct ib_device *ibdev,
417 struct mlx5_ib_dev *dev = to_mdev(ibdev);
419 switch (mlx5_get_vport_access_method(ibdev)) {
420 case MLX5_VPORT_ACCESS_METHOD_MAD:
421 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
423 case MLX5_VPORT_ACCESS_METHOD_HCA:
424 case MLX5_VPORT_ACCESS_METHOD_NIC:
425 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
432 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
438 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
439 case MLX5_VPORT_ACCESS_METHOD_MAD:
440 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
442 case MLX5_VPORT_ACCESS_METHOD_HCA:
443 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
446 case MLX5_VPORT_ACCESS_METHOD_NIC:
447 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
455 *node_guid = cpu_to_be64(tmp);
460 struct mlx5_reg_node_desc {
461 u8 desc[IB_DEVICE_NODE_DESC_MAX];
464 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
466 struct mlx5_reg_node_desc in;
468 if (mlx5_use_mad_ifc(dev))
469 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
471 memset(&in, 0, sizeof(in));
473 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
474 sizeof(struct mlx5_reg_node_desc),
475 MLX5_REG_NODE_DESC, 0, 0);
478 static int mlx5_ib_query_device(struct ib_device *ibdev,
479 struct ib_device_attr *props,
480 struct ib_udata *uhw)
482 struct mlx5_ib_dev *dev = to_mdev(ibdev);
483 struct mlx5_core_dev *mdev = dev->mdev;
487 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
488 struct mlx5_ib_query_device_resp resp = {};
492 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
493 if (uhw->outlen && uhw->outlen < resp_len)
496 resp.response_length = resp_len;
498 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
501 memset(props, 0, sizeof(*props));
502 err = mlx5_query_system_image_guid(ibdev,
503 &props->sys_image_guid);
507 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
511 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
515 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
516 (fw_rev_min(dev->mdev) << 16) |
517 fw_rev_sub(dev->mdev);
518 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
519 IB_DEVICE_PORT_ACTIVE_EVENT |
520 IB_DEVICE_SYS_IMAGE_GUID |
521 IB_DEVICE_RC_RNR_NAK_GEN;
523 if (MLX5_CAP_GEN(mdev, pkv))
524 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
525 if (MLX5_CAP_GEN(mdev, qkv))
526 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
527 if (MLX5_CAP_GEN(mdev, apm))
528 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
529 if (MLX5_CAP_GEN(mdev, xrc))
530 props->device_cap_flags |= IB_DEVICE_XRC;
531 if (MLX5_CAP_GEN(mdev, imaicl)) {
532 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
533 IB_DEVICE_MEM_WINDOW_TYPE_2B;
534 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
535 /* We support 'Gappy' memory registration too */
536 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
538 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
539 if (MLX5_CAP_GEN(mdev, sho)) {
540 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
541 /* At this stage no support for signature handover */
542 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
543 IB_PROT_T10DIF_TYPE_2 |
544 IB_PROT_T10DIF_TYPE_3;
545 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
546 IB_GUARD_T10DIF_CSUM;
548 if (MLX5_CAP_GEN(mdev, block_lb_mc))
549 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
551 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
552 if (MLX5_CAP_ETH(mdev, csum_cap))
553 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
555 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
556 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
558 resp.tso_caps.max_tso = 1 << max_tso;
559 resp.tso_caps.supported_qpts |=
560 1 << IB_QPT_RAW_PACKET;
561 resp.response_length += sizeof(resp.tso_caps);
565 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
566 resp.rss_caps.rx_hash_function =
567 MLX5_RX_HASH_FUNC_TOEPLITZ;
568 resp.rss_caps.rx_hash_fields_mask =
569 MLX5_RX_HASH_SRC_IPV4 |
570 MLX5_RX_HASH_DST_IPV4 |
571 MLX5_RX_HASH_SRC_IPV6 |
572 MLX5_RX_HASH_DST_IPV6 |
573 MLX5_RX_HASH_SRC_PORT_TCP |
574 MLX5_RX_HASH_DST_PORT_TCP |
575 MLX5_RX_HASH_SRC_PORT_UDP |
576 MLX5_RX_HASH_DST_PORT_UDP;
577 resp.response_length += sizeof(resp.rss_caps);
580 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
581 resp.response_length += sizeof(resp.tso_caps);
582 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
583 resp.response_length += sizeof(resp.rss_caps);
586 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
587 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
588 props->device_cap_flags |= IB_DEVICE_UD_TSO;
591 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
592 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
593 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
595 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
596 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
598 props->vendor_part_id = mdev->pdev->device;
599 props->hw_ver = mdev->pdev->revision;
601 props->max_mr_size = ~0ull;
602 props->page_size_cap = ~(min_page_size - 1);
603 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
604 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
605 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
606 sizeof(struct mlx5_wqe_data_seg);
607 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
608 sizeof(struct mlx5_wqe_ctrl_seg)) /
609 sizeof(struct mlx5_wqe_data_seg);
610 props->max_sge = min(max_rq_sg, max_sq_sg);
611 props->max_sge_rd = MLX5_MAX_SGE_RD;
612 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
613 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
614 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
615 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
616 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
617 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
618 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
619 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
620 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
621 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
622 props->max_srq_sge = max_rq_sg - 1;
623 props->max_fast_reg_page_list_len =
624 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
625 get_atomic_caps(dev, props);
626 props->masked_atomic_cap = IB_ATOMIC_NONE;
627 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
628 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
629 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
630 props->max_mcast_grp;
631 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
632 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
633 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
635 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
636 if (MLX5_CAP_GEN(mdev, pg))
637 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
638 props->odp_caps = dev->odp_caps;
641 if (MLX5_CAP_GEN(mdev, cd))
642 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
644 if (!mlx5_core_is_pf(mdev))
645 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
647 if (mlx5_ib_port_link_layer(ibdev, 1) ==
648 IB_LINK_LAYER_ETHERNET) {
649 props->rss_caps.max_rwq_indirection_tables =
650 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
651 props->rss_caps.max_rwq_indirection_table_size =
652 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
653 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
654 props->max_wq_type_rq =
655 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
659 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
669 MLX5_IB_WIDTH_1X = 1 << 0,
670 MLX5_IB_WIDTH_2X = 1 << 1,
671 MLX5_IB_WIDTH_4X = 1 << 2,
672 MLX5_IB_WIDTH_8X = 1 << 3,
673 MLX5_IB_WIDTH_12X = 1 << 4
676 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
679 struct mlx5_ib_dev *dev = to_mdev(ibdev);
682 if (active_width & MLX5_IB_WIDTH_1X) {
683 *ib_width = IB_WIDTH_1X;
684 } else if (active_width & MLX5_IB_WIDTH_2X) {
685 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
688 } else if (active_width & MLX5_IB_WIDTH_4X) {
689 *ib_width = IB_WIDTH_4X;
690 } else if (active_width & MLX5_IB_WIDTH_8X) {
691 *ib_width = IB_WIDTH_8X;
692 } else if (active_width & MLX5_IB_WIDTH_12X) {
693 *ib_width = IB_WIDTH_12X;
695 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
708 __IB_MAX_VL_0_14 = 5,
711 enum mlx5_vl_hw_cap {
723 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
728 *max_vl_num = __IB_MAX_VL_0;
731 *max_vl_num = __IB_MAX_VL_0_1;
734 *max_vl_num = __IB_MAX_VL_0_3;
737 *max_vl_num = __IB_MAX_VL_0_7;
739 case MLX5_VL_HW_0_14:
740 *max_vl_num = __IB_MAX_VL_0_14;
750 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
751 struct ib_port_attr *props)
753 struct mlx5_ib_dev *dev = to_mdev(ibdev);
754 struct mlx5_core_dev *mdev = dev->mdev;
756 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
757 struct mlx5_ptys_reg *ptys;
758 struct mlx5_pmtu_reg *pmtu;
759 struct mlx5_pvlc_reg pvlc;
763 rep = mlx5_vzalloc(replen);
764 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
765 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
766 if (!rep || !ptys || !pmtu) {
771 memset(props, 0, sizeof(*props));
773 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
777 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
779 props->lid = MLX5_GET(hca_vport_context, ctx, lid);
780 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc);
781 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid);
782 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl);
783 props->state = MLX5_GET(hca_vport_context, ctx, vport_state);
784 props->phys_state = MLX5_GET(hca_vport_context, ctx,
785 port_physical_state);
786 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1);
787 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
788 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
789 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
790 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx,
791 pkey_violation_counter);
792 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx,
793 qkey_violation_counter);
794 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx,
796 props->init_type_reply = MLX5_GET(hca_vport_context, ctx,
798 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required);
800 ptys->proto_mask |= MLX5_PTYS_IB;
801 ptys->local_port = port;
802 err = mlx5_core_access_ptys(mdev, ptys, 0);
806 err = translate_active_width(ibdev, ptys->ib_link_width_oper,
807 &props->active_width);
811 props->active_speed = (u8)ptys->ib_proto_oper;
813 pmtu->local_port = port;
814 err = mlx5_core_access_pmtu(mdev, pmtu, 0);
818 props->max_mtu = pmtu->max_mtu;
819 props->active_mtu = pmtu->oper_mtu;
821 memset(&pvlc, 0, sizeof(pvlc));
822 pvlc.local_port = port;
823 err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
827 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
836 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
837 struct ib_port_attr *props)
839 switch (mlx5_get_vport_access_method(ibdev)) {
840 case MLX5_VPORT_ACCESS_METHOD_MAD:
841 return mlx5_query_mad_ifc_port(ibdev, port, props);
843 case MLX5_VPORT_ACCESS_METHOD_HCA:
844 return mlx5_query_hca_port(ibdev, port, props);
846 case MLX5_VPORT_ACCESS_METHOD_NIC:
847 return mlx5_query_port_roce(ibdev, port, props);
854 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
857 struct mlx5_ib_dev *dev = to_mdev(ibdev);
858 struct mlx5_core_dev *mdev = dev->mdev;
860 switch (mlx5_get_vport_access_method(ibdev)) {
861 case MLX5_VPORT_ACCESS_METHOD_MAD:
862 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
864 case MLX5_VPORT_ACCESS_METHOD_HCA:
865 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
873 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
876 struct mlx5_ib_dev *dev = to_mdev(ibdev);
877 struct mlx5_core_dev *mdev = dev->mdev;
879 switch (mlx5_get_vport_access_method(ibdev)) {
880 case MLX5_VPORT_ACCESS_METHOD_MAD:
881 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
883 case MLX5_VPORT_ACCESS_METHOD_HCA:
884 case MLX5_VPORT_ACCESS_METHOD_NIC:
885 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
892 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
893 struct ib_device_modify *props)
895 struct mlx5_ib_dev *dev = to_mdev(ibdev);
896 struct mlx5_reg_node_desc in;
897 struct mlx5_reg_node_desc out;
900 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
903 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
907 * If possible, pass node desc to FW, so it can generate
908 * a 144 trap. If cmd fails, just ignore.
910 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
911 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
912 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
916 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
921 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
922 struct ib_port_modify *props)
924 struct mlx5_ib_dev *dev = to_mdev(ibdev);
925 struct ib_port_attr attr;
929 mutex_lock(&dev->cap_mask_mutex);
931 err = mlx5_ib_query_port(ibdev, port, &attr);
935 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
936 ~props->clr_port_cap_mask;
938 err = mlx5_set_port_caps(dev->mdev, port, tmp);
941 mutex_unlock(&dev->cap_mask_mutex);
945 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
946 struct ib_udata *udata)
948 struct mlx5_ib_dev *dev = to_mdev(ibdev);
949 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
950 struct mlx5_ib_alloc_ucontext_resp resp = {};
951 struct mlx5_ib_ucontext *context;
952 struct mlx5_uuar_info *uuari;
953 struct mlx5_uar *uars;
961 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
965 return ERR_PTR(-EAGAIN);
967 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
968 return ERR_PTR(-EINVAL);
970 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
971 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
973 else if (reqlen >= min_req_v2)
976 return ERR_PTR(-EINVAL);
978 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
983 return ERR_PTR(-EINVAL);
985 if (req.total_num_uuars > MLX5_MAX_UUARS)
986 return ERR_PTR(-ENOMEM);
988 if (req.total_num_uuars == 0)
989 return ERR_PTR(-EINVAL);
991 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
992 return ERR_PTR(-EOPNOTSUPP);
994 if (reqlen > sizeof(req) &&
995 !ib_is_udata_cleared(udata, sizeof(req),
996 reqlen - sizeof(req)))
997 return ERR_PTR(-EOPNOTSUPP);
999 req.total_num_uuars = ALIGN(req.total_num_uuars,
1000 MLX5_NON_FP_BF_REGS_PER_PAGE);
1001 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1002 return ERR_PTR(-EINVAL);
1004 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1005 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1006 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1007 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1008 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1009 resp.cache_line_size = cache_line_size();
1010 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1011 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1012 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1013 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1014 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1015 resp.cqe_version = min_t(__u8,
1016 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1017 req.max_cqe_version);
1018 resp.response_length = min(offsetof(typeof(resp), response_length) +
1019 sizeof(resp.response_length), udata->outlen);
1021 context = kzalloc(sizeof(*context), GFP_KERNEL);
1023 return ERR_PTR(-ENOMEM);
1025 uuari = &context->uuari;
1026 mutex_init(&uuari->lock);
1027 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1033 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1034 sizeof(*uuari->bitmap),
1036 if (!uuari->bitmap) {
1041 * clear all fast path uuars
1043 for (i = 0; i < gross_uuars; i++) {
1045 if (uuarn == 2 || uuarn == 3)
1046 set_bit(i, uuari->bitmap);
1049 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1050 if (!uuari->count) {
1055 for (i = 0; i < num_uars; i++) {
1056 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1061 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1062 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1065 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1066 err = mlx5_alloc_transport_domain(dev->mdev,
1072 INIT_LIST_HEAD(&context->vma_private_list);
1073 INIT_LIST_HEAD(&context->db_page_list);
1074 mutex_init(&context->db_page_mutex);
1076 resp.tot_uuars = req.total_num_uuars;
1077 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1079 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1080 resp.response_length += sizeof(resp.cqe_version);
1082 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1083 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1084 resp.response_length += sizeof(resp.cmds_supp_uhw);
1088 * We don't want to expose information from the PCI bar that is located
1089 * after 4096 bytes, so if the arch only supports larger pages, let's
1090 * pretend we don't support reading the HCA's core clock. This is also
1091 * forced by mmap function.
1093 if (PAGE_SIZE <= 4096 &&
1094 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1096 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1097 resp.hca_core_clock_offset =
1098 offsetof(struct mlx5_init_seg, internal_timer_h) %
1100 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1101 sizeof(resp.reserved2);
1104 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1109 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1111 uuari->num_uars = num_uars;
1112 context->cqe_version = resp.cqe_version;
1114 return &context->ibucontext;
1117 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1118 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1121 for (i--; i >= 0; i--)
1122 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1124 kfree(uuari->count);
1127 kfree(uuari->bitmap);
1134 return ERR_PTR(err);
1137 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1139 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1140 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1141 struct mlx5_uuar_info *uuari = &context->uuari;
1144 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1145 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1147 for (i = 0; i < uuari->num_uars; i++) {
1148 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1149 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1152 kfree(uuari->count);
1153 kfree(uuari->bitmap);
1160 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1162 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1165 static int get_command(unsigned long offset)
1167 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1170 static int get_arg(unsigned long offset)
1172 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1175 static int get_index(unsigned long offset)
1177 return get_arg(offset);
1180 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1182 /* vma_open is called when a new VMA is created on top of our VMA. This
1183 * is done through either mremap flow or split_vma (usually due to
1184 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1185 * as this VMA is strongly hardware related. Therefore we set the
1186 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1187 * calling us again and trying to do incorrect actions. We assume that
1188 * the original VMA size is exactly a single page, and therefore all
1189 * "splitting" operation will not happen to it.
1191 area->vm_ops = NULL;
1194 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1196 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1198 /* It's guaranteed that all VMAs opened on a FD are closed before the
1199 * file itself is closed, therefore no sync is needed with the regular
1200 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1201 * However need a sync with accessing the vma as part of
1202 * mlx5_ib_disassociate_ucontext.
1203 * The close operation is usually called under mm->mmap_sem except when
1204 * process is exiting.
1205 * The exiting case is handled explicitly as part of
1206 * mlx5_ib_disassociate_ucontext.
1208 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1210 /* setting the vma context pointer to null in the mlx5_ib driver's
1211 * private data, to protect a race condition in
1212 * mlx5_ib_disassociate_ucontext().
1214 mlx5_ib_vma_priv_data->vma = NULL;
1215 list_del(&mlx5_ib_vma_priv_data->list);
1216 kfree(mlx5_ib_vma_priv_data);
1219 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1220 .open = mlx5_ib_vma_open,
1221 .close = mlx5_ib_vma_close
1224 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1225 struct mlx5_ib_ucontext *ctx)
1227 struct mlx5_ib_vma_private_data *vma_prv;
1228 struct list_head *vma_head = &ctx->vma_private_list;
1230 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1235 vma->vm_private_data = vma_prv;
1236 vma->vm_ops = &mlx5_ib_vm_ops;
1238 list_add(&vma_prv->list, vma_head);
1243 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1246 struct vm_area_struct *vma;
1247 struct mlx5_ib_vma_private_data *vma_private, *n;
1248 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1249 struct task_struct *owning_process = NULL;
1250 struct mm_struct *owning_mm = NULL;
1252 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1253 if (!owning_process)
1256 owning_mm = get_task_mm(owning_process);
1258 pr_info("no mm, disassociate ucontext is pending task termination\n");
1260 put_task_struct(owning_process);
1261 usleep_range(1000, 2000);
1262 owning_process = get_pid_task(ibcontext->tgid,
1264 if (!owning_process /* ||
1265 owning_process->state == TASK_DEAD */) {
1266 pr_info("disassociate ucontext done, task was terminated\n");
1267 /* in case task was dead need to release the
1271 put_task_struct(owning_process);
1277 /* need to protect from a race on closing the vma as part of
1278 * mlx5_ib_vma_close.
1280 down_read(&owning_mm->mmap_sem);
1281 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1283 vma = vma_private->vma;
1284 ret = zap_vma_ptes(vma, vma->vm_start,
1286 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1287 /* context going to be destroyed, should
1288 * not access ops any more.
1291 list_del(&vma_private->list);
1294 up_read(&owning_mm->mmap_sem);
1296 put_task_struct(owning_process);
1299 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1302 case MLX5_IB_MMAP_WC_PAGE:
1304 case MLX5_IB_MMAP_REGULAR_PAGE:
1305 return "best effort WC";
1306 case MLX5_IB_MMAP_NC_PAGE:
1313 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1314 struct vm_area_struct *vma,
1315 struct mlx5_ib_ucontext *context)
1317 struct mlx5_uuar_info *uuari = &context->uuari;
1320 phys_addr_t pfn, pa;
1324 case MLX5_IB_MMAP_WC_PAGE:
1325 /* Some architectures don't support WC memory */
1326 #if defined(CONFIG_X86)
1329 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1333 case MLX5_IB_MMAP_REGULAR_PAGE:
1334 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1335 prot = pgprot_writecombine(vma->vm_page_prot);
1337 case MLX5_IB_MMAP_NC_PAGE:
1338 prot = pgprot_noncached(vma->vm_page_prot);
1344 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1347 idx = get_index(vma->vm_pgoff);
1348 if (idx >= uuari->num_uars)
1351 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1352 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1354 vma->vm_page_prot = prot;
1355 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1356 PAGE_SIZE, vma->vm_page_prot);
1358 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n",
1359 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd));
1363 pa = pfn << PAGE_SHIFT;
1364 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd),
1365 (unsigned long long)vma->vm_start, &pa);
1367 return mlx5_ib_set_vma_data(vma, context);
1370 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1372 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1373 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1374 unsigned long command;
1377 command = get_command(vma->vm_pgoff);
1379 case MLX5_IB_MMAP_WC_PAGE:
1380 case MLX5_IB_MMAP_NC_PAGE:
1381 case MLX5_IB_MMAP_REGULAR_PAGE:
1382 return uar_mmap(dev, command, vma, context);
1384 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1387 case MLX5_IB_MMAP_CORE_CLOCK:
1388 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1391 if (vma->vm_flags & VM_WRITE)
1394 /* Don't expose to user-space information it shouldn't have */
1395 if (PAGE_SIZE > 4096)
1398 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1399 pfn = (dev->mdev->iseg_base +
1400 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1402 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1403 PAGE_SIZE, vma->vm_page_prot))
1406 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n",
1407 (unsigned long long)vma->vm_start,
1408 (unsigned long long)pfn << PAGE_SHIFT);
1418 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1419 struct ib_ucontext *context,
1420 struct ib_udata *udata)
1422 struct mlx5_ib_alloc_pd_resp resp;
1423 struct mlx5_ib_pd *pd;
1426 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1428 return ERR_PTR(-ENOMEM);
1430 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1433 return ERR_PTR(err);
1438 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1439 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1441 return ERR_PTR(-EFAULT);
1448 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1450 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1451 struct mlx5_ib_pd *mpd = to_mpd(pd);
1453 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1460 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1461 MATCH_CRITERIA_ENABLE_MISC_BIT,
1462 MATCH_CRITERIA_ENABLE_INNER_BIT
1465 #define HEADER_IS_ZERO(match_criteria, headers) \
1466 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1467 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1469 static u8 get_match_criteria_enable(u32 *match_criteria)
1471 u8 match_criteria_enable;
1473 match_criteria_enable =
1474 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1475 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1476 match_criteria_enable |=
1477 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1478 MATCH_CRITERIA_ENABLE_MISC_BIT;
1479 match_criteria_enable |=
1480 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1481 MATCH_CRITERIA_ENABLE_INNER_BIT;
1483 return match_criteria_enable;
1486 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1488 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1489 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1492 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1494 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1495 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1496 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1497 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1500 #define LAST_ETH_FIELD vlan_tag
1501 #define LAST_IB_FIELD sl
1502 #define LAST_IPV4_FIELD tos
1503 #define LAST_IPV6_FIELD traffic_class
1504 #define LAST_TCP_UDP_FIELD src_port
1506 /* Field is the last supported field */
1507 #define FIELDS_NOT_SUPPORTED(filter, field)\
1508 memchr_inv((void *)&filter.field +\
1509 sizeof(filter.field), 0,\
1511 offsetof(typeof(filter), field) -\
1512 sizeof(filter.field))
1514 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1515 const union ib_flow_spec *ib_spec)
1517 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1519 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1521 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1523 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1526 switch (ib_spec->type) {
1527 case IB_FLOW_SPEC_ETH:
1528 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1531 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1533 ib_spec->eth.mask.dst_mac);
1534 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1536 ib_spec->eth.val.dst_mac);
1538 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1540 ib_spec->eth.mask.src_mac);
1541 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1543 ib_spec->eth.val.src_mac);
1545 if (ib_spec->eth.mask.vlan_tag) {
1546 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1548 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1551 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1552 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1553 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1554 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1556 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1558 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1559 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1561 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1563 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1565 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1566 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1568 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1570 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1571 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1572 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1573 ethertype, ntohs(ib_spec->eth.val.ether_type));
1575 case IB_FLOW_SPEC_IPV4:
1576 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1581 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1582 ethertype, ETH_P_IP);
1584 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1585 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1586 &ib_spec->ipv4.mask.src_ip,
1587 sizeof(ib_spec->ipv4.mask.src_ip));
1588 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1589 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1590 &ib_spec->ipv4.val.src_ip,
1591 sizeof(ib_spec->ipv4.val.src_ip));
1592 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1593 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1594 &ib_spec->ipv4.mask.dst_ip,
1595 sizeof(ib_spec->ipv4.mask.dst_ip));
1596 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1597 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1598 &ib_spec->ipv4.val.dst_ip,
1599 sizeof(ib_spec->ipv4.val.dst_ip));
1601 set_tos(outer_headers_c, outer_headers_v,
1602 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1604 set_proto(outer_headers_c, outer_headers_v,
1605 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1607 case IB_FLOW_SPEC_IPV6:
1608 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1611 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1613 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1614 ethertype, IPPROTO_IPV6);
1616 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1617 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1618 &ib_spec->ipv6.mask.src_ip,
1619 sizeof(ib_spec->ipv6.mask.src_ip));
1620 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1621 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1622 &ib_spec->ipv6.val.src_ip,
1623 sizeof(ib_spec->ipv6.val.src_ip));
1624 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1625 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1626 &ib_spec->ipv6.mask.dst_ip,
1627 sizeof(ib_spec->ipv6.mask.dst_ip));
1628 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1629 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1630 &ib_spec->ipv6.val.dst_ip,
1631 sizeof(ib_spec->ipv6.val.dst_ip));
1633 set_tos(outer_headers_c, outer_headers_v,
1634 ib_spec->ipv6.mask.traffic_class,
1635 ib_spec->ipv6.val.traffic_class);
1637 set_proto(outer_headers_c, outer_headers_v,
1638 ib_spec->ipv6.mask.next_hdr,
1639 ib_spec->ipv6.val.next_hdr);
1641 MLX5_SET(fte_match_set_misc, misc_params_c,
1642 outer_ipv6_flow_label,
1643 ntohl(ib_spec->ipv6.mask.flow_label));
1644 MLX5_SET(fte_match_set_misc, misc_params_v,
1645 outer_ipv6_flow_label,
1646 ntohl(ib_spec->ipv6.val.flow_label));
1648 case IB_FLOW_SPEC_TCP:
1649 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1650 LAST_TCP_UDP_FIELD))
1653 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1655 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1658 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1659 ntohs(ib_spec->tcp_udp.mask.src_port));
1660 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1661 ntohs(ib_spec->tcp_udp.val.src_port));
1663 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1664 ntohs(ib_spec->tcp_udp.mask.dst_port));
1665 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1666 ntohs(ib_spec->tcp_udp.val.dst_port));
1668 case IB_FLOW_SPEC_UDP:
1669 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1670 LAST_TCP_UDP_FIELD))
1673 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1675 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1678 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1679 ntohs(ib_spec->tcp_udp.mask.src_port));
1680 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1681 ntohs(ib_spec->tcp_udp.val.src_port));
1683 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1684 ntohs(ib_spec->tcp_udp.mask.dst_port));
1685 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1686 ntohs(ib_spec->tcp_udp.val.dst_port));
1695 /* If a flow could catch both multicast and unicast packets,
1696 * it won't fall into the multicast flow steering table and this rule
1697 * could steal other multicast packets.
1699 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1701 struct ib_flow_spec_eth *eth_spec;
1703 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1704 ib_attr->size < sizeof(struct ib_flow_attr) +
1705 sizeof(struct ib_flow_spec_eth) ||
1706 ib_attr->num_of_specs < 1)
1709 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1710 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1711 eth_spec->size != sizeof(*eth_spec))
1714 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1715 is_multicast_ether_addr(eth_spec->val.dst_mac);
1718 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1720 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1721 bool has_ipv4_spec = false;
1722 bool eth_type_ipv4 = true;
1723 unsigned int spec_index;
1725 /* Validate that ethertype is correct */
1726 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1727 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1728 ib_spec->eth.mask.ether_type) {
1729 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1730 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1731 eth_type_ipv4 = false;
1732 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1733 has_ipv4_spec = true;
1735 ib_spec = (void *)ib_spec + ib_spec->size;
1737 return !has_ipv4_spec || eth_type_ipv4;
1740 static void put_flow_table(struct mlx5_ib_dev *dev,
1741 struct mlx5_ib_flow_prio *prio, bool ft_added)
1743 prio->refcount -= !!ft_added;
1744 if (!prio->refcount) {
1745 mlx5_destroy_flow_table(prio->flow_table);
1746 prio->flow_table = NULL;
1750 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1752 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1753 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1754 struct mlx5_ib_flow_handler,
1756 struct mlx5_ib_flow_handler *iter, *tmp;
1758 mutex_lock(&dev->flow_db.lock);
1760 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1761 mlx5_del_flow_rule(iter->rule);
1762 put_flow_table(dev, iter->prio, true);
1763 list_del(&iter->list);
1767 mlx5_del_flow_rule(handler->rule);
1768 put_flow_table(dev, handler->prio, true);
1769 mutex_unlock(&dev->flow_db.lock);
1776 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1784 enum flow_table_type {
1789 #define MLX5_FS_MAX_TYPES 10
1790 #define MLX5_FS_MAX_ENTRIES 32000UL
1791 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1792 struct ib_flow_attr *flow_attr,
1793 enum flow_table_type ft_type)
1795 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1796 struct mlx5_flow_namespace *ns = NULL;
1797 struct mlx5_ib_flow_prio *prio;
1798 struct mlx5_flow_table *ft;
1804 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1805 if (flow_is_multicast_only(flow_attr) &&
1807 priority = MLX5_IB_FLOW_MCAST_PRIO;
1809 priority = ib_prio_to_core_prio(flow_attr->priority,
1811 ns = mlx5_get_flow_namespace(dev->mdev,
1812 MLX5_FLOW_NAMESPACE_BYPASS);
1813 num_entries = MLX5_FS_MAX_ENTRIES;
1814 num_groups = MLX5_FS_MAX_TYPES;
1815 prio = &dev->flow_db.prios[priority];
1816 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1817 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1818 ns = mlx5_get_flow_namespace(dev->mdev,
1819 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1820 build_leftovers_ft_param("bypass", &priority,
1823 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1824 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1825 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1826 allow_sniffer_and_nic_rx_shared_tir))
1827 return ERR_PTR(-ENOTSUPP);
1829 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1830 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1831 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1833 prio = &dev->flow_db.sniffer[ft_type];
1840 return ERR_PTR(-ENOTSUPP);
1842 ft = prio->flow_table;
1844 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass",
1850 prio->flow_table = ft;
1856 return err ? ERR_PTR(err) : prio;
1859 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1860 struct mlx5_ib_flow_prio *ft_prio,
1861 const struct ib_flow_attr *flow_attr,
1862 struct mlx5_flow_destination *dst)
1864 struct mlx5_flow_table *ft = ft_prio->flow_table;
1865 struct mlx5_ib_flow_handler *handler;
1866 struct mlx5_flow_spec *spec;
1867 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1868 unsigned int spec_index;
1872 if (!is_valid_attr(flow_attr))
1873 return ERR_PTR(-EINVAL);
1875 spec = mlx5_vzalloc(sizeof(*spec));
1876 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1877 if (!handler || !spec) {
1882 INIT_LIST_HEAD(&handler->list);
1884 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1885 err = parse_flow_attr(spec->match_criteria,
1886 spec->match_value, ib_flow);
1890 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1893 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1894 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1895 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1896 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable,
1897 spec->match_criteria,
1900 MLX5_FS_DEFAULT_FLOW_TAG,
1903 if (IS_ERR(handler->rule)) {
1904 err = PTR_ERR(handler->rule);
1908 ft_prio->refcount++;
1909 handler->prio = ft_prio;
1911 ft_prio->flow_table = ft;
1916 return err ? ERR_PTR(err) : handler;
1919 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1920 struct mlx5_ib_flow_prio *ft_prio,
1921 struct ib_flow_attr *flow_attr,
1922 struct mlx5_flow_destination *dst)
1924 struct mlx5_ib_flow_handler *handler_dst = NULL;
1925 struct mlx5_ib_flow_handler *handler = NULL;
1927 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1928 if (!IS_ERR(handler)) {
1929 handler_dst = create_flow_rule(dev, ft_prio,
1931 if (IS_ERR(handler_dst)) {
1932 mlx5_del_flow_rule(handler->rule);
1933 ft_prio->refcount--;
1935 handler = handler_dst;
1937 list_add(&handler_dst->list, &handler->list);
1948 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1949 struct mlx5_ib_flow_prio *ft_prio,
1950 struct ib_flow_attr *flow_attr,
1951 struct mlx5_flow_destination *dst)
1953 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1954 struct mlx5_ib_flow_handler *handler = NULL;
1957 struct ib_flow_attr flow_attr;
1958 struct ib_flow_spec_eth eth_flow;
1959 } leftovers_specs[] = {
1963 .size = sizeof(leftovers_specs[0])
1966 .type = IB_FLOW_SPEC_ETH,
1967 .size = sizeof(struct ib_flow_spec_eth),
1968 .mask = {.dst_mac = {0x1} },
1969 .val = {.dst_mac = {0x1} }
1975 .size = sizeof(leftovers_specs[0])
1978 .type = IB_FLOW_SPEC_ETH,
1979 .size = sizeof(struct ib_flow_spec_eth),
1980 .mask = {.dst_mac = {0x1} },
1981 .val = {.dst_mac = {} }
1986 handler = create_flow_rule(dev, ft_prio,
1987 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1989 if (!IS_ERR(handler) &&
1990 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1991 handler_ucast = create_flow_rule(dev, ft_prio,
1992 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1994 if (IS_ERR(handler_ucast)) {
1995 mlx5_del_flow_rule(handler->rule);
1996 ft_prio->refcount--;
1998 handler = handler_ucast;
2000 list_add(&handler_ucast->list, &handler->list);
2007 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2008 struct mlx5_ib_flow_prio *ft_rx,
2009 struct mlx5_ib_flow_prio *ft_tx,
2010 struct mlx5_flow_destination *dst)
2012 struct mlx5_ib_flow_handler *handler_rx;
2013 struct mlx5_ib_flow_handler *handler_tx;
2015 static const struct ib_flow_attr flow_attr = {
2017 .size = sizeof(flow_attr)
2020 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2021 if (IS_ERR(handler_rx)) {
2022 err = PTR_ERR(handler_rx);
2026 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2027 if (IS_ERR(handler_tx)) {
2028 err = PTR_ERR(handler_tx);
2032 list_add(&handler_tx->list, &handler_rx->list);
2037 mlx5_del_flow_rule(handler_rx->rule);
2041 return ERR_PTR(err);
2044 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2045 struct ib_flow_attr *flow_attr,
2048 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2049 struct mlx5_ib_qp *mqp = to_mqp(qp);
2050 struct mlx5_ib_flow_handler *handler = NULL;
2051 struct mlx5_flow_destination *dst = NULL;
2052 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2053 struct mlx5_ib_flow_prio *ft_prio;
2056 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2057 return ERR_PTR(-ENOSPC);
2059 if (domain != IB_FLOW_DOMAIN_USER ||
2060 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2061 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2062 return ERR_PTR(-EINVAL);
2064 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2066 return ERR_PTR(-ENOMEM);
2068 mutex_lock(&dev->flow_db.lock);
2070 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2071 if (IS_ERR(ft_prio)) {
2072 err = PTR_ERR(ft_prio);
2075 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2076 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2077 if (IS_ERR(ft_prio_tx)) {
2078 err = PTR_ERR(ft_prio_tx);
2084 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2085 if (mqp->flags & MLX5_IB_QP_RSS)
2086 dst->tir_num = mqp->rss_qp.tirn;
2088 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2090 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2091 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2092 handler = create_dont_trap_rule(dev, ft_prio,
2095 handler = create_flow_rule(dev, ft_prio, flow_attr,
2098 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2099 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2100 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2102 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2103 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2109 if (IS_ERR(handler)) {
2110 err = PTR_ERR(handler);
2115 mutex_unlock(&dev->flow_db.lock);
2118 return &handler->ibflow;
2121 put_flow_table(dev, ft_prio, false);
2123 put_flow_table(dev, ft_prio_tx, false);
2125 mutex_unlock(&dev->flow_db.lock);
2128 return ERR_PTR(err);
2131 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2133 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2136 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2138 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2139 ibqp->qp_num, gid->raw);
2144 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2146 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2149 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2151 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2152 ibqp->qp_num, gid->raw);
2157 static int init_node_data(struct mlx5_ib_dev *dev)
2161 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2165 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2168 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2171 struct mlx5_ib_dev *dev =
2172 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2174 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2177 static ssize_t show_reg_pages(struct device *device,
2178 struct device_attribute *attr, char *buf)
2180 struct mlx5_ib_dev *dev =
2181 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2183 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2186 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2189 struct mlx5_ib_dev *dev =
2190 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2191 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2194 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2197 struct mlx5_ib_dev *dev =
2198 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2199 return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2202 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2205 struct mlx5_ib_dev *dev =
2206 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2207 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2208 dev->mdev->board_id);
2211 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2212 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2213 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2214 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2215 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2217 static struct device_attribute *mlx5_class_attributes[] = {
2222 &dev_attr_reg_pages,
2225 static void pkey_change_handler(struct work_struct *work)
2227 struct mlx5_ib_port_resources *ports =
2228 container_of(work, struct mlx5_ib_port_resources,
2231 mutex_lock(&ports->devr->mutex);
2232 mlx5_ib_gsi_pkey_change(ports->gsi);
2233 mutex_unlock(&ports->devr->mutex);
2236 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2238 struct mlx5_ib_qp *mqp;
2239 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2240 struct mlx5_core_cq *mcq;
2241 struct list_head cq_armed_list;
2242 unsigned long flags_qp;
2243 unsigned long flags_cq;
2244 unsigned long flags;
2246 INIT_LIST_HEAD(&cq_armed_list);
2248 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2249 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2250 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2251 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2252 if (mqp->sq.tail != mqp->sq.head) {
2253 send_mcq = to_mcq(mqp->ibqp.send_cq);
2254 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2255 if (send_mcq->mcq.comp &&
2256 mqp->ibqp.send_cq->comp_handler) {
2257 if (!send_mcq->mcq.reset_notify_added) {
2258 send_mcq->mcq.reset_notify_added = 1;
2259 list_add_tail(&send_mcq->mcq.reset_notify,
2263 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2265 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2266 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2267 /* no handling is needed for SRQ */
2268 if (!mqp->ibqp.srq) {
2269 if (mqp->rq.tail != mqp->rq.head) {
2270 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2271 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2272 if (recv_mcq->mcq.comp &&
2273 mqp->ibqp.recv_cq->comp_handler) {
2274 if (!recv_mcq->mcq.reset_notify_added) {
2275 recv_mcq->mcq.reset_notify_added = 1;
2276 list_add_tail(&recv_mcq->mcq.reset_notify,
2280 spin_unlock_irqrestore(&recv_mcq->lock,
2284 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2286 /*At that point all inflight post send were put to be executed as of we
2287 * lock/unlock above locks Now need to arm all involved CQs.
2289 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2292 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2295 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2296 enum mlx5_dev_event event, unsigned long param)
2298 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2299 struct ib_event ibev;
2304 case MLX5_DEV_EVENT_SYS_ERROR:
2305 ibev.event = IB_EVENT_DEVICE_FATAL;
2306 mlx5_ib_handle_internal_error(ibdev);
2310 case MLX5_DEV_EVENT_PORT_UP:
2311 case MLX5_DEV_EVENT_PORT_DOWN:
2312 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2315 /* In RoCE, port up/down events are handled in
2316 * mlx5_netdev_event().
2318 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2319 IB_LINK_LAYER_ETHERNET)
2322 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2323 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2326 case MLX5_DEV_EVENT_LID_CHANGE:
2327 ibev.event = IB_EVENT_LID_CHANGE;
2331 case MLX5_DEV_EVENT_PKEY_CHANGE:
2332 ibev.event = IB_EVENT_PKEY_CHANGE;
2335 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2338 case MLX5_DEV_EVENT_GUID_CHANGE:
2339 ibev.event = IB_EVENT_GID_CHANGE;
2343 case MLX5_DEV_EVENT_CLIENT_REREG:
2344 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2352 ibev.device = &ibdev->ib_dev;
2353 ibev.element.port_num = port;
2355 if (port < 1 || port > ibdev->num_ports) {
2356 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2360 if (ibdev->ib_active)
2361 ib_dispatch_event(&ibev);
2364 ibdev->ib_active = false;
2367 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2371 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2372 mlx5_query_ext_port_caps(dev, port);
2375 static int get_port_caps(struct mlx5_ib_dev *dev)
2377 struct ib_device_attr *dprops = NULL;
2378 struct ib_port_attr *pprops = NULL;
2381 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2383 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2387 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2391 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2393 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2397 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2398 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2400 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2404 dev->mdev->port_caps[port - 1].pkey_table_len =
2406 dev->mdev->port_caps[port - 1].gid_table_len =
2407 pprops->gid_tbl_len;
2408 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2409 dprops->max_pkeys, pprops->gid_tbl_len);
2419 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2423 err = mlx5_mr_cache_cleanup(dev);
2425 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2427 mlx5_ib_destroy_qp(dev->umrc.qp);
2428 ib_free_cq(dev->umrc.cq);
2429 ib_dealloc_pd(dev->umrc.pd);
2436 static int create_umr_res(struct mlx5_ib_dev *dev)
2438 struct ib_qp_init_attr *init_attr = NULL;
2439 struct ib_qp_attr *attr = NULL;
2445 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2446 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2447 if (!attr || !init_attr) {
2452 pd = ib_alloc_pd(&dev->ib_dev, 0);
2454 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2459 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2461 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2466 init_attr->send_cq = cq;
2467 init_attr->recv_cq = cq;
2468 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2469 init_attr->cap.max_send_wr = MAX_UMR_WR;
2470 init_attr->cap.max_send_sge = 1;
2471 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2472 init_attr->port_num = 1;
2473 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2475 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2479 qp->device = &dev->ib_dev;
2482 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2484 attr->qp_state = IB_QPS_INIT;
2486 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2489 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2493 memset(attr, 0, sizeof(*attr));
2494 attr->qp_state = IB_QPS_RTR;
2495 attr->path_mtu = IB_MTU_256;
2497 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2499 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2503 memset(attr, 0, sizeof(*attr));
2504 attr->qp_state = IB_QPS_RTS;
2505 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2507 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2515 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2516 ret = mlx5_mr_cache_init(dev);
2518 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2528 mlx5_ib_destroy_qp(qp);
2542 static int create_dev_resources(struct mlx5_ib_resources *devr)
2544 struct ib_srq_init_attr attr;
2545 struct mlx5_ib_dev *dev;
2546 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2550 dev = container_of(devr, struct mlx5_ib_dev, devr);
2552 mutex_init(&devr->mutex);
2554 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2555 if (IS_ERR(devr->p0)) {
2556 ret = PTR_ERR(devr->p0);
2559 devr->p0->device = &dev->ib_dev;
2560 devr->p0->uobject = NULL;
2561 atomic_set(&devr->p0->usecnt, 0);
2563 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2564 if (IS_ERR(devr->c0)) {
2565 ret = PTR_ERR(devr->c0);
2568 devr->c0->device = &dev->ib_dev;
2569 devr->c0->uobject = NULL;
2570 devr->c0->comp_handler = NULL;
2571 devr->c0->event_handler = NULL;
2572 devr->c0->cq_context = NULL;
2573 atomic_set(&devr->c0->usecnt, 0);
2575 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2576 if (IS_ERR(devr->x0)) {
2577 ret = PTR_ERR(devr->x0);
2580 devr->x0->device = &dev->ib_dev;
2581 devr->x0->inode = NULL;
2582 atomic_set(&devr->x0->usecnt, 0);
2583 mutex_init(&devr->x0->tgt_qp_mutex);
2584 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2586 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2587 if (IS_ERR(devr->x1)) {
2588 ret = PTR_ERR(devr->x1);
2591 devr->x1->device = &dev->ib_dev;
2592 devr->x1->inode = NULL;
2593 atomic_set(&devr->x1->usecnt, 0);
2594 mutex_init(&devr->x1->tgt_qp_mutex);
2595 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2597 memset(&attr, 0, sizeof(attr));
2598 attr.attr.max_sge = 1;
2599 attr.attr.max_wr = 1;
2600 attr.srq_type = IB_SRQT_XRC;
2601 attr.ext.xrc.cq = devr->c0;
2602 attr.ext.xrc.xrcd = devr->x0;
2604 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2605 if (IS_ERR(devr->s0)) {
2606 ret = PTR_ERR(devr->s0);
2609 devr->s0->device = &dev->ib_dev;
2610 devr->s0->pd = devr->p0;
2611 devr->s0->uobject = NULL;
2612 devr->s0->event_handler = NULL;
2613 devr->s0->srq_context = NULL;
2614 devr->s0->srq_type = IB_SRQT_XRC;
2615 devr->s0->ext.xrc.xrcd = devr->x0;
2616 devr->s0->ext.xrc.cq = devr->c0;
2617 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2618 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2619 atomic_inc(&devr->p0->usecnt);
2620 atomic_set(&devr->s0->usecnt, 0);
2622 memset(&attr, 0, sizeof(attr));
2623 attr.attr.max_sge = 1;
2624 attr.attr.max_wr = 1;
2625 attr.srq_type = IB_SRQT_BASIC;
2626 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2627 if (IS_ERR(devr->s1)) {
2628 ret = PTR_ERR(devr->s1);
2631 devr->s1->device = &dev->ib_dev;
2632 devr->s1->pd = devr->p0;
2633 devr->s1->uobject = NULL;
2634 devr->s1->event_handler = NULL;
2635 devr->s1->srq_context = NULL;
2636 devr->s1->srq_type = IB_SRQT_BASIC;
2637 devr->s1->ext.xrc.cq = devr->c0;
2638 atomic_inc(&devr->p0->usecnt);
2639 atomic_set(&devr->s0->usecnt, 0);
2641 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2642 INIT_WORK(&devr->ports[port].pkey_change_work,
2643 pkey_change_handler);
2644 devr->ports[port].devr = devr;
2650 mlx5_ib_destroy_srq(devr->s0);
2652 mlx5_ib_dealloc_xrcd(devr->x1);
2654 mlx5_ib_dealloc_xrcd(devr->x0);
2656 mlx5_ib_destroy_cq(devr->c0);
2658 mlx5_ib_dealloc_pd(devr->p0);
2663 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2665 struct mlx5_ib_dev *dev =
2666 container_of(devr, struct mlx5_ib_dev, devr);
2669 mlx5_ib_destroy_srq(devr->s1);
2670 mlx5_ib_destroy_srq(devr->s0);
2671 mlx5_ib_dealloc_xrcd(devr->x0);
2672 mlx5_ib_dealloc_xrcd(devr->x1);
2673 mlx5_ib_destroy_cq(devr->c0);
2674 mlx5_ib_dealloc_pd(devr->p0);
2676 /* Make sure no change P_Key work items are still executing */
2677 for (port = 0; port < dev->num_ports; ++port)
2678 cancel_work_sync(&devr->ports[port].pkey_change_work);
2681 static u32 get_core_cap_flags(struct ib_device *ibdev)
2683 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2684 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2685 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2686 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2689 if (ll == IB_LINK_LAYER_INFINIBAND)
2690 return RDMA_CORE_PORT_IBA_IB;
2692 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2695 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2698 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2699 ret |= RDMA_CORE_PORT_IBA_ROCE;
2701 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2702 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2707 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2708 struct ib_port_immutable *immutable)
2710 struct ib_port_attr attr;
2713 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2717 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2718 immutable->gid_tbl_len = attr.gid_tbl_len;
2719 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2720 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2725 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2728 struct mlx5_ib_dev *dev =
2729 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2730 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2731 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2734 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2739 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2743 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2745 if (dev->roce.nb.notifier_call) {
2746 unregister_netdevice_notifier(&dev->roce.nb);
2747 dev->roce.nb.notifier_call = NULL;
2751 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2753 VNET_ITERATOR_DECL(vnet_iter);
2754 struct net_device *idev;
2757 /* Check if mlx5en net device already exists */
2759 VNET_FOREACH(vnet_iter) {
2761 CURVNET_SET_QUIET(vnet_iter);
2762 TAILQ_FOREACH(idev, &V_ifnet, if_link) {
2763 /* check if network interface belongs to mlx5en */
2764 if (!mlx5_netdev_match(idev, dev->mdev, "mce"))
2766 write_lock(&dev->roce.netdev_lock);
2767 dev->roce.netdev = idev;
2768 write_unlock(&dev->roce.netdev_lock);
2773 VNET_LIST_RUNLOCK();
2775 dev->roce.nb.notifier_call = mlx5_netdev_event;
2776 err = register_netdevice_notifier(&dev->roce.nb);
2778 dev->roce.nb.notifier_call = NULL;
2782 err = mlx5_nic_vport_enable_roce(dev->mdev);
2784 goto err_unregister_netdevice_notifier;
2786 err = mlx5_roce_lag_init(dev);
2788 goto err_disable_roce;
2793 mlx5_nic_vport_disable_roce(dev->mdev);
2795 err_unregister_netdevice_notifier:
2796 mlx5_remove_roce_notifier(dev);
2800 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2802 mlx5_roce_lag_cleanup(dev);
2803 mlx5_nic_vport_disable_roce(dev->mdev);
2806 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
2808 mlx5_vport_dealloc_q_counter(dev->mdev,
2809 MLX5_INTERFACE_PROTOCOL_IB,
2810 dev->port[port_num].q_cnt_id);
2811 dev->port[port_num].q_cnt_id = 0;
2814 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2818 for (i = 0; i < dev->num_ports; i++)
2819 mlx5_ib_dealloc_q_port_counter(dev, i);
2822 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2827 for (i = 0; i < dev->num_ports; i++) {
2828 ret = mlx5_vport_alloc_q_counter(dev->mdev,
2829 MLX5_INTERFACE_PROTOCOL_IB,
2830 &dev->port[i].q_cnt_id);
2833 "couldn't allocate queue counter for port %d, err %d\n",
2835 goto dealloc_counters;
2843 mlx5_ib_dealloc_q_port_counter(dev, i);
2848 static const char * const names[] = {
2849 "rx_write_requests",
2851 "rx_atomic_requests",
2854 "duplicate_request",
2855 "rnr_nak_retry_err",
2857 "implied_nak_seq_err",
2858 "local_ack_timeout_err",
2861 static const size_t stats_offsets[] = {
2862 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2863 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2864 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2865 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2866 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2867 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2868 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2869 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2870 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2871 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2874 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2877 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2879 /* We support only per port stats */
2883 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2884 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2887 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2888 struct rdma_hw_stats *stats,
2891 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2892 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2898 if (!port || !stats)
2901 out = mlx5_vzalloc(outlen);
2905 ret = mlx5_vport_query_q_counter(dev->mdev,
2906 dev->port[port - 1].q_cnt_id, 0,
2911 for (i = 0; i < ARRAY_SIZE(names); i++) {
2912 val = *(__be32 *)(out + stats_offsets[i]);
2913 stats->value[i] = (u64)be32_to_cpu(val);
2917 return ARRAY_SIZE(names);
2920 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2922 struct mlx5_ib_dev *dev;
2923 enum rdma_link_layer ll;
2929 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2930 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2932 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2935 printk_once(KERN_INFO "%s", mlx5_version);
2937 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2943 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2948 rwlock_init(&dev->roce.netdev_lock);
2949 err = get_port_caps(dev);
2953 if (mlx5_use_mad_ifc(dev))
2954 get_ext_port_caps(dev);
2956 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2960 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2961 dev->ib_dev.owner = THIS_MODULE;
2962 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
2963 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
2964 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
2965 dev->ib_dev.phys_port_cnt = dev->num_ports;
2966 dev->ib_dev.num_comp_vectors =
2967 dev->mdev->priv.eq_table.num_comp_vectors;
2968 dev->ib_dev.dma_device = &mdev->pdev->dev;
2970 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2971 dev->ib_dev.uverbs_cmd_mask =
2972 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2973 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2974 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2975 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2976 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2977 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2978 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2979 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2980 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2981 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2982 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2983 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2984 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2985 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2986 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2987 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2988 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2989 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2990 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2991 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2992 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2993 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2994 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2995 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2996 dev->ib_dev.uverbs_ex_cmd_mask =
2997 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2998 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2999 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3001 dev->ib_dev.query_device = mlx5_ib_query_device;
3002 dev->ib_dev.query_port = mlx5_ib_query_port;
3003 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3004 if (ll == IB_LINK_LAYER_ETHERNET)
3005 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3006 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3007 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3008 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3009 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3010 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3011 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3012 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3013 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3014 dev->ib_dev.mmap = mlx5_ib_mmap;
3015 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3016 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3017 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3018 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3019 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3020 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3021 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3022 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3023 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3024 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3025 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3026 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3027 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3028 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3029 dev->ib_dev.post_send = mlx5_ib_post_send;
3030 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3031 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3032 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3033 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3034 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3035 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3036 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3037 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3038 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3039 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3040 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3041 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3042 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3043 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3044 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3045 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3046 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3047 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3048 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3049 if (mlx5_core_is_pf(mdev)) {
3050 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3051 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3052 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3053 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3056 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3058 mlx5_ib_internal_fill_odp_caps(dev);
3060 if (MLX5_CAP_GEN(mdev, imaicl)) {
3061 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3062 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3063 dev->ib_dev.uverbs_cmd_mask |=
3064 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3065 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3068 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3069 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3070 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3071 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3074 if (MLX5_CAP_GEN(mdev, xrc)) {
3075 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3076 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3077 dev->ib_dev.uverbs_cmd_mask |=
3078 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3079 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3082 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3083 IB_LINK_LAYER_ETHERNET) {
3084 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3085 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3086 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3087 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3088 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3089 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3090 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3091 dev->ib_dev.uverbs_ex_cmd_mask |=
3092 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3093 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3094 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3095 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3096 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3097 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3098 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3100 err = init_node_data(dev);
3104 mutex_init(&dev->flow_db.lock);
3105 mutex_init(&dev->cap_mask_mutex);
3106 INIT_LIST_HEAD(&dev->qp_list);
3107 spin_lock_init(&dev->reset_flow_resource_lock);
3109 if (ll == IB_LINK_LAYER_ETHERNET) {
3110 err = mlx5_enable_roce(dev);
3115 err = create_dev_resources(&dev->devr);
3117 goto err_disable_roce;
3119 err = mlx5_ib_odp_init_one(dev);
3123 err = mlx5_ib_alloc_q_counters(dev);
3127 err = ib_register_device(&dev->ib_dev, NULL);
3131 err = create_umr_res(dev);
3135 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3136 err = device_create_file(&dev->ib_dev.dev,
3137 mlx5_class_attributes[i]);
3142 dev->ib_active = true;
3147 destroy_umrc_res(dev);
3150 ib_unregister_device(&dev->ib_dev);
3153 mlx5_ib_dealloc_q_counters(dev);
3156 mlx5_ib_odp_remove_one(dev);
3159 destroy_dev_resources(&dev->devr);
3162 if (ll == IB_LINK_LAYER_ETHERNET) {
3163 mlx5_disable_roce(dev);
3164 mlx5_remove_roce_notifier(dev);
3171 ib_dealloc_device((struct ib_device *)dev);
3176 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3178 struct mlx5_ib_dev *dev = context;
3179 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3181 mlx5_remove_roce_notifier(dev);
3182 ib_unregister_device(&dev->ib_dev);
3183 mlx5_ib_dealloc_q_counters(dev);
3184 destroy_umrc_res(dev);
3185 mlx5_ib_odp_remove_one(dev);
3186 destroy_dev_resources(&dev->devr);
3187 if (ll == IB_LINK_LAYER_ETHERNET)
3188 mlx5_disable_roce(dev);
3190 ib_dealloc_device(&dev->ib_dev);
3193 static struct mlx5_interface mlx5_ib_interface = {
3195 .remove = mlx5_ib_remove,
3196 .event = mlx5_ib_event,
3197 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3200 static int __init mlx5_ib_init(void)
3204 if (deprecated_prof_sel != 2)
3205 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3207 err = mlx5_ib_odp_init();
3211 err = mlx5_register_interface(&mlx5_ib_interface);
3218 mlx5_ib_odp_cleanup();
3222 static void __exit mlx5_ib_cleanup(void)
3224 mlx5_unregister_interface(&mlx5_ib_interface);
3225 mlx5_ib_odp_cleanup();
3228 module_init_order(mlx5_ib_init, SI_ORDER_THIRD);
3229 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD);