sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/errno.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #if defined(CONFIG_X86)
  34 #include <asm/pat.h>
  35 #endif
  36 #include <linux/sched.h>
  37 #include <linux/delay.h>
  38 #include <linux/fs.h>
  39 #undef inode
  40 #include <rdma/ib_user_verbs.h>
  41 #include <rdma/ib_addr.h>
  42 #include <rdma/ib_cache.h>
  43 #include <dev/mlx5/vport.h>
  44 #include <linux/list.h>
  45 #include <rdma/ib_smi.h>
  46 #include <rdma/ib_umem.h>
  47 #include <linux/in.h>
  48 #include <linux/etherdevice.h>
  49 #include <dev/mlx5/fs.h>
  50 #include "mlx5_ib.h"
  51
  52 #define DRIVER_NAME "mlx5_ib"
  53 #define DRIVER_VERSION "3.4.1-BETA"
  54 #define DRIVER_RELDATE  "October 2017"
  55
  56 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  57 MODULE_LICENSE("Dual BSD/GPL");
  58 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
  59 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
  60 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
  61 MODULE_VERSION(mlx5ib, 1);
  62
  63 static int deprecated_prof_sel = 2;
  64 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  65 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  66
  67 static char mlx5_version[] =
  68         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  69         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  70
  71 enum {
  72         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  73 };
  74
  75 static enum rdma_link_layer
  76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  77 {
  78         switch (port_type_cap) {
  79         case MLX5_CAP_PORT_TYPE_IB:
  80                 return IB_LINK_LAYER_INFINIBAND;
  81         case MLX5_CAP_PORT_TYPE_ETH:
  82                 return IB_LINK_LAYER_ETHERNET;
  83         default:
  84                 return IB_LINK_LAYER_UNSPECIFIED;
  85         }
  86 }
  87
  88 static enum rdma_link_layer
  89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  90 {
  91         struct mlx5_ib_dev *dev = to_mdev(device);
  92         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  93
  94         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  95 }
  96
  97 static bool mlx5_netdev_match(struct net_device *ndev,
  98                               struct mlx5_core_dev *mdev,
  99                               const char *dname)
 100 {
 101         return ndev->if_type == IFT_ETHER &&
 102           ndev->if_dname != NULL &&
 103           strcmp(ndev->if_dname, dname) == 0 &&
 104           ndev->if_softc != NULL &&
 105           *(struct mlx5_core_dev **)ndev->if_softc == mdev;
 106 }
 107
 108 static int mlx5_netdev_event(struct notifier_block *this,
 109                              unsigned long event, void *ptr)
 110 {
 111         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 112         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 113                                                  roce.nb);
 114
 115         switch (event) {
 116         case NETDEV_REGISTER:
 117         case NETDEV_UNREGISTER:
 118                 write_lock(&ibdev->roce.netdev_lock);
 119                 /* check if network interface belongs to mlx5en */
 120                 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
 121                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 122                                              NULL : ndev;
 123                 write_unlock(&ibdev->roce.netdev_lock);
 124                 break;
 125
 126         case NETDEV_UP:
 127         case NETDEV_DOWN: {
 128                 struct net_device *upper = NULL;
 129
 130                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 131                     && ibdev->ib_active) {
 132                         struct ib_event ibev = {0};
 133
 134                         ibev.device = &ibdev->ib_dev;
 135                         ibev.event = (event == NETDEV_UP) ?
 136                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 137                         ibev.element.port_num = 1;
 138                         ib_dispatch_event(&ibev);
 139                 }
 140                 break;
 141         }
 142
 143         default:
 144                 break;
 145         }
 146
 147         return NOTIFY_DONE;
 148 }
 149
 150 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 151                                              u8 port_num)
 152 {
 153         struct mlx5_ib_dev *ibdev = to_mdev(device);
 154         struct net_device *ndev;
 155
 156         /* Ensure ndev does not disappear before we invoke dev_hold()
 157          */
 158         read_lock(&ibdev->roce.netdev_lock);
 159         ndev = ibdev->roce.netdev;
 160         if (ndev)
 161                 dev_hold(ndev);
 162         read_unlock(&ibdev->roce.netdev_lock);
 163
 164         return ndev;
 165 }
 166
 167 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 168                                 struct ib_port_attr *props)
 169 {
 170         struct mlx5_ib_dev *dev = to_mdev(device);
 171         struct net_device *ndev;
 172         enum ib_mtu ndev_ib_mtu;
 173         u16 qkey_viol_cntr;
 174
 175         memset(props, 0, sizeof(*props));
 176
 177         props->port_cap_flags  |= IB_PORT_CM_SUP;
 178         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 179
 180         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 181                                                 roce_address_table_size);
 182         props->max_mtu          = IB_MTU_4096;
 183         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 184         props->pkey_tbl_len     = 1;
 185         props->state            = IB_PORT_DOWN;
 186         props->phys_state       = 3;
 187
 188         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 189         props->qkey_viol_cntr = qkey_viol_cntr;
 190
 191         ndev = mlx5_ib_get_netdev(device, port_num);
 192         if (!ndev)
 193                 return 0;
 194
 195         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 196                 props->state      = IB_PORT_ACTIVE;
 197                 props->phys_state = 5;
 198         }
 199
 200         ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu);
 201
 202         dev_put(ndev);
 203
 204         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 205
 206         props->active_width     = IB_WIDTH_4X;  /* TODO */
 207         props->active_speed     = IB_SPEED_QDR; /* TODO */
 208
 209         return 0;
 210 }
 211
 212 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 213                                      const struct ib_gid_attr *attr,
 214                                      void *mlx5_addr)
 215 {
 216 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 217         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 218                                                source_l3_address);
 219         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 220                                                source_mac_47_32);
 221
 222         if (!gid)
 223                 return;
 224         ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev));
 225
 226         if (is_vlan_dev(attr->ndev)) {
 227                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 228                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 229         }
 230
 231         switch (attr->gid_type) {
 232         case IB_GID_TYPE_IB:
 233                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 234                 break;
 235         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 236                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 237                 break;
 238
 239         default:
 240                 WARN_ON(true);
 241         }
 242
 243         if (attr->gid_type != IB_GID_TYPE_IB) {
 244                 if (ipv6_addr_v4mapped((void *)gid))
 245                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 246                                     MLX5_ROCE_L3_TYPE_IPV4);
 247                 else
 248                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 249                                     MLX5_ROCE_L3_TYPE_IPV6);
 250         }
 251
 252         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 253             !ipv6_addr_v4mapped((void *)gid))
 254                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 255         else
 256                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 257 }
 258
 259 static int set_roce_addr(struct ib_device *device, u8 port_num,
 260                          unsigned int index,
 261                          const union ib_gid *gid,
 262                          const struct ib_gid_attr *attr)
 263 {
 264         struct mlx5_ib_dev *dev = to_mdev(device);
 265         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 266         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 267         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 268         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 269
 270         if (ll != IB_LINK_LAYER_ETHERNET)
 271                 return -EINVAL;
 272
 273         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 274
 275         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 276         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 277         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 278 }
 279
 280 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 281                            unsigned int index, const union ib_gid *gid,
 282                            const struct ib_gid_attr *attr,
 283                            __always_unused void **context)
 284 {
 285         return set_roce_addr(device, port_num, index, gid, attr);
 286 }
 287
 288 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 289                            unsigned int index, __always_unused void **context)
 290 {
 291         return set_roce_addr(device, port_num, index, NULL, NULL);
 292 }
 293
 294 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 295                                int index)
 296 {
 297         struct ib_gid_attr attr;
 298         union ib_gid gid;
 299
 300         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 301                 return 0;
 302
 303         if (!attr.ndev)
 304                 return 0;
 305
 306         dev_put(attr.ndev);
 307
 308         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 309                 return 0;
 310
 311         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 312 }
 313
 314 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 315 {
 316         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 317                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 318         return 0;
 319 }
 320
 321 enum {
 322         MLX5_VPORT_ACCESS_METHOD_MAD,
 323         MLX5_VPORT_ACCESS_METHOD_HCA,
 324         MLX5_VPORT_ACCESS_METHOD_NIC,
 325 };
 326
 327 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 328 {
 329         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 330                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 331
 332         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 333             IB_LINK_LAYER_ETHERNET)
 334                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 335
 336         return MLX5_VPORT_ACCESS_METHOD_HCA;
 337 }
 338
 339 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 340                             struct ib_device_attr *props)
 341 {
 342         u8 tmp;
 343         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 344         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 345         u8 atomic_req_8B_endianness_mode =
 346                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 347
 348         /* Check if HW supports 8 bytes standard atomic operations and capable
 349          * of host endianness respond
 350          */
 351         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 352         if (((atomic_operations & tmp) == tmp) &&
 353             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 354             (atomic_req_8B_endianness_mode)) {
 355                 props->atomic_cap = IB_ATOMIC_HCA;
 356         } else {
 357                 props->atomic_cap = IB_ATOMIC_NONE;
 358         }
 359 }
 360
 361 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 362                                         __be64 *sys_image_guid)
 363 {
 364         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 365         struct mlx5_core_dev *mdev = dev->mdev;
 366         u64 tmp;
 367         int err;
 368
 369         switch (mlx5_get_vport_access_method(ibdev)) {
 370         case MLX5_VPORT_ACCESS_METHOD_MAD:
 371                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 372                                                             sys_image_guid);
 373
 374         case MLX5_VPORT_ACCESS_METHOD_HCA:
 375                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 376                 break;
 377
 378         case MLX5_VPORT_ACCESS_METHOD_NIC:
 379                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 380                 break;
 381
 382         default:
 383                 return -EINVAL;
 384         }
 385
 386         if (!err)
 387                 *sys_image_guid = cpu_to_be64(tmp);
 388
 389         return err;
 390
 391 }
 392
 393 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 394                                 u16 *max_pkeys)
 395 {
 396         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 397         struct mlx5_core_dev *mdev = dev->mdev;
 398
 399         switch (mlx5_get_vport_access_method(ibdev)) {
 400         case MLX5_VPORT_ACCESS_METHOD_MAD:
 401                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 402
 403         case MLX5_VPORT_ACCESS_METHOD_HCA:
 404         case MLX5_VPORT_ACCESS_METHOD_NIC:
 405                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 406                                                 pkey_table_size));
 407                 return 0;
 408
 409         default:
 410                 return -EINVAL;
 411         }
 412 }
 413
 414 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 415                                 u32 *vendor_id)
 416 {
 417         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 418
 419         switch (mlx5_get_vport_access_method(ibdev)) {
 420         case MLX5_VPORT_ACCESS_METHOD_MAD:
 421                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 422
 423         case MLX5_VPORT_ACCESS_METHOD_HCA:
 424         case MLX5_VPORT_ACCESS_METHOD_NIC:
 425                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 426
 427         default:
 428                 return -EINVAL;
 429         }
 430 }
 431
 432 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 433                                 __be64 *node_guid)
 434 {
 435         u64 tmp;
 436         int err;
 437
 438         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 439         case MLX5_VPORT_ACCESS_METHOD_MAD:
 440                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 441
 442         case MLX5_VPORT_ACCESS_METHOD_HCA:
 443                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 444                 break;
 445
 446         case MLX5_VPORT_ACCESS_METHOD_NIC:
 447                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 448                 break;
 449
 450         default:
 451                 return -EINVAL;
 452         }
 453
 454         if (!err)
 455                 *node_guid = cpu_to_be64(tmp);
 456
 457         return err;
 458 }
 459
 460 struct mlx5_reg_node_desc {
 461         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 462 };
 463
 464 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 465 {
 466         struct mlx5_reg_node_desc in;
 467
 468         if (mlx5_use_mad_ifc(dev))
 469                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 470
 471         memset(&in, 0, sizeof(in));
 472
 473         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 474                                     sizeof(struct mlx5_reg_node_desc),
 475                                     MLX5_REG_NODE_DESC, 0, 0);
 476 }
 477
 478 static int mlx5_ib_query_device(struct ib_device *ibdev,
 479                                 struct ib_device_attr *props,
 480                                 struct ib_udata *uhw)
 481 {
 482         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 483         struct mlx5_core_dev *mdev = dev->mdev;
 484         int err = -ENOMEM;
 485         int max_rq_sg;
 486         int max_sq_sg;
 487         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 488         struct mlx5_ib_query_device_resp resp = {};
 489         size_t resp_len;
 490         u64 max_tso;
 491
 492         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 493         if (uhw->outlen && uhw->outlen < resp_len)
 494                 return -EINVAL;
 495         else
 496                 resp.response_length = resp_len;
 497
 498         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 499                 return -EINVAL;
 500
 501         memset(props, 0, sizeof(*props));
 502         err = mlx5_query_system_image_guid(ibdev,
 503                                            &props->sys_image_guid);
 504         if (err)
 505                 return err;
 506
 507         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 508         if (err)
 509                 return err;
 510
 511         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 512         if (err)
 513                 return err;
 514
 515         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 516                 (fw_rev_min(dev->mdev) << 16) |
 517                 fw_rev_sub(dev->mdev);
 518         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 519                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 520                 IB_DEVICE_SYS_IMAGE_GUID                |
 521                 IB_DEVICE_RC_RNR_NAK_GEN;
 522
 523         if (MLX5_CAP_GEN(mdev, pkv))
 524                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 525         if (MLX5_CAP_GEN(mdev, qkv))
 526                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 527         if (MLX5_CAP_GEN(mdev, apm))
 528                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 529         if (MLX5_CAP_GEN(mdev, xrc))
 530                 props->device_cap_flags |= IB_DEVICE_XRC;
 531         if (MLX5_CAP_GEN(mdev, imaicl)) {
 532                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 533                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 534                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 535                 /* We support 'Gappy' memory registration too */
 536                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 537         }
 538         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 539         if (MLX5_CAP_GEN(mdev, sho)) {
 540                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 541                 /* At this stage no support for signature handover */
 542                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 543                                       IB_PROT_T10DIF_TYPE_2 |
 544                                       IB_PROT_T10DIF_TYPE_3;
 545                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 546                                        IB_GUARD_T10DIF_CSUM;
 547         }
 548         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 549                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 550
 551         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 552                 if (MLX5_CAP_ETH(mdev, csum_cap))
 553                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 554
 555                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 556                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 557                         if (max_tso) {
 558                                 resp.tso_caps.max_tso = 1 << max_tso;
 559                                 resp.tso_caps.supported_qpts |=
 560                                         1 << IB_QPT_RAW_PACKET;
 561                                 resp.response_length += sizeof(resp.tso_caps);
 562                         }
 563                 }
 564
 565                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 566                         resp.rss_caps.rx_hash_function =
 567                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 568                         resp.rss_caps.rx_hash_fields_mask =
 569                                                 MLX5_RX_HASH_SRC_IPV4 |
 570                                                 MLX5_RX_HASH_DST_IPV4 |
 571                                                 MLX5_RX_HASH_SRC_IPV6 |
 572                                                 MLX5_RX_HASH_DST_IPV6 |
 573                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 574                                                 MLX5_RX_HASH_DST_PORT_TCP |
 575                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 576                                                 MLX5_RX_HASH_DST_PORT_UDP;
 577                         resp.response_length += sizeof(resp.rss_caps);
 578                 }
 579         } else {
 580                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 581                         resp.response_length += sizeof(resp.tso_caps);
 582                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 583                         resp.response_length += sizeof(resp.rss_caps);
 584         }
 585
 586         if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
 587                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 588                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 589         }
 590
 591         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 592             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 593                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 594
 595         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 596                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 597
 598         props->vendor_part_id      = mdev->pdev->device;
 599         props->hw_ver              = mdev->pdev->revision;
 600
 601         props->max_mr_size         = ~0ull;
 602         props->page_size_cap       = ~(min_page_size - 1);
 603         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 604         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 605         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 606                      sizeof(struct mlx5_wqe_data_seg);
 607         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 608                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 609                      sizeof(struct mlx5_wqe_data_seg);
 610         props->max_sge = min(max_rq_sg, max_sq_sg);
 611         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 612         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 613         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 614         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 615         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 616         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 617         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 618         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 619         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 620         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 621         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 622         props->max_srq_sge         = max_rq_sg - 1;
 623         props->max_fast_reg_page_list_len =
 624                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 625         get_atomic_caps(dev, props);
 626         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 627         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 628         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 629         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 630                                            props->max_mcast_grp;
 631         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 632         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 633         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 634
 635 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 636         if (MLX5_CAP_GEN(mdev, pg))
 637                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 638         props->odp_caps = dev->odp_caps;
 639 #endif
 640
 641         if (MLX5_CAP_GEN(mdev, cd))
 642                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 643
 644         if (!mlx5_core_is_pf(mdev))
 645                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 646
 647         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 648             IB_LINK_LAYER_ETHERNET) {
 649                 props->rss_caps.max_rwq_indirection_tables =
 650                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 651                 props->rss_caps.max_rwq_indirection_table_size =
 652                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 653                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 654                 props->max_wq_type_rq =
 655                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 656         }
 657
 658         if (uhw->outlen) {
 659                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 660
 661                 if (err)
 662                         return err;
 663         }
 664
 665         return 0;
 666 }
 667
 668 enum mlx5_ib_width {
 669         MLX5_IB_WIDTH_1X        = 1 << 0,
 670         MLX5_IB_WIDTH_2X        = 1 << 1,
 671         MLX5_IB_WIDTH_4X        = 1 << 2,
 672         MLX5_IB_WIDTH_8X        = 1 << 3,
 673         MLX5_IB_WIDTH_12X       = 1 << 4
 674 };
 675
 676 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 677                                   u8 *ib_width)
 678 {
 679         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 680         int err = 0;
 681
 682         if (active_width & MLX5_IB_WIDTH_1X) {
 683                 *ib_width = IB_WIDTH_1X;
 684         } else if (active_width & MLX5_IB_WIDTH_2X) {
 685                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 686                             (int)active_width);
 687                 err = -EINVAL;
 688         } else if (active_width & MLX5_IB_WIDTH_4X) {
 689                 *ib_width = IB_WIDTH_4X;
 690         } else if (active_width & MLX5_IB_WIDTH_8X) {
 691                 *ib_width = IB_WIDTH_8X;
 692         } else if (active_width & MLX5_IB_WIDTH_12X) {
 693                 *ib_width = IB_WIDTH_12X;
 694         } else {
 695                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 696                             (int)active_width);
 697                 err = -EINVAL;
 698         }
 699
 700         return err;
 701 }
 702
 703 enum ib_max_vl_num {
 704         __IB_MAX_VL_0           = 1,
 705         __IB_MAX_VL_0_1         = 2,
 706         __IB_MAX_VL_0_3         = 3,
 707         __IB_MAX_VL_0_7         = 4,
 708         __IB_MAX_VL_0_14        = 5,
 709 };
 710
 711 enum mlx5_vl_hw_cap {
 712         MLX5_VL_HW_0    = 1,
 713         MLX5_VL_HW_0_1  = 2,
 714         MLX5_VL_HW_0_2  = 3,
 715         MLX5_VL_HW_0_3  = 4,
 716         MLX5_VL_HW_0_4  = 5,
 717         MLX5_VL_HW_0_5  = 6,
 718         MLX5_VL_HW_0_6  = 7,
 719         MLX5_VL_HW_0_7  = 8,
 720         MLX5_VL_HW_0_14 = 15
 721 };
 722
 723 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 724                                 u8 *max_vl_num)
 725 {
 726         switch (vl_hw_cap) {
 727         case MLX5_VL_HW_0:
 728                 *max_vl_num = __IB_MAX_VL_0;
 729                 break;
 730         case MLX5_VL_HW_0_1:
 731                 *max_vl_num = __IB_MAX_VL_0_1;
 732                 break;
 733         case MLX5_VL_HW_0_3:
 734                 *max_vl_num = __IB_MAX_VL_0_3;
 735                 break;
 736         case MLX5_VL_HW_0_7:
 737                 *max_vl_num = __IB_MAX_VL_0_7;
 738                 break;
 739         case MLX5_VL_HW_0_14:
 740                 *max_vl_num = __IB_MAX_VL_0_14;
 741                 break;
 742
 743         default:
 744                 return -EINVAL;
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 751                                struct ib_port_attr *props)
 752 {
 753         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 754         struct mlx5_core_dev *mdev = dev->mdev;
 755         u32 *rep;
 756         int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
 757         struct mlx5_ptys_reg *ptys;
 758         struct mlx5_pmtu_reg *pmtu;
 759         struct mlx5_pvlc_reg pvlc;
 760         void *ctx;
 761         int err;
 762
 763         rep = mlx5_vzalloc(replen);
 764         ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
 765         pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
 766         if (!rep || !ptys || !pmtu) {
 767                 err = -ENOMEM;
 768                 goto out;
 769         }
 770
 771         memset(props, 0, sizeof(*props));
 772
 773         err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
 774         if (err)
 775                 goto out;
 776
 777         ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
 778
 779         props->lid              = MLX5_GET(hca_vport_context, ctx, lid);
 780         props->lmc              = MLX5_GET(hca_vport_context, ctx, lmc);
 781         props->sm_lid           = MLX5_GET(hca_vport_context, ctx, sm_lid);
 782         props->sm_sl            = MLX5_GET(hca_vport_context, ctx, sm_sl);
 783         props->state            = MLX5_GET(hca_vport_context, ctx, vport_state);
 784         props->phys_state       = MLX5_GET(hca_vport_context, ctx,
 785                                         port_physical_state);
 786         props->port_cap_flags   = MLX5_GET(hca_vport_context, ctx, cap_mask1);
 787         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 788         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 789         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 790         props->bad_pkey_cntr    = MLX5_GET(hca_vport_context, ctx,
 791                                         pkey_violation_counter);
 792         props->qkey_viol_cntr   = MLX5_GET(hca_vport_context, ctx,
 793                                         qkey_violation_counter);
 794         props->subnet_timeout   = MLX5_GET(hca_vport_context, ctx,
 795                                         subnet_timeout);
 796         props->init_type_reply  = MLX5_GET(hca_vport_context, ctx,
 797                                         init_type_reply);
 798         props->grh_required     = MLX5_GET(hca_vport_context, ctx, grh_required);
 799
 800         ptys->proto_mask |= MLX5_PTYS_IB;
 801         ptys->local_port = port;
 802         err = mlx5_core_access_ptys(mdev, ptys, 0);
 803         if (err)
 804                 goto out;
 805
 806         err = translate_active_width(ibdev, ptys->ib_link_width_oper,
 807                                      &props->active_width);
 808         if (err)
 809                 goto out;
 810
 811         props->active_speed     = (u8)ptys->ib_proto_oper;
 812
 813         pmtu->local_port = port;
 814         err = mlx5_core_access_pmtu(mdev, pmtu, 0);
 815         if (err)
 816                 goto out;
 817
 818         props->max_mtu          = pmtu->max_mtu;
 819         props->active_mtu       = pmtu->oper_mtu;
 820
 821         memset(&pvlc, 0, sizeof(pvlc));
 822         pvlc.local_port = port;
 823         err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
 824         if (err)
 825                 goto out;
 826
 827         err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
 828                                    &props->max_vl_num);
 829 out:
 830         kvfree(rep);
 831         kfree(ptys);
 832         kfree(pmtu);
 833         return err;
 834 }
 835
 836 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 837                        struct ib_port_attr *props)
 838 {
 839         switch (mlx5_get_vport_access_method(ibdev)) {
 840         case MLX5_VPORT_ACCESS_METHOD_MAD:
 841                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 842
 843         case MLX5_VPORT_ACCESS_METHOD_HCA:
 844                 return mlx5_query_hca_port(ibdev, port, props);
 845
 846         case MLX5_VPORT_ACCESS_METHOD_NIC:
 847                 return mlx5_query_port_roce(ibdev, port, props);
 848
 849         default:
 850                 return -EINVAL;
 851         }
 852 }
 853
 854 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 855                              union ib_gid *gid)
 856 {
 857         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 858         struct mlx5_core_dev *mdev = dev->mdev;
 859
 860         switch (mlx5_get_vport_access_method(ibdev)) {
 861         case MLX5_VPORT_ACCESS_METHOD_MAD:
 862                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 863
 864         case MLX5_VPORT_ACCESS_METHOD_HCA:
 865                 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
 866
 867         default:
 868                 return -EINVAL;
 869         }
 870
 871 }
 872
 873 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 874                               u16 *pkey)
 875 {
 876         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 877         struct mlx5_core_dev *mdev = dev->mdev;
 878
 879         switch (mlx5_get_vport_access_method(ibdev)) {
 880         case MLX5_VPORT_ACCESS_METHOD_MAD:
 881                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 882
 883         case MLX5_VPORT_ACCESS_METHOD_HCA:
 884         case MLX5_VPORT_ACCESS_METHOD_NIC:
 885                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 886                                                  pkey);
 887         default:
 888                 return -EINVAL;
 889         }
 890 }
 891
 892 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 893                                  struct ib_device_modify *props)
 894 {
 895         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 896         struct mlx5_reg_node_desc in;
 897         struct mlx5_reg_node_desc out;
 898         int err;
 899
 900         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 901                 return -EOPNOTSUPP;
 902
 903         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 904                 return 0;
 905
 906         /*
 907          * If possible, pass node desc to FW, so it can generate
 908          * a 144 trap.  If cmd fails, just ignore.
 909          */
 910         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 911         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 912                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 913         if (err)
 914                 return err;
 915
 916         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 917
 918         return err;
 919 }
 920
 921 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 922                                struct ib_port_modify *props)
 923 {
 924         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 925         struct ib_port_attr attr;
 926         u32 tmp;
 927         int err;
 928
 929         mutex_lock(&dev->cap_mask_mutex);
 930
 931         err = mlx5_ib_query_port(ibdev, port, &attr);
 932         if (err)
 933                 goto out;
 934
 935         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 936                 ~props->clr_port_cap_mask;
 937
 938         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 939
 940 out:
 941         mutex_unlock(&dev->cap_mask_mutex);
 942         return err;
 943 }
 944
 945 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 946                                                   struct ib_udata *udata)
 947 {
 948         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 949         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 950         struct mlx5_ib_alloc_ucontext_resp resp = {};
 951         struct mlx5_ib_ucontext *context;
 952         struct mlx5_uuar_info *uuari;
 953         struct mlx5_uar *uars;
 954         int gross_uuars;
 955         int num_uars;
 956         int ver;
 957         int uuarn;
 958         int err;
 959         int i;
 960         size_t reqlen;
 961         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 962                                      max_cqe_version);
 963
 964         if (!dev->ib_active)
 965                 return ERR_PTR(-EAGAIN);
 966
 967         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 968                 return ERR_PTR(-EINVAL);
 969
 970         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 971         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 972                 ver = 0;
 973         else if (reqlen >= min_req_v2)
 974                 ver = 2;
 975         else
 976                 return ERR_PTR(-EINVAL);
 977
 978         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 979         if (err)
 980                 return ERR_PTR(err);
 981
 982         if (req.flags)
 983                 return ERR_PTR(-EINVAL);
 984
 985         if (req.total_num_uuars > MLX5_MAX_UUARS)
 986                 return ERR_PTR(-ENOMEM);
 987
 988         if (req.total_num_uuars == 0)
 989                 return ERR_PTR(-EINVAL);
 990
 991         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 992                 return ERR_PTR(-EOPNOTSUPP);
 993
 994         if (reqlen > sizeof(req) &&
 995             !ib_is_udata_cleared(udata, sizeof(req),
 996                                  reqlen - sizeof(req)))
 997                 return ERR_PTR(-EOPNOTSUPP);
 998
 999         req.total_num_uuars = ALIGN(req.total_num_uuars,
1000                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1001         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1002                 return ERR_PTR(-EINVAL);
1003
1004         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1005         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1006         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1007         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1008                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1009         resp.cache_line_size = cache_line_size();
1010         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1011         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1012         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1013         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1014         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1015         resp.cqe_version = min_t(__u8,
1016                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1017                                  req.max_cqe_version);
1018         resp.response_length = min(offsetof(typeof(resp), response_length) +
1019                                    sizeof(resp.response_length), udata->outlen);
1020
1021         context = kzalloc(sizeof(*context), GFP_KERNEL);
1022         if (!context)
1023                 return ERR_PTR(-ENOMEM);
1024
1025         uuari = &context->uuari;
1026         mutex_init(&uuari->lock);
1027         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1028         if (!uars) {
1029                 err = -ENOMEM;
1030                 goto out_ctx;
1031         }
1032
1033         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1034                                 sizeof(*uuari->bitmap),
1035                                 GFP_KERNEL);
1036         if (!uuari->bitmap) {
1037                 err = -ENOMEM;
1038                 goto out_uar_ctx;
1039         }
1040         /*
1041          * clear all fast path uuars
1042          */
1043         for (i = 0; i < gross_uuars; i++) {
1044                 uuarn = i & 3;
1045                 if (uuarn == 2 || uuarn == 3)
1046                         set_bit(i, uuari->bitmap);
1047         }
1048
1049         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1050         if (!uuari->count) {
1051                 err = -ENOMEM;
1052                 goto out_bitmap;
1053         }
1054
1055         for (i = 0; i < num_uars; i++) {
1056                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1057                 if (err)
1058                         goto out_count;
1059         }
1060
1061 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1062         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1063 #endif
1064
1065         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1066                 err = mlx5_alloc_transport_domain(dev->mdev,
1067                                                        &context->tdn);
1068                 if (err)
1069                         goto out_uars;
1070         }
1071
1072         INIT_LIST_HEAD(&context->vma_private_list);
1073         INIT_LIST_HEAD(&context->db_page_list);
1074         mutex_init(&context->db_page_mutex);
1075
1076         resp.tot_uuars = req.total_num_uuars;
1077         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1078
1079         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1080                 resp.response_length += sizeof(resp.cqe_version);
1081
1082         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1083                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1084                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1085         }
1086
1087         /*
1088          * We don't want to expose information from the PCI bar that is located
1089          * after 4096 bytes, so if the arch only supports larger pages, let's
1090          * pretend we don't support reading the HCA's core clock. This is also
1091          * forced by mmap function.
1092          */
1093         if (PAGE_SIZE <= 4096 &&
1094             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1095                 resp.comp_mask |=
1096                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1097                 resp.hca_core_clock_offset =
1098                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1099                         PAGE_SIZE;
1100                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1101                                         sizeof(resp.reserved2);
1102         }
1103
1104         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1105         if (err)
1106                 goto out_td;
1107
1108         uuari->ver = ver;
1109         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1110         uuari->uars = uars;
1111         uuari->num_uars = num_uars;
1112         context->cqe_version = resp.cqe_version;
1113
1114         return &context->ibucontext;
1115
1116 out_td:
1117         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1118                 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1119
1120 out_uars:
1121         for (i--; i >= 0; i--)
1122                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1123 out_count:
1124         kfree(uuari->count);
1125
1126 out_bitmap:
1127         kfree(uuari->bitmap);
1128
1129 out_uar_ctx:
1130         kfree(uars);
1131
1132 out_ctx:
1133         kfree(context);
1134         return ERR_PTR(err);
1135 }
1136
1137 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1138 {
1139         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1140         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1141         struct mlx5_uuar_info *uuari = &context->uuari;
1142         int i;
1143
1144         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1145                 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1146
1147         for (i = 0; i < uuari->num_uars; i++) {
1148                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1149                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1150         }
1151
1152         kfree(uuari->count);
1153         kfree(uuari->bitmap);
1154         kfree(uuari->uars);
1155         kfree(context);
1156
1157         return 0;
1158 }
1159
1160 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1161 {
1162         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1163 }
1164
1165 static int get_command(unsigned long offset)
1166 {
1167         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1168 }
1169
1170 static int get_arg(unsigned long offset)
1171 {
1172         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1173 }
1174
1175 static int get_index(unsigned long offset)
1176 {
1177         return get_arg(offset);
1178 }
1179
1180 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1181 {
1182         /* vma_open is called when a new VMA is created on top of our VMA.  This
1183          * is done through either mremap flow or split_vma (usually due to
1184          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1185          * as this VMA is strongly hardware related.  Therefore we set the
1186          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1187          * calling us again and trying to do incorrect actions.  We assume that
1188          * the original VMA size is exactly a single page, and therefore all
1189          * "splitting" operation will not happen to it.
1190          */
1191         area->vm_ops = NULL;
1192 }
1193
1194 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1195 {
1196         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1197
1198         /* It's guaranteed that all VMAs opened on a FD are closed before the
1199          * file itself is closed, therefore no sync is needed with the regular
1200          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1201          * However need a sync with accessing the vma as part of
1202          * mlx5_ib_disassociate_ucontext.
1203          * The close operation is usually called under mm->mmap_sem except when
1204          * process is exiting.
1205          * The exiting case is handled explicitly as part of
1206          * mlx5_ib_disassociate_ucontext.
1207          */
1208         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1209
1210         /* setting the vma context pointer to null in the mlx5_ib driver's
1211          * private data, to protect a race condition in
1212          * mlx5_ib_disassociate_ucontext().
1213          */
1214         mlx5_ib_vma_priv_data->vma = NULL;
1215         list_del(&mlx5_ib_vma_priv_data->list);
1216         kfree(mlx5_ib_vma_priv_data);
1217 }
1218
1219 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1220         .open = mlx5_ib_vma_open,
1221         .close = mlx5_ib_vma_close
1222 };
1223
1224 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1225                                 struct mlx5_ib_ucontext *ctx)
1226 {
1227         struct mlx5_ib_vma_private_data *vma_prv;
1228         struct list_head *vma_head = &ctx->vma_private_list;
1229
1230         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1231         if (!vma_prv)
1232                 return -ENOMEM;
1233
1234         vma_prv->vma = vma;
1235         vma->vm_private_data = vma_prv;
1236         vma->vm_ops =  &mlx5_ib_vm_ops;
1237
1238         list_add(&vma_prv->list, vma_head);
1239
1240         return 0;
1241 }
1242
1243 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1244 {
1245         int ret;
1246         struct vm_area_struct *vma;
1247         struct mlx5_ib_vma_private_data *vma_private, *n;
1248         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1249         struct task_struct *owning_process  = NULL;
1250         struct mm_struct   *owning_mm       = NULL;
1251
1252         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1253         if (!owning_process)
1254                 return;
1255
1256         owning_mm = get_task_mm(owning_process);
1257         if (!owning_mm) {
1258                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1259                 while (1) {
1260                         put_task_struct(owning_process);
1261                         usleep_range(1000, 2000);
1262                         owning_process = get_pid_task(ibcontext->tgid,
1263                                                       PIDTYPE_PID);
1264                         if (!owning_process /* ||
1265                             owning_process->state == TASK_DEAD */) {
1266                                 pr_info("disassociate ucontext done, task was terminated\n");
1267                                 /* in case task was dead need to release the
1268                                  * task struct.
1269                                  */
1270                                 if (owning_process)
1271                                         put_task_struct(owning_process);
1272                                 return;
1273                         }
1274                 }
1275         }
1276
1277         /* need to protect from a race on closing the vma as part of
1278          * mlx5_ib_vma_close.
1279          */
1280         down_read(&owning_mm->mmap_sem);
1281         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1282                                  list) {
1283                 vma = vma_private->vma;
1284                 ret = zap_vma_ptes(vma, vma->vm_start,
1285                                    PAGE_SIZE);
1286                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1287                 /* context going to be destroyed, should
1288                  * not access ops any more.
1289                  */
1290                 vma->vm_ops = NULL;
1291                 list_del(&vma_private->list);
1292                 kfree(vma_private);
1293         }
1294         up_read(&owning_mm->mmap_sem);
1295         mmput(owning_mm);
1296         put_task_struct(owning_process);
1297 }
1298
1299 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1300 {
1301         switch (cmd) {
1302         case MLX5_IB_MMAP_WC_PAGE:
1303                 return "WC";
1304         case MLX5_IB_MMAP_REGULAR_PAGE:
1305                 return "best effort WC";
1306         case MLX5_IB_MMAP_NC_PAGE:
1307                 return "NC";
1308         default:
1309                 return NULL;
1310         }
1311 }
1312
1313 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1314                     struct vm_area_struct *vma,
1315                     struct mlx5_ib_ucontext *context)
1316 {
1317         struct mlx5_uuar_info *uuari = &context->uuari;
1318         int err;
1319         unsigned long idx;
1320         phys_addr_t pfn, pa;
1321         pgprot_t prot;
1322
1323         switch (cmd) {
1324         case MLX5_IB_MMAP_WC_PAGE:
1325 /* Some architectures don't support WC memory */
1326 #if defined(CONFIG_X86)
1327                 if (!pat_enabled())
1328                         return -EPERM;
1329 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1330                         return -EPERM;
1331 #endif
1332         /* fall through */
1333         case MLX5_IB_MMAP_REGULAR_PAGE:
1334                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1335                 prot = pgprot_writecombine(vma->vm_page_prot);
1336                 break;
1337         case MLX5_IB_MMAP_NC_PAGE:
1338                 prot = pgprot_noncached(vma->vm_page_prot);
1339                 break;
1340         default:
1341                 return -EINVAL;
1342         }
1343
1344         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1345                 return -EINVAL;
1346
1347         idx = get_index(vma->vm_pgoff);
1348         if (idx >= uuari->num_uars)
1349                 return -EINVAL;
1350
1351         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1352         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1353
1354         vma->vm_page_prot = prot;
1355         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1356                                  PAGE_SIZE, vma->vm_page_prot);
1357         if (err) {
1358                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n",
1359                             err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd));
1360                 return -EAGAIN;
1361         }
1362
1363         pa = pfn << PAGE_SHIFT;
1364         mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd),
1365                     (unsigned long long)vma->vm_start, &pa);
1366
1367         return mlx5_ib_set_vma_data(vma, context);
1368 }
1369
1370 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1371 {
1372         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1373         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1374         unsigned long command;
1375         phys_addr_t pfn;
1376
1377         command = get_command(vma->vm_pgoff);
1378         switch (command) {
1379         case MLX5_IB_MMAP_WC_PAGE:
1380         case MLX5_IB_MMAP_NC_PAGE:
1381         case MLX5_IB_MMAP_REGULAR_PAGE:
1382                 return uar_mmap(dev, command, vma, context);
1383
1384         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1385                 return -ENOSYS;
1386
1387         case MLX5_IB_MMAP_CORE_CLOCK:
1388                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1389                         return -EINVAL;
1390
1391                 if (vma->vm_flags & VM_WRITE)
1392                         return -EPERM;
1393
1394                 /* Don't expose to user-space information it shouldn't have */
1395                 if (PAGE_SIZE > 4096)
1396                         return -EOPNOTSUPP;
1397
1398                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1399                 pfn = (dev->mdev->iseg_base +
1400                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1401                         PAGE_SHIFT;
1402                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1403                                        PAGE_SIZE, vma->vm_page_prot))
1404                         return -EAGAIN;
1405
1406                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n",
1407                             (unsigned long long)vma->vm_start,
1408                             (unsigned long long)pfn << PAGE_SHIFT);
1409                 break;
1410
1411         default:
1412                 return -EINVAL;
1413         }
1414
1415         return 0;
1416 }
1417
1418 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1419                                       struct ib_ucontext *context,
1420                                       struct ib_udata *udata)
1421 {
1422         struct mlx5_ib_alloc_pd_resp resp;
1423         struct mlx5_ib_pd *pd;
1424         int err;
1425
1426         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1427         if (!pd)
1428                 return ERR_PTR(-ENOMEM);
1429
1430         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1431         if (err) {
1432                 kfree(pd);
1433                 return ERR_PTR(err);
1434         }
1435
1436         if (context) {
1437                 resp.pdn = pd->pdn;
1438                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1439                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1440                         kfree(pd);
1441                         return ERR_PTR(-EFAULT);
1442                 }
1443         }
1444
1445         return &pd->ibpd;
1446 }
1447
1448 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1449 {
1450         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1451         struct mlx5_ib_pd *mpd = to_mpd(pd);
1452
1453         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1454         kfree(mpd);
1455
1456         return 0;
1457 }
1458
1459 enum {
1460         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1461         MATCH_CRITERIA_ENABLE_MISC_BIT,
1462         MATCH_CRITERIA_ENABLE_INNER_BIT
1463 };
1464
1465 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1466         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1467                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1468
1469 static u8 get_match_criteria_enable(u32 *match_criteria)
1470 {
1471         u8 match_criteria_enable;
1472
1473         match_criteria_enable =
1474                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1475                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1476         match_criteria_enable |=
1477                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1478                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1479         match_criteria_enable |=
1480                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1481                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1482
1483         return match_criteria_enable;
1484 }
1485
1486 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1487 {
1488         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1489         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1490 }
1491
1492 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1493 {
1494         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1495         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1496         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1497         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1498 }
1499
1500 #define LAST_ETH_FIELD vlan_tag
1501 #define LAST_IB_FIELD sl
1502 #define LAST_IPV4_FIELD tos
1503 #define LAST_IPV6_FIELD traffic_class
1504 #define LAST_TCP_UDP_FIELD src_port
1505
1506 /* Field is the last supported field */
1507 #define FIELDS_NOT_SUPPORTED(filter, field)\
1508         memchr_inv((void *)&filter.field  +\
1509                    sizeof(filter.field), 0,\
1510                    sizeof(filter) -\
1511                    offsetof(typeof(filter), field) -\
1512                    sizeof(filter.field))
1513
1514 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1515                            const union ib_flow_spec *ib_spec)
1516 {
1517         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1518                                              outer_headers);
1519         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1520                                              outer_headers);
1521         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1522                                            misc_parameters);
1523         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1524                                            misc_parameters);
1525
1526         switch (ib_spec->type) {
1527         case IB_FLOW_SPEC_ETH:
1528                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1529                         return -ENOTSUPP;
1530
1531                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1532                                              dmac_47_16),
1533                                 ib_spec->eth.mask.dst_mac);
1534                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1535                                              dmac_47_16),
1536                                 ib_spec->eth.val.dst_mac);
1537
1538                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1539                                              smac_47_16),
1540                                 ib_spec->eth.mask.src_mac);
1541                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1542                                              smac_47_16),
1543                                 ib_spec->eth.val.src_mac);
1544
1545                 if (ib_spec->eth.mask.vlan_tag) {
1546                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1547                                  cvlan_tag, 1);
1548                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1549                                  cvlan_tag, 1);
1550
1551                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1552                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1553                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1554                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1555
1556                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1557                                  first_cfi,
1558                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1559                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1560                                  first_cfi,
1561                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1562
1563                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1564                                  first_prio,
1565                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1566                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1567                                  first_prio,
1568                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1569                 }
1570                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1571                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1572                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1573                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1574                 break;
1575         case IB_FLOW_SPEC_IPV4:
1576                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1577                         return -ENOTSUPP;
1578
1579                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1580                          ethertype, 0xffff);
1581                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1582                          ethertype, ETH_P_IP);
1583
1584                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1585                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1586                        &ib_spec->ipv4.mask.src_ip,
1587                        sizeof(ib_spec->ipv4.mask.src_ip));
1588                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1589                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1590                        &ib_spec->ipv4.val.src_ip,
1591                        sizeof(ib_spec->ipv4.val.src_ip));
1592                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1593                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1594                        &ib_spec->ipv4.mask.dst_ip,
1595                        sizeof(ib_spec->ipv4.mask.dst_ip));
1596                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1597                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1598                        &ib_spec->ipv4.val.dst_ip,
1599                        sizeof(ib_spec->ipv4.val.dst_ip));
1600
1601                 set_tos(outer_headers_c, outer_headers_v,
1602                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1603
1604                 set_proto(outer_headers_c, outer_headers_v,
1605                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1606                 break;
1607         case IB_FLOW_SPEC_IPV6:
1608                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1609                         return -ENOTSUPP;
1610
1611                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1612                          ethertype, 0xffff);
1613                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1614                          ethertype, IPPROTO_IPV6);
1615
1616                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1617                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1618                        &ib_spec->ipv6.mask.src_ip,
1619                        sizeof(ib_spec->ipv6.mask.src_ip));
1620                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1621                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1622                        &ib_spec->ipv6.val.src_ip,
1623                        sizeof(ib_spec->ipv6.val.src_ip));
1624                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1625                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1626                        &ib_spec->ipv6.mask.dst_ip,
1627                        sizeof(ib_spec->ipv6.mask.dst_ip));
1628                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1629                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1630                        &ib_spec->ipv6.val.dst_ip,
1631                        sizeof(ib_spec->ipv6.val.dst_ip));
1632
1633                 set_tos(outer_headers_c, outer_headers_v,
1634                         ib_spec->ipv6.mask.traffic_class,
1635                         ib_spec->ipv6.val.traffic_class);
1636
1637                 set_proto(outer_headers_c, outer_headers_v,
1638                           ib_spec->ipv6.mask.next_hdr,
1639                           ib_spec->ipv6.val.next_hdr);
1640
1641                 MLX5_SET(fte_match_set_misc, misc_params_c,
1642                          outer_ipv6_flow_label,
1643                          ntohl(ib_spec->ipv6.mask.flow_label));
1644                 MLX5_SET(fte_match_set_misc, misc_params_v,
1645                          outer_ipv6_flow_label,
1646                          ntohl(ib_spec->ipv6.val.flow_label));
1647                 break;
1648         case IB_FLOW_SPEC_TCP:
1649                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1650                                          LAST_TCP_UDP_FIELD))
1651                         return -ENOTSUPP;
1652
1653                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1654                          0xff);
1655                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1656                          IPPROTO_TCP);
1657
1658                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1659                          ntohs(ib_spec->tcp_udp.mask.src_port));
1660                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1661                          ntohs(ib_spec->tcp_udp.val.src_port));
1662
1663                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1664                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1665                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1666                          ntohs(ib_spec->tcp_udp.val.dst_port));
1667                 break;
1668         case IB_FLOW_SPEC_UDP:
1669                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1670                                          LAST_TCP_UDP_FIELD))
1671                         return -ENOTSUPP;
1672
1673                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1674                          0xff);
1675                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1676                          IPPROTO_UDP);
1677
1678                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1679                          ntohs(ib_spec->tcp_udp.mask.src_port));
1680                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1681                          ntohs(ib_spec->tcp_udp.val.src_port));
1682
1683                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1684                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1685                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1686                          ntohs(ib_spec->tcp_udp.val.dst_port));
1687                 break;
1688         default:
1689                 return -EINVAL;
1690         }
1691
1692         return 0;
1693 }
1694
1695 /* If a flow could catch both multicast and unicast packets,
1696  * it won't fall into the multicast flow steering table and this rule
1697  * could steal other multicast packets.
1698  */
1699 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1700 {
1701         struct ib_flow_spec_eth *eth_spec;
1702
1703         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1704             ib_attr->size < sizeof(struct ib_flow_attr) +
1705             sizeof(struct ib_flow_spec_eth) ||
1706             ib_attr->num_of_specs < 1)
1707                 return false;
1708
1709         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1710         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1711             eth_spec->size != sizeof(*eth_spec))
1712                 return false;
1713
1714         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1715                is_multicast_ether_addr(eth_spec->val.dst_mac);
1716 }
1717
1718 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1719 {
1720         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1721         bool has_ipv4_spec = false;
1722         bool eth_type_ipv4 = true;
1723         unsigned int spec_index;
1724
1725         /* Validate that ethertype is correct */
1726         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1727                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1728                     ib_spec->eth.mask.ether_type) {
1729                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1730                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1731                                 eth_type_ipv4 = false;
1732                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1733                         has_ipv4_spec = true;
1734                 }
1735                 ib_spec = (void *)ib_spec + ib_spec->size;
1736         }
1737         return !has_ipv4_spec || eth_type_ipv4;
1738 }
1739
1740 static void put_flow_table(struct mlx5_ib_dev *dev,
1741                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1742 {
1743         prio->refcount -= !!ft_added;
1744         if (!prio->refcount) {
1745                 mlx5_destroy_flow_table(prio->flow_table);
1746                 prio->flow_table = NULL;
1747         }
1748 }
1749
1750 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1751 {
1752         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1753         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1754                                                           struct mlx5_ib_flow_handler,
1755                                                           ibflow);
1756         struct mlx5_ib_flow_handler *iter, *tmp;
1757
1758         mutex_lock(&dev->flow_db.lock);
1759
1760         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1761                 mlx5_del_flow_rule(iter->rule);
1762                 put_flow_table(dev, iter->prio, true);
1763                 list_del(&iter->list);
1764                 kfree(iter);
1765         }
1766
1767         mlx5_del_flow_rule(handler->rule);
1768         put_flow_table(dev, handler->prio, true);
1769         mutex_unlock(&dev->flow_db.lock);
1770
1771         kfree(handler);
1772
1773         return 0;
1774 }
1775
1776 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1777 {
1778         priority *= 2;
1779         if (!dont_trap)
1780                 priority++;
1781         return priority;
1782 }
1783
1784 enum flow_table_type {
1785         MLX5_IB_FT_RX,
1786         MLX5_IB_FT_TX
1787 };
1788
1789 #define MLX5_FS_MAX_TYPES        10
1790 #define MLX5_FS_MAX_ENTRIES      32000UL
1791 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1792                                                 struct ib_flow_attr *flow_attr,
1793                                                 enum flow_table_type ft_type)
1794 {
1795         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1796         struct mlx5_flow_namespace *ns = NULL;
1797         struct mlx5_ib_flow_prio *prio;
1798         struct mlx5_flow_table *ft;
1799         int num_entries;
1800         int num_groups;
1801         int priority;
1802         int err = 0;
1803
1804         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1805                 if (flow_is_multicast_only(flow_attr) &&
1806                     !dont_trap)
1807                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1808                 else
1809                         priority = ib_prio_to_core_prio(flow_attr->priority,
1810                                                         dont_trap);
1811                 ns = mlx5_get_flow_namespace(dev->mdev,
1812                                              MLX5_FLOW_NAMESPACE_BYPASS);
1813                 num_entries = MLX5_FS_MAX_ENTRIES;
1814                 num_groups = MLX5_FS_MAX_TYPES;
1815                 prio = &dev->flow_db.prios[priority];
1816         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1817                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1818                 ns = mlx5_get_flow_namespace(dev->mdev,
1819                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1820                 build_leftovers_ft_param("bypass", &priority,
1821                                          &num_entries,
1822                                          &num_groups);
1823                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1824         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1825                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1826                                         allow_sniffer_and_nic_rx_shared_tir))
1827                         return ERR_PTR(-ENOTSUPP);
1828
1829                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1830                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1831                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1832
1833                 prio = &dev->flow_db.sniffer[ft_type];
1834                 priority = 0;
1835                 num_entries = 1;
1836                 num_groups = 1;
1837         }
1838
1839         if (!ns)
1840                 return ERR_PTR(-ENOTSUPP);
1841
1842         ft = prio->flow_table;
1843         if (!ft) {
1844                 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass",
1845                                                          num_entries,
1846                                                          num_groups);
1847
1848                 if (!IS_ERR(ft)) {
1849                         prio->refcount = 0;
1850                         prio->flow_table = ft;
1851                 } else {
1852                         err = PTR_ERR(ft);
1853                 }
1854         }
1855
1856         return err ? ERR_PTR(err) : prio;
1857 }
1858
1859 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1860                                                      struct mlx5_ib_flow_prio *ft_prio,
1861                                                      const struct ib_flow_attr *flow_attr,
1862                                                      struct mlx5_flow_destination *dst)
1863 {
1864         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1865         struct mlx5_ib_flow_handler *handler;
1866         struct mlx5_flow_spec *spec;
1867         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1868         unsigned int spec_index;
1869         u32 action;
1870         int err = 0;
1871
1872         if (!is_valid_attr(flow_attr))
1873                 return ERR_PTR(-EINVAL);
1874
1875         spec = mlx5_vzalloc(sizeof(*spec));
1876         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1877         if (!handler || !spec) {
1878                 err = -ENOMEM;
1879                 goto free;
1880         }
1881
1882         INIT_LIST_HEAD(&handler->list);
1883
1884         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1885                 err = parse_flow_attr(spec->match_criteria,
1886                                       spec->match_value, ib_flow);
1887                 if (err < 0)
1888                         goto free;
1889
1890                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1891         }
1892
1893         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1894         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1895                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1896         handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable,
1897                                            spec->match_criteria,
1898                                            spec->match_value,
1899                                            action,
1900                                            MLX5_FS_DEFAULT_FLOW_TAG,
1901                                            dst);
1902
1903         if (IS_ERR(handler->rule)) {
1904                 err = PTR_ERR(handler->rule);
1905                 goto free;
1906         }
1907
1908         ft_prio->refcount++;
1909         handler->prio = ft_prio;
1910
1911         ft_prio->flow_table = ft;
1912 free:
1913         if (err)
1914                 kfree(handler);
1915         kvfree(spec);
1916         return err ? ERR_PTR(err) : handler;
1917 }
1918
1919 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1920                                                           struct mlx5_ib_flow_prio *ft_prio,
1921                                                           struct ib_flow_attr *flow_attr,
1922                                                           struct mlx5_flow_destination *dst)
1923 {
1924         struct mlx5_ib_flow_handler *handler_dst = NULL;
1925         struct mlx5_ib_flow_handler *handler = NULL;
1926
1927         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1928         if (!IS_ERR(handler)) {
1929                 handler_dst = create_flow_rule(dev, ft_prio,
1930                                                flow_attr, dst);
1931                 if (IS_ERR(handler_dst)) {
1932                         mlx5_del_flow_rule(handler->rule);
1933                         ft_prio->refcount--;
1934                         kfree(handler);
1935                         handler = handler_dst;
1936                 } else {
1937                         list_add(&handler_dst->list, &handler->list);
1938                 }
1939         }
1940
1941         return handler;
1942 }
1943 enum {
1944         LEFTOVERS_MC,
1945         LEFTOVERS_UC,
1946 };
1947
1948 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1949                                                           struct mlx5_ib_flow_prio *ft_prio,
1950                                                           struct ib_flow_attr *flow_attr,
1951                                                           struct mlx5_flow_destination *dst)
1952 {
1953         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1954         struct mlx5_ib_flow_handler *handler = NULL;
1955
1956         static struct {
1957                 struct ib_flow_attr     flow_attr;
1958                 struct ib_flow_spec_eth eth_flow;
1959         } leftovers_specs[] = {
1960                 [LEFTOVERS_MC] = {
1961                         .flow_attr = {
1962                                 .num_of_specs = 1,
1963                                 .size = sizeof(leftovers_specs[0])
1964                         },
1965                         .eth_flow = {
1966                                 .type = IB_FLOW_SPEC_ETH,
1967                                 .size = sizeof(struct ib_flow_spec_eth),
1968                                 .mask = {.dst_mac = {0x1} },
1969                                 .val =  {.dst_mac = {0x1} }
1970                         }
1971                 },
1972                 [LEFTOVERS_UC] = {
1973                         .flow_attr = {
1974                                 .num_of_specs = 1,
1975                                 .size = sizeof(leftovers_specs[0])
1976                         },
1977                         .eth_flow = {
1978                                 .type = IB_FLOW_SPEC_ETH,
1979                                 .size = sizeof(struct ib_flow_spec_eth),
1980                                 .mask = {.dst_mac = {0x1} },
1981                                 .val = {.dst_mac = {} }
1982                         }
1983                 }
1984         };
1985
1986         handler = create_flow_rule(dev, ft_prio,
1987                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1988                                    dst);
1989         if (!IS_ERR(handler) &&
1990             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1991                 handler_ucast = create_flow_rule(dev, ft_prio,
1992                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1993                                                  dst);
1994                 if (IS_ERR(handler_ucast)) {
1995                         mlx5_del_flow_rule(handler->rule);
1996                         ft_prio->refcount--;
1997                         kfree(handler);
1998                         handler = handler_ucast;
1999                 } else {
2000                         list_add(&handler_ucast->list, &handler->list);
2001                 }
2002         }
2003
2004         return handler;
2005 }
2006
2007 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2008                                                         struct mlx5_ib_flow_prio *ft_rx,
2009                                                         struct mlx5_ib_flow_prio *ft_tx,
2010                                                         struct mlx5_flow_destination *dst)
2011 {
2012         struct mlx5_ib_flow_handler *handler_rx;
2013         struct mlx5_ib_flow_handler *handler_tx;
2014         int err;
2015         static const struct ib_flow_attr flow_attr  = {
2016                 .num_of_specs = 0,
2017                 .size = sizeof(flow_attr)
2018         };
2019
2020         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2021         if (IS_ERR(handler_rx)) {
2022                 err = PTR_ERR(handler_rx);
2023                 goto err;
2024         }
2025
2026         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2027         if (IS_ERR(handler_tx)) {
2028                 err = PTR_ERR(handler_tx);
2029                 goto err_tx;
2030         }
2031
2032         list_add(&handler_tx->list, &handler_rx->list);
2033
2034         return handler_rx;
2035
2036 err_tx:
2037         mlx5_del_flow_rule(handler_rx->rule);
2038         ft_rx->refcount--;
2039         kfree(handler_rx);
2040 err:
2041         return ERR_PTR(err);
2042 }
2043
2044 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2045                                            struct ib_flow_attr *flow_attr,
2046                                            int domain)
2047 {
2048         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2049         struct mlx5_ib_qp *mqp = to_mqp(qp);
2050         struct mlx5_ib_flow_handler *handler = NULL;
2051         struct mlx5_flow_destination *dst = NULL;
2052         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2053         struct mlx5_ib_flow_prio *ft_prio;
2054         int err;
2055
2056         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2057                 return ERR_PTR(-ENOSPC);
2058
2059         if (domain != IB_FLOW_DOMAIN_USER ||
2060             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2061             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2062                 return ERR_PTR(-EINVAL);
2063
2064         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2065         if (!dst)
2066                 return ERR_PTR(-ENOMEM);
2067
2068         mutex_lock(&dev->flow_db.lock);
2069
2070         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2071         if (IS_ERR(ft_prio)) {
2072                 err = PTR_ERR(ft_prio);
2073                 goto unlock;
2074         }
2075         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2076                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2077                 if (IS_ERR(ft_prio_tx)) {
2078                         err = PTR_ERR(ft_prio_tx);
2079                         ft_prio_tx = NULL;
2080                         goto destroy_ft;
2081                 }
2082         }
2083
2084         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2085         if (mqp->flags & MLX5_IB_QP_RSS)
2086                 dst->tir_num = mqp->rss_qp.tirn;
2087         else
2088                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2089
2090         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2091                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2092                         handler = create_dont_trap_rule(dev, ft_prio,
2093                                                         flow_attr, dst);
2094                 } else {
2095                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2096                                                    dst);
2097                 }
2098         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2099                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2100                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2101                                                 dst);
2102         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2103                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2104         } else {
2105                 err = -EINVAL;
2106                 goto destroy_ft;
2107         }
2108
2109         if (IS_ERR(handler)) {
2110                 err = PTR_ERR(handler);
2111                 handler = NULL;
2112                 goto destroy_ft;
2113         }
2114
2115         mutex_unlock(&dev->flow_db.lock);
2116         kfree(dst);
2117
2118         return &handler->ibflow;
2119
2120 destroy_ft:
2121         put_flow_table(dev, ft_prio, false);
2122         if (ft_prio_tx)
2123                 put_flow_table(dev, ft_prio_tx, false);
2124 unlock:
2125         mutex_unlock(&dev->flow_db.lock);
2126         kfree(dst);
2127         kfree(handler);
2128         return ERR_PTR(err);
2129 }
2130
2131 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2132 {
2133         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2134         int err;
2135
2136         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2137         if (err)
2138                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2139                              ibqp->qp_num, gid->raw);
2140
2141         return err;
2142 }
2143
2144 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2145 {
2146         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2147         int err;
2148
2149         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2150         if (err)
2151                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2152                              ibqp->qp_num, gid->raw);
2153
2154         return err;
2155 }
2156
2157 static int init_node_data(struct mlx5_ib_dev *dev)
2158 {
2159         int err;
2160
2161         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2162         if (err)
2163                 return err;
2164
2165         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2166 }
2167
2168 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2169                              char *buf)
2170 {
2171         struct mlx5_ib_dev *dev =
2172                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2173
2174         return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2175 }
2176
2177 static ssize_t show_reg_pages(struct device *device,
2178                               struct device_attribute *attr, char *buf)
2179 {
2180         struct mlx5_ib_dev *dev =
2181                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2182
2183         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2184 }
2185
2186 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2187                         char *buf)
2188 {
2189         struct mlx5_ib_dev *dev =
2190                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2191         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2192 }
2193
2194 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2195                         char *buf)
2196 {
2197         struct mlx5_ib_dev *dev =
2198                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2199         return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2200 }
2201
2202 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2203                           char *buf)
2204 {
2205         struct mlx5_ib_dev *dev =
2206                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2207         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2208                        dev->mdev->board_id);
2209 }
2210
2211 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2212 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2213 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2214 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2215 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2216
2217 static struct device_attribute *mlx5_class_attributes[] = {
2218         &dev_attr_hw_rev,
2219         &dev_attr_hca_type,
2220         &dev_attr_board_id,
2221         &dev_attr_fw_pages,
2222         &dev_attr_reg_pages,
2223 };
2224
2225 static void pkey_change_handler(struct work_struct *work)
2226 {
2227         struct mlx5_ib_port_resources *ports =
2228                 container_of(work, struct mlx5_ib_port_resources,
2229                              pkey_change_work);
2230
2231         mutex_lock(&ports->devr->mutex);
2232         mlx5_ib_gsi_pkey_change(ports->gsi);
2233         mutex_unlock(&ports->devr->mutex);
2234 }
2235
2236 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2237 {
2238         struct mlx5_ib_qp *mqp;
2239         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2240         struct mlx5_core_cq *mcq;
2241         struct list_head cq_armed_list;
2242         unsigned long flags_qp;
2243         unsigned long flags_cq;
2244         unsigned long flags;
2245
2246         INIT_LIST_HEAD(&cq_armed_list);
2247
2248         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2249         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2250         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2251                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2252                 if (mqp->sq.tail != mqp->sq.head) {
2253                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2254                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2255                         if (send_mcq->mcq.comp &&
2256                             mqp->ibqp.send_cq->comp_handler) {
2257                                 if (!send_mcq->mcq.reset_notify_added) {
2258                                         send_mcq->mcq.reset_notify_added = 1;
2259                                         list_add_tail(&send_mcq->mcq.reset_notify,
2260                                                       &cq_armed_list);
2261                                 }
2262                         }
2263                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2264                 }
2265                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2266                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2267                 /* no handling is needed for SRQ */
2268                 if (!mqp->ibqp.srq) {
2269                         if (mqp->rq.tail != mqp->rq.head) {
2270                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2271                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2272                                 if (recv_mcq->mcq.comp &&
2273                                     mqp->ibqp.recv_cq->comp_handler) {
2274                                         if (!recv_mcq->mcq.reset_notify_added) {
2275                                                 recv_mcq->mcq.reset_notify_added = 1;
2276                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2277                                                               &cq_armed_list);
2278                                         }
2279                                 }
2280                                 spin_unlock_irqrestore(&recv_mcq->lock,
2281                                                        flags_cq);
2282                         }
2283                 }
2284                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2285         }
2286         /*At that point all inflight post send were put to be executed as of we
2287          * lock/unlock above locks Now need to arm all involved CQs.
2288          */
2289         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2290                 mcq->comp(mcq);
2291         }
2292         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2293 }
2294
2295 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2296                           enum mlx5_dev_event event, unsigned long param)
2297 {
2298         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2299         struct ib_event ibev;
2300         bool fatal = false;
2301         u8 port = 0;
2302
2303         switch (event) {
2304         case MLX5_DEV_EVENT_SYS_ERROR:
2305                 ibev.event = IB_EVENT_DEVICE_FATAL;
2306                 mlx5_ib_handle_internal_error(ibdev);
2307                 fatal = true;
2308                 break;
2309
2310         case MLX5_DEV_EVENT_PORT_UP:
2311         case MLX5_DEV_EVENT_PORT_DOWN:
2312         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2313                 port = (u8)param;
2314
2315                 /* In RoCE, port up/down events are handled in
2316                  * mlx5_netdev_event().
2317                  */
2318                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2319                         IB_LINK_LAYER_ETHERNET)
2320                         return;
2321
2322                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2323                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2324                 break;
2325
2326         case MLX5_DEV_EVENT_LID_CHANGE:
2327                 ibev.event = IB_EVENT_LID_CHANGE;
2328                 port = (u8)param;
2329                 break;
2330
2331         case MLX5_DEV_EVENT_PKEY_CHANGE:
2332                 ibev.event = IB_EVENT_PKEY_CHANGE;
2333                 port = (u8)param;
2334
2335                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2336                 break;
2337
2338         case MLX5_DEV_EVENT_GUID_CHANGE:
2339                 ibev.event = IB_EVENT_GID_CHANGE;
2340                 port = (u8)param;
2341                 break;
2342
2343         case MLX5_DEV_EVENT_CLIENT_REREG:
2344                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2345                 port = (u8)param;
2346                 break;
2347
2348         default:
2349                 break;
2350         }
2351
2352         ibev.device           = &ibdev->ib_dev;
2353         ibev.element.port_num = port;
2354
2355         if (port < 1 || port > ibdev->num_ports) {
2356                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2357                 return;
2358         }
2359
2360         if (ibdev->ib_active)
2361                 ib_dispatch_event(&ibev);
2362
2363         if (fatal)
2364                 ibdev->ib_active = false;
2365 }
2366
2367 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2368 {
2369         int port;
2370
2371         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2372                 mlx5_query_ext_port_caps(dev, port);
2373 }
2374
2375 static int get_port_caps(struct mlx5_ib_dev *dev)
2376 {
2377         struct ib_device_attr *dprops = NULL;
2378         struct ib_port_attr *pprops = NULL;
2379         int err = -ENOMEM;
2380         int port;
2381         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2382
2383         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2384         if (!pprops)
2385                 goto out;
2386
2387         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2388         if (!dprops)
2389                 goto out;
2390
2391         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2392         if (err) {
2393                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2394                 goto out;
2395         }
2396
2397         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2398                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2399                 if (err) {
2400                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2401                                      port, err);
2402                         break;
2403                 }
2404                 dev->mdev->port_caps[port - 1].pkey_table_len =
2405                                                 dprops->max_pkeys;
2406                 dev->mdev->port_caps[port - 1].gid_table_len =
2407                                                 pprops->gid_tbl_len;
2408                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2409                             dprops->max_pkeys, pprops->gid_tbl_len);
2410         }
2411
2412 out:
2413         kfree(pprops);
2414         kfree(dprops);
2415
2416         return err;
2417 }
2418
2419 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2420 {
2421         int err;
2422
2423         err = mlx5_mr_cache_cleanup(dev);
2424         if (err)
2425                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2426
2427         mlx5_ib_destroy_qp(dev->umrc.qp);
2428         ib_free_cq(dev->umrc.cq);
2429         ib_dealloc_pd(dev->umrc.pd);
2430 }
2431
2432 enum {
2433         MAX_UMR_WR = 128,
2434 };
2435
2436 static int create_umr_res(struct mlx5_ib_dev *dev)
2437 {
2438         struct ib_qp_init_attr *init_attr = NULL;
2439         struct ib_qp_attr *attr = NULL;
2440         struct ib_pd *pd;
2441         struct ib_cq *cq;
2442         struct ib_qp *qp;
2443         int ret;
2444
2445         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2446         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2447         if (!attr || !init_attr) {
2448                 ret = -ENOMEM;
2449                 goto error_0;
2450         }
2451
2452         pd = ib_alloc_pd(&dev->ib_dev, 0);
2453         if (IS_ERR(pd)) {
2454                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2455                 ret = PTR_ERR(pd);
2456                 goto error_0;
2457         }
2458
2459         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2460         if (IS_ERR(cq)) {
2461                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2462                 ret = PTR_ERR(cq);
2463                 goto error_2;
2464         }
2465
2466         init_attr->send_cq = cq;
2467         init_attr->recv_cq = cq;
2468         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2469         init_attr->cap.max_send_wr = MAX_UMR_WR;
2470         init_attr->cap.max_send_sge = 1;
2471         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2472         init_attr->port_num = 1;
2473         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2474         if (IS_ERR(qp)) {
2475                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2476                 ret = PTR_ERR(qp);
2477                 goto error_3;
2478         }
2479         qp->device     = &dev->ib_dev;
2480         qp->real_qp    = qp;
2481         qp->uobject    = NULL;
2482         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2483
2484         attr->qp_state = IB_QPS_INIT;
2485         attr->port_num = 1;
2486         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2487                                 IB_QP_PORT, NULL);
2488         if (ret) {
2489                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2490                 goto error_4;
2491         }
2492
2493         memset(attr, 0, sizeof(*attr));
2494         attr->qp_state = IB_QPS_RTR;
2495         attr->path_mtu = IB_MTU_256;
2496
2497         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2498         if (ret) {
2499                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2500                 goto error_4;
2501         }
2502
2503         memset(attr, 0, sizeof(*attr));
2504         attr->qp_state = IB_QPS_RTS;
2505         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2506         if (ret) {
2507                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2508                 goto error_4;
2509         }
2510
2511         dev->umrc.qp = qp;
2512         dev->umrc.cq = cq;
2513         dev->umrc.pd = pd;
2514
2515         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2516         ret = mlx5_mr_cache_init(dev);
2517         if (ret) {
2518                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2519                 goto error_4;
2520         }
2521
2522         kfree(attr);
2523         kfree(init_attr);
2524
2525         return 0;
2526
2527 error_4:
2528         mlx5_ib_destroy_qp(qp);
2529
2530 error_3:
2531         ib_free_cq(cq);
2532
2533 error_2:
2534         ib_dealloc_pd(pd);
2535
2536 error_0:
2537         kfree(attr);
2538         kfree(init_attr);
2539         return ret;
2540 }
2541
2542 static int create_dev_resources(struct mlx5_ib_resources *devr)
2543 {
2544         struct ib_srq_init_attr attr;
2545         struct mlx5_ib_dev *dev;
2546         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2547         int port;
2548         int ret = 0;
2549
2550         dev = container_of(devr, struct mlx5_ib_dev, devr);
2551
2552         mutex_init(&devr->mutex);
2553
2554         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2555         if (IS_ERR(devr->p0)) {
2556                 ret = PTR_ERR(devr->p0);
2557                 goto error0;
2558         }
2559         devr->p0->device  = &dev->ib_dev;
2560         devr->p0->uobject = NULL;
2561         atomic_set(&devr->p0->usecnt, 0);
2562
2563         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2564         if (IS_ERR(devr->c0)) {
2565                 ret = PTR_ERR(devr->c0);
2566                 goto error1;
2567         }
2568         devr->c0->device        = &dev->ib_dev;
2569         devr->c0->uobject       = NULL;
2570         devr->c0->comp_handler  = NULL;
2571         devr->c0->event_handler = NULL;
2572         devr->c0->cq_context    = NULL;
2573         atomic_set(&devr->c0->usecnt, 0);
2574
2575         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2576         if (IS_ERR(devr->x0)) {
2577                 ret = PTR_ERR(devr->x0);
2578                 goto error2;
2579         }
2580         devr->x0->device = &dev->ib_dev;
2581         devr->x0->inode = NULL;
2582         atomic_set(&devr->x0->usecnt, 0);
2583         mutex_init(&devr->x0->tgt_qp_mutex);
2584         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2585
2586         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2587         if (IS_ERR(devr->x1)) {
2588                 ret = PTR_ERR(devr->x1);
2589                 goto error3;
2590         }
2591         devr->x1->device = &dev->ib_dev;
2592         devr->x1->inode = NULL;
2593         atomic_set(&devr->x1->usecnt, 0);
2594         mutex_init(&devr->x1->tgt_qp_mutex);
2595         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2596
2597         memset(&attr, 0, sizeof(attr));
2598         attr.attr.max_sge = 1;
2599         attr.attr.max_wr = 1;
2600         attr.srq_type = IB_SRQT_XRC;
2601         attr.ext.xrc.cq = devr->c0;
2602         attr.ext.xrc.xrcd = devr->x0;
2603
2604         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2605         if (IS_ERR(devr->s0)) {
2606                 ret = PTR_ERR(devr->s0);
2607                 goto error4;
2608         }
2609         devr->s0->device        = &dev->ib_dev;
2610         devr->s0->pd            = devr->p0;
2611         devr->s0->uobject       = NULL;
2612         devr->s0->event_handler = NULL;
2613         devr->s0->srq_context   = NULL;
2614         devr->s0->srq_type      = IB_SRQT_XRC;
2615         devr->s0->ext.xrc.xrcd  = devr->x0;
2616         devr->s0->ext.xrc.cq    = devr->c0;
2617         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2618         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2619         atomic_inc(&devr->p0->usecnt);
2620         atomic_set(&devr->s0->usecnt, 0);
2621
2622         memset(&attr, 0, sizeof(attr));
2623         attr.attr.max_sge = 1;
2624         attr.attr.max_wr = 1;
2625         attr.srq_type = IB_SRQT_BASIC;
2626         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2627         if (IS_ERR(devr->s1)) {
2628                 ret = PTR_ERR(devr->s1);
2629                 goto error5;
2630         }
2631         devr->s1->device        = &dev->ib_dev;
2632         devr->s1->pd            = devr->p0;
2633         devr->s1->uobject       = NULL;
2634         devr->s1->event_handler = NULL;
2635         devr->s1->srq_context   = NULL;
2636         devr->s1->srq_type      = IB_SRQT_BASIC;
2637         devr->s1->ext.xrc.cq    = devr->c0;
2638         atomic_inc(&devr->p0->usecnt);
2639         atomic_set(&devr->s0->usecnt, 0);
2640
2641         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2642                 INIT_WORK(&devr->ports[port].pkey_change_work,
2643                           pkey_change_handler);
2644                 devr->ports[port].devr = devr;
2645         }
2646
2647         return 0;
2648
2649 error5:
2650         mlx5_ib_destroy_srq(devr->s0);
2651 error4:
2652         mlx5_ib_dealloc_xrcd(devr->x1);
2653 error3:
2654         mlx5_ib_dealloc_xrcd(devr->x0);
2655 error2:
2656         mlx5_ib_destroy_cq(devr->c0);
2657 error1:
2658         mlx5_ib_dealloc_pd(devr->p0);
2659 error0:
2660         return ret;
2661 }
2662
2663 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2664 {
2665         struct mlx5_ib_dev *dev =
2666                 container_of(devr, struct mlx5_ib_dev, devr);
2667         int port;
2668
2669         mlx5_ib_destroy_srq(devr->s1);
2670         mlx5_ib_destroy_srq(devr->s0);
2671         mlx5_ib_dealloc_xrcd(devr->x0);
2672         mlx5_ib_dealloc_xrcd(devr->x1);
2673         mlx5_ib_destroy_cq(devr->c0);
2674         mlx5_ib_dealloc_pd(devr->p0);
2675
2676         /* Make sure no change P_Key work items are still executing */
2677         for (port = 0; port < dev->num_ports; ++port)
2678                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2679 }
2680
2681 static u32 get_core_cap_flags(struct ib_device *ibdev)
2682 {
2683         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2684         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2685         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2686         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2687         u32 ret = 0;
2688
2689         if (ll == IB_LINK_LAYER_INFINIBAND)
2690                 return RDMA_CORE_PORT_IBA_IB;
2691
2692         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2693                 return 0;
2694
2695         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2696                 return 0;
2697
2698         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2699                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2700
2701         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2702                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2703
2704         return ret;
2705 }
2706
2707 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2708                                struct ib_port_immutable *immutable)
2709 {
2710         struct ib_port_attr attr;
2711         int err;
2712
2713         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2714         if (err)
2715                 return err;
2716
2717         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2718         immutable->gid_tbl_len = attr.gid_tbl_len;
2719         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2720         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2721
2722         return 0;
2723 }
2724
2725 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2726                            size_t str_len)
2727 {
2728         struct mlx5_ib_dev *dev =
2729                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2730         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2731                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2732 }
2733
2734 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2735 {
2736         return 0;
2737 }
2738
2739 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2740 {
2741 }
2742
2743 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2744 {
2745         if (dev->roce.nb.notifier_call) {
2746                 unregister_netdevice_notifier(&dev->roce.nb);
2747                 dev->roce.nb.notifier_call = NULL;
2748         }
2749 }
2750
2751 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2752 {
2753         VNET_ITERATOR_DECL(vnet_iter);
2754         struct net_device *idev;
2755         int err;
2756
2757         /* Check if mlx5en net device already exists */
2758         VNET_LIST_RLOCK();
2759         VNET_FOREACH(vnet_iter) {
2760                 IFNET_RLOCK();
2761                 CURVNET_SET_QUIET(vnet_iter);
2762                 TAILQ_FOREACH(idev, &V_ifnet, if_link) {
2763                         /* check if network interface belongs to mlx5en */
2764                         if (!mlx5_netdev_match(idev, dev->mdev, "mce"))
2765                                 continue;
2766                         write_lock(&dev->roce.netdev_lock);
2767                         dev->roce.netdev = idev;
2768                         write_unlock(&dev->roce.netdev_lock);
2769                 }
2770                 CURVNET_RESTORE();
2771                 IFNET_RUNLOCK();
2772         }
2773         VNET_LIST_RUNLOCK();
2774
2775         dev->roce.nb.notifier_call = mlx5_netdev_event;
2776         err = register_netdevice_notifier(&dev->roce.nb);
2777         if (err) {
2778                 dev->roce.nb.notifier_call = NULL;
2779                 return err;
2780         }
2781
2782         err = mlx5_nic_vport_enable_roce(dev->mdev);
2783         if (err)
2784                 goto err_unregister_netdevice_notifier;
2785
2786         err = mlx5_roce_lag_init(dev);
2787         if (err)
2788                 goto err_disable_roce;
2789
2790         return 0;
2791
2792 err_disable_roce:
2793         mlx5_nic_vport_disable_roce(dev->mdev);
2794
2795 err_unregister_netdevice_notifier:
2796         mlx5_remove_roce_notifier(dev);
2797         return err;
2798 }
2799
2800 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2801 {
2802         mlx5_roce_lag_cleanup(dev);
2803         mlx5_nic_vport_disable_roce(dev->mdev);
2804 }
2805
2806 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
2807 {
2808         mlx5_vport_dealloc_q_counter(dev->mdev,
2809                                      MLX5_INTERFACE_PROTOCOL_IB,
2810                                      dev->port[port_num].q_cnt_id);
2811         dev->port[port_num].q_cnt_id = 0;
2812 }
2813
2814 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2815 {
2816         unsigned int i;
2817
2818         for (i = 0; i < dev->num_ports; i++)
2819                 mlx5_ib_dealloc_q_port_counter(dev, i);
2820 }
2821
2822 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2823 {
2824         int i;
2825         int ret;
2826
2827         for (i = 0; i < dev->num_ports; i++) {
2828                 ret = mlx5_vport_alloc_q_counter(dev->mdev,
2829                                                  MLX5_INTERFACE_PROTOCOL_IB,
2830                                                  &dev->port[i].q_cnt_id);
2831                 if (ret) {
2832                         mlx5_ib_warn(dev,
2833                                      "couldn't allocate queue counter for port %d, err %d\n",
2834                                      i + 1, ret);
2835                         goto dealloc_counters;
2836                 }
2837         }
2838
2839         return 0;
2840
2841 dealloc_counters:
2842         while (--i >= 0)
2843                 mlx5_ib_dealloc_q_port_counter(dev, i);
2844
2845         return ret;
2846 }
2847
2848 static const char * const names[] = {
2849         "rx_write_requests",
2850         "rx_read_requests",
2851         "rx_atomic_requests",
2852         "out_of_buffer",
2853         "out_of_sequence",
2854         "duplicate_request",
2855         "rnr_nak_retry_err",
2856         "packet_seq_err",
2857         "implied_nak_seq_err",
2858         "local_ack_timeout_err",
2859 };
2860
2861 static const size_t stats_offsets[] = {
2862         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2863         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2864         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2865         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2866         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2867         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2868         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2869         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2870         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2871         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2872 };
2873
2874 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2875                                                     u8 port_num)
2876 {
2877         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2878
2879         /* We support only per port stats */
2880         if (port_num == 0)
2881                 return NULL;
2882
2883         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2884                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2885 }
2886
2887 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2888                                 struct rdma_hw_stats *stats,
2889                                 u8 port, int index)
2890 {
2891         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2892         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2893         void *out;
2894         __be32 val;
2895         int ret;
2896         int i;
2897
2898         if (!port || !stats)
2899                 return -ENOSYS;
2900
2901         out = mlx5_vzalloc(outlen);
2902         if (!out)
2903                 return -ENOMEM;
2904
2905         ret = mlx5_vport_query_q_counter(dev->mdev,
2906                                         dev->port[port - 1].q_cnt_id, 0,
2907                                         out, outlen);
2908         if (ret)
2909                 goto free;
2910
2911         for (i = 0; i < ARRAY_SIZE(names); i++) {
2912                 val = *(__be32 *)(out + stats_offsets[i]);
2913                 stats->value[i] = (u64)be32_to_cpu(val);
2914         }
2915 free:
2916         kvfree(out);
2917         return ARRAY_SIZE(names);
2918 }
2919
2920 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2921 {
2922         struct mlx5_ib_dev *dev;
2923         enum rdma_link_layer ll;
2924         int port_type_cap;
2925         const char *name;
2926         int err;
2927         int i;
2928
2929         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2930         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2931
2932         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2933                 return NULL;
2934
2935         printk_once(KERN_INFO "%s", mlx5_version);
2936
2937         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2938         if (!dev)
2939                 return NULL;
2940
2941         dev->mdev = mdev;
2942
2943         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2944                             GFP_KERNEL);
2945         if (!dev->port)
2946                 goto err_dealloc;
2947
2948         rwlock_init(&dev->roce.netdev_lock);
2949         err = get_port_caps(dev);
2950         if (err)
2951                 goto err_free_port;
2952
2953         if (mlx5_use_mad_ifc(dev))
2954                 get_ext_port_caps(dev);
2955
2956         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2957
2958         name = "mlx5_%d";
2959
2960         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2961         dev->ib_dev.owner               = THIS_MODULE;
2962         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2963         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2964         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2965         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2966         dev->ib_dev.num_comp_vectors    =
2967                 dev->mdev->priv.eq_table.num_comp_vectors;
2968         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2969
2970         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2971         dev->ib_dev.uverbs_cmd_mask     =
2972                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2973                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2974                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2975                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2976                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2977                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2978                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2979                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2980                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2981                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2982                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2983                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2984                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2985                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2986                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2987                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2988                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2989                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2990                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2991                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2992                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2993                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2994                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2995                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2996         dev->ib_dev.uverbs_ex_cmd_mask =
2997                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2998                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2999                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3000
3001         dev->ib_dev.query_device        = mlx5_ib_query_device;
3002         dev->ib_dev.query_port          = mlx5_ib_query_port;
3003         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3004         if (ll == IB_LINK_LAYER_ETHERNET)
3005                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3006         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3007         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3008         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3009         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3010         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3011         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3012         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3013         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3014         dev->ib_dev.mmap                = mlx5_ib_mmap;
3015         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3016         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3017         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3018         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3019         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3020         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3021         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3022         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3023         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3024         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3025         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3026         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3027         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3028         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3029         dev->ib_dev.post_send           = mlx5_ib_post_send;
3030         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3031         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3032         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3033         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3034         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3035         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3036         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3037         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3038         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3039         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3040         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3041         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3042         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3043         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3044         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3045         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3046         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3047         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3048         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3049         if (mlx5_core_is_pf(mdev)) {
3050                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3051                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3052                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3053                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3054         }
3055
3056         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3057
3058         mlx5_ib_internal_fill_odp_caps(dev);
3059
3060         if (MLX5_CAP_GEN(mdev, imaicl)) {
3061                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3062                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3063                 dev->ib_dev.uverbs_cmd_mask |=
3064                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3065                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3066         }
3067
3068         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3069             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3070                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3071                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3072         }
3073
3074         if (MLX5_CAP_GEN(mdev, xrc)) {
3075                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3076                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3077                 dev->ib_dev.uverbs_cmd_mask |=
3078                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3079                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3080         }
3081
3082         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3083             IB_LINK_LAYER_ETHERNET) {
3084                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3085                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3086                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3087                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3088                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3089                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3090                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3091                 dev->ib_dev.uverbs_ex_cmd_mask |=
3092                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3093                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3094                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3095                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3096                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3097                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3098                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3099         }
3100         err = init_node_data(dev);
3101         if (err)
3102                 goto err_free_port;
3103
3104         mutex_init(&dev->flow_db.lock);
3105         mutex_init(&dev->cap_mask_mutex);
3106         INIT_LIST_HEAD(&dev->qp_list);
3107         spin_lock_init(&dev->reset_flow_resource_lock);
3108
3109         if (ll == IB_LINK_LAYER_ETHERNET) {
3110                 err = mlx5_enable_roce(dev);
3111                 if (err)
3112                         goto err_free_port;
3113         }
3114
3115         err = create_dev_resources(&dev->devr);
3116         if (err)
3117                 goto err_disable_roce;
3118
3119         err = mlx5_ib_odp_init_one(dev);
3120         if (err)
3121                 goto err_rsrc;
3122
3123         err = mlx5_ib_alloc_q_counters(dev);
3124         if (err)
3125                 goto err_odp;
3126
3127         err = ib_register_device(&dev->ib_dev, NULL);
3128         if (err)
3129                 goto err_q_cnt;
3130
3131         err = create_umr_res(dev);
3132         if (err)
3133                 goto err_dev;
3134
3135         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3136                 err = device_create_file(&dev->ib_dev.dev,
3137                                          mlx5_class_attributes[i]);
3138                 if (err)
3139                         goto err_umrc;
3140         }
3141
3142         dev->ib_active = true;
3143
3144         return dev;
3145
3146 err_umrc:
3147         destroy_umrc_res(dev);
3148
3149 err_dev:
3150         ib_unregister_device(&dev->ib_dev);
3151
3152 err_q_cnt:
3153         mlx5_ib_dealloc_q_counters(dev);
3154
3155 err_odp:
3156         mlx5_ib_odp_remove_one(dev);
3157
3158 err_rsrc:
3159         destroy_dev_resources(&dev->devr);
3160
3161 err_disable_roce:
3162         if (ll == IB_LINK_LAYER_ETHERNET) {
3163                 mlx5_disable_roce(dev);
3164                 mlx5_remove_roce_notifier(dev);
3165         }
3166
3167 err_free_port:
3168         kfree(dev->port);
3169
3170 err_dealloc:
3171         ib_dealloc_device((struct ib_device *)dev);
3172
3173         return NULL;
3174 }
3175
3176 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3177 {
3178         struct mlx5_ib_dev *dev = context;
3179         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3180
3181         mlx5_remove_roce_notifier(dev);
3182         ib_unregister_device(&dev->ib_dev);
3183         mlx5_ib_dealloc_q_counters(dev);
3184         destroy_umrc_res(dev);
3185         mlx5_ib_odp_remove_one(dev);
3186         destroy_dev_resources(&dev->devr);
3187         if (ll == IB_LINK_LAYER_ETHERNET)
3188                 mlx5_disable_roce(dev);
3189         kfree(dev->port);
3190         ib_dealloc_device(&dev->ib_dev);
3191 }
3192
3193 static struct mlx5_interface mlx5_ib_interface = {
3194         .add            = mlx5_ib_add,
3195         .remove         = mlx5_ib_remove,
3196         .event          = mlx5_ib_event,
3197         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3198 };
3199
3200 static int __init mlx5_ib_init(void)
3201 {
3202         int err;
3203
3204         if (deprecated_prof_sel != 2)
3205                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3206
3207         err = mlx5_ib_odp_init();
3208         if (err)
3209                 return err;
3210
3211         err = mlx5_register_interface(&mlx5_ib_interface);
3212         if (err)
3213                 goto clean_odp;
3214
3215         return err;
3216
3217 clean_odp:
3218         mlx5_ib_odp_cleanup();
3219         return err;
3220 }
3221
3222 static void __exit mlx5_ib_cleanup(void)
3223 {
3224         mlx5_unregister_interface(&mlx5_ib_interface);
3225         mlx5_ib_odp_cleanup();
3226 }
3227
3228 module_init_order(mlx5_ib_init, SI_ORDER_THIRD);
3229 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD);