sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/errno.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #if defined(CONFIG_X86)
  34 #include <asm/pat.h>
  35 #endif
  36 #include <linux/sched.h>
  37 #include <linux/delay.h>
  38 #include <linux/fs.h>
  39 #undef inode
  40 #include <rdma/ib_user_verbs.h>
  41 #include <rdma/ib_addr.h>
  42 #include <rdma/ib_cache.h>
  43 #include <dev/mlx5/port.h>
  44 #include <dev/mlx5/vport.h>
  45 #include <linux/list.h>
  46 #include <rdma/ib_smi.h>
  47 #include <rdma/ib_umem.h>
  48 #include <linux/in.h>
  49 #include <linux/etherdevice.h>
  50 #include <dev/mlx5/fs.h>
  51 #include "mlx5_ib.h"
  52
  53 #define DRIVER_NAME "mlx5_ib"
  54 #define DRIVER_VERSION "3.4.1-BETA"
  55 #define DRIVER_RELDATE  "October 2017"
  56
  57 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  58 MODULE_LICENSE("Dual BSD/GPL");
  59 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
  60 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
  61 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
  62 MODULE_VERSION(mlx5ib, 1);
  63
  64 static int deprecated_prof_sel = 2;
  65 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  66 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  67
  68 static char mlx5_version[] =
  69         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  70         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  71
  72 enum {
  73         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  74 };
  75
  76 static enum rdma_link_layer
  77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  78 {
  79         switch (port_type_cap) {
  80         case MLX5_CAP_PORT_TYPE_IB:
  81                 return IB_LINK_LAYER_INFINIBAND;
  82         case MLX5_CAP_PORT_TYPE_ETH:
  83                 return IB_LINK_LAYER_ETHERNET;
  84         default:
  85                 return IB_LINK_LAYER_UNSPECIFIED;
  86         }
  87 }
  88
  89 static enum rdma_link_layer
  90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  91 {
  92         struct mlx5_ib_dev *dev = to_mdev(device);
  93         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  94
  95         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  96 }
  97
  98 static bool mlx5_netdev_match(struct net_device *ndev,
  99                               struct mlx5_core_dev *mdev,
 100                               const char *dname)
 101 {
 102         return ndev->if_type == IFT_ETHER &&
 103           ndev->if_dname != NULL &&
 104           strcmp(ndev->if_dname, dname) == 0 &&
 105           ndev->if_softc != NULL &&
 106           *(struct mlx5_core_dev **)ndev->if_softc == mdev;
 107 }
 108
 109 static int mlx5_netdev_event(struct notifier_block *this,
 110                              unsigned long event, void *ptr)
 111 {
 112         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 113         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 114                                                  roce.nb);
 115
 116         switch (event) {
 117         case NETDEV_REGISTER:
 118         case NETDEV_UNREGISTER:
 119                 write_lock(&ibdev->roce.netdev_lock);
 120                 /* check if network interface belongs to mlx5en */
 121                 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
 122                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 123                                              NULL : ndev;
 124                 write_unlock(&ibdev->roce.netdev_lock);
 125                 break;
 126
 127         case NETDEV_UP:
 128         case NETDEV_DOWN: {
 129                 struct net_device *upper = NULL;
 130
 131                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 132                     && ibdev->ib_active) {
 133                         struct ib_event ibev = {0};
 134
 135                         ibev.device = &ibdev->ib_dev;
 136                         ibev.event = (event == NETDEV_UP) ?
 137                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 138                         ibev.element.port_num = 1;
 139                         ib_dispatch_event(&ibev);
 140                 }
 141                 break;
 142         }
 143
 144         default:
 145                 break;
 146         }
 147
 148         return NOTIFY_DONE;
 149 }
 150
 151 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 152                                              u8 port_num)
 153 {
 154         struct mlx5_ib_dev *ibdev = to_mdev(device);
 155         struct net_device *ndev;
 156
 157         /* Ensure ndev does not disappear before we invoke dev_hold()
 158          */
 159         read_lock(&ibdev->roce.netdev_lock);
 160         ndev = ibdev->roce.netdev;
 161         if (ndev)
 162                 dev_hold(ndev);
 163         read_unlock(&ibdev->roce.netdev_lock);
 164
 165         return ndev;
 166 }
 167
 168 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 169                                 struct ib_port_attr *props)
 170 {
 171         struct mlx5_ib_dev *dev = to_mdev(device);
 172         struct net_device *ndev;
 173         enum ib_mtu ndev_ib_mtu;
 174         u16 qkey_viol_cntr;
 175
 176         memset(props, 0, sizeof(*props));
 177
 178         props->port_cap_flags  |= IB_PORT_CM_SUP;
 179         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 180
 181         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 182                                                 roce_address_table_size);
 183         props->max_mtu          = IB_MTU_4096;
 184         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 185         props->pkey_tbl_len     = 1;
 186         props->state            = IB_PORT_DOWN;
 187         props->phys_state       = 3;
 188
 189         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 190         props->qkey_viol_cntr = qkey_viol_cntr;
 191
 192         ndev = mlx5_ib_get_netdev(device, port_num);
 193         if (!ndev)
 194                 return 0;
 195
 196         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 197                 props->state      = IB_PORT_ACTIVE;
 198                 props->phys_state = 5;
 199         }
 200
 201         ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu);
 202
 203         dev_put(ndev);
 204
 205         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 206
 207         props->active_width     = IB_WIDTH_4X;  /* TODO */
 208         props->active_speed     = IB_SPEED_QDR; /* TODO */
 209
 210         return 0;
 211 }
 212
 213 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 214                                      const struct ib_gid_attr *attr,
 215                                      void *mlx5_addr)
 216 {
 217 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 218         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 219                                                source_l3_address);
 220         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 221                                                source_mac_47_32);
 222
 223         if (!gid)
 224                 return;
 225         ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev));
 226
 227         if (is_vlan_dev(attr->ndev)) {
 228                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 229                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 230         }
 231
 232         switch (attr->gid_type) {
 233         case IB_GID_TYPE_IB:
 234                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 235                 break;
 236         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 237                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 238                 break;
 239
 240         default:
 241                 WARN_ON(true);
 242         }
 243
 244         if (attr->gid_type != IB_GID_TYPE_IB) {
 245                 if (ipv6_addr_v4mapped((void *)gid))
 246                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 247                                     MLX5_ROCE_L3_TYPE_IPV4);
 248                 else
 249                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 250                                     MLX5_ROCE_L3_TYPE_IPV6);
 251         }
 252
 253         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 254             !ipv6_addr_v4mapped((void *)gid))
 255                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 256         else
 257                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 258 }
 259
 260 static int set_roce_addr(struct ib_device *device, u8 port_num,
 261                          unsigned int index,
 262                          const union ib_gid *gid,
 263                          const struct ib_gid_attr *attr)
 264 {
 265         struct mlx5_ib_dev *dev = to_mdev(device);
 266         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 267         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 268         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 269         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 270
 271         if (ll != IB_LINK_LAYER_ETHERNET)
 272                 return -EINVAL;
 273
 274         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 275
 276         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 277         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 278         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 279 }
 280
 281 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 282                            unsigned int index, const union ib_gid *gid,
 283                            const struct ib_gid_attr *attr,
 284                            __always_unused void **context)
 285 {
 286         return set_roce_addr(device, port_num, index, gid, attr);
 287 }
 288
 289 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 290                            unsigned int index, __always_unused void **context)
 291 {
 292         return set_roce_addr(device, port_num, index, NULL, NULL);
 293 }
 294
 295 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 296                                int index)
 297 {
 298         struct ib_gid_attr attr;
 299         union ib_gid gid;
 300
 301         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 302                 return 0;
 303
 304         if (!attr.ndev)
 305                 return 0;
 306
 307         dev_put(attr.ndev);
 308
 309         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 310                 return 0;
 311
 312         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 313 }
 314
 315 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 316 {
 317         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 318                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 319         return 0;
 320 }
 321
 322 enum {
 323         MLX5_VPORT_ACCESS_METHOD_MAD,
 324         MLX5_VPORT_ACCESS_METHOD_HCA,
 325         MLX5_VPORT_ACCESS_METHOD_NIC,
 326 };
 327
 328 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 329 {
 330         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 331                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 332
 333         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 334             IB_LINK_LAYER_ETHERNET)
 335                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 336
 337         return MLX5_VPORT_ACCESS_METHOD_HCA;
 338 }
 339
 340 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 341                             struct ib_device_attr *props)
 342 {
 343         u8 tmp;
 344         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 345         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 346         u8 atomic_req_8B_endianness_mode =
 347                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 348
 349         /* Check if HW supports 8 bytes standard atomic operations and capable
 350          * of host endianness respond
 351          */
 352         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 353         if (((atomic_operations & tmp) == tmp) &&
 354             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 355             (atomic_req_8B_endianness_mode)) {
 356                 props->atomic_cap = IB_ATOMIC_HCA;
 357         } else {
 358                 props->atomic_cap = IB_ATOMIC_NONE;
 359         }
 360 }
 361
 362 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 363                                         __be64 *sys_image_guid)
 364 {
 365         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 366         struct mlx5_core_dev *mdev = dev->mdev;
 367         u64 tmp;
 368         int err;
 369
 370         switch (mlx5_get_vport_access_method(ibdev)) {
 371         case MLX5_VPORT_ACCESS_METHOD_MAD:
 372                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 373                                                             sys_image_guid);
 374
 375         case MLX5_VPORT_ACCESS_METHOD_HCA:
 376                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 377                 break;
 378
 379         case MLX5_VPORT_ACCESS_METHOD_NIC:
 380                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 381                 break;
 382
 383         default:
 384                 return -EINVAL;
 385         }
 386
 387         if (!err)
 388                 *sys_image_guid = cpu_to_be64(tmp);
 389
 390         return err;
 391
 392 }
 393
 394 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 395                                 u16 *max_pkeys)
 396 {
 397         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 398         struct mlx5_core_dev *mdev = dev->mdev;
 399
 400         switch (mlx5_get_vport_access_method(ibdev)) {
 401         case MLX5_VPORT_ACCESS_METHOD_MAD:
 402                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 403
 404         case MLX5_VPORT_ACCESS_METHOD_HCA:
 405         case MLX5_VPORT_ACCESS_METHOD_NIC:
 406                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 407                                                 pkey_table_size));
 408                 return 0;
 409
 410         default:
 411                 return -EINVAL;
 412         }
 413 }
 414
 415 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 416                                 u32 *vendor_id)
 417 {
 418         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 419
 420         switch (mlx5_get_vport_access_method(ibdev)) {
 421         case MLX5_VPORT_ACCESS_METHOD_MAD:
 422                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 423
 424         case MLX5_VPORT_ACCESS_METHOD_HCA:
 425         case MLX5_VPORT_ACCESS_METHOD_NIC:
 426                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 427
 428         default:
 429                 return -EINVAL;
 430         }
 431 }
 432
 433 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 434                                 __be64 *node_guid)
 435 {
 436         u64 tmp;
 437         int err;
 438
 439         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 440         case MLX5_VPORT_ACCESS_METHOD_MAD:
 441                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 442
 443         case MLX5_VPORT_ACCESS_METHOD_HCA:
 444                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 445                 break;
 446
 447         case MLX5_VPORT_ACCESS_METHOD_NIC:
 448                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 449                 break;
 450
 451         default:
 452                 return -EINVAL;
 453         }
 454
 455         if (!err)
 456                 *node_guid = cpu_to_be64(tmp);
 457
 458         return err;
 459 }
 460
 461 struct mlx5_reg_node_desc {
 462         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 463 };
 464
 465 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 466 {
 467         struct mlx5_reg_node_desc in;
 468
 469         if (mlx5_use_mad_ifc(dev))
 470                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 471
 472         memset(&in, 0, sizeof(in));
 473
 474         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 475                                     sizeof(struct mlx5_reg_node_desc),
 476                                     MLX5_REG_NODE_DESC, 0, 0);
 477 }
 478
 479 static int mlx5_ib_query_device(struct ib_device *ibdev,
 480                                 struct ib_device_attr *props,
 481                                 struct ib_udata *uhw)
 482 {
 483         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 484         struct mlx5_core_dev *mdev = dev->mdev;
 485         int err = -ENOMEM;
 486         int max_rq_sg;
 487         int max_sq_sg;
 488         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 489         struct mlx5_ib_query_device_resp resp = {};
 490         size_t resp_len;
 491         u64 max_tso;
 492
 493         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 494         if (uhw->outlen && uhw->outlen < resp_len)
 495                 return -EINVAL;
 496         else
 497                 resp.response_length = resp_len;
 498
 499         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 500                 return -EINVAL;
 501
 502         memset(props, 0, sizeof(*props));
 503         err = mlx5_query_system_image_guid(ibdev,
 504                                            &props->sys_image_guid);
 505         if (err)
 506                 return err;
 507
 508         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 509         if (err)
 510                 return err;
 511
 512         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 513         if (err)
 514                 return err;
 515
 516         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 517                 (fw_rev_min(dev->mdev) << 16) |
 518                 fw_rev_sub(dev->mdev);
 519         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 520                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 521                 IB_DEVICE_SYS_IMAGE_GUID                |
 522                 IB_DEVICE_RC_RNR_NAK_GEN;
 523
 524         if (MLX5_CAP_GEN(mdev, pkv))
 525                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 526         if (MLX5_CAP_GEN(mdev, qkv))
 527                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 528         if (MLX5_CAP_GEN(mdev, apm))
 529                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 530         if (MLX5_CAP_GEN(mdev, xrc))
 531                 props->device_cap_flags |= IB_DEVICE_XRC;
 532         if (MLX5_CAP_GEN(mdev, imaicl)) {
 533                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 534                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 535                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 536                 /* We support 'Gappy' memory registration too */
 537                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 538         }
 539         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 540         if (MLX5_CAP_GEN(mdev, sho)) {
 541                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 542                 /* At this stage no support for signature handover */
 543                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 544                                       IB_PROT_T10DIF_TYPE_2 |
 545                                       IB_PROT_T10DIF_TYPE_3;
 546                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 547                                        IB_GUARD_T10DIF_CSUM;
 548         }
 549         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 550                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 551
 552         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 553                 if (MLX5_CAP_ETH(mdev, csum_cap))
 554                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 555
 556                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 557                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 558                         if (max_tso) {
 559                                 resp.tso_caps.max_tso = 1 << max_tso;
 560                                 resp.tso_caps.supported_qpts |=
 561                                         1 << IB_QPT_RAW_PACKET;
 562                                 resp.response_length += sizeof(resp.tso_caps);
 563                         }
 564                 }
 565
 566                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 567                         resp.rss_caps.rx_hash_function =
 568                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 569                         resp.rss_caps.rx_hash_fields_mask =
 570                                                 MLX5_RX_HASH_SRC_IPV4 |
 571                                                 MLX5_RX_HASH_DST_IPV4 |
 572                                                 MLX5_RX_HASH_SRC_IPV6 |
 573                                                 MLX5_RX_HASH_DST_IPV6 |
 574                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 575                                                 MLX5_RX_HASH_DST_PORT_TCP |
 576                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 577                                                 MLX5_RX_HASH_DST_PORT_UDP;
 578                         resp.response_length += sizeof(resp.rss_caps);
 579                 }
 580         } else {
 581                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 582                         resp.response_length += sizeof(resp.tso_caps);
 583                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 584                         resp.response_length += sizeof(resp.rss_caps);
 585         }
 586
 587         if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
 588                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 589                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 590         }
 591
 592         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 593             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 594                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 595
 596         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 597                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 598
 599         props->vendor_part_id      = mdev->pdev->device;
 600         props->hw_ver              = mdev->pdev->revision;
 601
 602         props->max_mr_size         = ~0ull;
 603         props->page_size_cap       = ~(min_page_size - 1);
 604         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 605         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 606         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 607                      sizeof(struct mlx5_wqe_data_seg);
 608         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 609                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 610                      sizeof(struct mlx5_wqe_data_seg);
 611         props->max_sge = min(max_rq_sg, max_sq_sg);
 612         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 613         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 614         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 615         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 616         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 617         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 618         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 619         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 620         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 621         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 622         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 623         props->max_srq_sge         = max_rq_sg - 1;
 624         props->max_fast_reg_page_list_len =
 625                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 626         get_atomic_caps(dev, props);
 627         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 628         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 629         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 630         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 631                                            props->max_mcast_grp;
 632         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 633         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 634         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 635
 636 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 637         if (MLX5_CAP_GEN(mdev, pg))
 638                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 639         props->odp_caps = dev->odp_caps;
 640 #endif
 641
 642         if (MLX5_CAP_GEN(mdev, cd))
 643                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 644
 645         if (!mlx5_core_is_pf(mdev))
 646                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 647
 648         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 649             IB_LINK_LAYER_ETHERNET) {
 650                 props->rss_caps.max_rwq_indirection_tables =
 651                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 652                 props->rss_caps.max_rwq_indirection_table_size =
 653                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 654                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 655                 props->max_wq_type_rq =
 656                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 657         }
 658
 659         if (uhw->outlen) {
 660                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 661
 662                 if (err)
 663                         return err;
 664         }
 665
 666         return 0;
 667 }
 668
 669 enum mlx5_ib_width {
 670         MLX5_IB_WIDTH_1X        = 1 << 0,
 671         MLX5_IB_WIDTH_2X        = 1 << 1,
 672         MLX5_IB_WIDTH_4X        = 1 << 2,
 673         MLX5_IB_WIDTH_8X        = 1 << 3,
 674         MLX5_IB_WIDTH_12X       = 1 << 4
 675 };
 676
 677 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 678                                   u8 *ib_width)
 679 {
 680         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 681         int err = 0;
 682
 683         if (active_width & MLX5_IB_WIDTH_1X) {
 684                 *ib_width = IB_WIDTH_1X;
 685         } else if (active_width & MLX5_IB_WIDTH_2X) {
 686                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 687                             (int)active_width);
 688                 err = -EINVAL;
 689         } else if (active_width & MLX5_IB_WIDTH_4X) {
 690                 *ib_width = IB_WIDTH_4X;
 691         } else if (active_width & MLX5_IB_WIDTH_8X) {
 692                 *ib_width = IB_WIDTH_8X;
 693         } else if (active_width & MLX5_IB_WIDTH_12X) {
 694                 *ib_width = IB_WIDTH_12X;
 695         } else {
 696                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 697                             (int)active_width);
 698                 err = -EINVAL;
 699         }
 700
 701         return err;
 702 }
 703
 704 enum ib_max_vl_num {
 705         __IB_MAX_VL_0           = 1,
 706         __IB_MAX_VL_0_1         = 2,
 707         __IB_MAX_VL_0_3         = 3,
 708         __IB_MAX_VL_0_7         = 4,
 709         __IB_MAX_VL_0_14        = 5,
 710 };
 711
 712 enum mlx5_vl_hw_cap {
 713         MLX5_VL_HW_0    = 1,
 714         MLX5_VL_HW_0_1  = 2,
 715         MLX5_VL_HW_0_2  = 3,
 716         MLX5_VL_HW_0_3  = 4,
 717         MLX5_VL_HW_0_4  = 5,
 718         MLX5_VL_HW_0_5  = 6,
 719         MLX5_VL_HW_0_6  = 7,
 720         MLX5_VL_HW_0_7  = 8,
 721         MLX5_VL_HW_0_14 = 15
 722 };
 723
 724 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 725                                 u8 *max_vl_num)
 726 {
 727         switch (vl_hw_cap) {
 728         case MLX5_VL_HW_0:
 729                 *max_vl_num = __IB_MAX_VL_0;
 730                 break;
 731         case MLX5_VL_HW_0_1:
 732                 *max_vl_num = __IB_MAX_VL_0_1;
 733                 break;
 734         case MLX5_VL_HW_0_3:
 735                 *max_vl_num = __IB_MAX_VL_0_3;
 736                 break;
 737         case MLX5_VL_HW_0_7:
 738                 *max_vl_num = __IB_MAX_VL_0_7;
 739                 break;
 740         case MLX5_VL_HW_0_14:
 741                 *max_vl_num = __IB_MAX_VL_0_14;
 742                 break;
 743
 744         default:
 745                 return -EINVAL;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 752                                struct ib_port_attr *props)
 753 {
 754         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 755         struct mlx5_core_dev *mdev = dev->mdev;
 756         u32 *rep;
 757         int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
 758         struct mlx5_ptys_reg *ptys;
 759         struct mlx5_pmtu_reg *pmtu;
 760         struct mlx5_pvlc_reg pvlc;
 761         void *ctx;
 762         int err;
 763
 764         rep = mlx5_vzalloc(replen);
 765         ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
 766         pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
 767         if (!rep || !ptys || !pmtu) {
 768                 err = -ENOMEM;
 769                 goto out;
 770         }
 771
 772         memset(props, 0, sizeof(*props));
 773
 774         err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
 775         if (err)
 776                 goto out;
 777
 778         ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
 779
 780         props->lid              = MLX5_GET(hca_vport_context, ctx, lid);
 781         props->lmc              = MLX5_GET(hca_vport_context, ctx, lmc);
 782         props->sm_lid           = MLX5_GET(hca_vport_context, ctx, sm_lid);
 783         props->sm_sl            = MLX5_GET(hca_vport_context, ctx, sm_sl);
 784         props->state            = MLX5_GET(hca_vport_context, ctx, vport_state);
 785         props->phys_state       = MLX5_GET(hca_vport_context, ctx,
 786                                         port_physical_state);
 787         props->port_cap_flags   = MLX5_GET(hca_vport_context, ctx, cap_mask1);
 788         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 789         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 790         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 791         props->bad_pkey_cntr    = MLX5_GET(hca_vport_context, ctx,
 792                                         pkey_violation_counter);
 793         props->qkey_viol_cntr   = MLX5_GET(hca_vport_context, ctx,
 794                                         qkey_violation_counter);
 795         props->subnet_timeout   = MLX5_GET(hca_vport_context, ctx,
 796                                         subnet_timeout);
 797         props->init_type_reply  = MLX5_GET(hca_vport_context, ctx,
 798                                         init_type_reply);
 799         props->grh_required     = MLX5_GET(hca_vport_context, ctx, grh_required);
 800
 801         ptys->proto_mask |= MLX5_PTYS_IB;
 802         ptys->local_port = port;
 803         err = mlx5_core_access_ptys(mdev, ptys, 0);
 804         if (err)
 805                 goto out;
 806
 807         err = translate_active_width(ibdev, ptys->ib_link_width_oper,
 808                                      &props->active_width);
 809         if (err)
 810                 goto out;
 811
 812         props->active_speed     = (u8)ptys->ib_proto_oper;
 813
 814         pmtu->local_port = port;
 815         err = mlx5_core_access_pmtu(mdev, pmtu, 0);
 816         if (err)
 817                 goto out;
 818
 819         props->max_mtu          = pmtu->max_mtu;
 820         props->active_mtu       = pmtu->oper_mtu;
 821
 822         memset(&pvlc, 0, sizeof(pvlc));
 823         pvlc.local_port = port;
 824         err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
 825         if (err)
 826                 goto out;
 827
 828         err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
 829                                    &props->max_vl_num);
 830 out:
 831         kvfree(rep);
 832         kfree(ptys);
 833         kfree(pmtu);
 834         return err;
 835 }
 836
 837 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 838                        struct ib_port_attr *props)
 839 {
 840         switch (mlx5_get_vport_access_method(ibdev)) {
 841         case MLX5_VPORT_ACCESS_METHOD_MAD:
 842                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 843
 844         case MLX5_VPORT_ACCESS_METHOD_HCA:
 845                 return mlx5_query_hca_port(ibdev, port, props);
 846
 847         case MLX5_VPORT_ACCESS_METHOD_NIC:
 848                 return mlx5_query_port_roce(ibdev, port, props);
 849
 850         default:
 851                 return -EINVAL;
 852         }
 853 }
 854
 855 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 856                              union ib_gid *gid)
 857 {
 858         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 859         struct mlx5_core_dev *mdev = dev->mdev;
 860
 861         switch (mlx5_get_vport_access_method(ibdev)) {
 862         case MLX5_VPORT_ACCESS_METHOD_MAD:
 863                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 864
 865         case MLX5_VPORT_ACCESS_METHOD_HCA:
 866                 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
 867
 868         default:
 869                 return -EINVAL;
 870         }
 871
 872 }
 873
 874 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 875                               u16 *pkey)
 876 {
 877         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 878         struct mlx5_core_dev *mdev = dev->mdev;
 879
 880         switch (mlx5_get_vport_access_method(ibdev)) {
 881         case MLX5_VPORT_ACCESS_METHOD_MAD:
 882                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 883
 884         case MLX5_VPORT_ACCESS_METHOD_HCA:
 885         case MLX5_VPORT_ACCESS_METHOD_NIC:
 886                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 887                                                  pkey);
 888         default:
 889                 return -EINVAL;
 890         }
 891 }
 892
 893 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 894                                  struct ib_device_modify *props)
 895 {
 896         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 897         struct mlx5_reg_node_desc in;
 898         struct mlx5_reg_node_desc out;
 899         int err;
 900
 901         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 902                 return -EOPNOTSUPP;
 903
 904         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 905                 return 0;
 906
 907         /*
 908          * If possible, pass node desc to FW, so it can generate
 909          * a 144 trap.  If cmd fails, just ignore.
 910          */
 911         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 912         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 913                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 914         if (err)
 915                 return err;
 916
 917         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 918
 919         return err;
 920 }
 921
 922 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 923                                struct ib_port_modify *props)
 924 {
 925         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 926         struct ib_port_attr attr;
 927         u32 tmp;
 928         int err;
 929
 930         mutex_lock(&dev->cap_mask_mutex);
 931
 932         err = mlx5_ib_query_port(ibdev, port, &attr);
 933         if (err)
 934                 goto out;
 935
 936         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 937                 ~props->clr_port_cap_mask;
 938
 939         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 940
 941 out:
 942         mutex_unlock(&dev->cap_mask_mutex);
 943         return err;
 944 }
 945
 946 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 947                                                   struct ib_udata *udata)
 948 {
 949         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 950         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 951         struct mlx5_ib_alloc_ucontext_resp resp = {};
 952         struct mlx5_ib_ucontext *context;
 953         struct mlx5_uuar_info *uuari;
 954         struct mlx5_uar *uars;
 955         int gross_uuars;
 956         int num_uars;
 957         int ver;
 958         int uuarn;
 959         int err;
 960         int i;
 961         size_t reqlen;
 962         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 963                                      max_cqe_version);
 964
 965         if (!dev->ib_active)
 966                 return ERR_PTR(-EAGAIN);
 967
 968         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 969                 return ERR_PTR(-EINVAL);
 970
 971         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 972         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 973                 ver = 0;
 974         else if (reqlen >= min_req_v2)
 975                 ver = 2;
 976         else
 977                 return ERR_PTR(-EINVAL);
 978
 979         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 980         if (err)
 981                 return ERR_PTR(err);
 982
 983         if (req.flags)
 984                 return ERR_PTR(-EINVAL);
 985
 986         if (req.total_num_uuars > MLX5_MAX_UUARS)
 987                 return ERR_PTR(-ENOMEM);
 988
 989         if (req.total_num_uuars == 0)
 990                 return ERR_PTR(-EINVAL);
 991
 992         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 993                 return ERR_PTR(-EOPNOTSUPP);
 994
 995         if (reqlen > sizeof(req) &&
 996             !ib_is_udata_cleared(udata, sizeof(req),
 997                                  reqlen - sizeof(req)))
 998                 return ERR_PTR(-EOPNOTSUPP);
 999
1000         req.total_num_uuars = ALIGN(req.total_num_uuars,
1001                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1002         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1003                 return ERR_PTR(-EINVAL);
1004
1005         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1006         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1007         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1008         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1009                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1010         resp.cache_line_size = cache_line_size();
1011         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1012         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1013         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1014         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1015         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1016         resp.cqe_version = min_t(__u8,
1017                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1018                                  req.max_cqe_version);
1019         resp.response_length = min(offsetof(typeof(resp), response_length) +
1020                                    sizeof(resp.response_length), udata->outlen);
1021
1022         context = kzalloc(sizeof(*context), GFP_KERNEL);
1023         if (!context)
1024                 return ERR_PTR(-ENOMEM);
1025
1026         uuari = &context->uuari;
1027         mutex_init(&uuari->lock);
1028         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1029         if (!uars) {
1030                 err = -ENOMEM;
1031                 goto out_ctx;
1032         }
1033
1034         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1035                                 sizeof(*uuari->bitmap),
1036                                 GFP_KERNEL);
1037         if (!uuari->bitmap) {
1038                 err = -ENOMEM;
1039                 goto out_uar_ctx;
1040         }
1041         /*
1042          * clear all fast path uuars
1043          */
1044         for (i = 0; i < gross_uuars; i++) {
1045                 uuarn = i & 3;
1046                 if (uuarn == 2 || uuarn == 3)
1047                         set_bit(i, uuari->bitmap);
1048         }
1049
1050         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1051         if (!uuari->count) {
1052                 err = -ENOMEM;
1053                 goto out_bitmap;
1054         }
1055
1056         for (i = 0; i < num_uars; i++) {
1057                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1058                 if (err)
1059                         goto out_count;
1060         }
1061
1062 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1063         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1064 #endif
1065
1066         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1067                 err = mlx5_alloc_transport_domain(dev->mdev,
1068                                                        &context->tdn);
1069                 if (err)
1070                         goto out_uars;
1071         }
1072
1073         INIT_LIST_HEAD(&context->vma_private_list);
1074         INIT_LIST_HEAD(&context->db_page_list);
1075         mutex_init(&context->db_page_mutex);
1076
1077         resp.tot_uuars = req.total_num_uuars;
1078         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1079
1080         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1081                 resp.response_length += sizeof(resp.cqe_version);
1082
1083         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1084                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1085                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1086         }
1087
1088         /*
1089          * We don't want to expose information from the PCI bar that is located
1090          * after 4096 bytes, so if the arch only supports larger pages, let's
1091          * pretend we don't support reading the HCA's core clock. This is also
1092          * forced by mmap function.
1093          */
1094         if (PAGE_SIZE <= 4096 &&
1095             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1096                 resp.comp_mask |=
1097                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1098                 resp.hca_core_clock_offset =
1099                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1100                         PAGE_SIZE;
1101                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1102                                         sizeof(resp.reserved2);
1103         }
1104
1105         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1106         if (err)
1107                 goto out_td;
1108
1109         uuari->ver = ver;
1110         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1111         uuari->uars = uars;
1112         uuari->num_uars = num_uars;
1113         context->cqe_version = resp.cqe_version;
1114
1115         return &context->ibucontext;
1116
1117 out_td:
1118         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1119                 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1120
1121 out_uars:
1122         for (i--; i >= 0; i--)
1123                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1124 out_count:
1125         kfree(uuari->count);
1126
1127 out_bitmap:
1128         kfree(uuari->bitmap);
1129
1130 out_uar_ctx:
1131         kfree(uars);
1132
1133 out_ctx:
1134         kfree(context);
1135         return ERR_PTR(err);
1136 }
1137
1138 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1139 {
1140         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1141         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1142         struct mlx5_uuar_info *uuari = &context->uuari;
1143         int i;
1144
1145         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1146                 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1147
1148         for (i = 0; i < uuari->num_uars; i++) {
1149                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1150                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1151         }
1152
1153         kfree(uuari->count);
1154         kfree(uuari->bitmap);
1155         kfree(uuari->uars);
1156         kfree(context);
1157
1158         return 0;
1159 }
1160
1161 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1162 {
1163         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1164 }
1165
1166 static int get_command(unsigned long offset)
1167 {
1168         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1169 }
1170
1171 static int get_arg(unsigned long offset)
1172 {
1173         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1174 }
1175
1176 static int get_index(unsigned long offset)
1177 {
1178         return get_arg(offset);
1179 }
1180
1181 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1182 {
1183         /* vma_open is called when a new VMA is created on top of our VMA.  This
1184          * is done through either mremap flow or split_vma (usually due to
1185          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1186          * as this VMA is strongly hardware related.  Therefore we set the
1187          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1188          * calling us again and trying to do incorrect actions.  We assume that
1189          * the original VMA size is exactly a single page, and therefore all
1190          * "splitting" operation will not happen to it.
1191          */
1192         area->vm_ops = NULL;
1193 }
1194
1195 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1196 {
1197         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1198
1199         /* It's guaranteed that all VMAs opened on a FD are closed before the
1200          * file itself is closed, therefore no sync is needed with the regular
1201          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1202          * However need a sync with accessing the vma as part of
1203          * mlx5_ib_disassociate_ucontext.
1204          * The close operation is usually called under mm->mmap_sem except when
1205          * process is exiting.
1206          * The exiting case is handled explicitly as part of
1207          * mlx5_ib_disassociate_ucontext.
1208          */
1209         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1210
1211         /* setting the vma context pointer to null in the mlx5_ib driver's
1212          * private data, to protect a race condition in
1213          * mlx5_ib_disassociate_ucontext().
1214          */
1215         mlx5_ib_vma_priv_data->vma = NULL;
1216         list_del(&mlx5_ib_vma_priv_data->list);
1217         kfree(mlx5_ib_vma_priv_data);
1218 }
1219
1220 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1221         .open = mlx5_ib_vma_open,
1222         .close = mlx5_ib_vma_close
1223 };
1224
1225 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1226                                 struct mlx5_ib_ucontext *ctx)
1227 {
1228         struct mlx5_ib_vma_private_data *vma_prv;
1229         struct list_head *vma_head = &ctx->vma_private_list;
1230
1231         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1232         if (!vma_prv)
1233                 return -ENOMEM;
1234
1235         vma_prv->vma = vma;
1236         vma->vm_private_data = vma_prv;
1237         vma->vm_ops =  &mlx5_ib_vm_ops;
1238
1239         list_add(&vma_prv->list, vma_head);
1240
1241         return 0;
1242 }
1243
1244 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1245 {
1246         int ret;
1247         struct vm_area_struct *vma;
1248         struct mlx5_ib_vma_private_data *vma_private, *n;
1249         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1250         struct task_struct *owning_process  = NULL;
1251         struct mm_struct   *owning_mm       = NULL;
1252
1253         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1254         if (!owning_process)
1255                 return;
1256
1257         owning_mm = get_task_mm(owning_process);
1258         if (!owning_mm) {
1259                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1260                 while (1) {
1261                         put_task_struct(owning_process);
1262                         usleep_range(1000, 2000);
1263                         owning_process = get_pid_task(ibcontext->tgid,
1264                                                       PIDTYPE_PID);
1265                         if (!owning_process /* ||
1266                             owning_process->state == TASK_DEAD */) {
1267                                 pr_info("disassociate ucontext done, task was terminated\n");
1268                                 /* in case task was dead need to release the
1269                                  * task struct.
1270                                  */
1271                                 if (owning_process)
1272                                         put_task_struct(owning_process);
1273                                 return;
1274                         }
1275                 }
1276         }
1277
1278         /* need to protect from a race on closing the vma as part of
1279          * mlx5_ib_vma_close.
1280          */
1281         down_read(&owning_mm->mmap_sem);
1282         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1283                                  list) {
1284                 vma = vma_private->vma;
1285                 ret = zap_vma_ptes(vma, vma->vm_start,
1286                                    PAGE_SIZE);
1287                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1288                 /* context going to be destroyed, should
1289                  * not access ops any more.
1290                  */
1291                 vma->vm_ops = NULL;
1292                 list_del(&vma_private->list);
1293                 kfree(vma_private);
1294         }
1295         up_read(&owning_mm->mmap_sem);
1296         mmput(owning_mm);
1297         put_task_struct(owning_process);
1298 }
1299
1300 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1301 {
1302         switch (cmd) {
1303         case MLX5_IB_MMAP_WC_PAGE:
1304                 return "WC";
1305         case MLX5_IB_MMAP_REGULAR_PAGE:
1306                 return "best effort WC";
1307         case MLX5_IB_MMAP_NC_PAGE:
1308                 return "NC";
1309         default:
1310                 return NULL;
1311         }
1312 }
1313
1314 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1315                     struct vm_area_struct *vma,
1316                     struct mlx5_ib_ucontext *context)
1317 {
1318         struct mlx5_uuar_info *uuari = &context->uuari;
1319         int err;
1320         unsigned long idx;
1321         phys_addr_t pfn, pa;
1322         pgprot_t prot;
1323
1324         switch (cmd) {
1325         case MLX5_IB_MMAP_WC_PAGE:
1326 /* Some architectures don't support WC memory */
1327 #if defined(CONFIG_X86)
1328                 if (!pat_enabled())
1329                         return -EPERM;
1330 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1331                         return -EPERM;
1332 #endif
1333         /* fall through */
1334         case MLX5_IB_MMAP_REGULAR_PAGE:
1335                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1336                 prot = pgprot_writecombine(vma->vm_page_prot);
1337                 break;
1338         case MLX5_IB_MMAP_NC_PAGE:
1339                 prot = pgprot_noncached(vma->vm_page_prot);
1340                 break;
1341         default:
1342                 return -EINVAL;
1343         }
1344
1345         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1346                 return -EINVAL;
1347
1348         idx = get_index(vma->vm_pgoff);
1349         if (idx >= uuari->num_uars)
1350                 return -EINVAL;
1351
1352         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1353         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1354
1355         vma->vm_page_prot = prot;
1356         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1357                                  PAGE_SIZE, vma->vm_page_prot);
1358         if (err) {
1359                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n",
1360                             err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd));
1361                 return -EAGAIN;
1362         }
1363
1364         pa = pfn << PAGE_SHIFT;
1365         mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd),
1366                     (unsigned long long)vma->vm_start, &pa);
1367
1368         return mlx5_ib_set_vma_data(vma, context);
1369 }
1370
1371 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1372 {
1373         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1374         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1375         unsigned long command;
1376         phys_addr_t pfn;
1377
1378         command = get_command(vma->vm_pgoff);
1379         switch (command) {
1380         case MLX5_IB_MMAP_WC_PAGE:
1381         case MLX5_IB_MMAP_NC_PAGE:
1382         case MLX5_IB_MMAP_REGULAR_PAGE:
1383                 return uar_mmap(dev, command, vma, context);
1384
1385         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1386                 return -ENOSYS;
1387
1388         case MLX5_IB_MMAP_CORE_CLOCK:
1389                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1390                         return -EINVAL;
1391
1392                 if (vma->vm_flags & VM_WRITE)
1393                         return -EPERM;
1394
1395                 /* Don't expose to user-space information it shouldn't have */
1396                 if (PAGE_SIZE > 4096)
1397                         return -EOPNOTSUPP;
1398
1399                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1400                 pfn = (dev->mdev->iseg_base +
1401                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1402                         PAGE_SHIFT;
1403                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1404                                        PAGE_SIZE, vma->vm_page_prot))
1405                         return -EAGAIN;
1406
1407                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n",
1408                             (unsigned long long)vma->vm_start,
1409                             (unsigned long long)pfn << PAGE_SHIFT);
1410                 break;
1411
1412         default:
1413                 return -EINVAL;
1414         }
1415
1416         return 0;
1417 }
1418
1419 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1420                                       struct ib_ucontext *context,
1421                                       struct ib_udata *udata)
1422 {
1423         struct mlx5_ib_alloc_pd_resp resp;
1424         struct mlx5_ib_pd *pd;
1425         int err;
1426
1427         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1428         if (!pd)
1429                 return ERR_PTR(-ENOMEM);
1430
1431         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1432         if (err) {
1433                 kfree(pd);
1434                 return ERR_PTR(err);
1435         }
1436
1437         if (context) {
1438                 resp.pdn = pd->pdn;
1439                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1440                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1441                         kfree(pd);
1442                         return ERR_PTR(-EFAULT);
1443                 }
1444         }
1445
1446         return &pd->ibpd;
1447 }
1448
1449 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1450 {
1451         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1452         struct mlx5_ib_pd *mpd = to_mpd(pd);
1453
1454         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1455         kfree(mpd);
1456
1457         return 0;
1458 }
1459
1460 enum {
1461         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1462         MATCH_CRITERIA_ENABLE_MISC_BIT,
1463         MATCH_CRITERIA_ENABLE_INNER_BIT
1464 };
1465
1466 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1467         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1468                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1469
1470 static u8 get_match_criteria_enable(u32 *match_criteria)
1471 {
1472         u8 match_criteria_enable;
1473
1474         match_criteria_enable =
1475                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1476                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1477         match_criteria_enable |=
1478                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1479                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1480         match_criteria_enable |=
1481                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1482                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1483
1484         return match_criteria_enable;
1485 }
1486
1487 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1488 {
1489         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1490         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1491 }
1492
1493 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1494 {
1495         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1496         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1497         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1498         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1499 }
1500
1501 #define LAST_ETH_FIELD vlan_tag
1502 #define LAST_IB_FIELD sl
1503 #define LAST_IPV4_FIELD tos
1504 #define LAST_IPV6_FIELD traffic_class
1505 #define LAST_TCP_UDP_FIELD src_port
1506
1507 /* Field is the last supported field */
1508 #define FIELDS_NOT_SUPPORTED(filter, field)\
1509         memchr_inv((void *)&filter.field  +\
1510                    sizeof(filter.field), 0,\
1511                    sizeof(filter) -\
1512                    offsetof(typeof(filter), field) -\
1513                    sizeof(filter.field))
1514
1515 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1516                            const union ib_flow_spec *ib_spec)
1517 {
1518         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1519                                              outer_headers);
1520         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1521                                              outer_headers);
1522         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1523                                            misc_parameters);
1524         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1525                                            misc_parameters);
1526
1527         switch (ib_spec->type) {
1528         case IB_FLOW_SPEC_ETH:
1529                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1530                         return -ENOTSUPP;
1531
1532                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1533                                              dmac_47_16),
1534                                 ib_spec->eth.mask.dst_mac);
1535                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1536                                              dmac_47_16),
1537                                 ib_spec->eth.val.dst_mac);
1538
1539                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1540                                              smac_47_16),
1541                                 ib_spec->eth.mask.src_mac);
1542                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1543                                              smac_47_16),
1544                                 ib_spec->eth.val.src_mac);
1545
1546                 if (ib_spec->eth.mask.vlan_tag) {
1547                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1548                                  cvlan_tag, 1);
1549                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1550                                  cvlan_tag, 1);
1551
1552                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1553                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1554                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1555                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1556
1557                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1558                                  first_cfi,
1559                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1560                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1561                                  first_cfi,
1562                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1563
1564                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1565                                  first_prio,
1566                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1567                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1568                                  first_prio,
1569                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1570                 }
1571                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1572                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1573                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1574                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1575                 break;
1576         case IB_FLOW_SPEC_IPV4:
1577                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1578                         return -ENOTSUPP;
1579
1580                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1581                          ethertype, 0xffff);
1582                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1583                          ethertype, ETH_P_IP);
1584
1585                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1586                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1587                        &ib_spec->ipv4.mask.src_ip,
1588                        sizeof(ib_spec->ipv4.mask.src_ip));
1589                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1590                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1591                        &ib_spec->ipv4.val.src_ip,
1592                        sizeof(ib_spec->ipv4.val.src_ip));
1593                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1594                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1595                        &ib_spec->ipv4.mask.dst_ip,
1596                        sizeof(ib_spec->ipv4.mask.dst_ip));
1597                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1598                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1599                        &ib_spec->ipv4.val.dst_ip,
1600                        sizeof(ib_spec->ipv4.val.dst_ip));
1601
1602                 set_tos(outer_headers_c, outer_headers_v,
1603                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1604
1605                 set_proto(outer_headers_c, outer_headers_v,
1606                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1607                 break;
1608         case IB_FLOW_SPEC_IPV6:
1609                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1610                         return -ENOTSUPP;
1611
1612                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1613                          ethertype, 0xffff);
1614                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1615                          ethertype, IPPROTO_IPV6);
1616
1617                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1618                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1619                        &ib_spec->ipv6.mask.src_ip,
1620                        sizeof(ib_spec->ipv6.mask.src_ip));
1621                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1622                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1623                        &ib_spec->ipv6.val.src_ip,
1624                        sizeof(ib_spec->ipv6.val.src_ip));
1625                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1626                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1627                        &ib_spec->ipv6.mask.dst_ip,
1628                        sizeof(ib_spec->ipv6.mask.dst_ip));
1629                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1630                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1631                        &ib_spec->ipv6.val.dst_ip,
1632                        sizeof(ib_spec->ipv6.val.dst_ip));
1633
1634                 set_tos(outer_headers_c, outer_headers_v,
1635                         ib_spec->ipv6.mask.traffic_class,
1636                         ib_spec->ipv6.val.traffic_class);
1637
1638                 set_proto(outer_headers_c, outer_headers_v,
1639                           ib_spec->ipv6.mask.next_hdr,
1640                           ib_spec->ipv6.val.next_hdr);
1641
1642                 MLX5_SET(fte_match_set_misc, misc_params_c,
1643                          outer_ipv6_flow_label,
1644                          ntohl(ib_spec->ipv6.mask.flow_label));
1645                 MLX5_SET(fte_match_set_misc, misc_params_v,
1646                          outer_ipv6_flow_label,
1647                          ntohl(ib_spec->ipv6.val.flow_label));
1648                 break;
1649         case IB_FLOW_SPEC_TCP:
1650                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1651                                          LAST_TCP_UDP_FIELD))
1652                         return -ENOTSUPP;
1653
1654                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1655                          0xff);
1656                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1657                          IPPROTO_TCP);
1658
1659                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1660                          ntohs(ib_spec->tcp_udp.mask.src_port));
1661                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1662                          ntohs(ib_spec->tcp_udp.val.src_port));
1663
1664                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1665                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1666                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1667                          ntohs(ib_spec->tcp_udp.val.dst_port));
1668                 break;
1669         case IB_FLOW_SPEC_UDP:
1670                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1671                                          LAST_TCP_UDP_FIELD))
1672                         return -ENOTSUPP;
1673
1674                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1675                          0xff);
1676                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1677                          IPPROTO_UDP);
1678
1679                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1680                          ntohs(ib_spec->tcp_udp.mask.src_port));
1681                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1682                          ntohs(ib_spec->tcp_udp.val.src_port));
1683
1684                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1685                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1686                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1687                          ntohs(ib_spec->tcp_udp.val.dst_port));
1688                 break;
1689         default:
1690                 return -EINVAL;
1691         }
1692
1693         return 0;
1694 }
1695
1696 /* If a flow could catch both multicast and unicast packets,
1697  * it won't fall into the multicast flow steering table and this rule
1698  * could steal other multicast packets.
1699  */
1700 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1701 {
1702         struct ib_flow_spec_eth *eth_spec;
1703
1704         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1705             ib_attr->size < sizeof(struct ib_flow_attr) +
1706             sizeof(struct ib_flow_spec_eth) ||
1707             ib_attr->num_of_specs < 1)
1708                 return false;
1709
1710         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1711         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1712             eth_spec->size != sizeof(*eth_spec))
1713                 return false;
1714
1715         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1716                is_multicast_ether_addr(eth_spec->val.dst_mac);
1717 }
1718
1719 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1720 {
1721         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1722         bool has_ipv4_spec = false;
1723         bool eth_type_ipv4 = true;
1724         unsigned int spec_index;
1725
1726         /* Validate that ethertype is correct */
1727         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1728                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1729                     ib_spec->eth.mask.ether_type) {
1730                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1731                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1732                                 eth_type_ipv4 = false;
1733                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1734                         has_ipv4_spec = true;
1735                 }
1736                 ib_spec = (void *)ib_spec + ib_spec->size;
1737         }
1738         return !has_ipv4_spec || eth_type_ipv4;
1739 }
1740
1741 static void put_flow_table(struct mlx5_ib_dev *dev,
1742                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1743 {
1744         prio->refcount -= !!ft_added;
1745         if (!prio->refcount) {
1746                 mlx5_destroy_flow_table(prio->flow_table);
1747                 prio->flow_table = NULL;
1748         }
1749 }
1750
1751 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1752 {
1753         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1754         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1755                                                           struct mlx5_ib_flow_handler,
1756                                                           ibflow);
1757         struct mlx5_ib_flow_handler *iter, *tmp;
1758
1759         mutex_lock(&dev->flow_db.lock);
1760
1761         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1762                 mlx5_del_flow_rule(iter->rule);
1763                 put_flow_table(dev, iter->prio, true);
1764                 list_del(&iter->list);
1765                 kfree(iter);
1766         }
1767
1768         mlx5_del_flow_rule(handler->rule);
1769         put_flow_table(dev, handler->prio, true);
1770         mutex_unlock(&dev->flow_db.lock);
1771
1772         kfree(handler);
1773
1774         return 0;
1775 }
1776
1777 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1778 {
1779         priority *= 2;
1780         if (!dont_trap)
1781                 priority++;
1782         return priority;
1783 }
1784
1785 enum flow_table_type {
1786         MLX5_IB_FT_RX,
1787         MLX5_IB_FT_TX
1788 };
1789
1790 #define MLX5_FS_MAX_TYPES        10
1791 #define MLX5_FS_MAX_ENTRIES      32000UL
1792 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1793                                                 struct ib_flow_attr *flow_attr,
1794                                                 enum flow_table_type ft_type)
1795 {
1796         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1797         struct mlx5_flow_namespace *ns = NULL;
1798         struct mlx5_ib_flow_prio *prio;
1799         struct mlx5_flow_table *ft;
1800         int num_entries;
1801         int num_groups;
1802         int priority;
1803         int err = 0;
1804
1805         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1806                 if (flow_is_multicast_only(flow_attr) &&
1807                     !dont_trap)
1808                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1809                 else
1810                         priority = ib_prio_to_core_prio(flow_attr->priority,
1811                                                         dont_trap);
1812                 ns = mlx5_get_flow_namespace(dev->mdev,
1813                                              MLX5_FLOW_NAMESPACE_BYPASS);
1814                 num_entries = MLX5_FS_MAX_ENTRIES;
1815                 num_groups = MLX5_FS_MAX_TYPES;
1816                 prio = &dev->flow_db.prios[priority];
1817         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1818                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1819                 ns = mlx5_get_flow_namespace(dev->mdev,
1820                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1821                 build_leftovers_ft_param("bypass", &priority,
1822                                          &num_entries,
1823                                          &num_groups);
1824                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1825         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1826                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1827                                         allow_sniffer_and_nic_rx_shared_tir))
1828                         return ERR_PTR(-ENOTSUPP);
1829
1830                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1831                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1832                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1833
1834                 prio = &dev->flow_db.sniffer[ft_type];
1835                 priority = 0;
1836                 num_entries = 1;
1837                 num_groups = 1;
1838         }
1839
1840         if (!ns)
1841                 return ERR_PTR(-ENOTSUPP);
1842
1843         ft = prio->flow_table;
1844         if (!ft) {
1845                 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass",
1846                                                          num_entries,
1847                                                          num_groups);
1848
1849                 if (!IS_ERR(ft)) {
1850                         prio->refcount = 0;
1851                         prio->flow_table = ft;
1852                 } else {
1853                         err = PTR_ERR(ft);
1854                 }
1855         }
1856
1857         return err ? ERR_PTR(err) : prio;
1858 }
1859
1860 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1861                                                      struct mlx5_ib_flow_prio *ft_prio,
1862                                                      const struct ib_flow_attr *flow_attr,
1863                                                      struct mlx5_flow_destination *dst)
1864 {
1865         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1866         struct mlx5_ib_flow_handler *handler;
1867         struct mlx5_flow_spec *spec;
1868         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1869         unsigned int spec_index;
1870         u32 action;
1871         int err = 0;
1872
1873         if (!is_valid_attr(flow_attr))
1874                 return ERR_PTR(-EINVAL);
1875
1876         spec = mlx5_vzalloc(sizeof(*spec));
1877         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1878         if (!handler || !spec) {
1879                 err = -ENOMEM;
1880                 goto free;
1881         }
1882
1883         INIT_LIST_HEAD(&handler->list);
1884
1885         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1886                 err = parse_flow_attr(spec->match_criteria,
1887                                       spec->match_value, ib_flow);
1888                 if (err < 0)
1889                         goto free;
1890
1891                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1892         }
1893
1894         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1895         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1896                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1897         handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable,
1898                                            spec->match_criteria,
1899                                            spec->match_value,
1900                                            action,
1901                                            MLX5_FS_DEFAULT_FLOW_TAG,
1902                                            dst);
1903
1904         if (IS_ERR(handler->rule)) {
1905                 err = PTR_ERR(handler->rule);
1906                 goto free;
1907         }
1908
1909         ft_prio->refcount++;
1910         handler->prio = ft_prio;
1911
1912         ft_prio->flow_table = ft;
1913 free:
1914         if (err)
1915                 kfree(handler);
1916         kvfree(spec);
1917         return err ? ERR_PTR(err) : handler;
1918 }
1919
1920 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1921                                                           struct mlx5_ib_flow_prio *ft_prio,
1922                                                           struct ib_flow_attr *flow_attr,
1923                                                           struct mlx5_flow_destination *dst)
1924 {
1925         struct mlx5_ib_flow_handler *handler_dst = NULL;
1926         struct mlx5_ib_flow_handler *handler = NULL;
1927
1928         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1929         if (!IS_ERR(handler)) {
1930                 handler_dst = create_flow_rule(dev, ft_prio,
1931                                                flow_attr, dst);
1932                 if (IS_ERR(handler_dst)) {
1933                         mlx5_del_flow_rule(handler->rule);
1934                         ft_prio->refcount--;
1935                         kfree(handler);
1936                         handler = handler_dst;
1937                 } else {
1938                         list_add(&handler_dst->list, &handler->list);
1939                 }
1940         }
1941
1942         return handler;
1943 }
1944 enum {
1945         LEFTOVERS_MC,
1946         LEFTOVERS_UC,
1947 };
1948
1949 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1950                                                           struct mlx5_ib_flow_prio *ft_prio,
1951                                                           struct ib_flow_attr *flow_attr,
1952                                                           struct mlx5_flow_destination *dst)
1953 {
1954         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1955         struct mlx5_ib_flow_handler *handler = NULL;
1956
1957         static struct {
1958                 struct ib_flow_attr     flow_attr;
1959                 struct ib_flow_spec_eth eth_flow;
1960         } leftovers_specs[] = {
1961                 [LEFTOVERS_MC] = {
1962                         .flow_attr = {
1963                                 .num_of_specs = 1,
1964                                 .size = sizeof(leftovers_specs[0])
1965                         },
1966                         .eth_flow = {
1967                                 .type = IB_FLOW_SPEC_ETH,
1968                                 .size = sizeof(struct ib_flow_spec_eth),
1969                                 .mask = {.dst_mac = {0x1} },
1970                                 .val =  {.dst_mac = {0x1} }
1971                         }
1972                 },
1973                 [LEFTOVERS_UC] = {
1974                         .flow_attr = {
1975                                 .num_of_specs = 1,
1976                                 .size = sizeof(leftovers_specs[0])
1977                         },
1978                         .eth_flow = {
1979                                 .type = IB_FLOW_SPEC_ETH,
1980                                 .size = sizeof(struct ib_flow_spec_eth),
1981                                 .mask = {.dst_mac = {0x1} },
1982                                 .val = {.dst_mac = {} }
1983                         }
1984                 }
1985         };
1986
1987         handler = create_flow_rule(dev, ft_prio,
1988                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1989                                    dst);
1990         if (!IS_ERR(handler) &&
1991             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1992                 handler_ucast = create_flow_rule(dev, ft_prio,
1993                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1994                                                  dst);
1995                 if (IS_ERR(handler_ucast)) {
1996                         mlx5_del_flow_rule(handler->rule);
1997                         ft_prio->refcount--;
1998                         kfree(handler);
1999                         handler = handler_ucast;
2000                 } else {
2001                         list_add(&handler_ucast->list, &handler->list);
2002                 }
2003         }
2004
2005         return handler;
2006 }
2007
2008 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2009                                                         struct mlx5_ib_flow_prio *ft_rx,
2010                                                         struct mlx5_ib_flow_prio *ft_tx,
2011                                                         struct mlx5_flow_destination *dst)
2012 {
2013         struct mlx5_ib_flow_handler *handler_rx;
2014         struct mlx5_ib_flow_handler *handler_tx;
2015         int err;
2016         static const struct ib_flow_attr flow_attr  = {
2017                 .num_of_specs = 0,
2018                 .size = sizeof(flow_attr)
2019         };
2020
2021         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2022         if (IS_ERR(handler_rx)) {
2023                 err = PTR_ERR(handler_rx);
2024                 goto err;
2025         }
2026
2027         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2028         if (IS_ERR(handler_tx)) {
2029                 err = PTR_ERR(handler_tx);
2030                 goto err_tx;
2031         }
2032
2033         list_add(&handler_tx->list, &handler_rx->list);
2034
2035         return handler_rx;
2036
2037 err_tx:
2038         mlx5_del_flow_rule(handler_rx->rule);
2039         ft_rx->refcount--;
2040         kfree(handler_rx);
2041 err:
2042         return ERR_PTR(err);
2043 }
2044
2045 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2046                                            struct ib_flow_attr *flow_attr,
2047                                            int domain)
2048 {
2049         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2050         struct mlx5_ib_qp *mqp = to_mqp(qp);
2051         struct mlx5_ib_flow_handler *handler = NULL;
2052         struct mlx5_flow_destination *dst = NULL;
2053         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2054         struct mlx5_ib_flow_prio *ft_prio;
2055         int err;
2056
2057         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2058                 return ERR_PTR(-ENOSPC);
2059
2060         if (domain != IB_FLOW_DOMAIN_USER ||
2061             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2062             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2063                 return ERR_PTR(-EINVAL);
2064
2065         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2066         if (!dst)
2067                 return ERR_PTR(-ENOMEM);
2068
2069         mutex_lock(&dev->flow_db.lock);
2070
2071         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2072         if (IS_ERR(ft_prio)) {
2073                 err = PTR_ERR(ft_prio);
2074                 goto unlock;
2075         }
2076         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2077                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2078                 if (IS_ERR(ft_prio_tx)) {
2079                         err = PTR_ERR(ft_prio_tx);
2080                         ft_prio_tx = NULL;
2081                         goto destroy_ft;
2082                 }
2083         }
2084
2085         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2086         if (mqp->flags & MLX5_IB_QP_RSS)
2087                 dst->tir_num = mqp->rss_qp.tirn;
2088         else
2089                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2090
2091         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2092                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2093                         handler = create_dont_trap_rule(dev, ft_prio,
2094                                                         flow_attr, dst);
2095                 } else {
2096                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2097                                                    dst);
2098                 }
2099         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2100                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2101                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2102                                                 dst);
2103         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2104                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2105         } else {
2106                 err = -EINVAL;
2107                 goto destroy_ft;
2108         }
2109
2110         if (IS_ERR(handler)) {
2111                 err = PTR_ERR(handler);
2112                 handler = NULL;
2113                 goto destroy_ft;
2114         }
2115
2116         mutex_unlock(&dev->flow_db.lock);
2117         kfree(dst);
2118
2119         return &handler->ibflow;
2120
2121 destroy_ft:
2122         put_flow_table(dev, ft_prio, false);
2123         if (ft_prio_tx)
2124                 put_flow_table(dev, ft_prio_tx, false);
2125 unlock:
2126         mutex_unlock(&dev->flow_db.lock);
2127         kfree(dst);
2128         kfree(handler);
2129         return ERR_PTR(err);
2130 }
2131
2132 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2133 {
2134         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2135         int err;
2136
2137         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2138         if (err)
2139                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2140                              ibqp->qp_num, gid->raw);
2141
2142         return err;
2143 }
2144
2145 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2146 {
2147         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2148         int err;
2149
2150         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2151         if (err)
2152                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2153                              ibqp->qp_num, gid->raw);
2154
2155         return err;
2156 }
2157
2158 static int init_node_data(struct mlx5_ib_dev *dev)
2159 {
2160         int err;
2161
2162         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2163         if (err)
2164                 return err;
2165
2166         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2167 }
2168
2169 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2170                              char *buf)
2171 {
2172         struct mlx5_ib_dev *dev =
2173                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2174
2175         return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2176 }
2177
2178 static ssize_t show_reg_pages(struct device *device,
2179                               struct device_attribute *attr, char *buf)
2180 {
2181         struct mlx5_ib_dev *dev =
2182                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2183
2184         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2185 }
2186
2187 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2188                         char *buf)
2189 {
2190         struct mlx5_ib_dev *dev =
2191                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2192         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2193 }
2194
2195 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2196                         char *buf)
2197 {
2198         struct mlx5_ib_dev *dev =
2199                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2200         return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2201 }
2202
2203 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2204                           char *buf)
2205 {
2206         struct mlx5_ib_dev *dev =
2207                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2208         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2209                        dev->mdev->board_id);
2210 }
2211
2212 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2213 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2214 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2215 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2216 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2217
2218 static struct device_attribute *mlx5_class_attributes[] = {
2219         &dev_attr_hw_rev,
2220         &dev_attr_hca_type,
2221         &dev_attr_board_id,
2222         &dev_attr_fw_pages,
2223         &dev_attr_reg_pages,
2224 };
2225
2226 static void pkey_change_handler(struct work_struct *work)
2227 {
2228         struct mlx5_ib_port_resources *ports =
2229                 container_of(work, struct mlx5_ib_port_resources,
2230                              pkey_change_work);
2231
2232         mutex_lock(&ports->devr->mutex);
2233         mlx5_ib_gsi_pkey_change(ports->gsi);
2234         mutex_unlock(&ports->devr->mutex);
2235 }
2236
2237 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2238 {
2239         struct mlx5_ib_qp *mqp;
2240         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2241         struct mlx5_core_cq *mcq;
2242         struct list_head cq_armed_list;
2243         unsigned long flags_qp;
2244         unsigned long flags_cq;
2245         unsigned long flags;
2246
2247         INIT_LIST_HEAD(&cq_armed_list);
2248
2249         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2250         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2251         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2252                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2253                 if (mqp->sq.tail != mqp->sq.head) {
2254                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2255                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2256                         if (send_mcq->mcq.comp &&
2257                             mqp->ibqp.send_cq->comp_handler) {
2258                                 if (!send_mcq->mcq.reset_notify_added) {
2259                                         send_mcq->mcq.reset_notify_added = 1;
2260                                         list_add_tail(&send_mcq->mcq.reset_notify,
2261                                                       &cq_armed_list);
2262                                 }
2263                         }
2264                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2265                 }
2266                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2267                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2268                 /* no handling is needed for SRQ */
2269                 if (!mqp->ibqp.srq) {
2270                         if (mqp->rq.tail != mqp->rq.head) {
2271                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2272                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2273                                 if (recv_mcq->mcq.comp &&
2274                                     mqp->ibqp.recv_cq->comp_handler) {
2275                                         if (!recv_mcq->mcq.reset_notify_added) {
2276                                                 recv_mcq->mcq.reset_notify_added = 1;
2277                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2278                                                               &cq_armed_list);
2279                                         }
2280                                 }
2281                                 spin_unlock_irqrestore(&recv_mcq->lock,
2282                                                        flags_cq);
2283                         }
2284                 }
2285                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2286         }
2287         /*At that point all inflight post send were put to be executed as of we
2288          * lock/unlock above locks Now need to arm all involved CQs.
2289          */
2290         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2291                 mcq->comp(mcq);
2292         }
2293         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2294 }
2295
2296 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2297                           enum mlx5_dev_event event, unsigned long param)
2298 {
2299         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2300         struct ib_event ibev;
2301         bool fatal = false;
2302         u8 port = 0;
2303
2304         switch (event) {
2305         case MLX5_DEV_EVENT_SYS_ERROR:
2306                 ibev.event = IB_EVENT_DEVICE_FATAL;
2307                 mlx5_ib_handle_internal_error(ibdev);
2308                 fatal = true;
2309                 break;
2310
2311         case MLX5_DEV_EVENT_PORT_UP:
2312         case MLX5_DEV_EVENT_PORT_DOWN:
2313         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2314                 port = (u8)param;
2315
2316                 /* In RoCE, port up/down events are handled in
2317                  * mlx5_netdev_event().
2318                  */
2319                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2320                         IB_LINK_LAYER_ETHERNET)
2321                         return;
2322
2323                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2324                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2325                 break;
2326
2327         case MLX5_DEV_EVENT_LID_CHANGE:
2328                 ibev.event = IB_EVENT_LID_CHANGE;
2329                 port = (u8)param;
2330                 break;
2331
2332         case MLX5_DEV_EVENT_PKEY_CHANGE:
2333                 ibev.event = IB_EVENT_PKEY_CHANGE;
2334                 port = (u8)param;
2335
2336                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2337                 break;
2338
2339         case MLX5_DEV_EVENT_GUID_CHANGE:
2340                 ibev.event = IB_EVENT_GID_CHANGE;
2341                 port = (u8)param;
2342                 break;
2343
2344         case MLX5_DEV_EVENT_CLIENT_REREG:
2345                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2346                 port = (u8)param;
2347                 break;
2348
2349         default:
2350                 break;
2351         }
2352
2353         ibev.device           = &ibdev->ib_dev;
2354         ibev.element.port_num = port;
2355
2356         if (port < 1 || port > ibdev->num_ports) {
2357                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2358                 return;
2359         }
2360
2361         if (ibdev->ib_active)
2362                 ib_dispatch_event(&ibev);
2363
2364         if (fatal)
2365                 ibdev->ib_active = false;
2366 }
2367
2368 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2369 {
2370         int port;
2371
2372         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2373                 mlx5_query_ext_port_caps(dev, port);
2374 }
2375
2376 static int get_port_caps(struct mlx5_ib_dev *dev)
2377 {
2378         struct ib_device_attr *dprops = NULL;
2379         struct ib_port_attr *pprops = NULL;
2380         int err = -ENOMEM;
2381         int port;
2382         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2383
2384         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2385         if (!pprops)
2386                 goto out;
2387
2388         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2389         if (!dprops)
2390                 goto out;
2391
2392         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2393         if (err) {
2394                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2395                 goto out;
2396         }
2397
2398         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2399                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2400                 if (err) {
2401                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2402                                      port, err);
2403                         break;
2404                 }
2405                 dev->mdev->port_caps[port - 1].pkey_table_len =
2406                                                 dprops->max_pkeys;
2407                 dev->mdev->port_caps[port - 1].gid_table_len =
2408                                                 pprops->gid_tbl_len;
2409                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2410                             dprops->max_pkeys, pprops->gid_tbl_len);
2411         }
2412
2413 out:
2414         kfree(pprops);
2415         kfree(dprops);
2416
2417         return err;
2418 }
2419
2420 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2421 {
2422         int err;
2423
2424         err = mlx5_mr_cache_cleanup(dev);
2425         if (err)
2426                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2427
2428         mlx5_ib_destroy_qp(dev->umrc.qp);
2429         ib_free_cq(dev->umrc.cq);
2430         ib_dealloc_pd(dev->umrc.pd);
2431 }
2432
2433 enum {
2434         MAX_UMR_WR = 128,
2435 };
2436
2437 static int create_umr_res(struct mlx5_ib_dev *dev)
2438 {
2439         struct ib_qp_init_attr *init_attr = NULL;
2440         struct ib_qp_attr *attr = NULL;
2441         struct ib_pd *pd;
2442         struct ib_cq *cq;
2443         struct ib_qp *qp;
2444         int ret;
2445
2446         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2447         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2448         if (!attr || !init_attr) {
2449                 ret = -ENOMEM;
2450                 goto error_0;
2451         }
2452
2453         pd = ib_alloc_pd(&dev->ib_dev, 0);
2454         if (IS_ERR(pd)) {
2455                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2456                 ret = PTR_ERR(pd);
2457                 goto error_0;
2458         }
2459
2460         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2461         if (IS_ERR(cq)) {
2462                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2463                 ret = PTR_ERR(cq);
2464                 goto error_2;
2465         }
2466
2467         init_attr->send_cq = cq;
2468         init_attr->recv_cq = cq;
2469         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2470         init_attr->cap.max_send_wr = MAX_UMR_WR;
2471         init_attr->cap.max_send_sge = 1;
2472         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2473         init_attr->port_num = 1;
2474         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2475         if (IS_ERR(qp)) {
2476                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2477                 ret = PTR_ERR(qp);
2478                 goto error_3;
2479         }
2480         qp->device     = &dev->ib_dev;
2481         qp->real_qp    = qp;
2482         qp->uobject    = NULL;
2483         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2484
2485         attr->qp_state = IB_QPS_INIT;
2486         attr->port_num = 1;
2487         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2488                                 IB_QP_PORT, NULL);
2489         if (ret) {
2490                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2491                 goto error_4;
2492         }
2493
2494         memset(attr, 0, sizeof(*attr));
2495         attr->qp_state = IB_QPS_RTR;
2496         attr->path_mtu = IB_MTU_256;
2497
2498         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2499         if (ret) {
2500                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2501                 goto error_4;
2502         }
2503
2504         memset(attr, 0, sizeof(*attr));
2505         attr->qp_state = IB_QPS_RTS;
2506         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2507         if (ret) {
2508                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2509                 goto error_4;
2510         }
2511
2512         dev->umrc.qp = qp;
2513         dev->umrc.cq = cq;
2514         dev->umrc.pd = pd;
2515
2516         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2517         ret = mlx5_mr_cache_init(dev);
2518         if (ret) {
2519                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2520                 goto error_4;
2521         }
2522
2523         kfree(attr);
2524         kfree(init_attr);
2525
2526         return 0;
2527
2528 error_4:
2529         mlx5_ib_destroy_qp(qp);
2530
2531 error_3:
2532         ib_free_cq(cq);
2533
2534 error_2:
2535         ib_dealloc_pd(pd);
2536
2537 error_0:
2538         kfree(attr);
2539         kfree(init_attr);
2540         return ret;
2541 }
2542
2543 static int create_dev_resources(struct mlx5_ib_resources *devr)
2544 {
2545         struct ib_srq_init_attr attr;
2546         struct mlx5_ib_dev *dev;
2547         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2548         int port;
2549         int ret = 0;
2550
2551         dev = container_of(devr, struct mlx5_ib_dev, devr);
2552
2553         mutex_init(&devr->mutex);
2554
2555         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2556         if (IS_ERR(devr->p0)) {
2557                 ret = PTR_ERR(devr->p0);
2558                 goto error0;
2559         }
2560         devr->p0->device  = &dev->ib_dev;
2561         devr->p0->uobject = NULL;
2562         atomic_set(&devr->p0->usecnt, 0);
2563
2564         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2565         if (IS_ERR(devr->c0)) {
2566                 ret = PTR_ERR(devr->c0);
2567                 goto error1;
2568         }
2569         devr->c0->device        = &dev->ib_dev;
2570         devr->c0->uobject       = NULL;
2571         devr->c0->comp_handler  = NULL;
2572         devr->c0->event_handler = NULL;
2573         devr->c0->cq_context    = NULL;
2574         atomic_set(&devr->c0->usecnt, 0);
2575
2576         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2577         if (IS_ERR(devr->x0)) {
2578                 ret = PTR_ERR(devr->x0);
2579                 goto error2;
2580         }
2581         devr->x0->device = &dev->ib_dev;
2582         devr->x0->inode = NULL;
2583         atomic_set(&devr->x0->usecnt, 0);
2584         mutex_init(&devr->x0->tgt_qp_mutex);
2585         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2586
2587         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2588         if (IS_ERR(devr->x1)) {
2589                 ret = PTR_ERR(devr->x1);
2590                 goto error3;
2591         }
2592         devr->x1->device = &dev->ib_dev;
2593         devr->x1->inode = NULL;
2594         atomic_set(&devr->x1->usecnt, 0);
2595         mutex_init(&devr->x1->tgt_qp_mutex);
2596         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2597
2598         memset(&attr, 0, sizeof(attr));
2599         attr.attr.max_sge = 1;
2600         attr.attr.max_wr = 1;
2601         attr.srq_type = IB_SRQT_XRC;
2602         attr.ext.xrc.cq = devr->c0;
2603         attr.ext.xrc.xrcd = devr->x0;
2604
2605         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2606         if (IS_ERR(devr->s0)) {
2607                 ret = PTR_ERR(devr->s0);
2608                 goto error4;
2609         }
2610         devr->s0->device        = &dev->ib_dev;
2611         devr->s0->pd            = devr->p0;
2612         devr->s0->uobject       = NULL;
2613         devr->s0->event_handler = NULL;
2614         devr->s0->srq_context   = NULL;
2615         devr->s0->srq_type      = IB_SRQT_XRC;
2616         devr->s0->ext.xrc.xrcd  = devr->x0;
2617         devr->s0->ext.xrc.cq    = devr->c0;
2618         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2619         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2620         atomic_inc(&devr->p0->usecnt);
2621         atomic_set(&devr->s0->usecnt, 0);
2622
2623         memset(&attr, 0, sizeof(attr));
2624         attr.attr.max_sge = 1;
2625         attr.attr.max_wr = 1;
2626         attr.srq_type = IB_SRQT_BASIC;
2627         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2628         if (IS_ERR(devr->s1)) {
2629                 ret = PTR_ERR(devr->s1);
2630                 goto error5;
2631         }
2632         devr->s1->device        = &dev->ib_dev;
2633         devr->s1->pd            = devr->p0;
2634         devr->s1->uobject       = NULL;
2635         devr->s1->event_handler = NULL;
2636         devr->s1->srq_context   = NULL;
2637         devr->s1->srq_type      = IB_SRQT_BASIC;
2638         devr->s1->ext.xrc.cq    = devr->c0;
2639         atomic_inc(&devr->p0->usecnt);
2640         atomic_set(&devr->s0->usecnt, 0);
2641
2642         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2643                 INIT_WORK(&devr->ports[port].pkey_change_work,
2644                           pkey_change_handler);
2645                 devr->ports[port].devr = devr;
2646         }
2647
2648         return 0;
2649
2650 error5:
2651         mlx5_ib_destroy_srq(devr->s0);
2652 error4:
2653         mlx5_ib_dealloc_xrcd(devr->x1);
2654 error3:
2655         mlx5_ib_dealloc_xrcd(devr->x0);
2656 error2:
2657         mlx5_ib_destroy_cq(devr->c0);
2658 error1:
2659         mlx5_ib_dealloc_pd(devr->p0);
2660 error0:
2661         return ret;
2662 }
2663
2664 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2665 {
2666         struct mlx5_ib_dev *dev =
2667                 container_of(devr, struct mlx5_ib_dev, devr);
2668         int port;
2669
2670         mlx5_ib_destroy_srq(devr->s1);
2671         mlx5_ib_destroy_srq(devr->s0);
2672         mlx5_ib_dealloc_xrcd(devr->x0);
2673         mlx5_ib_dealloc_xrcd(devr->x1);
2674         mlx5_ib_destroy_cq(devr->c0);
2675         mlx5_ib_dealloc_pd(devr->p0);
2676
2677         /* Make sure no change P_Key work items are still executing */
2678         for (port = 0; port < dev->num_ports; ++port)
2679                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2680 }
2681
2682 static u32 get_core_cap_flags(struct ib_device *ibdev)
2683 {
2684         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2685         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2686         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2687         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2688         u32 ret = 0;
2689
2690         if (ll == IB_LINK_LAYER_INFINIBAND)
2691                 return RDMA_CORE_PORT_IBA_IB;
2692
2693         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2694                 return 0;
2695
2696         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2697                 return 0;
2698
2699         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2700                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2701
2702         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2703                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2704
2705         return ret;
2706 }
2707
2708 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2709                                struct ib_port_immutable *immutable)
2710 {
2711         struct ib_port_attr attr;
2712         int err;
2713
2714         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2715         if (err)
2716                 return err;
2717
2718         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2719         immutable->gid_tbl_len = attr.gid_tbl_len;
2720         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2721         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2722
2723         return 0;
2724 }
2725
2726 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2727                            size_t str_len)
2728 {
2729         struct mlx5_ib_dev *dev =
2730                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2731         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2732                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2733 }
2734
2735 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2736 {
2737         return 0;
2738 }
2739
2740 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2741 {
2742 }
2743
2744 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2745 {
2746         if (dev->roce.nb.notifier_call) {
2747                 unregister_netdevice_notifier(&dev->roce.nb);
2748                 dev->roce.nb.notifier_call = NULL;
2749         }
2750 }
2751
2752 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2753 {
2754         VNET_ITERATOR_DECL(vnet_iter);
2755         struct net_device *idev;
2756         int err;
2757
2758         /* Check if mlx5en net device already exists */
2759         VNET_LIST_RLOCK();
2760         VNET_FOREACH(vnet_iter) {
2761                 IFNET_RLOCK();
2762                 CURVNET_SET_QUIET(vnet_iter);
2763                 TAILQ_FOREACH(idev, &V_ifnet, if_link) {
2764                         /* check if network interface belongs to mlx5en */
2765                         if (!mlx5_netdev_match(idev, dev->mdev, "mce"))
2766                                 continue;
2767                         write_lock(&dev->roce.netdev_lock);
2768                         dev->roce.netdev = idev;
2769                         write_unlock(&dev->roce.netdev_lock);
2770                 }
2771                 CURVNET_RESTORE();
2772                 IFNET_RUNLOCK();
2773         }
2774         VNET_LIST_RUNLOCK();
2775
2776         dev->roce.nb.notifier_call = mlx5_netdev_event;
2777         err = register_netdevice_notifier(&dev->roce.nb);
2778         if (err) {
2779                 dev->roce.nb.notifier_call = NULL;
2780                 return err;
2781         }
2782
2783         err = mlx5_nic_vport_enable_roce(dev->mdev);
2784         if (err)
2785                 goto err_unregister_netdevice_notifier;
2786
2787         err = mlx5_roce_lag_init(dev);
2788         if (err)
2789                 goto err_disable_roce;
2790
2791         return 0;
2792
2793 err_disable_roce:
2794         mlx5_nic_vport_disable_roce(dev->mdev);
2795
2796 err_unregister_netdevice_notifier:
2797         mlx5_remove_roce_notifier(dev);
2798         return err;
2799 }
2800
2801 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2802 {
2803         mlx5_roce_lag_cleanup(dev);
2804         mlx5_nic_vport_disable_roce(dev->mdev);
2805 }
2806
2807 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
2808 {
2809         mlx5_vport_dealloc_q_counter(dev->mdev,
2810                                      MLX5_INTERFACE_PROTOCOL_IB,
2811                                      dev->port[port_num].q_cnt_id);
2812         dev->port[port_num].q_cnt_id = 0;
2813 }
2814
2815 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2816 {
2817         unsigned int i;
2818
2819         for (i = 0; i < dev->num_ports; i++)
2820                 mlx5_ib_dealloc_q_port_counter(dev, i);
2821 }
2822
2823 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2824 {
2825         int i;
2826         int ret;
2827
2828         for (i = 0; i < dev->num_ports; i++) {
2829                 ret = mlx5_vport_alloc_q_counter(dev->mdev,
2830                                                  MLX5_INTERFACE_PROTOCOL_IB,
2831                                                  &dev->port[i].q_cnt_id);
2832                 if (ret) {
2833                         mlx5_ib_warn(dev,
2834                                      "couldn't allocate queue counter for port %d, err %d\n",
2835                                      i + 1, ret);
2836                         goto dealloc_counters;
2837                 }
2838         }
2839
2840         return 0;
2841
2842 dealloc_counters:
2843         while (--i >= 0)
2844                 mlx5_ib_dealloc_q_port_counter(dev, i);
2845
2846         return ret;
2847 }
2848
2849 static const char * const names[] = {
2850         "rx_write_requests",
2851         "rx_read_requests",
2852         "rx_atomic_requests",
2853         "out_of_buffer",
2854         "out_of_sequence",
2855         "duplicate_request",
2856         "rnr_nak_retry_err",
2857         "packet_seq_err",
2858         "implied_nak_seq_err",
2859         "local_ack_timeout_err",
2860 };
2861
2862 static const size_t stats_offsets[] = {
2863         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2864         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2865         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2866         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2867         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2868         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2869         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2870         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2871         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2872         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2873 };
2874
2875 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2876                                                     u8 port_num)
2877 {
2878         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2879
2880         /* We support only per port stats */
2881         if (port_num == 0)
2882                 return NULL;
2883
2884         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2885                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2886 }
2887
2888 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2889                                 struct rdma_hw_stats *stats,
2890                                 u8 port, int index)
2891 {
2892         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2893         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2894         void *out;
2895         __be32 val;
2896         int ret;
2897         int i;
2898
2899         if (!port || !stats)
2900                 return -ENOSYS;
2901
2902         out = mlx5_vzalloc(outlen);
2903         if (!out)
2904                 return -ENOMEM;
2905
2906         ret = mlx5_vport_query_q_counter(dev->mdev,
2907                                         dev->port[port - 1].q_cnt_id, 0,
2908                                         out, outlen);
2909         if (ret)
2910                 goto free;
2911
2912         for (i = 0; i < ARRAY_SIZE(names); i++) {
2913                 val = *(__be32 *)(out + stats_offsets[i]);
2914                 stats->value[i] = (u64)be32_to_cpu(val);
2915         }
2916 free:
2917         kvfree(out);
2918         return ARRAY_SIZE(names);
2919 }
2920
2921 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2922 {
2923         struct mlx5_ib_dev *dev;
2924         enum rdma_link_layer ll;
2925         int port_type_cap;
2926         const char *name;
2927         int err;
2928         int i;
2929
2930         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2931         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2932
2933         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2934                 return NULL;
2935
2936         printk_once(KERN_INFO "%s", mlx5_version);
2937
2938         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2939         if (!dev)
2940                 return NULL;
2941
2942         dev->mdev = mdev;
2943
2944         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2945                             GFP_KERNEL);
2946         if (!dev->port)
2947                 goto err_dealloc;
2948
2949         rwlock_init(&dev->roce.netdev_lock);
2950         err = get_port_caps(dev);
2951         if (err)
2952                 goto err_free_port;
2953
2954         if (mlx5_use_mad_ifc(dev))
2955                 get_ext_port_caps(dev);
2956
2957         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2958
2959         name = "mlx5_%d";
2960
2961         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2962         dev->ib_dev.owner               = THIS_MODULE;
2963         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2964         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2965         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2966         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2967         dev->ib_dev.num_comp_vectors    =
2968                 dev->mdev->priv.eq_table.num_comp_vectors;
2969         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2970
2971         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2972         dev->ib_dev.uverbs_cmd_mask     =
2973                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2974                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2975                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2976                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2977                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2978                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2979                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2980                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2981                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2982                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2983                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2984                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2985                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2986                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2987                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2988                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2989                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2990                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2991                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2992                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2993                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2994                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2995                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2996                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2997         dev->ib_dev.uverbs_ex_cmd_mask =
2998                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2999                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3000                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3001
3002         dev->ib_dev.query_device        = mlx5_ib_query_device;
3003         dev->ib_dev.query_port          = mlx5_ib_query_port;
3004         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3005         if (ll == IB_LINK_LAYER_ETHERNET)
3006                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3007         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3008         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3009         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3010         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3011         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3012         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3013         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3014         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3015         dev->ib_dev.mmap                = mlx5_ib_mmap;
3016         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3017         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3018         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3019         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3020         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3021         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3022         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3023         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3024         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3025         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3026         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3027         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3028         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3029         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3030         dev->ib_dev.post_send           = mlx5_ib_post_send;
3031         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3032         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3033         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3034         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3035         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3036         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3037         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3038         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3039         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3040         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3041         dev->ib_dev.reg_phys_mr         = mlx5_ib_reg_phys_mr;
3042         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3043         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3044         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3045         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3046         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3047         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3048         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3049         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3050         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3051         if (mlx5_core_is_pf(mdev)) {
3052                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3053                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3054                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3055                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3056         }
3057
3058         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3059
3060         mlx5_ib_internal_fill_odp_caps(dev);
3061
3062         if (MLX5_CAP_GEN(mdev, imaicl)) {
3063                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3064                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3065                 dev->ib_dev.uverbs_cmd_mask |=
3066                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3067                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3068         }
3069
3070         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3071             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3072                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3073                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3074         }
3075
3076         if (MLX5_CAP_GEN(mdev, xrc)) {
3077                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3078                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3079                 dev->ib_dev.uverbs_cmd_mask |=
3080                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3081                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3082         }
3083
3084         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3085             IB_LINK_LAYER_ETHERNET) {
3086                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3087                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3088                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3089                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3090                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3091                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3092                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3093                 dev->ib_dev.uverbs_ex_cmd_mask |=
3094                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3095                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3096                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3097                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3098                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3099                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3100                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3101         }
3102         err = init_node_data(dev);
3103         if (err)
3104                 goto err_free_port;
3105
3106         mutex_init(&dev->flow_db.lock);
3107         mutex_init(&dev->cap_mask_mutex);
3108         INIT_LIST_HEAD(&dev->qp_list);
3109         spin_lock_init(&dev->reset_flow_resource_lock);
3110
3111         if (ll == IB_LINK_LAYER_ETHERNET) {
3112                 err = mlx5_enable_roce(dev);
3113                 if (err)
3114                         goto err_free_port;
3115         }
3116
3117         err = create_dev_resources(&dev->devr);
3118         if (err)
3119                 goto err_disable_roce;
3120
3121         err = mlx5_ib_odp_init_one(dev);
3122         if (err)
3123                 goto err_rsrc;
3124
3125         err = mlx5_ib_alloc_q_counters(dev);
3126         if (err)
3127                 goto err_odp;
3128
3129         err = ib_register_device(&dev->ib_dev, NULL);
3130         if (err)
3131                 goto err_q_cnt;
3132
3133         err = create_umr_res(dev);
3134         if (err)
3135                 goto err_dev;
3136
3137         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3138                 err = device_create_file(&dev->ib_dev.dev,
3139                                          mlx5_class_attributes[i]);
3140                 if (err)
3141                         goto err_umrc;
3142         }
3143
3144         dev->ib_active = true;
3145
3146         return dev;
3147
3148 err_umrc:
3149         destroy_umrc_res(dev);
3150
3151 err_dev:
3152         ib_unregister_device(&dev->ib_dev);
3153
3154 err_q_cnt:
3155         mlx5_ib_dealloc_q_counters(dev);
3156
3157 err_odp:
3158         mlx5_ib_odp_remove_one(dev);
3159
3160 err_rsrc:
3161         destroy_dev_resources(&dev->devr);
3162
3163 err_disable_roce:
3164         if (ll == IB_LINK_LAYER_ETHERNET) {
3165                 mlx5_disable_roce(dev);
3166                 mlx5_remove_roce_notifier(dev);
3167         }
3168
3169 err_free_port:
3170         kfree(dev->port);
3171
3172 err_dealloc:
3173         ib_dealloc_device((struct ib_device *)dev);
3174
3175         return NULL;
3176 }
3177
3178 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3179 {
3180         struct mlx5_ib_dev *dev = context;
3181         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3182
3183         mlx5_remove_roce_notifier(dev);
3184         ib_unregister_device(&dev->ib_dev);
3185         mlx5_ib_dealloc_q_counters(dev);
3186         destroy_umrc_res(dev);
3187         mlx5_ib_odp_remove_one(dev);
3188         destroy_dev_resources(&dev->devr);
3189         if (ll == IB_LINK_LAYER_ETHERNET)
3190                 mlx5_disable_roce(dev);
3191         kfree(dev->port);
3192         ib_dealloc_device(&dev->ib_dev);
3193 }
3194
3195 static struct mlx5_interface mlx5_ib_interface = {
3196         .add            = mlx5_ib_add,
3197         .remove         = mlx5_ib_remove,
3198         .event          = mlx5_ib_event,
3199         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3200 };
3201
3202 static int __init mlx5_ib_init(void)
3203 {
3204         int err;
3205
3206         if (deprecated_prof_sel != 2)
3207                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3208
3209         err = mlx5_ib_odp_init();
3210         if (err)
3211                 return err;
3212
3213         err = mlx5_register_interface(&mlx5_ib_interface);
3214         if (err)
3215                 goto clean_odp;
3216
3217         return err;
3218
3219 clean_odp:
3220         mlx5_ib_odp_cleanup();
3221         return err;
3222 }
3223
3224 static void __exit mlx5_ib_cleanup(void)
3225 {
3226         mlx5_unregister_interface(&mlx5_ib_interface);
3227         mlx5_ib_odp_cleanup();
3228 }
3229
3230 module_init_order(mlx5_ib_init, SI_ORDER_THIRD);
3231 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD);