2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #if defined(CONFIG_X86)
36 #include <linux/sched.h>
37 #include <linux/delay.h>
40 #include <rdma/ib_user_verbs.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_cache.h>
43 #include <dev/mlx5/port.h>
44 #include <dev/mlx5/vport.h>
45 #include <linux/list.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_umem.h>
49 #include <linux/etherdevice.h>
50 #include <dev/mlx5/fs.h>
53 #define DRIVER_NAME "mlx5_ib"
54 #define DRIVER_VERSION "3.4.1-BETA"
55 #define DRIVER_RELDATE "October 2017"
57 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
58 MODULE_LICENSE("Dual BSD/GPL");
59 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
60 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
61 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
62 MODULE_VERSION(mlx5ib, 1);
64 static int deprecated_prof_sel = 2;
65 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
66 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
68 static char mlx5_version[] =
69 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
70 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
73 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76 static enum rdma_link_layer
77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
79 switch (port_type_cap) {
80 case MLX5_CAP_PORT_TYPE_IB:
81 return IB_LINK_LAYER_INFINIBAND;
82 case MLX5_CAP_PORT_TYPE_ETH:
83 return IB_LINK_LAYER_ETHERNET;
85 return IB_LINK_LAYER_UNSPECIFIED;
89 static enum rdma_link_layer
90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92 struct mlx5_ib_dev *dev = to_mdev(device);
93 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98 static bool mlx5_netdev_match(struct net_device *ndev,
99 struct mlx5_core_dev *mdev,
102 return ndev->if_type == IFT_ETHER &&
103 ndev->if_dname != NULL &&
104 strcmp(ndev->if_dname, dname) == 0 &&
105 ndev->if_softc != NULL &&
106 *(struct mlx5_core_dev **)ndev->if_softc == mdev;
109 static int mlx5_netdev_event(struct notifier_block *this,
110 unsigned long event, void *ptr)
112 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
113 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
117 case NETDEV_REGISTER:
118 case NETDEV_UNREGISTER:
119 write_lock(&ibdev->roce.netdev_lock);
120 /* check if network interface belongs to mlx5en */
121 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
122 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
124 write_unlock(&ibdev->roce.netdev_lock);
129 struct net_device *upper = NULL;
131 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
132 && ibdev->ib_active) {
133 struct ib_event ibev = {0};
135 ibev.device = &ibdev->ib_dev;
136 ibev.event = (event == NETDEV_UP) ?
137 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
138 ibev.element.port_num = 1;
139 ib_dispatch_event(&ibev);
151 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
154 struct mlx5_ib_dev *ibdev = to_mdev(device);
155 struct net_device *ndev;
157 /* Ensure ndev does not disappear before we invoke dev_hold()
159 read_lock(&ibdev->roce.netdev_lock);
160 ndev = ibdev->roce.netdev;
163 read_unlock(&ibdev->roce.netdev_lock);
168 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
171 switch (eth_proto_oper) {
172 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
173 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
174 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
175 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
176 *active_width = IB_WIDTH_1X;
177 *active_speed = IB_SPEED_SDR;
179 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
180 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
181 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
182 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
183 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
184 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
185 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
186 *active_width = IB_WIDTH_1X;
187 *active_speed = IB_SPEED_QDR;
189 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
190 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
191 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
192 *active_width = IB_WIDTH_1X;
193 *active_speed = IB_SPEED_EDR;
195 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
196 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
197 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
198 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
199 *active_width = IB_WIDTH_4X;
200 *active_speed = IB_SPEED_QDR;
202 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
203 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
204 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_HDR;
208 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
209 *active_width = IB_WIDTH_4X;
210 *active_speed = IB_SPEED_FDR;
212 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
213 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
214 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
215 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
216 *active_width = IB_WIDTH_4X;
217 *active_speed = IB_SPEED_EDR;
226 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
227 struct ib_port_attr *props)
229 struct mlx5_ib_dev *dev = to_mdev(device);
230 struct net_device *ndev;
231 enum ib_mtu ndev_ib_mtu;
236 memset(props, 0, sizeof(*props));
238 /* Possible bad flows are checked before filling out props so in case
239 * of an error it will still be zeroed out.
241 err = mlx5_query_port_eth_proto_oper(dev->mdev, ð_prot_oper, port_num);
245 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
246 &props->active_width);
248 props->port_cap_flags |= IB_PORT_CM_SUP;
249 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
251 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
252 roce_address_table_size);
253 props->max_mtu = IB_MTU_4096;
254 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
255 props->pkey_tbl_len = 1;
256 props->state = IB_PORT_DOWN;
257 props->phys_state = 3;
259 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
260 props->qkey_viol_cntr = qkey_viol_cntr;
262 ndev = mlx5_ib_get_netdev(device, port_num);
266 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
267 props->state = IB_PORT_ACTIVE;
268 props->phys_state = 5;
271 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu);
275 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
279 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
280 const struct ib_gid_attr *attr,
283 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
284 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
286 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
291 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev));
293 if (is_vlan_dev(attr->ndev)) {
294 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
295 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
298 switch (attr->gid_type) {
300 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
302 case IB_GID_TYPE_ROCE_UDP_ENCAP:
303 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
310 if (attr->gid_type != IB_GID_TYPE_IB) {
311 if (ipv6_addr_v4mapped((void *)gid))
312 MLX5_SET_RA(mlx5_addr, roce_l3_type,
313 MLX5_ROCE_L3_TYPE_IPV4);
315 MLX5_SET_RA(mlx5_addr, roce_l3_type,
316 MLX5_ROCE_L3_TYPE_IPV6);
319 if ((attr->gid_type == IB_GID_TYPE_IB) ||
320 !ipv6_addr_v4mapped((void *)gid))
321 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
323 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
326 static int set_roce_addr(struct ib_device *device, u8 port_num,
328 const union ib_gid *gid,
329 const struct ib_gid_attr *attr)
331 struct mlx5_ib_dev *dev = to_mdev(device);
332 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
333 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
334 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
335 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
337 if (ll != IB_LINK_LAYER_ETHERNET)
340 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
342 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
343 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
344 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
347 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
348 unsigned int index, const union ib_gid *gid,
349 const struct ib_gid_attr *attr,
350 __always_unused void **context)
352 return set_roce_addr(device, port_num, index, gid, attr);
355 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
356 unsigned int index, __always_unused void **context)
358 return set_roce_addr(device, port_num, index, NULL, NULL);
361 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
364 struct ib_gid_attr attr;
367 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
375 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
378 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
381 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
383 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
384 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
389 MLX5_VPORT_ACCESS_METHOD_MAD,
390 MLX5_VPORT_ACCESS_METHOD_HCA,
391 MLX5_VPORT_ACCESS_METHOD_NIC,
394 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
396 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
397 return MLX5_VPORT_ACCESS_METHOD_MAD;
399 if (mlx5_ib_port_link_layer(ibdev, 1) ==
400 IB_LINK_LAYER_ETHERNET)
401 return MLX5_VPORT_ACCESS_METHOD_NIC;
403 return MLX5_VPORT_ACCESS_METHOD_HCA;
406 static void get_atomic_caps(struct mlx5_ib_dev *dev,
407 struct ib_device_attr *props)
410 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
411 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
412 u8 atomic_req_8B_endianness_mode =
413 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
415 /* Check if HW supports 8 bytes standard atomic operations and capable
416 * of host endianness respond
418 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
419 if (((atomic_operations & tmp) == tmp) &&
420 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
421 (atomic_req_8B_endianness_mode)) {
422 props->atomic_cap = IB_ATOMIC_HCA;
424 props->atomic_cap = IB_ATOMIC_NONE;
428 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
429 __be64 *sys_image_guid)
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
432 struct mlx5_core_dev *mdev = dev->mdev;
436 switch (mlx5_get_vport_access_method(ibdev)) {
437 case MLX5_VPORT_ACCESS_METHOD_MAD:
438 return mlx5_query_mad_ifc_system_image_guid(ibdev,
441 case MLX5_VPORT_ACCESS_METHOD_HCA:
442 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
445 case MLX5_VPORT_ACCESS_METHOD_NIC:
446 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
454 *sys_image_guid = cpu_to_be64(tmp);
460 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
463 struct mlx5_ib_dev *dev = to_mdev(ibdev);
464 struct mlx5_core_dev *mdev = dev->mdev;
466 switch (mlx5_get_vport_access_method(ibdev)) {
467 case MLX5_VPORT_ACCESS_METHOD_MAD:
468 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
470 case MLX5_VPORT_ACCESS_METHOD_HCA:
471 case MLX5_VPORT_ACCESS_METHOD_NIC:
472 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
481 static int mlx5_query_vendor_id(struct ib_device *ibdev,
484 struct mlx5_ib_dev *dev = to_mdev(ibdev);
486 switch (mlx5_get_vport_access_method(ibdev)) {
487 case MLX5_VPORT_ACCESS_METHOD_MAD:
488 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
490 case MLX5_VPORT_ACCESS_METHOD_HCA:
491 case MLX5_VPORT_ACCESS_METHOD_NIC:
492 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
499 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
505 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
506 case MLX5_VPORT_ACCESS_METHOD_MAD:
507 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
509 case MLX5_VPORT_ACCESS_METHOD_HCA:
510 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
513 case MLX5_VPORT_ACCESS_METHOD_NIC:
514 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
522 *node_guid = cpu_to_be64(tmp);
527 struct mlx5_reg_node_desc {
528 u8 desc[IB_DEVICE_NODE_DESC_MAX];
531 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
533 struct mlx5_reg_node_desc in;
535 if (mlx5_use_mad_ifc(dev))
536 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
538 memset(&in, 0, sizeof(in));
540 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
541 sizeof(struct mlx5_reg_node_desc),
542 MLX5_REG_NODE_DESC, 0, 0);
545 static int mlx5_ib_query_device(struct ib_device *ibdev,
546 struct ib_device_attr *props,
547 struct ib_udata *uhw)
549 struct mlx5_ib_dev *dev = to_mdev(ibdev);
550 struct mlx5_core_dev *mdev = dev->mdev;
554 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
555 struct mlx5_ib_query_device_resp resp = {};
559 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
560 if (uhw->outlen && uhw->outlen < resp_len)
563 resp.response_length = resp_len;
565 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
568 memset(props, 0, sizeof(*props));
569 err = mlx5_query_system_image_guid(ibdev,
570 &props->sys_image_guid);
574 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
578 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
582 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
583 (fw_rev_min(dev->mdev) << 16) |
584 fw_rev_sub(dev->mdev);
585 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
586 IB_DEVICE_PORT_ACTIVE_EVENT |
587 IB_DEVICE_SYS_IMAGE_GUID |
588 IB_DEVICE_RC_RNR_NAK_GEN;
590 if (MLX5_CAP_GEN(mdev, pkv))
591 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
592 if (MLX5_CAP_GEN(mdev, qkv))
593 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
594 if (MLX5_CAP_GEN(mdev, apm))
595 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
596 if (MLX5_CAP_GEN(mdev, xrc))
597 props->device_cap_flags |= IB_DEVICE_XRC;
598 if (MLX5_CAP_GEN(mdev, imaicl)) {
599 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
600 IB_DEVICE_MEM_WINDOW_TYPE_2B;
601 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
602 /* We support 'Gappy' memory registration too */
603 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
605 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
606 if (MLX5_CAP_GEN(mdev, sho)) {
607 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
608 /* At this stage no support for signature handover */
609 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
610 IB_PROT_T10DIF_TYPE_2 |
611 IB_PROT_T10DIF_TYPE_3;
612 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
613 IB_GUARD_T10DIF_CSUM;
615 if (MLX5_CAP_GEN(mdev, block_lb_mc))
616 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
618 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
619 if (MLX5_CAP_ETH(mdev, csum_cap))
620 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
622 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
623 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
625 resp.tso_caps.max_tso = 1 << max_tso;
626 resp.tso_caps.supported_qpts |=
627 1 << IB_QPT_RAW_PACKET;
628 resp.response_length += sizeof(resp.tso_caps);
632 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
633 resp.rss_caps.rx_hash_function =
634 MLX5_RX_HASH_FUNC_TOEPLITZ;
635 resp.rss_caps.rx_hash_fields_mask =
636 MLX5_RX_HASH_SRC_IPV4 |
637 MLX5_RX_HASH_DST_IPV4 |
638 MLX5_RX_HASH_SRC_IPV6 |
639 MLX5_RX_HASH_DST_IPV6 |
640 MLX5_RX_HASH_SRC_PORT_TCP |
641 MLX5_RX_HASH_DST_PORT_TCP |
642 MLX5_RX_HASH_SRC_PORT_UDP |
643 MLX5_RX_HASH_DST_PORT_UDP;
644 resp.response_length += sizeof(resp.rss_caps);
647 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
648 resp.response_length += sizeof(resp.tso_caps);
649 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
650 resp.response_length += sizeof(resp.rss_caps);
653 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
654 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
655 props->device_cap_flags |= IB_DEVICE_UD_TSO;
658 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
659 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
660 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
662 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
663 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
665 props->vendor_part_id = mdev->pdev->device;
666 props->hw_ver = mdev->pdev->revision;
668 props->max_mr_size = ~0ull;
669 props->page_size_cap = ~(min_page_size - 1);
670 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
671 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
672 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
673 sizeof(struct mlx5_wqe_data_seg);
674 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
675 sizeof(struct mlx5_wqe_ctrl_seg)) /
676 sizeof(struct mlx5_wqe_data_seg);
677 props->max_sge = min(max_rq_sg, max_sq_sg);
678 props->max_sge_rd = MLX5_MAX_SGE_RD;
679 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
680 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
681 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
682 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
683 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
684 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
685 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
686 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
687 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
688 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
689 props->max_srq_sge = max_rq_sg - 1;
690 props->max_fast_reg_page_list_len =
691 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
692 get_atomic_caps(dev, props);
693 props->masked_atomic_cap = IB_ATOMIC_NONE;
694 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
695 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
696 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
697 props->max_mcast_grp;
698 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
699 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
700 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
702 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
703 if (MLX5_CAP_GEN(mdev, pg))
704 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
705 props->odp_caps = dev->odp_caps;
708 if (MLX5_CAP_GEN(mdev, cd))
709 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
711 if (!mlx5_core_is_pf(mdev))
712 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
714 if (mlx5_ib_port_link_layer(ibdev, 1) ==
715 IB_LINK_LAYER_ETHERNET) {
716 props->rss_caps.max_rwq_indirection_tables =
717 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
718 props->rss_caps.max_rwq_indirection_table_size =
719 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
720 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
721 props->max_wq_type_rq =
722 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
726 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
736 MLX5_IB_WIDTH_1X = 1 << 0,
737 MLX5_IB_WIDTH_2X = 1 << 1,
738 MLX5_IB_WIDTH_4X = 1 << 2,
739 MLX5_IB_WIDTH_8X = 1 << 3,
740 MLX5_IB_WIDTH_12X = 1 << 4
743 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
749 if (active_width & MLX5_IB_WIDTH_1X) {
750 *ib_width = IB_WIDTH_1X;
751 } else if (active_width & MLX5_IB_WIDTH_2X) {
752 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
755 } else if (active_width & MLX5_IB_WIDTH_4X) {
756 *ib_width = IB_WIDTH_4X;
757 } else if (active_width & MLX5_IB_WIDTH_8X) {
758 *ib_width = IB_WIDTH_8X;
759 } else if (active_width & MLX5_IB_WIDTH_12X) {
760 *ib_width = IB_WIDTH_12X;
762 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
775 __IB_MAX_VL_0_14 = 5,
778 enum mlx5_vl_hw_cap {
790 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
795 *max_vl_num = __IB_MAX_VL_0;
798 *max_vl_num = __IB_MAX_VL_0_1;
801 *max_vl_num = __IB_MAX_VL_0_3;
804 *max_vl_num = __IB_MAX_VL_0_7;
806 case MLX5_VL_HW_0_14:
807 *max_vl_num = __IB_MAX_VL_0_14;
817 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
818 struct ib_port_attr *props)
820 struct mlx5_ib_dev *dev = to_mdev(ibdev);
821 struct mlx5_core_dev *mdev = dev->mdev;
823 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
824 struct mlx5_ptys_reg *ptys;
825 struct mlx5_pmtu_reg *pmtu;
826 struct mlx5_pvlc_reg pvlc;
830 rep = mlx5_vzalloc(replen);
831 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
832 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
833 if (!rep || !ptys || !pmtu) {
838 memset(props, 0, sizeof(*props));
840 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
844 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
846 props->lid = MLX5_GET(hca_vport_context, ctx, lid);
847 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc);
848 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid);
849 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl);
850 props->state = MLX5_GET(hca_vport_context, ctx, vport_state);
851 props->phys_state = MLX5_GET(hca_vport_context, ctx,
852 port_physical_state);
853 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1);
854 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
855 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
856 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
857 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx,
858 pkey_violation_counter);
859 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx,
860 qkey_violation_counter);
861 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx,
863 props->init_type_reply = MLX5_GET(hca_vport_context, ctx,
865 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required);
867 ptys->proto_mask |= MLX5_PTYS_IB;
868 ptys->local_port = port;
869 err = mlx5_core_access_ptys(mdev, ptys, 0);
873 err = translate_active_width(ibdev, ptys->ib_link_width_oper,
874 &props->active_width);
878 props->active_speed = (u8)ptys->ib_proto_oper;
880 pmtu->local_port = port;
881 err = mlx5_core_access_pmtu(mdev, pmtu, 0);
885 props->max_mtu = pmtu->max_mtu;
886 props->active_mtu = pmtu->oper_mtu;
888 memset(&pvlc, 0, sizeof(pvlc));
889 pvlc.local_port = port;
890 err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
894 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
903 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
904 struct ib_port_attr *props)
906 switch (mlx5_get_vport_access_method(ibdev)) {
907 case MLX5_VPORT_ACCESS_METHOD_MAD:
908 return mlx5_query_mad_ifc_port(ibdev, port, props);
910 case MLX5_VPORT_ACCESS_METHOD_HCA:
911 return mlx5_query_hca_port(ibdev, port, props);
913 case MLX5_VPORT_ACCESS_METHOD_NIC:
914 return mlx5_query_port_roce(ibdev, port, props);
921 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
924 struct mlx5_ib_dev *dev = to_mdev(ibdev);
925 struct mlx5_core_dev *mdev = dev->mdev;
927 switch (mlx5_get_vport_access_method(ibdev)) {
928 case MLX5_VPORT_ACCESS_METHOD_MAD:
929 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
931 case MLX5_VPORT_ACCESS_METHOD_HCA:
932 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
940 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
943 struct mlx5_ib_dev *dev = to_mdev(ibdev);
944 struct mlx5_core_dev *mdev = dev->mdev;
946 switch (mlx5_get_vport_access_method(ibdev)) {
947 case MLX5_VPORT_ACCESS_METHOD_MAD:
948 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
950 case MLX5_VPORT_ACCESS_METHOD_HCA:
951 case MLX5_VPORT_ACCESS_METHOD_NIC:
952 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
959 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
960 struct ib_device_modify *props)
962 struct mlx5_ib_dev *dev = to_mdev(ibdev);
963 struct mlx5_reg_node_desc in;
964 struct mlx5_reg_node_desc out;
967 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
970 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
974 * If possible, pass node desc to FW, so it can generate
975 * a 144 trap. If cmd fails, just ignore.
977 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
978 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
979 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
983 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
988 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
989 struct ib_port_modify *props)
991 struct mlx5_ib_dev *dev = to_mdev(ibdev);
992 struct ib_port_attr attr;
996 mutex_lock(&dev->cap_mask_mutex);
998 err = mlx5_ib_query_port(ibdev, port, &attr);
1002 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1003 ~props->clr_port_cap_mask;
1005 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1008 mutex_unlock(&dev->cap_mask_mutex);
1012 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1013 struct ib_udata *udata)
1015 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1016 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1017 struct mlx5_ib_alloc_ucontext_resp resp = {};
1018 struct mlx5_ib_ucontext *context;
1019 struct mlx5_uuar_info *uuari;
1020 struct mlx5_uar *uars;
1028 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1031 if (!dev->ib_active)
1032 return ERR_PTR(-EAGAIN);
1034 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1035 return ERR_PTR(-EINVAL);
1037 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1038 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1040 else if (reqlen >= min_req_v2)
1043 return ERR_PTR(-EINVAL);
1045 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1047 return ERR_PTR(err);
1050 return ERR_PTR(-EINVAL);
1052 if (req.total_num_uuars > MLX5_MAX_UUARS)
1053 return ERR_PTR(-ENOMEM);
1055 if (req.total_num_uuars == 0)
1056 return ERR_PTR(-EINVAL);
1058 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1059 return ERR_PTR(-EOPNOTSUPP);
1061 if (reqlen > sizeof(req) &&
1062 !ib_is_udata_cleared(udata, sizeof(req),
1063 reqlen - sizeof(req)))
1064 return ERR_PTR(-EOPNOTSUPP);
1066 req.total_num_uuars = ALIGN(req.total_num_uuars,
1067 MLX5_NON_FP_BF_REGS_PER_PAGE);
1068 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1069 return ERR_PTR(-EINVAL);
1071 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1072 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1073 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1074 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1075 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1076 resp.cache_line_size = cache_line_size();
1077 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1078 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1079 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1080 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1081 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1082 resp.cqe_version = min_t(__u8,
1083 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1084 req.max_cqe_version);
1085 resp.response_length = min(offsetof(typeof(resp), response_length) +
1086 sizeof(resp.response_length), udata->outlen);
1088 context = kzalloc(sizeof(*context), GFP_KERNEL);
1090 return ERR_PTR(-ENOMEM);
1092 uuari = &context->uuari;
1093 mutex_init(&uuari->lock);
1094 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1100 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1101 sizeof(*uuari->bitmap),
1103 if (!uuari->bitmap) {
1108 * clear all fast path uuars
1110 for (i = 0; i < gross_uuars; i++) {
1112 if (uuarn == 2 || uuarn == 3)
1113 set_bit(i, uuari->bitmap);
1116 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1117 if (!uuari->count) {
1122 for (i = 0; i < num_uars; i++) {
1123 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1128 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1129 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1132 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1133 err = mlx5_alloc_transport_domain(dev->mdev,
1139 INIT_LIST_HEAD(&context->vma_private_list);
1140 INIT_LIST_HEAD(&context->db_page_list);
1141 mutex_init(&context->db_page_mutex);
1143 resp.tot_uuars = req.total_num_uuars;
1144 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1146 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1147 resp.response_length += sizeof(resp.cqe_version);
1149 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1150 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1151 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1152 resp.response_length += sizeof(resp.cmds_supp_uhw);
1156 * We don't want to expose information from the PCI bar that is located
1157 * after 4096 bytes, so if the arch only supports larger pages, let's
1158 * pretend we don't support reading the HCA's core clock. This is also
1159 * forced by mmap function.
1161 if (PAGE_SIZE <= 4096 &&
1162 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1164 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1165 resp.hca_core_clock_offset =
1166 offsetof(struct mlx5_init_seg, internal_timer_h) %
1168 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1169 sizeof(resp.reserved2);
1172 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1177 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1179 uuari->num_uars = num_uars;
1180 context->cqe_version = resp.cqe_version;
1182 return &context->ibucontext;
1185 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1186 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1189 for (i--; i >= 0; i--)
1190 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1192 kfree(uuari->count);
1195 kfree(uuari->bitmap);
1202 return ERR_PTR(err);
1205 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1207 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1208 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1209 struct mlx5_uuar_info *uuari = &context->uuari;
1212 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1213 mlx5_dealloc_transport_domain(dev->mdev, context->tdn);
1215 for (i = 0; i < uuari->num_uars; i++) {
1216 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1217 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1220 kfree(uuari->count);
1221 kfree(uuari->bitmap);
1228 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1230 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1233 static int get_command(unsigned long offset)
1235 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1238 static int get_arg(unsigned long offset)
1240 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1243 static int get_index(unsigned long offset)
1245 return get_arg(offset);
1248 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1250 /* vma_open is called when a new VMA is created on top of our VMA. This
1251 * is done through either mremap flow or split_vma (usually due to
1252 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1253 * as this VMA is strongly hardware related. Therefore we set the
1254 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1255 * calling us again and trying to do incorrect actions. We assume that
1256 * the original VMA size is exactly a single page, and therefore all
1257 * "splitting" operation will not happen to it.
1259 area->vm_ops = NULL;
1262 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1264 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1266 /* It's guaranteed that all VMAs opened on a FD are closed before the
1267 * file itself is closed, therefore no sync is needed with the regular
1268 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1269 * However need a sync with accessing the vma as part of
1270 * mlx5_ib_disassociate_ucontext.
1271 * The close operation is usually called under mm->mmap_sem except when
1272 * process is exiting.
1273 * The exiting case is handled explicitly as part of
1274 * mlx5_ib_disassociate_ucontext.
1276 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1278 /* setting the vma context pointer to null in the mlx5_ib driver's
1279 * private data, to protect a race condition in
1280 * mlx5_ib_disassociate_ucontext().
1282 mlx5_ib_vma_priv_data->vma = NULL;
1283 list_del(&mlx5_ib_vma_priv_data->list);
1284 kfree(mlx5_ib_vma_priv_data);
1287 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1288 .open = mlx5_ib_vma_open,
1289 .close = mlx5_ib_vma_close
1292 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1293 struct mlx5_ib_ucontext *ctx)
1295 struct mlx5_ib_vma_private_data *vma_prv;
1296 struct list_head *vma_head = &ctx->vma_private_list;
1298 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1303 vma->vm_private_data = vma_prv;
1304 vma->vm_ops = &mlx5_ib_vm_ops;
1306 list_add(&vma_prv->list, vma_head);
1311 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1314 case MLX5_IB_MMAP_WC_PAGE:
1316 case MLX5_IB_MMAP_REGULAR_PAGE:
1317 return "best effort WC";
1318 case MLX5_IB_MMAP_NC_PAGE:
1325 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1326 struct vm_area_struct *vma,
1327 struct mlx5_ib_ucontext *context)
1329 struct mlx5_uuar_info *uuari = &context->uuari;
1332 phys_addr_t pfn, pa;
1336 case MLX5_IB_MMAP_WC_PAGE:
1337 /* Some architectures don't support WC memory */
1338 #if defined(CONFIG_X86)
1341 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1345 case MLX5_IB_MMAP_REGULAR_PAGE:
1346 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1347 prot = pgprot_writecombine(vma->vm_page_prot);
1349 case MLX5_IB_MMAP_NC_PAGE:
1350 prot = pgprot_noncached(vma->vm_page_prot);
1356 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1359 idx = get_index(vma->vm_pgoff);
1360 if (idx >= uuari->num_uars)
1363 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1364 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1366 vma->vm_page_prot = prot;
1367 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1368 PAGE_SIZE, vma->vm_page_prot);
1370 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n",
1371 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd));
1375 pa = pfn << PAGE_SHIFT;
1376 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd),
1377 (unsigned long long)vma->vm_start, &pa);
1379 return mlx5_ib_set_vma_data(vma, context);
1382 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1384 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1385 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1386 unsigned long command;
1389 command = get_command(vma->vm_pgoff);
1391 case MLX5_IB_MMAP_WC_PAGE:
1392 case MLX5_IB_MMAP_NC_PAGE:
1393 case MLX5_IB_MMAP_REGULAR_PAGE:
1394 return uar_mmap(dev, command, vma, context);
1396 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1399 case MLX5_IB_MMAP_CORE_CLOCK:
1400 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1403 if (vma->vm_flags & VM_WRITE)
1406 /* Don't expose to user-space information it shouldn't have */
1407 if (PAGE_SIZE > 4096)
1410 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1411 pfn = (dev->mdev->iseg_base +
1412 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1414 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1415 PAGE_SIZE, vma->vm_page_prot))
1418 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n",
1419 (unsigned long long)vma->vm_start,
1420 (unsigned long long)pfn << PAGE_SHIFT);
1430 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1431 struct ib_ucontext *context,
1432 struct ib_udata *udata)
1434 struct mlx5_ib_alloc_pd_resp resp;
1435 struct mlx5_ib_pd *pd;
1438 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1440 return ERR_PTR(-ENOMEM);
1442 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1445 return ERR_PTR(err);
1450 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1451 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1453 return ERR_PTR(-EFAULT);
1460 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1462 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1463 struct mlx5_ib_pd *mpd = to_mpd(pd);
1465 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1472 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1473 MATCH_CRITERIA_ENABLE_MISC_BIT,
1474 MATCH_CRITERIA_ENABLE_INNER_BIT
1477 #define HEADER_IS_ZERO(match_criteria, headers) \
1478 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1479 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1481 static u8 get_match_criteria_enable(u32 *match_criteria)
1483 u8 match_criteria_enable;
1485 match_criteria_enable =
1486 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1487 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1488 match_criteria_enable |=
1489 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1490 MATCH_CRITERIA_ENABLE_MISC_BIT;
1491 match_criteria_enable |=
1492 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1493 MATCH_CRITERIA_ENABLE_INNER_BIT;
1495 return match_criteria_enable;
1498 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1500 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1501 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1504 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1506 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1507 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1508 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1509 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1512 #define LAST_ETH_FIELD vlan_tag
1513 #define LAST_IB_FIELD sl
1514 #define LAST_IPV4_FIELD tos
1515 #define LAST_IPV6_FIELD traffic_class
1516 #define LAST_TCP_UDP_FIELD src_port
1518 /* Field is the last supported field */
1519 #define FIELDS_NOT_SUPPORTED(filter, field)\
1520 memchr_inv((void *)&filter.field +\
1521 sizeof(filter.field), 0,\
1523 offsetof(typeof(filter), field) -\
1524 sizeof(filter.field))
1526 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1527 const union ib_flow_spec *ib_spec)
1529 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1531 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1533 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1535 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1538 switch (ib_spec->type) {
1539 case IB_FLOW_SPEC_ETH:
1540 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1543 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1545 ib_spec->eth.mask.dst_mac);
1546 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1548 ib_spec->eth.val.dst_mac);
1550 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1552 ib_spec->eth.mask.src_mac);
1553 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1555 ib_spec->eth.val.src_mac);
1557 if (ib_spec->eth.mask.vlan_tag) {
1558 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1560 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1563 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1564 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1565 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1566 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1568 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1570 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1571 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1573 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1575 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1577 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1578 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1580 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1582 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1583 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1584 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1585 ethertype, ntohs(ib_spec->eth.val.ether_type));
1587 case IB_FLOW_SPEC_IPV4:
1588 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1591 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1593 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1594 ethertype, ETH_P_IP);
1596 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1597 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1598 &ib_spec->ipv4.mask.src_ip,
1599 sizeof(ib_spec->ipv4.mask.src_ip));
1600 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1601 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1602 &ib_spec->ipv4.val.src_ip,
1603 sizeof(ib_spec->ipv4.val.src_ip));
1604 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1605 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1606 &ib_spec->ipv4.mask.dst_ip,
1607 sizeof(ib_spec->ipv4.mask.dst_ip));
1608 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1609 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1610 &ib_spec->ipv4.val.dst_ip,
1611 sizeof(ib_spec->ipv4.val.dst_ip));
1613 set_tos(outer_headers_c, outer_headers_v,
1614 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1616 set_proto(outer_headers_c, outer_headers_v,
1617 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1619 case IB_FLOW_SPEC_IPV6:
1620 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1623 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1625 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1626 ethertype, IPPROTO_IPV6);
1628 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1629 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1630 &ib_spec->ipv6.mask.src_ip,
1631 sizeof(ib_spec->ipv6.mask.src_ip));
1632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1633 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1634 &ib_spec->ipv6.val.src_ip,
1635 sizeof(ib_spec->ipv6.val.src_ip));
1636 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1637 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1638 &ib_spec->ipv6.mask.dst_ip,
1639 sizeof(ib_spec->ipv6.mask.dst_ip));
1640 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1641 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1642 &ib_spec->ipv6.val.dst_ip,
1643 sizeof(ib_spec->ipv6.val.dst_ip));
1645 set_tos(outer_headers_c, outer_headers_v,
1646 ib_spec->ipv6.mask.traffic_class,
1647 ib_spec->ipv6.val.traffic_class);
1649 set_proto(outer_headers_c, outer_headers_v,
1650 ib_spec->ipv6.mask.next_hdr,
1651 ib_spec->ipv6.val.next_hdr);
1653 MLX5_SET(fte_match_set_misc, misc_params_c,
1654 outer_ipv6_flow_label,
1655 ntohl(ib_spec->ipv6.mask.flow_label));
1656 MLX5_SET(fte_match_set_misc, misc_params_v,
1657 outer_ipv6_flow_label,
1658 ntohl(ib_spec->ipv6.val.flow_label));
1660 case IB_FLOW_SPEC_TCP:
1661 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1662 LAST_TCP_UDP_FIELD))
1665 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1667 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1670 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1671 ntohs(ib_spec->tcp_udp.mask.src_port));
1672 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1673 ntohs(ib_spec->tcp_udp.val.src_port));
1675 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1676 ntohs(ib_spec->tcp_udp.mask.dst_port));
1677 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1678 ntohs(ib_spec->tcp_udp.val.dst_port));
1680 case IB_FLOW_SPEC_UDP:
1681 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1682 LAST_TCP_UDP_FIELD))
1685 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1687 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1690 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1691 ntohs(ib_spec->tcp_udp.mask.src_port));
1692 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1693 ntohs(ib_spec->tcp_udp.val.src_port));
1695 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1696 ntohs(ib_spec->tcp_udp.mask.dst_port));
1697 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1698 ntohs(ib_spec->tcp_udp.val.dst_port));
1707 /* If a flow could catch both multicast and unicast packets,
1708 * it won't fall into the multicast flow steering table and this rule
1709 * could steal other multicast packets.
1711 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1713 struct ib_flow_spec_eth *eth_spec;
1715 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1716 ib_attr->size < sizeof(struct ib_flow_attr) +
1717 sizeof(struct ib_flow_spec_eth) ||
1718 ib_attr->num_of_specs < 1)
1721 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1722 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1723 eth_spec->size != sizeof(*eth_spec))
1726 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1727 is_multicast_ether_addr(eth_spec->val.dst_mac);
1730 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1732 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1733 bool has_ipv4_spec = false;
1734 bool eth_type_ipv4 = true;
1735 unsigned int spec_index;
1737 /* Validate that ethertype is correct */
1738 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1739 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1740 ib_spec->eth.mask.ether_type) {
1741 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1742 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1743 eth_type_ipv4 = false;
1744 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1745 has_ipv4_spec = true;
1747 ib_spec = (void *)ib_spec + ib_spec->size;
1749 return !has_ipv4_spec || eth_type_ipv4;
1752 static void put_flow_table(struct mlx5_ib_dev *dev,
1753 struct mlx5_ib_flow_prio *prio, bool ft_added)
1755 prio->refcount -= !!ft_added;
1756 if (!prio->refcount) {
1757 mlx5_destroy_flow_table(prio->flow_table);
1758 prio->flow_table = NULL;
1762 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1764 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1765 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1766 struct mlx5_ib_flow_handler,
1768 struct mlx5_ib_flow_handler *iter, *tmp;
1770 mutex_lock(&dev->flow_db.lock);
1772 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1773 mlx5_del_flow_rule(iter->rule);
1774 put_flow_table(dev, iter->prio, true);
1775 list_del(&iter->list);
1779 mlx5_del_flow_rule(handler->rule);
1780 put_flow_table(dev, handler->prio, true);
1781 mutex_unlock(&dev->flow_db.lock);
1788 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1796 enum flow_table_type {
1801 #define MLX5_FS_MAX_TYPES 10
1802 #define MLX5_FS_MAX_ENTRIES 32000UL
1803 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1804 struct ib_flow_attr *flow_attr,
1805 enum flow_table_type ft_type)
1807 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1808 struct mlx5_flow_namespace *ns = NULL;
1809 struct mlx5_ib_flow_prio *prio;
1810 struct mlx5_flow_table *ft;
1816 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1817 if (flow_is_multicast_only(flow_attr) &&
1819 priority = MLX5_IB_FLOW_MCAST_PRIO;
1821 priority = ib_prio_to_core_prio(flow_attr->priority,
1823 ns = mlx5_get_flow_namespace(dev->mdev,
1824 MLX5_FLOW_NAMESPACE_BYPASS);
1825 num_entries = MLX5_FS_MAX_ENTRIES;
1826 num_groups = MLX5_FS_MAX_TYPES;
1827 prio = &dev->flow_db.prios[priority];
1828 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1829 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1830 ns = mlx5_get_flow_namespace(dev->mdev,
1831 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1832 build_leftovers_ft_param("bypass", &priority,
1835 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1836 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1837 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1838 allow_sniffer_and_nic_rx_shared_tir))
1839 return ERR_PTR(-ENOTSUPP);
1841 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1842 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1843 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1845 prio = &dev->flow_db.sniffer[ft_type];
1852 return ERR_PTR(-ENOTSUPP);
1854 ft = prio->flow_table;
1856 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass",
1862 prio->flow_table = ft;
1868 return err ? ERR_PTR(err) : prio;
1871 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1872 struct mlx5_ib_flow_prio *ft_prio,
1873 const struct ib_flow_attr *flow_attr,
1874 struct mlx5_flow_destination *dst)
1876 struct mlx5_flow_table *ft = ft_prio->flow_table;
1877 struct mlx5_ib_flow_handler *handler;
1878 struct mlx5_flow_spec *spec;
1879 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1880 unsigned int spec_index;
1884 if (!is_valid_attr(flow_attr))
1885 return ERR_PTR(-EINVAL);
1887 spec = mlx5_vzalloc(sizeof(*spec));
1888 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1889 if (!handler || !spec) {
1894 INIT_LIST_HEAD(&handler->list);
1896 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1897 err = parse_flow_attr(spec->match_criteria,
1898 spec->match_value, ib_flow);
1902 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1905 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1906 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1907 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1908 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable,
1909 spec->match_criteria,
1912 MLX5_FS_DEFAULT_FLOW_TAG,
1915 if (IS_ERR(handler->rule)) {
1916 err = PTR_ERR(handler->rule);
1920 ft_prio->refcount++;
1921 handler->prio = ft_prio;
1923 ft_prio->flow_table = ft;
1928 return err ? ERR_PTR(err) : handler;
1931 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1932 struct mlx5_ib_flow_prio *ft_prio,
1933 struct ib_flow_attr *flow_attr,
1934 struct mlx5_flow_destination *dst)
1936 struct mlx5_ib_flow_handler *handler_dst = NULL;
1937 struct mlx5_ib_flow_handler *handler = NULL;
1939 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1940 if (!IS_ERR(handler)) {
1941 handler_dst = create_flow_rule(dev, ft_prio,
1943 if (IS_ERR(handler_dst)) {
1944 mlx5_del_flow_rule(handler->rule);
1945 ft_prio->refcount--;
1947 handler = handler_dst;
1949 list_add(&handler_dst->list, &handler->list);
1960 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1961 struct mlx5_ib_flow_prio *ft_prio,
1962 struct ib_flow_attr *flow_attr,
1963 struct mlx5_flow_destination *dst)
1965 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1966 struct mlx5_ib_flow_handler *handler = NULL;
1969 struct ib_flow_attr flow_attr;
1970 struct ib_flow_spec_eth eth_flow;
1971 } leftovers_specs[] = {
1975 .size = sizeof(leftovers_specs[0])
1978 .type = IB_FLOW_SPEC_ETH,
1979 .size = sizeof(struct ib_flow_spec_eth),
1980 .mask = {.dst_mac = {0x1} },
1981 .val = {.dst_mac = {0x1} }
1987 .size = sizeof(leftovers_specs[0])
1990 .type = IB_FLOW_SPEC_ETH,
1991 .size = sizeof(struct ib_flow_spec_eth),
1992 .mask = {.dst_mac = {0x1} },
1993 .val = {.dst_mac = {} }
1998 handler = create_flow_rule(dev, ft_prio,
1999 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2001 if (!IS_ERR(handler) &&
2002 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2003 handler_ucast = create_flow_rule(dev, ft_prio,
2004 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2006 if (IS_ERR(handler_ucast)) {
2007 mlx5_del_flow_rule(handler->rule);
2008 ft_prio->refcount--;
2010 handler = handler_ucast;
2012 list_add(&handler_ucast->list, &handler->list);
2019 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2020 struct mlx5_ib_flow_prio *ft_rx,
2021 struct mlx5_ib_flow_prio *ft_tx,
2022 struct mlx5_flow_destination *dst)
2024 struct mlx5_ib_flow_handler *handler_rx;
2025 struct mlx5_ib_flow_handler *handler_tx;
2027 static const struct ib_flow_attr flow_attr = {
2029 .size = sizeof(flow_attr)
2032 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2033 if (IS_ERR(handler_rx)) {
2034 err = PTR_ERR(handler_rx);
2038 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2039 if (IS_ERR(handler_tx)) {
2040 err = PTR_ERR(handler_tx);
2044 list_add(&handler_tx->list, &handler_rx->list);
2049 mlx5_del_flow_rule(handler_rx->rule);
2053 return ERR_PTR(err);
2056 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2057 struct ib_flow_attr *flow_attr,
2060 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2061 struct mlx5_ib_qp *mqp = to_mqp(qp);
2062 struct mlx5_ib_flow_handler *handler = NULL;
2063 struct mlx5_flow_destination *dst = NULL;
2064 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2065 struct mlx5_ib_flow_prio *ft_prio;
2068 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2069 return ERR_PTR(-ENOSPC);
2071 if (domain != IB_FLOW_DOMAIN_USER ||
2072 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2073 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2074 return ERR_PTR(-EINVAL);
2076 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2078 return ERR_PTR(-ENOMEM);
2080 mutex_lock(&dev->flow_db.lock);
2082 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2083 if (IS_ERR(ft_prio)) {
2084 err = PTR_ERR(ft_prio);
2087 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2088 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2089 if (IS_ERR(ft_prio_tx)) {
2090 err = PTR_ERR(ft_prio_tx);
2096 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2097 if (mqp->flags & MLX5_IB_QP_RSS)
2098 dst->tir_num = mqp->rss_qp.tirn;
2100 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2102 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2103 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2104 handler = create_dont_trap_rule(dev, ft_prio,
2107 handler = create_flow_rule(dev, ft_prio, flow_attr,
2110 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2111 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2112 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2114 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2115 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2121 if (IS_ERR(handler)) {
2122 err = PTR_ERR(handler);
2127 mutex_unlock(&dev->flow_db.lock);
2130 return &handler->ibflow;
2133 put_flow_table(dev, ft_prio, false);
2135 put_flow_table(dev, ft_prio_tx, false);
2137 mutex_unlock(&dev->flow_db.lock);
2140 return ERR_PTR(err);
2143 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2145 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2148 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2150 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2151 ibqp->qp_num, gid->raw);
2156 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2158 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2161 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2163 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2164 ibqp->qp_num, gid->raw);
2169 static int init_node_data(struct mlx5_ib_dev *dev)
2173 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2177 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2180 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2183 struct mlx5_ib_dev *dev =
2184 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2186 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2189 static ssize_t show_reg_pages(struct device *device,
2190 struct device_attribute *attr, char *buf)
2192 struct mlx5_ib_dev *dev =
2193 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2195 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2198 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2201 struct mlx5_ib_dev *dev =
2202 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2203 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2206 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2209 struct mlx5_ib_dev *dev =
2210 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2211 return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2214 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2217 struct mlx5_ib_dev *dev =
2218 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2219 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2220 dev->mdev->board_id);
2223 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2224 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2225 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2226 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2227 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2229 static struct device_attribute *mlx5_class_attributes[] = {
2234 &dev_attr_reg_pages,
2237 static void pkey_change_handler(struct work_struct *work)
2239 struct mlx5_ib_port_resources *ports =
2240 container_of(work, struct mlx5_ib_port_resources,
2243 mutex_lock(&ports->devr->mutex);
2244 mlx5_ib_gsi_pkey_change(ports->gsi);
2245 mutex_unlock(&ports->devr->mutex);
2248 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2250 struct mlx5_ib_qp *mqp;
2251 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2252 struct mlx5_core_cq *mcq;
2253 struct list_head cq_armed_list;
2254 unsigned long flags_qp;
2255 unsigned long flags_cq;
2256 unsigned long flags;
2258 INIT_LIST_HEAD(&cq_armed_list);
2260 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2261 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2262 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2263 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2264 if (mqp->sq.tail != mqp->sq.head) {
2265 send_mcq = to_mcq(mqp->ibqp.send_cq);
2266 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2267 if (send_mcq->mcq.comp &&
2268 mqp->ibqp.send_cq->comp_handler) {
2269 if (!send_mcq->mcq.reset_notify_added) {
2270 send_mcq->mcq.reset_notify_added = 1;
2271 list_add_tail(&send_mcq->mcq.reset_notify,
2275 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2277 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2278 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2279 /* no handling is needed for SRQ */
2280 if (!mqp->ibqp.srq) {
2281 if (mqp->rq.tail != mqp->rq.head) {
2282 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2283 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2284 if (recv_mcq->mcq.comp &&
2285 mqp->ibqp.recv_cq->comp_handler) {
2286 if (!recv_mcq->mcq.reset_notify_added) {
2287 recv_mcq->mcq.reset_notify_added = 1;
2288 list_add_tail(&recv_mcq->mcq.reset_notify,
2292 spin_unlock_irqrestore(&recv_mcq->lock,
2296 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2298 /*At that point all inflight post send were put to be executed as of we
2299 * lock/unlock above locks Now need to arm all involved CQs.
2301 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2304 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2307 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2308 enum mlx5_dev_event event, unsigned long param)
2310 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2311 struct ib_event ibev;
2316 case MLX5_DEV_EVENT_SYS_ERROR:
2317 ibev.event = IB_EVENT_DEVICE_FATAL;
2318 mlx5_ib_handle_internal_error(ibdev);
2322 case MLX5_DEV_EVENT_PORT_UP:
2323 case MLX5_DEV_EVENT_PORT_DOWN:
2324 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2327 /* In RoCE, port up/down events are handled in
2328 * mlx5_netdev_event().
2330 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2331 IB_LINK_LAYER_ETHERNET)
2334 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2335 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2338 case MLX5_DEV_EVENT_LID_CHANGE:
2339 ibev.event = IB_EVENT_LID_CHANGE;
2343 case MLX5_DEV_EVENT_PKEY_CHANGE:
2344 ibev.event = IB_EVENT_PKEY_CHANGE;
2347 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2350 case MLX5_DEV_EVENT_GUID_CHANGE:
2351 ibev.event = IB_EVENT_GID_CHANGE;
2355 case MLX5_DEV_EVENT_CLIENT_REREG:
2356 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2364 ibev.device = &ibdev->ib_dev;
2365 ibev.element.port_num = port;
2367 if (port < 1 || port > ibdev->num_ports) {
2368 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2372 if (ibdev->ib_active)
2373 ib_dispatch_event(&ibev);
2376 ibdev->ib_active = false;
2379 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2383 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2384 mlx5_query_ext_port_caps(dev, port);
2387 static int get_port_caps(struct mlx5_ib_dev *dev)
2389 struct ib_device_attr *dprops = NULL;
2390 struct ib_port_attr *pprops = NULL;
2393 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2395 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2399 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2403 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2405 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2409 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2410 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2412 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2416 dev->mdev->port_caps[port - 1].pkey_table_len =
2418 dev->mdev->port_caps[port - 1].gid_table_len =
2419 pprops->gid_tbl_len;
2420 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2421 dprops->max_pkeys, pprops->gid_tbl_len);
2431 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2435 err = mlx5_mr_cache_cleanup(dev);
2437 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2439 mlx5_ib_destroy_qp(dev->umrc.qp);
2440 ib_free_cq(dev->umrc.cq);
2441 ib_dealloc_pd(dev->umrc.pd);
2448 static int create_umr_res(struct mlx5_ib_dev *dev)
2450 struct ib_qp_init_attr *init_attr = NULL;
2451 struct ib_qp_attr *attr = NULL;
2457 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2458 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2459 if (!attr || !init_attr) {
2464 pd = ib_alloc_pd(&dev->ib_dev, 0);
2466 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2471 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2473 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2478 init_attr->send_cq = cq;
2479 init_attr->recv_cq = cq;
2480 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2481 init_attr->cap.max_send_wr = MAX_UMR_WR;
2482 init_attr->cap.max_send_sge = 1;
2483 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2484 init_attr->port_num = 1;
2485 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2487 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2491 qp->device = &dev->ib_dev;
2494 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2496 attr->qp_state = IB_QPS_INIT;
2498 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2501 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2505 memset(attr, 0, sizeof(*attr));
2506 attr->qp_state = IB_QPS_RTR;
2507 attr->path_mtu = IB_MTU_256;
2509 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2511 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2515 memset(attr, 0, sizeof(*attr));
2516 attr->qp_state = IB_QPS_RTS;
2517 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2519 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2527 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2528 ret = mlx5_mr_cache_init(dev);
2530 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2540 mlx5_ib_destroy_qp(qp);
2554 static int create_dev_resources(struct mlx5_ib_resources *devr)
2556 struct ib_srq_init_attr attr;
2557 struct mlx5_ib_dev *dev;
2558 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2562 dev = container_of(devr, struct mlx5_ib_dev, devr);
2564 mutex_init(&devr->mutex);
2566 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2567 if (IS_ERR(devr->p0)) {
2568 ret = PTR_ERR(devr->p0);
2571 devr->p0->device = &dev->ib_dev;
2572 devr->p0->uobject = NULL;
2573 atomic_set(&devr->p0->usecnt, 0);
2575 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2576 if (IS_ERR(devr->c0)) {
2577 ret = PTR_ERR(devr->c0);
2580 devr->c0->device = &dev->ib_dev;
2581 devr->c0->uobject = NULL;
2582 devr->c0->comp_handler = NULL;
2583 devr->c0->event_handler = NULL;
2584 devr->c0->cq_context = NULL;
2585 atomic_set(&devr->c0->usecnt, 0);
2587 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2588 if (IS_ERR(devr->x0)) {
2589 ret = PTR_ERR(devr->x0);
2592 devr->x0->device = &dev->ib_dev;
2593 devr->x0->inode = NULL;
2594 atomic_set(&devr->x0->usecnt, 0);
2595 mutex_init(&devr->x0->tgt_qp_mutex);
2596 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2598 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2599 if (IS_ERR(devr->x1)) {
2600 ret = PTR_ERR(devr->x1);
2603 devr->x1->device = &dev->ib_dev;
2604 devr->x1->inode = NULL;
2605 atomic_set(&devr->x1->usecnt, 0);
2606 mutex_init(&devr->x1->tgt_qp_mutex);
2607 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2609 memset(&attr, 0, sizeof(attr));
2610 attr.attr.max_sge = 1;
2611 attr.attr.max_wr = 1;
2612 attr.srq_type = IB_SRQT_XRC;
2613 attr.ext.xrc.cq = devr->c0;
2614 attr.ext.xrc.xrcd = devr->x0;
2616 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2617 if (IS_ERR(devr->s0)) {
2618 ret = PTR_ERR(devr->s0);
2621 devr->s0->device = &dev->ib_dev;
2622 devr->s0->pd = devr->p0;
2623 devr->s0->uobject = NULL;
2624 devr->s0->event_handler = NULL;
2625 devr->s0->srq_context = NULL;
2626 devr->s0->srq_type = IB_SRQT_XRC;
2627 devr->s0->ext.xrc.xrcd = devr->x0;
2628 devr->s0->ext.xrc.cq = devr->c0;
2629 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2630 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2631 atomic_inc(&devr->p0->usecnt);
2632 atomic_set(&devr->s0->usecnt, 0);
2634 memset(&attr, 0, sizeof(attr));
2635 attr.attr.max_sge = 1;
2636 attr.attr.max_wr = 1;
2637 attr.srq_type = IB_SRQT_BASIC;
2638 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2639 if (IS_ERR(devr->s1)) {
2640 ret = PTR_ERR(devr->s1);
2643 devr->s1->device = &dev->ib_dev;
2644 devr->s1->pd = devr->p0;
2645 devr->s1->uobject = NULL;
2646 devr->s1->event_handler = NULL;
2647 devr->s1->srq_context = NULL;
2648 devr->s1->srq_type = IB_SRQT_BASIC;
2649 devr->s1->ext.xrc.cq = devr->c0;
2650 atomic_inc(&devr->p0->usecnt);
2651 atomic_set(&devr->s0->usecnt, 0);
2653 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2654 INIT_WORK(&devr->ports[port].pkey_change_work,
2655 pkey_change_handler);
2656 devr->ports[port].devr = devr;
2662 mlx5_ib_destroy_srq(devr->s0);
2664 mlx5_ib_dealloc_xrcd(devr->x1);
2666 mlx5_ib_dealloc_xrcd(devr->x0);
2668 mlx5_ib_destroy_cq(devr->c0);
2670 mlx5_ib_dealloc_pd(devr->p0);
2675 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2677 struct mlx5_ib_dev *dev =
2678 container_of(devr, struct mlx5_ib_dev, devr);
2681 mlx5_ib_destroy_srq(devr->s1);
2682 mlx5_ib_destroy_srq(devr->s0);
2683 mlx5_ib_dealloc_xrcd(devr->x0);
2684 mlx5_ib_dealloc_xrcd(devr->x1);
2685 mlx5_ib_destroy_cq(devr->c0);
2686 mlx5_ib_dealloc_pd(devr->p0);
2688 /* Make sure no change P_Key work items are still executing */
2689 for (port = 0; port < dev->num_ports; ++port)
2690 cancel_work_sync(&devr->ports[port].pkey_change_work);
2693 static u32 get_core_cap_flags(struct ib_device *ibdev)
2695 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2696 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2697 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2698 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2701 if (ll == IB_LINK_LAYER_INFINIBAND)
2702 return RDMA_CORE_PORT_IBA_IB;
2704 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2707 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2710 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2711 ret |= RDMA_CORE_PORT_IBA_ROCE;
2713 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2714 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2719 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2720 struct ib_port_immutable *immutable)
2722 struct ib_port_attr attr;
2725 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2729 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2730 immutable->gid_tbl_len = attr.gid_tbl_len;
2731 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2732 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2737 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2740 struct mlx5_ib_dev *dev =
2741 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2742 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2743 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2746 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2751 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2755 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2757 if (dev->roce.nb.notifier_call) {
2758 unregister_netdevice_notifier(&dev->roce.nb);
2759 dev->roce.nb.notifier_call = NULL;
2763 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2765 VNET_ITERATOR_DECL(vnet_iter);
2766 struct net_device *idev;
2769 /* Check if mlx5en net device already exists */
2771 VNET_FOREACH(vnet_iter) {
2773 CURVNET_SET_QUIET(vnet_iter);
2774 TAILQ_FOREACH(idev, &V_ifnet, if_link) {
2775 /* check if network interface belongs to mlx5en */
2776 if (!mlx5_netdev_match(idev, dev->mdev, "mce"))
2778 write_lock(&dev->roce.netdev_lock);
2779 dev->roce.netdev = idev;
2780 write_unlock(&dev->roce.netdev_lock);
2785 VNET_LIST_RUNLOCK();
2787 dev->roce.nb.notifier_call = mlx5_netdev_event;
2788 err = register_netdevice_notifier(&dev->roce.nb);
2790 dev->roce.nb.notifier_call = NULL;
2794 err = mlx5_nic_vport_enable_roce(dev->mdev);
2796 goto err_unregister_netdevice_notifier;
2798 err = mlx5_roce_lag_init(dev);
2800 goto err_disable_roce;
2805 mlx5_nic_vport_disable_roce(dev->mdev);
2807 err_unregister_netdevice_notifier:
2808 mlx5_remove_roce_notifier(dev);
2812 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2814 mlx5_roce_lag_cleanup(dev);
2815 mlx5_nic_vport_disable_roce(dev->mdev);
2818 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
2820 mlx5_vport_dealloc_q_counter(dev->mdev,
2821 MLX5_INTERFACE_PROTOCOL_IB,
2822 dev->port[port_num].q_cnt_id);
2823 dev->port[port_num].q_cnt_id = 0;
2826 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2830 for (i = 0; i < dev->num_ports; i++)
2831 mlx5_ib_dealloc_q_port_counter(dev, i);
2834 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2839 for (i = 0; i < dev->num_ports; i++) {
2840 ret = mlx5_vport_alloc_q_counter(dev->mdev,
2841 MLX5_INTERFACE_PROTOCOL_IB,
2842 &dev->port[i].q_cnt_id);
2845 "couldn't allocate queue counter for port %d, err %d\n",
2847 goto dealloc_counters;
2855 mlx5_ib_dealloc_q_port_counter(dev, i);
2860 static const char * const names[] = {
2861 "rx_write_requests",
2863 "rx_atomic_requests",
2866 "duplicate_request",
2867 "rnr_nak_retry_err",
2869 "implied_nak_seq_err",
2870 "local_ack_timeout_err",
2873 static const size_t stats_offsets[] = {
2874 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2875 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2876 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2877 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2878 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2879 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2880 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2881 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2882 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2883 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2886 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2889 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2891 /* We support only per port stats */
2895 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2896 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2899 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2900 struct rdma_hw_stats *stats,
2903 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2904 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2910 if (!port || !stats)
2913 out = mlx5_vzalloc(outlen);
2917 ret = mlx5_vport_query_q_counter(dev->mdev,
2918 dev->port[port - 1].q_cnt_id, 0,
2923 for (i = 0; i < ARRAY_SIZE(names); i++) {
2924 val = *(__be32 *)(out + stats_offsets[i]);
2925 stats->value[i] = (u64)be32_to_cpu(val);
2929 return ARRAY_SIZE(names);
2932 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2934 struct mlx5_ib_dev *dev;
2935 enum rdma_link_layer ll;
2941 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2942 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2944 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2947 printk_once(KERN_INFO "%s", mlx5_version);
2949 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2955 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2960 rwlock_init(&dev->roce.netdev_lock);
2961 err = get_port_caps(dev);
2965 if (mlx5_use_mad_ifc(dev))
2966 get_ext_port_caps(dev);
2968 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2972 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2973 dev->ib_dev.owner = THIS_MODULE;
2974 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
2975 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
2976 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
2977 dev->ib_dev.phys_port_cnt = dev->num_ports;
2978 dev->ib_dev.num_comp_vectors =
2979 dev->mdev->priv.eq_table.num_comp_vectors;
2980 dev->ib_dev.dma_device = &mdev->pdev->dev;
2982 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2983 dev->ib_dev.uverbs_cmd_mask =
2984 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2985 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2986 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2987 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2988 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2989 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2990 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2991 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2992 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2993 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2994 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2995 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2996 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2997 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2998 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2999 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3000 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3001 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3002 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3003 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3004 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3005 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3006 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3007 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3008 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3009 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3010 dev->ib_dev.uverbs_ex_cmd_mask =
3011 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3012 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3013 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3015 dev->ib_dev.query_device = mlx5_ib_query_device;
3016 dev->ib_dev.query_port = mlx5_ib_query_port;
3017 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3018 if (ll == IB_LINK_LAYER_ETHERNET)
3019 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3020 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3021 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3022 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3023 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3024 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3025 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3026 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3027 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3028 dev->ib_dev.mmap = mlx5_ib_mmap;
3029 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3030 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3031 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3032 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3033 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3034 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3035 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3036 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3037 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3038 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3039 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3040 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3041 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3042 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3043 dev->ib_dev.post_send = mlx5_ib_post_send;
3044 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3045 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3046 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3047 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3048 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3049 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3050 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3051 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3052 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3053 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3054 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3055 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3056 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3057 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3058 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3059 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3060 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3061 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3062 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3063 if (mlx5_core_is_pf(mdev)) {
3064 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3065 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3066 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3067 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3070 mlx5_ib_internal_fill_odp_caps(dev);
3072 if (MLX5_CAP_GEN(mdev, imaicl)) {
3073 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3074 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3075 dev->ib_dev.uverbs_cmd_mask |=
3076 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3077 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3080 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3081 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3082 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3083 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3086 if (MLX5_CAP_GEN(mdev, xrc)) {
3087 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3088 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3089 dev->ib_dev.uverbs_cmd_mask |=
3090 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3091 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3094 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3095 IB_LINK_LAYER_ETHERNET) {
3096 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3097 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3098 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3099 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3100 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3101 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3102 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3103 dev->ib_dev.uverbs_ex_cmd_mask |=
3104 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3105 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3106 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3107 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3108 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3109 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3110 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3112 err = init_node_data(dev);
3116 mutex_init(&dev->flow_db.lock);
3117 mutex_init(&dev->cap_mask_mutex);
3118 INIT_LIST_HEAD(&dev->qp_list);
3119 spin_lock_init(&dev->reset_flow_resource_lock);
3121 if (ll == IB_LINK_LAYER_ETHERNET) {
3122 err = mlx5_enable_roce(dev);
3127 err = create_dev_resources(&dev->devr);
3129 goto err_disable_roce;
3131 err = mlx5_ib_odp_init_one(dev);
3135 err = mlx5_ib_alloc_q_counters(dev);
3139 err = ib_register_device(&dev->ib_dev, NULL);
3143 err = create_umr_res(dev);
3147 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3148 err = device_create_file(&dev->ib_dev.dev,
3149 mlx5_class_attributes[i]);
3154 err = mlx5_ib_init_congestion(dev);
3158 dev->ib_active = true;
3163 destroy_umrc_res(dev);
3166 ib_unregister_device(&dev->ib_dev);
3169 mlx5_ib_dealloc_q_counters(dev);
3172 mlx5_ib_odp_remove_one(dev);
3175 destroy_dev_resources(&dev->devr);
3178 if (ll == IB_LINK_LAYER_ETHERNET) {
3179 mlx5_disable_roce(dev);
3180 mlx5_remove_roce_notifier(dev);
3187 ib_dealloc_device((struct ib_device *)dev);
3192 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3194 struct mlx5_ib_dev *dev = context;
3195 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3197 mlx5_ib_cleanup_congestion(dev);
3198 mlx5_remove_roce_notifier(dev);
3199 ib_unregister_device(&dev->ib_dev);
3200 mlx5_ib_dealloc_q_counters(dev);
3201 destroy_umrc_res(dev);
3202 mlx5_ib_odp_remove_one(dev);
3203 destroy_dev_resources(&dev->devr);
3204 if (ll == IB_LINK_LAYER_ETHERNET)
3205 mlx5_disable_roce(dev);
3207 ib_dealloc_device(&dev->ib_dev);
3210 static struct mlx5_interface mlx5_ib_interface = {
3212 .remove = mlx5_ib_remove,
3213 .event = mlx5_ib_event,
3214 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3217 static int __init mlx5_ib_init(void)
3221 if (deprecated_prof_sel != 2)
3222 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3224 err = mlx5_ib_odp_init();
3228 err = mlx5_register_interface(&mlx5_ib_interface);
3235 mlx5_ib_odp_cleanup();
3239 static void __exit mlx5_ib_cleanup(void)
3241 mlx5_unregister_interface(&mlx5_ib_interface);
3242 mlx5_ib_odp_cleanup();
3245 module_init_order(mlx5_ib_init, SI_ORDER_THIRD);
3246 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD);