sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <linux/module.h>
  29 #include <rdma/ib_umem.h>
  30 #include <rdma/ib_cache.h>
  31 #include <rdma/ib_user_verbs.h>
  32 #include "mlx5_ib.h"
  33
  34 /* not supported currently */
  35 static int wq_signature;
  36
  37 enum {
  38         MLX5_IB_ACK_REQ_FREQ    = 8,
  39 };
  40
  41 enum {
  42         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  43         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  44         MLX5_IB_LINK_TYPE_IB            = 0,
  45         MLX5_IB_LINK_TYPE_ETH           = 1
  46 };
  47
  48 enum {
  49         MLX5_IB_SQ_STRIDE       = 6,
  50 };
  51
  52 static const u32 mlx5_ib_opcode[] = {
  53         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  54         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  55         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  56         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  57         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  58         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  59         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  60         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  61         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  62         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  63         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  64         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  65         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  66         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  67 };
  68
  69 struct mlx5_wqe_eth_pad {
  70         u8 rsvd0[16];
  71 };
  72
  73 enum raw_qp_set_mask_map {
  74         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  75 };
  76
  77 struct mlx5_modify_raw_qp_param {
  78         u16 operation;
  79
  80         u32 set_mask; /* raw_qp_set_mask_map */
  81         u8 rq_q_ctr_id;
  82 };
  83
  84 static void get_cqs(enum ib_qp_type qp_type,
  85                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  86                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  87
  88 static int is_qp0(enum ib_qp_type qp_type)
  89 {
  90         return qp_type == IB_QPT_SMI;
  91 }
  92
  93 static int is_sqp(enum ib_qp_type qp_type)
  94 {
  95         return is_qp0(qp_type) || is_qp1(qp_type);
  96 }
  97
  98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  99 {
 100         return mlx5_buf_offset(&qp->buf, offset);
 101 }
 102
 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 104 {
 105         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 106 }
 107
 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 111 }
 112
 113 /**
 114  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 115  *
 116  * @qp: QP to copy from.
 117  * @send: copy from the send queue when non-zero, use the receive queue
 118  *        otherwise.
 119  * @wqe_index:  index to start copying from. For send work queues, the
 120  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 121  *              For receive work queue, it is the number of work queue
 122  *              element in the queue.
 123  * @buffer: destination buffer.
 124  * @length: maximum number of bytes to copy.
 125  *
 126  * Copies at least a single WQE, but may copy more data.
 127  *
 128  * Return: the number of bytes copied, or an error code.
 129  */
 130 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 131                           void *buffer, u32 length,
 132                           struct mlx5_ib_qp_base *base)
 133 {
 134         struct ib_device *ibdev = qp->ibqp.device;
 135         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 136         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 137         size_t offset;
 138         size_t wq_end;
 139         struct ib_umem *umem = base->ubuffer.umem;
 140         u32 first_copy_length;
 141         int wqe_length;
 142         int ret;
 143
 144         if (wq->wqe_cnt == 0) {
 145                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 146                             qp->ibqp.qp_type);
 147                 return -EINVAL;
 148         }
 149
 150         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 151         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 152
 153         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 154                 return -EINVAL;
 155
 156         if (offset > umem->length ||
 157             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 158                 return -EINVAL;
 159
 160         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 161         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 162         if (ret)
 163                 return ret;
 164
 165         if (send) {
 166                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 167                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 168
 169                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 170         } else {
 171                 wqe_length = 1 << wq->wqe_shift;
 172         }
 173
 174         if (wqe_length <= first_copy_length)
 175                 return first_copy_length;
 176
 177         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 178                                 wqe_length - first_copy_length);
 179         if (ret)
 180                 return ret;
 181
 182         return wqe_length;
 183 }
 184
 185 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 186 {
 187         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 188         struct ib_event event;
 189
 190         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 191                 /* This event is only valid for trans_qps */
 192                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 193         }
 194
 195         if (ibqp->event_handler) {
 196                 event.device     = ibqp->device;
 197                 event.element.qp = ibqp;
 198                 switch (type) {
 199                 case MLX5_EVENT_TYPE_PATH_MIG:
 200                         event.event = IB_EVENT_PATH_MIG;
 201                         break;
 202                 case MLX5_EVENT_TYPE_COMM_EST:
 203                         event.event = IB_EVENT_COMM_EST;
 204                         break;
 205                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 206                         event.event = IB_EVENT_SQ_DRAINED;
 207                         break;
 208                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 209                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 210                         break;
 211                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 212                         event.event = IB_EVENT_QP_FATAL;
 213                         break;
 214                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 215                         event.event = IB_EVENT_PATH_MIG_ERR;
 216                         break;
 217                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 218                         event.event = IB_EVENT_QP_REQ_ERR;
 219                         break;
 220                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 221                         event.event = IB_EVENT_QP_ACCESS_ERR;
 222                         break;
 223                 default:
 224                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 225                         return;
 226                 }
 227
 228                 ibqp->event_handler(&event, ibqp->qp_context);
 229         }
 230 }
 231
 232 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 233                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 234 {
 235         int wqe_size;
 236         int wq_size;
 237
 238         /* Sanity check RQ size before proceeding */
 239         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 240                 return -EINVAL;
 241
 242         if (!has_rq) {
 243                 qp->rq.max_gs = 0;
 244                 qp->rq.wqe_cnt = 0;
 245                 qp->rq.wqe_shift = 0;
 246                 cap->max_recv_wr = 0;
 247                 cap->max_recv_sge = 0;
 248         } else {
 249                 if (ucmd) {
 250                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 251                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 252                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 253                         qp->rq.max_post = qp->rq.wqe_cnt;
 254                 } else {
 255                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 256                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 257                         wqe_size = roundup_pow_of_two(wqe_size);
 258                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 259                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 260                         qp->rq.wqe_cnt = wq_size / wqe_size;
 261                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 262                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 263                                             wqe_size,
 264                                             MLX5_CAP_GEN(dev->mdev,
 265                                                          max_wqe_sz_rq));
 266                                 return -EINVAL;
 267                         }
 268                         qp->rq.wqe_shift = ilog2(wqe_size);
 269                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 270                         qp->rq.max_post = qp->rq.wqe_cnt;
 271                 }
 272         }
 273
 274         return 0;
 275 }
 276
 277 static int sq_overhead(struct ib_qp_init_attr *attr)
 278 {
 279         int size = 0;
 280
 281         switch (attr->qp_type) {
 282         case IB_QPT_XRC_INI:
 283                 size += sizeof(struct mlx5_wqe_xrc_seg);
 284                 /* fall through */
 285         case IB_QPT_RC:
 286                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 287                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 288                             sizeof(struct mlx5_wqe_raddr_seg),
 289                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 290                             sizeof(struct mlx5_mkey_seg));
 291                 break;
 292
 293         case IB_QPT_XRC_TGT:
 294                 return 0;
 295
 296         case IB_QPT_UC:
 297                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 298                         max(sizeof(struct mlx5_wqe_raddr_seg),
 299                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 300                             sizeof(struct mlx5_mkey_seg));
 301                 break;
 302
 303         case IB_QPT_UD:
 304                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 305                         size += sizeof(struct mlx5_wqe_eth_pad) +
 306                                 sizeof(struct mlx5_wqe_eth_seg);
 307                 /* fall through */
 308         case IB_QPT_SMI:
 309         case MLX5_IB_QPT_HW_GSI:
 310                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 311                         sizeof(struct mlx5_wqe_datagram_seg);
 312                 break;
 313
 314         case MLX5_IB_QPT_REG_UMR:
 315                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 316                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 317                         sizeof(struct mlx5_mkey_seg);
 318                 break;
 319
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         return size;
 325 }
 326
 327 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 328 {
 329         int inl_size = 0;
 330         int size;
 331
 332         size = sq_overhead(attr);
 333         if (size < 0)
 334                 return size;
 335
 336         if (attr->cap.max_inline_data) {
 337                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 338                         attr->cap.max_inline_data;
 339         }
 340
 341         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 342         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 343             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 344                         return MLX5_SIG_WQE_SIZE;
 345         else
 346                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 347 }
 348
 349 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 350                         struct mlx5_ib_qp *qp)
 351 {
 352         int wqe_size;
 353         int wq_size;
 354
 355         if (!attr->cap.max_send_wr)
 356                 return 0;
 357
 358         wqe_size = calc_send_wqe(attr);
 359         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 360         if (wqe_size < 0)
 361                 return wqe_size;
 362
 363         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 364                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 365                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 366                 return -EINVAL;
 367         }
 368
 369         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 370                               sizeof(struct mlx5_wqe_inline_seg);
 371         attr->cap.max_inline_data = qp->max_inline_data;
 372
 373         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 374                 qp->signature_en = true;
 375
 376         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 377         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 378         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 379                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 380                             qp->sq.wqe_cnt,
 381                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 382                 return -ENOMEM;
 383         }
 384         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 385         qp->sq.max_gs = attr->cap.max_send_sge;
 386         qp->sq.max_post = wq_size / wqe_size;
 387         attr->cap.max_send_wr = qp->sq.max_post;
 388
 389         return wq_size;
 390 }
 391
 392 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 393                             struct mlx5_ib_qp *qp,
 394                             struct mlx5_ib_create_qp *ucmd,
 395                             struct mlx5_ib_qp_base *base,
 396                             struct ib_qp_init_attr *attr)
 397 {
 398         int desc_sz = 1 << qp->sq.wqe_shift;
 399
 400         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 401                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 402                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 403                 return -EINVAL;
 404         }
 405
 406         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 407                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 408                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 409                 return -EINVAL;
 410         }
 411
 412         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 413
 414         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 415                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 416                              qp->sq.wqe_cnt,
 417                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 418                 return -EINVAL;
 419         }
 420
 421         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 422                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 423                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 424         } else {
 425                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 426                                          (qp->sq.wqe_cnt << 6);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int qp_has_rq(struct ib_qp_init_attr *attr)
 433 {
 434         if (attr->qp_type == IB_QPT_XRC_INI ||
 435             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 436             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 437             !attr->cap.max_recv_wr)
 438                 return 0;
 439
 440         return 1;
 441 }
 442
 443 static int first_med_uuar(void)
 444 {
 445         return 1;
 446 }
 447
 448 static int next_uuar(int n)
 449 {
 450         n++;
 451
 452         while (((n % 4) & 2))
 453                 n++;
 454
 455         return n;
 456 }
 457
 458 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 459 {
 460         int n;
 461
 462         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 463                 uuari->num_low_latency_uuars - 1;
 464
 465         return n >= 0 ? n : 0;
 466 }
 467
 468 static int max_uuari(struct mlx5_uuar_info *uuari)
 469 {
 470         return uuari->num_uars * 4;
 471 }
 472
 473 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 474 {
 475         int med;
 476         int i;
 477         int t;
 478
 479         med = num_med_uuar(uuari);
 480         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 481                 t++;
 482                 if (t == med)
 483                         return next_uuar(i);
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 490 {
 491         int i;
 492
 493         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 494                 if (!test_bit(i, uuari->bitmap)) {
 495                         set_bit(i, uuari->bitmap);
 496                         uuari->count[i]++;
 497                         return i;
 498                 }
 499         }
 500
 501         return -ENOMEM;
 502 }
 503
 504 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 505 {
 506         int minidx = first_med_uuar();
 507         int i;
 508
 509         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 510                 if (uuari->count[i] < uuari->count[minidx])
 511                         minidx = i;
 512         }
 513
 514         uuari->count[minidx]++;
 515         return minidx;
 516 }
 517
 518 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 519                       enum mlx5_ib_latency_class lat)
 520 {
 521         int uuarn = -EINVAL;
 522
 523         mutex_lock(&uuari->lock);
 524         switch (lat) {
 525         case MLX5_IB_LATENCY_CLASS_LOW:
 526                 uuarn = 0;
 527                 uuari->count[uuarn]++;
 528                 break;
 529
 530         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 531                 if (uuari->ver < 2)
 532                         uuarn = -ENOMEM;
 533                 else
 534                         uuarn = alloc_med_class_uuar(uuari);
 535                 break;
 536
 537         case MLX5_IB_LATENCY_CLASS_HIGH:
 538                 if (uuari->ver < 2)
 539                         uuarn = -ENOMEM;
 540                 else
 541                         uuarn = alloc_high_class_uuar(uuari);
 542                 break;
 543
 544         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 545                 uuarn = 2;
 546                 break;
 547         }
 548         mutex_unlock(&uuari->lock);
 549
 550         return uuarn;
 551 }
 552
 553 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 554 {
 555         clear_bit(uuarn, uuari->bitmap);
 556         --uuari->count[uuarn];
 557 }
 558
 559 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 560 {
 561         clear_bit(uuarn, uuari->bitmap);
 562         --uuari->count[uuarn];
 563 }
 564
 565 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 566 {
 567         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 568         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 569
 570         mutex_lock(&uuari->lock);
 571         if (uuarn == 0) {
 572                 --uuari->count[uuarn];
 573                 goto out;
 574         }
 575
 576         if (uuarn < high_uuar) {
 577                 free_med_class_uuar(uuari, uuarn);
 578                 goto out;
 579         }
 580
 581         free_high_class_uuar(uuari, uuarn);
 582
 583 out:
 584         mutex_unlock(&uuari->lock);
 585 }
 586
 587 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 588 {
 589         switch (state) {
 590         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 591         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 592         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 593         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 594         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 595         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 596         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 597         default:                return -1;
 598         }
 599 }
 600
 601 static int to_mlx5_st(enum ib_qp_type type)
 602 {
 603         switch (type) {
 604         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 605         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 606         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 607         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 608         case IB_QPT_XRC_INI:
 609         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 610         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 611         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 612         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 613         case IB_QPT_RAW_PACKET:
 614         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 615         case IB_QPT_MAX:
 616         default:                return -EINVAL;
 617         }
 618 }
 619
 620 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 621                              struct mlx5_ib_cq *recv_cq);
 622 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 623                                struct mlx5_ib_cq *recv_cq);
 624
 625 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 626 {
 627         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 628 }
 629
 630 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 631                             struct ib_pd *pd,
 632                             unsigned long addr, size_t size,
 633                             struct ib_umem **umem,
 634                             int *npages, int *page_shift, int *ncont,
 635                             u32 *offset)
 636 {
 637         int err;
 638
 639         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 640         if (IS_ERR(*umem)) {
 641                 mlx5_ib_dbg(dev, "umem_get failed\n");
 642                 return PTR_ERR(*umem);
 643         }
 644
 645         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 646
 647         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 648         if (err) {
 649                 mlx5_ib_warn(dev, "bad offset\n");
 650                 goto err_umem;
 651         }
 652
 653         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 654                     addr, size, *npages, *page_shift, *ncont, *offset);
 655
 656         return 0;
 657
 658 err_umem:
 659         ib_umem_release(*umem);
 660         *umem = NULL;
 661
 662         return err;
 663 }
 664
 665 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 666 {
 667         struct mlx5_ib_ucontext *context;
 668
 669         context = to_mucontext(pd->uobject->context);
 670         mlx5_ib_db_unmap_user(context, &rwq->db);
 671         if (rwq->umem)
 672                 ib_umem_release(rwq->umem);
 673 }
 674
 675 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 676                           struct mlx5_ib_rwq *rwq,
 677                           struct mlx5_ib_create_wq *ucmd)
 678 {
 679         struct mlx5_ib_ucontext *context;
 680         int page_shift = 0;
 681         int npages;
 682         u32 offset = 0;
 683         int ncont = 0;
 684         int err;
 685
 686         if (!ucmd->buf_addr)
 687                 return -EINVAL;
 688
 689         context = to_mucontext(pd->uobject->context);
 690         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 691                                rwq->buf_size, 0, 0);
 692         if (IS_ERR(rwq->umem)) {
 693                 mlx5_ib_dbg(dev, "umem_get failed\n");
 694                 err = PTR_ERR(rwq->umem);
 695                 return err;
 696         }
 697
 698         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 699                            &ncont, NULL);
 700         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 701                                      &rwq->rq_page_offset);
 702         if (err) {
 703                 mlx5_ib_warn(dev, "bad offset\n");
 704                 goto err_umem;
 705         }
 706
 707         rwq->rq_num_pas = ncont;
 708         rwq->page_shift = page_shift;
 709         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 710         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 711
 712         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 713                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 714                     npages, page_shift, ncont, offset);
 715
 716         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 717         if (err) {
 718                 mlx5_ib_dbg(dev, "map failed\n");
 719                 goto err_umem;
 720         }
 721
 722         rwq->create_type = MLX5_WQ_USER;
 723         return 0;
 724
 725 err_umem:
 726         ib_umem_release(rwq->umem);
 727         return err;
 728 }
 729
 730 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 731                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 732                           struct ib_qp_init_attr *attr,
 733                           u32 **in,
 734                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 735                           struct mlx5_ib_qp_base *base)
 736 {
 737         struct mlx5_ib_ucontext *context;
 738         struct mlx5_ib_create_qp ucmd;
 739         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 740         int page_shift = 0;
 741         int uar_index;
 742         int npages;
 743         u32 offset = 0;
 744         int uuarn;
 745         int ncont = 0;
 746         __be64 *pas;
 747         void *qpc;
 748         int err;
 749
 750         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 751         if (err) {
 752                 mlx5_ib_dbg(dev, "copy failed\n");
 753                 return err;
 754         }
 755
 756         context = to_mucontext(pd->uobject->context);
 757         /*
 758          * TBD: should come from the verbs when we have the API
 759          */
 760         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 761                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 762                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 763         else {
 764                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 765                 if (uuarn < 0) {
 766                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 767                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 768                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 769                         if (uuarn < 0) {
 770                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 771                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 772                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 773                                 if (uuarn < 0) {
 774                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 775                                         return uuarn;
 776                                 }
 777                         }
 778                 }
 779         }
 780
 781         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 782         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 783
 784         qp->rq.offset = 0;
 785         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 786         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 787
 788         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 789         if (err)
 790                 goto err_uuar;
 791
 792         if (ucmd.buf_addr && ubuffer->buf_size) {
 793                 ubuffer->buf_addr = ucmd.buf_addr;
 794                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 795                                        ubuffer->buf_size,
 796                                        &ubuffer->umem, &npages, &page_shift,
 797                                        &ncont, &offset);
 798                 if (err)
 799                         goto err_uuar;
 800         } else {
 801                 ubuffer->umem = NULL;
 802         }
 803
 804         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 805                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 806         *in = mlx5_vzalloc(*inlen);
 807         if (!*in) {
 808                 err = -ENOMEM;
 809                 goto err_umem;
 810         }
 811
 812         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 813         if (ubuffer->umem)
 814                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 815
 816         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 817
 818         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 819         MLX5_SET(qpc, qpc, page_offset, offset);
 820
 821         MLX5_SET(qpc, qpc, uar_page, uar_index);
 822         resp->uuar_index = uuarn;
 823         qp->uuarn = uuarn;
 824
 825         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 826         if (err) {
 827                 mlx5_ib_dbg(dev, "map failed\n");
 828                 goto err_free;
 829         }
 830
 831         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 832         if (err) {
 833                 mlx5_ib_dbg(dev, "copy failed\n");
 834                 goto err_unmap;
 835         }
 836         qp->create_type = MLX5_QP_USER;
 837
 838         return 0;
 839
 840 err_unmap:
 841         mlx5_ib_db_unmap_user(context, &qp->db);
 842
 843 err_free:
 844         kvfree(*in);
 845
 846 err_umem:
 847         if (ubuffer->umem)
 848                 ib_umem_release(ubuffer->umem);
 849
 850 err_uuar:
 851         free_uuar(&context->uuari, uuarn);
 852         return err;
 853 }
 854
 855 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 856                             struct mlx5_ib_qp_base *base)
 857 {
 858         struct mlx5_ib_ucontext *context;
 859
 860         context = to_mucontext(pd->uobject->context);
 861         mlx5_ib_db_unmap_user(context, &qp->db);
 862         if (base->ubuffer.umem)
 863                 ib_umem_release(base->ubuffer.umem);
 864         free_uuar(&context->uuari, qp->uuarn);
 865 }
 866
 867 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 868                             struct ib_qp_init_attr *init_attr,
 869                             struct mlx5_ib_qp *qp,
 870                             u32 **in, int *inlen,
 871                             struct mlx5_ib_qp_base *base)
 872 {
 873         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 874         struct mlx5_uuar_info *uuari;
 875         int uar_index;
 876         void *qpc;
 877         int uuarn;
 878         int err;
 879
 880         uuari = &dev->mdev->priv.uuari;
 881         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 882                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 883                                         IB_QP_CREATE_IPOIB_UD_LSO |
 884                                         mlx5_ib_create_qp_sqpn_qp1()))
 885                 return -EINVAL;
 886
 887         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 888                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 889
 890         uuarn = alloc_uuar(uuari, lc);
 891         if (uuarn < 0) {
 892                 mlx5_ib_dbg(dev, "\n");
 893                 return -ENOMEM;
 894         }
 895
 896         qp->bf = &uuari->bfs[uuarn];
 897         uar_index = qp->bf->uar->index;
 898
 899         err = calc_sq_size(dev, init_attr, qp);
 900         if (err < 0) {
 901                 mlx5_ib_dbg(dev, "err %d\n", err);
 902                 goto err_uuar;
 903         }
 904
 905         qp->rq.offset = 0;
 906         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 907         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 908
 909         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size,
 910             2 * PAGE_SIZE, &qp->buf);
 911         if (err) {
 912                 mlx5_ib_dbg(dev, "err %d\n", err);
 913                 goto err_uuar;
 914         }
 915
 916         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 917         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 918                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 919         *in = mlx5_vzalloc(*inlen);
 920         if (!*in) {
 921                 err = -ENOMEM;
 922                 goto err_buf;
 923         }
 924
 925         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 926         MLX5_SET(qpc, qpc, uar_page, uar_index);
 927         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 928
 929         /* Set "fast registration enabled" for all kernel QPs */
 930         MLX5_SET(qpc, qpc, fre, 1);
 931         MLX5_SET(qpc, qpc, rlky, 1);
 932
 933         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 934                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 935                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 936         }
 937
 938         mlx5_fill_page_array(&qp->buf,
 939                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 940
 941         err = mlx5_db_alloc(dev->mdev, &qp->db);
 942         if (err) {
 943                 mlx5_ib_dbg(dev, "err %d\n", err);
 944                 goto err_free;
 945         }
 946
 947         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 948         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 949         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 950         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 951         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 952
 953         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 954             !qp->sq.w_list || !qp->sq.wqe_head) {
 955                 err = -ENOMEM;
 956                 goto err_wrid;
 957         }
 958         qp->create_type = MLX5_QP_KERNEL;
 959
 960         return 0;
 961
 962 err_wrid:
 963         mlx5_db_free(dev->mdev, &qp->db);
 964         kfree(qp->sq.wqe_head);
 965         kfree(qp->sq.w_list);
 966         kfree(qp->sq.wrid);
 967         kfree(qp->sq.wr_data);
 968         kfree(qp->rq.wrid);
 969
 970 err_free:
 971         kvfree(*in);
 972
 973 err_buf:
 974         mlx5_buf_free(dev->mdev, &qp->buf);
 975
 976 err_uuar:
 977         free_uuar(&dev->mdev->priv.uuari, uuarn);
 978         return err;
 979 }
 980
 981 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 982 {
 983         mlx5_db_free(dev->mdev, &qp->db);
 984         kfree(qp->sq.wqe_head);
 985         kfree(qp->sq.w_list);
 986         kfree(qp->sq.wrid);
 987         kfree(qp->sq.wr_data);
 988         kfree(qp->rq.wrid);
 989         mlx5_buf_free(dev->mdev, &qp->buf);
 990         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 991 }
 992
 993 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 994 {
 995         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 996             (attr->qp_type == IB_QPT_XRC_INI))
 997                 return MLX5_SRQ_RQ;
 998         else if (!qp->has_rq)
 999                 return MLX5_ZERO_LEN_RQ;
1000         else
1001                 return MLX5_NON_ZERO_RQ;
1002 }
1003
1004 static int is_connected(enum ib_qp_type qp_type)
1005 {
1006         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1007                 return 1;
1008
1009         return 0;
1010 }
1011
1012 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1013                                     struct mlx5_ib_sq *sq, u32 tdn)
1014 {
1015         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1016         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1017
1018         MLX5_SET(tisc, tisc, transport_domain, tdn);
1019         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1020 }
1021
1022 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1023                                       struct mlx5_ib_sq *sq)
1024 {
1025         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1026 }
1027
1028 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1029                                    struct mlx5_ib_sq *sq, void *qpin,
1030                                    struct ib_pd *pd)
1031 {
1032         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1033         __be64 *pas;
1034         void *in;
1035         void *sqc;
1036         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1037         void *wq;
1038         int inlen;
1039         int err;
1040         int page_shift = 0;
1041         int npages;
1042         int ncont = 0;
1043         u32 offset = 0;
1044
1045         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1046                                &sq->ubuffer.umem, &npages, &page_shift,
1047                                &ncont, &offset);
1048         if (err)
1049                 return err;
1050
1051         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1052         in = mlx5_vzalloc(inlen);
1053         if (!in) {
1054                 err = -ENOMEM;
1055                 goto err_umem;
1056         }
1057
1058         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1059         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1060         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1061         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1062         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1063         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1064         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1065
1066         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1067         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1068         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1069         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1070         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1071         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1072         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1073         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1074         MLX5_SET(wq, wq, page_offset, offset);
1075
1076         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1077         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1078
1079         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1080
1081         kvfree(in);
1082
1083         if (err)
1084                 goto err_umem;
1085
1086         return 0;
1087
1088 err_umem:
1089         ib_umem_release(sq->ubuffer.umem);
1090         sq->ubuffer.umem = NULL;
1091
1092         return err;
1093 }
1094
1095 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1096                                      struct mlx5_ib_sq *sq)
1097 {
1098         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1099         ib_umem_release(sq->ubuffer.umem);
1100 }
1101
1102 static int get_rq_pas_size(void *qpc)
1103 {
1104         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1105         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1106         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1107         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1108         u32 po_quanta     = 1 << (log_page_size - 6);
1109         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1110         u32 page_size     = 1 << log_page_size;
1111         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1112         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1113
1114         return rq_num_pas * sizeof(u64);
1115 }
1116
1117 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1118                                    struct mlx5_ib_rq *rq, void *qpin)
1119 {
1120         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1121         __be64 *pas;
1122         __be64 *qp_pas;
1123         void *in;
1124         void *rqc;
1125         void *wq;
1126         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1127         int inlen;
1128         int err;
1129         u32 rq_pas_size = get_rq_pas_size(qpc);
1130
1131         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1132         in = mlx5_vzalloc(inlen);
1133         if (!in)
1134                 return -ENOMEM;
1135
1136         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1137         MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
1138         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
1139         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1140         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1141         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1142         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1143
1144         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1145                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1146
1147         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1148         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1149         MLX5_SET(wq, wq, end_padding_mode,
1150                  MLX5_GET(qpc, qpc, end_padding_mode));
1151         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1152         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1153         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1154         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1155         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1156         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1157
1158         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1159         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1160         memcpy(pas, qp_pas, rq_pas_size);
1161
1162         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1163
1164         kvfree(in);
1165
1166         return err;
1167 }
1168
1169 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1170                                      struct mlx5_ib_rq *rq)
1171 {
1172         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1173 }
1174
1175 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1176                                     struct mlx5_ib_rq *rq, u32 tdn)
1177 {
1178         u32 *in;
1179         void *tirc;
1180         int inlen;
1181         int err;
1182
1183         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1184         in = mlx5_vzalloc(inlen);
1185         if (!in)
1186                 return -ENOMEM;
1187
1188         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1189         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1190         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1191         MLX5_SET(tirc, tirc, transport_domain, tdn);
1192
1193         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1194
1195         kvfree(in);
1196
1197         return err;
1198 }
1199
1200 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1201                                       struct mlx5_ib_rq *rq)
1202 {
1203         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1204 }
1205
1206 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1207                                 u32 *in,
1208                                 struct ib_pd *pd)
1209 {
1210         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1211         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1212         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1213         struct ib_uobject *uobj = pd->uobject;
1214         struct ib_ucontext *ucontext = uobj->context;
1215         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1216         int err;
1217         u32 tdn = mucontext->tdn;
1218
1219         if (qp->sq.wqe_cnt) {
1220                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1221                 if (err)
1222                         return err;
1223
1224                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1225                 if (err)
1226                         goto err_destroy_tis;
1227
1228                 sq->base.container_mibqp = qp;
1229         }
1230
1231         if (qp->rq.wqe_cnt) {
1232                 rq->base.container_mibqp = qp;
1233
1234                 err = create_raw_packet_qp_rq(dev, rq, in);
1235                 if (err)
1236                         goto err_destroy_sq;
1237
1238
1239                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1240                 if (err)
1241                         goto err_destroy_rq;
1242         }
1243
1244         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1245                                                      rq->base.mqp.qpn;
1246
1247         return 0;
1248
1249 err_destroy_rq:
1250         destroy_raw_packet_qp_rq(dev, rq);
1251 err_destroy_sq:
1252         if (!qp->sq.wqe_cnt)
1253                 return err;
1254         destroy_raw_packet_qp_sq(dev, sq);
1255 err_destroy_tis:
1256         destroy_raw_packet_qp_tis(dev, sq);
1257
1258         return err;
1259 }
1260
1261 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1262                                   struct mlx5_ib_qp *qp)
1263 {
1264         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1265         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1266         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1267
1268         if (qp->rq.wqe_cnt) {
1269                 destroy_raw_packet_qp_tir(dev, rq);
1270                 destroy_raw_packet_qp_rq(dev, rq);
1271         }
1272
1273         if (qp->sq.wqe_cnt) {
1274                 destroy_raw_packet_qp_sq(dev, sq);
1275                 destroy_raw_packet_qp_tis(dev, sq);
1276         }
1277 }
1278
1279 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1280                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1281 {
1282         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1283         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1284
1285         sq->sq = &qp->sq;
1286         rq->rq = &qp->rq;
1287         sq->doorbell = &qp->db;
1288         rq->doorbell = &qp->db;
1289 }
1290
1291 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1292 {
1293         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1294 }
1295
1296 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1297                                  struct ib_pd *pd,
1298                                  struct ib_qp_init_attr *init_attr,
1299                                  struct ib_udata *udata)
1300 {
1301         struct ib_uobject *uobj = pd->uobject;
1302         struct ib_ucontext *ucontext = uobj->context;
1303         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1304         struct mlx5_ib_create_qp_resp resp = {};
1305         int inlen;
1306         int err;
1307         u32 *in;
1308         void *tirc;
1309         void *hfso;
1310         u32 selected_fields = 0;
1311         size_t min_resp_len;
1312         u32 tdn = mucontext->tdn;
1313         struct mlx5_ib_create_qp_rss ucmd = {};
1314         size_t required_cmd_sz;
1315
1316         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1317                 return -EOPNOTSUPP;
1318
1319         if (init_attr->create_flags || init_attr->send_cq)
1320                 return -EINVAL;
1321
1322         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1323         if (udata->outlen < min_resp_len)
1324                 return -EINVAL;
1325
1326         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1327         if (udata->inlen < required_cmd_sz) {
1328                 mlx5_ib_dbg(dev, "invalid inlen\n");
1329                 return -EINVAL;
1330         }
1331
1332         if (udata->inlen > sizeof(ucmd) &&
1333             !ib_is_udata_cleared(udata, sizeof(ucmd),
1334                                  udata->inlen - sizeof(ucmd))) {
1335                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1336                 return -EOPNOTSUPP;
1337         }
1338
1339         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1340                 mlx5_ib_dbg(dev, "copy failed\n");
1341                 return -EFAULT;
1342         }
1343
1344         if (ucmd.comp_mask) {
1345                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1346                 return -EOPNOTSUPP;
1347         }
1348
1349         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1350                 mlx5_ib_dbg(dev, "invalid reserved\n");
1351                 return -EOPNOTSUPP;
1352         }
1353
1354         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1355         if (err) {
1356                 mlx5_ib_dbg(dev, "copy failed\n");
1357                 return -EINVAL;
1358         }
1359
1360         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1361         in = mlx5_vzalloc(inlen);
1362         if (!in)
1363                 return -ENOMEM;
1364
1365         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1366         MLX5_SET(tirc, tirc, disp_type,
1367                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1368         MLX5_SET(tirc, tirc, indirect_table,
1369                  init_attr->rwq_ind_tbl->ind_tbl_num);
1370         MLX5_SET(tirc, tirc, transport_domain, tdn);
1371
1372         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1373         switch (ucmd.rx_hash_function) {
1374         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1375         {
1376                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1377                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1378
1379                 if (len != ucmd.rx_key_len) {
1380                         err = -EINVAL;
1381                         goto err;
1382                 }
1383
1384                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ);
1385                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1386                 memcpy(rss_key, ucmd.rx_hash_key, len);
1387                 break;
1388         }
1389         default:
1390                 err = -EOPNOTSUPP;
1391                 goto err;
1392         }
1393
1394         if (!ucmd.rx_hash_fields_mask) {
1395                 /* special case when this TIR serves as steering entry without hashing */
1396                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1397                         goto create_tir;
1398                 err = -EINVAL;
1399                 goto err;
1400         }
1401
1402         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1403              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1404              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1405              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1406                 err = -EINVAL;
1407                 goto err;
1408         }
1409
1410         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1411         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1412             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1413                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1414                          MLX5_L3_PROT_TYPE_IPV4);
1415         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1416                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1417                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1418                          MLX5_L3_PROT_TYPE_IPV6);
1419
1420         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1421              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1422              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1423              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1424                 err = -EINVAL;
1425                 goto err;
1426         }
1427
1428         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1429         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1430             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1431                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1432                          MLX5_L4_PROT_TYPE_TCP);
1433         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1434                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1435                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1436                          MLX5_L4_PROT_TYPE_UDP);
1437
1438         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1439             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1440                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1441
1442         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1443             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1444                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1445
1446         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1447             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1448                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1449
1450         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1451             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1452                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1453
1454         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1455
1456 create_tir:
1457         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1458
1459         if (err)
1460                 goto err;
1461
1462         kvfree(in);
1463         /* qpn is reserved for that QP */
1464         qp->trans_qp.base.mqp.qpn = 0;
1465         qp->flags |= MLX5_IB_QP_RSS;
1466         return 0;
1467
1468 err:
1469         kvfree(in);
1470         return err;
1471 }
1472
1473 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1474                             struct ib_qp_init_attr *init_attr,
1475                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1476 {
1477         struct mlx5_ib_resources *devr = &dev->devr;
1478         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1479         struct mlx5_core_dev *mdev = dev->mdev;
1480         struct mlx5_ib_create_qp_resp resp;
1481         struct mlx5_ib_cq *send_cq;
1482         struct mlx5_ib_cq *recv_cq;
1483         unsigned long flags;
1484         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1485         struct mlx5_ib_create_qp ucmd;
1486         struct mlx5_ib_qp_base *base;
1487         void *qpc;
1488         u32 *in;
1489         int err;
1490
1491         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1492                &qp->raw_packet_qp.rq.base :
1493                &qp->trans_qp.base;
1494
1495         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1496                 mlx5_ib_odp_create_qp(qp);
1497
1498         mutex_init(&qp->mutex);
1499         spin_lock_init(&qp->sq.lock);
1500         spin_lock_init(&qp->rq.lock);
1501
1502         if (init_attr->rwq_ind_tbl) {
1503                 if (!udata)
1504                         return -ENOSYS;
1505
1506                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1507                 return err;
1508         }
1509
1510         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1511                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1512                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1513                         return -EINVAL;
1514                 } else {
1515                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1516                 }
1517         }
1518
1519         if (init_attr->create_flags &
1520                         (IB_QP_CREATE_CROSS_CHANNEL |
1521                          IB_QP_CREATE_MANAGED_SEND |
1522                          IB_QP_CREATE_MANAGED_RECV)) {
1523                 if (!MLX5_CAP_GEN(mdev, cd)) {
1524                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1525                         return -EINVAL;
1526                 }
1527                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1528                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1529                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1530                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1531                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1532                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1533         }
1534
1535         if (init_attr->qp_type == IB_QPT_UD &&
1536             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1537                 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
1538                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1539                         return -EOPNOTSUPP;
1540                 }
1541
1542         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1543                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1544                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1545                         return -EOPNOTSUPP;
1546                 }
1547                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1548                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1549                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1550                         return -EOPNOTSUPP;
1551                 }
1552                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1553         }
1554
1555         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1556                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1557
1558         if (pd && pd->uobject) {
1559                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1560                         mlx5_ib_dbg(dev, "copy failed\n");
1561                         return -EFAULT;
1562                 }
1563
1564                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1565                                         &ucmd, udata->inlen, &uidx);
1566                 if (err)
1567                         return err;
1568
1569                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1570                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1571         } else {
1572                 qp->wq_sig = !!wq_signature;
1573         }
1574
1575         qp->has_rq = qp_has_rq(init_attr);
1576         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1577                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1578         if (err) {
1579                 mlx5_ib_dbg(dev, "err %d\n", err);
1580                 return err;
1581         }
1582
1583         if (pd) {
1584                 if (pd->uobject) {
1585                         __u32 max_wqes =
1586                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1587                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1588                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1589                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1590                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1591                                 return -EINVAL;
1592                         }
1593                         if (ucmd.sq_wqe_count > max_wqes) {
1594                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1595                                             ucmd.sq_wqe_count, max_wqes);
1596                                 return -EINVAL;
1597                         }
1598                         if (init_attr->create_flags &
1599                             mlx5_ib_create_qp_sqpn_qp1()) {
1600                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1601                                 return -EINVAL;
1602                         }
1603                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1604                                              &resp, &inlen, base);
1605                         if (err)
1606                                 mlx5_ib_dbg(dev, "err %d\n", err);
1607                 } else {
1608                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1609                                                base);
1610                         if (err)
1611                                 mlx5_ib_dbg(dev, "err %d\n", err);
1612                 }
1613
1614                 if (err)
1615                         return err;
1616         } else {
1617                 in = mlx5_vzalloc(inlen);
1618                 if (!in)
1619                         return -ENOMEM;
1620
1621                 qp->create_type = MLX5_QP_EMPTY;
1622         }
1623
1624         if (is_sqp(init_attr->qp_type))
1625                 qp->port = init_attr->port_num;
1626
1627         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1628
1629         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1630         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1631
1632         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1633                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1634         else
1635                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1636
1637
1638         if (qp->wq_sig)
1639                 MLX5_SET(qpc, qpc, wq_signature, 1);
1640
1641         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1642                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1643
1644         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1645                 MLX5_SET(qpc, qpc, cd_master, 1);
1646         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1647                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1648         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1649                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1650
1651         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1652                 int rcqe_sz;
1653                 int scqe_sz;
1654
1655                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1656                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1657
1658                 if (rcqe_sz == 128)
1659                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1660                 else
1661                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1662
1663                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1664                         if (scqe_sz == 128)
1665                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1666                         else
1667                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1668                 }
1669         }
1670
1671         if (qp->rq.wqe_cnt) {
1672                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1673                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1674         }
1675
1676         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1677
1678         if (qp->sq.wqe_cnt)
1679                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1680         else
1681                 MLX5_SET(qpc, qpc, no_sq, 1);
1682
1683         /* Set default resources */
1684         switch (init_attr->qp_type) {
1685         case IB_QPT_XRC_TGT:
1686                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1687                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1688                 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1689                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1690                 break;
1691         case IB_QPT_XRC_INI:
1692                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1693                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1694                 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1695                 break;
1696         default:
1697                 if (init_attr->srq) {
1698                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1699                         MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn);
1700                 } else {
1701                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1702                         MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn);
1703                 }
1704         }
1705
1706         if (init_attr->send_cq)
1707                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1708
1709         if (init_attr->recv_cq)
1710                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1711
1712         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1713
1714         /* 0xffffff means we ask to work with cqe version 0 */
1715         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1716                 MLX5_SET(qpc, qpc, user_index, uidx);
1717
1718         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1719         if (init_attr->qp_type == IB_QPT_UD &&
1720             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1721                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1722                 qp->flags |= MLX5_IB_QP_LSO;
1723         }
1724
1725         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1726                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1727                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1728                 err = create_raw_packet_qp(dev, qp, in, pd);
1729         } else {
1730                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, (struct mlx5_create_qp_mbox_in *)in, inlen);
1731         }
1732
1733         if (err) {
1734                 mlx5_ib_dbg(dev, "create qp failed\n");
1735                 goto err_create;
1736         }
1737
1738         kvfree(in);
1739
1740         base->container_mibqp = qp;
1741         base->mqp.event = mlx5_ib_qp_event;
1742
1743         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1744                 &send_cq, &recv_cq);
1745         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1746         mlx5_ib_lock_cqs(send_cq, recv_cq);
1747         /* Maintain device to QPs access, needed for further handling via reset
1748          * flow
1749          */
1750         list_add_tail(&qp->qps_list, &dev->qp_list);
1751         /* Maintain CQ to QPs access, needed for further handling via reset flow
1752          */
1753         if (send_cq)
1754                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1755         if (recv_cq)
1756                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1757         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1758         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1759
1760         return 0;
1761
1762 err_create:
1763         if (qp->create_type == MLX5_QP_USER)
1764                 destroy_qp_user(pd, qp, base);
1765         else if (qp->create_type == MLX5_QP_KERNEL)
1766                 destroy_qp_kernel(dev, qp);
1767
1768         kvfree(in);
1769         return err;
1770 }
1771
1772 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1773         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1774 {
1775         if (send_cq) {
1776                 if (recv_cq) {
1777                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1778                                 spin_lock(&send_cq->lock);
1779                                 spin_lock_nested(&recv_cq->lock,
1780                                                  SINGLE_DEPTH_NESTING);
1781                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1782                                 spin_lock(&send_cq->lock);
1783                                 __acquire(&recv_cq->lock);
1784                         } else {
1785                                 spin_lock(&recv_cq->lock);
1786                                 spin_lock_nested(&send_cq->lock,
1787                                                  SINGLE_DEPTH_NESTING);
1788                         }
1789                 } else {
1790                         spin_lock(&send_cq->lock);
1791                         __acquire(&recv_cq->lock);
1792                 }
1793         } else if (recv_cq) {
1794                 spin_lock(&recv_cq->lock);
1795                 __acquire(&send_cq->lock);
1796         } else {
1797                 __acquire(&send_cq->lock);
1798                 __acquire(&recv_cq->lock);
1799         }
1800 }
1801
1802 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1803         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1804 {
1805         if (send_cq) {
1806                 if (recv_cq) {
1807                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1808                                 spin_unlock(&recv_cq->lock);
1809                                 spin_unlock(&send_cq->lock);
1810                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1811                                 __release(&recv_cq->lock);
1812                                 spin_unlock(&send_cq->lock);
1813                         } else {
1814                                 spin_unlock(&send_cq->lock);
1815                                 spin_unlock(&recv_cq->lock);
1816                         }
1817                 } else {
1818                         __release(&recv_cq->lock);
1819                         spin_unlock(&send_cq->lock);
1820                 }
1821         } else if (recv_cq) {
1822                 __release(&send_cq->lock);
1823                 spin_unlock(&recv_cq->lock);
1824         } else {
1825                 __release(&recv_cq->lock);
1826                 __release(&send_cq->lock);
1827         }
1828 }
1829
1830 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1831 {
1832         return to_mpd(qp->ibqp.pd);
1833 }
1834
1835 static void get_cqs(enum ib_qp_type qp_type,
1836                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1837                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1838 {
1839         switch (qp_type) {
1840         case IB_QPT_XRC_TGT:
1841                 *send_cq = NULL;
1842                 *recv_cq = NULL;
1843                 break;
1844         case MLX5_IB_QPT_REG_UMR:
1845         case IB_QPT_XRC_INI:
1846                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1847                 *recv_cq = NULL;
1848                 break;
1849
1850         case IB_QPT_SMI:
1851         case MLX5_IB_QPT_HW_GSI:
1852         case IB_QPT_RC:
1853         case IB_QPT_UC:
1854         case IB_QPT_UD:
1855         case IB_QPT_RAW_IPV6:
1856         case IB_QPT_RAW_ETHERTYPE:
1857         case IB_QPT_RAW_PACKET:
1858                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1859                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1860                 break;
1861
1862         case IB_QPT_MAX:
1863         default:
1864                 *send_cq = NULL;
1865                 *recv_cq = NULL;
1866                 break;
1867         }
1868 }
1869
1870 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1871                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1872                                 u8 lag_tx_affinity);
1873
1874 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1875 {
1876         struct mlx5_ib_cq *send_cq, *recv_cq;
1877         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1878         unsigned long flags;
1879         int err;
1880
1881         if (qp->ibqp.rwq_ind_tbl) {
1882                 destroy_rss_raw_qp_tir(dev, qp);
1883                 return;
1884         }
1885
1886         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1887                &qp->raw_packet_qp.rq.base :
1888                &qp->trans_qp.base;
1889
1890         if (qp->state != IB_QPS_RESET) {
1891                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1892                         struct mlx5_modify_qp_mbox_in *in;
1893
1894                         mlx5_ib_qp_disable_pagefaults(qp);
1895
1896                         in = kzalloc(sizeof(*in), GFP_KERNEL);
1897                         if (in != NULL) {
1898                                 err = mlx5_core_qp_modify(dev->mdev,
1899                                                           MLX5_CMD_OP_2RST_QP,
1900                                                           in, 0, &base->mqp);
1901                                 kfree(in);
1902                         } else {
1903                                 err = -ENOMEM;
1904                         }
1905                 } else {
1906                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1907                                 .operation = MLX5_CMD_OP_2RST_QP
1908                         };
1909
1910                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1911                 }
1912                 if (err)
1913                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1914                                      base->mqp.qpn);
1915         }
1916
1917         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1918                 &send_cq, &recv_cq);
1919
1920         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1921         mlx5_ib_lock_cqs(send_cq, recv_cq);
1922         /* del from lists under both locks above to protect reset flow paths */
1923         list_del(&qp->qps_list);
1924         if (send_cq)
1925                 list_del(&qp->cq_send_list);
1926
1927         if (recv_cq)
1928                 list_del(&qp->cq_recv_list);
1929
1930         if (qp->create_type == MLX5_QP_KERNEL) {
1931                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1932                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1933                 if (send_cq != recv_cq)
1934                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1935                                            NULL);
1936         }
1937         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1938         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1939
1940         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1941                 destroy_raw_packet_qp(dev, qp);
1942         } else {
1943                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1944                 if (err)
1945                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1946                                      base->mqp.qpn);
1947         }
1948
1949         if (qp->create_type == MLX5_QP_KERNEL)
1950                 destroy_qp_kernel(dev, qp);
1951         else if (qp->create_type == MLX5_QP_USER)
1952                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1953 }
1954
1955 static const char *ib_qp_type_str(enum ib_qp_type type)
1956 {
1957         switch (type) {
1958         case IB_QPT_SMI:
1959                 return "IB_QPT_SMI";
1960         case IB_QPT_GSI:
1961                 return "IB_QPT_GSI";
1962         case IB_QPT_RC:
1963                 return "IB_QPT_RC";
1964         case IB_QPT_UC:
1965                 return "IB_QPT_UC";
1966         case IB_QPT_UD:
1967                 return "IB_QPT_UD";
1968         case IB_QPT_RAW_IPV6:
1969                 return "IB_QPT_RAW_IPV6";
1970         case IB_QPT_RAW_ETHERTYPE:
1971                 return "IB_QPT_RAW_ETHERTYPE";
1972         case IB_QPT_XRC_INI:
1973                 return "IB_QPT_XRC_INI";
1974         case IB_QPT_XRC_TGT:
1975                 return "IB_QPT_XRC_TGT";
1976         case IB_QPT_RAW_PACKET:
1977                 return "IB_QPT_RAW_PACKET";
1978         case MLX5_IB_QPT_REG_UMR:
1979                 return "MLX5_IB_QPT_REG_UMR";
1980         case IB_QPT_MAX:
1981         default:
1982                 return "Invalid QP type";
1983         }
1984 }
1985
1986 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1987                                 struct ib_qp_init_attr *init_attr,
1988                                 struct ib_udata *udata)
1989 {
1990         struct mlx5_ib_dev *dev;
1991         struct mlx5_ib_qp *qp;
1992         u16 xrcdn = 0;
1993         int err;
1994
1995         if (pd) {
1996                 dev = to_mdev(pd->device);
1997
1998                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1999                         if (!pd->uobject) {
2000                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2001                                 return ERR_PTR(-EINVAL);
2002                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2003                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2004                                 return ERR_PTR(-EINVAL);
2005                         }
2006                 }
2007         } else {
2008                 /* being cautious here */
2009                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2010                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2011                         pr_warn("%s: no PD for transport %s\n", __func__,
2012                                 ib_qp_type_str(init_attr->qp_type));
2013                         return ERR_PTR(-EINVAL);
2014                 }
2015                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2016         }
2017
2018         switch (init_attr->qp_type) {
2019         case IB_QPT_XRC_TGT:
2020         case IB_QPT_XRC_INI:
2021                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2022                         mlx5_ib_dbg(dev, "XRC not supported\n");
2023                         return ERR_PTR(-ENOSYS);
2024                 }
2025                 init_attr->recv_cq = NULL;
2026                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2027                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2028                         init_attr->send_cq = NULL;
2029                 }
2030
2031                 /* fall through */
2032         case IB_QPT_RAW_PACKET:
2033         case IB_QPT_RC:
2034         case IB_QPT_UC:
2035         case IB_QPT_UD:
2036         case IB_QPT_SMI:
2037         case MLX5_IB_QPT_HW_GSI:
2038         case MLX5_IB_QPT_REG_UMR:
2039                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2040                 if (!qp)
2041                         return ERR_PTR(-ENOMEM);
2042
2043                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2044                 if (err) {
2045                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2046                         kfree(qp);
2047                         return ERR_PTR(err);
2048                 }
2049
2050                 if (is_qp0(init_attr->qp_type))
2051                         qp->ibqp.qp_num = 0;
2052                 else if (is_qp1(init_attr->qp_type))
2053                         qp->ibqp.qp_num = 1;
2054                 else
2055                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2056
2057                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2058                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2059                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2060                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2061
2062                 qp->trans_qp.xrcdn = xrcdn;
2063
2064                 break;
2065
2066         case IB_QPT_GSI:
2067                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2068
2069         case IB_QPT_RAW_IPV6:
2070         case IB_QPT_RAW_ETHERTYPE:
2071         case IB_QPT_MAX:
2072         default:
2073                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2074                             init_attr->qp_type);
2075                 /* Don't support raw QPs */
2076                 return ERR_PTR(-EINVAL);
2077         }
2078
2079         return &qp->ibqp;
2080 }
2081
2082 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2083 {
2084         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2085         struct mlx5_ib_qp *mqp = to_mqp(qp);
2086
2087         if (unlikely(qp->qp_type == IB_QPT_GSI))
2088                 return mlx5_ib_gsi_destroy_qp(qp);
2089
2090         destroy_qp_common(dev, mqp);
2091
2092         kfree(mqp);
2093
2094         return 0;
2095 }
2096
2097 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2098                                    int attr_mask)
2099 {
2100         u32 hw_access_flags = 0;
2101         u8 dest_rd_atomic;
2102         u32 access_flags;
2103
2104         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2105                 dest_rd_atomic = attr->max_dest_rd_atomic;
2106         else
2107                 dest_rd_atomic = qp->trans_qp.resp_depth;
2108
2109         if (attr_mask & IB_QP_ACCESS_FLAGS)
2110                 access_flags = attr->qp_access_flags;
2111         else
2112                 access_flags = qp->trans_qp.atomic_rd_en;
2113
2114         if (!dest_rd_atomic)
2115                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2116
2117         if (access_flags & IB_ACCESS_REMOTE_READ)
2118                 hw_access_flags |= MLX5_QP_BIT_RRE;
2119         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2120                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2121         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2122                 hw_access_flags |= MLX5_QP_BIT_RWE;
2123
2124         return cpu_to_be32(hw_access_flags);
2125 }
2126
2127 enum {
2128         MLX5_PATH_FLAG_FL       = 1 << 0,
2129         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2130         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2131 };
2132
2133 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2134 {
2135         if (rate == IB_RATE_PORT_CURRENT) {
2136                 return 0;
2137         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2138                 return -EINVAL;
2139         } else {
2140                 while (rate != IB_RATE_2_5_GBPS &&
2141                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2142                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2143                         --rate;
2144         }
2145
2146         return rate + MLX5_STAT_RATE_OFFSET;
2147 }
2148
2149 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2150                                       struct mlx5_ib_sq *sq, u8 sl)
2151 {
2152         void *in;
2153         void *tisc;
2154         int inlen;
2155         int err;
2156
2157         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2158         in = mlx5_vzalloc(inlen);
2159         if (!in)
2160                 return -ENOMEM;
2161
2162         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2163
2164         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2165         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2166
2167         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2168
2169         kvfree(in);
2170
2171         return err;
2172 }
2173
2174 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2175                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2176 {
2177         void *in;
2178         void *tisc;
2179         int inlen;
2180         int err;
2181
2182         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2183         in = mlx5_vzalloc(inlen);
2184         if (!in)
2185                 return -ENOMEM;
2186
2187         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2188
2189         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2190         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2191
2192         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2193
2194         kvfree(in);
2195
2196         return err;
2197 }
2198
2199 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2200                          const struct ib_ah_attr *ah,
2201                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2202                          u32 path_flags, const struct ib_qp_attr *attr,
2203                          bool alt)
2204 {
2205         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2206         int err;
2207
2208         if (attr_mask & IB_QP_PKEY_INDEX)
2209                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2210                                                      attr->pkey_index);
2211
2212         if (ah->ah_flags & IB_AH_GRH) {
2213                 if (ah->grh.sgid_index >=
2214                     dev->mdev->port_caps[port - 1].gid_table_len) {
2215                         pr_err("sgid_index (%u) too large. max is %d\n",
2216                                ah->grh.sgid_index,
2217                                dev->mdev->port_caps[port - 1].gid_table_len);
2218                         return -EINVAL;
2219                 }
2220         }
2221
2222         if (ll == IB_LINK_LAYER_ETHERNET) {
2223                 if (!(ah->ah_flags & IB_AH_GRH))
2224                         return -EINVAL;
2225                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2226                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2227                                                           ah->grh.sgid_index);
2228                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2229         } else {
2230                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2231                 path->fl_free_ar |=
2232                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2233                 path->rlid = cpu_to_be16(ah->dlid);
2234                 path->grh_mlid = ah->src_path_bits & 0x7f;
2235                 if (ah->ah_flags & IB_AH_GRH)
2236                         path->grh_mlid  |= 1 << 7;
2237                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2238         }
2239
2240         if (ah->ah_flags & IB_AH_GRH) {
2241                 path->mgid_index = ah->grh.sgid_index;
2242                 path->hop_limit  = ah->grh.hop_limit;
2243                 path->tclass_flowlabel =
2244                         cpu_to_be32((ah->grh.traffic_class << 20) |
2245                                     (ah->grh.flow_label));
2246                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2247         }
2248
2249         err = ib_rate_to_mlx5(dev, ah->static_rate);
2250         if (err < 0)
2251                 return err;
2252         path->static_rate = err;
2253         path->port = port;
2254
2255         if (attr_mask & IB_QP_TIMEOUT)
2256                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2257
2258         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2259                 return modify_raw_packet_eth_prio(dev->mdev,
2260                                                   &qp->raw_packet_qp.sq,
2261                                                   ah->sl & 0xf);
2262
2263         return 0;
2264 }
2265
2266 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2267         [MLX5_QP_STATE_INIT] = {
2268                 [MLX5_QP_STATE_INIT] = {
2269                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2270                                           MLX5_QP_OPTPAR_RAE            |
2271                                           MLX5_QP_OPTPAR_RWE            |
2272                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2273                                           MLX5_QP_OPTPAR_PRI_PORT,
2274                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2275                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2276                                           MLX5_QP_OPTPAR_PRI_PORT,
2277                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2278                                           MLX5_QP_OPTPAR_Q_KEY          |
2279                                           MLX5_QP_OPTPAR_PRI_PORT,
2280                 },
2281                 [MLX5_QP_STATE_RTR] = {
2282                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2283                                           MLX5_QP_OPTPAR_RRE            |
2284                                           MLX5_QP_OPTPAR_RAE            |
2285                                           MLX5_QP_OPTPAR_RWE            |
2286                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2287                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2288                                           MLX5_QP_OPTPAR_RWE            |
2289                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2290                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2291                                           MLX5_QP_OPTPAR_Q_KEY,
2292                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2293                                            MLX5_QP_OPTPAR_Q_KEY,
2294                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2295                                           MLX5_QP_OPTPAR_RRE            |
2296                                           MLX5_QP_OPTPAR_RAE            |
2297                                           MLX5_QP_OPTPAR_RWE            |
2298                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2299                 },
2300         },
2301         [MLX5_QP_STATE_RTR] = {
2302                 [MLX5_QP_STATE_RTS] = {
2303                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2304                                           MLX5_QP_OPTPAR_RRE            |
2305                                           MLX5_QP_OPTPAR_RAE            |
2306                                           MLX5_QP_OPTPAR_RWE            |
2307                                           MLX5_QP_OPTPAR_PM_STATE       |
2308                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2309                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2310                                           MLX5_QP_OPTPAR_RWE            |
2311                                           MLX5_QP_OPTPAR_PM_STATE,
2312                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2313                 },
2314         },
2315         [MLX5_QP_STATE_RTS] = {
2316                 [MLX5_QP_STATE_RTS] = {
2317                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2318                                           MLX5_QP_OPTPAR_RAE            |
2319                                           MLX5_QP_OPTPAR_RWE            |
2320                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2321                                           MLX5_QP_OPTPAR_PM_STATE       |
2322                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2323                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2324                                           MLX5_QP_OPTPAR_PM_STATE       |
2325                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2326                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2327                                           MLX5_QP_OPTPAR_SRQN           |
2328                                           MLX5_QP_OPTPAR_CQN_RCV,
2329                 },
2330         },
2331         [MLX5_QP_STATE_SQER] = {
2332                 [MLX5_QP_STATE_RTS] = {
2333                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2334                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2335                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2336                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2337                                            MLX5_QP_OPTPAR_RWE           |
2338                                            MLX5_QP_OPTPAR_RAE           |
2339                                            MLX5_QP_OPTPAR_RRE,
2340                 },
2341         },
2342 };
2343
2344 static int ib_nr_to_mlx5_nr(int ib_mask)
2345 {
2346         switch (ib_mask) {
2347         case IB_QP_STATE:
2348                 return 0;
2349         case IB_QP_CUR_STATE:
2350                 return 0;
2351         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2352                 return 0;
2353         case IB_QP_ACCESS_FLAGS:
2354                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2355                         MLX5_QP_OPTPAR_RAE;
2356         case IB_QP_PKEY_INDEX:
2357                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2358         case IB_QP_PORT:
2359                 return MLX5_QP_OPTPAR_PRI_PORT;
2360         case IB_QP_QKEY:
2361                 return MLX5_QP_OPTPAR_Q_KEY;
2362         case IB_QP_AV:
2363                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2364                         MLX5_QP_OPTPAR_PRI_PORT;
2365         case IB_QP_PATH_MTU:
2366                 return 0;
2367         case IB_QP_TIMEOUT:
2368                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2369         case IB_QP_RETRY_CNT:
2370                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2371         case IB_QP_RNR_RETRY:
2372                 return MLX5_QP_OPTPAR_RNR_RETRY;
2373         case IB_QP_RQ_PSN:
2374                 return 0;
2375         case IB_QP_MAX_QP_RD_ATOMIC:
2376                 return MLX5_QP_OPTPAR_SRA_MAX;
2377         case IB_QP_ALT_PATH:
2378                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2379         case IB_QP_MIN_RNR_TIMER:
2380                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2381         case IB_QP_SQ_PSN:
2382                 return 0;
2383         case IB_QP_MAX_DEST_RD_ATOMIC:
2384                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2385                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2386         case IB_QP_PATH_MIG_STATE:
2387                 return MLX5_QP_OPTPAR_PM_STATE;
2388         case IB_QP_CAP:
2389                 return 0;
2390         case IB_QP_DEST_QPN:
2391                 return 0;
2392         }
2393         return 0;
2394 }
2395
2396 static int ib_mask_to_mlx5_opt(int ib_mask)
2397 {
2398         int result = 0;
2399         int i;
2400
2401         for (i = 0; i < 8 * sizeof(int); i++) {
2402                 if ((1 << i) & ib_mask)
2403                         result |= ib_nr_to_mlx5_nr(1 << i);
2404         }
2405
2406         return result;
2407 }
2408
2409 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2410                                    struct mlx5_ib_rq *rq, int new_state,
2411                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2412 {
2413         void *in;
2414         void *rqc;
2415         int inlen;
2416         int err;
2417
2418         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2419         in = mlx5_vzalloc(inlen);
2420         if (!in)
2421                 return -ENOMEM;
2422
2423         MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn);
2424         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2425
2426         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2427         MLX5_SET(rqc, rqc, state, new_state);
2428
2429         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2430                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) {
2431                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2432                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2433                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2434                 } else
2435                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2436                                      dev->ib_dev.name);
2437         }
2438
2439         err = mlx5_core_modify_rq(dev->mdev, in, inlen);
2440         if (err)
2441                 goto out;
2442
2443         rq->state = new_state;
2444
2445 out:
2446         kvfree(in);
2447         return err;
2448 }
2449
2450 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2451                                    struct mlx5_ib_sq *sq, int new_state)
2452 {
2453         void *in;
2454         void *sqc;
2455         int inlen;
2456         int err;
2457
2458         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2459         in = mlx5_vzalloc(inlen);
2460         if (!in)
2461                 return -ENOMEM;
2462
2463         MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn);
2464         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2465
2466         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2467         MLX5_SET(sqc, sqc, state, new_state);
2468
2469         err = mlx5_core_modify_sq(dev, in, inlen);
2470         if (err)
2471                 goto out;
2472
2473         sq->state = new_state;
2474
2475 out:
2476         kvfree(in);
2477         return err;
2478 }
2479
2480 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2481                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2482                                 u8 tx_affinity)
2483 {
2484         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2485         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2486         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2487         int rq_state;
2488         int sq_state;
2489         int err;
2490
2491         switch (raw_qp_param->operation) {
2492         case MLX5_CMD_OP_RST2INIT_QP:
2493                 rq_state = MLX5_RQC_STATE_RDY;
2494                 sq_state = MLX5_SQC_STATE_RDY;
2495                 break;
2496         case MLX5_CMD_OP_2ERR_QP:
2497                 rq_state = MLX5_RQC_STATE_ERR;
2498                 sq_state = MLX5_SQC_STATE_ERR;
2499                 break;
2500         case MLX5_CMD_OP_2RST_QP:
2501                 rq_state = MLX5_RQC_STATE_RST;
2502                 sq_state = MLX5_SQC_STATE_RST;
2503                 break;
2504         case MLX5_CMD_OP_INIT2INIT_QP:
2505         case MLX5_CMD_OP_INIT2RTR_QP:
2506         case MLX5_CMD_OP_RTR2RTS_QP:
2507         case MLX5_CMD_OP_RTS2RTS_QP:
2508                 if (raw_qp_param->set_mask)
2509                         return -EINVAL;
2510                 else
2511                         return 0;
2512         default:
2513                 WARN_ON(1);
2514                 return -EINVAL;
2515         }
2516
2517         if (qp->rq.wqe_cnt) {
2518                 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2519                 if (err)
2520                         return err;
2521         }
2522
2523         if (qp->sq.wqe_cnt) {
2524                 if (tx_affinity) {
2525                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2526                                                             tx_affinity);
2527                         if (err)
2528                                 return err;
2529                 }
2530
2531                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2532         }
2533
2534         return 0;
2535 }
2536
2537 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2538                                const struct ib_qp_attr *attr, int attr_mask,
2539                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2540 {
2541         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2542                 [MLX5_QP_STATE_RST] = {
2543                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2544                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2545                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2546                 },
2547                 [MLX5_QP_STATE_INIT]  = {
2548                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2549                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2550                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2551                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2552                 },
2553                 [MLX5_QP_STATE_RTR]   = {
2554                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2555                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2556                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2557                 },
2558                 [MLX5_QP_STATE_RTS]   = {
2559                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2560                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2561                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2562                 },
2563                 [MLX5_QP_STATE_SQD] = {
2564                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2565                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2566                 },
2567                 [MLX5_QP_STATE_SQER] = {
2568                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2569                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2570                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2571                 },
2572                 [MLX5_QP_STATE_ERR] = {
2573                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2574                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2575                 }
2576         };
2577
2578         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2579         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2580         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2581         struct mlx5_ib_cq *send_cq, *recv_cq;
2582         struct mlx5_qp_context *context;
2583         struct mlx5_modify_qp_mbox_in *in;
2584         struct mlx5_ib_pd *pd;
2585         struct mlx5_ib_port *mibport = NULL;
2586         enum mlx5_qp_state mlx5_cur, mlx5_new;
2587         enum mlx5_qp_optpar optpar;
2588         int sqd_event;
2589         int mlx5_st;
2590         int err;
2591         u16 op;
2592
2593         in = kzalloc(sizeof(*in), GFP_KERNEL);
2594         if (!in)
2595                 return -ENOMEM;
2596
2597         context = &in->ctx;
2598         err = to_mlx5_st(ibqp->qp_type);
2599         if (err < 0) {
2600                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2601                 goto out;
2602         }
2603
2604         context->flags = cpu_to_be32(err << 16);
2605
2606         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2607                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2608         } else {
2609                 switch (attr->path_mig_state) {
2610                 case IB_MIG_MIGRATED:
2611                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2612                         break;
2613                 case IB_MIG_REARM:
2614                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2615                         break;
2616                 case IB_MIG_ARMED:
2617                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2618                         break;
2619                 }
2620         }
2621
2622         if (is_sqp(ibqp->qp_type)) {
2623                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2624         } else if (ibqp->qp_type == IB_QPT_UD ||
2625                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2626                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2627         } else if (attr_mask & IB_QP_PATH_MTU) {
2628                 if (attr->path_mtu < IB_MTU_256 ||
2629                     attr->path_mtu > IB_MTU_4096) {
2630                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2631                         err = -EINVAL;
2632                         goto out;
2633                 }
2634                 context->mtu_msgmax = (attr->path_mtu << 5) |
2635                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2636         }
2637
2638         if (attr_mask & IB_QP_DEST_QPN)
2639                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2640
2641         if (attr_mask & IB_QP_PKEY_INDEX)
2642                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2643
2644         /* todo implement counter_index functionality */
2645
2646         if (is_sqp(ibqp->qp_type))
2647                 context->pri_path.port = qp->port;
2648
2649         if (attr_mask & IB_QP_PORT)
2650                 context->pri_path.port = attr->port_num;
2651
2652         if (attr_mask & IB_QP_AV) {
2653                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2654                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2655                                     attr_mask, 0, attr, false);
2656                 if (err)
2657                         goto out;
2658         }
2659
2660         if (attr_mask & IB_QP_TIMEOUT)
2661                 context->pri_path.ackto_lt |= attr->timeout << 3;
2662
2663         if (attr_mask & IB_QP_ALT_PATH) {
2664                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2665                                     &context->alt_path,
2666                                     attr->alt_port_num,
2667                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2668                                     0, attr, true);
2669                 if (err)
2670                         goto out;
2671         }
2672
2673         pd = get_pd(qp);
2674         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2675                 &send_cq, &recv_cq);
2676
2677         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2678         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2679         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2680         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2681
2682         if (attr_mask & IB_QP_RNR_RETRY)
2683                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2684
2685         if (attr_mask & IB_QP_RETRY_CNT)
2686                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2687
2688         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2689                 if (attr->max_rd_atomic)
2690                         context->params1 |=
2691                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2692         }
2693
2694         if (attr_mask & IB_QP_SQ_PSN)
2695                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2696
2697         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2698                 if (attr->max_dest_rd_atomic)
2699                         context->params2 |=
2700                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2701         }
2702
2703         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2704                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2705
2706         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2707                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2708
2709         if (attr_mask & IB_QP_RQ_PSN)
2710                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2711
2712         if (attr_mask & IB_QP_QKEY)
2713                 context->qkey = cpu_to_be32(attr->qkey);
2714
2715         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2716                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2717
2718         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2719             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2720                 sqd_event = 1;
2721         else
2722                 sqd_event = 0;
2723
2724         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2725                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2726                                qp->port) - 1;
2727                 mibport = &dev->port[port_num];
2728                 context->qp_counter_set_usr_page |=
2729                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2730         }
2731
2732         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2733                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2734
2735         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2736                 context->deth_sqpn = cpu_to_be32(1);
2737
2738         mlx5_cur = to_mlx5_state(cur_state);
2739         mlx5_new = to_mlx5_state(new_state);
2740         mlx5_st = to_mlx5_st(ibqp->qp_type);
2741         if (mlx5_st < 0)
2742                 goto out;
2743
2744         /* If moving to a reset or error state, we must disable page faults on
2745          * this QP and flush all current page faults. Otherwise a stale page
2746          * fault may attempt to work on this QP after it is reset and moved
2747          * again to RTS, and may cause the driver and the device to get out of
2748          * sync. */
2749         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2750             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2751             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2752                 mlx5_ib_qp_disable_pagefaults(qp);
2753
2754         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2755             !optab[mlx5_cur][mlx5_new])
2756                 goto out;
2757
2758         op = optab[mlx5_cur][mlx5_new];
2759         optpar = ib_mask_to_mlx5_opt(attr_mask);
2760         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2761         in->optparam = cpu_to_be32(optpar);
2762
2763         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2764                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2765
2766                 raw_qp_param.operation = op;
2767                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2768                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2769                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2770                 }
2771                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2772         } else {
2773                 err = mlx5_core_qp_modify(dev->mdev, op, in, 0, &base->mqp);
2774         }
2775
2776         if (err)
2777                 goto out;
2778
2779         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2780             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2781                 mlx5_ib_qp_enable_pagefaults(qp);
2782
2783         qp->state = new_state;
2784
2785         if (attr_mask & IB_QP_ACCESS_FLAGS)
2786                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2787         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2788                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2789         if (attr_mask & IB_QP_PORT)
2790                 qp->port = attr->port_num;
2791         if (attr_mask & IB_QP_ALT_PATH)
2792                 qp->trans_qp.alt_port = attr->alt_port_num;
2793
2794         /*
2795          * If we moved a kernel QP to RESET, clean up all old CQ
2796          * entries and reinitialize the QP.
2797          */
2798         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2799                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2800                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2801                 if (send_cq != recv_cq)
2802                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2803
2804                 qp->rq.head = 0;
2805                 qp->rq.tail = 0;
2806                 qp->sq.head = 0;
2807                 qp->sq.tail = 0;
2808                 qp->sq.cur_post = 0;
2809                 qp->sq.last_poll = 0;
2810                 qp->db.db[MLX5_RCV_DBR] = 0;
2811                 qp->db.db[MLX5_SND_DBR] = 0;
2812         }
2813
2814 out:
2815         kfree(in);
2816         return err;
2817 }
2818
2819 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2820                       int attr_mask, struct ib_udata *udata)
2821 {
2822         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2823         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2824         enum ib_qp_type qp_type;
2825         enum ib_qp_state cur_state, new_state;
2826         int err = -EINVAL;
2827         int port;
2828         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2829
2830         if (ibqp->rwq_ind_tbl)
2831                 return -ENOSYS;
2832
2833         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2834                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2835
2836         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2837                 IB_QPT_GSI : ibqp->qp_type;
2838
2839         mutex_lock(&qp->mutex);
2840
2841         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2842         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2843
2844         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2845                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2846                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2847         }
2848
2849         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2850             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2851                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2852                             cur_state, new_state, ibqp->qp_type, attr_mask);
2853                 goto out;
2854         }
2855
2856         if ((attr_mask & IB_QP_PORT) &&
2857             (attr->port_num == 0 ||
2858              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2859                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2860                             attr->port_num, dev->num_ports);
2861                 goto out;
2862         }
2863
2864         if (attr_mask & IB_QP_PKEY_INDEX) {
2865                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2866                 if (attr->pkey_index >=
2867                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2868                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2869                                     attr->pkey_index);
2870                         goto out;
2871                 }
2872         }
2873
2874         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2875             attr->max_rd_atomic >
2876             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2877                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2878                             attr->max_rd_atomic);
2879                 goto out;
2880         }
2881
2882         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2883             attr->max_dest_rd_atomic >
2884             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2885                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2886                             attr->max_dest_rd_atomic);
2887                 goto out;
2888         }
2889
2890         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2891                 err = 0;
2892                 goto out;
2893         }
2894
2895         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2896
2897 out:
2898         mutex_unlock(&qp->mutex);
2899         return err;
2900 }
2901
2902 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2903 {
2904         struct mlx5_ib_cq *cq;
2905         unsigned cur;
2906
2907         cur = wq->head - wq->tail;
2908         if (likely(cur + nreq < wq->max_post))
2909                 return 0;
2910
2911         cq = to_mcq(ib_cq);
2912         spin_lock(&cq->lock);
2913         cur = wq->head - wq->tail;
2914         spin_unlock(&cq->lock);
2915
2916         return cur + nreq >= wq->max_post;
2917 }
2918
2919 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2920                                           u64 remote_addr, u32 rkey)
2921 {
2922         rseg->raddr    = cpu_to_be64(remote_addr);
2923         rseg->rkey     = cpu_to_be32(rkey);
2924         rseg->reserved = 0;
2925 }
2926
2927 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2928                          struct ib_send_wr *wr, void *qend,
2929                          struct mlx5_ib_qp *qp, int *size)
2930 {
2931         void *seg = eseg;
2932
2933         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2934
2935         if (wr->send_flags & IB_SEND_IP_CSUM)
2936                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2937                                  MLX5_ETH_WQE_L4_CSUM;
2938
2939         seg += sizeof(struct mlx5_wqe_eth_seg);
2940         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2941
2942         if (wr->opcode == IB_WR_LSO) {
2943                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2944                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2945                 u64 left, leftlen, copysz;
2946                 void *pdata = ud_wr->header;
2947
2948                 left = ud_wr->hlen;
2949                 eseg->mss = cpu_to_be16(ud_wr->mss);
2950                 eseg->inline_hdr_sz = cpu_to_be16(left);
2951
2952                 /*
2953                  * check if there is space till the end of queue, if yes,
2954                  * copy all in one shot, otherwise copy till the end of queue,
2955                  * rollback and than the copy the left
2956                  */
2957                 leftlen = qend - (void *)eseg->inline_hdr_start;
2958                 copysz = min_t(u64, leftlen, left);
2959
2960                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2961
2962                 if (likely(copysz > size_of_inl_hdr_start)) {
2963                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2964                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2965                 }
2966
2967                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2968                         seg = mlx5_get_send_wqe(qp, 0);
2969                         left -= copysz;
2970                         pdata += copysz;
2971                         memcpy(seg, pdata, left);
2972                         seg += ALIGN(left, 16);
2973                         *size += ALIGN(left, 16) / 16;
2974                 }
2975         }
2976
2977         return seg;
2978 }
2979
2980 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2981                              struct ib_send_wr *wr)
2982 {
2983         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2984         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2985         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2986 }
2987
2988 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2989 {
2990         dseg->byte_count = cpu_to_be32(sg->length);
2991         dseg->lkey       = cpu_to_be32(sg->lkey);
2992         dseg->addr       = cpu_to_be64(sg->addr);
2993 }
2994
2995 static __be16 get_klm_octo(int npages)
2996 {
2997         return cpu_to_be16(ALIGN(npages, 8) / 2);
2998 }
2999
3000 static __be64 frwr_mkey_mask(void)
3001 {
3002         u64 result;
3003
3004         result = MLX5_MKEY_MASK_LEN             |
3005                 MLX5_MKEY_MASK_PAGE_SIZE        |
3006                 MLX5_MKEY_MASK_START_ADDR       |
3007                 MLX5_MKEY_MASK_EN_RINVAL        |
3008                 MLX5_MKEY_MASK_KEY              |
3009                 MLX5_MKEY_MASK_LR               |
3010                 MLX5_MKEY_MASK_LW               |
3011                 MLX5_MKEY_MASK_RR               |
3012                 MLX5_MKEY_MASK_RW               |
3013                 MLX5_MKEY_MASK_A                |
3014                 MLX5_MKEY_MASK_SMALL_FENCE      |
3015                 MLX5_MKEY_MASK_FREE;
3016
3017         return cpu_to_be64(result);
3018 }
3019
3020 static __be64 sig_mkey_mask(void)
3021 {
3022         u64 result;
3023
3024         result = MLX5_MKEY_MASK_LEN             |
3025                 MLX5_MKEY_MASK_PAGE_SIZE        |
3026                 MLX5_MKEY_MASK_START_ADDR       |
3027                 MLX5_MKEY_MASK_EN_SIGERR        |
3028                 MLX5_MKEY_MASK_EN_RINVAL        |
3029                 MLX5_MKEY_MASK_KEY              |
3030                 MLX5_MKEY_MASK_LR               |
3031                 MLX5_MKEY_MASK_LW               |
3032                 MLX5_MKEY_MASK_RR               |
3033                 MLX5_MKEY_MASK_RW               |
3034                 MLX5_MKEY_MASK_SMALL_FENCE      |
3035                 MLX5_MKEY_MASK_FREE             |
3036                 MLX5_MKEY_MASK_BSF_EN;
3037
3038         return cpu_to_be64(result);
3039 }
3040
3041 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3042                                 struct mlx5_ib_mr *mr)
3043 {
3044         int ndescs = mr->ndescs;
3045
3046         memset(umr, 0, sizeof(*umr));
3047
3048         if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3049                 /* KLMs take twice the size of MTTs */
3050                 ndescs *= 2;
3051
3052         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3053         umr->klm_octowords = get_klm_octo(ndescs);
3054         umr->mkey_mask = frwr_mkey_mask();
3055 }
3056
3057 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3058 {
3059         memset(umr, 0, sizeof(*umr));
3060         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3061         umr->flags = 1 << 7;
3062 }
3063
3064 static __be64 get_umr_reg_mr_mask(void)
3065 {
3066         u64 result;
3067
3068         result = MLX5_MKEY_MASK_LEN             |
3069                  MLX5_MKEY_MASK_PAGE_SIZE       |
3070                  MLX5_MKEY_MASK_START_ADDR      |
3071                  MLX5_MKEY_MASK_PD              |
3072                  MLX5_MKEY_MASK_LR              |
3073                  MLX5_MKEY_MASK_LW              |
3074                  MLX5_MKEY_MASK_KEY             |
3075                  MLX5_MKEY_MASK_RR              |
3076                  MLX5_MKEY_MASK_RW              |
3077                  MLX5_MKEY_MASK_A               |
3078                  MLX5_MKEY_MASK_FREE;
3079
3080         return cpu_to_be64(result);
3081 }
3082
3083 static __be64 get_umr_unreg_mr_mask(void)
3084 {
3085         u64 result;
3086
3087         result = MLX5_MKEY_MASK_FREE;
3088
3089         return cpu_to_be64(result);
3090 }
3091
3092 static __be64 get_umr_update_mtt_mask(void)
3093 {
3094         u64 result;
3095
3096         result = MLX5_MKEY_MASK_FREE;
3097
3098         return cpu_to_be64(result);
3099 }
3100
3101 static __be64 get_umr_update_translation_mask(void)
3102 {
3103         u64 result;
3104
3105         result = MLX5_MKEY_MASK_LEN |
3106                  MLX5_MKEY_MASK_PAGE_SIZE |
3107                  MLX5_MKEY_MASK_START_ADDR |
3108                  MLX5_MKEY_MASK_KEY |
3109                  MLX5_MKEY_MASK_FREE;
3110
3111         return cpu_to_be64(result);
3112 }
3113
3114 static __be64 get_umr_update_access_mask(void)
3115 {
3116         u64 result;
3117
3118         result = MLX5_MKEY_MASK_LW |
3119                  MLX5_MKEY_MASK_RR |
3120                  MLX5_MKEY_MASK_RW |
3121                  MLX5_MKEY_MASK_A |
3122                  MLX5_MKEY_MASK_KEY |
3123                  MLX5_MKEY_MASK_FREE;
3124
3125         return cpu_to_be64(result);
3126 }
3127
3128 static __be64 get_umr_update_pd_mask(void)
3129 {
3130         u64 result;
3131
3132         result = MLX5_MKEY_MASK_PD |
3133                  MLX5_MKEY_MASK_KEY |
3134                  MLX5_MKEY_MASK_FREE;
3135
3136         return cpu_to_be64(result);
3137 }
3138
3139 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3140                                 struct ib_send_wr *wr)
3141 {
3142         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3143
3144         memset(umr, 0, sizeof(*umr));
3145
3146         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3147                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3148         else
3149                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3150
3151         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3152                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3153                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3154                         umr->mkey_mask = get_umr_update_mtt_mask();
3155                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3156                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3157                 }
3158                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3159                         umr->mkey_mask |= get_umr_update_translation_mask();
3160                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3161                         umr->mkey_mask |= get_umr_update_access_mask();
3162                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3163                         umr->mkey_mask |= get_umr_update_pd_mask();
3164                 if (!umr->mkey_mask)
3165                         umr->mkey_mask = get_umr_reg_mr_mask();
3166         } else {
3167                 umr->mkey_mask = get_umr_unreg_mr_mask();
3168         }
3169
3170         if (!wr->num_sge)
3171                 umr->flags |= MLX5_UMR_INLINE;
3172 }
3173
3174 static u8 get_umr_flags(int acc)
3175 {
3176         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3177                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3178                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3179                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3180                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3181 }
3182
3183 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3184                              struct mlx5_ib_mr *mr,
3185                              u32 key, int access)
3186 {
3187         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3188
3189         memset(seg, 0, sizeof(*seg));
3190
3191         if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3192                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3193         else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3194                 /* KLMs take twice the size of MTTs */
3195                 ndescs *= 2;
3196
3197         seg->flags = get_umr_flags(access) | mr->access_mode;
3198         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3199         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3200         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3201         seg->len = cpu_to_be64(mr->ibmr.length);
3202         seg->xlt_oct_size = cpu_to_be32(ndescs);
3203 }
3204
3205 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3206 {
3207         memset(seg, 0, sizeof(*seg));
3208         seg->status = MLX5_MKEY_STATUS_FREE;
3209 }
3210
3211 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3212 {
3213         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3214
3215         memset(seg, 0, sizeof(*seg));
3216         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3217                 seg->status = MLX5_MKEY_STATUS_FREE;
3218                 return;
3219         }
3220
3221         seg->flags = convert_access(umrwr->access_flags);
3222         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3223                 if (umrwr->pd)
3224                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3225                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3226         }
3227         seg->len = cpu_to_be64(umrwr->length);
3228         seg->log2_page_size = umrwr->page_shift;
3229         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3230                                        mlx5_mkey_variant(umrwr->mkey));
3231 }
3232
3233 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3234                              struct mlx5_ib_mr *mr,
3235                              struct mlx5_ib_pd *pd)
3236 {
3237         int bcount = mr->desc_size * mr->ndescs;
3238
3239         dseg->addr = cpu_to_be64(mr->desc_map);
3240         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3241         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3242 }
3243
3244 static __be32 send_ieth(struct ib_send_wr *wr)
3245 {
3246         switch (wr->opcode) {
3247         case IB_WR_SEND_WITH_IMM:
3248         case IB_WR_RDMA_WRITE_WITH_IMM:
3249                 return wr->ex.imm_data;
3250
3251         case IB_WR_SEND_WITH_INV:
3252                 return cpu_to_be32(wr->ex.invalidate_rkey);
3253
3254         default:
3255                 return 0;
3256         }
3257 }
3258
3259 static u8 calc_sig(void *wqe, int size)
3260 {
3261         u8 *p = wqe;
3262         u8 res = 0;
3263         int i;
3264
3265         for (i = 0; i < size; i++)
3266                 res ^= p[i];
3267
3268         return ~res;
3269 }
3270
3271 static u8 wq_sig(void *wqe)
3272 {
3273         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3274 }
3275
3276 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3277                             void *wqe, int *sz)
3278 {
3279         struct mlx5_wqe_inline_seg *seg;
3280         void *qend = qp->sq.qend;
3281         void *addr;
3282         int inl = 0;
3283         int copy;
3284         int len;
3285         int i;
3286
3287         seg = wqe;
3288         wqe += sizeof(*seg);
3289         for (i = 0; i < wr->num_sge; i++) {
3290                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3291                 len  = wr->sg_list[i].length;
3292                 inl += len;
3293
3294                 if (unlikely(inl > qp->max_inline_data))
3295                         return -ENOMEM;
3296
3297                 if (unlikely(wqe + len > qend)) {
3298                         copy = qend - wqe;
3299                         memcpy(wqe, addr, copy);
3300                         addr += copy;
3301                         len -= copy;
3302                         wqe = mlx5_get_send_wqe(qp, 0);
3303                 }
3304                 memcpy(wqe, addr, len);
3305                 wqe += len;
3306         }
3307
3308         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3309
3310         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3311
3312         return 0;
3313 }
3314
3315 static u16 prot_field_size(enum ib_signature_type type)
3316 {
3317         switch (type) {
3318         case IB_SIG_TYPE_T10_DIF:
3319                 return MLX5_DIF_SIZE;
3320         default:
3321                 return 0;
3322         }
3323 }
3324
3325 static u8 bs_selector(int block_size)
3326 {
3327         switch (block_size) {
3328         case 512:           return 0x1;
3329         case 520:           return 0x2;
3330         case 4096:          return 0x3;
3331         case 4160:          return 0x4;
3332         case 1073741824:    return 0x5;
3333         default:            return 0;
3334         }
3335 }
3336
3337 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3338                               struct mlx5_bsf_inl *inl)
3339 {
3340         /* Valid inline section and allow BSF refresh */
3341         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3342                                        MLX5_BSF_REFRESH_DIF);
3343         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3344         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3345         /* repeating block */
3346         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3347         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3348                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3349
3350         if (domain->sig.dif.ref_remap)
3351                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3352
3353         if (domain->sig.dif.app_escape) {
3354                 if (domain->sig.dif.ref_escape)
3355                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3356                 else
3357                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3358         }
3359
3360         inl->dif_app_bitmask_check =
3361                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3362 }
3363
3364 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3365                         struct ib_sig_attrs *sig_attrs,
3366                         struct mlx5_bsf *bsf, u32 data_size)
3367 {
3368         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3369         struct mlx5_bsf_basic *basic = &bsf->basic;
3370         struct ib_sig_domain *mem = &sig_attrs->mem;
3371         struct ib_sig_domain *wire = &sig_attrs->wire;
3372
3373         memset(bsf, 0, sizeof(*bsf));
3374
3375         /* Basic + Extended + Inline */
3376         basic->bsf_size_sbs = 1 << 7;
3377         /* Input domain check byte mask */
3378         basic->check_byte_mask = sig_attrs->check_mask;
3379         basic->raw_data_size = cpu_to_be32(data_size);
3380
3381         /* Memory domain */
3382         switch (sig_attrs->mem.sig_type) {
3383         case IB_SIG_TYPE_NONE:
3384                 break;
3385         case IB_SIG_TYPE_T10_DIF:
3386                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3387                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3388                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3389                 break;
3390         default:
3391                 return -EINVAL;
3392         }
3393
3394         /* Wire domain */
3395         switch (sig_attrs->wire.sig_type) {
3396         case IB_SIG_TYPE_NONE:
3397                 break;
3398         case IB_SIG_TYPE_T10_DIF:
3399                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3400                     mem->sig_type == wire->sig_type) {
3401                         /* Same block structure */
3402                         basic->bsf_size_sbs |= 1 << 4;
3403                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3404                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3405                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3406                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3407                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3408                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3409                 } else
3410                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3411
3412                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3413                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3414                 break;
3415         default:
3416                 return -EINVAL;
3417         }
3418
3419         return 0;
3420 }
3421
3422 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3423                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3424 {
3425         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3426         struct ib_mr *sig_mr = wr->sig_mr;
3427         struct mlx5_bsf *bsf;
3428         u32 data_len = wr->wr.sg_list->length;
3429         u32 data_key = wr->wr.sg_list->lkey;
3430         u64 data_va = wr->wr.sg_list->addr;
3431         int ret;
3432         int wqe_size;
3433
3434         if (!wr->prot ||
3435             (data_key == wr->prot->lkey &&
3436              data_va == wr->prot->addr &&
3437              data_len == wr->prot->length)) {
3438                 /**
3439                  * Source domain doesn't contain signature information
3440                  * or data and protection are interleaved in memory.
3441                  * So need construct:
3442                  *                  ------------------
3443                  *                 |     data_klm     |
3444                  *                  ------------------
3445                  *                 |       BSF        |
3446                  *                  ------------------
3447                  **/
3448                 struct mlx5_klm *data_klm = *seg;
3449
3450                 data_klm->bcount = cpu_to_be32(data_len);
3451                 data_klm->key = cpu_to_be32(data_key);
3452                 data_klm->va = cpu_to_be64(data_va);
3453                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3454         } else {
3455                 /**
3456                  * Source domain contains signature information
3457                  * So need construct a strided block format:
3458                  *               ---------------------------
3459                  *              |     stride_block_ctrl     |
3460                  *               ---------------------------
3461                  *              |          data_klm         |
3462                  *               ---------------------------
3463                  *              |          prot_klm         |
3464                  *               ---------------------------
3465                  *              |             BSF           |
3466                  *               ---------------------------
3467                  **/
3468                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3469                 struct mlx5_stride_block_entry *data_sentry;
3470                 struct mlx5_stride_block_entry *prot_sentry;
3471                 u32 prot_key = wr->prot->lkey;
3472                 u64 prot_va = wr->prot->addr;
3473                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3474                 int prot_size;
3475
3476                 sblock_ctrl = *seg;
3477                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3478                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3479
3480                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3481                 if (!prot_size) {
3482                         pr_err("Bad block size given: %u\n", block_size);
3483                         return -EINVAL;
3484                 }
3485                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3486                                                             prot_size);
3487                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3488                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3489                 sblock_ctrl->num_entries = cpu_to_be16(2);
3490
3491                 data_sentry->bcount = cpu_to_be16(block_size);
3492                 data_sentry->key = cpu_to_be32(data_key);
3493                 data_sentry->va = cpu_to_be64(data_va);
3494                 data_sentry->stride = cpu_to_be16(block_size);
3495
3496                 prot_sentry->bcount = cpu_to_be16(prot_size);
3497                 prot_sentry->key = cpu_to_be32(prot_key);
3498                 prot_sentry->va = cpu_to_be64(prot_va);
3499                 prot_sentry->stride = cpu_to_be16(prot_size);
3500
3501                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3502                                  sizeof(*prot_sentry), 64);
3503         }
3504
3505         *seg += wqe_size;
3506         *size += wqe_size / 16;
3507         if (unlikely((*seg == qp->sq.qend)))
3508                 *seg = mlx5_get_send_wqe(qp, 0);
3509
3510         bsf = *seg;
3511         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3512         if (ret)
3513                 return -EINVAL;
3514
3515         *seg += sizeof(*bsf);
3516         *size += sizeof(*bsf) / 16;
3517         if (unlikely((*seg == qp->sq.qend)))
3518                 *seg = mlx5_get_send_wqe(qp, 0);
3519
3520         return 0;
3521 }
3522
3523 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3524                                  struct ib_sig_handover_wr *wr, u32 nelements,
3525                                  u32 length, u32 pdn)
3526 {
3527         struct ib_mr *sig_mr = wr->sig_mr;
3528         u32 sig_key = sig_mr->rkey;
3529         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3530
3531         memset(seg, 0, sizeof(*seg));
3532
3533         seg->flags = get_umr_flags(wr->access_flags) |
3534                                    MLX5_ACCESS_MODE_KLM;
3535         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3536         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3537                                     MLX5_MKEY_BSF_EN | pdn);
3538         seg->len = cpu_to_be64(length);
3539         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3540         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3541 }
3542
3543 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3544                                 u32 nelements)
3545 {
3546         memset(umr, 0, sizeof(*umr));
3547
3548         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3549         umr->klm_octowords = get_klm_octo(nelements);
3550         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3551         umr->mkey_mask = sig_mkey_mask();
3552 }
3553
3554
3555 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3556                           void **seg, int *size)
3557 {
3558         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3559         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3560         u32 pdn = get_pd(qp)->pdn;
3561         u32 klm_oct_size;
3562         int region_len, ret;
3563
3564         if (unlikely(wr->wr.num_sge != 1) ||
3565             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3566             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3567             unlikely(!sig_mr->sig->sig_status_checked))
3568                 return -EINVAL;
3569
3570         /* length of the protected region, data + protection */
3571         region_len = wr->wr.sg_list->length;
3572         if (wr->prot &&
3573             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3574              wr->prot->addr != wr->wr.sg_list->addr  ||
3575              wr->prot->length != wr->wr.sg_list->length))
3576                 region_len += wr->prot->length;
3577
3578         /**
3579          * KLM octoword size - if protection was provided
3580          * then we use strided block format (3 octowords),
3581          * else we use single KLM (1 octoword)
3582          **/
3583         klm_oct_size = wr->prot ? 3 : 1;
3584
3585         set_sig_umr_segment(*seg, klm_oct_size);
3586         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3587         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3588         if (unlikely((*seg == qp->sq.qend)))
3589                 *seg = mlx5_get_send_wqe(qp, 0);
3590
3591         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3592         *seg += sizeof(struct mlx5_mkey_seg);
3593         *size += sizeof(struct mlx5_mkey_seg) / 16;
3594         if (unlikely((*seg == qp->sq.qend)))
3595                 *seg = mlx5_get_send_wqe(qp, 0);
3596
3597         ret = set_sig_data_segment(wr, qp, seg, size);
3598         if (ret)
3599                 return ret;
3600
3601         sig_mr->sig->sig_status_checked = false;
3602         return 0;
3603 }
3604
3605 static int set_psv_wr(struct ib_sig_domain *domain,
3606                       u32 psv_idx, void **seg, int *size)
3607 {
3608         struct mlx5_seg_set_psv *psv_seg = *seg;
3609
3610         memset(psv_seg, 0, sizeof(*psv_seg));
3611         psv_seg->psv_num = cpu_to_be32(psv_idx);
3612         switch (domain->sig_type) {
3613         case IB_SIG_TYPE_NONE:
3614                 break;
3615         case IB_SIG_TYPE_T10_DIF:
3616                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3617                                                      domain->sig.dif.app_tag);
3618                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3619                 break;
3620         default:
3621                 pr_err("Bad signature type given.\n");
3622                 return 1;
3623         }
3624
3625         *seg += sizeof(*psv_seg);
3626         *size += sizeof(*psv_seg) / 16;
3627
3628         return 0;
3629 }
3630
3631 static int set_reg_wr(struct mlx5_ib_qp *qp,
3632                       struct ib_reg_wr *wr,
3633                       void **seg, int *size)
3634 {
3635         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3636         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3637
3638         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3639                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3640                              "Invalid IB_SEND_INLINE send flag\n");
3641                 return -EINVAL;
3642         }
3643
3644         set_reg_umr_seg(*seg, mr);
3645         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3646         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3647         if (unlikely((*seg == qp->sq.qend)))
3648                 *seg = mlx5_get_send_wqe(qp, 0);
3649
3650         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3651         *seg += sizeof(struct mlx5_mkey_seg);
3652         *size += sizeof(struct mlx5_mkey_seg) / 16;
3653         if (unlikely((*seg == qp->sq.qend)))
3654                 *seg = mlx5_get_send_wqe(qp, 0);
3655
3656         set_reg_data_seg(*seg, mr, pd);
3657         *seg += sizeof(struct mlx5_wqe_data_seg);
3658         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3659
3660         return 0;
3661 }
3662
3663 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3664 {
3665         set_linv_umr_seg(*seg);
3666         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3667         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3668         if (unlikely((*seg == qp->sq.qend)))
3669                 *seg = mlx5_get_send_wqe(qp, 0);
3670         set_linv_mkey_seg(*seg);
3671         *seg += sizeof(struct mlx5_mkey_seg);
3672         *size += sizeof(struct mlx5_mkey_seg) / 16;
3673         if (unlikely((*seg == qp->sq.qend)))
3674                 *seg = mlx5_get_send_wqe(qp, 0);
3675 }
3676
3677 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3678 {
3679         __be32 *p = NULL;
3680         int tidx = idx;
3681         int i, j;
3682
3683         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3684         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3685                 if ((i & 0xf) == 0) {
3686                         void *buf = mlx5_get_send_wqe(qp, tidx);
3687                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3688                         p = buf;
3689                         j = 0;
3690                 }
3691                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3692                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3693                          be32_to_cpu(p[j + 3]));
3694         }
3695 }
3696
3697 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3698                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3699 {
3700         while (bytecnt > 0) {
3701                 __iowrite64_copy(dst++, src++, 8);
3702                 __iowrite64_copy(dst++, src++, 8);
3703                 __iowrite64_copy(dst++, src++, 8);
3704                 __iowrite64_copy(dst++, src++, 8);
3705                 __iowrite64_copy(dst++, src++, 8);
3706                 __iowrite64_copy(dst++, src++, 8);
3707                 __iowrite64_copy(dst++, src++, 8);
3708                 __iowrite64_copy(dst++, src++, 8);
3709                 bytecnt -= 64;
3710                 if (unlikely(src == qp->sq.qend))
3711                         src = mlx5_get_send_wqe(qp, 0);
3712         }
3713 }
3714
3715 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3716 {
3717         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3718                      wr->send_flags & IB_SEND_FENCE))
3719                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3720
3721         if (unlikely(fence)) {
3722                 if (wr->send_flags & IB_SEND_FENCE)
3723                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3724                 else
3725                         return fence;
3726         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3727                 return MLX5_FENCE_MODE_FENCE;
3728         }
3729
3730         return 0;
3731 }
3732
3733 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3734                      struct mlx5_wqe_ctrl_seg **ctrl,
3735                      struct ib_send_wr *wr, unsigned *idx,
3736                      int *size, int nreq)
3737 {
3738         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3739                 return -ENOMEM;
3740
3741         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3742         *seg = mlx5_get_send_wqe(qp, *idx);
3743         *ctrl = *seg;
3744         *(uint32_t *)(*seg + 8) = 0;
3745         (*ctrl)->imm = send_ieth(wr);
3746         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3747                 (wr->send_flags & IB_SEND_SIGNALED ?
3748                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3749                 (wr->send_flags & IB_SEND_SOLICITED ?
3750                  MLX5_WQE_CTRL_SOLICITED : 0);
3751
3752         *seg += sizeof(**ctrl);
3753         *size = sizeof(**ctrl) / 16;
3754
3755         return 0;
3756 }
3757
3758 static void finish_wqe(struct mlx5_ib_qp *qp,
3759                        struct mlx5_wqe_ctrl_seg *ctrl,
3760                        u8 size, unsigned idx, u64 wr_id,
3761                        int nreq, u8 fence, u8 next_fence,
3762                        u32 mlx5_opcode)
3763 {
3764         u8 opmod = 0;
3765
3766         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3767                                              mlx5_opcode | ((u32)opmod << 24));
3768         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3769         ctrl->fm_ce_se |= fence;
3770         qp->fm_cache = next_fence;
3771         if (unlikely(qp->wq_sig))
3772                 ctrl->signature = wq_sig(ctrl);
3773
3774         qp->sq.wrid[idx] = wr_id;
3775         qp->sq.w_list[idx].opcode = mlx5_opcode;
3776         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3777         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3778         qp->sq.w_list[idx].next = qp->sq.cur_post;
3779 }
3780
3781
3782 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3783                       struct ib_send_wr **bad_wr)
3784 {
3785         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3786         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3787         struct mlx5_core_dev *mdev = dev->mdev;
3788         struct mlx5_ib_qp *qp;
3789         struct mlx5_ib_mr *mr;
3790         struct mlx5_wqe_data_seg *dpseg;
3791         struct mlx5_wqe_xrc_seg *xrc;
3792         struct mlx5_bf *bf;
3793         int uninitialized_var(size);
3794         void *qend;
3795         unsigned long flags;
3796         unsigned idx;
3797         int err = 0;
3798         int inl = 0;
3799         int num_sge;
3800         void *seg;
3801         int nreq;
3802         int i;
3803         u8 next_fence = 0;
3804         u8 fence;
3805
3806         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3807                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3808
3809         qp = to_mqp(ibqp);
3810         bf = qp->bf;
3811         qend = qp->sq.qend;
3812
3813         spin_lock_irqsave(&qp->sq.lock, flags);
3814
3815         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3816                 err = -EIO;
3817                 *bad_wr = wr;
3818                 nreq = 0;
3819                 goto out;
3820         }
3821
3822         for (nreq = 0; wr; nreq++, wr = wr->next) {
3823                 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3824                         mlx5_ib_warn(dev, "\n");
3825                         err = -EINVAL;
3826                         *bad_wr = wr;
3827                         goto out;
3828                 }
3829
3830                 fence = qp->fm_cache;
3831                 num_sge = wr->num_sge;
3832                 if (unlikely(num_sge > qp->sq.max_gs)) {
3833                         mlx5_ib_warn(dev, "\n");
3834                         err = -EINVAL;
3835                         *bad_wr = wr;
3836                         goto out;
3837                 }
3838
3839                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3840                 if (err) {
3841                         mlx5_ib_warn(dev, "\n");
3842                         err = -ENOMEM;
3843                         *bad_wr = wr;
3844                         goto out;
3845                 }
3846
3847                 switch (ibqp->qp_type) {
3848                 case IB_QPT_XRC_INI:
3849                         xrc = seg;
3850                         seg += sizeof(*xrc);
3851                         size += sizeof(*xrc) / 16;
3852                         /* fall through */
3853                 case IB_QPT_RC:
3854                         switch (wr->opcode) {
3855                         case IB_WR_RDMA_READ:
3856                         case IB_WR_RDMA_WRITE:
3857                         case IB_WR_RDMA_WRITE_WITH_IMM:
3858                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3859                                               rdma_wr(wr)->rkey);
3860                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3861                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3862                                 break;
3863
3864                         case IB_WR_ATOMIC_CMP_AND_SWP:
3865                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3866                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3867                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3868                                 err = -ENOSYS;
3869                                 *bad_wr = wr;
3870                                 goto out;
3871
3872                         case IB_WR_LOCAL_INV:
3873                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3874                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3875                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3876                                 set_linv_wr(qp, &seg, &size);
3877                                 num_sge = 0;
3878                                 break;
3879
3880                         case IB_WR_REG_MR:
3881                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3882                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3883                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3884                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3885                                 if (err) {
3886                                         *bad_wr = wr;
3887                                         goto out;
3888                                 }
3889                                 num_sge = 0;
3890                                 break;
3891
3892                         case IB_WR_REG_SIG_MR:
3893                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3894                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3895
3896                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3897                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3898                                 if (err) {
3899                                         mlx5_ib_warn(dev, "\n");
3900                                         *bad_wr = wr;
3901                                         goto out;
3902                                 }
3903
3904                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3905                                            nreq, get_fence(fence, wr),
3906                                            next_fence, MLX5_OPCODE_UMR);
3907                                 /*
3908                                  * SET_PSV WQEs are not signaled and solicited
3909                                  * on error
3910                                  */
3911                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3912                                 wr->send_flags |= IB_SEND_SOLICITED;
3913                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3914                                                 &idx, &size, nreq);
3915                                 if (err) {
3916                                         mlx5_ib_warn(dev, "\n");
3917                                         err = -ENOMEM;
3918                                         *bad_wr = wr;
3919                                         goto out;
3920                                 }
3921
3922                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3923                                                  mr->sig->psv_memory.psv_idx, &seg,
3924                                                  &size);
3925                                 if (err) {
3926                                         mlx5_ib_warn(dev, "\n");
3927                                         *bad_wr = wr;
3928                                         goto out;
3929                                 }
3930
3931                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3932                                            nreq, get_fence(fence, wr),
3933                                            next_fence, MLX5_OPCODE_SET_PSV);
3934                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3935                                                 &idx, &size, nreq);
3936                                 if (err) {
3937                                         mlx5_ib_warn(dev, "\n");
3938                                         err = -ENOMEM;
3939                                         *bad_wr = wr;
3940                                         goto out;
3941                                 }
3942
3943                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3944                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3945                                                  mr->sig->psv_wire.psv_idx, &seg,
3946                                                  &size);
3947                                 if (err) {
3948                                         mlx5_ib_warn(dev, "\n");
3949                                         *bad_wr = wr;
3950                                         goto out;
3951                                 }
3952
3953                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3954                                            nreq, get_fence(fence, wr),
3955                                            next_fence, MLX5_OPCODE_SET_PSV);
3956                                 num_sge = 0;
3957                                 goto skip_psv;
3958
3959                         default:
3960                                 break;
3961                         }
3962                         break;
3963
3964                 case IB_QPT_UC:
3965                         switch (wr->opcode) {
3966                         case IB_WR_RDMA_WRITE:
3967                         case IB_WR_RDMA_WRITE_WITH_IMM:
3968                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3969                                               rdma_wr(wr)->rkey);
3970                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3971                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3972                                 break;
3973
3974                         default:
3975                                 break;
3976                         }
3977                         break;
3978
3979                 case IB_QPT_SMI:
3980                 case MLX5_IB_QPT_HW_GSI:
3981                         set_datagram_seg(seg, wr);
3982                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3983                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3984                         if (unlikely((seg == qend)))
3985                                 seg = mlx5_get_send_wqe(qp, 0);
3986                         break;
3987                 case IB_QPT_UD:
3988                         set_datagram_seg(seg, wr);
3989                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3990                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3991
3992                         if (unlikely((seg == qend)))
3993                                 seg = mlx5_get_send_wqe(qp, 0);
3994
3995                         /* handle qp that supports ud offload */
3996                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3997                                 struct mlx5_wqe_eth_pad *pad;
3998
3999                                 pad = seg;
4000                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4001                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4002                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4003
4004                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4005
4006                                 if (unlikely((seg == qend)))
4007                                         seg = mlx5_get_send_wqe(qp, 0);
4008                         }
4009                         break;
4010                 case MLX5_IB_QPT_REG_UMR:
4011                         if (wr->opcode != MLX5_IB_WR_UMR) {
4012                                 err = -EINVAL;
4013                                 mlx5_ib_warn(dev, "bad opcode\n");
4014                                 goto out;
4015                         }
4016                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4017                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4018                         set_reg_umr_segment(seg, wr);
4019                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4020                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4021                         if (unlikely((seg == qend)))
4022                                 seg = mlx5_get_send_wqe(qp, 0);
4023                         set_reg_mkey_segment(seg, wr);
4024                         seg += sizeof(struct mlx5_mkey_seg);
4025                         size += sizeof(struct mlx5_mkey_seg) / 16;
4026                         if (unlikely((seg == qend)))
4027                                 seg = mlx5_get_send_wqe(qp, 0);
4028                         break;
4029
4030                 default:
4031                         break;
4032                 }
4033
4034                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4035                         int uninitialized_var(sz);
4036
4037                         err = set_data_inl_seg(qp, wr, seg, &sz);
4038                         if (unlikely(err)) {
4039                                 mlx5_ib_warn(dev, "\n");
4040                                 *bad_wr = wr;
4041                                 goto out;
4042                         }
4043                         inl = 1;
4044                         size += sz;
4045                 } else {
4046                         dpseg = seg;
4047                         for (i = 0; i < num_sge; i++) {
4048                                 if (unlikely(dpseg == qend)) {
4049                                         seg = mlx5_get_send_wqe(qp, 0);
4050                                         dpseg = seg;
4051                                 }
4052                                 if (likely(wr->sg_list[i].length)) {
4053                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4054                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4055                                         dpseg++;
4056                                 }
4057                         }
4058                 }
4059
4060                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4061                            get_fence(fence, wr), next_fence,
4062                            mlx5_ib_opcode[wr->opcode]);
4063 skip_psv:
4064                 if (0)
4065                         dump_wqe(qp, idx, size);
4066         }
4067
4068 out:
4069         if (likely(nreq)) {
4070                 qp->sq.head += nreq;
4071
4072                 /* Make sure that descriptors are written before
4073                  * updating doorbell record and ringing the doorbell
4074                  */
4075                 wmb();
4076
4077                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4078
4079                 /* Make sure doorbell record is visible to the HCA before
4080                  * we hit doorbell */
4081                 wmb();
4082
4083                 if (bf->need_lock)
4084                         spin_lock(&bf->lock);
4085                 else
4086                         __acquire(&bf->lock);
4087
4088                 /* TBD enable WC */
4089                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4090                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4091                         /* wc_wmb(); */
4092                 } else {
4093                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4094                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4095                         /* Make sure doorbells don't leak out of SQ spinlock
4096                          * and reach the HCA out of order.
4097                          */
4098                         mmiowb();
4099                 }
4100                 bf->offset ^= bf->buf_size;
4101                 if (bf->need_lock)
4102                         spin_unlock(&bf->lock);
4103                 else
4104                         __release(&bf->lock);
4105         }
4106
4107         spin_unlock_irqrestore(&qp->sq.lock, flags);
4108
4109         return err;
4110 }
4111
4112 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4113 {
4114         sig->signature = calc_sig(sig, size);
4115 }
4116
4117 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4118                       struct ib_recv_wr **bad_wr)
4119 {
4120         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4121         struct mlx5_wqe_data_seg *scat;
4122         struct mlx5_rwqe_sig *sig;
4123         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4124         struct mlx5_core_dev *mdev = dev->mdev;
4125         unsigned long flags;
4126         int err = 0;
4127         int nreq;
4128         int ind;
4129         int i;
4130
4131         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4132                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4133
4134         spin_lock_irqsave(&qp->rq.lock, flags);
4135
4136         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4137                 err = -EIO;
4138                 *bad_wr = wr;
4139                 nreq = 0;
4140                 goto out;
4141         }
4142
4143         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4144
4145         for (nreq = 0; wr; nreq++, wr = wr->next) {
4146                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4147                         err = -ENOMEM;
4148                         *bad_wr = wr;
4149                         goto out;
4150                 }
4151
4152                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4153                         err = -EINVAL;
4154                         *bad_wr = wr;
4155                         goto out;
4156                 }
4157
4158                 scat = get_recv_wqe(qp, ind);
4159                 if (qp->wq_sig)
4160                         scat++;
4161
4162                 for (i = 0; i < wr->num_sge; i++)
4163                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4164
4165                 if (i < qp->rq.max_gs) {
4166                         scat[i].byte_count = 0;
4167                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4168                         scat[i].addr       = 0;
4169                 }
4170
4171                 if (qp->wq_sig) {
4172                         sig = (struct mlx5_rwqe_sig *)scat;
4173                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4174                 }
4175
4176                 qp->rq.wrid[ind] = wr->wr_id;
4177
4178                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4179         }
4180
4181 out:
4182         if (likely(nreq)) {
4183                 qp->rq.head += nreq;
4184
4185                 /* Make sure that descriptors are written before
4186                  * doorbell record.
4187                  */
4188                 wmb();
4189
4190                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4191         }
4192
4193         spin_unlock_irqrestore(&qp->rq.lock, flags);
4194
4195         return err;
4196 }
4197
4198 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4199 {
4200         switch (mlx5_state) {
4201         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4202         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4203         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4204         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4205         case MLX5_QP_STATE_SQ_DRAINING:
4206         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4207         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4208         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4209         default:                     return -1;
4210         }
4211 }
4212
4213 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4214 {
4215         switch (mlx5_mig_state) {
4216         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4217         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4218         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4219         default: return -1;
4220         }
4221 }
4222
4223 static int to_ib_qp_access_flags(int mlx5_flags)
4224 {
4225         int ib_flags = 0;
4226
4227         if (mlx5_flags & MLX5_QP_BIT_RRE)
4228                 ib_flags |= IB_ACCESS_REMOTE_READ;
4229         if (mlx5_flags & MLX5_QP_BIT_RWE)
4230                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4231         if (mlx5_flags & MLX5_QP_BIT_RAE)
4232                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4233
4234         return ib_flags;
4235 }
4236
4237 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4238                                 struct mlx5_qp_path *path)
4239 {
4240         struct mlx5_core_dev *dev = ibdev->mdev;
4241
4242         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4243         ib_ah_attr->port_num      = path->port;
4244
4245         if (ib_ah_attr->port_num == 0 ||
4246             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4247                 return;
4248
4249         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4250
4251         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4252         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4253         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4254         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4255         if (ib_ah_attr->ah_flags) {
4256                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4257                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4258                 ib_ah_attr->grh.traffic_class =
4259                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4260                 ib_ah_attr->grh.flow_label =
4261                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4262                 memcpy(ib_ah_attr->grh.dgid.raw,
4263                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4264         }
4265 }
4266
4267 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4268                                         struct mlx5_ib_sq *sq,
4269                                         u8 *sq_state)
4270 {
4271         void *out;
4272         void *sqc;
4273         int inlen;
4274         int err;
4275
4276         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4277         out = mlx5_vzalloc(inlen);
4278         if (!out)
4279                 return -ENOMEM;
4280
4281         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4282         if (err)
4283                 goto out;
4284
4285         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4286         *sq_state = MLX5_GET(sqc, sqc, state);
4287         sq->state = *sq_state;
4288
4289 out:
4290         kvfree(out);
4291         return err;
4292 }
4293
4294 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4295                                         struct mlx5_ib_rq *rq,
4296                                         u8 *rq_state)
4297 {
4298         void *out;
4299         void *rqc;
4300         int inlen;
4301         int err;
4302
4303         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4304         out = mlx5_vzalloc(inlen);
4305         if (!out)
4306                 return -ENOMEM;
4307
4308         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4309         if (err)
4310                 goto out;
4311
4312         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4313         *rq_state = MLX5_GET(rqc, rqc, state);
4314         rq->state = *rq_state;
4315
4316 out:
4317         kvfree(out);
4318         return err;
4319 }
4320
4321 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4322                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4323 {
4324         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4325                 [MLX5_RQC_STATE_RST] = {
4326                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4327                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4328                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4329                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4330                 },
4331                 [MLX5_RQC_STATE_RDY] = {
4332                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4333                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4334                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4335                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4336                 },
4337                 [MLX5_RQC_STATE_ERR] = {
4338                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4339                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4340                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4341                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4342                 },
4343                 [MLX5_RQ_STATE_NA] = {
4344                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4345                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4346                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4347                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4348                 },
4349         };
4350
4351         *qp_state = sqrq_trans[rq_state][sq_state];
4352
4353         if (*qp_state == MLX5_QP_STATE_BAD) {
4354                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4355                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4356                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4357                 return -EINVAL;
4358         }
4359
4360         if (*qp_state == MLX5_QP_STATE)
4361                 *qp_state = qp->state;
4362
4363         return 0;
4364 }
4365
4366 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4367                                      struct mlx5_ib_qp *qp,
4368                                      u8 *raw_packet_qp_state)
4369 {
4370         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4371         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4372         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4373         int err;
4374         u8 sq_state = MLX5_SQ_STATE_NA;
4375         u8 rq_state = MLX5_RQ_STATE_NA;
4376
4377         if (qp->sq.wqe_cnt) {
4378                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4379                 if (err)
4380                         return err;
4381         }
4382
4383         if (qp->rq.wqe_cnt) {
4384                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4385                 if (err)
4386                         return err;
4387         }
4388
4389         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4390                                       raw_packet_qp_state);
4391 }
4392
4393 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4394                          struct ib_qp_attr *qp_attr)
4395 {
4396         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4397         struct mlx5_qp_context *context;
4398         int mlx5_state;
4399         u32 *outb;
4400         int err = 0;
4401
4402         outb = kzalloc(outlen, GFP_KERNEL);
4403         if (!outb)
4404                 return -ENOMEM;
4405
4406         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp,
4407                                  (struct mlx5_query_qp_mbox_out *)outb,
4408                                  outlen);
4409         if (err)
4410                 goto out;
4411
4412         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4413         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4414
4415         mlx5_state = be32_to_cpu(context->flags) >> 28;
4416
4417         qp->state                    = to_ib_qp_state(mlx5_state);
4418         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4419         qp_attr->path_mig_state      =
4420                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4421         qp_attr->qkey                = be32_to_cpu(context->qkey);
4422         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4423         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4424         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4425         qp_attr->qp_access_flags     =
4426                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4427
4428         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4429                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4430                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4431                 qp_attr->alt_pkey_index =
4432                         be16_to_cpu(context->alt_path.pkey_index);
4433                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4434         }
4435
4436         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4437         qp_attr->port_num = context->pri_path.port;
4438
4439         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4440         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4441
4442         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4443
4444         qp_attr->max_dest_rd_atomic =
4445                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4446         qp_attr->min_rnr_timer      =
4447                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4448         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4449         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4450         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4451         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4452
4453 out:
4454         kfree(outb);
4455         return err;
4456 }
4457
4458 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4459                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4460 {
4461         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4462         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4463         int err = 0;
4464         u8 raw_packet_qp_state;
4465
4466         if (ibqp->rwq_ind_tbl)
4467                 return -ENOSYS;
4468
4469         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4470                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4471                                             qp_init_attr);
4472
4473 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4474         /*
4475          * Wait for any outstanding page faults, in case the user frees memory
4476          * based upon this query's result.
4477          */
4478         flush_workqueue(mlx5_ib_page_fault_wq);
4479 #endif
4480
4481         mutex_lock(&qp->mutex);
4482
4483         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4484                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4485                 if (err)
4486                         goto out;
4487                 qp->state = raw_packet_qp_state;
4488                 qp_attr->port_num = 1;
4489         } else {
4490                 err = query_qp_attr(dev, qp, qp_attr);
4491                 if (err)
4492                         goto out;
4493         }
4494
4495         qp_attr->qp_state            = qp->state;
4496         qp_attr->cur_qp_state        = qp_attr->qp_state;
4497         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4498         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4499
4500         if (!ibqp->uobject) {
4501                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4502                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4503                 qp_init_attr->qp_context = ibqp->qp_context;
4504         } else {
4505                 qp_attr->cap.max_send_wr  = 0;
4506                 qp_attr->cap.max_send_sge = 0;
4507         }
4508
4509         qp_init_attr->qp_type = ibqp->qp_type;
4510         qp_init_attr->recv_cq = ibqp->recv_cq;
4511         qp_init_attr->send_cq = ibqp->send_cq;
4512         qp_init_attr->srq = ibqp->srq;
4513         qp_attr->cap.max_inline_data = qp->max_inline_data;
4514
4515         qp_init_attr->cap            = qp_attr->cap;
4516
4517         qp_init_attr->create_flags = 0;
4518         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4519                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4520
4521         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4522                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4523         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4524                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4525         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4526                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4527         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4528                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4529
4530         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4531                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4532
4533 out:
4534         mutex_unlock(&qp->mutex);
4535         return err;
4536 }
4537
4538 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4539                                           struct ib_ucontext *context,
4540                                           struct ib_udata *udata)
4541 {
4542         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4543         struct mlx5_ib_xrcd *xrcd;
4544         int err;
4545
4546         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4547                 return ERR_PTR(-ENOSYS);
4548
4549         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4550         if (!xrcd)
4551                 return ERR_PTR(-ENOMEM);
4552
4553         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4554         if (err) {
4555                 kfree(xrcd);
4556                 return ERR_PTR(-ENOMEM);
4557         }
4558
4559         return &xrcd->ibxrcd;
4560 }
4561
4562 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4563 {
4564         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4565         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4566         int err;
4567
4568         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4569         if (err) {
4570                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4571                 return err;
4572         }
4573
4574         kfree(xrcd);
4575
4576         return 0;
4577 }
4578
4579 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4580 {
4581         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4582         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4583         struct ib_event event;
4584
4585         if (rwq->ibwq.event_handler) {
4586                 event.device     = rwq->ibwq.device;
4587                 event.element.wq = &rwq->ibwq;
4588                 switch (type) {
4589                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4590                         event.event = IB_EVENT_WQ_FATAL;
4591                         break;
4592                 default:
4593                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4594                         return;
4595                 }
4596
4597                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4598         }
4599 }
4600
4601 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4602                       struct ib_wq_init_attr *init_attr)
4603 {
4604         struct mlx5_ib_dev *dev;
4605         __be64 *rq_pas0;
4606         void *in;
4607         void *rqc;
4608         void *wq;
4609         int inlen;
4610         int err;
4611
4612         dev = to_mdev(pd->device);
4613
4614         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4615         in = mlx5_vzalloc(inlen);
4616         if (!in)
4617                 return -ENOMEM;
4618
4619         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4620         MLX5_SET(rqc,  rqc, mem_rq_type,
4621                  MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
4622         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4623         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4624         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4625         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4626         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4627         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4628         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4629         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4630         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4631         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4632         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4633         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4634         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4635         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4636         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4637         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4638         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4639         kvfree(in);
4640         return err;
4641 }
4642
4643 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4644                             struct ib_wq_init_attr *wq_init_attr,
4645                             struct mlx5_ib_create_wq *ucmd,
4646                             struct mlx5_ib_rwq *rwq)
4647 {
4648         /* Sanity check RQ size before proceeding */
4649         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4650                 return -EINVAL;
4651
4652         if (!ucmd->rq_wqe_count)
4653                 return -EINVAL;
4654
4655         rwq->wqe_count = ucmd->rq_wqe_count;
4656         rwq->wqe_shift = ucmd->rq_wqe_shift;
4657         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4658         rwq->log_rq_stride = rwq->wqe_shift;
4659         rwq->log_rq_size = ilog2(rwq->wqe_count);
4660         return 0;
4661 }
4662
4663 static int prepare_user_rq(struct ib_pd *pd,
4664                            struct ib_wq_init_attr *init_attr,
4665                            struct ib_udata *udata,
4666                            struct mlx5_ib_rwq *rwq)
4667 {
4668         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4669         struct mlx5_ib_create_wq ucmd = {};
4670         int err;
4671         size_t required_cmd_sz;
4672
4673         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4674         if (udata->inlen < required_cmd_sz) {
4675                 mlx5_ib_dbg(dev, "invalid inlen\n");
4676                 return -EINVAL;
4677         }
4678
4679         if (udata->inlen > sizeof(ucmd) &&
4680             !ib_is_udata_cleared(udata, sizeof(ucmd),
4681                                  udata->inlen - sizeof(ucmd))) {
4682                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4683                 return -EOPNOTSUPP;
4684         }
4685
4686         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4687                 mlx5_ib_dbg(dev, "copy failed\n");
4688                 return -EFAULT;
4689         }
4690
4691         if (ucmd.comp_mask) {
4692                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4693                 return -EOPNOTSUPP;
4694         }
4695
4696         if (ucmd.reserved) {
4697                 mlx5_ib_dbg(dev, "invalid reserved\n");
4698                 return -EOPNOTSUPP;
4699         }
4700
4701         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4702         if (err) {
4703                 mlx5_ib_dbg(dev, "err %d\n", err);
4704                 return err;
4705         }
4706
4707         err = create_user_rq(dev, pd, rwq, &ucmd);
4708         if (err) {
4709                 mlx5_ib_dbg(dev, "err %d\n", err);
4710                 if (err)
4711                         return err;
4712         }
4713
4714         rwq->user_index = ucmd.user_index;
4715         return 0;
4716 }
4717
4718 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4719                                 struct ib_wq_init_attr *init_attr,
4720                                 struct ib_udata *udata)
4721 {
4722         struct mlx5_ib_dev *dev;
4723         struct mlx5_ib_rwq *rwq;
4724         struct mlx5_ib_create_wq_resp resp = {};
4725         size_t min_resp_len;
4726         int err;
4727
4728         if (!udata)
4729                 return ERR_PTR(-ENOSYS);
4730
4731         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4732         if (udata->outlen && udata->outlen < min_resp_len)
4733                 return ERR_PTR(-EINVAL);
4734
4735         dev = to_mdev(pd->device);
4736         switch (init_attr->wq_type) {
4737         case IB_WQT_RQ:
4738                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4739                 if (!rwq)
4740                         return ERR_PTR(-ENOMEM);
4741                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4742                 if (err)
4743                         goto err;
4744                 err = create_rq(rwq, pd, init_attr);
4745                 if (err)
4746                         goto err_user_rq;
4747                 break;
4748         default:
4749                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4750                             init_attr->wq_type);
4751                 return ERR_PTR(-EINVAL);
4752         }
4753
4754         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4755         rwq->ibwq.state = IB_WQS_RESET;
4756         if (udata->outlen) {
4757                 resp.response_length = offsetof(typeof(resp), response_length) +
4758                                 sizeof(resp.response_length);
4759                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4760                 if (err)
4761                         goto err_copy;
4762         }
4763
4764         rwq->core_qp.event = mlx5_ib_wq_event;
4765         rwq->ibwq.event_handler = init_attr->event_handler;
4766         return &rwq->ibwq;
4767
4768 err_copy:
4769         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4770 err_user_rq:
4771         destroy_user_rq(pd, rwq);
4772 err:
4773         kfree(rwq);
4774         return ERR_PTR(err);
4775 }
4776
4777 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4778 {
4779         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4780         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4781
4782         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4783         destroy_user_rq(wq->pd, rwq);
4784         kfree(rwq);
4785
4786         return 0;
4787 }
4788
4789 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4790                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4791                                                       struct ib_udata *udata)
4792 {
4793         struct mlx5_ib_dev *dev = to_mdev(device);
4794         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4795         int sz = 1 << init_attr->log_ind_tbl_size;
4796         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4797         size_t min_resp_len;
4798         int inlen;
4799         int err;
4800         int i;
4801         u32 *in;
4802         void *rqtc;
4803
4804         if (udata->inlen > 0 &&
4805             !ib_is_udata_cleared(udata, 0,
4806                                  udata->inlen))
4807                 return ERR_PTR(-EOPNOTSUPP);
4808
4809         if (init_attr->log_ind_tbl_size >
4810             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4811                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4812                             init_attr->log_ind_tbl_size,
4813                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4814                 return ERR_PTR(-EINVAL);
4815         }
4816
4817         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4818         if (udata->outlen && udata->outlen < min_resp_len)
4819                 return ERR_PTR(-EINVAL);
4820
4821         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4822         if (!rwq_ind_tbl)
4823                 return ERR_PTR(-ENOMEM);
4824
4825         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4826         in = mlx5_vzalloc(inlen);
4827         if (!in) {
4828                 err = -ENOMEM;
4829                 goto err;
4830         }
4831
4832         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4833
4834         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4835         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4836
4837         for (i = 0; i < sz; i++)
4838                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4839
4840         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4841         kvfree(in);
4842
4843         if (err)
4844                 goto err;
4845
4846         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4847         if (udata->outlen) {
4848                 resp.response_length = offsetof(typeof(resp), response_length) +
4849                                         sizeof(resp.response_length);
4850                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4851                 if (err)
4852                         goto err_copy;
4853         }
4854
4855         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4856
4857 err_copy:
4858         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4859 err:
4860         kfree(rwq_ind_tbl);
4861         return ERR_PTR(err);
4862 }
4863
4864 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4865 {
4866         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4867         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4868
4869         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4870
4871         kfree(rwq_ind_tbl);
4872         return 0;
4873 }
4874
4875 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4876                       u32 wq_attr_mask, struct ib_udata *udata)
4877 {
4878         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4879         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4880         struct mlx5_ib_modify_wq ucmd = {};
4881         size_t required_cmd_sz;
4882         int curr_wq_state;
4883         int wq_state;
4884         int inlen;
4885         int err;
4886         void *rqc;
4887         void *in;
4888
4889         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4890         if (udata->inlen < required_cmd_sz)
4891                 return -EINVAL;
4892
4893         if (udata->inlen > sizeof(ucmd) &&
4894             !ib_is_udata_cleared(udata, sizeof(ucmd),
4895                                  udata->inlen - sizeof(ucmd)))
4896                 return -EOPNOTSUPP;
4897
4898         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4899                 return -EFAULT;
4900
4901         if (ucmd.comp_mask || ucmd.reserved)
4902                 return -EOPNOTSUPP;
4903
4904         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4905         in = mlx5_vzalloc(inlen);
4906         if (!in)
4907                 return -ENOMEM;
4908
4909         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4910
4911         MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn);
4912         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4913                 wq_attr->curr_wq_state : wq->state;
4914         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4915                 wq_attr->wq_state : curr_wq_state;
4916         if (curr_wq_state == IB_WQS_ERR)
4917                 curr_wq_state = MLX5_RQC_STATE_ERR;
4918         if (wq_state == IB_WQS_ERR)
4919                 wq_state = MLX5_RQC_STATE_ERR;
4920         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4921         MLX5_SET(rqc, rqc, state, wq_state);
4922
4923         err = mlx5_core_modify_rq(dev->mdev, in, inlen);
4924         kvfree(in);
4925         if (!err)
4926                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4927
4928         return err;
4929 }