sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
  32
  33 enum {
  34         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  35         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  36         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  37         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  38         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  39         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  40         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  41         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  42         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  43         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  44         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  45         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  46         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  47         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  48         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  49         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  50         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  51         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  52         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  53         MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
  54         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  56         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  57         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  58         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  59         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  60         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  61         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  62         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  63         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
  64         MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
  65         MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
  66         MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT                   = 0x27,
  67 };
  68
  69 enum {
  70         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  71         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  72         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  73         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  74         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  75 };
  76
  77 enum {
  78         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  79 };
  80
  81 enum {
  82         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  83         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  84 };
  85
  86 enum {
  87         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  88         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  89         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  90         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  91         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  92         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  93         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  94         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  95         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  96         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  97         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  98         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  99         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
 100         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 107         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 108         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 109         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 110         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 111         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 112         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 113         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 114         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 115         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 116         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 117         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 118         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 119         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 120         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 121         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 122         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 123         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 124         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 125         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 126         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 127         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 128         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 129         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 130         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 131         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 132         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 133         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 134         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 135         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 136         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 137         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 138         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 139         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 140         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 141         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 142         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 143         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 144         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 145         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 146         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 147         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 148         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 149         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 150         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 151         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 152         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 153         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 154         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 155         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 156         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 157         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 158         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 159         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 160         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 161         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 162         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 163         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 164         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 165         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 166         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 167         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 168         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 169         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 170         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 171         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 172         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 173         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 174         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 175         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 176         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 177         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 178         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 179         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 180         MLX5_CMD_OP_NOP                           = 0x80d,
 181         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 182         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 183         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 184         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 185         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 186         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 190         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 191         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 192         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 193         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 194         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 195         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 196         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 197         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 198         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 199         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 200         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 201         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 202         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 203         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 204         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 205         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 206         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 207         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 208         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 209         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 210         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 211         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 212         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 213         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 214         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 215         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 216         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 217         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 218         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 219         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 220         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 221         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 222         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 223         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 224         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 225         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 226         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 227         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 228         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 229         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 230         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 231         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 232         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 233         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 234         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 235         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 236         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 237         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 238         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 239         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 240         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 241         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 242         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 243         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 244         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 245         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 246         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 247         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 248         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 249         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 250         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
 260
 261 };
 262
 263 enum {
 264         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 265         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 266         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 267         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 268         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 269         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 270         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 271         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 272         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 273         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 274         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 275         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 276 };
 277
 278 enum {
 279         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
 280 };
 281
 282 enum {
 283         MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
 284 };
 285
 286 enum {
 287         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
 288         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
 289 };
 290
 291 enum {
 292         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
 293 };
 294
 295 struct mlx5_ifc_flow_table_fields_supported_bits {
 296         u8         outer_dmac[0x1];
 297         u8         outer_smac[0x1];
 298         u8         outer_ether_type[0x1];
 299         u8         reserved_0[0x1];
 300         u8         outer_first_prio[0x1];
 301         u8         outer_first_cfi[0x1];
 302         u8         outer_first_vid[0x1];
 303         u8         reserved_1[0x1];
 304         u8         outer_second_prio[0x1];
 305         u8         outer_second_cfi[0x1];
 306         u8         outer_second_vid[0x1];
 307         u8         outer_ipv6_flow_label[0x1];
 308         u8         outer_sip[0x1];
 309         u8         outer_dip[0x1];
 310         u8         outer_frag[0x1];
 311         u8         outer_ip_protocol[0x1];
 312         u8         outer_ip_ecn[0x1];
 313         u8         outer_ip_dscp[0x1];
 314         u8         outer_udp_sport[0x1];
 315         u8         outer_udp_dport[0x1];
 316         u8         outer_tcp_sport[0x1];
 317         u8         outer_tcp_dport[0x1];
 318         u8         outer_tcp_flags[0x1];
 319         u8         outer_gre_protocol[0x1];
 320         u8         outer_gre_key[0x1];
 321         u8         outer_vxlan_vni[0x1];
 322         u8         outer_geneve_vni[0x1];
 323         u8         outer_geneve_oam[0x1];
 324         u8         outer_geneve_protocol_type[0x1];
 325         u8         outer_geneve_opt_len[0x1];
 326         u8         reserved_2[0x1];
 327         u8         source_eswitch_port[0x1];
 328
 329         u8         inner_dmac[0x1];
 330         u8         inner_smac[0x1];
 331         u8         inner_ether_type[0x1];
 332         u8         reserved_3[0x1];
 333         u8         inner_first_prio[0x1];
 334         u8         inner_first_cfi[0x1];
 335         u8         inner_first_vid[0x1];
 336         u8         reserved_4[0x1];
 337         u8         inner_second_prio[0x1];
 338         u8         inner_second_cfi[0x1];
 339         u8         inner_second_vid[0x1];
 340         u8         inner_ipv6_flow_label[0x1];
 341         u8         inner_sip[0x1];
 342         u8         inner_dip[0x1];
 343         u8         inner_frag[0x1];
 344         u8         inner_ip_protocol[0x1];
 345         u8         inner_ip_ecn[0x1];
 346         u8         inner_ip_dscp[0x1];
 347         u8         inner_udp_sport[0x1];
 348         u8         inner_udp_dport[0x1];
 349         u8         inner_tcp_sport[0x1];
 350         u8         inner_tcp_dport[0x1];
 351         u8         inner_tcp_flags[0x1];
 352         u8         reserved_5[0x9];
 353
 354         u8         reserved_6[0x1a];
 355         u8         bth_dst_qp[0x1];
 356         u8         reserved_7[0x4];
 357         u8         source_sqn[0x1];
 358
 359         u8         reserved_8[0x20];
 360 };
 361
 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 363         u8         ingress_general_high[0x20];
 364
 365         u8         ingress_general_low[0x20];
 366
 367         u8         ingress_policy_engine_high[0x20];
 368
 369         u8         ingress_policy_engine_low[0x20];
 370
 371         u8         ingress_vlan_membership_high[0x20];
 372
 373         u8         ingress_vlan_membership_low[0x20];
 374
 375         u8         ingress_tag_frame_type_high[0x20];
 376
 377         u8         ingress_tag_frame_type_low[0x20];
 378
 379         u8         egress_vlan_membership_high[0x20];
 380
 381         u8         egress_vlan_membership_low[0x20];
 382
 383         u8         loopback_filter_high[0x20];
 384
 385         u8         loopback_filter_low[0x20];
 386
 387         u8         egress_general_high[0x20];
 388
 389         u8         egress_general_low[0x20];
 390
 391         u8         reserved_at_1c0[0x40];
 392
 393         u8         egress_hoq_high[0x20];
 394
 395         u8         egress_hoq_low[0x20];
 396
 397         u8         port_isolation_high[0x20];
 398
 399         u8         port_isolation_low[0x20];
 400
 401         u8         egress_policy_engine_high[0x20];
 402
 403         u8         egress_policy_engine_low[0x20];
 404
 405         u8         ingress_tx_link_down_high[0x20];
 406
 407         u8         ingress_tx_link_down_low[0x20];
 408
 409         u8         egress_stp_filter_high[0x20];
 410
 411         u8         egress_stp_filter_low[0x20];
 412
 413         u8         egress_hoq_stall_high[0x20];
 414
 415         u8         egress_hoq_stall_low[0x20];
 416
 417         u8         reserved_at_340[0x440];
 418 };
 419 struct mlx5_ifc_flow_table_prop_layout_bits {
 420         u8         ft_support[0x1];
 421         u8         flow_tag[0x1];
 422         u8         flow_counter[0x1];
 423         u8         flow_modify_en[0x1];
 424         u8         modify_root[0x1];
 425         u8         identified_miss_table[0x1];
 426         u8         flow_table_modify[0x1];
 427         u8         encap[0x1];
 428         u8         decap[0x1];
 429         u8         reset_root_to_default[0x1];
 430         u8         reserved_at_a[0x16];
 431
 432         u8         reserved_at_20[0x2];
 433         u8         log_max_ft_size[0x6];
 434         u8         reserved_at_28[0x10];
 435         u8         max_ft_level[0x8];
 436
 437         u8         reserved_at_40[0x20];
 438
 439         u8         reserved_at_60[0x18];
 440         u8         log_max_ft_num[0x8];
 441
 442         u8         reserved_at_80[0x10];
 443         u8         log_max_flow_counter[0x8];
 444         u8         log_max_destination[0x8];
 445
 446         u8         reserved_at_a0[0x18];
 447         u8         log_max_flow[0x8];
 448
 449         u8         reserved_at_c0[0x40];
 450
 451         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 452
 453         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 454 };
 455
 456 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 457         u8         send[0x1];
 458         u8         receive[0x1];
 459         u8         write[0x1];
 460         u8         read[0x1];
 461         u8         atomic[0x1];
 462         u8         srq_receive[0x1];
 463         u8         reserved_0[0x1a];
 464 };
 465
 466 struct mlx5_ifc_flow_counter_list_bits {
 467         u8         reserved_0[0x10];
 468         u8         flow_counter_id[0x10];
 469
 470         u8         reserved_1[0x20];
 471 };
 472
 473 enum {
 474         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 475         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 476         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 477         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 478 };
 479
 480 struct mlx5_ifc_dest_format_struct_bits {
 481         u8         destination_type[0x8];
 482         u8         destination_id[0x18];
 483
 484         u8         reserved_0[0x20];
 485 };
 486
 487 struct mlx5_ifc_ipv4_layout_bits {
 488         u8         reserved_at_0[0x60];
 489
 490         u8         ipv4[0x20];
 491 };
 492
 493 struct mlx5_ifc_ipv6_layout_bits {
 494         u8         ipv6[16][0x8];
 495 };
 496
 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 498         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 499         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 500         u8         reserved_at_0[0x80];
 501 };
 502
 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 504         u8         smac_47_16[0x20];
 505
 506         u8         smac_15_0[0x10];
 507         u8         ethertype[0x10];
 508
 509         u8         dmac_47_16[0x20];
 510
 511         u8         dmac_15_0[0x10];
 512         u8         first_prio[0x3];
 513         u8         first_cfi[0x1];
 514         u8         first_vid[0xc];
 515
 516         u8         ip_protocol[0x8];
 517         u8         ip_dscp[0x6];
 518         u8         ip_ecn[0x2];
 519         u8         cvlan_tag[0x1];
 520         u8         svlan_tag[0x1];
 521         u8         frag[0x1];
 522         u8         reserved_1[0x4];
 523         u8         tcp_flags[0x9];
 524
 525         u8         tcp_sport[0x10];
 526         u8         tcp_dport[0x10];
 527
 528         u8         reserved_2[0x20];
 529
 530         u8         udp_sport[0x10];
 531         u8         udp_dport[0x10];
 532
 533         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 534
 535         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 536 };
 537
 538 struct mlx5_ifc_fte_match_set_misc_bits {
 539         u8         reserved_0[0x8];
 540         u8         source_sqn[0x18];
 541
 542         u8         reserved_1[0x10];
 543         u8         source_port[0x10];
 544
 545         u8         outer_second_prio[0x3];
 546         u8         outer_second_cfi[0x1];
 547         u8         outer_second_vid[0xc];
 548         u8         inner_second_prio[0x3];
 549         u8         inner_second_cfi[0x1];
 550         u8         inner_second_vid[0xc];
 551
 552         u8         outer_second_vlan_tag[0x1];
 553         u8         inner_second_vlan_tag[0x1];
 554         u8         reserved_2[0xe];
 555         u8         gre_protocol[0x10];
 556
 557         u8         gre_key_h[0x18];
 558         u8         gre_key_l[0x8];
 559
 560         u8         vxlan_vni[0x18];
 561         u8         reserved_3[0x8];
 562
 563         u8         geneve_vni[0x18];
 564         u8         reserved4[0x7];
 565         u8         geneve_oam[0x1];
 566
 567         u8         reserved_5[0xc];
 568         u8         outer_ipv6_flow_label[0x14];
 569
 570         u8         reserved_6[0xc];
 571         u8         inner_ipv6_flow_label[0x14];
 572
 573         u8         reserved_7[0xa];
 574         u8         geneve_opt_len[0x6];
 575         u8         geneve_protocol_type[0x10];
 576
 577         u8         reserved_8[0x8];
 578         u8         bth_dst_qp[0x18];
 579
 580         u8         reserved_9[0xa0];
 581 };
 582
 583 struct mlx5_ifc_cmd_pas_bits {
 584         u8         pa_h[0x20];
 585
 586         u8         pa_l[0x14];
 587         u8         reserved_0[0xc];
 588 };
 589
 590 struct mlx5_ifc_uint64_bits {
 591         u8         hi[0x20];
 592
 593         u8         lo[0x20];
 594 };
 595
 596 struct mlx5_ifc_application_prio_entry_bits {
 597         u8         reserved_0[0x8];
 598         u8         priority[0x3];
 599         u8         reserved_1[0x2];
 600         u8         sel[0x3];
 601         u8         protocol_id[0x10];
 602 };
 603
 604 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 605         u8         reserved_0[0x8];
 606         u8         ring_pi[0x10];
 607         u8         reserved_1[0x8];
 608 };
 609
 610 enum {
 611         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 612         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 613         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 614         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 615         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 616         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 617         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 618         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 619         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 620         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 621 };
 622
 623 struct mlx5_ifc_ads_bits {
 624         u8         fl[0x1];
 625         u8         free_ar[0x1];
 626         u8         reserved_0[0xe];
 627         u8         pkey_index[0x10];
 628
 629         u8         reserved_1[0x8];
 630         u8         grh[0x1];
 631         u8         mlid[0x7];
 632         u8         rlid[0x10];
 633
 634         u8         ack_timeout[0x5];
 635         u8         reserved_2[0x3];
 636         u8         src_addr_index[0x8];
 637         u8         log_rtm[0x4];
 638         u8         stat_rate[0x4];
 639         u8         hop_limit[0x8];
 640
 641         u8         reserved_3[0x4];
 642         u8         tclass[0x8];
 643         u8         flow_label[0x14];
 644
 645         u8         rgid_rip[16][0x8];
 646
 647         u8         reserved_4[0x4];
 648         u8         f_dscp[0x1];
 649         u8         f_ecn[0x1];
 650         u8         reserved_5[0x1];
 651         u8         f_eth_prio[0x1];
 652         u8         ecn[0x2];
 653         u8         dscp[0x6];
 654         u8         udp_sport[0x10];
 655
 656         u8         dei_cfi[0x1];
 657         u8         eth_prio[0x3];
 658         u8         sl[0x4];
 659         u8         port[0x8];
 660         u8         rmac_47_32[0x10];
 661
 662         u8         rmac_31_0[0x20];
 663 };
 664
 665 struct mlx5_ifc_diagnostic_counter_cap_bits {
 666         u8         sync[0x1];
 667         u8         reserved_0[0xf];
 668         u8         counter_id[0x10];
 669 };
 670
 671 struct mlx5_ifc_debug_cap_bits {
 672         u8         reserved_0[0x18];
 673         u8         log_max_samples[0x8];
 674
 675         u8         single[0x1];
 676         u8         repetitive[0x1];
 677         u8         health_mon_rx_activity[0x1];
 678         u8         reserved_1[0x15];
 679         u8         log_min_sample_period[0x8];
 680
 681         u8         reserved_2[0x1c0];
 682
 683         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 684 };
 685
 686 struct mlx5_ifc_qos_cap_bits {
 687         u8         packet_pacing[0x1];
 688         u8         esw_scheduling[0x1];
 689         u8         esw_bw_share[0x1];
 690         u8         esw_rate_limit[0x1];
 691         u8         hll[0x1];
 692         u8         packet_pacing_burst_bound[0x1];
 693         u8         packet_pacing_typical_size[0x1];
 694         u8         reserved_at_7[0x19];
 695
 696         u8         reserved_at_20[0x20];
 697
 698         u8         packet_pacing_max_rate[0x20];
 699
 700         u8         packet_pacing_min_rate[0x20];
 701
 702         u8         reserved_at_80[0x10];
 703         u8         packet_pacing_rate_table_size[0x10];
 704
 705         u8         esw_element_type[0x10];
 706         u8         esw_tsar_type[0x10];
 707
 708         u8         reserved_at_c0[0x10];
 709         u8         max_qos_para_vport[0x10];
 710
 711         u8         max_tsar_bw_share[0x20];
 712
 713         u8         reserved_at_100[0x700];
 714 };
 715
 716 struct mlx5_ifc_snapshot_cap_bits {
 717         u8         reserved_0[0x1d];
 718         u8         suspend_qp_uc[0x1];
 719         u8         suspend_qp_ud[0x1];
 720         u8         suspend_qp_rc[0x1];
 721
 722         u8         reserved_1[0x1c];
 723         u8         restore_pd[0x1];
 724         u8         restore_uar[0x1];
 725         u8         restore_mkey[0x1];
 726         u8         restore_qp[0x1];
 727
 728         u8         reserved_2[0x1e];
 729         u8         named_mkey[0x1];
 730         u8         named_qp[0x1];
 731
 732         u8         reserved_3[0x7a0];
 733 };
 734
 735 struct mlx5_ifc_e_switch_cap_bits {
 736         u8         vport_svlan_strip[0x1];
 737         u8         vport_cvlan_strip[0x1];
 738         u8         vport_svlan_insert[0x1];
 739         u8         vport_cvlan_insert_if_not_exist[0x1];
 740         u8         vport_cvlan_insert_overwrite[0x1];
 741
 742         u8         reserved_0[0x19];
 743
 744         u8         nic_vport_node_guid_modify[0x1];
 745         u8         nic_vport_port_guid_modify[0x1];
 746
 747         u8         reserved_1[0x7e0];
 748 };
 749
 750 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 751         u8         reserved_0[0x200];
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 754
 755         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 756
 757         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 758
 759         u8         reserved_1[0x7800];
 760 };
 761
 762 struct mlx5_ifc_flow_table_nic_cap_bits {
 763         u8         nic_rx_multi_path_tirs[0x1];
 764         u8         nic_rx_multi_path_tirs_fts[0x1];
 765         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 766         u8         reserved_at_3[0x1fd];
 767
 768         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 769
 770         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 771
 772         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 773
 774         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 775
 776         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 777
 778         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 779
 780         u8         reserved_1[0x7200];
 781 };
 782
 783 struct mlx5_ifc_pddr_module_info_bits {
 784         u8         cable_technology[0x8];
 785         u8         cable_breakout[0x8];
 786         u8         ext_ethernet_compliance_code[0x8];
 787         u8         ethernet_compliance_code[0x8];
 788
 789         u8         cable_type[0x4];
 790         u8         cable_vendor[0x4];
 791         u8         cable_length[0x8];
 792         u8         cable_identifier[0x8];
 793         u8         cable_power_class[0x8];
 794
 795         u8         reserved_at_40[0x8];
 796         u8         cable_rx_amp[0x8];
 797         u8         cable_rx_emphasis[0x8];
 798         u8         cable_tx_equalization[0x8];
 799
 800         u8         reserved_at_60[0x8];
 801         u8         cable_attenuation_12g[0x8];
 802         u8         cable_attenuation_7g[0x8];
 803         u8         cable_attenuation_5g[0x8];
 804
 805         u8         reserved_at_80[0x8];
 806         u8         rx_cdr_cap[0x4];
 807         u8         tx_cdr_cap[0x4];
 808         u8         reserved_at_90[0x4];
 809         u8         rx_cdr_state[0x4];
 810         u8         reserved_at_98[0x4];
 811         u8         tx_cdr_state[0x4];
 812
 813         u8         vendor_name[16][0x8];
 814
 815         u8         vendor_pn[16][0x8];
 816
 817         u8         vendor_rev[0x20];
 818
 819         u8         fw_version[0x20];
 820
 821         u8         vendor_sn[16][0x8];
 822
 823         u8         temperature[0x10];
 824         u8         voltage[0x10];
 825
 826         u8         rx_power_lane0[0x10];
 827         u8         rx_power_lane1[0x10];
 828
 829         u8         rx_power_lane2[0x10];
 830         u8         rx_power_lane3[0x10];
 831
 832         u8         reserved_at_2c0[0x40];
 833
 834         u8         tx_power_lane0[0x10];
 835         u8         tx_power_lane1[0x10];
 836
 837         u8         tx_power_lane2[0x10];
 838         u8         tx_power_lane3[0x10];
 839
 840         u8         reserved_at_340[0x40];
 841
 842         u8         tx_bias_lane0[0x10];
 843         u8         tx_bias_lane1[0x10];
 844
 845         u8         tx_bias_lane2[0x10];
 846         u8         tx_bias_lane3[0x10];
 847
 848         u8         reserved_at_3c0[0x40];
 849
 850         u8         temperature_high_th[0x10];
 851         u8         temperature_low_th[0x10];
 852
 853         u8         voltage_high_th[0x10];
 854         u8         voltage_low_th[0x10];
 855
 856         u8         rx_power_high_th[0x10];
 857         u8         rx_power_low_th[0x10];
 858
 859         u8         tx_power_high_th[0x10];
 860         u8         tx_power_low_th[0x10];
 861
 862         u8         tx_bias_high_th[0x10];
 863         u8         tx_bias_low_th[0x10];
 864
 865         u8         reserved_at_4a0[0x10];
 866         u8         wavelength[0x10];
 867
 868         u8         reserved_at_4c0[0x300];
 869 };
 870
 871 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 872         u8         csum_cap[0x1];
 873         u8         vlan_cap[0x1];
 874         u8         lro_cap[0x1];
 875         u8         lro_psh_flag[0x1];
 876         u8         lro_time_stamp[0x1];
 877         u8         lro_max_msg_sz_mode[0x2];
 878         u8         wqe_vlan_insert[0x1];
 879         u8         self_lb_en_modifiable[0x1];
 880         u8         self_lb_mc[0x1];
 881         u8         self_lb_uc[0x1];
 882         u8         max_lso_cap[0x5];
 883         u8         multi_pkt_send_wqe[0x2];
 884         u8         wqe_inline_mode[0x2];
 885         u8         rss_ind_tbl_cap[0x4];
 886         u8         scatter_fcs[0x1];
 887         u8         reserved_1[0x2];
 888         u8         tunnel_lso_const_out_ip_id[0x1];
 889         u8         tunnel_lro_gre[0x1];
 890         u8         tunnel_lro_vxlan[0x1];
 891         u8         tunnel_statless_gre[0x1];
 892         u8         tunnel_stateless_vxlan[0x1];
 893
 894         u8         swp[0x1];
 895         u8         swp_csum[0x1];
 896         u8         swp_lso[0x1];
 897         u8         reserved_2[0x1b];
 898         u8         max_geneve_opt_len[0x1];
 899         u8         tunnel_stateless_geneve_rx[0x1];
 900
 901         u8         reserved_3[0x10];
 902         u8         lro_min_mss_size[0x10];
 903
 904         u8         reserved_4[0x120];
 905
 906         u8         lro_timer_supported_periods[4][0x20];
 907
 908         u8         reserved_5[0x600];
 909 };
 910
 911 enum {
 912         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 913         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 914         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 915 };
 916
 917 struct mlx5_ifc_roce_cap_bits {
 918         u8         roce_apm[0x1];
 919         u8         rts2rts_primary_eth_prio[0x1];
 920         u8         roce_rx_allow_untagged[0x1];
 921         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 922
 923         u8         reserved_0[0x1c];
 924
 925         u8         reserved_1[0x60];
 926
 927         u8         reserved_2[0xc];
 928         u8         l3_type[0x4];
 929         u8         reserved_3[0x8];
 930         u8         roce_version[0x8];
 931
 932         u8         reserved_4[0x10];
 933         u8         r_roce_dest_udp_port[0x10];
 934
 935         u8         r_roce_max_src_udp_port[0x10];
 936         u8         r_roce_min_src_udp_port[0x10];
 937
 938         u8         reserved_5[0x10];
 939         u8         roce_address_table_size[0x10];
 940
 941         u8         reserved_6[0x700];
 942 };
 943
 944 enum {
 945         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 946         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 947         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 948         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 949         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 950         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 951         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 952         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 953         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 954 };
 955
 956 enum {
 957         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 958         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 959         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 960         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 961         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 962         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 963         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 964         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 965         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 966 };
 967
 968 struct mlx5_ifc_atomic_caps_bits {
 969         u8         reserved_0[0x40];
 970
 971         u8         atomic_req_8B_endianess_mode[0x2];
 972         u8         reserved_1[0x4];
 973         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 974
 975         u8         reserved_2[0x19];
 976
 977         u8         reserved_3[0x20];
 978
 979         u8         reserved_4[0x10];
 980         u8         atomic_operations[0x10];
 981
 982         u8         reserved_5[0x10];
 983         u8         atomic_size_qp[0x10];
 984
 985         u8         reserved_6[0x10];
 986         u8         atomic_size_dc[0x10];
 987
 988         u8         reserved_7[0x720];
 989 };
 990
 991 struct mlx5_ifc_odp_cap_bits {
 992         u8         reserved_0[0x40];
 993
 994         u8         sig[0x1];
 995         u8         reserved_1[0x1f];
 996
 997         u8         reserved_2[0x20];
 998
 999         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1000
1001         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1002
1003         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1004
1005         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1006
1007         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1008
1009         u8         reserved_3[0x6e0];
1010 };
1011
1012 enum {
1013         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1014         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1015         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1016         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1017         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1018 };
1019
1020 enum {
1021         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1022         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1023         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1024         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1025         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1026         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1027 };
1028
1029 enum {
1030         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1031         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1032 };
1033
1034 enum {
1035         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1036         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1037         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1038 };
1039
1040 struct mlx5_ifc_cmd_hca_cap_bits {
1041         u8         reserved_0[0x80];
1042
1043         u8         log_max_srq_sz[0x8];
1044         u8         log_max_qp_sz[0x8];
1045         u8         reserved_1[0xb];
1046         u8         log_max_qp[0x5];
1047
1048         u8         reserved_2[0xb];
1049         u8         log_max_srq[0x5];
1050         u8         reserved_3[0x10];
1051
1052         u8         reserved_4[0x8];
1053         u8         log_max_cq_sz[0x8];
1054         u8         reserved_5[0xb];
1055         u8         log_max_cq[0x5];
1056
1057         u8         log_max_eq_sz[0x8];
1058         u8         relaxed_ordering_write[1];
1059         u8         reserved_6[0x1];
1060         u8         log_max_mkey[0x6];
1061         u8         reserved_7[0xb];
1062         u8         fast_teardown[0x1];
1063         u8         log_max_eq[0x4];
1064
1065         u8         max_indirection[0x8];
1066         u8         reserved_8[0x1];
1067         u8         log_max_mrw_sz[0x7];
1068         u8         force_teardown[0x1];
1069         u8         reserved_9[0x1];
1070         u8         log_max_bsf_list_size[0x6];
1071         u8         reserved_10[0x2];
1072         u8         log_max_klm_list_size[0x6];
1073
1074         u8         reserved_11[0xa];
1075         u8         log_max_ra_req_dc[0x6];
1076         u8         reserved_12[0xa];
1077         u8         log_max_ra_res_dc[0x6];
1078
1079         u8         reserved_13[0xa];
1080         u8         log_max_ra_req_qp[0x6];
1081         u8         reserved_14[0xa];
1082         u8         log_max_ra_res_qp[0x6];
1083
1084         u8         pad_cap[0x1];
1085         u8         cc_query_allowed[0x1];
1086         u8         cc_modify_allowed[0x1];
1087         u8         start_pad[0x1];
1088         u8         cache_line_128byte[0x1];
1089         u8         reserved_at_165[0xa];
1090         u8         qcam_reg[0x1];
1091         u8         gid_table_size[0x10];
1092
1093         u8         out_of_seq_cnt[0x1];
1094         u8         vport_counters[0x1];
1095         u8         retransmission_q_counters[0x1];
1096         u8         debug[0x1];
1097         u8         modify_rq_counters_set_id[0x1];
1098         u8         rq_delay_drop[0x1];
1099         u8         max_qp_cnt[0xa];
1100         u8         pkey_table_size[0x10];
1101
1102         u8         vport_group_manager[0x1];
1103         u8         vhca_group_manager[0x1];
1104         u8         ib_virt[0x1];
1105         u8         eth_virt[0x1];
1106         u8         reserved_17[0x1];
1107         u8         ets[0x1];
1108         u8         nic_flow_table[0x1];
1109         u8         eswitch_flow_table[0x1];
1110         u8         reserved_18[0x1];
1111         u8         mcam_reg[0x1];
1112         u8         pcam_reg[0x1];
1113         u8         local_ca_ack_delay[0x5];
1114         u8         port_module_event[0x1];
1115         u8         reserved_19[0x5];
1116         u8         port_type[0x2];
1117         u8         num_ports[0x8];
1118
1119         u8         snapshot[0x1];
1120         u8         reserved_20[0x2];
1121         u8         log_max_msg[0x5];
1122         u8         reserved_21[0x4];
1123         u8         max_tc[0x4];
1124         u8         temp_warn_event[0x1];
1125         u8         dcbx[0x1];
1126         u8         general_notification_event[0x1];
1127         u8         reserved_at_1d3[0x2];
1128         u8         fpga[0x1];
1129         u8         rol_s[0x1];
1130         u8         rol_g[0x1];
1131         u8         reserved_23[0x1];
1132         u8         wol_s[0x1];
1133         u8         wol_g[0x1];
1134         u8         wol_a[0x1];
1135         u8         wol_b[0x1];
1136         u8         wol_m[0x1];
1137         u8         wol_u[0x1];
1138         u8         wol_p[0x1];
1139
1140         u8         stat_rate_support[0x10];
1141         u8         reserved_24[0xc];
1142         u8         cqe_version[0x4];
1143
1144         u8         compact_address_vector[0x1];
1145         u8         striding_rq[0x1];
1146         u8         reserved_25[0x1];
1147         u8         ipoib_enhanced_offloads[0x1];
1148         u8         ipoib_ipoib_offloads[0x1];
1149         u8         reserved_26[0x8];
1150         u8         dc_connect_qp[0x1];
1151         u8         dc_cnak_trace[0x1];
1152         u8         drain_sigerr[0x1];
1153         u8         cmdif_checksum[0x2];
1154         u8         sigerr_cqe[0x1];
1155         u8         reserved_27[0x1];
1156         u8         wq_signature[0x1];
1157         u8         sctr_data_cqe[0x1];
1158         u8         reserved_28[0x1];
1159         u8         sho[0x1];
1160         u8         tph[0x1];
1161         u8         rf[0x1];
1162         u8         dct[0x1];
1163         u8         qos[0x1];
1164         u8         eth_net_offloads[0x1];
1165         u8         roce[0x1];
1166         u8         atomic[0x1];
1167         u8         reserved_30[0x1];
1168
1169         u8         cq_oi[0x1];
1170         u8         cq_resize[0x1];
1171         u8         cq_moderation[0x1];
1172         u8         cq_period_mode_modify[0x1];
1173         u8         cq_invalidate[0x1];
1174         u8         reserved_at_225[0x1];
1175         u8         cq_eq_remap[0x1];
1176         u8         pg[0x1];
1177         u8         block_lb_mc[0x1];
1178         u8         exponential_backoff[0x1];
1179         u8         scqe_break_moderation[0x1];
1180         u8         cq_period_start_from_cqe[0x1];
1181         u8         cd[0x1];
1182         u8         atm[0x1];
1183         u8         apm[0x1];
1184         u8         imaicl[0x1];
1185         u8         reserved_32[0x6];
1186         u8         qkv[0x1];
1187         u8         pkv[0x1];
1188         u8         set_deth_sqpn[0x1];
1189         u8         reserved_33[0x3];
1190         u8         xrc[0x1];
1191         u8         ud[0x1];
1192         u8         uc[0x1];
1193         u8         rc[0x1];
1194
1195         u8         reserved_34[0xa];
1196         u8         uar_sz[0x6];
1197         u8         reserved_35[0x8];
1198         u8         log_pg_sz[0x8];
1199
1200         u8         bf[0x1];
1201         u8         driver_version[0x1];
1202         u8         pad_tx_eth_packet[0x1];
1203         u8         reserved_36[0x8];
1204         u8         log_bf_reg_size[0x5];
1205         u8         reserved_37[0x10];
1206
1207         u8         num_of_diagnostic_counters[0x10];
1208         u8         max_wqe_sz_sq[0x10];
1209
1210         u8         reserved_38[0x10];
1211         u8         max_wqe_sz_rq[0x10];
1212
1213         u8         reserved_39[0x10];
1214         u8         max_wqe_sz_sq_dc[0x10];
1215
1216         u8         reserved_40[0x7];
1217         u8         max_qp_mcg[0x19];
1218
1219         u8         reserved_41[0x18];
1220         u8         log_max_mcg[0x8];
1221
1222         u8         reserved_42[0x3];
1223         u8         log_max_transport_domain[0x5];
1224         u8         reserved_43[0x3];
1225         u8         log_max_pd[0x5];
1226         u8         reserved_44[0xb];
1227         u8         log_max_xrcd[0x5];
1228
1229         u8         nic_receive_steering_discard[0x1];
1230         u8         reserved_45[0x7];
1231         u8         log_max_flow_counter_bulk[0x8];
1232         u8         max_flow_counter[0x10];
1233
1234         u8         reserved_46[0x3];
1235         u8         log_max_rq[0x5];
1236         u8         reserved_47[0x3];
1237         u8         log_max_sq[0x5];
1238         u8         reserved_48[0x3];
1239         u8         log_max_tir[0x5];
1240         u8         reserved_49[0x3];
1241         u8         log_max_tis[0x5];
1242
1243         u8         basic_cyclic_rcv_wqe[0x1];
1244         u8         reserved_50[0x2];
1245         u8         log_max_rmp[0x5];
1246         u8         reserved_51[0x3];
1247         u8         log_max_rqt[0x5];
1248         u8         reserved_52[0x3];
1249         u8         log_max_rqt_size[0x5];
1250         u8         reserved_53[0x3];
1251         u8         log_max_tis_per_sq[0x5];
1252
1253         u8         reserved_54[0x3];
1254         u8         log_max_stride_sz_rq[0x5];
1255         u8         reserved_55[0x3];
1256         u8         log_min_stride_sz_rq[0x5];
1257         u8         reserved_56[0x3];
1258         u8         log_max_stride_sz_sq[0x5];
1259         u8         reserved_57[0x3];
1260         u8         log_min_stride_sz_sq[0x5];
1261
1262         u8         reserved_58[0x1b];
1263         u8         log_max_wq_sz[0x5];
1264
1265         u8         nic_vport_change_event[0x1];
1266         u8         disable_local_lb[0x1];
1267         u8         reserved_59[0x9];
1268         u8         log_max_vlan_list[0x5];
1269         u8         reserved_60[0x3];
1270         u8         log_max_current_mc_list[0x5];
1271         u8         reserved_61[0x3];
1272         u8         log_max_current_uc_list[0x5];
1273
1274         u8         general_obj_types[0x40];
1275
1276         u8         reserved_at_440[0x8];
1277         u8         create_qp_start_hint[0x18];
1278
1279         u8         reserved_at_460[0x3];
1280         u8         log_max_uctx[0x5];
1281         u8         reserved_at_468[0x3];
1282         u8         log_max_umem[0x5];
1283         u8         max_num_eqs[0x10];
1284
1285         u8         reserved_at_480[0x1];
1286         u8         tls_tx[0x1];
1287         u8         reserved_at_482[0x1];
1288         u8         log_max_l2_table[0x5];
1289         u8         reserved_64[0x8];
1290         u8         log_uar_page_sz[0x10];
1291
1292         u8         reserved_65[0x20];
1293
1294         u8         device_frequency_mhz[0x20];
1295
1296         u8         device_frequency_khz[0x20];
1297
1298         u8         reserved_66[0x80];
1299
1300         u8         log_max_atomic_size_qp[0x8];
1301         u8         reserved_67[0x10];
1302         u8         log_max_atomic_size_dc[0x8];
1303
1304         u8         reserved_at_5a0[0x13];
1305         u8         log_max_dek[0x5];
1306         u8         reserved_at_5b8[0x4];
1307         u8         mini_cqe_resp_stride_index[0x1];
1308         u8         cqe_128_always[0x1];
1309         u8         cqe_compression_128b[0x1];
1310
1311         u8         cqe_compression[0x1];
1312
1313         u8         cqe_compression_timeout[0x10];
1314         u8         cqe_compression_max_num[0x10];
1315
1316         u8         reserved_69[0x220];
1317 };
1318
1319 enum mlx5_flow_destination_type {
1320         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1321         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1322         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1323 };
1324
1325 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1326         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1327         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1328         u8         reserved_0[0x40];
1329 };
1330
1331 struct mlx5_ifc_fte_match_param_bits {
1332         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1333
1334         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1335
1336         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1337
1338         u8         reserved_0[0xa00];
1339 };
1340
1341 enum {
1342         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1343         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1344         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1345         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1346         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1347 };
1348
1349 struct mlx5_ifc_rx_hash_field_select_bits {
1350         u8         l3_prot_type[0x1];
1351         u8         l4_prot_type[0x1];
1352         u8         selected_fields[0x1e];
1353 };
1354
1355 struct mlx5_ifc_tls_capabilities_bits {
1356         u8         tls_1_2_aes_gcm_128[0x1];
1357         u8         tls_1_3_aes_gcm_128[0x1];
1358         u8         tls_1_2_aes_gcm_256[0x1];
1359         u8         tls_1_3_aes_gcm_256[0x1];
1360         u8         reserved_at_4[0x1c];
1361
1362         u8         reserved_at_20[0x7e0];
1363 };
1364
1365 enum {
1366         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1367         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1368         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1369         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1370 };
1371
1372 enum rq_type {
1373         RQ_TYPE_NONE,
1374         RQ_TYPE_STRIDE,
1375 };
1376
1377 enum {
1378         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1379         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1380 };
1381
1382 struct mlx5_ifc_wq_bits {
1383         u8         wq_type[0x4];
1384         u8         wq_signature[0x1];
1385         u8         end_padding_mode[0x2];
1386         u8         cd_slave[0x1];
1387         u8         reserved_0[0x18];
1388
1389         u8         hds_skip_first_sge[0x1];
1390         u8         log2_hds_buf_size[0x3];
1391         u8         reserved_1[0x7];
1392         u8         page_offset[0x5];
1393         u8         lwm[0x10];
1394
1395         u8         reserved_2[0x8];
1396         u8         pd[0x18];
1397
1398         u8         reserved_3[0x8];
1399         u8         uar_page[0x18];
1400
1401         u8         dbr_addr[0x40];
1402
1403         u8         hw_counter[0x20];
1404
1405         u8         sw_counter[0x20];
1406
1407         u8         reserved_4[0xc];
1408         u8         log_wq_stride[0x4];
1409         u8         reserved_5[0x3];
1410         u8         log_wq_pg_sz[0x5];
1411         u8         reserved_6[0x3];
1412         u8         log_wq_sz[0x5];
1413
1414         u8         reserved_7[0x15];
1415         u8         single_wqe_log_num_of_strides[0x3];
1416         u8         two_byte_shift_en[0x1];
1417         u8         reserved_8[0x4];
1418         u8         single_stride_log_num_of_bytes[0x3];
1419
1420         u8         reserved_9[0x4c0];
1421
1422         struct mlx5_ifc_cmd_pas_bits pas[0];
1423 };
1424
1425 struct mlx5_ifc_rq_num_bits {
1426         u8         reserved_0[0x8];
1427         u8         rq_num[0x18];
1428 };
1429
1430 struct mlx5_ifc_mac_address_layout_bits {
1431         u8         reserved_0[0x10];
1432         u8         mac_addr_47_32[0x10];
1433
1434         u8         mac_addr_31_0[0x20];
1435 };
1436
1437 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1438         u8         reserved_0[0xa0];
1439
1440         u8         min_time_between_cnps[0x20];
1441
1442         u8         reserved_1[0x12];
1443         u8         cnp_dscp[0x6];
1444         u8         reserved_2[0x4];
1445         u8         cnp_prio_mode[0x1];
1446         u8         cnp_802p_prio[0x3];
1447
1448         u8         reserved_3[0x720];
1449 };
1450
1451 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1452         u8         reserved_0[0x60];
1453
1454         u8         reserved_1[0x4];
1455         u8         clamp_tgt_rate[0x1];
1456         u8         reserved_2[0x3];
1457         u8         clamp_tgt_rate_after_time_inc[0x1];
1458         u8         reserved_3[0x17];
1459
1460         u8         reserved_4[0x20];
1461
1462         u8         rpg_time_reset[0x20];
1463
1464         u8         rpg_byte_reset[0x20];
1465
1466         u8         rpg_threshold[0x20];
1467
1468         u8         rpg_max_rate[0x20];
1469
1470         u8         rpg_ai_rate[0x20];
1471
1472         u8         rpg_hai_rate[0x20];
1473
1474         u8         rpg_gd[0x20];
1475
1476         u8         rpg_min_dec_fac[0x20];
1477
1478         u8         rpg_min_rate[0x20];
1479
1480         u8         reserved_5[0xe0];
1481
1482         u8         rate_to_set_on_first_cnp[0x20];
1483
1484         u8         dce_tcp_g[0x20];
1485
1486         u8         dce_tcp_rtt[0x20];
1487
1488         u8         rate_reduce_monitor_period[0x20];
1489
1490         u8         reserved_6[0x20];
1491
1492         u8         initial_alpha_value[0x20];
1493
1494         u8         reserved_7[0x4a0];
1495 };
1496
1497 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1498         u8         reserved_0[0x80];
1499
1500         u8         rppp_max_rps[0x20];
1501
1502         u8         rpg_time_reset[0x20];
1503
1504         u8         rpg_byte_reset[0x20];
1505
1506         u8         rpg_threshold[0x20];
1507
1508         u8         rpg_max_rate[0x20];
1509
1510         u8         rpg_ai_rate[0x20];
1511
1512         u8         rpg_hai_rate[0x20];
1513
1514         u8         rpg_gd[0x20];
1515
1516         u8         rpg_min_dec_fac[0x20];
1517
1518         u8         rpg_min_rate[0x20];
1519
1520         u8         reserved_1[0x640];
1521 };
1522
1523 enum {
1524         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1525         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1526         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1527 };
1528
1529 struct mlx5_ifc_resize_field_select_bits {
1530         u8         resize_field_select[0x20];
1531 };
1532
1533 enum {
1534         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1535         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1536         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1537         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1538         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1539         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1540 };
1541
1542 struct mlx5_ifc_modify_field_select_bits {
1543         u8         modify_field_select[0x20];
1544 };
1545
1546 struct mlx5_ifc_field_select_r_roce_np_bits {
1547         u8         field_select_r_roce_np[0x20];
1548 };
1549
1550 enum {
1551         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1552         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1553         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1554         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1555         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1556         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1557         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1558         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1559         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1560         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1561         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1562         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1563         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1564         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1565         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1566 };
1567
1568 struct mlx5_ifc_field_select_r_roce_rp_bits {
1569         u8         field_select_r_roce_rp[0x20];
1570 };
1571
1572 enum {
1573         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1574         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1575         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1576         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1577         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1578         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1579         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1580         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1581         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1582         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1583 };
1584
1585 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1586         u8         field_select_8021qaurp[0x20];
1587 };
1588
1589 struct mlx5_ifc_pptb_reg_bits {
1590         u8         reserved_at_0[0x2];
1591         u8         mm[0x2];
1592         u8         reserved_at_4[0x4];
1593         u8         local_port[0x8];
1594         u8         reserved_at_10[0x6];
1595         u8         cm[0x1];
1596         u8         um[0x1];
1597         u8         pm[0x8];
1598
1599         u8         prio_x_buff[0x20];
1600
1601         u8         pm_msb[0x8];
1602         u8         reserved_at_48[0x10];
1603         u8         ctrl_buff[0x4];
1604         u8         untagged_buff[0x4];
1605 };
1606
1607 struct mlx5_ifc_dcbx_app_reg_bits {
1608         u8         reserved_0[0x8];
1609         u8         port_number[0x8];
1610         u8         reserved_1[0x10];
1611
1612         u8         reserved_2[0x1a];
1613         u8         num_app_prio[0x6];
1614
1615         u8         reserved_3[0x40];
1616
1617         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1618 };
1619
1620 struct mlx5_ifc_dcbx_param_reg_bits {
1621         u8         dcbx_cee_cap[0x1];
1622         u8         dcbx_ieee_cap[0x1];
1623         u8         dcbx_standby_cap[0x1];
1624         u8         reserved_0[0x5];
1625         u8         port_number[0x8];
1626         u8         reserved_1[0xa];
1627         u8         max_application_table_size[0x6];
1628
1629         u8         reserved_2[0x15];
1630         u8         version_oper[0x3];
1631         u8         reserved_3[0x5];
1632         u8         version_admin[0x3];
1633
1634         u8         willing_admin[0x1];
1635         u8         reserved_4[0x3];
1636         u8         pfc_cap_oper[0x4];
1637         u8         reserved_5[0x4];
1638         u8         pfc_cap_admin[0x4];
1639         u8         reserved_6[0x4];
1640         u8         num_of_tc_oper[0x4];
1641         u8         reserved_7[0x4];
1642         u8         num_of_tc_admin[0x4];
1643
1644         u8         remote_willing[0x1];
1645         u8         reserved_8[0x3];
1646         u8         remote_pfc_cap[0x4];
1647         u8         reserved_9[0x14];
1648         u8         remote_num_of_tc[0x4];
1649
1650         u8         reserved_10[0x18];
1651         u8         error[0x8];
1652
1653         u8         reserved_11[0x160];
1654 };
1655
1656 struct mlx5_ifc_qhll_bits {
1657         u8         reserved_at_0[0x8];
1658         u8         local_port[0x8];
1659         u8         reserved_at_10[0x10];
1660
1661         u8         reserved_at_20[0x1b];
1662         u8         hll_time[0x5];
1663
1664         u8         stall_en[0x1];
1665         u8         reserved_at_41[0x1c];
1666         u8         stall_cnt[0x3];
1667 };
1668
1669 struct mlx5_ifc_qetcr_reg_bits {
1670         u8         operation_type[0x2];
1671         u8         cap_local_admin[0x1];
1672         u8         cap_remote_admin[0x1];
1673         u8         reserved_0[0x4];
1674         u8         port_number[0x8];
1675         u8         reserved_1[0x10];
1676
1677         u8         reserved_2[0x20];
1678
1679         u8         tc[8][0x40];
1680
1681         u8         global_configuration[0x40];
1682 };
1683
1684 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1685         u8         queue_address_63_32[0x20];
1686
1687         u8         queue_address_31_12[0x14];
1688         u8         reserved_0[0x6];
1689         u8         log_size[0x6];
1690
1691         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1692
1693         u8         reserved_1[0x8];
1694         u8         queue_number[0x18];
1695
1696         u8         q_key[0x20];
1697
1698         u8         reserved_2[0x10];
1699         u8         pkey_index[0x10];
1700
1701         u8         reserved_3[0x40];
1702 };
1703
1704 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1705         u8         reserved_0[0x8];
1706         u8         cq_ci[0x10];
1707         u8         reserved_1[0x8];
1708 };
1709
1710 enum {
1711         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1712         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1713 };
1714
1715 enum {
1716         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1717         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1718         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1719         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1720 };
1721
1722 struct mlx5_ifc_nodnic_event_word_bits {
1723         u8         driver_reset_needed[0x1];
1724         u8         port_management_change_event[0x1];
1725         u8         reserved_0[0x19];
1726         u8         link_type[0x1];
1727         u8         port_state[0x4];
1728 };
1729
1730 struct mlx5_ifc_nic_vport_change_event_bits {
1731         u8         reserved_0[0x10];
1732         u8         vport_num[0x10];
1733
1734         u8         reserved_1[0xc0];
1735 };
1736
1737 struct mlx5_ifc_pages_req_event_bits {
1738         u8         reserved_0[0x10];
1739         u8         function_id[0x10];
1740
1741         u8         num_pages[0x20];
1742
1743         u8         reserved_1[0xa0];
1744 };
1745
1746 struct mlx5_ifc_cmd_inter_comp_event_bits {
1747         u8         command_completion_vector[0x20];
1748
1749         u8         reserved_0[0xc0];
1750 };
1751
1752 struct mlx5_ifc_stall_vl_event_bits {
1753         u8         reserved_0[0x18];
1754         u8         port_num[0x1];
1755         u8         reserved_1[0x3];
1756         u8         vl[0x4];
1757
1758         u8         reserved_2[0xa0];
1759 };
1760
1761 struct mlx5_ifc_db_bf_congestion_event_bits {
1762         u8         event_subtype[0x8];
1763         u8         reserved_0[0x8];
1764         u8         congestion_level[0x8];
1765         u8         reserved_1[0x8];
1766
1767         u8         reserved_2[0xa0];
1768 };
1769
1770 struct mlx5_ifc_gpio_event_bits {
1771         u8         reserved_0[0x60];
1772
1773         u8         gpio_event_hi[0x20];
1774
1775         u8         gpio_event_lo[0x20];
1776
1777         u8         reserved_1[0x40];
1778 };
1779
1780 struct mlx5_ifc_port_state_change_event_bits {
1781         u8         reserved_0[0x40];
1782
1783         u8         port_num[0x4];
1784         u8         reserved_1[0x1c];
1785
1786         u8         reserved_2[0x80];
1787 };
1788
1789 struct mlx5_ifc_dropped_packet_logged_bits {
1790         u8         reserved_0[0xe0];
1791 };
1792
1793 enum {
1794         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1795         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1796 };
1797
1798 struct mlx5_ifc_cq_error_bits {
1799         u8         reserved_0[0x8];
1800         u8         cqn[0x18];
1801
1802         u8         reserved_1[0x20];
1803
1804         u8         reserved_2[0x18];
1805         u8         syndrome[0x8];
1806
1807         u8         reserved_3[0x80];
1808 };
1809
1810 struct mlx5_ifc_rdma_page_fault_event_bits {
1811         u8         bytes_commited[0x20];
1812
1813         u8         r_key[0x20];
1814
1815         u8         reserved_0[0x10];
1816         u8         packet_len[0x10];
1817
1818         u8         rdma_op_len[0x20];
1819
1820         u8         rdma_va[0x40];
1821
1822         u8         reserved_1[0x5];
1823         u8         rdma[0x1];
1824         u8         write[0x1];
1825         u8         requestor[0x1];
1826         u8         qp_number[0x18];
1827 };
1828
1829 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1830         u8         bytes_committed[0x20];
1831
1832         u8         reserved_0[0x10];
1833         u8         wqe_index[0x10];
1834
1835         u8         reserved_1[0x10];
1836         u8         len[0x10];
1837
1838         u8         reserved_2[0x60];
1839
1840         u8         reserved_3[0x5];
1841         u8         rdma[0x1];
1842         u8         write_read[0x1];
1843         u8         requestor[0x1];
1844         u8         qpn[0x18];
1845 };
1846
1847 enum {
1848         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1849         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1850         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1851 };
1852
1853 struct mlx5_ifc_qp_events_bits {
1854         u8         reserved_0[0xa0];
1855
1856         u8         type[0x8];
1857         u8         reserved_1[0x18];
1858
1859         u8         reserved_2[0x8];
1860         u8         qpn_rqn_sqn[0x18];
1861 };
1862
1863 struct mlx5_ifc_dct_events_bits {
1864         u8         reserved_0[0xc0];
1865
1866         u8         reserved_1[0x8];
1867         u8         dct_number[0x18];
1868 };
1869
1870 struct mlx5_ifc_comp_event_bits {
1871         u8         reserved_0[0xc0];
1872
1873         u8         reserved_1[0x8];
1874         u8         cq_number[0x18];
1875 };
1876
1877 struct mlx5_ifc_fw_version_bits {
1878         u8         major[0x10];
1879         u8         reserved_0[0x10];
1880
1881         u8         minor[0x10];
1882         u8         subminor[0x10];
1883
1884         u8         second[0x8];
1885         u8         minute[0x8];
1886         u8         hour[0x8];
1887         u8         reserved_1[0x8];
1888
1889         u8         year[0x10];
1890         u8         month[0x8];
1891         u8         day[0x8];
1892 };
1893
1894 enum {
1895         MLX5_QPC_STATE_RST        = 0x0,
1896         MLX5_QPC_STATE_INIT       = 0x1,
1897         MLX5_QPC_STATE_RTR        = 0x2,
1898         MLX5_QPC_STATE_RTS        = 0x3,
1899         MLX5_QPC_STATE_SQER       = 0x4,
1900         MLX5_QPC_STATE_SQD        = 0x5,
1901         MLX5_QPC_STATE_ERR        = 0x6,
1902         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1903 };
1904
1905 enum {
1906         MLX5_QPC_ST_RC            = 0x0,
1907         MLX5_QPC_ST_UC            = 0x1,
1908         MLX5_QPC_ST_UD            = 0x2,
1909         MLX5_QPC_ST_XRC           = 0x3,
1910         MLX5_QPC_ST_DCI           = 0x5,
1911         MLX5_QPC_ST_QP0           = 0x7,
1912         MLX5_QPC_ST_QP1           = 0x8,
1913         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1914         MLX5_QPC_ST_REG_UMR       = 0xc,
1915 };
1916
1917 enum {
1918         MLX5_QP_PM_ARMED            = 0x0,
1919         MLX5_QP_PM_REARM            = 0x1,
1920         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1921         MLX5_QP_PM_MIGRATED         = 0x3,
1922 };
1923
1924 enum {
1925         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1926         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1927 };
1928
1929 enum {
1930         MLX5_QPC_MTU_256_BYTES        = 0x1,
1931         MLX5_QPC_MTU_512_BYTES        = 0x2,
1932         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1933         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1934         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1935         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1936 };
1937
1938 enum {
1939         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1940         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1941         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1942         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1943         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1944         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1945         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1946         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1947 };
1948
1949 enum {
1950         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1951         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1952         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1953 };
1954
1955 enum {
1956         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1957         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1958         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1959 };
1960
1961 struct mlx5_ifc_qpc_bits {
1962         u8         state[0x4];
1963         u8         lag_tx_port_affinity[0x4];
1964         u8         st[0x8];
1965         u8         reserved_1[0x3];
1966         u8         pm_state[0x2];
1967         u8         reserved_2[0x7];
1968         u8         end_padding_mode[0x2];
1969         u8         reserved_3[0x2];
1970
1971         u8         wq_signature[0x1];
1972         u8         block_lb_mc[0x1];
1973         u8         atomic_like_write_en[0x1];
1974         u8         latency_sensitive[0x1];
1975         u8         reserved_4[0x1];
1976         u8         drain_sigerr[0x1];
1977         u8         reserved_5[0x2];
1978         u8         pd[0x18];
1979
1980         u8         mtu[0x3];
1981         u8         log_msg_max[0x5];
1982         u8         reserved_6[0x1];
1983         u8         log_rq_size[0x4];
1984         u8         log_rq_stride[0x3];
1985         u8         no_sq[0x1];
1986         u8         log_sq_size[0x4];
1987         u8         reserved_7[0x6];
1988         u8         rlky[0x1];
1989         u8         ulp_stateless_offload_mode[0x4];
1990
1991         u8         counter_set_id[0x8];
1992         u8         uar_page[0x18];
1993
1994         u8         reserved_8[0x8];
1995         u8         user_index[0x18];
1996
1997         u8         reserved_9[0x3];
1998         u8         log_page_size[0x5];
1999         u8         remote_qpn[0x18];
2000
2001         struct mlx5_ifc_ads_bits primary_address_path;
2002
2003         struct mlx5_ifc_ads_bits secondary_address_path;
2004
2005         u8         log_ack_req_freq[0x4];
2006         u8         reserved_10[0x4];
2007         u8         log_sra_max[0x3];
2008         u8         reserved_11[0x2];
2009         u8         retry_count[0x3];
2010         u8         rnr_retry[0x3];
2011         u8         reserved_12[0x1];
2012         u8         fre[0x1];
2013         u8         cur_rnr_retry[0x3];
2014         u8         cur_retry_count[0x3];
2015         u8         reserved_13[0x5];
2016
2017         u8         reserved_14[0x20];
2018
2019         u8         reserved_15[0x8];
2020         u8         next_send_psn[0x18];
2021
2022         u8         reserved_16[0x8];
2023         u8         cqn_snd[0x18];
2024
2025         u8         reserved_at_400[0x8];
2026
2027         u8         deth_sqpn[0x18];
2028         u8         reserved_17[0x20];
2029
2030         u8         reserved_18[0x8];
2031         u8         last_acked_psn[0x18];
2032
2033         u8         reserved_19[0x8];
2034         u8         ssn[0x18];
2035
2036         u8         reserved_20[0x8];
2037         u8         log_rra_max[0x3];
2038         u8         reserved_21[0x1];
2039         u8         atomic_mode[0x4];
2040         u8         rre[0x1];
2041         u8         rwe[0x1];
2042         u8         rae[0x1];
2043         u8         reserved_22[0x1];
2044         u8         page_offset[0x6];
2045         u8         reserved_23[0x3];
2046         u8         cd_slave_receive[0x1];
2047         u8         cd_slave_send[0x1];
2048         u8         cd_master[0x1];
2049
2050         u8         reserved_24[0x3];
2051         u8         min_rnr_nak[0x5];
2052         u8         next_rcv_psn[0x18];
2053
2054         u8         reserved_25[0x8];
2055         u8         xrcd[0x18];
2056
2057         u8         reserved_26[0x8];
2058         u8         cqn_rcv[0x18];
2059
2060         u8         dbr_addr[0x40];
2061
2062         u8         q_key[0x20];
2063
2064         u8         reserved_27[0x5];
2065         u8         rq_type[0x3];
2066         u8         srqn_rmpn[0x18];
2067
2068         u8         reserved_28[0x8];
2069         u8         rmsn[0x18];
2070
2071         u8         hw_sq_wqebb_counter[0x10];
2072         u8         sw_sq_wqebb_counter[0x10];
2073
2074         u8         hw_rq_counter[0x20];
2075
2076         u8         sw_rq_counter[0x20];
2077
2078         u8         reserved_29[0x20];
2079
2080         u8         reserved_30[0xf];
2081         u8         cgs[0x1];
2082         u8         cs_req[0x8];
2083         u8         cs_res[0x8];
2084
2085         u8         dc_access_key[0x40];
2086
2087         u8         rdma_active[0x1];
2088         u8         comm_est[0x1];
2089         u8         suspended[0x1];
2090         u8         reserved_31[0x5];
2091         u8         send_msg_psn[0x18];
2092
2093         u8         reserved_32[0x8];
2094         u8         rcv_msg_psn[0x18];
2095
2096         u8         rdma_va[0x40];
2097
2098         u8         rdma_key[0x20];
2099
2100         u8         reserved_33[0x20];
2101 };
2102
2103 struct mlx5_ifc_roce_addr_layout_bits {
2104         u8         source_l3_address[16][0x8];
2105
2106         u8         reserved_0[0x3];
2107         u8         vlan_valid[0x1];
2108         u8         vlan_id[0xc];
2109         u8         source_mac_47_32[0x10];
2110
2111         u8         source_mac_31_0[0x20];
2112
2113         u8         reserved_1[0x14];
2114         u8         roce_l3_type[0x4];
2115         u8         roce_version[0x8];
2116
2117         u8         reserved_2[0x20];
2118 };
2119
2120 struct mlx5_ifc_rdbc_bits {
2121         u8         reserved_0[0x1c];
2122         u8         type[0x4];
2123
2124         u8         reserved_1[0x20];
2125
2126         u8         reserved_2[0x8];
2127         u8         psn[0x18];
2128
2129         u8         rkey[0x20];
2130
2131         u8         address[0x40];
2132
2133         u8         byte_count[0x20];
2134
2135         u8         reserved_3[0x20];
2136
2137         u8         atomic_resp[32][0x8];
2138 };
2139
2140 enum {
2141         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2142         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2143         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2144         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2145 };
2146
2147 struct mlx5_ifc_flow_context_bits {
2148         u8         reserved_0[0x20];
2149
2150         u8         group_id[0x20];
2151
2152         u8         reserved_1[0x8];
2153         u8         flow_tag[0x18];
2154
2155         u8         reserved_2[0x10];
2156         u8         action[0x10];
2157
2158         u8         reserved_3[0x8];
2159         u8         destination_list_size[0x18];
2160
2161         u8         reserved_4[0x8];
2162         u8         flow_counter_list_size[0x18];
2163
2164         u8         reserved_5[0x140];
2165
2166         struct mlx5_ifc_fte_match_param_bits match_value;
2167
2168         u8         reserved_6[0x600];
2169
2170         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2171 };
2172
2173 enum {
2174         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2175         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2176 };
2177
2178 struct mlx5_ifc_xrc_srqc_bits {
2179         u8         state[0x4];
2180         u8         log_xrc_srq_size[0x4];
2181         u8         reserved_0[0x18];
2182
2183         u8         wq_signature[0x1];
2184         u8         cont_srq[0x1];
2185         u8         reserved_1[0x1];
2186         u8         rlky[0x1];
2187         u8         basic_cyclic_rcv_wqe[0x1];
2188         u8         log_rq_stride[0x3];
2189         u8         xrcd[0x18];
2190
2191         u8         page_offset[0x6];
2192         u8         reserved_2[0x2];
2193         u8         cqn[0x18];
2194
2195         u8         reserved_3[0x20];
2196
2197         u8         reserved_4[0x2];
2198         u8         log_page_size[0x6];
2199         u8         user_index[0x18];
2200
2201         u8         reserved_5[0x20];
2202
2203         u8         reserved_6[0x8];
2204         u8         pd[0x18];
2205
2206         u8         lwm[0x10];
2207         u8         wqe_cnt[0x10];
2208
2209         u8         reserved_7[0x40];
2210
2211         u8         db_record_addr_h[0x20];
2212
2213         u8         db_record_addr_l[0x1e];
2214         u8         reserved_8[0x2];
2215
2216         u8         reserved_9[0x80];
2217 };
2218
2219 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2220         u8         counter_error_queues[0x20];
2221
2222         u8         total_error_queues[0x20];
2223
2224         u8         send_queue_priority_update_flow[0x20];
2225
2226         u8         reserved_at_60[0x20];
2227
2228         u8         nic_receive_steering_discard[0x40];
2229
2230         u8         receive_discard_vport_down[0x40];
2231
2232         u8         transmit_discard_vport_down[0x40];
2233
2234         u8         reserved_at_140[0xec0];
2235 };
2236
2237 struct mlx5_ifc_traffic_counter_bits {
2238         u8         packets[0x40];
2239
2240         u8         octets[0x40];
2241 };
2242
2243 struct mlx5_ifc_tisc_bits {
2244         u8         strict_lag_tx_port_affinity[0x1];
2245         u8         tls_en[0x1];
2246         u8         reserved_at_2[0x2];
2247         u8         lag_tx_port_affinity[0x04];
2248
2249         u8         reserved_at_8[0x4];
2250         u8         prio[0x4];
2251         u8         reserved_1[0x10];
2252
2253         u8         reserved_2[0x100];
2254
2255         u8         reserved_3[0x8];
2256         u8         transport_domain[0x18];
2257
2258         u8         reserved_4[0x8];
2259         u8         underlay_qpn[0x18];
2260
2261         u8         reserved_5[0x8];
2262         u8         pd[0x18];
2263
2264         u8         reserved_6[0x380];
2265 };
2266
2267 enum {
2268         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2269         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2270 };
2271
2272 enum {
2273         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2274         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2275 };
2276
2277 enum {
2278         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2279         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2280         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2281 };
2282
2283 enum {
2284         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2285         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2286 };
2287
2288 struct mlx5_ifc_tirc_bits {
2289         u8         reserved_0[0x20];
2290
2291         u8         disp_type[0x4];
2292         u8         tls_en[0x1];
2293         u8         reserved_at_25[0x1b];
2294
2295         u8         reserved_2[0x40];
2296
2297         u8         reserved_3[0x4];
2298         u8         lro_timeout_period_usecs[0x10];
2299         u8         lro_enable_mask[0x4];
2300         u8         lro_max_msg_sz[0x8];
2301
2302         u8         reserved_4[0x40];
2303
2304         u8         reserved_5[0x8];
2305         u8         inline_rqn[0x18];
2306
2307         u8         rx_hash_symmetric[0x1];
2308         u8         reserved_6[0x1];
2309         u8         tunneled_offload_en[0x1];
2310         u8         reserved_7[0x5];
2311         u8         indirect_table[0x18];
2312
2313         u8         rx_hash_fn[0x4];
2314         u8         reserved_8[0x2];
2315         u8         self_lb_en[0x2];
2316         u8         transport_domain[0x18];
2317
2318         u8         rx_hash_toeplitz_key[10][0x20];
2319
2320         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2321
2322         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2323
2324         u8         reserved_9[0x4c0];
2325 };
2326
2327 enum {
2328         MLX5_SRQC_STATE_GOOD   = 0x0,
2329         MLX5_SRQC_STATE_ERROR  = 0x1,
2330 };
2331
2332 struct mlx5_ifc_srqc_bits {
2333         u8         state[0x4];
2334         u8         log_srq_size[0x4];
2335         u8         reserved_0[0x18];
2336
2337         u8         wq_signature[0x1];
2338         u8         cont_srq[0x1];
2339         u8         reserved_1[0x1];
2340         u8         rlky[0x1];
2341         u8         reserved_2[0x1];
2342         u8         log_rq_stride[0x3];
2343         u8         xrcd[0x18];
2344
2345         u8         page_offset[0x6];
2346         u8         reserved_3[0x2];
2347         u8         cqn[0x18];
2348
2349         u8         reserved_4[0x20];
2350
2351         u8         reserved_5[0x2];
2352         u8         log_page_size[0x6];
2353         u8         reserved_6[0x18];
2354
2355         u8         reserved_7[0x20];
2356
2357         u8         reserved_8[0x8];
2358         u8         pd[0x18];
2359
2360         u8         lwm[0x10];
2361         u8         wqe_cnt[0x10];
2362
2363         u8         reserved_9[0x40];
2364
2365         u8         dbr_addr[0x40];
2366
2367         u8         reserved_10[0x80];
2368 };
2369
2370 enum {
2371         MLX5_SQC_STATE_RST  = 0x0,
2372         MLX5_SQC_STATE_RDY  = 0x1,
2373         MLX5_SQC_STATE_ERR  = 0x3,
2374 };
2375
2376 struct mlx5_ifc_sqc_bits {
2377         u8         rlkey[0x1];
2378         u8         cd_master[0x1];
2379         u8         fre[0x1];
2380         u8         flush_in_error_en[0x1];
2381         u8         allow_multi_pkt_send_wqe[0x1];
2382         u8         min_wqe_inline_mode[0x3];
2383         u8         state[0x4];
2384         u8         reg_umr[0x1];
2385         u8         allow_swp[0x1];
2386         u8         reserved_0[0x12];
2387
2388         u8         reserved_1[0x8];
2389         u8         user_index[0x18];
2390
2391         u8         reserved_2[0x8];
2392         u8         cqn[0x18];
2393
2394         u8         reserved_3[0x80];
2395
2396         u8         qos_para_vport_number[0x10];
2397         u8         packet_pacing_rate_limit_index[0x10];
2398
2399         u8         tis_lst_sz[0x10];
2400         u8         reserved_4[0x10];
2401
2402         u8         reserved_5[0x40];
2403
2404         u8         reserved_6[0x8];
2405         u8         tis_num_0[0x18];
2406
2407         struct mlx5_ifc_wq_bits wq;
2408 };
2409
2410 enum {
2411         MLX5_TSAR_TYPE_DWRR = 0,
2412         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2413         MLX5_TSAR_TYPE_ETS = 2
2414 };
2415
2416 struct mlx5_ifc_tsar_element_attributes_bits {
2417         u8         reserved_0[0x8];
2418         u8         tsar_type[0x8];
2419         u8         reserved_1[0x10];
2420 };
2421
2422 struct mlx5_ifc_vport_element_attributes_bits {
2423         u8         reserved_0[0x10];
2424         u8         vport_number[0x10];
2425 };
2426
2427 struct mlx5_ifc_vport_tc_element_attributes_bits {
2428         u8         traffic_class[0x10];
2429         u8         vport_number[0x10];
2430 };
2431
2432 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2433         u8         reserved_0[0x0C];
2434         u8         traffic_class[0x04];
2435         u8         qos_para_vport_number[0x10];
2436 };
2437
2438 enum {
2439         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2440         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2441         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2442         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2443 };
2444
2445 struct mlx5_ifc_scheduling_context_bits {
2446         u8         element_type[0x8];
2447         u8         reserved_at_8[0x18];
2448
2449         u8         element_attributes[0x20];
2450
2451         u8         parent_element_id[0x20];
2452
2453         u8         reserved_at_60[0x40];
2454
2455         u8         bw_share[0x20];
2456
2457         u8         max_average_bw[0x20];
2458
2459         u8         reserved_at_e0[0x120];
2460 };
2461
2462 struct mlx5_ifc_rqtc_bits {
2463         u8         reserved_0[0xa0];
2464
2465         u8         reserved_1[0x10];
2466         u8         rqt_max_size[0x10];
2467
2468         u8         reserved_2[0x10];
2469         u8         rqt_actual_size[0x10];
2470
2471         u8         reserved_3[0x6a0];
2472
2473         struct mlx5_ifc_rq_num_bits rq_num[0];
2474 };
2475
2476 enum {
2477         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2478         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2479 };
2480
2481 enum {
2482         MLX5_RQC_STATE_RST  = 0x0,
2483         MLX5_RQC_STATE_RDY  = 0x1,
2484         MLX5_RQC_STATE_ERR  = 0x3,
2485 };
2486
2487 enum {
2488         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2489         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2490 };
2491
2492 struct mlx5_ifc_rqc_bits {
2493         u8         rlkey[0x1];
2494         u8         delay_drop_en[0x1];
2495         u8         scatter_fcs[0x1];
2496         u8         vlan_strip_disable[0x1];
2497         u8         mem_rq_type[0x4];
2498         u8         state[0x4];
2499         u8         reserved_1[0x1];
2500         u8         flush_in_error_en[0x1];
2501         u8         reserved_2[0x12];
2502
2503         u8         reserved_3[0x8];
2504         u8         user_index[0x18];
2505
2506         u8         reserved_4[0x8];
2507         u8         cqn[0x18];
2508
2509         u8         counter_set_id[0x8];
2510         u8         reserved_5[0x18];
2511
2512         u8         reserved_6[0x8];
2513         u8         rmpn[0x18];
2514
2515         u8         reserved_7[0xe0];
2516
2517         struct mlx5_ifc_wq_bits wq;
2518 };
2519
2520 enum {
2521         MLX5_RMPC_STATE_RDY  = 0x1,
2522         MLX5_RMPC_STATE_ERR  = 0x3,
2523 };
2524
2525 struct mlx5_ifc_rmpc_bits {
2526         u8         reserved_0[0x8];
2527         u8         state[0x4];
2528         u8         reserved_1[0x14];
2529
2530         u8         basic_cyclic_rcv_wqe[0x1];
2531         u8         reserved_2[0x1f];
2532
2533         u8         reserved_3[0x140];
2534
2535         struct mlx5_ifc_wq_bits wq;
2536 };
2537
2538 enum {
2539         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2540         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2541         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2542 };
2543
2544 struct mlx5_ifc_nic_vport_context_bits {
2545         u8         reserved_0[0x5];
2546         u8         min_wqe_inline_mode[0x3];
2547         u8         reserved_1[0x15];
2548         u8         disable_mc_local_lb[0x1];
2549         u8         disable_uc_local_lb[0x1];
2550         u8         roce_en[0x1];
2551
2552         u8         arm_change_event[0x1];
2553         u8         reserved_2[0x1a];
2554         u8         event_on_mtu[0x1];
2555         u8         event_on_promisc_change[0x1];
2556         u8         event_on_vlan_change[0x1];
2557         u8         event_on_mc_address_change[0x1];
2558         u8         event_on_uc_address_change[0x1];
2559
2560         u8         reserved_3[0xe0];
2561
2562         u8         reserved_4[0x10];
2563         u8         mtu[0x10];
2564
2565         u8         system_image_guid[0x40];
2566
2567         u8         port_guid[0x40];
2568
2569         u8         node_guid[0x40];
2570
2571         u8         reserved_5[0x140];
2572
2573         u8         qkey_violation_counter[0x10];
2574         u8         reserved_6[0x10];
2575
2576         u8         reserved_7[0x420];
2577
2578         u8         promisc_uc[0x1];
2579         u8         promisc_mc[0x1];
2580         u8         promisc_all[0x1];
2581         u8         reserved_8[0x2];
2582         u8         allowed_list_type[0x3];
2583         u8         reserved_9[0xc];
2584         u8         allowed_list_size[0xc];
2585
2586         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2587
2588         u8         reserved_10[0x20];
2589
2590         u8         current_uc_mac_address[0][0x40];
2591 };
2592
2593 enum {
2594         MLX5_ACCESS_MODE_PA        = 0x0,
2595         MLX5_ACCESS_MODE_MTT       = 0x1,
2596         MLX5_ACCESS_MODE_KLM       = 0x2,
2597 };
2598
2599 struct mlx5_ifc_mkc_bits {
2600         u8         reserved_at_0[0x1];
2601         u8         free[0x1];
2602         u8         reserved_at_2[0x1];
2603         u8         access_mode_4_2[0x3];
2604         u8         reserved_at_6[0x7];
2605         u8         relaxed_ordering_write[0x1];
2606         u8         reserved_at_e[0x1];
2607         u8         small_fence_on_rdma_read_response[0x1];
2608         u8         umr_en[0x1];
2609         u8         a[0x1];
2610         u8         rw[0x1];
2611         u8         rr[0x1];
2612         u8         lw[0x1];
2613         u8         lr[0x1];
2614         u8         access_mode[0x2];
2615         u8         reserved_2[0x8];
2616
2617         u8         qpn[0x18];
2618         u8         mkey_7_0[0x8];
2619
2620         u8         reserved_3[0x20];
2621
2622         u8         length64[0x1];
2623         u8         bsf_en[0x1];
2624         u8         sync_umr[0x1];
2625         u8         reserved_4[0x2];
2626         u8         expected_sigerr_count[0x1];
2627         u8         reserved_5[0x1];
2628         u8         en_rinval[0x1];
2629         u8         pd[0x18];
2630
2631         u8         start_addr[0x40];
2632
2633         u8         len[0x40];
2634
2635         u8         bsf_octword_size[0x20];
2636
2637         u8         reserved_6[0x80];
2638
2639         u8         translations_octword_size[0x20];
2640
2641         u8         reserved_7[0x1b];
2642         u8         log_page_size[0x5];
2643
2644         u8         reserved_8[0x20];
2645 };
2646
2647 struct mlx5_ifc_pkey_bits {
2648         u8         reserved_0[0x10];
2649         u8         pkey[0x10];
2650 };
2651
2652 struct mlx5_ifc_array128_auto_bits {
2653         u8         array128_auto[16][0x8];
2654 };
2655
2656 enum {
2657         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2658         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2659         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2660 };
2661
2662 enum {
2663         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2664         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2665         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2666         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2667         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2668         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2669         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2670 };
2671
2672 enum {
2673         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2674         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2675         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2676 };
2677
2678 enum {
2679         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2680         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2681         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2682         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2683 };
2684
2685 enum {
2686         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2687         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2688         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2689         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2690 };
2691
2692 struct mlx5_ifc_hca_vport_context_bits {
2693         u8         field_select[0x20];
2694
2695         u8         reserved_0[0xe0];
2696
2697         u8         sm_virt_aware[0x1];
2698         u8         has_smi[0x1];
2699         u8         has_raw[0x1];
2700         u8         grh_required[0x1];
2701         u8         reserved_1[0x1];
2702         u8         min_wqe_inline_mode[0x3];
2703         u8         reserved_2[0x8];
2704         u8         port_physical_state[0x4];
2705         u8         vport_state_policy[0x4];
2706         u8         port_state[0x4];
2707         u8         vport_state[0x4];
2708
2709         u8         reserved_3[0x20];
2710
2711         u8         system_image_guid[0x40];
2712
2713         u8         port_guid[0x40];
2714
2715         u8         node_guid[0x40];
2716
2717         u8         cap_mask1[0x20];
2718
2719         u8         cap_mask1_field_select[0x20];
2720
2721         u8         cap_mask2[0x20];
2722
2723         u8         cap_mask2_field_select[0x20];
2724
2725         u8         reserved_4[0x80];
2726
2727         u8         lid[0x10];
2728         u8         reserved_5[0x4];
2729         u8         init_type_reply[0x4];
2730         u8         lmc[0x3];
2731         u8         subnet_timeout[0x5];
2732
2733         u8         sm_lid[0x10];
2734         u8         sm_sl[0x4];
2735         u8         reserved_6[0xc];
2736
2737         u8         qkey_violation_counter[0x10];
2738         u8         pkey_violation_counter[0x10];
2739
2740         u8         reserved_7[0xca0];
2741 };
2742
2743 union mlx5_ifc_hca_cap_union_bits {
2744         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2745         struct mlx5_ifc_odp_cap_bits odp_cap;
2746         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2747         struct mlx5_ifc_roce_cap_bits roce_cap;
2748         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2749         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2750         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2751         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2752         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2753         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2754         struct mlx5_ifc_qos_cap_bits qos_cap;
2755         struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2756         u8         reserved_0[0x8000];
2757 };
2758
2759 enum {
2760         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2761         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2762 };
2763
2764 struct mlx5_ifc_flow_table_context_bits {
2765         u8         encap_en[0x1];
2766         u8         decap_en[0x1];
2767         u8         reserved_at_2[0x2];
2768         u8         table_miss_action[0x4];
2769         u8         level[0x8];
2770         u8         reserved_at_10[0x8];
2771         u8         log_size[0x8];
2772
2773         u8         reserved_at_20[0x8];
2774         u8         table_miss_id[0x18];
2775
2776         u8         reserved_at_40[0x8];
2777         u8         lag_master_next_table_id[0x18];
2778
2779         u8         reserved_at_60[0xe0];
2780 };
2781
2782 struct mlx5_ifc_esw_vport_context_bits {
2783         u8         reserved_0[0x3];
2784         u8         vport_svlan_strip[0x1];
2785         u8         vport_cvlan_strip[0x1];
2786         u8         vport_svlan_insert[0x1];
2787         u8         vport_cvlan_insert[0x2];
2788         u8         reserved_1[0x18];
2789
2790         u8         reserved_2[0x20];
2791
2792         u8         svlan_cfi[0x1];
2793         u8         svlan_pcp[0x3];
2794         u8         svlan_id[0xc];
2795         u8         cvlan_cfi[0x1];
2796         u8         cvlan_pcp[0x3];
2797         u8         cvlan_id[0xc];
2798
2799         u8         reserved_3[0x7a0];
2800 };
2801
2802 enum {
2803         MLX5_EQC_STATUS_OK                = 0x0,
2804         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2805 };
2806
2807 enum {
2808         MLX5_EQ_STATE_ARMED = 0x9,
2809         MLX5_EQ_STATE_FIRED = 0xa,
2810 };
2811
2812 struct mlx5_ifc_eqc_bits {
2813         u8         status[0x4];
2814         u8         reserved_0[0x9];
2815         u8         ec[0x1];
2816         u8         oi[0x1];
2817         u8         reserved_1[0x5];
2818         u8         st[0x4];
2819         u8         reserved_2[0x8];
2820
2821         u8         reserved_3[0x20];
2822
2823         u8         reserved_4[0x14];
2824         u8         page_offset[0x6];
2825         u8         reserved_5[0x6];
2826
2827         u8         reserved_6[0x3];
2828         u8         log_eq_size[0x5];
2829         u8         uar_page[0x18];
2830
2831         u8         reserved_7[0x20];
2832
2833         u8         reserved_8[0x18];
2834         u8         intr[0x8];
2835
2836         u8         reserved_9[0x3];
2837         u8         log_page_size[0x5];
2838         u8         reserved_10[0x18];
2839
2840         u8         reserved_11[0x60];
2841
2842         u8         reserved_12[0x8];
2843         u8         consumer_counter[0x18];
2844
2845         u8         reserved_13[0x8];
2846         u8         producer_counter[0x18];
2847
2848         u8         reserved_14[0x80];
2849 };
2850
2851 enum {
2852         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2853         MLX5_DCTC_STATE_DRAINING  = 0x1,
2854         MLX5_DCTC_STATE_DRAINED   = 0x2,
2855 };
2856
2857 enum {
2858         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2859         MLX5_DCTC_CS_RES_NA         = 0x1,
2860         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2861 };
2862
2863 enum {
2864         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2865         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2866         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2867         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2868         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2869 };
2870
2871 struct mlx5_ifc_dctc_bits {
2872         u8         reserved_0[0x4];
2873         u8         state[0x4];
2874         u8         reserved_1[0x18];
2875
2876         u8         reserved_2[0x8];
2877         u8         user_index[0x18];
2878
2879         u8         reserved_3[0x8];
2880         u8         cqn[0x18];
2881
2882         u8         counter_set_id[0x8];
2883         u8         atomic_mode[0x4];
2884         u8         rre[0x1];
2885         u8         rwe[0x1];
2886         u8         rae[0x1];
2887         u8         atomic_like_write_en[0x1];
2888         u8         latency_sensitive[0x1];
2889         u8         rlky[0x1];
2890         u8         reserved_4[0xe];
2891
2892         u8         reserved_5[0x8];
2893         u8         cs_res[0x8];
2894         u8         reserved_6[0x3];
2895         u8         min_rnr_nak[0x5];
2896         u8         reserved_7[0x8];
2897
2898         u8         reserved_8[0x8];
2899         u8         srqn[0x18];
2900
2901         u8         reserved_9[0x8];
2902         u8         pd[0x18];
2903
2904         u8         tclass[0x8];
2905         u8         reserved_10[0x4];
2906         u8         flow_label[0x14];
2907
2908         u8         dc_access_key[0x40];
2909
2910         u8         reserved_11[0x5];
2911         u8         mtu[0x3];
2912         u8         port[0x8];
2913         u8         pkey_index[0x10];
2914
2915         u8         reserved_12[0x8];
2916         u8         my_addr_index[0x8];
2917         u8         reserved_13[0x8];
2918         u8         hop_limit[0x8];
2919
2920         u8         dc_access_key_violation_count[0x20];
2921
2922         u8         reserved_14[0x14];
2923         u8         dei_cfi[0x1];
2924         u8         eth_prio[0x3];
2925         u8         ecn[0x2];
2926         u8         dscp[0x6];
2927
2928         u8         reserved_15[0x40];
2929 };
2930
2931 enum {
2932         MLX5_CQC_STATUS_OK             = 0x0,
2933         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2934         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2935 };
2936
2937 enum {
2938         CQE_SIZE_64                = 0x0,
2939         CQE_SIZE_128               = 0x1,
2940 };
2941
2942 enum {
2943         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2944         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2945 };
2946
2947 enum {
2948         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2949         MLX5_CQ_STATE_ARMED                               = 0x9,
2950         MLX5_CQ_STATE_FIRED                               = 0xa,
2951 };
2952
2953 struct mlx5_ifc_cqc_bits {
2954         u8         status[0x4];
2955         u8         reserved_0[0x4];
2956         u8         cqe_sz[0x3];
2957         u8         cc[0x1];
2958         u8         reserved_1[0x1];
2959         u8         scqe_break_moderation_en[0x1];
2960         u8         oi[0x1];
2961         u8         cq_period_mode[0x2];
2962         u8         cqe_compression_en[0x1];
2963         u8         mini_cqe_res_format[0x2];
2964         u8         st[0x4];
2965         u8         reserved_2[0x8];
2966
2967         u8         reserved_3[0x20];
2968
2969         u8         reserved_4[0x14];
2970         u8         page_offset[0x6];
2971         u8         reserved_5[0x6];
2972
2973         u8         reserved_6[0x3];
2974         u8         log_cq_size[0x5];
2975         u8         uar_page[0x18];
2976
2977         u8         reserved_7[0x4];
2978         u8         cq_period[0xc];
2979         u8         cq_max_count[0x10];
2980
2981         u8         reserved_8[0x18];
2982         u8         c_eqn[0x8];
2983
2984         u8         reserved_9[0x3];
2985         u8         log_page_size[0x5];
2986         u8         reserved_10[0x18];
2987
2988         u8         reserved_11[0x20];
2989
2990         u8         reserved_12[0x8];
2991         u8         last_notified_index[0x18];
2992
2993         u8         reserved_13[0x8];
2994         u8         last_solicit_index[0x18];
2995
2996         u8         reserved_14[0x8];
2997         u8         consumer_counter[0x18];
2998
2999         u8         reserved_15[0x8];
3000         u8         producer_counter[0x18];
3001
3002         u8         reserved_16[0x40];
3003
3004         u8         dbr_addr[0x40];
3005 };
3006
3007 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3008         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3009         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3010         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3011         u8         reserved_0[0x800];
3012 };
3013
3014 struct mlx5_ifc_query_adapter_param_block_bits {
3015         u8         reserved_0[0xc0];
3016
3017         u8         reserved_1[0x8];
3018         u8         ieee_vendor_id[0x18];
3019
3020         u8         reserved_2[0x10];
3021         u8         vsd_vendor_id[0x10];
3022
3023         u8         vsd[208][0x8];
3024
3025         u8         vsd_contd_psid[16][0x8];
3026 };
3027
3028 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3029         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3030         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3031         u8         reserved_0[0x20];
3032 };
3033
3034 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3035         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3036         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3037         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3038         u8         reserved_0[0x20];
3039 };
3040
3041 struct mlx5_ifc_bufferx_reg_bits {
3042         u8         reserved_0[0x6];
3043         u8         lossy[0x1];
3044         u8         epsb[0x1];
3045         u8         reserved_1[0xc];
3046         u8         size[0xc];
3047
3048         u8         xoff_threshold[0x10];
3049         u8         xon_threshold[0x10];
3050 };
3051
3052 struct mlx5_ifc_config_item_bits {
3053         u8         valid[0x2];
3054         u8         reserved_0[0x2];
3055         u8         header_type[0x2];
3056         u8         reserved_1[0x2];
3057         u8         default_location[0x1];
3058         u8         reserved_2[0x7];
3059         u8         version[0x4];
3060         u8         reserved_3[0x3];
3061         u8         length[0x9];
3062
3063         u8         type[0x20];
3064
3065         u8         reserved_4[0x10];
3066         u8         crc16[0x10];
3067 };
3068
3069 struct mlx5_ifc_nodnic_port_config_reg_bits {
3070         struct mlx5_ifc_nodnic_event_word_bits event;
3071
3072         u8         network_en[0x1];
3073         u8         dma_en[0x1];
3074         u8         promisc_en[0x1];
3075         u8         promisc_multicast_en[0x1];
3076         u8         reserved_0[0x17];
3077         u8         receive_filter_en[0x5];
3078
3079         u8         reserved_1[0x10];
3080         u8         mac_47_32[0x10];
3081
3082         u8         mac_31_0[0x20];
3083
3084         u8         receive_filters_mgid_mac[64][0x8];
3085
3086         u8         gid[16][0x8];
3087
3088         u8         reserved_2[0x10];
3089         u8         lid[0x10];
3090
3091         u8         reserved_3[0xc];
3092         u8         sm_sl[0x4];
3093         u8         sm_lid[0x10];
3094
3095         u8         completion_address_63_32[0x20];
3096
3097         u8         completion_address_31_12[0x14];
3098         u8         reserved_4[0x6];
3099         u8         log_cq_size[0x6];
3100
3101         u8         working_buffer_address_63_32[0x20];
3102
3103         u8         working_buffer_address_31_12[0x14];
3104         u8         reserved_5[0xc];
3105
3106         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3107
3108         u8         pkey_index[0x10];
3109         u8         pkey[0x10];
3110
3111         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3112
3113         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3114
3115         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3116
3117         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3118
3119         u8         reserved_6[0x400];
3120 };
3121
3122 union mlx5_ifc_event_auto_bits {
3123         struct mlx5_ifc_comp_event_bits comp_event;
3124         struct mlx5_ifc_dct_events_bits dct_events;
3125         struct mlx5_ifc_qp_events_bits qp_events;
3126         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3127         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3128         struct mlx5_ifc_cq_error_bits cq_error;
3129         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3130         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3131         struct mlx5_ifc_gpio_event_bits gpio_event;
3132         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3133         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3134         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3135         struct mlx5_ifc_pages_req_event_bits pages_req_event;
3136         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3137         u8         reserved_0[0xe0];
3138 };
3139
3140 struct mlx5_ifc_health_buffer_bits {
3141         u8         reserved_0[0x100];
3142
3143         u8         assert_existptr[0x20];
3144
3145         u8         assert_callra[0x20];
3146
3147         u8         reserved_1[0x40];
3148
3149         u8         fw_version[0x20];
3150
3151         u8         hw_id[0x20];
3152
3153         u8         reserved_2[0x20];
3154
3155         u8         irisc_index[0x8];
3156         u8         synd[0x8];
3157         u8         ext_synd[0x10];
3158 };
3159
3160 struct mlx5_ifc_register_loopback_control_bits {
3161         u8         no_lb[0x1];
3162         u8         reserved_0[0x7];
3163         u8         port[0x8];
3164         u8         reserved_1[0x10];
3165
3166         u8         reserved_2[0x60];
3167 };
3168
3169 struct mlx5_ifc_lrh_bits {
3170         u8      vl[4];
3171         u8      lver[4];
3172         u8      sl[4];
3173         u8      reserved2[2];
3174         u8      lnh[2];
3175         u8      dlid[16];
3176         u8      reserved5[5];
3177         u8      pkt_len[11];
3178         u8      slid[16];
3179 };
3180
3181 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3182         u8         reserved_0[0x40];
3183
3184         u8         reserved_1[0x10];
3185         u8         rol_mode[0x8];
3186         u8         wol_mode[0x8];
3187 };
3188
3189 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3190         u8         reserved_0[0x40];
3191
3192         u8         rol_mode_valid[0x1];
3193         u8         wol_mode_valid[0x1];
3194         u8         reserved_1[0xe];
3195         u8         rol_mode[0x8];
3196         u8         wol_mode[0x8];
3197
3198         u8         reserved_2[0x7a0];
3199 };
3200
3201 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3202         u8         virtual_mac_en[0x1];
3203         u8         mac_aux_v[0x1];
3204         u8         reserved_0[0x1e];
3205
3206         u8         reserved_1[0x40];
3207
3208         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3209
3210         u8         reserved_2[0x760];
3211 };
3212
3213 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3214         u8         virtual_mac_en[0x1];
3215         u8         mac_aux_v[0x1];
3216         u8         reserved_0[0x1e];
3217
3218         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3219
3220         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3221
3222         u8         reserved_1[0x760];
3223 };
3224
3225 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3226         struct mlx5_ifc_fw_version_bits fw_version;
3227
3228         u8         reserved_0[0x10];
3229         u8         hash_signature[0x10];
3230
3231         u8         psid[16][0x8];
3232
3233         u8         reserved_1[0x6e0];
3234 };
3235
3236 struct mlx5_ifc_icmd_query_cap_in_bits {
3237         u8         reserved_0[0x10];
3238         u8         capability_group[0x10];
3239 };
3240
3241 struct mlx5_ifc_icmd_query_cap_general_bits {
3242         u8         nv_access[0x1];
3243         u8         fw_info_psid[0x1];
3244         u8         reserved_0[0x1e];
3245
3246         u8         reserved_1[0x16];
3247         u8         rol_s[0x1];
3248         u8         rol_g[0x1];
3249         u8         reserved_2[0x1];
3250         u8         wol_s[0x1];
3251         u8         wol_g[0x1];
3252         u8         wol_a[0x1];
3253         u8         wol_b[0x1];
3254         u8         wol_m[0x1];
3255         u8         wol_u[0x1];
3256         u8         wol_p[0x1];
3257 };
3258
3259 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3260         u8         status[0x8];
3261         u8         reserved_0[0x18];
3262
3263         u8         reserved_1[0x7e0];
3264 };
3265
3266 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3267         u8         status[0x8];
3268         u8         reserved_0[0x18];
3269
3270         u8         reserved_1[0x7e0];
3271 };
3272
3273 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3274         u8         address_hi[0x20];
3275
3276         u8         address_lo[0x20];
3277
3278         u8         reserved_0[0x7c0];
3279 };
3280
3281 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3282         u8         reserved_0[0x20];
3283
3284         u8         address_hi[0x20];
3285
3286         u8         address_lo[0x20];
3287
3288         u8         reserved_1[0x7a0];
3289 };
3290
3291 struct mlx5_ifc_icmd_access_reg_out_bits {
3292         u8         reserved_0[0x11];
3293         u8         status[0x7];
3294         u8         reserved_1[0x8];
3295
3296         u8         register_id[0x10];
3297         u8         reserved_2[0x10];
3298
3299         u8         reserved_3[0x40];
3300
3301         u8         reserved_4[0x5];
3302         u8         len[0xb];
3303         u8         reserved_5[0x10];
3304
3305         u8         register_data[0][0x20];
3306 };
3307
3308 enum {
3309         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3310         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3311 };
3312
3313 struct mlx5_ifc_icmd_access_reg_in_bits {
3314         u8         constant_1[0x5];
3315         u8         constant_2[0xb];
3316         u8         reserved_0[0x10];
3317
3318         u8         register_id[0x10];
3319         u8         reserved_1[0x1];
3320         u8         method[0x7];
3321         u8         constant_3[0x8];
3322
3323         u8         reserved_2[0x40];
3324
3325         u8         constant_4[0x5];
3326         u8         len[0xb];
3327         u8         reserved_3[0x10];
3328
3329         u8         register_data[0][0x20];
3330 };
3331
3332 enum {
3333         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3334         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3335 };
3336
3337 struct mlx5_ifc_teardown_hca_out_bits {
3338         u8         status[0x8];
3339         u8         reserved_0[0x18];
3340
3341         u8         syndrome[0x20];
3342
3343         u8         reserved_1[0x3f];
3344
3345         u8         state[0x1];
3346 };
3347
3348 enum {
3349         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3350         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3351         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3352 };
3353
3354 struct mlx5_ifc_teardown_hca_in_bits {
3355         u8         opcode[0x10];
3356         u8         reserved_0[0x10];
3357
3358         u8         reserved_1[0x10];
3359         u8         op_mod[0x10];
3360
3361         u8         reserved_2[0x10];
3362         u8         profile[0x10];
3363
3364         u8         reserved_3[0x20];
3365 };
3366
3367 struct mlx5_ifc_set_delay_drop_params_out_bits {
3368         u8         status[0x8];
3369         u8         reserved_at_8[0x18];
3370
3371         u8         syndrome[0x20];
3372
3373         u8         reserved_at_40[0x40];
3374 };
3375
3376 struct mlx5_ifc_set_delay_drop_params_in_bits {
3377         u8         opcode[0x10];
3378         u8         reserved_at_10[0x10];
3379
3380         u8         reserved_at_20[0x10];
3381         u8         op_mod[0x10];
3382
3383         u8         reserved_at_40[0x20];
3384
3385         u8         reserved_at_60[0x10];
3386         u8         delay_drop_timeout[0x10];
3387 };
3388
3389 struct mlx5_ifc_query_delay_drop_params_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_at_8[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_at_40[0x20];
3396
3397         u8         reserved_at_60[0x10];
3398         u8         delay_drop_timeout[0x10];
3399 };
3400
3401 struct mlx5_ifc_query_delay_drop_params_in_bits {
3402         u8         opcode[0x10];
3403         u8         reserved_at_10[0x10];
3404
3405         u8         reserved_at_20[0x10];
3406         u8         op_mod[0x10];
3407
3408         u8         reserved_at_40[0x40];
3409 };
3410
3411 struct mlx5_ifc_suspend_qp_out_bits {
3412         u8         status[0x8];
3413         u8         reserved_0[0x18];
3414
3415         u8         syndrome[0x20];
3416
3417         u8         reserved_1[0x40];
3418 };
3419
3420 struct mlx5_ifc_suspend_qp_in_bits {
3421         u8         opcode[0x10];
3422         u8         reserved_0[0x10];
3423
3424         u8         reserved_1[0x10];
3425         u8         op_mod[0x10];
3426
3427         u8         reserved_2[0x8];
3428         u8         qpn[0x18];
3429
3430         u8         reserved_3[0x20];
3431 };
3432
3433 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3434         u8         status[0x8];
3435         u8         reserved_0[0x18];
3436
3437         u8         syndrome[0x20];
3438
3439         u8         reserved_1[0x40];
3440 };
3441
3442 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3443         u8         opcode[0x10];
3444         u8         reserved_0[0x10];
3445
3446         u8         reserved_1[0x10];
3447         u8         op_mod[0x10];
3448
3449         u8         reserved_2[0x8];
3450         u8         qpn[0x18];
3451
3452         u8         reserved_3[0x20];
3453
3454         u8         opt_param_mask[0x20];
3455
3456         u8         reserved_4[0x20];
3457
3458         struct mlx5_ifc_qpc_bits qpc;
3459
3460         u8         reserved_5[0x80];
3461 };
3462
3463 struct mlx5_ifc_sqd2rts_qp_out_bits {
3464         u8         status[0x8];
3465         u8         reserved_0[0x18];
3466
3467         u8         syndrome[0x20];
3468
3469         u8         reserved_1[0x40];
3470 };
3471
3472 struct mlx5_ifc_sqd2rts_qp_in_bits {
3473         u8         opcode[0x10];
3474         u8         reserved_0[0x10];
3475
3476         u8         reserved_1[0x10];
3477         u8         op_mod[0x10];
3478
3479         u8         reserved_2[0x8];
3480         u8         qpn[0x18];
3481
3482         u8         reserved_3[0x20];
3483
3484         u8         opt_param_mask[0x20];
3485
3486         u8         reserved_4[0x20];
3487
3488         struct mlx5_ifc_qpc_bits qpc;
3489
3490         u8         reserved_5[0x80];
3491 };
3492
3493 struct mlx5_ifc_set_wol_rol_out_bits {
3494         u8         status[0x8];
3495         u8         reserved_0[0x18];
3496
3497         u8         syndrome[0x20];
3498
3499         u8         reserved_1[0x40];
3500 };
3501
3502 struct mlx5_ifc_set_wol_rol_in_bits {
3503         u8         opcode[0x10];
3504         u8         reserved_0[0x10];
3505
3506         u8         reserved_1[0x10];
3507         u8         op_mod[0x10];
3508
3509         u8         rol_mode_valid[0x1];
3510         u8         wol_mode_valid[0x1];
3511         u8         reserved_2[0xe];
3512         u8         rol_mode[0x8];
3513         u8         wol_mode[0x8];
3514
3515         u8         reserved_3[0x20];
3516 };
3517
3518 struct mlx5_ifc_set_roce_address_out_bits {
3519         u8         status[0x8];
3520         u8         reserved_0[0x18];
3521
3522         u8         syndrome[0x20];
3523
3524         u8         reserved_1[0x40];
3525 };
3526
3527 struct mlx5_ifc_set_roce_address_in_bits {
3528         u8         opcode[0x10];
3529         u8         reserved_0[0x10];
3530
3531         u8         reserved_1[0x10];
3532         u8         op_mod[0x10];
3533
3534         u8         roce_address_index[0x10];
3535         u8         reserved_2[0x10];
3536
3537         u8         reserved_3[0x20];
3538
3539         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3540 };
3541
3542 struct mlx5_ifc_set_rdb_out_bits {
3543         u8         status[0x8];
3544         u8         reserved_0[0x18];
3545
3546         u8         syndrome[0x20];
3547
3548         u8         reserved_1[0x40];
3549 };
3550
3551 struct mlx5_ifc_set_rdb_in_bits {
3552         u8         opcode[0x10];
3553         u8         reserved_0[0x10];
3554
3555         u8         reserved_1[0x10];
3556         u8         op_mod[0x10];
3557
3558         u8         reserved_2[0x8];
3559         u8         qpn[0x18];
3560
3561         u8         reserved_3[0x18];
3562         u8         rdb_list_size[0x8];
3563
3564         struct mlx5_ifc_rdbc_bits rdb_context[0];
3565 };
3566
3567 struct mlx5_ifc_set_mad_demux_out_bits {
3568         u8         status[0x8];
3569         u8         reserved_0[0x18];
3570
3571         u8         syndrome[0x20];
3572
3573         u8         reserved_1[0x40];
3574 };
3575
3576 enum {
3577         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3578         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3579 };
3580
3581 struct mlx5_ifc_set_mad_demux_in_bits {
3582         u8         opcode[0x10];
3583         u8         reserved_0[0x10];
3584
3585         u8         reserved_1[0x10];
3586         u8         op_mod[0x10];
3587
3588         u8         reserved_2[0x20];
3589
3590         u8         reserved_3[0x6];
3591         u8         demux_mode[0x2];
3592         u8         reserved_4[0x18];
3593 };
3594
3595 struct mlx5_ifc_set_l2_table_entry_out_bits {
3596         u8         status[0x8];
3597         u8         reserved_0[0x18];
3598
3599         u8         syndrome[0x20];
3600
3601         u8         reserved_1[0x40];
3602 };
3603
3604 struct mlx5_ifc_set_l2_table_entry_in_bits {
3605         u8         opcode[0x10];
3606         u8         reserved_0[0x10];
3607
3608         u8         reserved_1[0x10];
3609         u8         op_mod[0x10];
3610
3611         u8         reserved_2[0x60];
3612
3613         u8         reserved_3[0x8];
3614         u8         table_index[0x18];
3615
3616         u8         reserved_4[0x20];
3617
3618         u8         reserved_5[0x13];
3619         u8         vlan_valid[0x1];
3620         u8         vlan[0xc];
3621
3622         struct mlx5_ifc_mac_address_layout_bits mac_address;
3623
3624         u8         reserved_6[0xc0];
3625 };
3626
3627 struct mlx5_ifc_set_issi_out_bits {
3628         u8         status[0x8];
3629         u8         reserved_0[0x18];
3630
3631         u8         syndrome[0x20];
3632
3633         u8         reserved_1[0x40];
3634 };
3635
3636 struct mlx5_ifc_set_issi_in_bits {
3637         u8         opcode[0x10];
3638         u8         reserved_0[0x10];
3639
3640         u8         reserved_1[0x10];
3641         u8         op_mod[0x10];
3642
3643         u8         reserved_2[0x10];
3644         u8         current_issi[0x10];
3645
3646         u8         reserved_3[0x20];
3647 };
3648
3649 struct mlx5_ifc_set_hca_cap_out_bits {
3650         u8         status[0x8];
3651         u8         reserved_0[0x18];
3652
3653         u8         syndrome[0x20];
3654
3655         u8         reserved_1[0x40];
3656 };
3657
3658 struct mlx5_ifc_set_hca_cap_in_bits {
3659         u8         opcode[0x10];
3660         u8         reserved_0[0x10];
3661
3662         u8         reserved_1[0x10];
3663         u8         op_mod[0x10];
3664
3665         u8         reserved_2[0x40];
3666
3667         union mlx5_ifc_hca_cap_union_bits capability;
3668 };
3669
3670 enum {
3671         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3672         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3673         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3674         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3675 };
3676
3677 struct mlx5_ifc_set_flow_table_root_out_bits {
3678         u8         status[0x8];
3679         u8         reserved_0[0x18];
3680
3681         u8         syndrome[0x20];
3682
3683         u8         reserved_1[0x40];
3684 };
3685
3686 struct mlx5_ifc_set_flow_table_root_in_bits {
3687         u8         opcode[0x10];
3688         u8         reserved_0[0x10];
3689
3690         u8         reserved_1[0x10];
3691         u8         op_mod[0x10];
3692
3693         u8         other_vport[0x1];
3694         u8         reserved_2[0xf];
3695         u8         vport_number[0x10];
3696
3697         u8         reserved_3[0x20];
3698
3699         u8         table_type[0x8];
3700         u8         reserved_4[0x18];
3701
3702         u8         reserved_5[0x8];
3703         u8         table_id[0x18];
3704
3705         u8         reserved_6[0x8];
3706         u8         underlay_qpn[0x18];
3707
3708         u8         reserved_7[0x120];
3709 };
3710
3711 struct mlx5_ifc_set_fte_out_bits {
3712         u8         status[0x8];
3713         u8         reserved_0[0x18];
3714
3715         u8         syndrome[0x20];
3716
3717         u8         reserved_1[0x40];
3718 };
3719
3720 struct mlx5_ifc_set_fte_in_bits {
3721         u8         opcode[0x10];
3722         u8         reserved_0[0x10];
3723
3724         u8         reserved_1[0x10];
3725         u8         op_mod[0x10];
3726
3727         u8         other_vport[0x1];
3728         u8         reserved_2[0xf];
3729         u8         vport_number[0x10];
3730
3731         u8         reserved_3[0x20];
3732
3733         u8         table_type[0x8];
3734         u8         reserved_4[0x18];
3735
3736         u8         reserved_5[0x8];
3737         u8         table_id[0x18];
3738
3739         u8         reserved_6[0x18];
3740         u8         modify_enable_mask[0x8];
3741
3742         u8         reserved_7[0x20];
3743
3744         u8         flow_index[0x20];
3745
3746         u8         reserved_8[0xe0];
3747
3748         struct mlx5_ifc_flow_context_bits flow_context;
3749 };
3750
3751 struct mlx5_ifc_set_driver_version_out_bits {
3752         u8         status[0x8];
3753         u8         reserved_0[0x18];
3754
3755         u8         syndrome[0x20];
3756
3757         u8         reserved_1[0x40];
3758 };
3759
3760 struct mlx5_ifc_set_driver_version_in_bits {
3761         u8         opcode[0x10];
3762         u8         reserved_0[0x10];
3763
3764         u8         reserved_1[0x10];
3765         u8         op_mod[0x10];
3766
3767         u8         reserved_2[0x40];
3768
3769         u8         driver_version[64][0x8];
3770 };
3771
3772 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3773         u8         status[0x8];
3774         u8         reserved_0[0x18];
3775
3776         u8         syndrome[0x20];
3777
3778         u8         reserved_1[0x40];
3779 };
3780
3781 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3782         u8         opcode[0x10];
3783         u8         reserved_0[0x10];
3784
3785         u8         reserved_1[0x10];
3786         u8         op_mod[0x10];
3787
3788         u8         enable[0x1];
3789         u8         reserved_2[0x1f];
3790
3791         u8         reserved_3[0x160];
3792
3793         struct mlx5_ifc_cmd_pas_bits pas;
3794 };
3795
3796 struct mlx5_ifc_set_burst_size_out_bits {
3797         u8         status[0x8];
3798         u8         reserved_0[0x18];
3799
3800         u8         syndrome[0x20];
3801
3802         u8         reserved_1[0x40];
3803 };
3804
3805 struct mlx5_ifc_set_burst_size_in_bits {
3806         u8         opcode[0x10];
3807         u8         reserved_0[0x10];
3808
3809         u8         reserved_1[0x10];
3810         u8         op_mod[0x10];
3811
3812         u8         reserved_2[0x20];
3813
3814         u8         reserved_3[0x9];
3815         u8         device_burst_size[0x17];
3816 };
3817
3818 struct mlx5_ifc_rts2rts_qp_out_bits {
3819         u8         status[0x8];
3820         u8         reserved_0[0x18];
3821
3822         u8         syndrome[0x20];
3823
3824         u8         reserved_1[0x40];
3825 };
3826
3827 struct mlx5_ifc_rts2rts_qp_in_bits {
3828         u8         opcode[0x10];
3829         u8         reserved_0[0x10];
3830
3831         u8         reserved_1[0x10];
3832         u8         op_mod[0x10];
3833
3834         u8         reserved_2[0x8];
3835         u8         qpn[0x18];
3836
3837         u8         reserved_3[0x20];
3838
3839         u8         opt_param_mask[0x20];
3840
3841         u8         reserved_4[0x20];
3842
3843         struct mlx5_ifc_qpc_bits qpc;
3844
3845         u8         reserved_5[0x80];
3846 };
3847
3848 struct mlx5_ifc_rtr2rts_qp_out_bits {
3849         u8         status[0x8];
3850         u8         reserved_0[0x18];
3851
3852         u8         syndrome[0x20];
3853
3854         u8         reserved_1[0x40];
3855 };
3856
3857 struct mlx5_ifc_rtr2rts_qp_in_bits {
3858         u8         opcode[0x10];
3859         u8         reserved_0[0x10];
3860
3861         u8         reserved_1[0x10];
3862         u8         op_mod[0x10];
3863
3864         u8         reserved_2[0x8];
3865         u8         qpn[0x18];
3866
3867         u8         reserved_3[0x20];
3868
3869         u8         opt_param_mask[0x20];
3870
3871         u8         reserved_4[0x20];
3872
3873         struct mlx5_ifc_qpc_bits qpc;
3874
3875         u8         reserved_5[0x80];
3876 };
3877
3878 struct mlx5_ifc_rst2init_qp_out_bits {
3879         u8         status[0x8];
3880         u8         reserved_0[0x18];
3881
3882         u8         syndrome[0x20];
3883
3884         u8         reserved_1[0x40];
3885 };
3886
3887 struct mlx5_ifc_rst2init_qp_in_bits {
3888         u8         opcode[0x10];
3889         u8         reserved_0[0x10];
3890
3891         u8         reserved_1[0x10];
3892         u8         op_mod[0x10];
3893
3894         u8         reserved_2[0x8];
3895         u8         qpn[0x18];
3896
3897         u8         reserved_3[0x20];
3898
3899         u8         opt_param_mask[0x20];
3900
3901         u8         reserved_4[0x20];
3902
3903         struct mlx5_ifc_qpc_bits qpc;
3904
3905         u8         reserved_5[0x80];
3906 };
3907
3908 struct mlx5_ifc_resume_qp_out_bits {
3909         u8         status[0x8];
3910         u8         reserved_0[0x18];
3911
3912         u8         syndrome[0x20];
3913
3914         u8         reserved_1[0x40];
3915 };
3916
3917 struct mlx5_ifc_resume_qp_in_bits {
3918         u8         opcode[0x10];
3919         u8         reserved_0[0x10];
3920
3921         u8         reserved_1[0x10];
3922         u8         op_mod[0x10];
3923
3924         u8         reserved_2[0x8];
3925         u8         qpn[0x18];
3926
3927         u8         reserved_3[0x20];
3928 };
3929
3930 struct mlx5_ifc_query_xrc_srq_out_bits {
3931         u8         status[0x8];
3932         u8         reserved_0[0x18];
3933
3934         u8         syndrome[0x20];
3935
3936         u8         reserved_1[0x40];
3937
3938         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3939
3940         u8         reserved_2[0x600];
3941
3942         u8         pas[0][0x40];
3943 };
3944
3945 struct mlx5_ifc_query_xrc_srq_in_bits {
3946         u8         opcode[0x10];
3947         u8         reserved_0[0x10];
3948
3949         u8         reserved_1[0x10];
3950         u8         op_mod[0x10];
3951
3952         u8         reserved_2[0x8];
3953         u8         xrc_srqn[0x18];
3954
3955         u8         reserved_3[0x20];
3956 };
3957
3958 struct mlx5_ifc_query_wol_rol_out_bits {
3959         u8         status[0x8];
3960         u8         reserved_0[0x18];
3961
3962         u8         syndrome[0x20];
3963
3964         u8         reserved_1[0x10];
3965         u8         rol_mode[0x8];
3966         u8         wol_mode[0x8];
3967
3968         u8         reserved_2[0x20];
3969 };
3970
3971 struct mlx5_ifc_query_wol_rol_in_bits {
3972         u8         opcode[0x10];
3973         u8         reserved_0[0x10];
3974
3975         u8         reserved_1[0x10];
3976         u8         op_mod[0x10];
3977
3978         u8         reserved_2[0x40];
3979 };
3980
3981 enum {
3982         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3983         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3984 };
3985
3986 struct mlx5_ifc_query_vport_state_out_bits {
3987         u8         status[0x8];
3988         u8         reserved_0[0x18];
3989
3990         u8         syndrome[0x20];
3991
3992         u8         reserved_1[0x20];
3993
3994         u8         reserved_2[0x18];
3995         u8         admin_state[0x4];
3996         u8         state[0x4];
3997 };
3998
3999 enum {
4000         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4001         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4002         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4003 };
4004
4005 struct mlx5_ifc_query_vport_state_in_bits {
4006         u8         opcode[0x10];
4007         u8         reserved_0[0x10];
4008
4009         u8         reserved_1[0x10];
4010         u8         op_mod[0x10];
4011
4012         u8         other_vport[0x1];
4013         u8         reserved_2[0xf];
4014         u8         vport_number[0x10];
4015
4016         u8         reserved_3[0x20];
4017 };
4018
4019 struct mlx5_ifc_query_vnic_env_out_bits {
4020         u8         status[0x8];
4021         u8         reserved_at_8[0x18];
4022
4023         u8         syndrome[0x20];
4024
4025         u8         reserved_at_40[0x40];
4026
4027         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4028 };
4029
4030 enum {
4031         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4032 };
4033
4034 struct mlx5_ifc_query_vnic_env_in_bits {
4035         u8         opcode[0x10];
4036         u8         reserved_at_10[0x10];
4037
4038         u8         reserved_at_20[0x10];
4039         u8         op_mod[0x10];
4040
4041         u8         other_vport[0x1];
4042         u8         reserved_at_41[0xf];
4043         u8         vport_number[0x10];
4044
4045         u8         reserved_at_60[0x20];
4046 };
4047
4048 struct mlx5_ifc_query_vport_counter_out_bits {
4049         u8         status[0x8];
4050         u8         reserved_0[0x18];
4051
4052         u8         syndrome[0x20];
4053
4054         u8         reserved_1[0x40];
4055
4056         struct mlx5_ifc_traffic_counter_bits received_errors;
4057
4058         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4059
4060         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4061
4062         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4063
4064         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4065
4066         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4067
4068         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4069
4070         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4071
4072         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4073
4074         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4075
4076         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4077
4078         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4079
4080         u8         reserved_2[0xa00];
4081 };
4082
4083 enum {
4084         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4085 };
4086
4087 struct mlx5_ifc_query_vport_counter_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_0[0x10];
4090
4091         u8         reserved_1[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         other_vport[0x1];
4095         u8         reserved_2[0xb];
4096         u8         port_num[0x4];
4097         u8         vport_number[0x10];
4098
4099         u8         reserved_3[0x60];
4100
4101         u8         clear[0x1];
4102         u8         reserved_4[0x1f];
4103
4104         u8         reserved_5[0x20];
4105 };
4106
4107 struct mlx5_ifc_query_tis_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_0[0x18];
4110
4111         u8         syndrome[0x20];
4112
4113         u8         reserved_1[0x40];
4114
4115         struct mlx5_ifc_tisc_bits tis_context;
4116 };
4117
4118 struct mlx5_ifc_query_tis_in_bits {
4119         u8         opcode[0x10];
4120         u8         reserved_0[0x10];
4121
4122         u8         reserved_1[0x10];
4123         u8         op_mod[0x10];
4124
4125         u8         reserved_2[0x8];
4126         u8         tisn[0x18];
4127
4128         u8         reserved_3[0x20];
4129 };
4130
4131 struct mlx5_ifc_query_tir_out_bits {
4132         u8         status[0x8];
4133         u8         reserved_0[0x18];
4134
4135         u8         syndrome[0x20];
4136
4137         u8         reserved_1[0xc0];
4138
4139         struct mlx5_ifc_tirc_bits tir_context;
4140 };
4141
4142 struct mlx5_ifc_query_tir_in_bits {
4143         u8         opcode[0x10];
4144         u8         reserved_0[0x10];
4145
4146         u8         reserved_1[0x10];
4147         u8         op_mod[0x10];
4148
4149         u8         reserved_2[0x8];
4150         u8         tirn[0x18];
4151
4152         u8         reserved_3[0x20];
4153 };
4154
4155 struct mlx5_ifc_query_srq_out_bits {
4156         u8         status[0x8];
4157         u8         reserved_0[0x18];
4158
4159         u8         syndrome[0x20];
4160
4161         u8         reserved_1[0x40];
4162
4163         struct mlx5_ifc_srqc_bits srq_context_entry;
4164
4165         u8         reserved_2[0x600];
4166
4167         u8         pas[0][0x40];
4168 };
4169
4170 struct mlx5_ifc_query_srq_in_bits {
4171         u8         opcode[0x10];
4172         u8         reserved_0[0x10];
4173
4174         u8         reserved_1[0x10];
4175         u8         op_mod[0x10];
4176
4177         u8         reserved_2[0x8];
4178         u8         srqn[0x18];
4179
4180         u8         reserved_3[0x20];
4181 };
4182
4183 struct mlx5_ifc_query_sq_out_bits {
4184         u8         status[0x8];
4185         u8         reserved_0[0x18];
4186
4187         u8         syndrome[0x20];
4188
4189         u8         reserved_1[0xc0];
4190
4191         struct mlx5_ifc_sqc_bits sq_context;
4192 };
4193
4194 struct mlx5_ifc_query_sq_in_bits {
4195         u8         opcode[0x10];
4196         u8         reserved_0[0x10];
4197
4198         u8         reserved_1[0x10];
4199         u8         op_mod[0x10];
4200
4201         u8         reserved_2[0x8];
4202         u8         sqn[0x18];
4203
4204         u8         reserved_3[0x20];
4205 };
4206
4207 struct mlx5_ifc_query_special_contexts_out_bits {
4208         u8         status[0x8];
4209         u8         reserved_0[0x18];
4210
4211         u8         syndrome[0x20];
4212
4213         u8         dump_fill_mkey[0x20];
4214
4215         u8         resd_lkey[0x20];
4216 };
4217
4218 struct mlx5_ifc_query_special_contexts_in_bits {
4219         u8         opcode[0x10];
4220         u8         reserved_0[0x10];
4221
4222         u8         reserved_1[0x10];
4223         u8         op_mod[0x10];
4224
4225         u8         reserved_2[0x40];
4226 };
4227
4228 struct mlx5_ifc_query_scheduling_element_out_bits {
4229         u8         status[0x8];
4230         u8         reserved_at_8[0x18];
4231
4232         u8         syndrome[0x20];
4233
4234         u8         reserved_at_40[0xc0];
4235
4236         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4237
4238         u8         reserved_at_300[0x100];
4239 };
4240
4241 enum {
4242         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4243 };
4244
4245 struct mlx5_ifc_query_scheduling_element_in_bits {
4246         u8         opcode[0x10];
4247         u8         reserved_at_10[0x10];
4248
4249         u8         reserved_at_20[0x10];
4250         u8         op_mod[0x10];
4251
4252         u8         scheduling_hierarchy[0x8];
4253         u8         reserved_at_48[0x18];
4254
4255         u8         scheduling_element_id[0x20];
4256
4257         u8         reserved_at_80[0x180];
4258 };
4259
4260 struct mlx5_ifc_query_rqt_out_bits {
4261         u8         status[0x8];
4262         u8         reserved_0[0x18];
4263
4264         u8         syndrome[0x20];
4265
4266         u8         reserved_1[0xc0];
4267
4268         struct mlx5_ifc_rqtc_bits rqt_context;
4269 };
4270
4271 struct mlx5_ifc_query_rqt_in_bits {
4272         u8         opcode[0x10];
4273         u8         reserved_0[0x10];
4274
4275         u8         reserved_1[0x10];
4276         u8         op_mod[0x10];
4277
4278         u8         reserved_2[0x8];
4279         u8         rqtn[0x18];
4280
4281         u8         reserved_3[0x20];
4282 };
4283
4284 struct mlx5_ifc_query_rq_out_bits {
4285         u8         status[0x8];
4286         u8         reserved_0[0x18];
4287
4288         u8         syndrome[0x20];
4289
4290         u8         reserved_1[0xc0];
4291
4292         struct mlx5_ifc_rqc_bits rq_context;
4293 };
4294
4295 struct mlx5_ifc_query_rq_in_bits {
4296         u8         opcode[0x10];
4297         u8         reserved_0[0x10];
4298
4299         u8         reserved_1[0x10];
4300         u8         op_mod[0x10];
4301
4302         u8         reserved_2[0x8];
4303         u8         rqn[0x18];
4304
4305         u8         reserved_3[0x20];
4306 };
4307
4308 struct mlx5_ifc_query_roce_address_out_bits {
4309         u8         status[0x8];
4310         u8         reserved_0[0x18];
4311
4312         u8         syndrome[0x20];
4313
4314         u8         reserved_1[0x40];
4315
4316         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4317 };
4318
4319 struct mlx5_ifc_query_roce_address_in_bits {
4320         u8         opcode[0x10];
4321         u8         reserved_0[0x10];
4322
4323         u8         reserved_1[0x10];
4324         u8         op_mod[0x10];
4325
4326         u8         roce_address_index[0x10];
4327         u8         reserved_2[0x10];
4328
4329         u8         reserved_3[0x20];
4330 };
4331
4332 struct mlx5_ifc_query_rmp_out_bits {
4333         u8         status[0x8];
4334         u8         reserved_0[0x18];
4335
4336         u8         syndrome[0x20];
4337
4338         u8         reserved_1[0xc0];
4339
4340         struct mlx5_ifc_rmpc_bits rmp_context;
4341 };
4342
4343 struct mlx5_ifc_query_rmp_in_bits {
4344         u8         opcode[0x10];
4345         u8         reserved_0[0x10];
4346
4347         u8         reserved_1[0x10];
4348         u8         op_mod[0x10];
4349
4350         u8         reserved_2[0x8];
4351         u8         rmpn[0x18];
4352
4353         u8         reserved_3[0x20];
4354 };
4355
4356 struct mlx5_ifc_query_rdb_out_bits {
4357         u8         status[0x8];
4358         u8         reserved_0[0x18];
4359
4360         u8         syndrome[0x20];
4361
4362         u8         reserved_1[0x20];
4363
4364         u8         reserved_2[0x18];
4365         u8         rdb_list_size[0x8];
4366
4367         struct mlx5_ifc_rdbc_bits rdb_context[0];
4368 };
4369
4370 struct mlx5_ifc_query_rdb_in_bits {
4371         u8         opcode[0x10];
4372         u8         reserved_0[0x10];
4373
4374         u8         reserved_1[0x10];
4375         u8         op_mod[0x10];
4376
4377         u8         reserved_2[0x8];
4378         u8         qpn[0x18];
4379
4380         u8         reserved_3[0x20];
4381 };
4382
4383 struct mlx5_ifc_query_qp_out_bits {
4384         u8         status[0x8];
4385         u8         reserved_0[0x18];
4386
4387         u8         syndrome[0x20];
4388
4389         u8         reserved_1[0x40];
4390
4391         u8         opt_param_mask[0x20];
4392
4393         u8         reserved_2[0x20];
4394
4395         struct mlx5_ifc_qpc_bits qpc;
4396
4397         u8         reserved_3[0x80];
4398
4399         u8         pas[0][0x40];
4400 };
4401
4402 struct mlx5_ifc_query_qp_in_bits {
4403         u8         opcode[0x10];
4404         u8         reserved_0[0x10];
4405
4406         u8         reserved_1[0x10];
4407         u8         op_mod[0x10];
4408
4409         u8         reserved_2[0x8];
4410         u8         qpn[0x18];
4411
4412         u8         reserved_3[0x20];
4413 };
4414
4415 struct mlx5_ifc_query_q_counter_out_bits {
4416         u8         status[0x8];
4417         u8         reserved_0[0x18];
4418
4419         u8         syndrome[0x20];
4420
4421         u8         reserved_1[0x40];
4422
4423         u8         rx_write_requests[0x20];
4424
4425         u8         reserved_2[0x20];
4426
4427         u8         rx_read_requests[0x20];
4428
4429         u8         reserved_3[0x20];
4430
4431         u8         rx_atomic_requests[0x20];
4432
4433         u8         reserved_4[0x20];
4434
4435         u8         rx_dct_connect[0x20];
4436
4437         u8         reserved_5[0x20];
4438
4439         u8         out_of_buffer[0x20];
4440
4441         u8         reserved_7[0x20];
4442
4443         u8         out_of_sequence[0x20];
4444
4445         u8         reserved_8[0x20];
4446
4447         u8         duplicate_request[0x20];
4448
4449         u8         reserved_9[0x20];
4450
4451         u8         rnr_nak_retry_err[0x20];
4452
4453         u8         reserved_10[0x20];
4454
4455         u8         packet_seq_err[0x20];
4456
4457         u8         reserved_11[0x20];
4458
4459         u8         implied_nak_seq_err[0x20];
4460
4461         u8         reserved_12[0x20];
4462
4463         u8         local_ack_timeout_err[0x20];
4464
4465         u8         reserved_13[0x20];
4466
4467         u8         resp_rnr_nak[0x20];
4468
4469         u8         reserved_14[0x20];
4470
4471         u8         req_rnr_retries_exceeded[0x20];
4472
4473         u8         reserved_15[0x460];
4474 };
4475
4476 struct mlx5_ifc_query_q_counter_in_bits {
4477         u8         opcode[0x10];
4478         u8         reserved_0[0x10];
4479
4480         u8         reserved_1[0x10];
4481         u8         op_mod[0x10];
4482
4483         u8         reserved_2[0x80];
4484
4485         u8         clear[0x1];
4486         u8         reserved_3[0x1f];
4487
4488         u8         reserved_4[0x18];
4489         u8         counter_set_id[0x8];
4490 };
4491
4492 struct mlx5_ifc_query_pages_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_0[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         reserved_1[0x10];
4499         u8         function_id[0x10];
4500
4501         u8         num_pages[0x20];
4502 };
4503
4504 enum {
4505         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4506         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4507         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4508 };
4509
4510 struct mlx5_ifc_query_pages_in_bits {
4511         u8         opcode[0x10];
4512         u8         reserved_0[0x10];
4513
4514         u8         reserved_1[0x10];
4515         u8         op_mod[0x10];
4516
4517         u8         reserved_2[0x10];
4518         u8         function_id[0x10];
4519
4520         u8         reserved_3[0x20];
4521 };
4522
4523 struct mlx5_ifc_query_nic_vport_context_out_bits {
4524         u8         status[0x8];
4525         u8         reserved_0[0x18];
4526
4527         u8         syndrome[0x20];
4528
4529         u8         reserved_1[0x40];
4530
4531         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4532 };
4533
4534 struct mlx5_ifc_query_nic_vport_context_in_bits {
4535         u8         opcode[0x10];
4536         u8         reserved_0[0x10];
4537
4538         u8         reserved_1[0x10];
4539         u8         op_mod[0x10];
4540
4541         u8         other_vport[0x1];
4542         u8         reserved_2[0xf];
4543         u8         vport_number[0x10];
4544
4545         u8         reserved_3[0x5];
4546         u8         allowed_list_type[0x3];
4547         u8         reserved_4[0x18];
4548 };
4549
4550 struct mlx5_ifc_query_mkey_out_bits {
4551         u8         status[0x8];
4552         u8         reserved_0[0x18];
4553
4554         u8         syndrome[0x20];
4555
4556         u8         reserved_1[0x40];
4557
4558         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4559
4560         u8         reserved_2[0x600];
4561
4562         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4563
4564         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4565 };
4566
4567 struct mlx5_ifc_query_mkey_in_bits {
4568         u8         opcode[0x10];
4569         u8         reserved_0[0x10];
4570
4571         u8         reserved_1[0x10];
4572         u8         op_mod[0x10];
4573
4574         u8         reserved_2[0x8];
4575         u8         mkey_index[0x18];
4576
4577         u8         pg_access[0x1];
4578         u8         reserved_3[0x1f];
4579 };
4580
4581 struct mlx5_ifc_query_mad_demux_out_bits {
4582         u8         status[0x8];
4583         u8         reserved_0[0x18];
4584
4585         u8         syndrome[0x20];
4586
4587         u8         reserved_1[0x40];
4588
4589         u8         mad_dumux_parameters_block[0x20];
4590 };
4591
4592 struct mlx5_ifc_query_mad_demux_in_bits {
4593         u8         opcode[0x10];
4594         u8         reserved_0[0x10];
4595
4596         u8         reserved_1[0x10];
4597         u8         op_mod[0x10];
4598
4599         u8         reserved_2[0x40];
4600 };
4601
4602 struct mlx5_ifc_query_l2_table_entry_out_bits {
4603         u8         status[0x8];
4604         u8         reserved_0[0x18];
4605
4606         u8         syndrome[0x20];
4607
4608         u8         reserved_1[0xa0];
4609
4610         u8         reserved_2[0x13];
4611         u8         vlan_valid[0x1];
4612         u8         vlan[0xc];
4613
4614         struct mlx5_ifc_mac_address_layout_bits mac_address;
4615
4616         u8         reserved_3[0xc0];
4617 };
4618
4619 struct mlx5_ifc_query_l2_table_entry_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_0[0x10];
4622
4623         u8         reserved_1[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         reserved_2[0x60];
4627
4628         u8         reserved_3[0x8];
4629         u8         table_index[0x18];
4630
4631         u8         reserved_4[0x140];
4632 };
4633
4634 struct mlx5_ifc_query_issi_out_bits {
4635         u8         status[0x8];
4636         u8         reserved_0[0x18];
4637
4638         u8         syndrome[0x20];
4639
4640         u8         reserved_1[0x10];
4641         u8         current_issi[0x10];
4642
4643         u8         reserved_2[0xa0];
4644
4645         u8         supported_issi_reserved[76][0x8];
4646         u8         supported_issi_dw0[0x20];
4647 };
4648
4649 struct mlx5_ifc_query_issi_in_bits {
4650         u8         opcode[0x10];
4651         u8         reserved_0[0x10];
4652
4653         u8         reserved_1[0x10];
4654         u8         op_mod[0x10];
4655
4656         u8         reserved_2[0x40];
4657 };
4658
4659 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4660         u8         status[0x8];
4661         u8         reserved_0[0x18];
4662
4663         u8         syndrome[0x20];
4664
4665         u8         reserved_1[0x40];
4666
4667         struct mlx5_ifc_pkey_bits pkey[0];
4668 };
4669
4670 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_0[0x10];
4673
4674         u8         reserved_1[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         other_vport[0x1];
4678         u8         reserved_2[0xb];
4679         u8         port_num[0x4];
4680         u8         vport_number[0x10];
4681
4682         u8         reserved_3[0x10];
4683         u8         pkey_index[0x10];
4684 };
4685
4686 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4687         u8         status[0x8];
4688         u8         reserved_0[0x18];
4689
4690         u8         syndrome[0x20];
4691
4692         u8         reserved_1[0x20];
4693
4694         u8         gids_num[0x10];
4695         u8         reserved_2[0x10];
4696
4697         struct mlx5_ifc_array128_auto_bits gid[0];
4698 };
4699
4700 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4701         u8         opcode[0x10];
4702         u8         reserved_0[0x10];
4703
4704         u8         reserved_1[0x10];
4705         u8         op_mod[0x10];
4706
4707         u8         other_vport[0x1];
4708         u8         reserved_2[0xb];
4709         u8         port_num[0x4];
4710         u8         vport_number[0x10];
4711
4712         u8         reserved_3[0x10];
4713         u8         gid_index[0x10];
4714 };
4715
4716 struct mlx5_ifc_query_hca_vport_context_out_bits {
4717         u8         status[0x8];
4718         u8         reserved_0[0x18];
4719
4720         u8         syndrome[0x20];
4721
4722         u8         reserved_1[0x40];
4723
4724         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4725 };
4726
4727 struct mlx5_ifc_query_hca_vport_context_in_bits {
4728         u8         opcode[0x10];
4729         u8         reserved_0[0x10];
4730
4731         u8         reserved_1[0x10];
4732         u8         op_mod[0x10];
4733
4734         u8         other_vport[0x1];
4735         u8         reserved_2[0xb];
4736         u8         port_num[0x4];
4737         u8         vport_number[0x10];
4738
4739         u8         reserved_3[0x20];
4740 };
4741
4742 struct mlx5_ifc_query_hca_cap_out_bits {
4743         u8         status[0x8];
4744         u8         reserved_0[0x18];
4745
4746         u8         syndrome[0x20];
4747
4748         u8         reserved_1[0x40];
4749
4750         union mlx5_ifc_hca_cap_union_bits capability;
4751 };
4752
4753 struct mlx5_ifc_query_hca_cap_in_bits {
4754         u8         opcode[0x10];
4755         u8         reserved_0[0x10];
4756
4757         u8         reserved_1[0x10];
4758         u8         op_mod[0x10];
4759
4760         u8         reserved_2[0x40];
4761 };
4762
4763 struct mlx5_ifc_query_flow_table_out_bits {
4764         u8         status[0x8];
4765         u8         reserved_at_8[0x18];
4766
4767         u8         syndrome[0x20];
4768
4769         u8         reserved_at_40[0x80];
4770
4771         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4772 };
4773
4774 struct mlx5_ifc_query_flow_table_in_bits {
4775         u8         opcode[0x10];
4776         u8         reserved_0[0x10];
4777
4778         u8         reserved_1[0x10];
4779         u8         op_mod[0x10];
4780
4781         u8         other_vport[0x1];
4782         u8         reserved_2[0xf];
4783         u8         vport_number[0x10];
4784
4785         u8         reserved_3[0x20];
4786
4787         u8         table_type[0x8];
4788         u8         reserved_4[0x18];
4789
4790         u8         reserved_5[0x8];
4791         u8         table_id[0x18];
4792
4793         u8         reserved_6[0x140];
4794 };
4795
4796 struct mlx5_ifc_query_fte_out_bits {
4797         u8         status[0x8];
4798         u8         reserved_0[0x18];
4799
4800         u8         syndrome[0x20];
4801
4802         u8         reserved_1[0x1c0];
4803
4804         struct mlx5_ifc_flow_context_bits flow_context;
4805 };
4806
4807 struct mlx5_ifc_query_fte_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_0[0x10];
4810
4811         u8         reserved_1[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         other_vport[0x1];
4815         u8         reserved_2[0xf];
4816         u8         vport_number[0x10];
4817
4818         u8         reserved_3[0x20];
4819
4820         u8         table_type[0x8];
4821         u8         reserved_4[0x18];
4822
4823         u8         reserved_5[0x8];
4824         u8         table_id[0x18];
4825
4826         u8         reserved_6[0x40];
4827
4828         u8         flow_index[0x20];
4829
4830         u8         reserved_7[0xe0];
4831 };
4832
4833 enum {
4834         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4835         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4836         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4837 };
4838
4839 struct mlx5_ifc_query_flow_group_out_bits {
4840         u8         status[0x8];
4841         u8         reserved_0[0x18];
4842
4843         u8         syndrome[0x20];
4844
4845         u8         reserved_1[0xa0];
4846
4847         u8         start_flow_index[0x20];
4848
4849         u8         reserved_2[0x20];
4850
4851         u8         end_flow_index[0x20];
4852
4853         u8         reserved_3[0xa0];
4854
4855         u8         reserved_4[0x18];
4856         u8         match_criteria_enable[0x8];
4857
4858         struct mlx5_ifc_fte_match_param_bits match_criteria;
4859
4860         u8         reserved_5[0xe00];
4861 };
4862
4863 struct mlx5_ifc_query_flow_group_in_bits {
4864         u8         opcode[0x10];
4865         u8         reserved_0[0x10];
4866
4867         u8         reserved_1[0x10];
4868         u8         op_mod[0x10];
4869
4870         u8         other_vport[0x1];
4871         u8         reserved_2[0xf];
4872         u8         vport_number[0x10];
4873
4874         u8         reserved_3[0x20];
4875
4876         u8         table_type[0x8];
4877         u8         reserved_4[0x18];
4878
4879         u8         reserved_5[0x8];
4880         u8         table_id[0x18];
4881
4882         u8         group_id[0x20];
4883
4884         u8         reserved_6[0x120];
4885 };
4886
4887 struct mlx5_ifc_query_flow_counter_out_bits {
4888         u8         status[0x8];
4889         u8         reserved_at_8[0x18];
4890
4891         u8         syndrome[0x20];
4892
4893         u8         reserved_at_40[0x40];
4894
4895         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4896 };
4897
4898 struct mlx5_ifc_query_flow_counter_in_bits {
4899         u8         opcode[0x10];
4900         u8         reserved_at_10[0x10];
4901
4902         u8         reserved_at_20[0x10];
4903         u8         op_mod[0x10];
4904
4905         u8         reserved_at_40[0x80];
4906
4907         u8         clear[0x1];
4908         u8         reserved_at_c1[0xf];
4909         u8         num_of_counters[0x10];
4910
4911         u8         reserved_at_e0[0x10];
4912         u8         flow_counter_id[0x10];
4913 };
4914
4915 struct mlx5_ifc_query_esw_vport_context_out_bits {
4916         u8         status[0x8];
4917         u8         reserved_0[0x18];
4918
4919         u8         syndrome[0x20];
4920
4921         u8         reserved_1[0x40];
4922
4923         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4924 };
4925
4926 struct mlx5_ifc_query_esw_vport_context_in_bits {
4927         u8         opcode[0x10];
4928         u8         reserved_0[0x10];
4929
4930         u8         reserved_1[0x10];
4931         u8         op_mod[0x10];
4932
4933         u8         other_vport[0x1];
4934         u8         reserved_2[0xf];
4935         u8         vport_number[0x10];
4936
4937         u8         reserved_3[0x20];
4938 };
4939
4940 struct mlx5_ifc_query_eq_out_bits {
4941         u8         status[0x8];
4942         u8         reserved_0[0x18];
4943
4944         u8         syndrome[0x20];
4945
4946         u8         reserved_1[0x40];
4947
4948         struct mlx5_ifc_eqc_bits eq_context_entry;
4949
4950         u8         reserved_2[0x40];
4951
4952         u8         event_bitmask[0x40];
4953
4954         u8         reserved_3[0x580];
4955
4956         u8         pas[0][0x40];
4957 };
4958
4959 struct mlx5_ifc_query_eq_in_bits {
4960         u8         opcode[0x10];
4961         u8         reserved_0[0x10];
4962
4963         u8         reserved_1[0x10];
4964         u8         op_mod[0x10];
4965
4966         u8         reserved_2[0x18];
4967         u8         eq_number[0x8];
4968
4969         u8         reserved_3[0x20];
4970 };
4971
4972 struct mlx5_ifc_query_dct_out_bits {
4973         u8         status[0x8];
4974         u8         reserved_0[0x18];
4975
4976         u8         syndrome[0x20];
4977
4978         u8         reserved_1[0x40];
4979
4980         struct mlx5_ifc_dctc_bits dct_context_entry;
4981
4982         u8         reserved_2[0x180];
4983 };
4984
4985 struct mlx5_ifc_query_dct_in_bits {
4986         u8         opcode[0x10];
4987         u8         reserved_0[0x10];
4988
4989         u8         reserved_1[0x10];
4990         u8         op_mod[0x10];
4991
4992         u8         reserved_2[0x8];
4993         u8         dctn[0x18];
4994
4995         u8         reserved_3[0x20];
4996 };
4997
4998 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4999         u8         status[0x8];
5000         u8         reserved_0[0x18];
5001
5002         u8         syndrome[0x20];
5003
5004         u8         enable[0x1];
5005         u8         reserved_1[0x1f];
5006
5007         u8         reserved_2[0x160];
5008
5009         struct mlx5_ifc_cmd_pas_bits pas;
5010 };
5011
5012 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5013         u8         opcode[0x10];
5014         u8         reserved_0[0x10];
5015
5016         u8         reserved_1[0x10];
5017         u8         op_mod[0x10];
5018
5019         u8         reserved_2[0x40];
5020 };
5021
5022 struct mlx5_ifc_query_cq_out_bits {
5023         u8         status[0x8];
5024         u8         reserved_0[0x18];
5025
5026         u8         syndrome[0x20];
5027
5028         u8         reserved_1[0x40];
5029
5030         struct mlx5_ifc_cqc_bits cq_context;
5031
5032         u8         reserved_2[0x600];
5033
5034         u8         pas[0][0x40];
5035 };
5036
5037 struct mlx5_ifc_query_cq_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_0[0x10];
5040
5041         u8         reserved_1[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         reserved_2[0x8];
5045         u8         cqn[0x18];
5046
5047         u8         reserved_3[0x20];
5048 };
5049
5050 struct mlx5_ifc_query_cong_status_out_bits {
5051         u8         status[0x8];
5052         u8         reserved_0[0x18];
5053
5054         u8         syndrome[0x20];
5055
5056         u8         reserved_1[0x20];
5057
5058         u8         enable[0x1];
5059         u8         tag_enable[0x1];
5060         u8         reserved_2[0x1e];
5061 };
5062
5063 struct mlx5_ifc_query_cong_status_in_bits {
5064         u8         opcode[0x10];
5065         u8         reserved_0[0x10];
5066
5067         u8         reserved_1[0x10];
5068         u8         op_mod[0x10];
5069
5070         u8         reserved_2[0x18];
5071         u8         priority[0x4];
5072         u8         cong_protocol[0x4];
5073
5074         u8         reserved_3[0x20];
5075 };
5076
5077 struct mlx5_ifc_query_cong_statistics_out_bits {
5078         u8         status[0x8];
5079         u8         reserved_0[0x18];
5080
5081         u8         syndrome[0x20];
5082
5083         u8         reserved_1[0x40];
5084
5085         u8         rp_cur_flows[0x20];
5086
5087         u8         sum_flows[0x20];
5088
5089         u8         rp_cnp_ignored_high[0x20];
5090
5091         u8         rp_cnp_ignored_low[0x20];
5092
5093         u8         rp_cnp_handled_high[0x20];
5094
5095         u8         rp_cnp_handled_low[0x20];
5096
5097         u8         reserved_2[0x100];
5098
5099         u8         time_stamp_high[0x20];
5100
5101         u8         time_stamp_low[0x20];
5102
5103         u8         accumulators_period[0x20];
5104
5105         u8         np_ecn_marked_roce_packets_high[0x20];
5106
5107         u8         np_ecn_marked_roce_packets_low[0x20];
5108
5109         u8         np_cnp_sent_high[0x20];
5110
5111         u8         np_cnp_sent_low[0x20];
5112
5113         u8         reserved_3[0x560];
5114 };
5115
5116 struct mlx5_ifc_query_cong_statistics_in_bits {
5117         u8         opcode[0x10];
5118         u8         reserved_0[0x10];
5119
5120         u8         reserved_1[0x10];
5121         u8         op_mod[0x10];
5122
5123         u8         clear[0x1];
5124         u8         reserved_2[0x1f];
5125
5126         u8         reserved_3[0x20];
5127 };
5128
5129 struct mlx5_ifc_query_cong_params_out_bits {
5130         u8         status[0x8];
5131         u8         reserved_0[0x18];
5132
5133         u8         syndrome[0x20];
5134
5135         u8         reserved_1[0x40];
5136
5137         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5138 };
5139
5140 struct mlx5_ifc_query_cong_params_in_bits {
5141         u8         opcode[0x10];
5142         u8         reserved_0[0x10];
5143
5144         u8         reserved_1[0x10];
5145         u8         op_mod[0x10];
5146
5147         u8         reserved_2[0x1c];
5148         u8         cong_protocol[0x4];
5149
5150         u8         reserved_3[0x20];
5151 };
5152
5153 struct mlx5_ifc_query_burst_size_out_bits {
5154         u8         status[0x8];
5155         u8         reserved_0[0x18];
5156
5157         u8         syndrome[0x20];
5158
5159         u8         reserved_1[0x20];
5160
5161         u8         reserved_2[0x9];
5162         u8         device_burst_size[0x17];
5163 };
5164
5165 struct mlx5_ifc_query_burst_size_in_bits {
5166         u8         opcode[0x10];
5167         u8         reserved_0[0x10];
5168
5169         u8         reserved_1[0x10];
5170         u8         op_mod[0x10];
5171
5172         u8         reserved_2[0x40];
5173 };
5174
5175 struct mlx5_ifc_query_adapter_out_bits {
5176         u8         status[0x8];
5177         u8         reserved_0[0x18];
5178
5179         u8         syndrome[0x20];
5180
5181         u8         reserved_1[0x40];
5182
5183         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5184 };
5185
5186 struct mlx5_ifc_query_adapter_in_bits {
5187         u8         opcode[0x10];
5188         u8         reserved_0[0x10];
5189
5190         u8         reserved_1[0x10];
5191         u8         op_mod[0x10];
5192
5193         u8         reserved_2[0x40];
5194 };
5195
5196 struct mlx5_ifc_qp_2rst_out_bits {
5197         u8         status[0x8];
5198         u8         reserved_0[0x18];
5199
5200         u8         syndrome[0x20];
5201
5202         u8         reserved_1[0x40];
5203 };
5204
5205 struct mlx5_ifc_qp_2rst_in_bits {
5206         u8         opcode[0x10];
5207         u8         reserved_0[0x10];
5208
5209         u8         reserved_1[0x10];
5210         u8         op_mod[0x10];
5211
5212         u8         reserved_2[0x8];
5213         u8         qpn[0x18];
5214
5215         u8         reserved_3[0x20];
5216 };
5217
5218 struct mlx5_ifc_qp_2err_out_bits {
5219         u8         status[0x8];
5220         u8         reserved_0[0x18];
5221
5222         u8         syndrome[0x20];
5223
5224         u8         reserved_1[0x40];
5225 };
5226
5227 struct mlx5_ifc_qp_2err_in_bits {
5228         u8         opcode[0x10];
5229         u8         reserved_0[0x10];
5230
5231         u8         reserved_1[0x10];
5232         u8         op_mod[0x10];
5233
5234         u8         reserved_2[0x8];
5235         u8         qpn[0x18];
5236
5237         u8         reserved_3[0x20];
5238 };
5239
5240 struct mlx5_ifc_para_vport_element_bits {
5241         u8         reserved_at_0[0xc];
5242         u8         traffic_class[0x4];
5243         u8         qos_para_vport_number[0x10];
5244 };
5245
5246 struct mlx5_ifc_page_fault_resume_out_bits {
5247         u8         status[0x8];
5248         u8         reserved_0[0x18];
5249
5250         u8         syndrome[0x20];
5251
5252         u8         reserved_1[0x40];
5253 };
5254
5255 struct mlx5_ifc_page_fault_resume_in_bits {
5256         u8         opcode[0x10];
5257         u8         reserved_0[0x10];
5258
5259         u8         reserved_1[0x10];
5260         u8         op_mod[0x10];
5261
5262         u8         error[0x1];
5263         u8         reserved_2[0x4];
5264         u8         rdma[0x1];
5265         u8         read_write[0x1];
5266         u8         req_res[0x1];
5267         u8         qpn[0x18];
5268
5269         u8         reserved_3[0x20];
5270 };
5271
5272 struct mlx5_ifc_nop_out_bits {
5273         u8         status[0x8];
5274         u8         reserved_0[0x18];
5275
5276         u8         syndrome[0x20];
5277
5278         u8         reserved_1[0x40];
5279 };
5280
5281 struct mlx5_ifc_nop_in_bits {
5282         u8         opcode[0x10];
5283         u8         reserved_0[0x10];
5284
5285         u8         reserved_1[0x10];
5286         u8         op_mod[0x10];
5287
5288         u8         reserved_2[0x40];
5289 };
5290
5291 struct mlx5_ifc_modify_vport_state_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_0[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_1[0x40];
5298 };
5299
5300 enum {
5301         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5302         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5303         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5304 };
5305
5306 enum {
5307         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5308         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5309         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5310 };
5311
5312 struct mlx5_ifc_modify_vport_state_in_bits {
5313         u8         opcode[0x10];
5314         u8         reserved_0[0x10];
5315
5316         u8         reserved_1[0x10];
5317         u8         op_mod[0x10];
5318
5319         u8         other_vport[0x1];
5320         u8         reserved_2[0xf];
5321         u8         vport_number[0x10];
5322
5323         u8         reserved_3[0x18];
5324         u8         admin_state[0x4];
5325         u8         reserved_4[0x4];
5326 };
5327
5328 struct mlx5_ifc_modify_tis_out_bits {
5329         u8         status[0x8];
5330         u8         reserved_0[0x18];
5331
5332         u8         syndrome[0x20];
5333
5334         u8         reserved_1[0x40];
5335 };
5336
5337 struct mlx5_ifc_modify_tis_bitmask_bits {
5338         u8         reserved_at_0[0x20];
5339
5340         u8         reserved_at_20[0x1d];
5341         u8         lag_tx_port_affinity[0x1];
5342         u8         strict_lag_tx_port_affinity[0x1];
5343         u8         prio[0x1];
5344 };
5345
5346 struct mlx5_ifc_modify_tis_in_bits {
5347         u8         opcode[0x10];
5348         u8         reserved_0[0x10];
5349
5350         u8         reserved_1[0x10];
5351         u8         op_mod[0x10];
5352
5353         u8         reserved_2[0x8];
5354         u8         tisn[0x18];
5355
5356         u8         reserved_3[0x20];
5357
5358         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5359
5360         u8         reserved_4[0x40];
5361
5362         struct mlx5_ifc_tisc_bits ctx;
5363 };
5364
5365 struct mlx5_ifc_modify_tir_out_bits {
5366         u8         status[0x8];
5367         u8         reserved_0[0x18];
5368
5369         u8         syndrome[0x20];
5370
5371         u8         reserved_1[0x40];
5372 };
5373
5374 enum
5375 {
5376         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5377         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5378 };
5379
5380 struct mlx5_ifc_modify_tir_in_bits {
5381         u8         opcode[0x10];
5382         u8         reserved_0[0x10];
5383
5384         u8         reserved_1[0x10];
5385         u8         op_mod[0x10];
5386
5387         u8         reserved_2[0x8];
5388         u8         tirn[0x18];
5389
5390         u8         reserved_3[0x20];
5391
5392         u8         modify_bitmask[0x40];
5393
5394         u8         reserved_4[0x40];
5395
5396         struct mlx5_ifc_tirc_bits tir_context;
5397 };
5398
5399 struct mlx5_ifc_modify_sq_out_bits {
5400         u8         status[0x8];
5401         u8         reserved_0[0x18];
5402
5403         u8         syndrome[0x20];
5404
5405         u8         reserved_1[0x40];
5406 };
5407
5408 struct mlx5_ifc_modify_sq_in_bits {
5409         u8         opcode[0x10];
5410         u8         reserved_0[0x10];
5411
5412         u8         reserved_1[0x10];
5413         u8         op_mod[0x10];
5414
5415         u8         sq_state[0x4];
5416         u8         reserved_2[0x4];
5417         u8         sqn[0x18];
5418
5419         u8         reserved_3[0x20];
5420
5421         u8         modify_bitmask[0x40];
5422
5423         u8         reserved_4[0x40];
5424
5425         struct mlx5_ifc_sqc_bits ctx;
5426 };
5427
5428 struct mlx5_ifc_modify_scheduling_element_out_bits {
5429         u8         status[0x8];
5430         u8         reserved_at_8[0x18];
5431
5432         u8         syndrome[0x20];
5433
5434         u8         reserved_at_40[0x1c0];
5435 };
5436
5437 enum {
5438         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5439 };
5440
5441 enum {
5442         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5443         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5444 };
5445
5446 struct mlx5_ifc_modify_scheduling_element_in_bits {
5447         u8         opcode[0x10];
5448         u8         reserved_at_10[0x10];
5449
5450         u8         reserved_at_20[0x10];
5451         u8         op_mod[0x10];
5452
5453         u8         scheduling_hierarchy[0x8];
5454         u8         reserved_at_48[0x18];
5455
5456         u8         scheduling_element_id[0x20];
5457
5458         u8         reserved_at_80[0x20];
5459
5460         u8         modify_bitmask[0x20];
5461
5462         u8         reserved_at_c0[0x40];
5463
5464         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5465
5466         u8         reserved_at_300[0x100];
5467 };
5468
5469 struct mlx5_ifc_modify_rqt_out_bits {
5470         u8         status[0x8];
5471         u8         reserved_0[0x18];
5472
5473         u8         syndrome[0x20];
5474
5475         u8         reserved_1[0x40];
5476 };
5477
5478 struct mlx5_ifc_modify_rqt_in_bits {
5479         u8         opcode[0x10];
5480         u8         reserved_0[0x10];
5481
5482         u8         reserved_1[0x10];
5483         u8         op_mod[0x10];
5484
5485         u8         reserved_2[0x8];
5486         u8         rqtn[0x18];
5487
5488         u8         reserved_3[0x20];
5489
5490         u8         modify_bitmask[0x40];
5491
5492         u8         reserved_4[0x40];
5493
5494         struct mlx5_ifc_rqtc_bits ctx;
5495 };
5496
5497 struct mlx5_ifc_modify_rq_out_bits {
5498         u8         status[0x8];
5499         u8         reserved_0[0x18];
5500
5501         u8         syndrome[0x20];
5502
5503         u8         reserved_1[0x40];
5504 };
5505
5506 enum {
5507         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5508         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5509 };
5510
5511 struct mlx5_ifc_modify_rq_in_bits {
5512         u8         opcode[0x10];
5513         u8         reserved_0[0x10];
5514
5515         u8         reserved_1[0x10];
5516         u8         op_mod[0x10];
5517
5518         u8         rq_state[0x4];
5519         u8         reserved_2[0x4];
5520         u8         rqn[0x18];
5521
5522         u8         reserved_3[0x20];
5523
5524         u8         modify_bitmask[0x40];
5525
5526         u8         reserved_4[0x40];
5527
5528         struct mlx5_ifc_rqc_bits ctx;
5529 };
5530
5531 struct mlx5_ifc_modify_rmp_out_bits {
5532         u8         status[0x8];
5533         u8         reserved_0[0x18];
5534
5535         u8         syndrome[0x20];
5536
5537         u8         reserved_1[0x40];
5538 };
5539
5540 struct mlx5_ifc_rmp_bitmask_bits {
5541         u8         reserved[0x20];
5542
5543         u8         reserved1[0x1f];
5544         u8         lwm[0x1];
5545 };
5546
5547 struct mlx5_ifc_modify_rmp_in_bits {
5548         u8         opcode[0x10];
5549         u8         reserved_0[0x10];
5550
5551         u8         reserved_1[0x10];
5552         u8         op_mod[0x10];
5553
5554         u8         rmp_state[0x4];
5555         u8         reserved_2[0x4];
5556         u8         rmpn[0x18];
5557
5558         u8         reserved_3[0x20];
5559
5560         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5561
5562         u8         reserved_4[0x40];
5563
5564         struct mlx5_ifc_rmpc_bits ctx;
5565 };
5566
5567 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5568         u8         status[0x8];
5569         u8         reserved_0[0x18];
5570
5571         u8         syndrome[0x20];
5572
5573         u8         reserved_1[0x40];
5574 };
5575
5576 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5577         u8         reserved_0[0x14];
5578         u8         disable_uc_local_lb[0x1];
5579         u8         disable_mc_local_lb[0x1];
5580         u8         node_guid[0x1];
5581         u8         port_guid[0x1];
5582         u8         min_wqe_inline_mode[0x1];
5583         u8         mtu[0x1];
5584         u8         change_event[0x1];
5585         u8         promisc[0x1];
5586         u8         permanent_address[0x1];
5587         u8         addresses_list[0x1];
5588         u8         roce_en[0x1];
5589         u8         reserved_1[0x1];
5590 };
5591
5592 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5593         u8         opcode[0x10];
5594         u8         reserved_0[0x10];
5595
5596         u8         reserved_1[0x10];
5597         u8         op_mod[0x10];
5598
5599         u8         other_vport[0x1];
5600         u8         reserved_2[0xf];
5601         u8         vport_number[0x10];
5602
5603         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5604
5605         u8         reserved_3[0x780];
5606
5607         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5608 };
5609
5610 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5611         u8         status[0x8];
5612         u8         reserved_0[0x18];
5613
5614         u8         syndrome[0x20];
5615
5616         u8         reserved_1[0x40];
5617 };
5618
5619 struct mlx5_ifc_grh_bits {
5620         u8      ip_version[4];
5621         u8      traffic_class[8];
5622         u8      flow_label[20];
5623         u8      payload_length[16];
5624         u8      next_header[8];
5625         u8      hop_limit[8];
5626         u8      sgid[128];
5627         u8      dgid[128];
5628 };
5629
5630 struct mlx5_ifc_bth_bits {
5631         u8      opcode[8];
5632         u8      se[1];
5633         u8      migreq[1];
5634         u8      pad_count[2];
5635         u8      tver[4];
5636         u8      p_key[16];
5637         u8      reserved8[8];
5638         u8      dest_qp[24];
5639         u8      ack_req[1];
5640         u8      reserved7[7];
5641         u8      psn[24];
5642 };
5643
5644 struct mlx5_ifc_aeth_bits {
5645         u8      syndrome[8];
5646         u8      msn[24];
5647 };
5648
5649 struct mlx5_ifc_dceth_bits {
5650         u8      reserved0[8];
5651         u8      session_id[24];
5652         u8      reserved1[8];
5653         u8      dci_dct[24];
5654 };
5655
5656 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5657         u8         opcode[0x10];
5658         u8         reserved_0[0x10];
5659
5660         u8         reserved_1[0x10];
5661         u8         op_mod[0x10];
5662
5663         u8         other_vport[0x1];
5664         u8         reserved_2[0xb];
5665         u8         port_num[0x4];
5666         u8         vport_number[0x10];
5667
5668         u8         reserved_3[0x20];
5669
5670         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5671 };
5672
5673 struct mlx5_ifc_modify_flow_table_out_bits {
5674         u8         status[0x8];
5675         u8         reserved_at_8[0x18];
5676
5677         u8         syndrome[0x20];
5678
5679         u8         reserved_at_40[0x40];
5680 };
5681
5682 enum {
5683         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5684         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5685 };
5686
5687 struct mlx5_ifc_modify_flow_table_in_bits {
5688         u8         opcode[0x10];
5689         u8         reserved_at_10[0x10];
5690
5691         u8         reserved_at_20[0x10];
5692         u8         op_mod[0x10];
5693
5694         u8         other_vport[0x1];
5695         u8         reserved_at_41[0xf];
5696         u8         vport_number[0x10];
5697
5698         u8         reserved_at_60[0x10];
5699         u8         modify_field_select[0x10];
5700
5701         u8         table_type[0x8];
5702         u8         reserved_at_88[0x18];
5703
5704         u8         reserved_at_a0[0x8];
5705         u8         table_id[0x18];
5706
5707         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5708 };
5709
5710 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5711         u8         status[0x8];
5712         u8         reserved_0[0x18];
5713
5714         u8         syndrome[0x20];
5715
5716         u8         reserved_1[0x40];
5717 };
5718
5719 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5720         u8         reserved[0x1c];
5721         u8         vport_cvlan_insert[0x1];
5722         u8         vport_svlan_insert[0x1];
5723         u8         vport_cvlan_strip[0x1];
5724         u8         vport_svlan_strip[0x1];
5725 };
5726
5727 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5728         u8         opcode[0x10];
5729         u8         reserved_0[0x10];
5730
5731         u8         reserved_1[0x10];
5732         u8         op_mod[0x10];
5733
5734         u8         other_vport[0x1];
5735         u8         reserved_2[0xf];
5736         u8         vport_number[0x10];
5737
5738         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5739
5740         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5741 };
5742
5743 struct mlx5_ifc_modify_cq_out_bits {
5744         u8         status[0x8];
5745         u8         reserved_0[0x18];
5746
5747         u8         syndrome[0x20];
5748
5749         u8         reserved_1[0x40];
5750 };
5751
5752 enum {
5753         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5754         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5755 };
5756
5757 struct mlx5_ifc_modify_cq_in_bits {
5758         u8         opcode[0x10];
5759         u8         reserved_0[0x10];
5760
5761         u8         reserved_1[0x10];
5762         u8         op_mod[0x10];
5763
5764         u8         reserved_2[0x8];
5765         u8         cqn[0x18];
5766
5767         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5768
5769         struct mlx5_ifc_cqc_bits cq_context;
5770
5771         u8         reserved_3[0x600];
5772
5773         u8         pas[0][0x40];
5774 };
5775
5776 struct mlx5_ifc_modify_cong_status_out_bits {
5777         u8         status[0x8];
5778         u8         reserved_0[0x18];
5779
5780         u8         syndrome[0x20];
5781
5782         u8         reserved_1[0x40];
5783 };
5784
5785 struct mlx5_ifc_modify_cong_status_in_bits {
5786         u8         opcode[0x10];
5787         u8         reserved_0[0x10];
5788
5789         u8         reserved_1[0x10];
5790         u8         op_mod[0x10];
5791
5792         u8         reserved_2[0x18];
5793         u8         priority[0x4];
5794         u8         cong_protocol[0x4];
5795
5796         u8         enable[0x1];
5797         u8         tag_enable[0x1];
5798         u8         reserved_3[0x1e];
5799 };
5800
5801 struct mlx5_ifc_modify_cong_params_out_bits {
5802         u8         status[0x8];
5803         u8         reserved_0[0x18];
5804
5805         u8         syndrome[0x20];
5806
5807         u8         reserved_1[0x40];
5808 };
5809
5810 struct mlx5_ifc_modify_cong_params_in_bits {
5811         u8         opcode[0x10];
5812         u8         reserved_0[0x10];
5813
5814         u8         reserved_1[0x10];
5815         u8         op_mod[0x10];
5816
5817         u8         reserved_2[0x1c];
5818         u8         cong_protocol[0x4];
5819
5820         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5821
5822         u8         reserved_3[0x80];
5823
5824         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5825 };
5826
5827 struct mlx5_ifc_manage_pages_out_bits {
5828         u8         status[0x8];
5829         u8         reserved_0[0x18];
5830
5831         u8         syndrome[0x20];
5832
5833         u8         output_num_entries[0x20];
5834
5835         u8         reserved_1[0x20];
5836
5837         u8         pas[0][0x40];
5838 };
5839
5840 enum {
5841         MLX5_PAGES_CANT_GIVE                            = 0x0,
5842         MLX5_PAGES_GIVE                                 = 0x1,
5843         MLX5_PAGES_TAKE                                 = 0x2,
5844 };
5845
5846 struct mlx5_ifc_manage_pages_in_bits {
5847         u8         opcode[0x10];
5848         u8         reserved_0[0x10];
5849
5850         u8         reserved_1[0x10];
5851         u8         op_mod[0x10];
5852
5853         u8         reserved_2[0x10];
5854         u8         function_id[0x10];
5855
5856         u8         input_num_entries[0x20];
5857
5858         u8         pas[0][0x40];
5859 };
5860
5861 struct mlx5_ifc_mad_ifc_out_bits {
5862         u8         status[0x8];
5863         u8         reserved_0[0x18];
5864
5865         u8         syndrome[0x20];
5866
5867         u8         reserved_1[0x40];
5868
5869         u8         response_mad_packet[256][0x8];
5870 };
5871
5872 struct mlx5_ifc_mad_ifc_in_bits {
5873         u8         opcode[0x10];
5874         u8         reserved_0[0x10];
5875
5876         u8         reserved_1[0x10];
5877         u8         op_mod[0x10];
5878
5879         u8         remote_lid[0x10];
5880         u8         reserved_2[0x8];
5881         u8         port[0x8];
5882
5883         u8         reserved_3[0x20];
5884
5885         u8         mad[256][0x8];
5886 };
5887
5888 struct mlx5_ifc_init_hca_out_bits {
5889         u8         status[0x8];
5890         u8         reserved_0[0x18];
5891
5892         u8         syndrome[0x20];
5893
5894         u8         reserved_1[0x40];
5895 };
5896
5897 enum {
5898         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5899         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5900 };
5901
5902 struct mlx5_ifc_init_hca_in_bits {
5903         u8         opcode[0x10];
5904         u8         reserved_0[0x10];
5905
5906         u8         reserved_1[0x10];
5907         u8         op_mod[0x10];
5908
5909         u8         reserved_2[0x40];
5910 };
5911
5912 struct mlx5_ifc_init2rtr_qp_out_bits {
5913         u8         status[0x8];
5914         u8         reserved_0[0x18];
5915
5916         u8         syndrome[0x20];
5917
5918         u8         reserved_1[0x40];
5919 };
5920
5921 struct mlx5_ifc_init2rtr_qp_in_bits {
5922         u8         opcode[0x10];
5923         u8         reserved_0[0x10];
5924
5925         u8         reserved_1[0x10];
5926         u8         op_mod[0x10];
5927
5928         u8         reserved_2[0x8];
5929         u8         qpn[0x18];
5930
5931         u8         reserved_3[0x20];
5932
5933         u8         opt_param_mask[0x20];
5934
5935         u8         reserved_4[0x20];
5936
5937         struct mlx5_ifc_qpc_bits qpc;
5938
5939         u8         reserved_5[0x80];
5940 };
5941
5942 struct mlx5_ifc_init2init_qp_out_bits {
5943         u8         status[0x8];
5944         u8         reserved_0[0x18];
5945
5946         u8         syndrome[0x20];
5947
5948         u8         reserved_1[0x40];
5949 };
5950
5951 struct mlx5_ifc_init2init_qp_in_bits {
5952         u8         opcode[0x10];
5953         u8         reserved_0[0x10];
5954
5955         u8         reserved_1[0x10];
5956         u8         op_mod[0x10];
5957
5958         u8         reserved_2[0x8];
5959         u8         qpn[0x18];
5960
5961         u8         reserved_3[0x20];
5962
5963         u8         opt_param_mask[0x20];
5964
5965         u8         reserved_4[0x20];
5966
5967         struct mlx5_ifc_qpc_bits qpc;
5968
5969         u8         reserved_5[0x80];
5970 };
5971
5972 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5973         u8         status[0x8];
5974         u8         reserved_0[0x18];
5975
5976         u8         syndrome[0x20];
5977
5978         u8         reserved_1[0x40];
5979
5980         u8         packet_headers_log[128][0x8];
5981
5982         u8         packet_syndrome[64][0x8];
5983 };
5984
5985 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5986         u8         opcode[0x10];
5987         u8         reserved_0[0x10];
5988
5989         u8         reserved_1[0x10];
5990         u8         op_mod[0x10];
5991
5992         u8         reserved_2[0x40];
5993 };
5994
5995 struct mlx5_ifc_encryption_key_obj_bits {
5996         u8         modify_field_select[0x40];
5997
5998         u8         reserved_at_40[0x14];
5999         u8         key_size[0x4];
6000         u8         reserved_at_58[0x4];
6001         u8         key_type[0x4];
6002
6003         u8         reserved_at_60[0x8];
6004         u8         pd[0x18];
6005
6006         u8         reserved_at_80[0x180];
6007
6008         u8         key[8][0x20];
6009
6010         u8         reserved_at_300[0x500];
6011 };
6012
6013 struct mlx5_ifc_gen_eqe_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_0[0x10];
6016
6017         u8         reserved_1[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_2[0x18];
6021         u8         eq_number[0x8];
6022
6023         u8         reserved_3[0x20];
6024
6025         u8         eqe[64][0x8];
6026 };
6027
6028 struct mlx5_ifc_gen_eq_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_0[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_1[0x40];
6035 };
6036
6037 struct mlx5_ifc_enable_hca_out_bits {
6038         u8         status[0x8];
6039         u8         reserved_0[0x18];
6040
6041         u8         syndrome[0x20];
6042
6043         u8         reserved_1[0x20];
6044 };
6045
6046 struct mlx5_ifc_enable_hca_in_bits {
6047         u8         opcode[0x10];
6048         u8         reserved_0[0x10];
6049
6050         u8         reserved_1[0x10];
6051         u8         op_mod[0x10];
6052
6053         u8         reserved_2[0x10];
6054         u8         function_id[0x10];
6055
6056         u8         reserved_3[0x20];
6057 };
6058
6059 struct mlx5_ifc_drain_dct_out_bits {
6060         u8         status[0x8];
6061         u8         reserved_0[0x18];
6062
6063         u8         syndrome[0x20];
6064
6065         u8         reserved_1[0x40];
6066 };
6067
6068 struct mlx5_ifc_drain_dct_in_bits {
6069         u8         opcode[0x10];
6070         u8         reserved_0[0x10];
6071
6072         u8         reserved_1[0x10];
6073         u8         op_mod[0x10];
6074
6075         u8         reserved_2[0x8];
6076         u8         dctn[0x18];
6077
6078         u8         reserved_3[0x20];
6079 };
6080
6081 struct mlx5_ifc_disable_hca_out_bits {
6082         u8         status[0x8];
6083         u8         reserved_0[0x18];
6084
6085         u8         syndrome[0x20];
6086
6087         u8         reserved_1[0x20];
6088 };
6089
6090 struct mlx5_ifc_disable_hca_in_bits {
6091         u8         opcode[0x10];
6092         u8         reserved_0[0x10];
6093
6094         u8         reserved_1[0x10];
6095         u8         op_mod[0x10];
6096
6097         u8         reserved_2[0x10];
6098         u8         function_id[0x10];
6099
6100         u8         reserved_3[0x20];
6101 };
6102
6103 struct mlx5_ifc_detach_from_mcg_out_bits {
6104         u8         status[0x8];
6105         u8         reserved_0[0x18];
6106
6107         u8         syndrome[0x20];
6108
6109         u8         reserved_1[0x40];
6110 };
6111
6112 struct mlx5_ifc_detach_from_mcg_in_bits {
6113         u8         opcode[0x10];
6114         u8         reserved_0[0x10];
6115
6116         u8         reserved_1[0x10];
6117         u8         op_mod[0x10];
6118
6119         u8         reserved_2[0x8];
6120         u8         qpn[0x18];
6121
6122         u8         reserved_3[0x20];
6123
6124         u8         multicast_gid[16][0x8];
6125 };
6126
6127 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6128         u8         status[0x8];
6129         u8         reserved_0[0x18];
6130
6131         u8         syndrome[0x20];
6132
6133         u8         reserved_1[0x40];
6134 };
6135
6136 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6137         u8         opcode[0x10];
6138         u8         reserved_0[0x10];
6139
6140         u8         reserved_1[0x10];
6141         u8         op_mod[0x10];
6142
6143         u8         reserved_2[0x8];
6144         u8         xrc_srqn[0x18];
6145
6146         u8         reserved_3[0x20];
6147 };
6148
6149 struct mlx5_ifc_destroy_tis_out_bits {
6150         u8         status[0x8];
6151         u8         reserved_0[0x18];
6152
6153         u8         syndrome[0x20];
6154
6155         u8         reserved_1[0x40];
6156 };
6157
6158 struct mlx5_ifc_destroy_tis_in_bits {
6159         u8         opcode[0x10];
6160         u8         reserved_0[0x10];
6161
6162         u8         reserved_1[0x10];
6163         u8         op_mod[0x10];
6164
6165         u8         reserved_2[0x8];
6166         u8         tisn[0x18];
6167
6168         u8         reserved_3[0x20];
6169 };
6170
6171 struct mlx5_ifc_destroy_tir_out_bits {
6172         u8         status[0x8];
6173         u8         reserved_0[0x18];
6174
6175         u8         syndrome[0x20];
6176
6177         u8         reserved_1[0x40];
6178 };
6179
6180 struct mlx5_ifc_destroy_tir_in_bits {
6181         u8         opcode[0x10];
6182         u8         reserved_0[0x10];
6183
6184         u8         reserved_1[0x10];
6185         u8         op_mod[0x10];
6186
6187         u8         reserved_2[0x8];
6188         u8         tirn[0x18];
6189
6190         u8         reserved_3[0x20];
6191 };
6192
6193 struct mlx5_ifc_destroy_srq_out_bits {
6194         u8         status[0x8];
6195         u8         reserved_0[0x18];
6196
6197         u8         syndrome[0x20];
6198
6199         u8         reserved_1[0x40];
6200 };
6201
6202 struct mlx5_ifc_destroy_srq_in_bits {
6203         u8         opcode[0x10];
6204         u8         reserved_0[0x10];
6205
6206         u8         reserved_1[0x10];
6207         u8         op_mod[0x10];
6208
6209         u8         reserved_2[0x8];
6210         u8         srqn[0x18];
6211
6212         u8         reserved_3[0x20];
6213 };
6214
6215 struct mlx5_ifc_destroy_sq_out_bits {
6216         u8         status[0x8];
6217         u8         reserved_0[0x18];
6218
6219         u8         syndrome[0x20];
6220
6221         u8         reserved_1[0x40];
6222 };
6223
6224 struct mlx5_ifc_destroy_sq_in_bits {
6225         u8         opcode[0x10];
6226         u8         reserved_0[0x10];
6227
6228         u8         reserved_1[0x10];
6229         u8         op_mod[0x10];
6230
6231         u8         reserved_2[0x8];
6232         u8         sqn[0x18];
6233
6234         u8         reserved_3[0x20];
6235 };
6236
6237 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6238         u8         status[0x8];
6239         u8         reserved_at_8[0x18];
6240
6241         u8         syndrome[0x20];
6242
6243         u8         reserved_at_40[0x1c0];
6244 };
6245
6246 enum {
6247         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6248 };
6249
6250 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6251         u8         opcode[0x10];
6252         u8         reserved_at_10[0x10];
6253
6254         u8         reserved_at_20[0x10];
6255         u8         op_mod[0x10];
6256
6257         u8         scheduling_hierarchy[0x8];
6258         u8         reserved_at_48[0x18];
6259
6260         u8         scheduling_element_id[0x20];
6261
6262         u8         reserved_at_80[0x180];
6263 };
6264
6265 struct mlx5_ifc_destroy_rqt_out_bits {
6266         u8         status[0x8];
6267         u8         reserved_0[0x18];
6268
6269         u8         syndrome[0x20];
6270
6271         u8         reserved_1[0x40];
6272 };
6273
6274 struct mlx5_ifc_destroy_rqt_in_bits {
6275         u8         opcode[0x10];
6276         u8         reserved_0[0x10];
6277
6278         u8         reserved_1[0x10];
6279         u8         op_mod[0x10];
6280
6281         u8         reserved_2[0x8];
6282         u8         rqtn[0x18];
6283
6284         u8         reserved_3[0x20];
6285 };
6286
6287 struct mlx5_ifc_destroy_rq_out_bits {
6288         u8         status[0x8];
6289         u8         reserved_0[0x18];
6290
6291         u8         syndrome[0x20];
6292
6293         u8         reserved_1[0x40];
6294 };
6295
6296 struct mlx5_ifc_destroy_rq_in_bits {
6297         u8         opcode[0x10];
6298         u8         reserved_0[0x10];
6299
6300         u8         reserved_1[0x10];
6301         u8         op_mod[0x10];
6302
6303         u8         reserved_2[0x8];
6304         u8         rqn[0x18];
6305
6306         u8         reserved_3[0x20];
6307 };
6308
6309 struct mlx5_ifc_destroy_rmp_out_bits {
6310         u8         status[0x8];
6311         u8         reserved_0[0x18];
6312
6313         u8         syndrome[0x20];
6314
6315         u8         reserved_1[0x40];
6316 };
6317
6318 struct mlx5_ifc_destroy_rmp_in_bits {
6319         u8         opcode[0x10];
6320         u8         reserved_0[0x10];
6321
6322         u8         reserved_1[0x10];
6323         u8         op_mod[0x10];
6324
6325         u8         reserved_2[0x8];
6326         u8         rmpn[0x18];
6327
6328         u8         reserved_3[0x20];
6329 };
6330
6331 struct mlx5_ifc_destroy_qp_out_bits {
6332         u8         status[0x8];
6333         u8         reserved_0[0x18];
6334
6335         u8         syndrome[0x20];
6336
6337         u8         reserved_1[0x40];
6338 };
6339
6340 struct mlx5_ifc_destroy_qp_in_bits {
6341         u8         opcode[0x10];
6342         u8         reserved_0[0x10];
6343
6344         u8         reserved_1[0x10];
6345         u8         op_mod[0x10];
6346
6347         u8         reserved_2[0x8];
6348         u8         qpn[0x18];
6349
6350         u8         reserved_3[0x20];
6351 };
6352
6353 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6354         u8         status[0x8];
6355         u8         reserved_at_8[0x18];
6356
6357         u8         syndrome[0x20];
6358
6359         u8         reserved_at_40[0x1c0];
6360 };
6361
6362 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6363         u8         opcode[0x10];
6364         u8         reserved_at_10[0x10];
6365
6366         u8         reserved_at_20[0x10];
6367         u8         op_mod[0x10];
6368
6369         u8         reserved_at_40[0x20];
6370
6371         u8         reserved_at_60[0x10];
6372         u8         qos_para_vport_number[0x10];
6373
6374         u8         reserved_at_80[0x180];
6375 };
6376
6377 struct mlx5_ifc_destroy_psv_out_bits {
6378         u8         status[0x8];
6379         u8         reserved_0[0x18];
6380
6381         u8         syndrome[0x20];
6382
6383         u8         reserved_1[0x40];
6384 };
6385
6386 struct mlx5_ifc_destroy_psv_in_bits {
6387         u8         opcode[0x10];
6388         u8         reserved_0[0x10];
6389
6390         u8         reserved_1[0x10];
6391         u8         op_mod[0x10];
6392
6393         u8         reserved_2[0x8];
6394         u8         psvn[0x18];
6395
6396         u8         reserved_3[0x20];
6397 };
6398
6399 struct mlx5_ifc_destroy_mkey_out_bits {
6400         u8         status[0x8];
6401         u8         reserved_0[0x18];
6402
6403         u8         syndrome[0x20];
6404
6405         u8         reserved_1[0x40];
6406 };
6407
6408 struct mlx5_ifc_destroy_mkey_in_bits {
6409         u8         opcode[0x10];
6410         u8         reserved_0[0x10];
6411
6412         u8         reserved_1[0x10];
6413         u8         op_mod[0x10];
6414
6415         u8         reserved_2[0x8];
6416         u8         mkey_index[0x18];
6417
6418         u8         reserved_3[0x20];
6419 };
6420
6421 struct mlx5_ifc_destroy_flow_table_out_bits {
6422         u8         status[0x8];
6423         u8         reserved_0[0x18];
6424
6425         u8         syndrome[0x20];
6426
6427         u8         reserved_1[0x40];
6428 };
6429
6430 struct mlx5_ifc_destroy_flow_table_in_bits {
6431         u8         opcode[0x10];
6432         u8         reserved_0[0x10];
6433
6434         u8         reserved_1[0x10];
6435         u8         op_mod[0x10];
6436
6437         u8         other_vport[0x1];
6438         u8         reserved_2[0xf];
6439         u8         vport_number[0x10];
6440
6441         u8         reserved_3[0x20];
6442
6443         u8         table_type[0x8];
6444         u8         reserved_4[0x18];
6445
6446         u8         reserved_5[0x8];
6447         u8         table_id[0x18];
6448
6449         u8         reserved_6[0x140];
6450 };
6451
6452 struct mlx5_ifc_destroy_flow_group_out_bits {
6453         u8         status[0x8];
6454         u8         reserved_0[0x18];
6455
6456         u8         syndrome[0x20];
6457
6458         u8         reserved_1[0x40];
6459 };
6460
6461 struct mlx5_ifc_destroy_flow_group_in_bits {
6462         u8         opcode[0x10];
6463         u8         reserved_0[0x10];
6464
6465         u8         reserved_1[0x10];
6466         u8         op_mod[0x10];
6467
6468         u8         other_vport[0x1];
6469         u8         reserved_2[0xf];
6470         u8         vport_number[0x10];
6471
6472         u8         reserved_3[0x20];
6473
6474         u8         table_type[0x8];
6475         u8         reserved_4[0x18];
6476
6477         u8         reserved_5[0x8];
6478         u8         table_id[0x18];
6479
6480         u8         group_id[0x20];
6481
6482         u8         reserved_6[0x120];
6483 };
6484
6485 struct mlx5_ifc_destroy_encryption_key_out_bits {
6486         u8         status[0x8];
6487         u8         reserved_at_8[0x18];
6488
6489         u8         syndrome[0x20];
6490
6491         u8         reserved_at_40[0x40];
6492 };
6493
6494 struct mlx5_ifc_destroy_encryption_key_in_bits {
6495         u8         opcode[0x10];
6496         u8         reserved_at_10[0x10];
6497
6498         u8         reserved_at_20[0x10];
6499         u8         obj_type[0x10];
6500
6501         u8         obj_id[0x20];
6502
6503         u8         reserved_at_60[0x20];
6504 };
6505
6506 struct mlx5_ifc_destroy_eq_out_bits {
6507         u8         status[0x8];
6508         u8         reserved_0[0x18];
6509
6510         u8         syndrome[0x20];
6511
6512         u8         reserved_1[0x40];
6513 };
6514
6515 struct mlx5_ifc_destroy_eq_in_bits {
6516         u8         opcode[0x10];
6517         u8         reserved_0[0x10];
6518
6519         u8         reserved_1[0x10];
6520         u8         op_mod[0x10];
6521
6522         u8         reserved_2[0x18];
6523         u8         eq_number[0x8];
6524
6525         u8         reserved_3[0x20];
6526 };
6527
6528 struct mlx5_ifc_destroy_dct_out_bits {
6529         u8         status[0x8];
6530         u8         reserved_0[0x18];
6531
6532         u8         syndrome[0x20];
6533
6534         u8         reserved_1[0x40];
6535 };
6536
6537 struct mlx5_ifc_destroy_dct_in_bits {
6538         u8         opcode[0x10];
6539         u8         reserved_0[0x10];
6540
6541         u8         reserved_1[0x10];
6542         u8         op_mod[0x10];
6543
6544         u8         reserved_2[0x8];
6545         u8         dctn[0x18];
6546
6547         u8         reserved_3[0x20];
6548 };
6549
6550 struct mlx5_ifc_destroy_cq_out_bits {
6551         u8         status[0x8];
6552         u8         reserved_0[0x18];
6553
6554         u8         syndrome[0x20];
6555
6556         u8         reserved_1[0x40];
6557 };
6558
6559 struct mlx5_ifc_destroy_cq_in_bits {
6560         u8         opcode[0x10];
6561         u8         reserved_0[0x10];
6562
6563         u8         reserved_1[0x10];
6564         u8         op_mod[0x10];
6565
6566         u8         reserved_2[0x8];
6567         u8         cqn[0x18];
6568
6569         u8         reserved_3[0x20];
6570 };
6571
6572 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6573         u8         status[0x8];
6574         u8         reserved_0[0x18];
6575
6576         u8         syndrome[0x20];
6577
6578         u8         reserved_1[0x40];
6579 };
6580
6581 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6582         u8         opcode[0x10];
6583         u8         reserved_0[0x10];
6584
6585         u8         reserved_1[0x10];
6586         u8         op_mod[0x10];
6587
6588         u8         reserved_2[0x20];
6589
6590         u8         reserved_3[0x10];
6591         u8         vxlan_udp_port[0x10];
6592 };
6593
6594 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6595         u8         status[0x8];
6596         u8         reserved_0[0x18];
6597
6598         u8         syndrome[0x20];
6599
6600         u8         reserved_1[0x40];
6601 };
6602
6603 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6604         u8         opcode[0x10];
6605         u8         reserved_0[0x10];
6606
6607         u8         reserved_1[0x10];
6608         u8         op_mod[0x10];
6609
6610         u8         reserved_2[0x60];
6611
6612         u8         reserved_3[0x8];
6613         u8         table_index[0x18];
6614
6615         u8         reserved_4[0x140];
6616 };
6617
6618 struct mlx5_ifc_delete_fte_out_bits {
6619         u8         status[0x8];
6620         u8         reserved_0[0x18];
6621
6622         u8         syndrome[0x20];
6623
6624         u8         reserved_1[0x40];
6625 };
6626
6627 struct mlx5_ifc_delete_fte_in_bits {
6628         u8         opcode[0x10];
6629         u8         reserved_0[0x10];
6630
6631         u8         reserved_1[0x10];
6632         u8         op_mod[0x10];
6633
6634         u8         other_vport[0x1];
6635         u8         reserved_2[0xf];
6636         u8         vport_number[0x10];
6637
6638         u8         reserved_3[0x20];
6639
6640         u8         table_type[0x8];
6641         u8         reserved_4[0x18];
6642
6643         u8         reserved_5[0x8];
6644         u8         table_id[0x18];
6645
6646         u8         reserved_6[0x40];
6647
6648         u8         flow_index[0x20];
6649
6650         u8         reserved_7[0xe0];
6651 };
6652
6653 struct mlx5_ifc_dealloc_xrcd_out_bits {
6654         u8         status[0x8];
6655         u8         reserved_0[0x18];
6656
6657         u8         syndrome[0x20];
6658
6659         u8         reserved_1[0x40];
6660 };
6661
6662 struct mlx5_ifc_dealloc_xrcd_in_bits {
6663         u8         opcode[0x10];
6664         u8         reserved_0[0x10];
6665
6666         u8         reserved_1[0x10];
6667         u8         op_mod[0x10];
6668
6669         u8         reserved_2[0x8];
6670         u8         xrcd[0x18];
6671
6672         u8         reserved_3[0x20];
6673 };
6674
6675 struct mlx5_ifc_dealloc_uar_out_bits {
6676         u8         status[0x8];
6677         u8         reserved_0[0x18];
6678
6679         u8         syndrome[0x20];
6680
6681         u8         reserved_1[0x40];
6682 };
6683
6684 struct mlx5_ifc_dealloc_uar_in_bits {
6685         u8         opcode[0x10];
6686         u8         reserved_0[0x10];
6687
6688         u8         reserved_1[0x10];
6689         u8         op_mod[0x10];
6690
6691         u8         reserved_2[0x8];
6692         u8         uar[0x18];
6693
6694         u8         reserved_3[0x20];
6695 };
6696
6697 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6698         u8         status[0x8];
6699         u8         reserved_0[0x18];
6700
6701         u8         syndrome[0x20];
6702
6703         u8         reserved_1[0x40];
6704 };
6705
6706 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6707         u8         opcode[0x10];
6708         u8         reserved_0[0x10];
6709
6710         u8         reserved_1[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         reserved_2[0x8];
6714         u8         transport_domain[0x18];
6715
6716         u8         reserved_3[0x20];
6717 };
6718
6719 struct mlx5_ifc_dealloc_q_counter_out_bits {
6720         u8         status[0x8];
6721         u8         reserved_0[0x18];
6722
6723         u8         syndrome[0x20];
6724
6725         u8         reserved_1[0x40];
6726 };
6727
6728 struct mlx5_ifc_counter_id_bits {
6729         u8         reserved[0x10];
6730         u8         counter_id[0x10];
6731 };
6732
6733 struct mlx5_ifc_diagnostic_params_context_bits {
6734         u8         num_of_counters[0x10];
6735         u8         reserved_2[0x8];
6736         u8         log_num_of_samples[0x8];
6737
6738         u8         single[0x1];
6739         u8         repetitive[0x1];
6740         u8         sync[0x1];
6741         u8         clear[0x1];
6742         u8         on_demand[0x1];
6743         u8         enable[0x1];
6744         u8         reserved_3[0x12];
6745         u8         log_sample_period[0x8];
6746
6747         u8         reserved_4[0x80];
6748
6749         struct mlx5_ifc_counter_id_bits counter_id[0];
6750 };
6751
6752 struct mlx5_ifc_set_diagnostic_params_in_bits {
6753         u8         opcode[0x10];
6754         u8         reserved_0[0x10];
6755
6756         u8         reserved_1[0x10];
6757         u8         op_mod[0x10];
6758
6759         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6760 };
6761
6762 struct mlx5_ifc_set_diagnostic_params_out_bits {
6763         u8         status[0x8];
6764         u8         reserved_0[0x18];
6765
6766         u8         syndrome[0x20];
6767
6768         u8         reserved_1[0x40];
6769 };
6770
6771 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6772         u8         opcode[0x10];
6773         u8         reserved_0[0x10];
6774
6775         u8         reserved_1[0x10];
6776         u8         op_mod[0x10];
6777
6778         u8         num_of_samples[0x10];
6779         u8         sample_index[0x10];
6780
6781         u8         reserved_2[0x20];
6782 };
6783
6784 struct mlx5_ifc_diagnostic_counter_bits {
6785         u8         counter_id[0x10];
6786         u8         sample_id[0x10];
6787
6788         u8         time_stamp_31_0[0x20];
6789
6790         u8         counter_value_h[0x20];
6791
6792         u8         counter_value_l[0x20];
6793 };
6794
6795 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6796         u8         status[0x8];
6797         u8         reserved_0[0x18];
6798
6799         u8         syndrome[0x20];
6800
6801         u8         reserved_1[0x40];
6802
6803         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6804 };
6805
6806 struct mlx5_ifc_dealloc_q_counter_in_bits {
6807         u8         opcode[0x10];
6808         u8         reserved_0[0x10];
6809
6810         u8         reserved_1[0x10];
6811         u8         op_mod[0x10];
6812
6813         u8         reserved_2[0x18];
6814         u8         counter_set_id[0x8];
6815
6816         u8         reserved_3[0x20];
6817 };
6818
6819 struct mlx5_ifc_dealloc_pd_out_bits {
6820         u8         status[0x8];
6821         u8         reserved_0[0x18];
6822
6823         u8         syndrome[0x20];
6824
6825         u8         reserved_1[0x40];
6826 };
6827
6828 struct mlx5_ifc_dealloc_pd_in_bits {
6829         u8         opcode[0x10];
6830         u8         reserved_0[0x10];
6831
6832         u8         reserved_1[0x10];
6833         u8         op_mod[0x10];
6834
6835         u8         reserved_2[0x8];
6836         u8         pd[0x18];
6837
6838         u8         reserved_3[0x20];
6839 };
6840
6841 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6842         u8         status[0x8];
6843         u8         reserved_0[0x18];
6844
6845         u8         syndrome[0x20];
6846
6847         u8         reserved_1[0x40];
6848 };
6849
6850 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6851         u8         opcode[0x10];
6852         u8         reserved_0[0x10];
6853
6854         u8         reserved_1[0x10];
6855         u8         op_mod[0x10];
6856
6857         u8         reserved_2[0x10];
6858         u8         flow_counter_id[0x10];
6859
6860         u8         reserved_3[0x20];
6861 };
6862
6863 struct mlx5_ifc_deactivate_tracer_out_bits {
6864         u8         status[0x8];
6865         u8         reserved_0[0x18];
6866
6867         u8         syndrome[0x20];
6868
6869         u8         reserved_1[0x40];
6870 };
6871
6872 struct mlx5_ifc_deactivate_tracer_in_bits {
6873         u8         opcode[0x10];
6874         u8         reserved_0[0x10];
6875
6876         u8         reserved_1[0x10];
6877         u8         op_mod[0x10];
6878
6879         u8         mkey[0x20];
6880
6881         u8         reserved_2[0x20];
6882 };
6883
6884 struct mlx5_ifc_create_xrc_srq_out_bits {
6885         u8         status[0x8];
6886         u8         reserved_0[0x18];
6887
6888         u8         syndrome[0x20];
6889
6890         u8         reserved_1[0x8];
6891         u8         xrc_srqn[0x18];
6892
6893         u8         reserved_2[0x20];
6894 };
6895
6896 struct mlx5_ifc_create_xrc_srq_in_bits {
6897         u8         opcode[0x10];
6898         u8         reserved_0[0x10];
6899
6900         u8         reserved_1[0x10];
6901         u8         op_mod[0x10];
6902
6903         u8         reserved_2[0x40];
6904
6905         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6906
6907         u8         reserved_3[0x600];
6908
6909         u8         pas[0][0x40];
6910 };
6911
6912 struct mlx5_ifc_create_tis_out_bits {
6913         u8         status[0x8];
6914         u8         reserved_0[0x18];
6915
6916         u8         syndrome[0x20];
6917
6918         u8         reserved_1[0x8];
6919         u8         tisn[0x18];
6920
6921         u8         reserved_2[0x20];
6922 };
6923
6924 struct mlx5_ifc_create_tis_in_bits {
6925         u8         opcode[0x10];
6926         u8         reserved_0[0x10];
6927
6928         u8         reserved_1[0x10];
6929         u8         op_mod[0x10];
6930
6931         u8         reserved_2[0xc0];
6932
6933         struct mlx5_ifc_tisc_bits ctx;
6934 };
6935
6936 struct mlx5_ifc_create_tir_out_bits {
6937         u8         status[0x8];
6938         u8         reserved_0[0x18];
6939
6940         u8         syndrome[0x20];
6941
6942         u8         reserved_1[0x8];
6943         u8         tirn[0x18];
6944
6945         u8         reserved_2[0x20];
6946 };
6947
6948 struct mlx5_ifc_create_tir_in_bits {
6949         u8         opcode[0x10];
6950         u8         reserved_0[0x10];
6951
6952         u8         reserved_1[0x10];
6953         u8         op_mod[0x10];
6954
6955         u8         reserved_2[0xc0];
6956
6957         struct mlx5_ifc_tirc_bits tir_context;
6958 };
6959
6960 struct mlx5_ifc_create_srq_out_bits {
6961         u8         status[0x8];
6962         u8         reserved_0[0x18];
6963
6964         u8         syndrome[0x20];
6965
6966         u8         reserved_1[0x8];
6967         u8         srqn[0x18];
6968
6969         u8         reserved_2[0x20];
6970 };
6971
6972 struct mlx5_ifc_create_srq_in_bits {
6973         u8         opcode[0x10];
6974         u8         reserved_0[0x10];
6975
6976         u8         reserved_1[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_2[0x40];
6980
6981         struct mlx5_ifc_srqc_bits srq_context_entry;
6982
6983         u8         reserved_3[0x600];
6984
6985         u8         pas[0][0x40];
6986 };
6987
6988 struct mlx5_ifc_create_sq_out_bits {
6989         u8         status[0x8];
6990         u8         reserved_0[0x18];
6991
6992         u8         syndrome[0x20];
6993
6994         u8         reserved_1[0x8];
6995         u8         sqn[0x18];
6996
6997         u8         reserved_2[0x20];
6998 };
6999
7000 struct mlx5_ifc_create_sq_in_bits {
7001         u8         opcode[0x10];
7002         u8         reserved_0[0x10];
7003
7004         u8         reserved_1[0x10];
7005         u8         op_mod[0x10];
7006
7007         u8         reserved_2[0xc0];
7008
7009         struct mlx5_ifc_sqc_bits ctx;
7010 };
7011
7012 struct mlx5_ifc_create_scheduling_element_out_bits {
7013         u8         status[0x8];
7014         u8         reserved_at_8[0x18];
7015
7016         u8         syndrome[0x20];
7017
7018         u8         reserved_at_40[0x40];
7019
7020         u8         scheduling_element_id[0x20];
7021
7022         u8         reserved_at_a0[0x160];
7023 };
7024
7025 enum {
7026         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7027 };
7028
7029 struct mlx5_ifc_create_scheduling_element_in_bits {
7030         u8         opcode[0x10];
7031         u8         reserved_at_10[0x10];
7032
7033         u8         reserved_at_20[0x10];
7034         u8         op_mod[0x10];
7035
7036         u8         scheduling_hierarchy[0x8];
7037         u8         reserved_at_48[0x18];
7038
7039         u8         reserved_at_60[0xa0];
7040
7041         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7042
7043         u8         reserved_at_300[0x100];
7044 };
7045
7046 struct mlx5_ifc_create_rqt_out_bits {
7047         u8         status[0x8];
7048         u8         reserved_0[0x18];
7049
7050         u8         syndrome[0x20];
7051
7052         u8         reserved_1[0x8];
7053         u8         rqtn[0x18];
7054
7055         u8         reserved_2[0x20];
7056 };
7057
7058 struct mlx5_ifc_create_rqt_in_bits {
7059         u8         opcode[0x10];
7060         u8         reserved_0[0x10];
7061
7062         u8         reserved_1[0x10];
7063         u8         op_mod[0x10];
7064
7065         u8         reserved_2[0xc0];
7066
7067         struct mlx5_ifc_rqtc_bits rqt_context;
7068 };
7069
7070 struct mlx5_ifc_create_rq_out_bits {
7071         u8         status[0x8];
7072         u8         reserved_0[0x18];
7073
7074         u8         syndrome[0x20];
7075
7076         u8         reserved_1[0x8];
7077         u8         rqn[0x18];
7078
7079         u8         reserved_2[0x20];
7080 };
7081
7082 struct mlx5_ifc_create_rq_in_bits {
7083         u8         opcode[0x10];
7084         u8         reserved_0[0x10];
7085
7086         u8         reserved_1[0x10];
7087         u8         op_mod[0x10];
7088
7089         u8         reserved_2[0xc0];
7090
7091         struct mlx5_ifc_rqc_bits ctx;
7092 };
7093
7094 struct mlx5_ifc_create_rmp_out_bits {
7095         u8         status[0x8];
7096         u8         reserved_0[0x18];
7097
7098         u8         syndrome[0x20];
7099
7100         u8         reserved_1[0x8];
7101         u8         rmpn[0x18];
7102
7103         u8         reserved_2[0x20];
7104 };
7105
7106 struct mlx5_ifc_create_rmp_in_bits {
7107         u8         opcode[0x10];
7108         u8         reserved_0[0x10];
7109
7110         u8         reserved_1[0x10];
7111         u8         op_mod[0x10];
7112
7113         u8         reserved_2[0xc0];
7114
7115         struct mlx5_ifc_rmpc_bits ctx;
7116 };
7117
7118 struct mlx5_ifc_create_qp_out_bits {
7119         u8         status[0x8];
7120         u8         reserved_0[0x18];
7121
7122         u8         syndrome[0x20];
7123
7124         u8         reserved_1[0x8];
7125         u8         qpn[0x18];
7126
7127         u8         reserved_2[0x20];
7128 };
7129
7130 struct mlx5_ifc_create_qp_in_bits {
7131         u8         opcode[0x10];
7132         u8         reserved_0[0x10];
7133
7134         u8         reserved_1[0x10];
7135         u8         op_mod[0x10];
7136
7137         u8         reserved_2[0x8];
7138         u8         input_qpn[0x18];
7139
7140         u8         reserved_3[0x20];
7141
7142         u8         opt_param_mask[0x20];
7143
7144         u8         reserved_4[0x20];
7145
7146         struct mlx5_ifc_qpc_bits qpc;
7147
7148         u8         reserved_5[0x80];
7149
7150         u8         pas[0][0x40];
7151 };
7152
7153 struct mlx5_ifc_create_qos_para_vport_out_bits {
7154         u8         status[0x8];
7155         u8         reserved_at_8[0x18];
7156
7157         u8         syndrome[0x20];
7158
7159         u8         reserved_at_40[0x20];
7160
7161         u8         reserved_at_60[0x10];
7162         u8         qos_para_vport_number[0x10];
7163
7164         u8         reserved_at_80[0x180];
7165 };
7166
7167 struct mlx5_ifc_create_qos_para_vport_in_bits {
7168         u8         opcode[0x10];
7169         u8         reserved_at_10[0x10];
7170
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173
7174         u8         reserved_at_40[0x1c0];
7175 };
7176
7177 struct mlx5_ifc_create_psv_out_bits {
7178         u8         status[0x8];
7179         u8         reserved_0[0x18];
7180
7181         u8         syndrome[0x20];
7182
7183         u8         reserved_1[0x40];
7184
7185         u8         reserved_2[0x8];
7186         u8         psv0_index[0x18];
7187
7188         u8         reserved_3[0x8];
7189         u8         psv1_index[0x18];
7190
7191         u8         reserved_4[0x8];
7192         u8         psv2_index[0x18];
7193
7194         u8         reserved_5[0x8];
7195         u8         psv3_index[0x18];
7196 };
7197
7198 struct mlx5_ifc_create_psv_in_bits {
7199         u8         opcode[0x10];
7200         u8         reserved_0[0x10];
7201
7202         u8         reserved_1[0x10];
7203         u8         op_mod[0x10];
7204
7205         u8         num_psv[0x4];
7206         u8         reserved_2[0x4];
7207         u8         pd[0x18];
7208
7209         u8         reserved_3[0x20];
7210 };
7211
7212 struct mlx5_ifc_create_mkey_out_bits {
7213         u8         status[0x8];
7214         u8         reserved_0[0x18];
7215
7216         u8         syndrome[0x20];
7217
7218         u8         reserved_1[0x8];
7219         u8         mkey_index[0x18];
7220
7221         u8         reserved_2[0x20];
7222 };
7223
7224 struct mlx5_ifc_create_mkey_in_bits {
7225         u8         opcode[0x10];
7226         u8         reserved_0[0x10];
7227
7228         u8         reserved_1[0x10];
7229         u8         op_mod[0x10];
7230
7231         u8         reserved_2[0x20];
7232
7233         u8         pg_access[0x1];
7234         u8         reserved_3[0x1f];
7235
7236         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7237
7238         u8         reserved_4[0x80];
7239
7240         u8         translations_octword_actual_size[0x20];
7241
7242         u8         reserved_5[0x560];
7243
7244         u8         klm_pas_mtt[0][0x20];
7245 };
7246
7247 struct mlx5_ifc_create_flow_table_out_bits {
7248         u8         status[0x8];
7249         u8         reserved_0[0x18];
7250
7251         u8         syndrome[0x20];
7252
7253         u8         reserved_1[0x8];
7254         u8         table_id[0x18];
7255
7256         u8         reserved_2[0x20];
7257 };
7258
7259 struct mlx5_ifc_create_flow_table_in_bits {
7260         u8         opcode[0x10];
7261         u8         reserved_at_10[0x10];
7262
7263         u8         reserved_at_20[0x10];
7264         u8         op_mod[0x10];
7265
7266         u8         other_vport[0x1];
7267         u8         reserved_at_41[0xf];
7268         u8         vport_number[0x10];
7269
7270         u8         reserved_at_60[0x20];
7271
7272         u8         table_type[0x8];
7273         u8         reserved_at_88[0x18];
7274
7275         u8         reserved_at_a0[0x20];
7276
7277         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7278 };
7279
7280 struct mlx5_ifc_create_flow_group_out_bits {
7281         u8         status[0x8];
7282         u8         reserved_0[0x18];
7283
7284         u8         syndrome[0x20];
7285
7286         u8         reserved_1[0x8];
7287         u8         group_id[0x18];
7288
7289         u8         reserved_2[0x20];
7290 };
7291
7292 enum {
7293         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7294         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7295         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7296 };
7297
7298 struct mlx5_ifc_create_flow_group_in_bits {
7299         u8         opcode[0x10];
7300         u8         reserved_0[0x10];
7301
7302         u8         reserved_1[0x10];
7303         u8         op_mod[0x10];
7304
7305         u8         other_vport[0x1];
7306         u8         reserved_2[0xf];
7307         u8         vport_number[0x10];
7308
7309         u8         reserved_3[0x20];
7310
7311         u8         table_type[0x8];
7312         u8         reserved_4[0x18];
7313
7314         u8         reserved_5[0x8];
7315         u8         table_id[0x18];
7316
7317         u8         reserved_6[0x20];
7318
7319         u8         start_flow_index[0x20];
7320
7321         u8         reserved_7[0x20];
7322
7323         u8         end_flow_index[0x20];
7324
7325         u8         reserved_8[0xa0];
7326
7327         u8         reserved_9[0x18];
7328         u8         match_criteria_enable[0x8];
7329
7330         struct mlx5_ifc_fte_match_param_bits match_criteria;
7331
7332         u8         reserved_10[0xe00];
7333 };
7334
7335 struct mlx5_ifc_create_encryption_key_out_bits {
7336         u8         status[0x8];
7337         u8         reserved_at_8[0x18];
7338
7339         u8         syndrome[0x20];
7340
7341         u8         obj_id[0x20];
7342
7343         u8         reserved_at_60[0x20];
7344 };
7345
7346 struct mlx5_ifc_create_encryption_key_in_bits {
7347         u8         opcode[0x10];
7348         u8         reserved_at_10[0x10];
7349
7350         u8         reserved_at_20[0x10];
7351         u8         obj_type[0x10];
7352
7353         u8         reserved_at_40[0x40];
7354
7355         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7356 };
7357
7358 struct mlx5_ifc_create_eq_out_bits {
7359         u8         status[0x8];
7360         u8         reserved_0[0x18];
7361
7362         u8         syndrome[0x20];
7363
7364         u8         reserved_1[0x18];
7365         u8         eq_number[0x8];
7366
7367         u8         reserved_2[0x20];
7368 };
7369
7370 struct mlx5_ifc_create_eq_in_bits {
7371         u8         opcode[0x10];
7372         u8         reserved_0[0x10];
7373
7374         u8         reserved_1[0x10];
7375         u8         op_mod[0x10];
7376
7377         u8         reserved_2[0x40];
7378
7379         struct mlx5_ifc_eqc_bits eq_context_entry;
7380
7381         u8         reserved_3[0x40];
7382
7383         u8         event_bitmask[0x40];
7384
7385         u8         reserved_4[0x580];
7386
7387         u8         pas[0][0x40];
7388 };
7389
7390 struct mlx5_ifc_create_dct_out_bits {
7391         u8         status[0x8];
7392         u8         reserved_0[0x18];
7393
7394         u8         syndrome[0x20];
7395
7396         u8         reserved_1[0x8];
7397         u8         dctn[0x18];
7398
7399         u8         reserved_2[0x20];
7400 };
7401
7402 struct mlx5_ifc_create_dct_in_bits {
7403         u8         opcode[0x10];
7404         u8         reserved_0[0x10];
7405
7406         u8         reserved_1[0x10];
7407         u8         op_mod[0x10];
7408
7409         u8         reserved_2[0x40];
7410
7411         struct mlx5_ifc_dctc_bits dct_context_entry;
7412
7413         u8         reserved_3[0x180];
7414 };
7415
7416 struct mlx5_ifc_create_cq_out_bits {
7417         u8         status[0x8];
7418         u8         reserved_0[0x18];
7419
7420         u8         syndrome[0x20];
7421
7422         u8         reserved_1[0x8];
7423         u8         cqn[0x18];
7424
7425         u8         reserved_2[0x20];
7426 };
7427
7428 struct mlx5_ifc_create_cq_in_bits {
7429         u8         opcode[0x10];
7430         u8         reserved_0[0x10];
7431
7432         u8         reserved_1[0x10];
7433         u8         op_mod[0x10];
7434
7435         u8         reserved_2[0x40];
7436
7437         struct mlx5_ifc_cqc_bits cq_context;
7438
7439         u8         reserved_3[0x600];
7440
7441         u8         pas[0][0x40];
7442 };
7443
7444 struct mlx5_ifc_config_int_moderation_out_bits {
7445         u8         status[0x8];
7446         u8         reserved_0[0x18];
7447
7448         u8         syndrome[0x20];
7449
7450         u8         reserved_1[0x4];
7451         u8         min_delay[0xc];
7452         u8         int_vector[0x10];
7453
7454         u8         reserved_2[0x20];
7455 };
7456
7457 enum {
7458         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7459         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7460 };
7461
7462 struct mlx5_ifc_config_int_moderation_in_bits {
7463         u8         opcode[0x10];
7464         u8         reserved_0[0x10];
7465
7466         u8         reserved_1[0x10];
7467         u8         op_mod[0x10];
7468
7469         u8         reserved_2[0x4];
7470         u8         min_delay[0xc];
7471         u8         int_vector[0x10];
7472
7473         u8         reserved_3[0x20];
7474 };
7475
7476 struct mlx5_ifc_attach_to_mcg_out_bits {
7477         u8         status[0x8];
7478         u8         reserved_0[0x18];
7479
7480         u8         syndrome[0x20];
7481
7482         u8         reserved_1[0x40];
7483 };
7484
7485 struct mlx5_ifc_attach_to_mcg_in_bits {
7486         u8         opcode[0x10];
7487         u8         reserved_0[0x10];
7488
7489         u8         reserved_1[0x10];
7490         u8         op_mod[0x10];
7491
7492         u8         reserved_2[0x8];
7493         u8         qpn[0x18];
7494
7495         u8         reserved_3[0x20];
7496
7497         u8         multicast_gid[16][0x8];
7498 };
7499
7500 struct mlx5_ifc_arm_xrc_srq_out_bits {
7501         u8         status[0x8];
7502         u8         reserved_0[0x18];
7503
7504         u8         syndrome[0x20];
7505
7506         u8         reserved_1[0x40];
7507 };
7508
7509 enum {
7510         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7511 };
7512
7513 struct mlx5_ifc_arm_xrc_srq_in_bits {
7514         u8         opcode[0x10];
7515         u8         reserved_0[0x10];
7516
7517         u8         reserved_1[0x10];
7518         u8         op_mod[0x10];
7519
7520         u8         reserved_2[0x8];
7521         u8         xrc_srqn[0x18];
7522
7523         u8         reserved_3[0x10];
7524         u8         lwm[0x10];
7525 };
7526
7527 struct mlx5_ifc_arm_rq_out_bits {
7528         u8         status[0x8];
7529         u8         reserved_0[0x18];
7530
7531         u8         syndrome[0x20];
7532
7533         u8         reserved_1[0x40];
7534 };
7535
7536 enum {
7537         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7538 };
7539
7540 struct mlx5_ifc_arm_rq_in_bits {
7541         u8         opcode[0x10];
7542         u8         reserved_0[0x10];
7543
7544         u8         reserved_1[0x10];
7545         u8         op_mod[0x10];
7546
7547         u8         reserved_2[0x8];
7548         u8         srq_number[0x18];
7549
7550         u8         reserved_3[0x10];
7551         u8         lwm[0x10];
7552 };
7553
7554 struct mlx5_ifc_arm_dct_out_bits {
7555         u8         status[0x8];
7556         u8         reserved_0[0x18];
7557
7558         u8         syndrome[0x20];
7559
7560         u8         reserved_1[0x40];
7561 };
7562
7563 struct mlx5_ifc_arm_dct_in_bits {
7564         u8         opcode[0x10];
7565         u8         reserved_0[0x10];
7566
7567         u8         reserved_1[0x10];
7568         u8         op_mod[0x10];
7569
7570         u8         reserved_2[0x8];
7571         u8         dctn[0x18];
7572
7573         u8         reserved_3[0x20];
7574 };
7575
7576 struct mlx5_ifc_alloc_xrcd_out_bits {
7577         u8         status[0x8];
7578         u8         reserved_0[0x18];
7579
7580         u8         syndrome[0x20];
7581
7582         u8         reserved_1[0x8];
7583         u8         xrcd[0x18];
7584
7585         u8         reserved_2[0x20];
7586 };
7587
7588 struct mlx5_ifc_alloc_xrcd_in_bits {
7589         u8         opcode[0x10];
7590         u8         reserved_0[0x10];
7591
7592         u8         reserved_1[0x10];
7593         u8         op_mod[0x10];
7594
7595         u8         reserved_2[0x40];
7596 };
7597
7598 struct mlx5_ifc_alloc_uar_out_bits {
7599         u8         status[0x8];
7600         u8         reserved_0[0x18];
7601
7602         u8         syndrome[0x20];
7603
7604         u8         reserved_1[0x8];
7605         u8         uar[0x18];
7606
7607         u8         reserved_2[0x20];
7608 };
7609
7610 struct mlx5_ifc_alloc_uar_in_bits {
7611         u8         opcode[0x10];
7612         u8         reserved_0[0x10];
7613
7614         u8         reserved_1[0x10];
7615         u8         op_mod[0x10];
7616
7617         u8         reserved_2[0x40];
7618 };
7619
7620 struct mlx5_ifc_alloc_transport_domain_out_bits {
7621         u8         status[0x8];
7622         u8         reserved_0[0x18];
7623
7624         u8         syndrome[0x20];
7625
7626         u8         reserved_1[0x8];
7627         u8         transport_domain[0x18];
7628
7629         u8         reserved_2[0x20];
7630 };
7631
7632 struct mlx5_ifc_alloc_transport_domain_in_bits {
7633         u8         opcode[0x10];
7634         u8         reserved_0[0x10];
7635
7636         u8         reserved_1[0x10];
7637         u8         op_mod[0x10];
7638
7639         u8         reserved_2[0x40];
7640 };
7641
7642 struct mlx5_ifc_alloc_q_counter_out_bits {
7643         u8         status[0x8];
7644         u8         reserved_0[0x18];
7645
7646         u8         syndrome[0x20];
7647
7648         u8         reserved_1[0x18];
7649         u8         counter_set_id[0x8];
7650
7651         u8         reserved_2[0x20];
7652 };
7653
7654 struct mlx5_ifc_alloc_q_counter_in_bits {
7655         u8         opcode[0x10];
7656         u8         reserved_0[0x10];
7657
7658         u8         reserved_1[0x10];
7659         u8         op_mod[0x10];
7660
7661         u8         reserved_2[0x40];
7662 };
7663
7664 struct mlx5_ifc_alloc_pd_out_bits {
7665         u8         status[0x8];
7666         u8         reserved_0[0x18];
7667
7668         u8         syndrome[0x20];
7669
7670         u8         reserved_1[0x8];
7671         u8         pd[0x18];
7672
7673         u8         reserved_2[0x20];
7674 };
7675
7676 struct mlx5_ifc_alloc_pd_in_bits {
7677         u8         opcode[0x10];
7678         u8         reserved_0[0x10];
7679
7680         u8         reserved_1[0x10];
7681         u8         op_mod[0x10];
7682
7683         u8         reserved_2[0x40];
7684 };
7685
7686 struct mlx5_ifc_alloc_flow_counter_out_bits {
7687         u8         status[0x8];
7688         u8         reserved_0[0x18];
7689
7690         u8         syndrome[0x20];
7691
7692         u8         reserved_1[0x10];
7693         u8         flow_counter_id[0x10];
7694
7695         u8         reserved_2[0x20];
7696 };
7697
7698 struct mlx5_ifc_alloc_flow_counter_in_bits {
7699         u8         opcode[0x10];
7700         u8         reserved_0[0x10];
7701
7702         u8         reserved_1[0x10];
7703         u8         op_mod[0x10];
7704
7705         u8         reserved_2[0x40];
7706 };
7707
7708 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7709         u8         status[0x8];
7710         u8         reserved_0[0x18];
7711
7712         u8         syndrome[0x20];
7713
7714         u8         reserved_1[0x40];
7715 };
7716
7717 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7718         u8         opcode[0x10];
7719         u8         reserved_0[0x10];
7720
7721         u8         reserved_1[0x10];
7722         u8         op_mod[0x10];
7723
7724         u8         reserved_2[0x20];
7725
7726         u8         reserved_3[0x10];
7727         u8         vxlan_udp_port[0x10];
7728 };
7729
7730 struct mlx5_ifc_activate_tracer_out_bits {
7731         u8         status[0x8];
7732         u8         reserved_0[0x18];
7733
7734         u8         syndrome[0x20];
7735
7736         u8         reserved_1[0x40];
7737 };
7738
7739 struct mlx5_ifc_activate_tracer_in_bits {
7740         u8         opcode[0x10];
7741         u8         reserved_0[0x10];
7742
7743         u8         reserved_1[0x10];
7744         u8         op_mod[0x10];
7745
7746         u8         mkey[0x20];
7747
7748         u8         reserved_2[0x20];
7749 };
7750
7751 struct mlx5_ifc_set_rate_limit_out_bits {
7752         u8         status[0x8];
7753         u8         reserved_at_8[0x18];
7754
7755         u8         syndrome[0x20];
7756
7757         u8         reserved_at_40[0x40];
7758 };
7759
7760 struct mlx5_ifc_set_rate_limit_in_bits {
7761         u8         opcode[0x10];
7762         u8         reserved_at_10[0x10];
7763
7764         u8         reserved_at_20[0x10];
7765         u8         op_mod[0x10];
7766
7767         u8         reserved_at_40[0x10];
7768         u8         rate_limit_index[0x10];
7769
7770         u8         reserved_at_60[0x20];
7771
7772         u8         rate_limit[0x20];
7773
7774         u8         burst_upper_bound[0x20];
7775
7776         u8         reserved_at_c0[0x10];
7777         u8         typical_packet_size[0x10];
7778
7779         u8         reserved_at_e0[0x120];
7780 };
7781
7782 struct mlx5_ifc_access_register_out_bits {
7783         u8         status[0x8];
7784         u8         reserved_0[0x18];
7785
7786         u8         syndrome[0x20];
7787
7788         u8         reserved_1[0x40];
7789
7790         u8         register_data[0][0x20];
7791 };
7792
7793 enum {
7794         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7795         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7796 };
7797
7798 struct mlx5_ifc_access_register_in_bits {
7799         u8         opcode[0x10];
7800         u8         reserved_0[0x10];
7801
7802         u8         reserved_1[0x10];
7803         u8         op_mod[0x10];
7804
7805         u8         reserved_2[0x10];
7806         u8         register_id[0x10];
7807
7808         u8         argument[0x20];
7809
7810         u8         register_data[0][0x20];
7811 };
7812
7813 struct mlx5_ifc_sltp_reg_bits {
7814         u8         status[0x4];
7815         u8         version[0x4];
7816         u8         local_port[0x8];
7817         u8         pnat[0x2];
7818         u8         reserved_0[0x2];
7819         u8         lane[0x4];
7820         u8         reserved_1[0x8];
7821
7822         u8         reserved_2[0x20];
7823
7824         u8         reserved_3[0x7];
7825         u8         polarity[0x1];
7826         u8         ob_tap0[0x8];
7827         u8         ob_tap1[0x8];
7828         u8         ob_tap2[0x8];
7829
7830         u8         reserved_4[0xc];
7831         u8         ob_preemp_mode[0x4];
7832         u8         ob_reg[0x8];
7833         u8         ob_bias[0x8];
7834
7835         u8         reserved_5[0x20];
7836 };
7837
7838 struct mlx5_ifc_slrp_reg_bits {
7839         u8         status[0x4];
7840         u8         version[0x4];
7841         u8         local_port[0x8];
7842         u8         pnat[0x2];
7843         u8         reserved_0[0x2];
7844         u8         lane[0x4];
7845         u8         reserved_1[0x8];
7846
7847         u8         ib_sel[0x2];
7848         u8         reserved_2[0x11];
7849         u8         dp_sel[0x1];
7850         u8         dp90sel[0x4];
7851         u8         mix90phase[0x8];
7852
7853         u8         ffe_tap0[0x8];
7854         u8         ffe_tap1[0x8];
7855         u8         ffe_tap2[0x8];
7856         u8         ffe_tap3[0x8];
7857
7858         u8         ffe_tap4[0x8];
7859         u8         ffe_tap5[0x8];
7860         u8         ffe_tap6[0x8];
7861         u8         ffe_tap7[0x8];
7862
7863         u8         ffe_tap8[0x8];
7864         u8         mixerbias_tap_amp[0x8];
7865         u8         reserved_3[0x7];
7866         u8         ffe_tap_en[0x9];
7867
7868         u8         ffe_tap_offset0[0x8];
7869         u8         ffe_tap_offset1[0x8];
7870         u8         slicer_offset0[0x10];
7871
7872         u8         mixer_offset0[0x10];
7873         u8         mixer_offset1[0x10];
7874
7875         u8         mixerbgn_inp[0x8];
7876         u8         mixerbgn_inn[0x8];
7877         u8         mixerbgn_refp[0x8];
7878         u8         mixerbgn_refn[0x8];
7879
7880         u8         sel_slicer_lctrl_h[0x1];
7881         u8         sel_slicer_lctrl_l[0x1];
7882         u8         reserved_4[0x1];
7883         u8         ref_mixer_vreg[0x5];
7884         u8         slicer_gctrl[0x8];
7885         u8         lctrl_input[0x8];
7886         u8         mixer_offset_cm1[0x8];
7887
7888         u8         common_mode[0x6];
7889         u8         reserved_5[0x1];
7890         u8         mixer_offset_cm0[0x9];
7891         u8         reserved_6[0x7];
7892         u8         slicer_offset_cm[0x9];
7893 };
7894
7895 struct mlx5_ifc_slrg_reg_bits {
7896         u8         status[0x4];
7897         u8         version[0x4];
7898         u8         local_port[0x8];
7899         u8         pnat[0x2];
7900         u8         reserved_0[0x2];
7901         u8         lane[0x4];
7902         u8         reserved_1[0x8];
7903
7904         u8         time_to_link_up[0x10];
7905         u8         reserved_2[0xc];
7906         u8         grade_lane_speed[0x4];
7907
7908         u8         grade_version[0x8];
7909         u8         grade[0x18];
7910
7911         u8         reserved_3[0x4];
7912         u8         height_grade_type[0x4];
7913         u8         height_grade[0x18];
7914
7915         u8         height_dz[0x10];
7916         u8         height_dv[0x10];
7917
7918         u8         reserved_4[0x10];
7919         u8         height_sigma[0x10];
7920
7921         u8         reserved_5[0x20];
7922
7923         u8         reserved_6[0x4];
7924         u8         phase_grade_type[0x4];
7925         u8         phase_grade[0x18];
7926
7927         u8         reserved_7[0x8];
7928         u8         phase_eo_pos[0x8];
7929         u8         reserved_8[0x8];
7930         u8         phase_eo_neg[0x8];
7931
7932         u8         ffe_set_tested[0x10];
7933         u8         test_errors_per_lane[0x10];
7934 };
7935
7936 struct mlx5_ifc_pvlc_reg_bits {
7937         u8         reserved_0[0x8];
7938         u8         local_port[0x8];
7939         u8         reserved_1[0x10];
7940
7941         u8         reserved_2[0x1c];
7942         u8         vl_hw_cap[0x4];
7943
7944         u8         reserved_3[0x1c];
7945         u8         vl_admin[0x4];
7946
7947         u8         reserved_4[0x1c];
7948         u8         vl_operational[0x4];
7949 };
7950
7951 struct mlx5_ifc_pude_reg_bits {
7952         u8         swid[0x8];
7953         u8         local_port[0x8];
7954         u8         reserved_0[0x4];
7955         u8         admin_status[0x4];
7956         u8         reserved_1[0x4];
7957         u8         oper_status[0x4];
7958
7959         u8         reserved_2[0x60];
7960 };
7961
7962 enum {
7963         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7964         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7965 };
7966
7967 struct mlx5_ifc_ptys_reg_bits {
7968         u8         reserved_0[0x1];
7969         u8         an_disable_admin[0x1];
7970         u8         an_disable_cap[0x1];
7971         u8         reserved_1[0x4];
7972         u8         force_tx_aba_param[0x1];
7973         u8         local_port[0x8];
7974         u8         reserved_2[0xd];
7975         u8         proto_mask[0x3];
7976
7977         u8         an_status[0x4];
7978         u8         reserved_3[0xc];
7979         u8         data_rate_oper[0x10];
7980
7981         u8         ext_eth_proto_capability[0x20];
7982
7983         u8         eth_proto_capability[0x20];
7984
7985         u8         ib_link_width_capability[0x10];
7986         u8         ib_proto_capability[0x10];
7987
7988         u8         ext_eth_proto_admin[0x20];
7989
7990         u8         eth_proto_admin[0x20];
7991
7992         u8         ib_link_width_admin[0x10];
7993         u8         ib_proto_admin[0x10];
7994
7995         u8         ext_eth_proto_oper[0x20];
7996
7997         u8         eth_proto_oper[0x20];
7998
7999         u8         ib_link_width_oper[0x10];
8000         u8         ib_proto_oper[0x10];
8001
8002         u8         reserved_4[0x1c];
8003         u8         connector_type[0x4];
8004
8005         u8         eth_proto_lp_advertise[0x20];
8006
8007         u8         reserved_5[0x60];
8008 };
8009
8010 struct mlx5_ifc_ptas_reg_bits {
8011         u8         reserved_0[0x20];
8012
8013         u8         algorithm_options[0x10];
8014         u8         reserved_1[0x4];
8015         u8         repetitions_mode[0x4];
8016         u8         num_of_repetitions[0x8];
8017
8018         u8         grade_version[0x8];
8019         u8         height_grade_type[0x4];
8020         u8         phase_grade_type[0x4];
8021         u8         height_grade_weight[0x8];
8022         u8         phase_grade_weight[0x8];
8023
8024         u8         gisim_measure_bits[0x10];
8025         u8         adaptive_tap_measure_bits[0x10];
8026
8027         u8         ber_bath_high_error_threshold[0x10];
8028         u8         ber_bath_mid_error_threshold[0x10];
8029
8030         u8         ber_bath_low_error_threshold[0x10];
8031         u8         one_ratio_high_threshold[0x10];
8032
8033         u8         one_ratio_high_mid_threshold[0x10];
8034         u8         one_ratio_low_mid_threshold[0x10];
8035
8036         u8         one_ratio_low_threshold[0x10];
8037         u8         ndeo_error_threshold[0x10];
8038
8039         u8         mixer_offset_step_size[0x10];
8040         u8         reserved_2[0x8];
8041         u8         mix90_phase_for_voltage_bath[0x8];
8042
8043         u8         mixer_offset_start[0x10];
8044         u8         mixer_offset_end[0x10];
8045
8046         u8         reserved_3[0x15];
8047         u8         ber_test_time[0xb];
8048 };
8049
8050 struct mlx5_ifc_pspa_reg_bits {
8051         u8         swid[0x8];
8052         u8         local_port[0x8];
8053         u8         sub_port[0x8];
8054         u8         reserved_0[0x8];
8055
8056         u8         reserved_1[0x20];
8057 };
8058
8059 struct mlx5_ifc_ppsc_reg_bits {
8060         u8         reserved_0[0x8];
8061         u8         local_port[0x8];
8062         u8         reserved_1[0x10];
8063
8064         u8         reserved_2[0x60];
8065
8066         u8         reserved_3[0x1c];
8067         u8         wrps_admin[0x4];
8068
8069         u8         reserved_4[0x1c];
8070         u8         wrps_status[0x4];
8071
8072         u8         up_th_vld[0x1];
8073         u8         down_th_vld[0x1];
8074         u8         reserved_5[0x6];
8075         u8         up_threshold[0x8];
8076         u8         reserved_6[0x8];
8077         u8         down_threshold[0x8];
8078
8079         u8         reserved_7[0x20];
8080
8081         u8         reserved_8[0x1c];
8082         u8         srps_admin[0x4];
8083
8084         u8         reserved_9[0x60];
8085 };
8086
8087 struct mlx5_ifc_pplr_reg_bits {
8088         u8         reserved_0[0x8];
8089         u8         local_port[0x8];
8090         u8         reserved_1[0x10];
8091
8092         u8         reserved_2[0x8];
8093         u8         lb_cap[0x8];
8094         u8         reserved_3[0x8];
8095         u8         lb_en[0x8];
8096 };
8097
8098 struct mlx5_ifc_pplm_reg_bits {
8099         u8         reserved_at_0[0x8];
8100         u8         local_port[0x8];
8101         u8         reserved_at_10[0x10];
8102
8103         u8         reserved_at_20[0x20];
8104
8105         u8         port_profile_mode[0x8];
8106         u8         static_port_profile[0x8];
8107         u8         active_port_profile[0x8];
8108         u8         reserved_at_58[0x8];
8109
8110         u8         retransmission_active[0x8];
8111         u8         fec_mode_active[0x18];
8112
8113         u8         rs_fec_correction_bypass_cap[0x4];
8114         u8         reserved_at_84[0x8];
8115         u8         fec_override_cap_56g[0x4];
8116         u8         fec_override_cap_100g[0x4];
8117         u8         fec_override_cap_50g[0x4];
8118         u8         fec_override_cap_25g[0x4];
8119         u8         fec_override_cap_10g_40g[0x4];
8120
8121         u8         rs_fec_correction_bypass_admin[0x4];
8122         u8         reserved_at_a4[0x8];
8123         u8         fec_override_admin_56g[0x4];
8124         u8         fec_override_admin_100g[0x4];
8125         u8         fec_override_admin_50g[0x4];
8126         u8         fec_override_admin_25g[0x4];
8127         u8         fec_override_admin_10g_40g[0x4];
8128
8129         u8         fec_override_cap_400g_8x[0x10];
8130         u8         fec_override_cap_200g_4x[0x10];
8131         u8         fec_override_cap_100g_2x[0x10];
8132         u8         fec_override_cap_50g_1x[0x10];
8133
8134         u8         fec_override_admin_400g_8x[0x10];
8135         u8         fec_override_admin_200g_4x[0x10];
8136         u8         fec_override_admin_100g_2x[0x10];
8137         u8         fec_override_admin_50g_1x[0x10];
8138
8139         u8         reserved_at_140[0xC0];
8140 };
8141
8142 struct mlx5_ifc_ppll_reg_bits {
8143         u8         num_pll_groups[0x8];
8144         u8         pll_group[0x8];
8145         u8         reserved_0[0x4];
8146         u8         num_plls[0x4];
8147         u8         reserved_1[0x8];
8148
8149         u8         reserved_2[0x1f];
8150         u8         ae[0x1];
8151
8152         u8         pll_status[4][0x40];
8153 };
8154
8155 struct mlx5_ifc_ppad_reg_bits {
8156         u8         reserved_0[0x3];
8157         u8         single_mac[0x1];
8158         u8         reserved_1[0x4];
8159         u8         local_port[0x8];
8160         u8         mac_47_32[0x10];
8161
8162         u8         mac_31_0[0x20];
8163
8164         u8         reserved_2[0x40];
8165 };
8166
8167 struct mlx5_ifc_pmtu_reg_bits {
8168         u8         reserved_0[0x8];
8169         u8         local_port[0x8];
8170         u8         reserved_1[0x10];
8171
8172         u8         max_mtu[0x10];
8173         u8         reserved_2[0x10];
8174
8175         u8         admin_mtu[0x10];
8176         u8         reserved_3[0x10];
8177
8178         u8         oper_mtu[0x10];
8179         u8         reserved_4[0x10];
8180 };
8181
8182 struct mlx5_ifc_pmpr_reg_bits {
8183         u8         reserved_0[0x8];
8184         u8         module[0x8];
8185         u8         reserved_1[0x10];
8186
8187         u8         reserved_2[0x18];
8188         u8         attenuation_5g[0x8];
8189
8190         u8         reserved_3[0x18];
8191         u8         attenuation_7g[0x8];
8192
8193         u8         reserved_4[0x18];
8194         u8         attenuation_12g[0x8];
8195 };
8196
8197 struct mlx5_ifc_pmpe_reg_bits {
8198         u8         reserved_0[0x8];
8199         u8         module[0x8];
8200         u8         reserved_1[0xc];
8201         u8         module_status[0x4];
8202
8203         u8         reserved_2[0x14];
8204         u8         error_type[0x4];
8205         u8         reserved_3[0x8];
8206
8207         u8         reserved_4[0x40];
8208 };
8209
8210 struct mlx5_ifc_pmpc_reg_bits {
8211         u8         module_state_updated[32][0x8];
8212 };
8213
8214 struct mlx5_ifc_pmlpn_reg_bits {
8215         u8         reserved_0[0x4];
8216         u8         mlpn_status[0x4];
8217         u8         local_port[0x8];
8218         u8         reserved_1[0x10];
8219
8220         u8         e[0x1];
8221         u8         reserved_2[0x1f];
8222 };
8223
8224 struct mlx5_ifc_pmlp_reg_bits {
8225         u8         rxtx[0x1];
8226         u8         reserved_0[0x7];
8227         u8         local_port[0x8];
8228         u8         reserved_1[0x8];
8229         u8         width[0x8];
8230
8231         u8         lane0_module_mapping[0x20];
8232
8233         u8         lane1_module_mapping[0x20];
8234
8235         u8         lane2_module_mapping[0x20];
8236
8237         u8         lane3_module_mapping[0x20];
8238
8239         u8         reserved_2[0x160];
8240 };
8241
8242 struct mlx5_ifc_pmaos_reg_bits {
8243         u8         reserved_0[0x8];
8244         u8         module[0x8];
8245         u8         reserved_1[0x4];
8246         u8         admin_status[0x4];
8247         u8         reserved_2[0x4];
8248         u8         oper_status[0x4];
8249
8250         u8         ase[0x1];
8251         u8         ee[0x1];
8252         u8         reserved_3[0x12];
8253         u8         error_type[0x4];
8254         u8         reserved_4[0x6];
8255         u8         e[0x2];
8256
8257         u8         reserved_5[0x40];
8258 };
8259
8260 struct mlx5_ifc_plpc_reg_bits {
8261         u8         reserved_0[0x4];
8262         u8         profile_id[0xc];
8263         u8         reserved_1[0x4];
8264         u8         proto_mask[0x4];
8265         u8         reserved_2[0x8];
8266
8267         u8         reserved_3[0x10];
8268         u8         lane_speed[0x10];
8269
8270         u8         reserved_4[0x17];
8271         u8         lpbf[0x1];
8272         u8         fec_mode_policy[0x8];
8273
8274         u8         retransmission_capability[0x8];
8275         u8         fec_mode_capability[0x18];
8276
8277         u8         retransmission_support_admin[0x8];
8278         u8         fec_mode_support_admin[0x18];
8279
8280         u8         retransmission_request_admin[0x8];
8281         u8         fec_mode_request_admin[0x18];
8282
8283         u8         reserved_5[0x80];
8284 };
8285
8286 struct mlx5_ifc_pll_status_data_bits {
8287         u8         reserved_0[0x1];
8288         u8         lock_cal[0x1];
8289         u8         lock_status[0x2];
8290         u8         reserved_1[0x2];
8291         u8         algo_f_ctrl[0xa];
8292         u8         analog_algo_num_var[0x6];
8293         u8         f_ctrl_measure[0xa];
8294
8295         u8         reserved_2[0x2];
8296         u8         analog_var[0x6];
8297         u8         reserved_3[0x2];
8298         u8         high_var[0x6];
8299         u8         reserved_4[0x2];
8300         u8         low_var[0x6];
8301         u8         reserved_5[0x2];
8302         u8         mid_val[0x6];
8303 };
8304
8305 struct mlx5_ifc_plib_reg_bits {
8306         u8         reserved_0[0x8];
8307         u8         local_port[0x8];
8308         u8         reserved_1[0x8];
8309         u8         ib_port[0x8];
8310
8311         u8         reserved_2[0x60];
8312 };
8313
8314 struct mlx5_ifc_plbf_reg_bits {
8315         u8         reserved_0[0x8];
8316         u8         local_port[0x8];
8317         u8         reserved_1[0xd];
8318         u8         lbf_mode[0x3];
8319
8320         u8         reserved_2[0x20];
8321 };
8322
8323 struct mlx5_ifc_pipg_reg_bits {
8324         u8         reserved_0[0x8];
8325         u8         local_port[0x8];
8326         u8         reserved_1[0x10];
8327
8328         u8         dic[0x1];
8329         u8         reserved_2[0x19];
8330         u8         ipg[0x4];
8331         u8         reserved_3[0x2];
8332 };
8333
8334 struct mlx5_ifc_pifr_reg_bits {
8335         u8         reserved_0[0x8];
8336         u8         local_port[0x8];
8337         u8         reserved_1[0x10];
8338
8339         u8         reserved_2[0xe0];
8340
8341         u8         port_filter[8][0x20];
8342
8343         u8         port_filter_update_en[8][0x20];
8344 };
8345
8346 struct mlx5_ifc_phys_layer_cntrs_bits {
8347         u8         time_since_last_clear_high[0x20];
8348
8349         u8         time_since_last_clear_low[0x20];
8350
8351         u8         symbol_errors_high[0x20];
8352
8353         u8         symbol_errors_low[0x20];
8354
8355         u8         sync_headers_errors_high[0x20];
8356
8357         u8         sync_headers_errors_low[0x20];
8358
8359         u8         edpl_bip_errors_lane0_high[0x20];
8360
8361         u8         edpl_bip_errors_lane0_low[0x20];
8362
8363         u8         edpl_bip_errors_lane1_high[0x20];
8364
8365         u8         edpl_bip_errors_lane1_low[0x20];
8366
8367         u8         edpl_bip_errors_lane2_high[0x20];
8368
8369         u8         edpl_bip_errors_lane2_low[0x20];
8370
8371         u8         edpl_bip_errors_lane3_high[0x20];
8372
8373         u8         edpl_bip_errors_lane3_low[0x20];
8374
8375         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8376
8377         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8378
8379         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8380
8381         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8382
8383         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8384
8385         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8386
8387         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8388
8389         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8390
8391         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8392
8393         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8394
8395         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8396
8397         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8398
8399         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8400
8401         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8402
8403         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8404
8405         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8406
8407         u8         rs_fec_corrected_blocks_high[0x20];
8408
8409         u8         rs_fec_corrected_blocks_low[0x20];
8410
8411         u8         rs_fec_uncorrectable_blocks_high[0x20];
8412
8413         u8         rs_fec_uncorrectable_blocks_low[0x20];
8414
8415         u8         rs_fec_no_errors_blocks_high[0x20];
8416
8417         u8         rs_fec_no_errors_blocks_low[0x20];
8418
8419         u8         rs_fec_single_error_blocks_high[0x20];
8420
8421         u8         rs_fec_single_error_blocks_low[0x20];
8422
8423         u8         rs_fec_corrected_symbols_total_high[0x20];
8424
8425         u8         rs_fec_corrected_symbols_total_low[0x20];
8426
8427         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8428
8429         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8430
8431         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8432
8433         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8434
8435         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8436
8437         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8438
8439         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8440
8441         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8442
8443         u8         link_down_events[0x20];
8444
8445         u8         successful_recovery_events[0x20];
8446
8447         u8         reserved_0[0x180];
8448 };
8449
8450 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8451         u8         symbol_error_counter[0x10];
8452
8453         u8         link_error_recovery_counter[0x8];
8454
8455         u8         link_downed_counter[0x8];
8456
8457         u8         port_rcv_errors[0x10];
8458
8459         u8         port_rcv_remote_physical_errors[0x10];
8460
8461         u8         port_rcv_switch_relay_errors[0x10];
8462
8463         u8         port_xmit_discards[0x10];
8464
8465         u8         port_xmit_constraint_errors[0x8];
8466
8467         u8         port_rcv_constraint_errors[0x8];
8468
8469         u8         reserved_at_70[0x8];
8470
8471         u8         link_overrun_errors[0x8];
8472
8473         u8         reserved_at_80[0x10];
8474
8475         u8         vl_15_dropped[0x10];
8476
8477         u8         reserved_at_a0[0xa0];
8478 };
8479
8480 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8481         u8         time_since_last_clear_high[0x20];
8482
8483         u8         time_since_last_clear_low[0x20];
8484
8485         u8         phy_received_bits_high[0x20];
8486
8487         u8         phy_received_bits_low[0x20];
8488
8489         u8         phy_symbol_errors_high[0x20];
8490
8491         u8         phy_symbol_errors_low[0x20];
8492
8493         u8         phy_corrected_bits_high[0x20];
8494
8495         u8         phy_corrected_bits_low[0x20];
8496
8497         u8         phy_corrected_bits_lane0_high[0x20];
8498
8499         u8         phy_corrected_bits_lane0_low[0x20];
8500
8501         u8         phy_corrected_bits_lane1_high[0x20];
8502
8503         u8         phy_corrected_bits_lane1_low[0x20];
8504
8505         u8         phy_corrected_bits_lane2_high[0x20];
8506
8507         u8         phy_corrected_bits_lane2_low[0x20];
8508
8509         u8         phy_corrected_bits_lane3_high[0x20];
8510
8511         u8         phy_corrected_bits_lane3_low[0x20];
8512
8513         u8         reserved_at_200[0x5c0];
8514 };
8515
8516 struct mlx5_ifc_infiniband_port_cntrs_bits {
8517         u8         symbol_error_counter[0x10];
8518         u8         link_error_recovery_counter[0x8];
8519         u8         link_downed_counter[0x8];
8520
8521         u8         port_rcv_errors[0x10];
8522         u8         port_rcv_remote_physical_errors[0x10];
8523
8524         u8         port_rcv_switch_relay_errors[0x10];
8525         u8         port_xmit_discards[0x10];
8526
8527         u8         port_xmit_constraint_errors[0x8];
8528         u8         port_rcv_constraint_errors[0x8];
8529         u8         reserved_0[0x8];
8530         u8         local_link_integrity_errors[0x4];
8531         u8         excessive_buffer_overrun_errors[0x4];
8532
8533         u8         reserved_1[0x10];
8534         u8         vl_15_dropped[0x10];
8535
8536         u8         port_xmit_data[0x20];
8537
8538         u8         port_rcv_data[0x20];
8539
8540         u8         port_xmit_pkts[0x20];
8541
8542         u8         port_rcv_pkts[0x20];
8543
8544         u8         port_xmit_wait[0x20];
8545
8546         u8         reserved_2[0x680];
8547 };
8548
8549 struct mlx5_ifc_phrr_reg_bits {
8550         u8         clr[0x1];
8551         u8         reserved_0[0x7];
8552         u8         local_port[0x8];
8553         u8         reserved_1[0x10];
8554
8555         u8         hist_group[0x8];
8556         u8         reserved_2[0x10];
8557         u8         hist_id[0x8];
8558
8559         u8         reserved_3[0x40];
8560
8561         u8         time_since_last_clear_high[0x20];
8562
8563         u8         time_since_last_clear_low[0x20];
8564
8565         u8         bin[10][0x20];
8566 };
8567
8568 struct mlx5_ifc_phbr_for_prio_reg_bits {
8569         u8         reserved_0[0x18];
8570         u8         prio[0x8];
8571 };
8572
8573 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8574         u8         reserved_0[0x18];
8575         u8         tclass[0x8];
8576 };
8577
8578 struct mlx5_ifc_phbr_binding_reg_bits {
8579         u8         opcode[0x4];
8580         u8         reserved_0[0x4];
8581         u8         local_port[0x8];
8582         u8         pnat[0x2];
8583         u8         reserved_1[0xe];
8584
8585         u8         hist_group[0x8];
8586         u8         reserved_2[0x10];
8587         u8         hist_id[0x8];
8588
8589         u8         reserved_3[0x10];
8590         u8         hist_type[0x10];
8591
8592         u8         hist_parameters[0x20];
8593
8594         u8         hist_min_value[0x20];
8595
8596         u8         hist_max_value[0x20];
8597
8598         u8         sample_time[0x20];
8599 };
8600
8601 enum {
8602         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8603         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8604 };
8605
8606 struct mlx5_ifc_pfcc_reg_bits {
8607         u8         dcbx_operation_type[0x2];
8608         u8         cap_local_admin[0x1];
8609         u8         cap_remote_admin[0x1];
8610         u8         reserved_0[0x4];
8611         u8         local_port[0x8];
8612         u8         pnat[0x2];
8613         u8         reserved_1[0xc];
8614         u8         shl_cap[0x1];
8615         u8         shl_opr[0x1];
8616
8617         u8         ppan[0x4];
8618         u8         reserved_2[0x4];
8619         u8         prio_mask_tx[0x8];
8620         u8         reserved_3[0x8];
8621         u8         prio_mask_rx[0x8];
8622
8623         u8         pptx[0x1];
8624         u8         aptx[0x1];
8625         u8         reserved_4[0x6];
8626         u8         pfctx[0x8];
8627         u8         reserved_5[0x8];
8628         u8         cbftx[0x8];
8629
8630         u8         pprx[0x1];
8631         u8         aprx[0x1];
8632         u8         reserved_6[0x6];
8633         u8         pfcrx[0x8];
8634         u8         reserved_7[0x8];
8635         u8         cbfrx[0x8];
8636
8637         u8         device_stall_minor_watermark[0x10];
8638         u8         device_stall_critical_watermark[0x10];
8639
8640         u8         reserved_8[0x60];
8641 };
8642
8643 struct mlx5_ifc_pelc_reg_bits {
8644         u8         op[0x4];
8645         u8         reserved_0[0x4];
8646         u8         local_port[0x8];
8647         u8         reserved_1[0x10];
8648
8649         u8         op_admin[0x8];
8650         u8         op_capability[0x8];
8651         u8         op_request[0x8];
8652         u8         op_active[0x8];
8653
8654         u8         admin[0x40];
8655
8656         u8         capability[0x40];
8657
8658         u8         request[0x40];
8659
8660         u8         active[0x40];
8661
8662         u8         reserved_2[0x80];
8663 };
8664
8665 struct mlx5_ifc_peir_reg_bits {
8666         u8         reserved_0[0x8];
8667         u8         local_port[0x8];
8668         u8         reserved_1[0x10];
8669
8670         u8         reserved_2[0xc];
8671         u8         error_count[0x4];
8672         u8         reserved_3[0x10];
8673
8674         u8         reserved_4[0xc];
8675         u8         lane[0x4];
8676         u8         reserved_5[0x8];
8677         u8         error_type[0x8];
8678 };
8679
8680 struct mlx5_ifc_qcam_access_reg_cap_mask {
8681         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8682         u8         qpdpm[0x1];
8683         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8684         u8         qdpm[0x1];
8685         u8         qpts[0x1];
8686         u8         qcap[0x1];
8687         u8         qcam_access_reg_cap_mask_0[0x1];
8688 };
8689
8690 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8691         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8692         u8         qpts_trust_both[0x1];
8693 };
8694
8695 struct mlx5_ifc_qcam_reg_bits {
8696         u8         reserved_at_0[0x8];
8697         u8         feature_group[0x8];
8698         u8         reserved_at_10[0x8];
8699         u8         access_reg_group[0x8];
8700         u8         reserved_at_20[0x20];
8701
8702         union {
8703                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8704                 u8  reserved_at_0[0x80];
8705         } qos_access_reg_cap_mask;
8706
8707         u8         reserved_at_c0[0x80];
8708
8709         union {
8710                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8711                 u8  reserved_at_0[0x80];
8712         } qos_feature_cap_mask;
8713
8714         u8         reserved_at_1c0[0x80];
8715 };
8716
8717 struct mlx5_ifc_pcam_enhanced_features_bits {
8718         u8         reserved_at_0[0x6d];
8719         u8         rx_icrc_encapsulated_counter[0x1];
8720         u8         reserved_at_6e[0x4];
8721         u8         ptys_extended_ethernet[0x1];
8722         u8         reserved_at_73[0x3];
8723         u8         pfcc_mask[0x1];
8724         u8         reserved_at_77[0x3];
8725         u8         per_lane_error_counters[0x1];
8726         u8         rx_buffer_fullness_counters[0x1];
8727         u8         ptys_connector_type[0x1];
8728         u8         reserved_at_7d[0x1];
8729         u8         ppcnt_discard_group[0x1];
8730         u8         ppcnt_statistical_group[0x1];
8731 };
8732
8733 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8734         u8         port_access_reg_cap_mask_127_to_96[0x20];
8735         u8         port_access_reg_cap_mask_95_to_64[0x20];
8736
8737         u8         reserved_at_40[0xe];
8738         u8         pddr[0x1];
8739         u8         reserved_at_4f[0xd];
8740
8741         u8         pplm[0x1];
8742         u8         port_access_reg_cap_mask_34_to_32[0x3];
8743
8744         u8         port_access_reg_cap_mask_31_to_13[0x13];
8745         u8         pbmc[0x1];
8746         u8         pptb[0x1];
8747         u8         port_access_reg_cap_mask_10_to_09[0x2];
8748         u8         ppcnt[0x1];
8749         u8         port_access_reg_cap_mask_07_to_00[0x8];
8750 };
8751
8752 struct mlx5_ifc_pcam_reg_bits {
8753         u8         reserved_at_0[0x8];
8754         u8         feature_group[0x8];
8755         u8         reserved_at_10[0x8];
8756         u8         access_reg_group[0x8];
8757
8758         u8         reserved_at_20[0x20];
8759
8760         union {
8761                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8762                 u8         reserved_at_0[0x80];
8763         } port_access_reg_cap_mask;
8764
8765         u8         reserved_at_c0[0x80];
8766
8767         union {
8768                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8769                 u8         reserved_at_0[0x80];
8770         } feature_cap_mask;
8771
8772         u8         reserved_at_1c0[0xc0];
8773 };
8774
8775 struct mlx5_ifc_mcam_enhanced_features_bits {
8776         u8         reserved_at_0[0x6e];
8777         u8         pcie_status_and_power[0x1];
8778         u8         reserved_at_111[0x10];
8779         u8         pcie_performance_group[0x1];
8780 };
8781
8782 struct mlx5_ifc_mcam_access_reg_bits {
8783         u8         reserved_at_0[0x1c];
8784         u8         mcda[0x1];
8785         u8         mcc[0x1];
8786         u8         mcqi[0x1];
8787         u8         reserved_at_1f[0x1];
8788
8789         u8         regs_95_to_64[0x20];
8790         u8         regs_63_to_32[0x20];
8791         u8         regs_31_to_0[0x20];
8792 };
8793
8794 struct mlx5_ifc_mcam_reg_bits {
8795         u8         reserved_at_0[0x8];
8796         u8         feature_group[0x8];
8797         u8         reserved_at_10[0x8];
8798         u8         access_reg_group[0x8];
8799
8800         u8         reserved_at_20[0x20];
8801
8802         union {
8803                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8804                 u8         reserved_at_0[0x80];
8805         } mng_access_reg_cap_mask;
8806
8807         u8         reserved_at_c0[0x80];
8808
8809         union {
8810                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8811                 u8         reserved_at_0[0x80];
8812         } mng_feature_cap_mask;
8813
8814         u8         reserved_at_1c0[0x80];
8815 };
8816
8817 struct mlx5_ifc_pcap_reg_bits {
8818         u8         reserved_0[0x8];
8819         u8         local_port[0x8];
8820         u8         reserved_1[0x10];
8821
8822         u8         port_capability_mask[4][0x20];
8823 };
8824
8825 struct mlx5_ifc_pbmc_reg_bits {
8826         u8         reserved_at_0[0x8];
8827         u8         local_port[0x8];
8828         u8         reserved_at_10[0x10];
8829
8830         u8         xoff_timer_value[0x10];
8831         u8         xoff_refresh[0x10];
8832
8833         u8         reserved_at_40[0x9];
8834         u8         fullness_threshold[0x7];
8835         u8         port_buffer_size[0x10];
8836
8837         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8838
8839         u8         reserved_at_2e0[0x40];
8840 };
8841
8842 struct mlx5_ifc_paos_reg_bits {
8843         u8         swid[0x8];
8844         u8         local_port[0x8];
8845         u8         reserved_0[0x4];
8846         u8         admin_status[0x4];
8847         u8         reserved_1[0x4];
8848         u8         oper_status[0x4];
8849
8850         u8         ase[0x1];
8851         u8         ee[0x1];
8852         u8         reserved_2[0x1c];
8853         u8         e[0x2];
8854
8855         u8         reserved_3[0x40];
8856 };
8857
8858 struct mlx5_ifc_pamp_reg_bits {
8859         u8         reserved_0[0x8];
8860         u8         opamp_group[0x8];
8861         u8         reserved_1[0xc];
8862         u8         opamp_group_type[0x4];
8863
8864         u8         start_index[0x10];
8865         u8         reserved_2[0x4];
8866         u8         num_of_indices[0xc];
8867
8868         u8         index_data[18][0x10];
8869 };
8870
8871 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8872         u8         llr_rx_cells_high[0x20];
8873
8874         u8         llr_rx_cells_low[0x20];
8875
8876         u8         llr_rx_error_high[0x20];
8877
8878         u8         llr_rx_error_low[0x20];
8879
8880         u8         llr_rx_crc_error_high[0x20];
8881
8882         u8         llr_rx_crc_error_low[0x20];
8883
8884         u8         llr_tx_cells_high[0x20];
8885
8886         u8         llr_tx_cells_low[0x20];
8887
8888         u8         llr_tx_ret_cells_high[0x20];
8889
8890         u8         llr_tx_ret_cells_low[0x20];
8891
8892         u8         llr_tx_ret_events_high[0x20];
8893
8894         u8         llr_tx_ret_events_low[0x20];
8895
8896         u8         reserved_0[0x640];
8897 };
8898
8899 struct mlx5_ifc_mtmp_reg_bits {
8900         u8         i[0x1];
8901         u8         reserved_at_1[0x18];
8902         u8         sensor_index[0x7];
8903
8904         u8         reserved_at_20[0x10];
8905         u8         temperature[0x10];
8906
8907         u8         mte[0x1];
8908         u8         mtr[0x1];
8909         u8         reserved_at_42[0x0e];
8910         u8         max_temperature[0x10];
8911
8912         u8         tee[0x2];
8913         u8         reserved_at_62[0x0e];
8914         u8         temperature_threshold_hi[0x10];
8915
8916         u8         reserved_at_80[0x10];
8917         u8         temperature_threshold_lo[0x10];
8918
8919         u8         reserved_at_100[0x20];
8920
8921         u8         sensor_name[0x40];
8922 };
8923
8924 struct mlx5_ifc_lane_2_module_mapping_bits {
8925         u8         reserved_0[0x6];
8926         u8         rx_lane[0x2];
8927         u8         reserved_1[0x6];
8928         u8         tx_lane[0x2];
8929         u8         reserved_2[0x8];
8930         u8         module[0x8];
8931 };
8932
8933 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8934         u8         transmit_queue_high[0x20];
8935
8936         u8         transmit_queue_low[0x20];
8937
8938         u8         reserved_0[0x780];
8939 };
8940
8941 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8942         u8         no_buffer_discard_uc_high[0x20];
8943
8944         u8         no_buffer_discard_uc_low[0x20];
8945
8946         u8         wred_discard_high[0x20];
8947
8948         u8         wred_discard_low[0x20];
8949
8950         u8         reserved_0[0x740];
8951 };
8952
8953 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8954         u8         rx_octets_high[0x20];
8955
8956         u8         rx_octets_low[0x20];
8957
8958         u8         reserved_0[0xc0];
8959
8960         u8         rx_frames_high[0x20];
8961
8962         u8         rx_frames_low[0x20];
8963
8964         u8         tx_octets_high[0x20];
8965
8966         u8         tx_octets_low[0x20];
8967
8968         u8         reserved_1[0xc0];
8969
8970         u8         tx_frames_high[0x20];
8971
8972         u8         tx_frames_low[0x20];
8973
8974         u8         rx_pause_high[0x20];
8975
8976         u8         rx_pause_low[0x20];
8977
8978         u8         rx_pause_duration_high[0x20];
8979
8980         u8         rx_pause_duration_low[0x20];
8981
8982         u8         tx_pause_high[0x20];
8983
8984         u8         tx_pause_low[0x20];
8985
8986         u8         tx_pause_duration_high[0x20];
8987
8988         u8         tx_pause_duration_low[0x20];
8989
8990         u8         rx_pause_transition_high[0x20];
8991
8992         u8         rx_pause_transition_low[0x20];
8993
8994         u8         rx_discards_high[0x20];
8995
8996         u8         rx_discards_low[0x20];
8997
8998         u8         device_stall_minor_watermark_cnt_high[0x20];
8999
9000         u8         device_stall_minor_watermark_cnt_low[0x20];
9001
9002         u8         device_stall_critical_watermark_cnt_high[0x20];
9003
9004         u8         device_stall_critical_watermark_cnt_low[0x20];
9005
9006         u8         reserved_2[0x340];
9007 };
9008
9009 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9010         u8         port_transmit_wait_high[0x20];
9011
9012         u8         port_transmit_wait_low[0x20];
9013
9014         u8         ecn_marked_high[0x20];
9015
9016         u8         ecn_marked_low[0x20];
9017
9018         u8         no_buffer_discard_mc_high[0x20];
9019
9020         u8         no_buffer_discard_mc_low[0x20];
9021
9022         u8         rx_ebp_high[0x20];
9023
9024         u8         rx_ebp_low[0x20];
9025
9026         u8         tx_ebp_high[0x20];
9027
9028         u8         tx_ebp_low[0x20];
9029
9030         u8         rx_buffer_almost_full_high[0x20];
9031
9032         u8         rx_buffer_almost_full_low[0x20];
9033
9034         u8         rx_buffer_full_high[0x20];
9035
9036         u8         rx_buffer_full_low[0x20];
9037
9038         u8         rx_icrc_encapsulated_high[0x20];
9039
9040         u8         rx_icrc_encapsulated_low[0x20];
9041
9042         u8         reserved_0[0x80];
9043
9044         u8         tx_stats_pkts64octets_high[0x20];
9045
9046         u8         tx_stats_pkts64octets_low[0x20];
9047
9048         u8         tx_stats_pkts65to127octets_high[0x20];
9049
9050         u8         tx_stats_pkts65to127octets_low[0x20];
9051
9052         u8         tx_stats_pkts128to255octets_high[0x20];
9053
9054         u8         tx_stats_pkts128to255octets_low[0x20];
9055
9056         u8         tx_stats_pkts256to511octets_high[0x20];
9057
9058         u8         tx_stats_pkts256to511octets_low[0x20];
9059
9060         u8         tx_stats_pkts512to1023octets_high[0x20];
9061
9062         u8         tx_stats_pkts512to1023octets_low[0x20];
9063
9064         u8         tx_stats_pkts1024to1518octets_high[0x20];
9065
9066         u8         tx_stats_pkts1024to1518octets_low[0x20];
9067
9068         u8         tx_stats_pkts1519to2047octets_high[0x20];
9069
9070         u8         tx_stats_pkts1519to2047octets_low[0x20];
9071
9072         u8         tx_stats_pkts2048to4095octets_high[0x20];
9073
9074         u8         tx_stats_pkts2048to4095octets_low[0x20];
9075
9076         u8         tx_stats_pkts4096to8191octets_high[0x20];
9077
9078         u8         tx_stats_pkts4096to8191octets_low[0x20];
9079
9080         u8         tx_stats_pkts8192to10239octets_high[0x20];
9081
9082         u8         tx_stats_pkts8192to10239octets_low[0x20];
9083
9084         u8         reserved_1[0x2C0];
9085 };
9086
9087 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9088         u8         a_frames_transmitted_ok_high[0x20];
9089
9090         u8         a_frames_transmitted_ok_low[0x20];
9091
9092         u8         a_frames_received_ok_high[0x20];
9093
9094         u8         a_frames_received_ok_low[0x20];
9095
9096         u8         a_frame_check_sequence_errors_high[0x20];
9097
9098         u8         a_frame_check_sequence_errors_low[0x20];
9099
9100         u8         a_alignment_errors_high[0x20];
9101
9102         u8         a_alignment_errors_low[0x20];
9103
9104         u8         a_octets_transmitted_ok_high[0x20];
9105
9106         u8         a_octets_transmitted_ok_low[0x20];
9107
9108         u8         a_octets_received_ok_high[0x20];
9109
9110         u8         a_octets_received_ok_low[0x20];
9111
9112         u8         a_multicast_frames_xmitted_ok_high[0x20];
9113
9114         u8         a_multicast_frames_xmitted_ok_low[0x20];
9115
9116         u8         a_broadcast_frames_xmitted_ok_high[0x20];
9117
9118         u8         a_broadcast_frames_xmitted_ok_low[0x20];
9119
9120         u8         a_multicast_frames_received_ok_high[0x20];
9121
9122         u8         a_multicast_frames_received_ok_low[0x20];
9123
9124         u8         a_broadcast_frames_recieved_ok_high[0x20];
9125
9126         u8         a_broadcast_frames_recieved_ok_low[0x20];
9127
9128         u8         a_in_range_length_errors_high[0x20];
9129
9130         u8         a_in_range_length_errors_low[0x20];
9131
9132         u8         a_out_of_range_length_field_high[0x20];
9133
9134         u8         a_out_of_range_length_field_low[0x20];
9135
9136         u8         a_frame_too_long_errors_high[0x20];
9137
9138         u8         a_frame_too_long_errors_low[0x20];
9139
9140         u8         a_symbol_error_during_carrier_high[0x20];
9141
9142         u8         a_symbol_error_during_carrier_low[0x20];
9143
9144         u8         a_mac_control_frames_transmitted_high[0x20];
9145
9146         u8         a_mac_control_frames_transmitted_low[0x20];
9147
9148         u8         a_mac_control_frames_received_high[0x20];
9149
9150         u8         a_mac_control_frames_received_low[0x20];
9151
9152         u8         a_unsupported_opcodes_received_high[0x20];
9153
9154         u8         a_unsupported_opcodes_received_low[0x20];
9155
9156         u8         a_pause_mac_ctrl_frames_received_high[0x20];
9157
9158         u8         a_pause_mac_ctrl_frames_received_low[0x20];
9159
9160         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9161
9162         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9163
9164         u8         reserved_0[0x300];
9165 };
9166
9167 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9168         u8         dot3stats_alignment_errors_high[0x20];
9169
9170         u8         dot3stats_alignment_errors_low[0x20];
9171
9172         u8         dot3stats_fcs_errors_high[0x20];
9173
9174         u8         dot3stats_fcs_errors_low[0x20];
9175
9176         u8         dot3stats_single_collision_frames_high[0x20];
9177
9178         u8         dot3stats_single_collision_frames_low[0x20];
9179
9180         u8         dot3stats_multiple_collision_frames_high[0x20];
9181
9182         u8         dot3stats_multiple_collision_frames_low[0x20];
9183
9184         u8         dot3stats_sqe_test_errors_high[0x20];
9185
9186         u8         dot3stats_sqe_test_errors_low[0x20];
9187
9188         u8         dot3stats_deferred_transmissions_high[0x20];
9189
9190         u8         dot3stats_deferred_transmissions_low[0x20];
9191
9192         u8         dot3stats_late_collisions_high[0x20];
9193
9194         u8         dot3stats_late_collisions_low[0x20];
9195
9196         u8         dot3stats_excessive_collisions_high[0x20];
9197
9198         u8         dot3stats_excessive_collisions_low[0x20];
9199
9200         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9201
9202         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9203
9204         u8         dot3stats_carrier_sense_errors_high[0x20];
9205
9206         u8         dot3stats_carrier_sense_errors_low[0x20];
9207
9208         u8         dot3stats_frame_too_longs_high[0x20];
9209
9210         u8         dot3stats_frame_too_longs_low[0x20];
9211
9212         u8         dot3stats_internal_mac_receive_errors_high[0x20];
9213
9214         u8         dot3stats_internal_mac_receive_errors_low[0x20];
9215
9216         u8         dot3stats_symbol_errors_high[0x20];
9217
9218         u8         dot3stats_symbol_errors_low[0x20];
9219
9220         u8         dot3control_in_unknown_opcodes_high[0x20];
9221
9222         u8         dot3control_in_unknown_opcodes_low[0x20];
9223
9224         u8         dot3in_pause_frames_high[0x20];
9225
9226         u8         dot3in_pause_frames_low[0x20];
9227
9228         u8         dot3out_pause_frames_high[0x20];
9229
9230         u8         dot3out_pause_frames_low[0x20];
9231
9232         u8         reserved_0[0x3c0];
9233 };
9234
9235 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9236         u8         if_in_octets_high[0x20];
9237
9238         u8         if_in_octets_low[0x20];
9239
9240         u8         if_in_ucast_pkts_high[0x20];
9241
9242         u8         if_in_ucast_pkts_low[0x20];
9243
9244         u8         if_in_discards_high[0x20];
9245
9246         u8         if_in_discards_low[0x20];
9247
9248         u8         if_in_errors_high[0x20];
9249
9250         u8         if_in_errors_low[0x20];
9251
9252         u8         if_in_unknown_protos_high[0x20];
9253
9254         u8         if_in_unknown_protos_low[0x20];
9255
9256         u8         if_out_octets_high[0x20];
9257
9258         u8         if_out_octets_low[0x20];
9259
9260         u8         if_out_ucast_pkts_high[0x20];
9261
9262         u8         if_out_ucast_pkts_low[0x20];
9263
9264         u8         if_out_discards_high[0x20];
9265
9266         u8         if_out_discards_low[0x20];
9267
9268         u8         if_out_errors_high[0x20];
9269
9270         u8         if_out_errors_low[0x20];
9271
9272         u8         if_in_multicast_pkts_high[0x20];
9273
9274         u8         if_in_multicast_pkts_low[0x20];
9275
9276         u8         if_in_broadcast_pkts_high[0x20];
9277
9278         u8         if_in_broadcast_pkts_low[0x20];
9279
9280         u8         if_out_multicast_pkts_high[0x20];
9281
9282         u8         if_out_multicast_pkts_low[0x20];
9283
9284         u8         if_out_broadcast_pkts_high[0x20];
9285
9286         u8         if_out_broadcast_pkts_low[0x20];
9287
9288         u8         reserved_0[0x480];
9289 };
9290
9291 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9292         u8         ether_stats_drop_events_high[0x20];
9293
9294         u8         ether_stats_drop_events_low[0x20];
9295
9296         u8         ether_stats_octets_high[0x20];
9297
9298         u8         ether_stats_octets_low[0x20];
9299
9300         u8         ether_stats_pkts_high[0x20];
9301
9302         u8         ether_stats_pkts_low[0x20];
9303
9304         u8         ether_stats_broadcast_pkts_high[0x20];
9305
9306         u8         ether_stats_broadcast_pkts_low[0x20];
9307
9308         u8         ether_stats_multicast_pkts_high[0x20];
9309
9310         u8         ether_stats_multicast_pkts_low[0x20];
9311
9312         u8         ether_stats_crc_align_errors_high[0x20];
9313
9314         u8         ether_stats_crc_align_errors_low[0x20];
9315
9316         u8         ether_stats_undersize_pkts_high[0x20];
9317
9318         u8         ether_stats_undersize_pkts_low[0x20];
9319
9320         u8         ether_stats_oversize_pkts_high[0x20];
9321
9322         u8         ether_stats_oversize_pkts_low[0x20];
9323
9324         u8         ether_stats_fragments_high[0x20];
9325
9326         u8         ether_stats_fragments_low[0x20];
9327
9328         u8         ether_stats_jabbers_high[0x20];
9329
9330         u8         ether_stats_jabbers_low[0x20];
9331
9332         u8         ether_stats_collisions_high[0x20];
9333
9334         u8         ether_stats_collisions_low[0x20];
9335
9336         u8         ether_stats_pkts64octets_high[0x20];
9337
9338         u8         ether_stats_pkts64octets_low[0x20];
9339
9340         u8         ether_stats_pkts65to127octets_high[0x20];
9341
9342         u8         ether_stats_pkts65to127octets_low[0x20];
9343
9344         u8         ether_stats_pkts128to255octets_high[0x20];
9345
9346         u8         ether_stats_pkts128to255octets_low[0x20];
9347
9348         u8         ether_stats_pkts256to511octets_high[0x20];
9349
9350         u8         ether_stats_pkts256to511octets_low[0x20];
9351
9352         u8         ether_stats_pkts512to1023octets_high[0x20];
9353
9354         u8         ether_stats_pkts512to1023octets_low[0x20];
9355
9356         u8         ether_stats_pkts1024to1518octets_high[0x20];
9357
9358         u8         ether_stats_pkts1024to1518octets_low[0x20];
9359
9360         u8         ether_stats_pkts1519to2047octets_high[0x20];
9361
9362         u8         ether_stats_pkts1519to2047octets_low[0x20];
9363
9364         u8         ether_stats_pkts2048to4095octets_high[0x20];
9365
9366         u8         ether_stats_pkts2048to4095octets_low[0x20];
9367
9368         u8         ether_stats_pkts4096to8191octets_high[0x20];
9369
9370         u8         ether_stats_pkts4096to8191octets_low[0x20];
9371
9372         u8         ether_stats_pkts8192to10239octets_high[0x20];
9373
9374         u8         ether_stats_pkts8192to10239octets_low[0x20];
9375
9376         u8         reserved_0[0x280];
9377 };
9378
9379 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9380         u8         symbol_error_counter[0x10];
9381         u8         link_error_recovery_counter[0x8];
9382         u8         link_downed_counter[0x8];
9383
9384         u8         port_rcv_errors[0x10];
9385         u8         port_rcv_remote_physical_errors[0x10];
9386
9387         u8         port_rcv_switch_relay_errors[0x10];
9388         u8         port_xmit_discards[0x10];
9389
9390         u8         port_xmit_constraint_errors[0x8];
9391         u8         port_rcv_constraint_errors[0x8];
9392         u8         reserved_0[0x8];
9393         u8         local_link_integrity_errors[0x4];
9394         u8         excessive_buffer_overrun_errors[0x4];
9395
9396         u8         reserved_1[0x10];
9397         u8         vl_15_dropped[0x10];
9398
9399         u8         port_xmit_data[0x20];
9400
9401         u8         port_rcv_data[0x20];
9402
9403         u8         port_xmit_pkts[0x20];
9404
9405         u8         port_rcv_pkts[0x20];
9406
9407         u8         port_xmit_wait[0x20];
9408
9409         u8         reserved_2[0x680];
9410 };
9411
9412 struct mlx5_ifc_trc_tlb_reg_bits {
9413         u8         reserved_0[0x80];
9414
9415         u8         tlb_addr[0][0x40];
9416 };
9417
9418 struct mlx5_ifc_trc_read_fifo_reg_bits {
9419         u8         reserved_0[0x10];
9420         u8         requested_event_num[0x10];
9421
9422         u8         reserved_1[0x20];
9423
9424         u8         reserved_2[0x10];
9425         u8         acual_event_num[0x10];
9426
9427         u8         reserved_3[0x20];
9428
9429         u8         event[0][0x40];
9430 };
9431
9432 struct mlx5_ifc_trc_lock_reg_bits {
9433         u8         reserved_0[0x1f];
9434         u8         lock[0x1];
9435
9436         u8         reserved_1[0x60];
9437 };
9438
9439 struct mlx5_ifc_trc_filter_reg_bits {
9440         u8         status[0x1];
9441         u8         reserved_0[0xf];
9442         u8         filter_index[0x10];
9443
9444         u8         reserved_1[0x20];
9445
9446         u8         filter_val[0x20];
9447
9448         u8         reserved_2[0x1a0];
9449 };
9450
9451 struct mlx5_ifc_trc_event_reg_bits {
9452         u8         status[0x1];
9453         u8         reserved_0[0xf];
9454         u8         event_index[0x10];
9455
9456         u8         reserved_1[0x20];
9457
9458         u8         event_id[0x20];
9459
9460         u8         event_selector_val[0x10];
9461         u8         event_selector_size[0x10];
9462
9463         u8         reserved_2[0x180];
9464 };
9465
9466 struct mlx5_ifc_trc_conf_reg_bits {
9467         u8         limit_en[0x1];
9468         u8         reserved_0[0x3];
9469         u8         dump_mode[0x4];
9470         u8         reserved_1[0x15];
9471         u8         state[0x3];
9472
9473         u8         reserved_2[0x20];
9474
9475         u8         limit_event_index[0x20];
9476
9477         u8         mkey[0x20];
9478
9479         u8         fifo_ready_ev_num[0x20];
9480
9481         u8         reserved_3[0x160];
9482 };
9483
9484 struct mlx5_ifc_trc_cap_reg_bits {
9485         u8         reserved_0[0x18];
9486         u8         dump_mode[0x8];
9487
9488         u8         reserved_1[0x20];
9489
9490         u8         num_of_events[0x10];
9491         u8         num_of_filters[0x10];
9492
9493         u8         fifo_size[0x20];
9494
9495         u8         tlb_size[0x10];
9496         u8         event_size[0x10];
9497
9498         u8         reserved_2[0x160];
9499 };
9500
9501 struct mlx5_ifc_set_node_in_bits {
9502         u8         node_description[64][0x8];
9503 };
9504
9505 struct mlx5_ifc_register_power_settings_bits {
9506         u8         reserved_0[0x18];
9507         u8         power_settings_level[0x8];
9508
9509         u8         reserved_1[0x60];
9510 };
9511
9512 struct mlx5_ifc_register_host_endianess_bits {
9513         u8         he[0x1];
9514         u8         reserved_0[0x1f];
9515
9516         u8         reserved_1[0x60];
9517 };
9518
9519 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9520         u8         physical_address[0x40];
9521 };
9522
9523 struct mlx5_ifc_qtct_reg_bits {
9524         u8         operation_type[0x2];
9525         u8         cap_local_admin[0x1];
9526         u8         cap_remote_admin[0x1];
9527         u8         reserved_0[0x4];
9528         u8         port_number[0x8];
9529         u8         reserved_1[0xd];
9530         u8         prio[0x3];
9531
9532         u8         reserved_2[0x1d];
9533         u8         tclass[0x3];
9534 };
9535
9536 struct mlx5_ifc_qpdp_reg_bits {
9537         u8         reserved_0[0x8];
9538         u8         port_number[0x8];
9539         u8         reserved_1[0x10];
9540
9541         u8         reserved_2[0x1d];
9542         u8         pprio[0x3];
9543 };
9544
9545 struct mlx5_ifc_port_info_ro_fields_param_bits {
9546         u8         reserved_0[0x8];
9547         u8         port[0x8];
9548         u8         max_gid[0x10];
9549
9550         u8         reserved_1[0x20];
9551
9552         u8         port_guid[0x40];
9553 };
9554
9555 struct mlx5_ifc_nvqc_reg_bits {
9556         u8         type[0x20];
9557
9558         u8         reserved_0[0x18];
9559         u8         version[0x4];
9560         u8         reserved_1[0x2];
9561         u8         support_wr[0x1];
9562         u8         support_rd[0x1];
9563 };
9564
9565 struct mlx5_ifc_nvia_reg_bits {
9566         u8         reserved_0[0x1d];
9567         u8         target[0x3];
9568
9569         u8         reserved_1[0x20];
9570 };
9571
9572 struct mlx5_ifc_nvdi_reg_bits {
9573         struct mlx5_ifc_config_item_bits configuration_item_header;
9574 };
9575
9576 struct mlx5_ifc_nvda_reg_bits {
9577         struct mlx5_ifc_config_item_bits configuration_item_header;
9578
9579         u8         configuration_item_data[0x20];
9580 };
9581
9582 struct mlx5_ifc_node_info_ro_fields_param_bits {
9583         u8         system_image_guid[0x40];
9584
9585         u8         reserved_0[0x40];
9586
9587         u8         node_guid[0x40];
9588
9589         u8         reserved_1[0x10];
9590         u8         max_pkey[0x10];
9591
9592         u8         reserved_2[0x20];
9593 };
9594
9595 struct mlx5_ifc_ets_tcn_config_reg_bits {
9596         u8         g[0x1];
9597         u8         b[0x1];
9598         u8         r[0x1];
9599         u8         reserved_0[0x9];
9600         u8         group[0x4];
9601         u8         reserved_1[0x9];
9602         u8         bw_allocation[0x7];
9603
9604         u8         reserved_2[0xc];
9605         u8         max_bw_units[0x4];
9606         u8         reserved_3[0x8];
9607         u8         max_bw_value[0x8];
9608 };
9609
9610 struct mlx5_ifc_ets_global_config_reg_bits {
9611         u8         reserved_0[0x2];
9612         u8         r[0x1];
9613         u8         reserved_1[0x1d];
9614
9615         u8         reserved_2[0xc];
9616         u8         max_bw_units[0x4];
9617         u8         reserved_3[0x8];
9618         u8         max_bw_value[0x8];
9619 };
9620
9621 struct mlx5_ifc_qetc_reg_bits {
9622         u8                                         reserved_at_0[0x8];
9623         u8                                         port_number[0x8];
9624         u8                                         reserved_at_10[0x30];
9625
9626         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9627         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9628 };
9629
9630 struct mlx5_ifc_nodnic_mac_filters_bits {
9631         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9632
9633         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9634
9635         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9636
9637         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9638
9639         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9640
9641         u8         reserved_0[0xc0];
9642 };
9643
9644 struct mlx5_ifc_nodnic_gid_filters_bits {
9645         u8         mgid_filter0[16][0x8];
9646
9647         u8         mgid_filter1[16][0x8];
9648
9649         u8         mgid_filter2[16][0x8];
9650
9651         u8         mgid_filter3[16][0x8];
9652 };
9653
9654 enum {
9655         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9656         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9657 };
9658
9659 enum {
9660         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9661         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9662 };
9663
9664 struct mlx5_ifc_nodnic_config_reg_bits {
9665         u8         no_dram_nic_revision[0x8];
9666         u8         hardware_format[0x8];
9667         u8         support_receive_filter[0x1];
9668         u8         support_promisc_filter[0x1];
9669         u8         support_promisc_multicast_filter[0x1];
9670         u8         reserved_0[0x2];
9671         u8         log_working_buffer_size[0x3];
9672         u8         log_pkey_table_size[0x4];
9673         u8         reserved_1[0x3];
9674         u8         num_ports[0x1];
9675
9676         u8         reserved_2[0x2];
9677         u8         log_max_ring_size[0x6];
9678         u8         reserved_3[0x18];
9679
9680         u8         lkey[0x20];
9681
9682         u8         cqe_format[0x4];
9683         u8         reserved_4[0x1c];
9684
9685         u8         node_guid[0x40];
9686
9687         u8         reserved_5[0x740];
9688
9689         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9690
9691         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9692 };
9693
9694 struct mlx5_ifc_vlan_layout_bits {
9695         u8         reserved_0[0x14];
9696         u8         vlan[0xc];
9697
9698         u8         reserved_1[0x20];
9699 };
9700
9701 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9702         u8         reserved_0[0x20];
9703
9704         u8         mkey[0x20];
9705
9706         u8         addressh_63_32[0x20];
9707
9708         u8         addressl_31_0[0x20];
9709 };
9710
9711 struct mlx5_ifc_ud_adrs_vector_bits {
9712         u8         dc_key[0x40];
9713
9714         u8         ext[0x1];
9715         u8         reserved_0[0x7];
9716         u8         destination_qp_dct[0x18];
9717
9718         u8         static_rate[0x4];
9719         u8         sl_eth_prio[0x4];
9720         u8         fl[0x1];
9721         u8         mlid[0x7];
9722         u8         rlid_udp_sport[0x10];
9723
9724         u8         reserved_1[0x20];
9725
9726         u8         rmac_47_16[0x20];
9727
9728         u8         rmac_15_0[0x10];
9729         u8         tclass[0x8];
9730         u8         hop_limit[0x8];
9731
9732         u8         reserved_2[0x1];
9733         u8         grh[0x1];
9734         u8         reserved_3[0x2];
9735         u8         src_addr_index[0x8];
9736         u8         flow_label[0x14];
9737
9738         u8         rgid_rip[16][0x8];
9739 };
9740
9741 struct mlx5_ifc_port_module_event_bits {
9742         u8         reserved_0[0x8];
9743         u8         module[0x8];
9744         u8         reserved_1[0xc];
9745         u8         module_status[0x4];
9746
9747         u8         reserved_2[0x14];
9748         u8         error_type[0x4];
9749         u8         reserved_3[0x8];
9750
9751         u8         reserved_4[0xa0];
9752 };
9753
9754 struct mlx5_ifc_icmd_control_bits {
9755         u8         opcode[0x10];
9756         u8         status[0x8];
9757         u8         reserved_0[0x7];
9758         u8         busy[0x1];
9759 };
9760
9761 struct mlx5_ifc_eqe_bits {
9762         u8         reserved_0[0x8];
9763         u8         event_type[0x8];
9764         u8         reserved_1[0x8];
9765         u8         event_sub_type[0x8];
9766
9767         u8         reserved_2[0xe0];
9768
9769         union mlx5_ifc_event_auto_bits event_data;
9770
9771         u8         reserved_3[0x10];
9772         u8         signature[0x8];
9773         u8         reserved_4[0x7];
9774         u8         owner[0x1];
9775 };
9776
9777 enum {
9778         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9779 };
9780
9781 struct mlx5_ifc_cmd_queue_entry_bits {
9782         u8         type[0x8];
9783         u8         reserved_0[0x18];
9784
9785         u8         input_length[0x20];
9786
9787         u8         input_mailbox_pointer_63_32[0x20];
9788
9789         u8         input_mailbox_pointer_31_9[0x17];
9790         u8         reserved_1[0x9];
9791
9792         u8         command_input_inline_data[16][0x8];
9793
9794         u8         command_output_inline_data[16][0x8];
9795
9796         u8         output_mailbox_pointer_63_32[0x20];
9797
9798         u8         output_mailbox_pointer_31_9[0x17];
9799         u8         reserved_2[0x9];
9800
9801         u8         output_length[0x20];
9802
9803         u8         token[0x8];
9804         u8         signature[0x8];
9805         u8         reserved_3[0x8];
9806         u8         status[0x7];
9807         u8         ownership[0x1];
9808 };
9809
9810 struct mlx5_ifc_cmd_out_bits {
9811         u8         status[0x8];
9812         u8         reserved_0[0x18];
9813
9814         u8         syndrome[0x20];
9815
9816         u8         command_output[0x20];
9817 };
9818
9819 struct mlx5_ifc_cmd_in_bits {
9820         u8         opcode[0x10];
9821         u8         reserved_0[0x10];
9822
9823         u8         reserved_1[0x10];
9824         u8         op_mod[0x10];
9825
9826         u8         command[0][0x20];
9827 };
9828
9829 struct mlx5_ifc_cmd_if_box_bits {
9830         u8         mailbox_data[512][0x8];
9831
9832         u8         reserved_0[0x180];
9833
9834         u8         next_pointer_63_32[0x20];
9835
9836         u8         next_pointer_31_10[0x16];
9837         u8         reserved_1[0xa];
9838
9839         u8         block_number[0x20];
9840
9841         u8         reserved_2[0x8];
9842         u8         token[0x8];
9843         u8         ctrl_signature[0x8];
9844         u8         signature[0x8];
9845 };
9846
9847 struct mlx5_ifc_mtt_bits {
9848         u8         ptag_63_32[0x20];
9849
9850         u8         ptag_31_8[0x18];
9851         u8         reserved_0[0x6];
9852         u8         wr_en[0x1];
9853         u8         rd_en[0x1];
9854 };
9855
9856 struct mlx5_ifc_tls_progress_params_bits {
9857         u8         valid[0x1];
9858         u8         reserved_at_1[0x7];
9859         u8         pd[0x18];
9860
9861         u8         next_record_tcp_sn[0x20];
9862
9863         u8         hw_resync_tcp_sn[0x20];
9864
9865         u8         record_tracker_state[0x2];
9866         u8         auth_state[0x2];
9867         u8         reserved_at_64[0x4];
9868         u8         hw_offset_record_number[0x18];
9869 };
9870
9871 struct mlx5_ifc_tls_static_params_bits {
9872         u8         const_2[0x2];
9873         u8         tls_version[0x4];
9874         u8         const_1[0x2];
9875         u8         reserved_at_8[0x14];
9876         u8         encryption_standard[0x4];
9877
9878         u8         reserved_at_20[0x20];
9879
9880         u8         initial_record_number[0x40];
9881
9882         u8         resync_tcp_sn[0x20];
9883
9884         u8         gcm_iv[0x20];
9885
9886         u8         implicit_iv[0x40];
9887
9888         u8         reserved_at_100[0x8];
9889         u8         dek_index[0x18];
9890
9891         u8         reserved_at_120[0xe0];
9892 };
9893
9894 /* Vendor Specific Capabilities, VSC */
9895 enum {
9896         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9897         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9898         MLX5_VSC_DOMAIN_SCAN_CRSPACE            = 0x7,
9899         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9900 };
9901
9902 struct mlx5_ifc_vendor_specific_cap_bits {
9903         u8         type[0x8];
9904         u8         length[0x8];
9905         u8         next_pointer[0x8];
9906         u8         capability_id[0x8];
9907
9908         u8         status[0x3];
9909         u8         reserved_0[0xd];
9910         u8         space[0x10];
9911
9912         u8         counter[0x20];
9913
9914         u8         semaphore[0x20];
9915
9916         u8         flag[0x1];
9917         u8         reserved_1[0x1];
9918         u8         address[0x1e];
9919
9920         u8         data[0x20];
9921 };
9922
9923 struct mlx5_ifc_vsc_space_bits {
9924         u8 status[0x3];
9925         u8 reserved0[0xd];
9926         u8 space[0x10];
9927 };
9928
9929 struct mlx5_ifc_vsc_addr_bits {
9930         u8 flag[0x1];
9931         u8 reserved0[0x1];
9932         u8 address[0x1e];
9933 };
9934
9935 enum {
9936         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9937         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9938         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9939 };
9940
9941 enum {
9942         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9943         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9944         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9945 };
9946
9947 enum {
9948         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9949         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9950         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9951         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9952         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9953         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9954         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9955         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9956         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9957         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9958         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9959 };
9960
9961 struct mlx5_ifc_initial_seg_bits {
9962         u8         fw_rev_minor[0x10];
9963         u8         fw_rev_major[0x10];
9964
9965         u8         cmd_interface_rev[0x10];
9966         u8         fw_rev_subminor[0x10];
9967
9968         u8         reserved_0[0x40];
9969
9970         u8         cmdq_phy_addr_63_32[0x20];
9971
9972         u8         cmdq_phy_addr_31_12[0x14];
9973         u8         reserved_1[0x2];
9974         u8         nic_interface[0x2];
9975         u8         log_cmdq_size[0x4];
9976         u8         log_cmdq_stride[0x4];
9977
9978         u8         command_doorbell_vector[0x20];
9979
9980         u8         reserved_2[0xf00];
9981
9982         u8         initializing[0x1];
9983         u8         reserved_3[0x4];
9984         u8         nic_interface_supported[0x3];
9985         u8         reserved_4[0x18];
9986
9987         struct mlx5_ifc_health_buffer_bits health_buffer;
9988
9989         u8         no_dram_nic_offset[0x20];
9990
9991         u8         reserved_5[0x6de0];
9992
9993         u8         internal_timer_h[0x20];
9994
9995         u8         internal_timer_l[0x20];
9996
9997         u8         reserved_6[0x20];
9998
9999         u8         reserved_7[0x1f];
10000         u8         clear_int[0x1];
10001
10002         u8         health_syndrome[0x8];
10003         u8         health_counter[0x18];
10004
10005         u8         reserved_8[0x17fc0];
10006 };
10007
10008 union mlx5_ifc_icmd_interface_document_bits {
10009         struct mlx5_ifc_fw_version_bits fw_version;
10010         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10011         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10012         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10013         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10014         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10015         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10016         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10017         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10018         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10019         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10020         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10021         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10022         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10023         u8         reserved_0[0x42c0];
10024 };
10025
10026 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10027         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10028         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10029         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10030         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10031         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10032         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10033         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10034         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10035         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10036         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10037         u8         reserved_0[0x7c0];
10038 };
10039
10040 struct mlx5_ifc_ppcnt_reg_bits {
10041         u8         swid[0x8];
10042         u8         local_port[0x8];
10043         u8         pnat[0x2];
10044         u8         reserved_0[0x8];
10045         u8         grp[0x6];
10046
10047         u8         clr[0x1];
10048         u8         reserved_1[0x1c];
10049         u8         prio_tc[0x3];
10050
10051         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10052 };
10053
10054 struct mlx5_ifc_pcie_lanes_counters_bits {
10055         u8         life_time_counter_high[0x20];
10056
10057         u8         life_time_counter_low[0x20];
10058
10059         u8         error_counter_lane0[0x20];
10060
10061         u8         error_counter_lane1[0x20];
10062
10063         u8         error_counter_lane2[0x20];
10064
10065         u8         error_counter_lane3[0x20];
10066
10067         u8         error_counter_lane4[0x20];
10068
10069         u8         error_counter_lane5[0x20];
10070
10071         u8         error_counter_lane6[0x20];
10072
10073         u8         error_counter_lane7[0x20];
10074
10075         u8         error_counter_lane8[0x20];
10076
10077         u8         error_counter_lane9[0x20];
10078
10079         u8         error_counter_lane10[0x20];
10080
10081         u8         error_counter_lane11[0x20];
10082
10083         u8         error_counter_lane12[0x20];
10084
10085         u8         error_counter_lane13[0x20];
10086
10087         u8         error_counter_lane14[0x20];
10088
10089         u8         error_counter_lane15[0x20];
10090
10091         u8         reserved_at_240[0x580];
10092 };
10093
10094 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10095         u8         reserved_at_0[0x40];
10096
10097         u8         error_counter_lane0[0x20];
10098
10099         u8         error_counter_lane1[0x20];
10100
10101         u8         error_counter_lane2[0x20];
10102
10103         u8         error_counter_lane3[0x20];
10104
10105         u8         error_counter_lane4[0x20];
10106
10107         u8         error_counter_lane5[0x20];
10108
10109         u8         error_counter_lane6[0x20];
10110
10111         u8         error_counter_lane7[0x20];
10112
10113         u8         error_counter_lane8[0x20];
10114
10115         u8         error_counter_lane9[0x20];
10116
10117         u8         error_counter_lane10[0x20];
10118
10119         u8         error_counter_lane11[0x20];
10120
10121         u8         error_counter_lane12[0x20];
10122
10123         u8         error_counter_lane13[0x20];
10124
10125         u8         error_counter_lane14[0x20];
10126
10127         u8         error_counter_lane15[0x20];
10128
10129         u8         reserved_at_240[0x580];
10130 };
10131
10132 struct mlx5_ifc_pcie_perf_counters_bits {
10133         u8         life_time_counter_high[0x20];
10134
10135         u8         life_time_counter_low[0x20];
10136
10137         u8         rx_errors[0x20];
10138
10139         u8         tx_errors[0x20];
10140
10141         u8         l0_to_recovery_eieos[0x20];
10142
10143         u8         l0_to_recovery_ts[0x20];
10144
10145         u8         l0_to_recovery_framing[0x20];
10146
10147         u8         l0_to_recovery_retrain[0x20];
10148
10149         u8         crc_error_dllp[0x20];
10150
10151         u8         crc_error_tlp[0x20];
10152
10153         u8         tx_overflow_buffer_pkt[0x40];
10154
10155         u8         outbound_stalled_reads[0x20];
10156
10157         u8         outbound_stalled_writes[0x20];
10158
10159         u8         outbound_stalled_reads_events[0x20];
10160
10161         u8         outbound_stalled_writes_events[0x20];
10162
10163         u8         tx_overflow_buffer_marked_pkt[0x40];
10164
10165         u8         reserved_at_240[0x580];
10166 };
10167
10168 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10169         u8         reserved_at_0[0x40];
10170
10171         u8         rx_errors[0x20];
10172
10173         u8         tx_errors[0x20];
10174
10175         u8         reserved_at_80[0xc0];
10176
10177         u8         tx_overflow_buffer_pkt[0x40];
10178
10179         u8         outbound_stalled_reads[0x20];
10180
10181         u8         outbound_stalled_writes[0x20];
10182
10183         u8         outbound_stalled_reads_events[0x20];
10184
10185         u8         outbound_stalled_writes_events[0x20];
10186
10187         u8         tx_overflow_buffer_marked_pkt[0x40];
10188
10189         u8         reserved_at_240[0x580];
10190 };
10191
10192 struct mlx5_ifc_pcie_timers_states_bits {
10193         u8         life_time_counter_high[0x20];
10194
10195         u8         life_time_counter_low[0x20];
10196
10197         u8         time_to_boot_image_start[0x20];
10198
10199         u8         time_to_link_image[0x20];
10200
10201         u8         calibration_time[0x20];
10202
10203         u8         time_to_first_perst[0x20];
10204
10205         u8         time_to_detect_state[0x20];
10206
10207         u8         time_to_l0[0x20];
10208
10209         u8         time_to_crs_en[0x20];
10210
10211         u8         time_to_plastic_image_start[0x20];
10212
10213         u8         time_to_iron_image_start[0x20];
10214
10215         u8         perst_handler[0x20];
10216
10217         u8         times_in_l1[0x20];
10218
10219         u8         times_in_l23[0x20];
10220
10221         u8         dl_down[0x20];
10222
10223         u8         config_cycle1usec[0x20];
10224
10225         u8         config_cycle2to7usec[0x20];
10226
10227         u8         config_cycle8to15usec[0x20];
10228
10229         u8         config_cycle16to63usec[0x20];
10230
10231         u8         config_cycle64usec[0x20];
10232
10233         u8         correctable_err_msg_sent[0x20];
10234
10235         u8         non_fatal_err_msg_sent[0x20];
10236
10237         u8         fatal_err_msg_sent[0x20];
10238
10239         u8         reserved_at_2e0[0x4e0];
10240 };
10241
10242 struct mlx5_ifc_pcie_timers_states_ext_bits {
10243         u8         reserved_at_0[0x40];
10244
10245         u8         time_to_boot_image_start[0x20];
10246
10247         u8         time_to_link_image[0x20];
10248
10249         u8         calibration_time[0x20];
10250
10251         u8         time_to_first_perst[0x20];
10252
10253         u8         time_to_detect_state[0x20];
10254
10255         u8         time_to_l0[0x20];
10256
10257         u8         time_to_crs_en[0x20];
10258
10259         u8         time_to_plastic_image_start[0x20];
10260
10261         u8         time_to_iron_image_start[0x20];
10262
10263         u8         perst_handler[0x20];
10264
10265         u8         times_in_l1[0x20];
10266
10267         u8         times_in_l23[0x20];
10268
10269         u8         dl_down[0x20];
10270
10271         u8         config_cycle1usec[0x20];
10272
10273         u8         config_cycle2to7usec[0x20];
10274
10275         u8         config_cycle8to15usec[0x20];
10276
10277         u8         config_cycle16to63usec[0x20];
10278
10279         u8         config_cycle64usec[0x20];
10280
10281         u8         correctable_err_msg_sent[0x20];
10282
10283         u8         non_fatal_err_msg_sent[0x20];
10284
10285         u8         fatal_err_msg_sent[0x20];
10286
10287         u8         reserved_at_2e0[0x4e0];
10288 };
10289
10290 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10291         struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10292         struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10293         struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10294         u8         reserved_at_0[0x7c0];
10295 };
10296
10297 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10298         struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10299         struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10300         struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10301         u8         reserved_at_0[0x7c0];
10302 };
10303
10304 struct mlx5_ifc_mpcnt_reg_bits {
10305         u8         reserved_at_0[0x2];
10306         u8         depth[0x6];
10307         u8         pcie_index[0x8];
10308         u8         node[0x8];
10309         u8         reserved_at_18[0x2];
10310         u8         grp[0x6];
10311
10312         u8         clr[0x1];
10313         u8         reserved_at_21[0x1f];
10314
10315         union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10316 };
10317
10318 struct mlx5_ifc_mpcnt_reg_ext_bits {
10319         u8         reserved_at_0[0x2];
10320         u8         depth[0x6];
10321         u8         pcie_index[0x8];
10322         u8         node[0x8];
10323         u8         reserved_at_18[0x2];
10324         u8         grp[0x6];
10325
10326         u8         clr[0x1];
10327         u8         reserved_at_21[0x1f];
10328
10329         union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10330 };
10331
10332 struct mlx5_ifc_monitor_opcodes_layout_bits {
10333         u8         reserved_at_0[0x10];
10334         u8         monitor_opcode[0x10];
10335 };
10336
10337 union mlx5_ifc_pddr_status_opcode_bits {
10338         struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
10339         u8         reserved_at_0[0x20];
10340 };
10341
10342 struct mlx5_ifc_troubleshooting_info_page_layout_bits {
10343         u8         reserved_at_0[0x10];
10344         u8         group_opcode[0x10];
10345
10346         union mlx5_ifc_pddr_status_opcode_bits status_opcode;
10347
10348         u8         user_feedback_data[0x10];
10349         u8         user_feedback_index[0x10];
10350
10351         u8         status_message[0x760];
10352 };
10353
10354 union mlx5_ifc_pddr_page_data_bits {
10355         struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
10356         struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
10357         u8         reserved_at_0[0x7c0];
10358 };
10359
10360 struct mlx5_ifc_pddr_reg_bits {
10361         u8         reserved_at_0[0x8];
10362         u8         local_port[0x8];
10363         u8         pnat[0x2];
10364         u8         reserved_at_12[0xe];
10365
10366         u8         reserved_at_20[0x18];
10367         u8         page_select[0x8];
10368
10369         union mlx5_ifc_pddr_page_data_bits page_data;
10370 };
10371
10372 enum {
10373         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10374         MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10375         MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10376         MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10377 };
10378
10379 struct mlx5_ifc_mpein_reg_bits {
10380         u8         reserved_at_0[0x2];
10381         u8         depth[0x6];
10382         u8         pcie_index[0x8];
10383         u8         node[0x8];
10384         u8         reserved_at_18[0x8];
10385
10386         u8         capability_mask[0x20];
10387
10388         u8         reserved_at_40[0x8];
10389         u8         link_width_enabled[0x8];
10390         u8         link_speed_enabled[0x10];
10391
10392         u8         lane0_physical_position[0x8];
10393         u8         link_width_active[0x8];
10394         u8         link_speed_active[0x10];
10395
10396         u8         num_of_pfs[0x10];
10397         u8         num_of_vfs[0x10];
10398
10399         u8         bdf0[0x10];
10400         u8         reserved_at_b0[0x10];
10401
10402         u8         max_read_request_size[0x4];
10403         u8         max_payload_size[0x4];
10404         u8         reserved_at_c8[0x5];
10405         u8         pwr_status[0x3];
10406         u8         port_type[0x4];
10407         u8         reserved_at_d4[0xb];
10408         u8         lane_reversal[0x1];
10409
10410         u8         reserved_at_e0[0x14];
10411         u8         pci_power[0xc];
10412
10413         u8         reserved_at_100[0x20];
10414
10415         u8         device_status[0x10];
10416         u8         port_state[0x8];
10417         u8         reserved_at_138[0x8];
10418
10419         u8         reserved_at_140[0x10];
10420         u8         receiver_detect_result[0x10];
10421
10422         u8         reserved_at_160[0x20];
10423 };
10424
10425 struct mlx5_ifc_mpein_reg_ext_bits {
10426         u8         reserved_at_0[0x2];
10427         u8         depth[0x6];
10428         u8         pcie_index[0x8];
10429         u8         node[0x8];
10430         u8         reserved_at_18[0x8];
10431
10432         u8         reserved_at_20[0x20];
10433
10434         u8         reserved_at_40[0x8];
10435         u8         link_width_enabled[0x8];
10436         u8         link_speed_enabled[0x10];
10437
10438         u8         lane0_physical_position[0x8];
10439         u8         link_width_active[0x8];
10440         u8         link_speed_active[0x10];
10441
10442         u8         num_of_pfs[0x10];
10443         u8         num_of_vfs[0x10];
10444
10445         u8         bdf0[0x10];
10446         u8         reserved_at_b0[0x10];
10447
10448         u8         max_read_request_size[0x4];
10449         u8         max_payload_size[0x4];
10450         u8         reserved_at_c8[0x5];
10451         u8         pwr_status[0x3];
10452         u8         port_type[0x4];
10453         u8         reserved_at_d4[0xb];
10454         u8         lane_reversal[0x1];
10455 };
10456
10457 struct mlx5_ifc_mcqi_cap_bits {
10458         u8         supported_info_bitmask[0x20];
10459
10460         u8         component_size[0x20];
10461
10462         u8         max_component_size[0x20];
10463
10464         u8         log_mcda_word_size[0x4];
10465         u8         reserved_at_64[0xc];
10466         u8         mcda_max_write_size[0x10];
10467
10468         u8         rd_en[0x1];
10469         u8         reserved_at_81[0x1];
10470         u8         match_chip_id[0x1];
10471         u8         match_psid[0x1];
10472         u8         check_user_timestamp[0x1];
10473         u8         match_base_guid_mac[0x1];
10474         u8         reserved_at_86[0x1a];
10475 };
10476
10477 struct mlx5_ifc_mcqi_reg_bits {
10478         u8         read_pending_component[0x1];
10479         u8         reserved_at_1[0xf];
10480         u8         component_index[0x10];
10481
10482         u8         reserved_at_20[0x20];
10483
10484         u8         reserved_at_40[0x1b];
10485         u8         info_type[0x5];
10486
10487         u8         info_size[0x20];
10488
10489         u8         offset[0x20];
10490
10491         u8         reserved_at_a0[0x10];
10492         u8         data_size[0x10];
10493
10494         u8         data[0][0x20];
10495 };
10496
10497 struct mlx5_ifc_mcc_reg_bits {
10498         u8         reserved_at_0[0x4];
10499         u8         time_elapsed_since_last_cmd[0xc];
10500         u8         reserved_at_10[0x8];
10501         u8         instruction[0x8];
10502
10503         u8         reserved_at_20[0x10];
10504         u8         component_index[0x10];
10505
10506         u8         reserved_at_40[0x8];
10507         u8         update_handle[0x18];
10508
10509         u8         handle_owner_type[0x4];
10510         u8         handle_owner_host_id[0x4];
10511         u8         reserved_at_68[0x1];
10512         u8         control_progress[0x7];
10513         u8         error_code[0x8];
10514         u8         reserved_at_78[0x4];
10515         u8         control_state[0x4];
10516
10517         u8         component_size[0x20];
10518
10519         u8         reserved_at_a0[0x60];
10520 };
10521
10522 struct mlx5_ifc_mcda_reg_bits {
10523         u8         reserved_at_0[0x8];
10524         u8         update_handle[0x18];
10525
10526         u8         offset[0x20];
10527
10528         u8         reserved_at_40[0x10];
10529         u8         size[0x10];
10530
10531         u8         reserved_at_60[0x20];
10532
10533         u8         data[0][0x20];
10534 };
10535
10536 union mlx5_ifc_ports_control_registers_document_bits {
10537         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10538         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10539         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10540         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10541         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10542         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10543         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10544         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10545         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10546         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10547         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10548         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10549         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10550         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10551         struct mlx5_ifc_paos_reg_bits paos_reg;
10552         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10553         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10554         struct mlx5_ifc_peir_reg_bits peir_reg;
10555         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10556         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10557         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10558         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10559         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10560         struct mlx5_ifc_phrr_reg_bits phrr_reg;
10561         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10562         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10563         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10564         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10565         struct mlx5_ifc_plib_reg_bits plib_reg;
10566         struct mlx5_ifc_pll_status_data_bits pll_status_data;
10567         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10568         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10569         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10570         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10571         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10572         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10573         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10574         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10575         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10576         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10577         struct mlx5_ifc_ppll_reg_bits ppll_reg;
10578         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10579         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10580         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10581         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10582         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10583         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10584         struct mlx5_ifc_pude_reg_bits pude_reg;
10585         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10586         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10587         struct mlx5_ifc_slrp_reg_bits slrp_reg;
10588         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10589         u8         reserved_0[0x7880];
10590 };
10591
10592 union mlx5_ifc_debug_enhancements_document_bits {
10593         struct mlx5_ifc_health_buffer_bits health_buffer;
10594         u8         reserved_0[0x200];
10595 };
10596
10597 union mlx5_ifc_no_dram_nic_document_bits {
10598         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10599         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10600         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10601         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10602         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10603         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10604         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10605         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10606         u8         reserved_0[0x3160];
10607 };
10608
10609 union mlx5_ifc_uplink_pci_interface_document_bits {
10610         struct mlx5_ifc_initial_seg_bits initial_seg;
10611         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10612         u8         reserved_0[0x20120];
10613 };
10614
10615 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10616         u8         e[0x1];
10617         u8         reserved_at_01[0x0b];
10618         u8         prio[0x04];
10619 };
10620
10621 struct mlx5_ifc_qpdpm_reg_bits {
10622         u8                                     reserved_at_0[0x8];
10623         u8                                     local_port[0x8];
10624         u8                                     reserved_at_10[0x10];
10625         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10626 };
10627
10628 struct mlx5_ifc_qpts_reg_bits {
10629         u8         reserved_at_0[0x8];
10630         u8         local_port[0x8];
10631         u8         reserved_at_10[0x2d];
10632         u8         trust_state[0x3];
10633 };
10634
10635 struct mlx5_ifc_mfrl_reg_bits {
10636         u8         reserved_at_0[0x38];
10637         u8         reset_level[0x8];
10638 };
10639
10640 enum {
10641       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP     = 0x9009,
10642       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR     = 0x9109,
10643       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP      = 0x900a,
10644       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE      = 0x900b,
10645       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR      = 0x900f,
10646       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE     = 0x910b,
10647       MLX5_MAX_TEMPERATURE = 16,
10648 };
10649
10650 struct mlx5_ifc_mtbr_temp_record_bits {
10651         u8         max_temperature[0x10];
10652         u8         temperature[0x10];
10653 };
10654
10655 struct mlx5_ifc_mtbr_reg_bits {
10656         u8         reserved_at_0[0x14];
10657         u8         base_sensor_index[0xc];
10658
10659         u8         reserved_at_20[0x18];
10660         u8         num_rec[0x8];
10661
10662         u8         reserved_at_40[0x40];
10663
10664         struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10665 };
10666
10667 struct mlx5_ifc_mtbr_reg_ext_bits {
10668         u8         reserved_at_0[0x14];
10669         u8         base_sensor_index[0xc];
10670
10671         u8         reserved_at_20[0x18];
10672         u8         num_rec[0x8];
10673
10674         u8         reserved_at_40[0x40];
10675
10676     struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10677 };
10678
10679 struct mlx5_ifc_mtcap_bits {
10680         u8         reserved_at_0[0x19];
10681         u8         sensor_count[0x7];
10682
10683         u8         reserved_at_20[0x19];
10684         u8         internal_sensor_count[0x7];
10685
10686         u8         sensor_map[0x40];
10687 };
10688
10689 struct mlx5_ifc_mtcap_ext_bits {
10690         u8         reserved_at_0[0x19];
10691         u8         sensor_count[0x7];
10692
10693         u8         reserved_at_20[0x20];
10694
10695         u8         sensor_map[0x40];
10696 };
10697
10698 struct mlx5_ifc_mtecr_bits {
10699         u8         reserved_at_0[0x4];
10700         u8         last_sensor[0xc];
10701         u8         reserved_at_10[0x4];
10702         u8         sensor_count[0xc];
10703
10704         u8         reserved_at_20[0x19];
10705         u8         internal_sensor_count[0x7];
10706
10707         u8         sensor_map_0[0x20];
10708
10709         u8         reserved_at_60[0x2a0];
10710 };
10711
10712 struct mlx5_ifc_mtecr_ext_bits {
10713         u8         reserved_at_0[0x4];
10714         u8         last_sensor[0xc];
10715         u8         reserved_at_10[0x4];
10716         u8         sensor_count[0xc];
10717
10718         u8         reserved_at_20[0x20];
10719
10720         u8         sensor_map_0[0x20];
10721
10722         u8         reserved_at_60[0x2a0];
10723 };
10724
10725 struct mlx5_ifc_mtewe_bits {
10726         u8         reserved_at_0[0x4];
10727         u8         last_sensor[0xc];
10728         u8         reserved_at_10[0x4];
10729         u8         sensor_count[0xc];
10730
10731         u8         sensor_warning_0[0x20];
10732
10733         u8         reserved_at_40[0x2a0];
10734 };
10735
10736 struct mlx5_ifc_mtewe_ext_bits {
10737         u8         reserved_at_0[0x4];
10738         u8         last_sensor[0xc];
10739         u8         reserved_at_10[0x4];
10740         u8         sensor_count[0xc];
10741
10742         u8         sensor_warning_0[0x20];
10743
10744         u8         reserved_at_40[0x2a0];
10745 };
10746
10747 struct mlx5_ifc_mtmp_bits {
10748         u8         reserved_at_0[0x14];
10749         u8         sensor_index[0xc];
10750
10751         u8         reserved_at_20[0x10];
10752         u8         temperature[0x10];
10753
10754         u8         mte[0x1];
10755         u8         mtr[0x1];
10756         u8         reserved_at_42[0xe];
10757         u8         max_temperature[0x10];
10758
10759         u8         tee[0x2];
10760         u8         reserved_at_62[0xe];
10761         u8         temperature_threshold_hi[0x10];
10762
10763         u8         reserved_at_80[0x10];
10764         u8         temperature_threshold_lo[0x10];
10765
10766         u8         reserved_at_a0[0x20];
10767
10768         u8         sensor_name_hi[0x20];
10769
10770         u8         sensor_name_lo[0x20];
10771 };
10772
10773 struct mlx5_ifc_mtmp_ext_bits {
10774         u8         reserved_at_0[0x14];
10775         u8         sensor_index[0xc];
10776
10777         u8         reserved_at_20[0x10];
10778         u8         temperature[0x10];
10779
10780         u8         mte[0x1];
10781         u8         mtr[0x1];
10782         u8         reserved_at_42[0xe];
10783         u8         max_temperature[0x10];
10784
10785         u8         tee[0x2];
10786         u8         reserved_at_62[0xe];
10787         u8         temperature_threshold_hi[0x10];
10788
10789         u8         reserved_at_80[0x10];
10790         u8         temperature_threshold_lo[0x10];
10791
10792         u8         reserved_at_a0[0x20];
10793
10794         u8         sensor_name_hi[0x20];
10795
10796         u8         sensor_name_lo[0x20];
10797 };
10798
10799 #endif /* MLX5_IFC_H */