2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 MLX5_EVENT_TYPE_COMP = 0x0,
33 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
34 MLX5_EVENT_TYPE_COMM_EST = 0x2,
35 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
36 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
37 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
38 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
39 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
40 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
41 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5,
42 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
43 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
44 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
45 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
46 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
47 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8,
48 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9,
49 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
50 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16,
51 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17,
52 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
53 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
54 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
55 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
56 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
57 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
58 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
59 MLX5_EVENT_TYPE_CMD = 0xa,
60 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
61 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd
65 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
66 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
67 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
68 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
69 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4
73 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1,
77 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
78 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
82 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
83 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
84 MLX5_CMD_OP_INIT_HCA = 0x102,
85 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
86 MLX5_CMD_OP_ENABLE_HCA = 0x104,
87 MLX5_CMD_OP_DISABLE_HCA = 0x105,
88 MLX5_CMD_OP_QUERY_PAGES = 0x107,
89 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
90 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
91 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
92 MLX5_CMD_OP_SET_ISSI = 0x10b,
93 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
94 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
95 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
96 MLX5_CMD_OP_CREATE_MKEY = 0x200,
97 MLX5_CMD_OP_QUERY_MKEY = 0x201,
98 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
101 MLX5_CMD_OP_CREATE_EQ = 0x301,
102 MLX5_CMD_OP_DESTROY_EQ = 0x302,
103 MLX5_CMD_OP_QUERY_EQ = 0x303,
104 MLX5_CMD_OP_GEN_EQE = 0x304,
105 MLX5_CMD_OP_CREATE_CQ = 0x400,
106 MLX5_CMD_OP_DESTROY_CQ = 0x401,
107 MLX5_CMD_OP_QUERY_CQ = 0x402,
108 MLX5_CMD_OP_MODIFY_CQ = 0x403,
109 MLX5_CMD_OP_CREATE_QP = 0x500,
110 MLX5_CMD_OP_DESTROY_QP = 0x501,
111 MLX5_CMD_OP_RST2INIT_QP = 0x502,
112 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
113 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
114 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
115 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
116 MLX5_CMD_OP_2ERR_QP = 0x507,
117 MLX5_CMD_OP_2RST_QP = 0x50a,
118 MLX5_CMD_OP_QUERY_QP = 0x50b,
119 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
120 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
121 MLX5_CMD_OP_CREATE_PSV = 0x600,
122 MLX5_CMD_OP_DESTROY_PSV = 0x601,
123 MLX5_CMD_OP_CREATE_SRQ = 0x700,
124 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
125 MLX5_CMD_OP_QUERY_SRQ = 0x702,
126 MLX5_CMD_OP_ARM_RQ = 0x703,
127 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
128 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
129 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
130 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
131 MLX5_CMD_OP_CREATE_DCT = 0x710,
132 MLX5_CMD_OP_DESTROY_DCT = 0x711,
133 MLX5_CMD_OP_DRAIN_DCT = 0x712,
134 MLX5_CMD_OP_QUERY_DCT = 0x713,
135 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
136 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715,
137 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
138 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
139 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
140 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
141 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
142 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
143 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
144 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
145 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
147 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
148 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
149 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
154 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
162 MLX5_CMD_OP_ALLOC_PD = 0x800,
163 MLX5_CMD_OP_DEALLOC_PD = 0x801,
164 MLX5_CMD_OP_ALLOC_UAR = 0x802,
165 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
167 MLX5_CMD_OP_ACCESS_REG = 0x805,
168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
171 MLX5_CMD_OP_MAD_IFC = 0x50d,
172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
174 MLX5_CMD_OP_NOP = 0x80d,
175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
177 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
178 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
179 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
180 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
181 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
182 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
183 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820,
184 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821,
185 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
186 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
187 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
188 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
189 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
190 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
191 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
192 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
193 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
194 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
195 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
196 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
197 MLX5_CMD_OP_CREATE_LAG = 0x840,
198 MLX5_CMD_OP_MODIFY_LAG = 0x841,
199 MLX5_CMD_OP_QUERY_LAG = 0x842,
200 MLX5_CMD_OP_DESTROY_LAG = 0x843,
201 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
202 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
203 MLX5_CMD_OP_CREATE_TIR = 0x900,
204 MLX5_CMD_OP_MODIFY_TIR = 0x901,
205 MLX5_CMD_OP_DESTROY_TIR = 0x902,
206 MLX5_CMD_OP_QUERY_TIR = 0x903,
207 MLX5_CMD_OP_CREATE_SQ = 0x904,
208 MLX5_CMD_OP_MODIFY_SQ = 0x905,
209 MLX5_CMD_OP_DESTROY_SQ = 0x906,
210 MLX5_CMD_OP_QUERY_SQ = 0x907,
211 MLX5_CMD_OP_CREATE_RQ = 0x908,
212 MLX5_CMD_OP_MODIFY_RQ = 0x909,
213 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
214 MLX5_CMD_OP_QUERY_RQ = 0x90b,
215 MLX5_CMD_OP_CREATE_RMP = 0x90c,
216 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
217 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
218 MLX5_CMD_OP_QUERY_RMP = 0x90f,
219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
220 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
221 MLX5_CMD_OP_CREATE_TIS = 0x912,
222 MLX5_CMD_OP_MODIFY_TIS = 0x913,
223 MLX5_CMD_OP_DESTROY_TIS = 0x914,
224 MLX5_CMD_OP_QUERY_TIS = 0x915,
225 MLX5_CMD_OP_CREATE_RQT = 0x916,
226 MLX5_CMD_OP_MODIFY_RQT = 0x917,
227 MLX5_CMD_OP_DESTROY_RQT = 0x918,
228 MLX5_CMD_OP_QUERY_RQT = 0x919,
229 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
230 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
231 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
232 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
233 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
234 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
235 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
236 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
237 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
238 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
239 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
240 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
241 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
242 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
243 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
244 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
248 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007,
249 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400,
250 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001,
251 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003,
252 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004,
253 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005,
254 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006,
255 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007,
256 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
257 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009,
258 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a,
259 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004
262 struct mlx5_ifc_flow_table_fields_supported_bits {
265 u8 outer_ether_type[0x1];
267 u8 outer_first_prio[0x1];
268 u8 outer_first_cfi[0x1];
269 u8 outer_first_vid[0x1];
271 u8 outer_second_prio[0x1];
272 u8 outer_second_cfi[0x1];
273 u8 outer_second_vid[0x1];
274 u8 outer_ipv6_flow_label[0x1];
278 u8 outer_ip_protocol[0x1];
279 u8 outer_ip_ecn[0x1];
280 u8 outer_ip_dscp[0x1];
281 u8 outer_udp_sport[0x1];
282 u8 outer_udp_dport[0x1];
283 u8 outer_tcp_sport[0x1];
284 u8 outer_tcp_dport[0x1];
285 u8 outer_tcp_flags[0x1];
286 u8 outer_gre_protocol[0x1];
287 u8 outer_gre_key[0x1];
288 u8 outer_vxlan_vni[0x1];
289 u8 outer_geneve_vni[0x1];
290 u8 outer_geneve_oam[0x1];
291 u8 outer_geneve_protocol_type[0x1];
292 u8 outer_geneve_opt_len[0x1];
294 u8 source_eswitch_port[0x1];
298 u8 inner_ether_type[0x1];
300 u8 inner_first_prio[0x1];
301 u8 inner_first_cfi[0x1];
302 u8 inner_first_vid[0x1];
304 u8 inner_second_prio[0x1];
305 u8 inner_second_cfi[0x1];
306 u8 inner_second_vid[0x1];
307 u8 inner_ipv6_flow_label[0x1];
311 u8 inner_ip_protocol[0x1];
312 u8 inner_ip_ecn[0x1];
313 u8 inner_ip_dscp[0x1];
314 u8 inner_udp_sport[0x1];
315 u8 inner_udp_dport[0x1];
316 u8 inner_tcp_sport[0x1];
317 u8 inner_tcp_dport[0x1];
318 u8 inner_tcp_flags[0x1];
329 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
330 u8 ingress_general_high[0x20];
332 u8 ingress_general_low[0x20];
334 u8 ingress_policy_engine_high[0x20];
336 u8 ingress_policy_engine_low[0x20];
338 u8 ingress_vlan_membership_high[0x20];
340 u8 ingress_vlan_membership_low[0x20];
342 u8 ingress_tag_frame_type_high[0x20];
344 u8 ingress_tag_frame_type_low[0x20];
346 u8 egress_vlan_membership_high[0x20];
348 u8 egress_vlan_membership_low[0x20];
350 u8 loopback_filter_high[0x20];
352 u8 loopback_filter_low[0x20];
354 u8 egress_general_high[0x20];
356 u8 egress_general_low[0x20];
358 u8 reserved_at_1c0[0x40];
360 u8 egress_hoq_high[0x20];
362 u8 egress_hoq_low[0x20];
364 u8 port_isolation_high[0x20];
366 u8 port_isolation_low[0x20];
368 u8 egress_policy_engine_high[0x20];
370 u8 egress_policy_engine_low[0x20];
372 u8 ingress_tx_link_down_high[0x20];
374 u8 ingress_tx_link_down_low[0x20];
376 u8 egress_stp_filter_high[0x20];
378 u8 egress_stp_filter_low[0x20];
380 u8 egress_hoq_stall_high[0x20];
382 u8 egress_hoq_stall_low[0x20];
384 u8 reserved_at_340[0x440];
386 struct mlx5_ifc_flow_table_prop_layout_bits {
389 u8 flow_counter[0x1];
390 u8 flow_modify_en[0x1];
392 u8 identified_miss_table[0x1];
393 u8 flow_table_modify[0x1];
396 u8 reset_root_to_default[0x1];
397 u8 reserved_at_a[0x16];
399 u8 reserved_at_20[0x2];
400 u8 log_max_ft_size[0x6];
401 u8 reserved_at_28[0x10];
402 u8 max_ft_level[0x8];
404 u8 reserved_at_40[0x20];
406 u8 reserved_at_60[0x18];
407 u8 log_max_ft_num[0x8];
409 u8 reserved_at_80[0x10];
410 u8 log_max_flow_counter[0x8];
411 u8 log_max_destination[0x8];
413 u8 reserved_at_a0[0x18];
414 u8 log_max_flow[0x8];
416 u8 reserved_at_c0[0x40];
418 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
420 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
423 struct mlx5_ifc_odp_per_transport_service_cap_bits {
433 struct mlx5_ifc_flow_counter_list_bits {
435 u8 flow_counter_id[0x10];
441 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,
442 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1,
443 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2,
444 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
447 struct mlx5_ifc_dest_format_struct_bits {
448 u8 destination_type[0x8];
449 u8 destination_id[0x18];
454 struct mlx5_ifc_ipv4_layout_bits {
455 u8 reserved_at_0[0x60];
460 struct mlx5_ifc_ipv6_layout_bits {
464 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
465 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
466 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
467 u8 reserved_at_0[0x80];
470 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
500 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
505 struct mlx5_ifc_fte_match_set_misc_bits {
510 u8 source_port[0x10];
512 u8 outer_second_prio[0x3];
513 u8 outer_second_cfi[0x1];
514 u8 outer_second_vid[0xc];
515 u8 inner_second_prio[0x3];
516 u8 inner_second_cfi[0x1];
517 u8 inner_second_vid[0xc];
519 u8 outer_second_vlan_tag[0x1];
520 u8 inner_second_vlan_tag[0x1];
522 u8 gre_protocol[0x10];
535 u8 outer_ipv6_flow_label[0x14];
538 u8 inner_ipv6_flow_label[0x14];
541 u8 geneve_opt_len[0x6];
542 u8 geneve_protocol_type[0x10];
550 struct mlx5_ifc_cmd_pas_bits {
557 struct mlx5_ifc_uint64_bits {
563 struct mlx5_ifc_application_prio_entry_bits {
568 u8 protocol_id[0x10];
571 struct mlx5_ifc_nodnic_ring_doorbell_bits {
578 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
579 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
580 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
581 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
582 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
583 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
584 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
585 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
586 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
587 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
590 struct mlx5_ifc_ads_bits {
603 u8 src_addr_index[0x8];
612 u8 rgid_rip[16][0x8];
632 struct mlx5_ifc_diagnostic_counter_cap_bits {
638 struct mlx5_ifc_debug_cap_bits {
640 u8 log_max_samples[0x8];
644 u8 health_mon_rx_activity[0x1];
646 u8 log_min_sample_period[0x8];
648 u8 reserved_2[0x1c0];
650 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
653 struct mlx5_ifc_qos_cap_bits {
654 u8 packet_pacing[0x1];
655 u8 esw_scheduling[0x1];
656 u8 esw_bw_share[0x1];
657 u8 esw_rate_limit[0x1];
659 u8 packet_pacing_burst_bound[0x1];
660 u8 reserved_at_6[0x1a];
662 u8 reserved_at_20[0x20];
664 u8 packet_pacing_max_rate[0x20];
666 u8 packet_pacing_min_rate[0x20];
668 u8 reserved_at_80[0x10];
669 u8 packet_pacing_rate_table_size[0x10];
671 u8 esw_element_type[0x10];
672 u8 esw_tsar_type[0x10];
674 u8 reserved_at_c0[0x10];
675 u8 max_qos_para_vport[0x10];
677 u8 max_tsar_bw_share[0x20];
679 u8 reserved_at_100[0x700];
682 struct mlx5_ifc_snapshot_cap_bits {
684 u8 suspend_qp_uc[0x1];
685 u8 suspend_qp_ud[0x1];
686 u8 suspend_qp_rc[0x1];
691 u8 restore_mkey[0x1];
698 u8 reserved_3[0x7a0];
701 struct mlx5_ifc_e_switch_cap_bits {
702 u8 vport_svlan_strip[0x1];
703 u8 vport_cvlan_strip[0x1];
704 u8 vport_svlan_insert[0x1];
705 u8 vport_cvlan_insert_if_not_exist[0x1];
706 u8 vport_cvlan_insert_overwrite[0x1];
710 u8 nic_vport_node_guid_modify[0x1];
711 u8 nic_vport_port_guid_modify[0x1];
713 u8 reserved_1[0x7e0];
716 struct mlx5_ifc_flow_table_eswitch_cap_bits {
717 u8 reserved_0[0x200];
719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
721 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
723 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
725 u8 reserved_1[0x7800];
728 struct mlx5_ifc_flow_table_nic_cap_bits {
729 u8 nic_rx_multi_path_tirs[0x1];
730 u8 nic_rx_multi_path_tirs_fts[0x1];
731 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
732 u8 reserved_at_3[0x1fd];
734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
740 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
742 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
746 u8 reserved_1[0x7200];
749 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
753 u8 lro_psh_flag[0x1];
754 u8 lro_time_stamp[0x1];
755 u8 lro_max_msg_sz_mode[0x2];
756 u8 wqe_vlan_insert[0x1];
757 u8 self_lb_en_modifiable[0x1];
761 u8 multi_pkt_send_wqe[0x2];
762 u8 wqe_inline_mode[0x2];
763 u8 rss_ind_tbl_cap[0x4];
766 u8 tunnel_lso_const_out_ip_id[0x1];
767 u8 tunnel_lro_gre[0x1];
768 u8 tunnel_lro_vxlan[0x1];
769 u8 tunnel_statless_gre[0x1];
770 u8 tunnel_stateless_vxlan[0x1];
776 u8 max_geneve_opt_len[0x1];
777 u8 tunnel_stateless_geneve_rx[0x1];
780 u8 lro_min_mss_size[0x10];
782 u8 reserved_4[0x120];
784 u8 lro_timer_supported_periods[4][0x20];
786 u8 reserved_5[0x600];
790 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1,
791 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2,
792 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
795 struct mlx5_ifc_roce_cap_bits {
797 u8 rts2rts_primary_eth_prio[0x1];
798 u8 roce_rx_allow_untagged[0x1];
799 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
808 u8 roce_version[0x8];
811 u8 r_roce_dest_udp_port[0x10];
813 u8 r_roce_max_src_udp_port[0x10];
814 u8 r_roce_min_src_udp_port[0x10];
817 u8 roce_address_table_size[0x10];
819 u8 reserved_6[0x700];
823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1,
824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
831 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
843 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
846 struct mlx5_ifc_atomic_caps_bits {
849 u8 atomic_req_8B_endianess_mode[0x2];
851 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
858 u8 atomic_operations[0x10];
861 u8 atomic_size_qp[0x10];
864 u8 atomic_size_dc[0x10];
866 u8 reserved_7[0x720];
869 struct mlx5_ifc_odp_cap_bits {
877 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
879 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
881 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
883 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
885 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
887 u8 reserved_3[0x6e0];
891 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
892 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
893 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
894 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
895 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
899 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
900 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
901 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
902 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
903 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
904 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
908 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
909 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
913 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
914 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
915 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
918 struct mlx5_ifc_cmd_hca_cap_bits {
921 u8 log_max_srq_sz[0x8];
922 u8 log_max_qp_sz[0x8];
931 u8 log_max_cq_sz[0x8];
935 u8 log_max_eq_sz[0x8];
937 u8 log_max_mkey[0x6];
941 u8 max_indirection[0x8];
943 u8 log_max_mrw_sz[0x7];
944 u8 force_teardown[0x1];
946 u8 log_max_bsf_list_size[0x6];
948 u8 log_max_klm_list_size[0x6];
951 u8 log_max_ra_req_dc[0x6];
953 u8 log_max_ra_res_dc[0x6];
956 u8 log_max_ra_req_qp[0x6];
958 u8 log_max_ra_res_qp[0x6];
961 u8 cc_query_allowed[0x1];
962 u8 cc_modify_allowed[0x1];
964 u8 cache_line_128byte[0x1];
966 u8 gid_table_size[0x10];
968 u8 out_of_seq_cnt[0x1];
969 u8 vport_counters[0x1];
970 u8 retransmission_q_counters[0x1];
972 u8 modify_rq_counters_set_id[0x1];
973 u8 rq_delay_drop[0x1];
975 u8 pkey_table_size[0x10];
977 u8 vport_group_manager[0x1];
978 u8 vhca_group_manager[0x1];
983 u8 nic_flow_table[0x1];
984 u8 eswitch_flow_table[0x1];
986 u8 local_ca_ack_delay[0x5];
987 u8 port_module_event[0x1];
997 u8 temp_warn_event[0x1];
1002 u8 reserved_23[0x1];
1011 u8 stat_rate_support[0x10];
1012 u8 reserved_24[0xc];
1013 u8 cqe_version[0x4];
1015 u8 compact_address_vector[0x1];
1016 u8 striding_rq[0x1];
1017 u8 reserved_25[0x1];
1018 u8 ipoib_enhanced_offloads[0x1];
1019 u8 ipoib_ipoib_offloads[0x1];
1020 u8 reserved_26[0x8];
1021 u8 dc_connect_qp[0x1];
1022 u8 dc_cnak_trace[0x1];
1023 u8 drain_sigerr[0x1];
1024 u8 cmdif_checksum[0x2];
1026 u8 reserved_27[0x1];
1027 u8 wq_signature[0x1];
1028 u8 sctr_data_cqe[0x1];
1029 u8 reserved_28[0x1];
1035 u8 eth_net_offloads[0x1];
1038 u8 reserved_30[0x1];
1042 u8 cq_moderation[0x1];
1043 u8 cq_period_mode_modify[0x1];
1044 u8 cq_invalidate[0x1];
1045 u8 reserved_at_225[0x1];
1046 u8 cq_eq_remap[0x1];
1048 u8 block_lb_mc[0x1];
1049 u8 exponential_backoff[0x1];
1050 u8 scqe_break_moderation[0x1];
1051 u8 cq_period_start_from_cqe[0x1];
1056 u8 reserved_32[0x6];
1059 u8 set_deth_sqpn[0x1];
1060 u8 reserved_33[0x3];
1066 u8 reserved_34[0xa];
1068 u8 reserved_35[0x8];
1072 u8 driver_version[0x1];
1073 u8 pad_tx_eth_packet[0x1];
1074 u8 reserved_36[0x8];
1075 u8 log_bf_reg_size[0x5];
1076 u8 reserved_37[0x10];
1078 u8 num_of_diagnostic_counters[0x10];
1079 u8 max_wqe_sz_sq[0x10];
1081 u8 reserved_38[0x10];
1082 u8 max_wqe_sz_rq[0x10];
1084 u8 reserved_39[0x10];
1085 u8 max_wqe_sz_sq_dc[0x10];
1087 u8 reserved_40[0x7];
1088 u8 max_qp_mcg[0x19];
1090 u8 reserved_41[0x18];
1091 u8 log_max_mcg[0x8];
1093 u8 reserved_42[0x3];
1094 u8 log_max_transport_domain[0x5];
1095 u8 reserved_43[0x3];
1097 u8 reserved_44[0xb];
1098 u8 log_max_xrcd[0x5];
1100 u8 reserved_45[0x10];
1101 u8 max_flow_counter[0x10];
1103 u8 reserved_46[0x3];
1105 u8 reserved_47[0x3];
1107 u8 reserved_48[0x3];
1108 u8 log_max_tir[0x5];
1109 u8 reserved_49[0x3];
1110 u8 log_max_tis[0x5];
1112 u8 basic_cyclic_rcv_wqe[0x1];
1113 u8 reserved_50[0x2];
1114 u8 log_max_rmp[0x5];
1115 u8 reserved_51[0x3];
1116 u8 log_max_rqt[0x5];
1117 u8 reserved_52[0x3];
1118 u8 log_max_rqt_size[0x5];
1119 u8 reserved_53[0x3];
1120 u8 log_max_tis_per_sq[0x5];
1122 u8 reserved_54[0x3];
1123 u8 log_max_stride_sz_rq[0x5];
1124 u8 reserved_55[0x3];
1125 u8 log_min_stride_sz_rq[0x5];
1126 u8 reserved_56[0x3];
1127 u8 log_max_stride_sz_sq[0x5];
1128 u8 reserved_57[0x3];
1129 u8 log_min_stride_sz_sq[0x5];
1131 u8 reserved_58[0x1b];
1132 u8 log_max_wq_sz[0x5];
1134 u8 nic_vport_change_event[0x1];
1135 u8 disable_local_lb[0x1];
1136 u8 reserved_59[0x9];
1137 u8 log_max_vlan_list[0x5];
1138 u8 reserved_60[0x3];
1139 u8 log_max_current_mc_list[0x5];
1140 u8 reserved_61[0x3];
1141 u8 log_max_current_uc_list[0x5];
1143 u8 reserved_62[0x80];
1145 u8 reserved_63[0x3];
1146 u8 log_max_l2_table[0x5];
1147 u8 reserved_64[0x8];
1148 u8 log_uar_page_sz[0x10];
1150 u8 reserved_65[0x20];
1152 u8 device_frequency_mhz[0x20];
1154 u8 device_frequency_khz[0x20];
1156 u8 reserved_66[0x80];
1158 u8 log_max_atomic_size_qp[0x8];
1159 u8 reserved_67[0x10];
1160 u8 log_max_atomic_size_dc[0x8];
1162 u8 reserved_68[0x1f];
1163 u8 cqe_compression[0x1];
1165 u8 cqe_compression_timeout[0x10];
1166 u8 cqe_compression_max_num[0x10];
1168 u8 reserved_69[0x220];
1171 enum mlx5_flow_destination_type {
1172 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1173 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1174 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1177 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1178 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1179 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1180 u8 reserved_0[0x40];
1183 struct mlx5_ifc_fte_match_param_bits {
1184 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1186 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1188 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1190 u8 reserved_0[0xa00];
1194 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1195 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1196 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1197 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1198 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1201 struct mlx5_ifc_rx_hash_field_select_bits {
1202 u8 l3_prot_type[0x1];
1203 u8 l4_prot_type[0x1];
1204 u8 selected_fields[0x1e];
1208 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1209 MLX5_WQ_TYPE_CYCLIC = 0x1,
1210 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2,
1211 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1220 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1221 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1224 struct mlx5_ifc_wq_bits {
1226 u8 wq_signature[0x1];
1227 u8 end_padding_mode[0x2];
1229 u8 reserved_0[0x18];
1231 u8 hds_skip_first_sge[0x1];
1232 u8 log2_hds_buf_size[0x3];
1234 u8 page_offset[0x5];
1245 u8 hw_counter[0x20];
1247 u8 sw_counter[0x20];
1250 u8 log_wq_stride[0x4];
1252 u8 log_wq_pg_sz[0x5];
1256 u8 reserved_7[0x15];
1257 u8 single_wqe_log_num_of_strides[0x3];
1258 u8 two_byte_shift_en[0x1];
1260 u8 single_stride_log_num_of_bytes[0x3];
1262 u8 reserved_9[0x4c0];
1264 struct mlx5_ifc_cmd_pas_bits pas[0];
1267 struct mlx5_ifc_rq_num_bits {
1272 struct mlx5_ifc_mac_address_layout_bits {
1273 u8 reserved_0[0x10];
1274 u8 mac_addr_47_32[0x10];
1276 u8 mac_addr_31_0[0x20];
1279 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1280 u8 reserved_0[0xa0];
1282 u8 min_time_between_cnps[0x20];
1284 u8 reserved_1[0x12];
1287 u8 cnp_prio_mode[0x1];
1288 u8 cnp_802p_prio[0x3];
1290 u8 reserved_3[0x720];
1293 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1294 u8 reserved_0[0x60];
1297 u8 clamp_tgt_rate[0x1];
1299 u8 clamp_tgt_rate_after_time_inc[0x1];
1300 u8 reserved_3[0x17];
1302 u8 reserved_4[0x20];
1304 u8 rpg_time_reset[0x20];
1306 u8 rpg_byte_reset[0x20];
1308 u8 rpg_threshold[0x20];
1310 u8 rpg_max_rate[0x20];
1312 u8 rpg_ai_rate[0x20];
1314 u8 rpg_hai_rate[0x20];
1318 u8 rpg_min_dec_fac[0x20];
1320 u8 rpg_min_rate[0x20];
1322 u8 reserved_5[0xe0];
1324 u8 rate_to_set_on_first_cnp[0x20];
1328 u8 dce_tcp_rtt[0x20];
1330 u8 rate_reduce_monitor_period[0x20];
1332 u8 reserved_6[0x20];
1334 u8 initial_alpha_value[0x20];
1336 u8 reserved_7[0x4a0];
1339 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1340 u8 reserved_0[0x80];
1342 u8 rppp_max_rps[0x20];
1344 u8 rpg_time_reset[0x20];
1346 u8 rpg_byte_reset[0x20];
1348 u8 rpg_threshold[0x20];
1350 u8 rpg_max_rate[0x20];
1352 u8 rpg_ai_rate[0x20];
1354 u8 rpg_hai_rate[0x20];
1358 u8 rpg_min_dec_fac[0x20];
1360 u8 rpg_min_rate[0x20];
1362 u8 reserved_1[0x640];
1366 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1367 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1368 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1371 struct mlx5_ifc_resize_field_select_bits {
1372 u8 resize_field_select[0x20];
1376 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1377 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1378 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1379 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1380 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
1381 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
1384 struct mlx5_ifc_modify_field_select_bits {
1385 u8 modify_field_select[0x20];
1388 struct mlx5_ifc_field_select_r_roce_np_bits {
1389 u8 field_select_r_roce_np[0x20];
1393 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2,
1394 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4,
1395 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8,
1396 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10,
1397 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20,
1398 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40,
1399 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80,
1400 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100,
1401 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200,
1402 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400,
1403 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800,
1404 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000,
1405 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000,
1406 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000,
1407 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000,
1410 struct mlx5_ifc_field_select_r_roce_rp_bits {
1411 u8 field_select_r_roce_rp[0x20];
1415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1427 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1428 u8 field_select_8021qaurp[0x20];
1431 struct mlx5_ifc_pptb_reg_bits {
1451 u8 reserved_3[0x10];
1453 u8 untagged_buff[0x4];
1456 struct mlx5_ifc_dcbx_app_reg_bits {
1458 u8 port_number[0x8];
1459 u8 reserved_1[0x10];
1461 u8 reserved_2[0x1a];
1462 u8 num_app_prio[0x6];
1464 u8 reserved_3[0x40];
1466 struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1469 struct mlx5_ifc_dcbx_param_reg_bits {
1470 u8 dcbx_cee_cap[0x1];
1471 u8 dcbx_ieee_cap[0x1];
1472 u8 dcbx_standby_cap[0x1];
1474 u8 port_number[0x8];
1476 u8 max_application_table_size[0x6];
1478 u8 reserved_2[0x15];
1479 u8 version_oper[0x3];
1481 u8 version_admin[0x3];
1483 u8 willing_admin[0x1];
1485 u8 pfc_cap_oper[0x4];
1487 u8 pfc_cap_admin[0x4];
1489 u8 num_of_tc_oper[0x4];
1491 u8 num_of_tc_admin[0x4];
1493 u8 remote_willing[0x1];
1495 u8 remote_pfc_cap[0x4];
1496 u8 reserved_9[0x14];
1497 u8 remote_num_of_tc[0x4];
1499 u8 reserved_10[0x18];
1502 u8 reserved_11[0x160];
1505 struct mlx5_ifc_qhll_bits {
1506 u8 reserved_at_0[0x8];
1508 u8 reserved_at_10[0x10];
1510 u8 reserved_at_20[0x1b];
1514 u8 reserved_at_41[0x1c];
1518 struct mlx5_ifc_qetcr_reg_bits {
1519 u8 operation_type[0x2];
1520 u8 cap_local_admin[0x1];
1521 u8 cap_remote_admin[0x1];
1523 u8 port_number[0x8];
1524 u8 reserved_1[0x10];
1526 u8 reserved_2[0x20];
1530 u8 global_configuration[0x40];
1533 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1534 u8 queue_address_63_32[0x20];
1536 u8 queue_address_31_12[0x14];
1540 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1543 u8 queue_number[0x18];
1547 u8 reserved_2[0x10];
1548 u8 pkey_index[0x10];
1550 u8 reserved_3[0x40];
1553 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1560 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0,
1561 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1,
1565 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0,
1566 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1,
1567 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2,
1568 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
1571 struct mlx5_ifc_nodnic_event_word_bits {
1572 u8 driver_reset_needed[0x1];
1573 u8 port_management_change_event[0x1];
1574 u8 reserved_0[0x19];
1579 struct mlx5_ifc_nic_vport_change_event_bits {
1580 u8 reserved_0[0x10];
1583 u8 reserved_1[0xc0];
1586 struct mlx5_ifc_pages_req_event_bits {
1587 u8 reserved_0[0x10];
1588 u8 function_id[0x10];
1592 u8 reserved_1[0xa0];
1595 struct mlx5_ifc_cmd_inter_comp_event_bits {
1596 u8 command_completion_vector[0x20];
1598 u8 reserved_0[0xc0];
1601 struct mlx5_ifc_stall_vl_event_bits {
1602 u8 reserved_0[0x18];
1607 u8 reserved_2[0xa0];
1610 struct mlx5_ifc_db_bf_congestion_event_bits {
1611 u8 event_subtype[0x8];
1613 u8 congestion_level[0x8];
1616 u8 reserved_2[0xa0];
1619 struct mlx5_ifc_gpio_event_bits {
1620 u8 reserved_0[0x60];
1622 u8 gpio_event_hi[0x20];
1624 u8 gpio_event_lo[0x20];
1626 u8 reserved_1[0x40];
1629 struct mlx5_ifc_port_state_change_event_bits {
1630 u8 reserved_0[0x40];
1633 u8 reserved_1[0x1c];
1635 u8 reserved_2[0x80];
1638 struct mlx5_ifc_dropped_packet_logged_bits {
1639 u8 reserved_0[0xe0];
1643 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1644 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1647 struct mlx5_ifc_cq_error_bits {
1651 u8 reserved_1[0x20];
1653 u8 reserved_2[0x18];
1656 u8 reserved_3[0x80];
1659 struct mlx5_ifc_rdma_page_fault_event_bits {
1660 u8 bytes_commited[0x20];
1664 u8 reserved_0[0x10];
1665 u8 packet_len[0x10];
1667 u8 rdma_op_len[0x20];
1678 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1679 u8 bytes_committed[0x20];
1681 u8 reserved_0[0x10];
1684 u8 reserved_1[0x10];
1687 u8 reserved_2[0x60];
1697 MLX5_QP_EVENTS_TYPE_QP = 0x0,
1698 MLX5_QP_EVENTS_TYPE_RQ = 0x1,
1699 MLX5_QP_EVENTS_TYPE_SQ = 0x2,
1702 struct mlx5_ifc_qp_events_bits {
1703 u8 reserved_0[0xa0];
1706 u8 reserved_1[0x18];
1709 u8 qpn_rqn_sqn[0x18];
1712 struct mlx5_ifc_dct_events_bits {
1713 u8 reserved_0[0xc0];
1716 u8 dct_number[0x18];
1719 struct mlx5_ifc_comp_event_bits {
1720 u8 reserved_0[0xc0];
1726 struct mlx5_ifc_fw_version_bits {
1728 u8 reserved_0[0x10];
1744 MLX5_QPC_STATE_RST = 0x0,
1745 MLX5_QPC_STATE_INIT = 0x1,
1746 MLX5_QPC_STATE_RTR = 0x2,
1747 MLX5_QPC_STATE_RTS = 0x3,
1748 MLX5_QPC_STATE_SQER = 0x4,
1749 MLX5_QPC_STATE_SQD = 0x5,
1750 MLX5_QPC_STATE_ERR = 0x6,
1751 MLX5_QPC_STATE_SUSPENDED = 0x9,
1755 MLX5_QPC_ST_RC = 0x0,
1756 MLX5_QPC_ST_UC = 0x1,
1757 MLX5_QPC_ST_UD = 0x2,
1758 MLX5_QPC_ST_XRC = 0x3,
1759 MLX5_QPC_ST_DCI = 0x5,
1760 MLX5_QPC_ST_QP0 = 0x7,
1761 MLX5_QPC_ST_QP1 = 0x8,
1762 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1763 MLX5_QPC_ST_REG_UMR = 0xc,
1767 MLX5_QP_PM_ARMED = 0x0,
1768 MLX5_QP_PM_REARM = 0x1,
1769 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1770 MLX5_QP_PM_MIGRATED = 0x3,
1774 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1775 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1779 MLX5_QPC_MTU_256_BYTES = 0x1,
1780 MLX5_QPC_MTU_512_BYTES = 0x2,
1781 MLX5_QPC_MTU_1K_BYTES = 0x3,
1782 MLX5_QPC_MTU_2K_BYTES = 0x4,
1783 MLX5_QPC_MTU_4K_BYTES = 0x5,
1784 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1788 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1789 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1790 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1791 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1792 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1793 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1794 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1795 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1799 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1800 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1801 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1805 MLX5_QPC_CS_RES_DISABLE = 0x0,
1806 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1807 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1810 struct mlx5_ifc_qpc_bits {
1812 u8 lag_tx_port_affinity[0x4];
1817 u8 end_padding_mode[0x2];
1820 u8 wq_signature[0x1];
1821 u8 block_lb_mc[0x1];
1822 u8 atomic_like_write_en[0x1];
1823 u8 latency_sensitive[0x1];
1825 u8 drain_sigerr[0x1];
1830 u8 log_msg_max[0x5];
1832 u8 log_rq_size[0x4];
1833 u8 log_rq_stride[0x3];
1835 u8 log_sq_size[0x4];
1838 u8 ulp_stateless_offload_mode[0x4];
1840 u8 counter_set_id[0x8];
1844 u8 user_index[0x18];
1847 u8 log_page_size[0x5];
1848 u8 remote_qpn[0x18];
1850 struct mlx5_ifc_ads_bits primary_address_path;
1852 struct mlx5_ifc_ads_bits secondary_address_path;
1854 u8 log_ack_req_freq[0x4];
1855 u8 reserved_10[0x4];
1856 u8 log_sra_max[0x3];
1857 u8 reserved_11[0x2];
1858 u8 retry_count[0x3];
1860 u8 reserved_12[0x1];
1862 u8 cur_rnr_retry[0x3];
1863 u8 cur_retry_count[0x3];
1864 u8 reserved_13[0x5];
1866 u8 reserved_14[0x20];
1868 u8 reserved_15[0x8];
1869 u8 next_send_psn[0x18];
1871 u8 reserved_16[0x8];
1874 u8 reserved_at_400[0x8];
1877 u8 reserved_17[0x20];
1879 u8 reserved_18[0x8];
1880 u8 last_acked_psn[0x18];
1882 u8 reserved_19[0x8];
1885 u8 reserved_20[0x8];
1886 u8 log_rra_max[0x3];
1887 u8 reserved_21[0x1];
1888 u8 atomic_mode[0x4];
1892 u8 reserved_22[0x1];
1893 u8 page_offset[0x6];
1894 u8 reserved_23[0x3];
1895 u8 cd_slave_receive[0x1];
1896 u8 cd_slave_send[0x1];
1899 u8 reserved_24[0x3];
1900 u8 min_rnr_nak[0x5];
1901 u8 next_rcv_psn[0x18];
1903 u8 reserved_25[0x8];
1906 u8 reserved_26[0x8];
1913 u8 reserved_27[0x5];
1917 u8 reserved_28[0x8];
1920 u8 hw_sq_wqebb_counter[0x10];
1921 u8 sw_sq_wqebb_counter[0x10];
1923 u8 hw_rq_counter[0x20];
1925 u8 sw_rq_counter[0x20];
1927 u8 reserved_29[0x20];
1929 u8 reserved_30[0xf];
1934 u8 dc_access_key[0x40];
1936 u8 rdma_active[0x1];
1939 u8 reserved_31[0x5];
1940 u8 send_msg_psn[0x18];
1942 u8 reserved_32[0x8];
1943 u8 rcv_msg_psn[0x18];
1949 u8 reserved_33[0x20];
1952 struct mlx5_ifc_roce_addr_layout_bits {
1953 u8 source_l3_address[16][0x8];
1958 u8 source_mac_47_32[0x10];
1960 u8 source_mac_31_0[0x20];
1962 u8 reserved_1[0x14];
1963 u8 roce_l3_type[0x4];
1964 u8 roce_version[0x8];
1966 u8 reserved_2[0x20];
1969 struct mlx5_ifc_rdbc_bits {
1970 u8 reserved_0[0x1c];
1973 u8 reserved_1[0x20];
1982 u8 byte_count[0x20];
1984 u8 reserved_3[0x20];
1986 u8 atomic_resp[32][0x8];
1990 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1991 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1992 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1993 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
1996 struct mlx5_ifc_flow_context_bits {
1997 u8 reserved_0[0x20];
2004 u8 reserved_2[0x10];
2008 u8 destination_list_size[0x18];
2011 u8 flow_counter_list_size[0x18];
2013 u8 reserved_5[0x140];
2015 struct mlx5_ifc_fte_match_param_bits match_value;
2017 u8 reserved_6[0x600];
2019 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2023 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2024 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2027 struct mlx5_ifc_xrc_srqc_bits {
2029 u8 log_xrc_srq_size[0x4];
2030 u8 reserved_0[0x18];
2032 u8 wq_signature[0x1];
2036 u8 basic_cyclic_rcv_wqe[0x1];
2037 u8 log_rq_stride[0x3];
2040 u8 page_offset[0x6];
2044 u8 reserved_3[0x20];
2047 u8 log_page_size[0x6];
2048 u8 user_index[0x18];
2050 u8 reserved_5[0x20];
2058 u8 reserved_7[0x40];
2060 u8 db_record_addr_h[0x20];
2062 u8 db_record_addr_l[0x1e];
2065 u8 reserved_9[0x80];
2068 struct mlx5_ifc_traffic_counter_bits {
2074 struct mlx5_ifc_tisc_bits {
2075 u8 strict_lag_tx_port_affinity[0x1];
2076 u8 reserved_at_1[0x3];
2077 u8 lag_tx_port_affinity[0x04];
2079 u8 reserved_at_8[0x4];
2081 u8 reserved_1[0x10];
2083 u8 reserved_2[0x100];
2086 u8 transport_domain[0x18];
2089 u8 underlay_qpn[0x18];
2091 u8 reserved_5[0x3a0];
2095 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2096 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2100 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2101 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2105 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
2106 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
2107 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
2111 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1,
2112 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2,
2115 struct mlx5_ifc_tirc_bits {
2116 u8 reserved_0[0x20];
2119 u8 reserved_1[0x1c];
2121 u8 reserved_2[0x40];
2124 u8 lro_timeout_period_usecs[0x10];
2125 u8 lro_enable_mask[0x4];
2126 u8 lro_max_msg_sz[0x8];
2128 u8 reserved_4[0x40];
2131 u8 inline_rqn[0x18];
2133 u8 rx_hash_symmetric[0x1];
2135 u8 tunneled_offload_en[0x1];
2137 u8 indirect_table[0x18];
2142 u8 transport_domain[0x18];
2144 u8 rx_hash_toeplitz_key[10][0x20];
2146 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2148 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2150 u8 reserved_9[0x4c0];
2154 MLX5_SRQC_STATE_GOOD = 0x0,
2155 MLX5_SRQC_STATE_ERROR = 0x1,
2158 struct mlx5_ifc_srqc_bits {
2160 u8 log_srq_size[0x4];
2161 u8 reserved_0[0x18];
2163 u8 wq_signature[0x1];
2168 u8 log_rq_stride[0x3];
2171 u8 page_offset[0x6];
2175 u8 reserved_4[0x20];
2178 u8 log_page_size[0x6];
2179 u8 reserved_6[0x18];
2181 u8 reserved_7[0x20];
2189 u8 reserved_9[0x40];
2193 u8 reserved_10[0x80];
2197 MLX5_SQC_STATE_RST = 0x0,
2198 MLX5_SQC_STATE_RDY = 0x1,
2199 MLX5_SQC_STATE_ERR = 0x3,
2202 struct mlx5_ifc_sqc_bits {
2206 u8 flush_in_error_en[0x1];
2207 u8 allow_multi_pkt_send_wqe[0x1];
2208 u8 min_wqe_inline_mode[0x3];
2212 u8 reserved_0[0x12];
2215 u8 user_index[0x18];
2220 u8 reserved_3[0x80];
2222 u8 qos_para_vport_number[0x10];
2223 u8 packet_pacing_rate_limit_index[0x10];
2225 u8 tis_lst_sz[0x10];
2226 u8 reserved_4[0x10];
2228 u8 reserved_5[0x40];
2233 struct mlx5_ifc_wq_bits wq;
2237 MLX5_TSAR_TYPE_DWRR = 0,
2238 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2239 MLX5_TSAR_TYPE_ETS = 2
2242 struct mlx5_ifc_tsar_element_attributes_bits {
2245 u8 reserved_1[0x10];
2248 struct mlx5_ifc_vport_element_attributes_bits {
2249 u8 reserved_0[0x10];
2250 u8 vport_number[0x10];
2253 struct mlx5_ifc_vport_tc_element_attributes_bits {
2254 u8 traffic_class[0x10];
2255 u8 vport_number[0x10];
2258 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2259 u8 reserved_0[0x0C];
2260 u8 traffic_class[0x04];
2261 u8 qos_para_vport_number[0x10];
2265 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2266 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2267 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2268 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2271 struct mlx5_ifc_scheduling_context_bits {
2272 u8 element_type[0x8];
2273 u8 reserved_at_8[0x18];
2275 u8 element_attributes[0x20];
2277 u8 parent_element_id[0x20];
2279 u8 reserved_at_60[0x40];
2283 u8 max_average_bw[0x20];
2285 u8 reserved_at_e0[0x120];
2288 struct mlx5_ifc_rqtc_bits {
2289 u8 reserved_0[0xa0];
2291 u8 reserved_1[0x10];
2292 u8 rqt_max_size[0x10];
2294 u8 reserved_2[0x10];
2295 u8 rqt_actual_size[0x10];
2297 u8 reserved_3[0x6a0];
2299 struct mlx5_ifc_rq_num_bits rq_num[0];
2303 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2304 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2308 MLX5_RQC_STATE_RST = 0x0,
2309 MLX5_RQC_STATE_RDY = 0x1,
2310 MLX5_RQC_STATE_ERR = 0x3,
2314 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
2315 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
2318 struct mlx5_ifc_rqc_bits {
2320 u8 delay_drop_en[0x1];
2321 u8 scatter_fcs[0x1];
2322 u8 vlan_strip_disable[0x1];
2323 u8 mem_rq_type[0x4];
2326 u8 flush_in_error_en[0x1];
2327 u8 reserved_2[0x12];
2330 u8 user_index[0x18];
2335 u8 counter_set_id[0x8];
2336 u8 reserved_5[0x18];
2341 u8 reserved_7[0xe0];
2343 struct mlx5_ifc_wq_bits wq;
2347 MLX5_RMPC_STATE_RDY = 0x1,
2348 MLX5_RMPC_STATE_ERR = 0x3,
2351 struct mlx5_ifc_rmpc_bits {
2354 u8 reserved_1[0x14];
2356 u8 basic_cyclic_rcv_wqe[0x1];
2357 u8 reserved_2[0x1f];
2359 u8 reserved_3[0x140];
2361 struct mlx5_ifc_wq_bits wq;
2365 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2366 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1,
2367 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2,
2370 struct mlx5_ifc_nic_vport_context_bits {
2372 u8 min_wqe_inline_mode[0x3];
2373 u8 reserved_1[0x15];
2374 u8 disable_mc_local_lb[0x1];
2375 u8 disable_uc_local_lb[0x1];
2378 u8 arm_change_event[0x1];
2379 u8 reserved_2[0x1a];
2380 u8 event_on_mtu[0x1];
2381 u8 event_on_promisc_change[0x1];
2382 u8 event_on_vlan_change[0x1];
2383 u8 event_on_mc_address_change[0x1];
2384 u8 event_on_uc_address_change[0x1];
2386 u8 reserved_3[0xe0];
2388 u8 reserved_4[0x10];
2391 u8 system_image_guid[0x40];
2397 u8 reserved_5[0x140];
2399 u8 qkey_violation_counter[0x10];
2400 u8 reserved_6[0x10];
2402 u8 reserved_7[0x420];
2406 u8 promisc_all[0x1];
2408 u8 allowed_list_type[0x3];
2410 u8 allowed_list_size[0xc];
2412 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2414 u8 reserved_10[0x20];
2416 u8 current_uc_mac_address[0][0x40];
2420 MLX5_ACCESS_MODE_PA = 0x0,
2421 MLX5_ACCESS_MODE_MTT = 0x1,
2422 MLX5_ACCESS_MODE_KLM = 0x2,
2425 struct mlx5_ifc_mkc_bits {
2429 u8 small_fence_on_rdma_read_response[0x1];
2436 u8 access_mode[0x2];
2442 u8 reserved_3[0x20];
2448 u8 expected_sigerr_count[0x1];
2453 u8 start_addr[0x40];
2457 u8 bsf_octword_size[0x20];
2459 u8 reserved_6[0x80];
2461 u8 translations_octword_size[0x20];
2463 u8 reserved_7[0x1b];
2464 u8 log_page_size[0x5];
2466 u8 reserved_8[0x20];
2469 struct mlx5_ifc_pkey_bits {
2470 u8 reserved_0[0x10];
2474 struct mlx5_ifc_array128_auto_bits {
2475 u8 array128_auto[16][0x8];
2479 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0,
2480 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1,
2481 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2,
2485 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1,
2486 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2,
2487 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
2488 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4,
2489 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5,
2490 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6,
2491 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
2495 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0,
2496 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1,
2497 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2,
2501 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1,
2502 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2,
2503 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
2504 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4,
2508 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1,
2509 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2,
2510 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
2511 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4,
2514 struct mlx5_ifc_hca_vport_context_bits {
2515 u8 field_select[0x20];
2517 u8 reserved_0[0xe0];
2519 u8 sm_virt_aware[0x1];
2522 u8 grh_required[0x1];
2524 u8 min_wqe_inline_mode[0x3];
2526 u8 port_physical_state[0x4];
2527 u8 vport_state_policy[0x4];
2529 u8 vport_state[0x4];
2531 u8 reserved_3[0x20];
2533 u8 system_image_guid[0x40];
2541 u8 cap_mask1_field_select[0x20];
2545 u8 cap_mask2_field_select[0x20];
2547 u8 reserved_4[0x80];
2551 u8 init_type_reply[0x4];
2553 u8 subnet_timeout[0x5];
2559 u8 qkey_violation_counter[0x10];
2560 u8 pkey_violation_counter[0x10];
2562 u8 reserved_7[0xca0];
2565 union mlx5_ifc_hca_cap_union_bits {
2566 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2567 struct mlx5_ifc_odp_cap_bits odp_cap;
2568 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2569 struct mlx5_ifc_roce_cap_bits roce_cap;
2570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2571 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2572 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2573 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2574 struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2575 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2576 struct mlx5_ifc_qos_cap_bits qos_cap;
2577 u8 reserved_0[0x8000];
2581 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2582 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2585 struct mlx5_ifc_flow_table_context_bits {
2588 u8 reserved_at_2[0x2];
2589 u8 table_miss_action[0x4];
2591 u8 reserved_at_10[0x8];
2594 u8 reserved_at_20[0x8];
2595 u8 table_miss_id[0x18];
2597 u8 reserved_at_40[0x8];
2598 u8 lag_master_next_table_id[0x18];
2600 u8 reserved_at_60[0xe0];
2603 struct mlx5_ifc_esw_vport_context_bits {
2605 u8 vport_svlan_strip[0x1];
2606 u8 vport_cvlan_strip[0x1];
2607 u8 vport_svlan_insert[0x1];
2608 u8 vport_cvlan_insert[0x2];
2609 u8 reserved_1[0x18];
2611 u8 reserved_2[0x20];
2620 u8 reserved_3[0x7a0];
2624 MLX5_EQC_STATUS_OK = 0x0,
2625 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2629 MLX5_EQ_STATE_ARMED = 0x9,
2630 MLX5_EQ_STATE_FIRED = 0xa,
2633 struct mlx5_ifc_eqc_bits {
2642 u8 reserved_3[0x20];
2644 u8 reserved_4[0x14];
2645 u8 page_offset[0x6];
2649 u8 log_eq_size[0x5];
2652 u8 reserved_7[0x20];
2654 u8 reserved_8[0x18];
2658 u8 log_page_size[0x5];
2659 u8 reserved_10[0x18];
2661 u8 reserved_11[0x60];
2663 u8 reserved_12[0x8];
2664 u8 consumer_counter[0x18];
2666 u8 reserved_13[0x8];
2667 u8 producer_counter[0x18];
2669 u8 reserved_14[0x80];
2673 MLX5_DCTC_STATE_ACTIVE = 0x0,
2674 MLX5_DCTC_STATE_DRAINING = 0x1,
2675 MLX5_DCTC_STATE_DRAINED = 0x2,
2679 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2680 MLX5_DCTC_CS_RES_NA = 0x1,
2681 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2685 MLX5_DCTC_MTU_256_BYTES = 0x1,
2686 MLX5_DCTC_MTU_512_BYTES = 0x2,
2687 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2688 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2689 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2692 struct mlx5_ifc_dctc_bits {
2695 u8 reserved_1[0x18];
2698 u8 user_index[0x18];
2703 u8 counter_set_id[0x8];
2704 u8 atomic_mode[0x4];
2708 u8 atomic_like_write_en[0x1];
2709 u8 latency_sensitive[0x1];
2716 u8 min_rnr_nak[0x5];
2726 u8 reserved_10[0x4];
2727 u8 flow_label[0x14];
2729 u8 dc_access_key[0x40];
2731 u8 reserved_11[0x5];
2734 u8 pkey_index[0x10];
2736 u8 reserved_12[0x8];
2737 u8 my_addr_index[0x8];
2738 u8 reserved_13[0x8];
2741 u8 dc_access_key_violation_count[0x20];
2743 u8 reserved_14[0x14];
2749 u8 reserved_15[0x40];
2753 MLX5_CQC_STATUS_OK = 0x0,
2754 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2755 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2764 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2765 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2769 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6,
2770 MLX5_CQ_STATE_ARMED = 0x9,
2771 MLX5_CQ_STATE_FIRED = 0xa,
2774 struct mlx5_ifc_cqc_bits {
2780 u8 scqe_break_moderation_en[0x1];
2782 u8 cq_period_mode[0x2];
2783 u8 cqe_compression_en[0x1];
2784 u8 mini_cqe_res_format[0x2];
2788 u8 reserved_3[0x20];
2790 u8 reserved_4[0x14];
2791 u8 page_offset[0x6];
2795 u8 log_cq_size[0x5];
2800 u8 cq_max_count[0x10];
2802 u8 reserved_8[0x18];
2806 u8 log_page_size[0x5];
2807 u8 reserved_10[0x18];
2809 u8 reserved_11[0x20];
2811 u8 reserved_12[0x8];
2812 u8 last_notified_index[0x18];
2814 u8 reserved_13[0x8];
2815 u8 last_solicit_index[0x18];
2817 u8 reserved_14[0x8];
2818 u8 consumer_counter[0x18];
2820 u8 reserved_15[0x8];
2821 u8 producer_counter[0x18];
2823 u8 reserved_16[0x40];
2828 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2829 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2830 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2831 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2832 u8 reserved_0[0x800];
2835 struct mlx5_ifc_query_adapter_param_block_bits {
2836 u8 reserved_0[0xc0];
2839 u8 ieee_vendor_id[0x18];
2841 u8 reserved_2[0x10];
2842 u8 vsd_vendor_id[0x10];
2846 u8 vsd_contd_psid[16][0x8];
2849 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2850 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2851 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2852 u8 reserved_0[0x20];
2855 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2856 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2857 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2858 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2859 u8 reserved_0[0x20];
2862 struct mlx5_ifc_bufferx_reg_bits {
2869 u8 xoff_threshold[0x10];
2870 u8 xon_threshold[0x10];
2873 struct mlx5_ifc_config_item_bits {
2876 u8 header_type[0x2];
2878 u8 default_location[0x1];
2886 u8 reserved_4[0x10];
2890 struct mlx5_ifc_nodnic_port_config_reg_bits {
2891 struct mlx5_ifc_nodnic_event_word_bits event;
2896 u8 promisc_multicast_en[0x1];
2897 u8 reserved_0[0x17];
2898 u8 receive_filter_en[0x5];
2900 u8 reserved_1[0x10];
2905 u8 receive_filters_mgid_mac[64][0x8];
2909 u8 reserved_2[0x10];
2916 u8 completion_address_63_32[0x20];
2918 u8 completion_address_31_12[0x14];
2920 u8 log_cq_size[0x6];
2922 u8 working_buffer_address_63_32[0x20];
2924 u8 working_buffer_address_31_12[0x14];
2927 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2929 u8 pkey_index[0x10];
2932 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2934 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2936 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2938 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2940 u8 reserved_6[0x400];
2943 union mlx5_ifc_event_auto_bits {
2944 struct mlx5_ifc_comp_event_bits comp_event;
2945 struct mlx5_ifc_dct_events_bits dct_events;
2946 struct mlx5_ifc_qp_events_bits qp_events;
2947 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2948 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2949 struct mlx5_ifc_cq_error_bits cq_error;
2950 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2951 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2952 struct mlx5_ifc_gpio_event_bits gpio_event;
2953 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2954 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2955 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2956 struct mlx5_ifc_pages_req_event_bits pages_req_event;
2957 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2958 u8 reserved_0[0xe0];
2961 struct mlx5_ifc_health_buffer_bits {
2962 u8 reserved_0[0x100];
2964 u8 assert_existptr[0x20];
2966 u8 assert_callra[0x20];
2968 u8 reserved_1[0x40];
2970 u8 fw_version[0x20];
2974 u8 reserved_2[0x20];
2976 u8 irisc_index[0x8];
2981 struct mlx5_ifc_register_loopback_control_bits {
2985 u8 reserved_1[0x10];
2987 u8 reserved_2[0x60];
2990 struct mlx5_ifc_lrh_bits {
3002 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3003 u8 reserved_0[0x40];
3005 u8 reserved_1[0x10];
3010 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3011 u8 reserved_0[0x40];
3013 u8 rol_mode_valid[0x1];
3014 u8 wol_mode_valid[0x1];
3019 u8 reserved_2[0x7a0];
3022 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3023 u8 virtual_mac_en[0x1];
3025 u8 reserved_0[0x1e];
3027 u8 reserved_1[0x40];
3029 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3031 u8 reserved_2[0x760];
3034 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3035 u8 virtual_mac_en[0x1];
3037 u8 reserved_0[0x1e];
3039 struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3041 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3043 u8 reserved_1[0x760];
3046 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3047 struct mlx5_ifc_fw_version_bits fw_version;
3049 u8 reserved_0[0x10];
3050 u8 hash_signature[0x10];
3054 u8 reserved_1[0x6e0];
3057 struct mlx5_ifc_icmd_query_cap_in_bits {
3058 u8 reserved_0[0x10];
3059 u8 capability_group[0x10];
3062 struct mlx5_ifc_icmd_query_cap_general_bits {
3064 u8 fw_info_psid[0x1];
3065 u8 reserved_0[0x1e];
3067 u8 reserved_1[0x16];
3080 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3082 u8 reserved_0[0x18];
3084 u8 reserved_1[0x7e0];
3087 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3089 u8 reserved_0[0x18];
3091 u8 reserved_1[0x7e0];
3094 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3095 u8 address_hi[0x20];
3097 u8 address_lo[0x20];
3099 u8 reserved_0[0x7c0];
3102 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3103 u8 reserved_0[0x20];
3105 u8 address_hi[0x20];
3107 u8 address_lo[0x20];
3109 u8 reserved_1[0x7a0];
3112 struct mlx5_ifc_icmd_access_reg_out_bits {
3113 u8 reserved_0[0x11];
3117 u8 register_id[0x10];
3118 u8 reserved_2[0x10];
3120 u8 reserved_3[0x40];
3124 u8 reserved_5[0x10];
3126 u8 register_data[0][0x20];
3130 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1,
3131 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2,
3134 struct mlx5_ifc_icmd_access_reg_in_bits {
3137 u8 reserved_0[0x10];
3139 u8 register_id[0x10];
3144 u8 reserved_2[0x40];
3148 u8 reserved_3[0x10];
3150 u8 register_data[0][0x20];
3154 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3155 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3158 struct mlx5_ifc_teardown_hca_out_bits {
3160 u8 reserved_0[0x18];
3164 u8 reserved_1[0x3f];
3166 u8 force_state[0x1];
3170 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3171 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3174 struct mlx5_ifc_teardown_hca_in_bits {
3176 u8 reserved_0[0x10];
3178 u8 reserved_1[0x10];
3181 u8 reserved_2[0x10];
3184 u8 reserved_3[0x20];
3187 struct mlx5_ifc_set_delay_drop_params_out_bits {
3189 u8 reserved_at_8[0x18];
3193 u8 reserved_at_40[0x40];
3196 struct mlx5_ifc_set_delay_drop_params_in_bits {
3198 u8 reserved_at_10[0x10];
3200 u8 reserved_at_20[0x10];
3203 u8 reserved_at_40[0x20];
3205 u8 reserved_at_60[0x10];
3206 u8 delay_drop_timeout[0x10];
3209 struct mlx5_ifc_query_delay_drop_params_out_bits {
3211 u8 reserved_at_8[0x18];
3215 u8 reserved_at_40[0x20];
3217 u8 reserved_at_60[0x10];
3218 u8 delay_drop_timeout[0x10];
3221 struct mlx5_ifc_query_delay_drop_params_in_bits {
3223 u8 reserved_at_10[0x10];
3225 u8 reserved_at_20[0x10];
3228 u8 reserved_at_40[0x40];
3231 struct mlx5_ifc_suspend_qp_out_bits {
3233 u8 reserved_0[0x18];
3237 u8 reserved_1[0x40];
3240 struct mlx5_ifc_suspend_qp_in_bits {
3242 u8 reserved_0[0x10];
3244 u8 reserved_1[0x10];
3250 u8 reserved_3[0x20];
3253 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3255 u8 reserved_0[0x18];
3259 u8 reserved_1[0x40];
3262 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3264 u8 reserved_0[0x10];
3266 u8 reserved_1[0x10];
3272 u8 reserved_3[0x20];
3274 u8 opt_param_mask[0x20];
3276 u8 reserved_4[0x20];
3278 struct mlx5_ifc_qpc_bits qpc;
3280 u8 reserved_5[0x80];
3283 struct mlx5_ifc_sqd2rts_qp_out_bits {
3285 u8 reserved_0[0x18];
3289 u8 reserved_1[0x40];
3292 struct mlx5_ifc_sqd2rts_qp_in_bits {
3294 u8 reserved_0[0x10];
3296 u8 reserved_1[0x10];
3302 u8 reserved_3[0x20];
3304 u8 opt_param_mask[0x20];
3306 u8 reserved_4[0x20];
3308 struct mlx5_ifc_qpc_bits qpc;
3310 u8 reserved_5[0x80];
3313 struct mlx5_ifc_set_wol_rol_out_bits {
3315 u8 reserved_0[0x18];
3319 u8 reserved_1[0x40];
3322 struct mlx5_ifc_set_wol_rol_in_bits {
3324 u8 reserved_0[0x10];
3326 u8 reserved_1[0x10];
3329 u8 rol_mode_valid[0x1];
3330 u8 wol_mode_valid[0x1];
3335 u8 reserved_3[0x20];
3338 struct mlx5_ifc_set_roce_address_out_bits {
3340 u8 reserved_0[0x18];
3344 u8 reserved_1[0x40];
3347 struct mlx5_ifc_set_roce_address_in_bits {
3349 u8 reserved_0[0x10];
3351 u8 reserved_1[0x10];
3354 u8 roce_address_index[0x10];
3355 u8 reserved_2[0x10];
3357 u8 reserved_3[0x20];
3359 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3362 struct mlx5_ifc_set_rdb_out_bits {
3364 u8 reserved_0[0x18];
3368 u8 reserved_1[0x40];
3371 struct mlx5_ifc_set_rdb_in_bits {
3373 u8 reserved_0[0x10];
3375 u8 reserved_1[0x10];
3381 u8 reserved_3[0x18];
3382 u8 rdb_list_size[0x8];
3384 struct mlx5_ifc_rdbc_bits rdb_context[0];
3387 struct mlx5_ifc_set_mad_demux_out_bits {
3389 u8 reserved_0[0x18];
3393 u8 reserved_1[0x40];
3397 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3398 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3401 struct mlx5_ifc_set_mad_demux_in_bits {
3403 u8 reserved_0[0x10];
3405 u8 reserved_1[0x10];
3408 u8 reserved_2[0x20];
3412 u8 reserved_4[0x18];
3415 struct mlx5_ifc_set_l2_table_entry_out_bits {
3417 u8 reserved_0[0x18];
3421 u8 reserved_1[0x40];
3424 struct mlx5_ifc_set_l2_table_entry_in_bits {
3426 u8 reserved_0[0x10];
3428 u8 reserved_1[0x10];
3431 u8 reserved_2[0x60];
3434 u8 table_index[0x18];
3436 u8 reserved_4[0x20];
3438 u8 reserved_5[0x13];
3442 struct mlx5_ifc_mac_address_layout_bits mac_address;
3444 u8 reserved_6[0xc0];
3447 struct mlx5_ifc_set_issi_out_bits {
3449 u8 reserved_0[0x18];
3453 u8 reserved_1[0x40];
3456 struct mlx5_ifc_set_issi_in_bits {
3458 u8 reserved_0[0x10];
3460 u8 reserved_1[0x10];
3463 u8 reserved_2[0x10];
3464 u8 current_issi[0x10];
3466 u8 reserved_3[0x20];
3469 struct mlx5_ifc_set_hca_cap_out_bits {
3471 u8 reserved_0[0x18];
3475 u8 reserved_1[0x40];
3478 struct mlx5_ifc_set_hca_cap_in_bits {
3480 u8 reserved_0[0x10];
3482 u8 reserved_1[0x10];
3485 u8 reserved_2[0x40];
3487 union mlx5_ifc_hca_cap_union_bits capability;
3491 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3492 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3493 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3494 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3497 struct mlx5_ifc_set_flow_table_root_out_bits {
3499 u8 reserved_0[0x18];
3503 u8 reserved_1[0x40];
3506 struct mlx5_ifc_set_flow_table_root_in_bits {
3508 u8 reserved_0[0x10];
3510 u8 reserved_1[0x10];
3513 u8 other_vport[0x1];
3515 u8 vport_number[0x10];
3517 u8 reserved_3[0x20];
3520 u8 reserved_4[0x18];
3526 u8 underlay_qpn[0x18];
3528 u8 reserved_7[0x120];
3531 struct mlx5_ifc_set_fte_out_bits {
3533 u8 reserved_0[0x18];
3537 u8 reserved_1[0x40];
3540 struct mlx5_ifc_set_fte_in_bits {
3542 u8 reserved_0[0x10];
3544 u8 reserved_1[0x10];
3547 u8 other_vport[0x1];
3549 u8 vport_number[0x10];
3551 u8 reserved_3[0x20];
3554 u8 reserved_4[0x18];
3559 u8 reserved_6[0x18];
3560 u8 modify_enable_mask[0x8];
3562 u8 reserved_7[0x20];
3564 u8 flow_index[0x20];
3566 u8 reserved_8[0xe0];
3568 struct mlx5_ifc_flow_context_bits flow_context;
3571 struct mlx5_ifc_set_driver_version_out_bits {
3573 u8 reserved_0[0x18];
3577 u8 reserved_1[0x40];
3580 struct mlx5_ifc_set_driver_version_in_bits {
3582 u8 reserved_0[0x10];
3584 u8 reserved_1[0x10];
3587 u8 reserved_2[0x40];
3589 u8 driver_version[64][0x8];
3592 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3594 u8 reserved_0[0x18];
3598 u8 reserved_1[0x40];
3601 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3603 u8 reserved_0[0x10];
3605 u8 reserved_1[0x10];
3609 u8 reserved_2[0x1f];
3611 u8 reserved_3[0x160];
3613 struct mlx5_ifc_cmd_pas_bits pas;
3616 struct mlx5_ifc_set_burst_size_out_bits {
3618 u8 reserved_0[0x18];
3622 u8 reserved_1[0x40];
3625 struct mlx5_ifc_set_burst_size_in_bits {
3627 u8 reserved_0[0x10];
3629 u8 reserved_1[0x10];
3632 u8 reserved_2[0x20];
3635 u8 device_burst_size[0x17];
3638 struct mlx5_ifc_rts2rts_qp_out_bits {
3640 u8 reserved_0[0x18];
3644 u8 reserved_1[0x40];
3647 struct mlx5_ifc_rts2rts_qp_in_bits {
3649 u8 reserved_0[0x10];
3651 u8 reserved_1[0x10];
3657 u8 reserved_3[0x20];
3659 u8 opt_param_mask[0x20];
3661 u8 reserved_4[0x20];
3663 struct mlx5_ifc_qpc_bits qpc;
3665 u8 reserved_5[0x80];
3668 struct mlx5_ifc_rtr2rts_qp_out_bits {
3670 u8 reserved_0[0x18];
3674 u8 reserved_1[0x40];
3677 struct mlx5_ifc_rtr2rts_qp_in_bits {
3679 u8 reserved_0[0x10];
3681 u8 reserved_1[0x10];
3687 u8 reserved_3[0x20];
3689 u8 opt_param_mask[0x20];
3691 u8 reserved_4[0x20];
3693 struct mlx5_ifc_qpc_bits qpc;
3695 u8 reserved_5[0x80];
3698 struct mlx5_ifc_rst2init_qp_out_bits {
3700 u8 reserved_0[0x18];
3704 u8 reserved_1[0x40];
3707 struct mlx5_ifc_rst2init_qp_in_bits {
3709 u8 reserved_0[0x10];
3711 u8 reserved_1[0x10];
3717 u8 reserved_3[0x20];
3719 u8 opt_param_mask[0x20];
3721 u8 reserved_4[0x20];
3723 struct mlx5_ifc_qpc_bits qpc;
3725 u8 reserved_5[0x80];
3728 struct mlx5_ifc_resume_qp_out_bits {
3730 u8 reserved_0[0x18];
3734 u8 reserved_1[0x40];
3737 struct mlx5_ifc_resume_qp_in_bits {
3739 u8 reserved_0[0x10];
3741 u8 reserved_1[0x10];
3747 u8 reserved_3[0x20];
3750 struct mlx5_ifc_query_xrc_srq_out_bits {
3752 u8 reserved_0[0x18];
3756 u8 reserved_1[0x40];
3758 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3760 u8 reserved_2[0x600];
3765 struct mlx5_ifc_query_xrc_srq_in_bits {
3767 u8 reserved_0[0x10];
3769 u8 reserved_1[0x10];
3775 u8 reserved_3[0x20];
3778 struct mlx5_ifc_query_wol_rol_out_bits {
3780 u8 reserved_0[0x18];
3784 u8 reserved_1[0x10];
3788 u8 reserved_2[0x20];
3791 struct mlx5_ifc_query_wol_rol_in_bits {
3793 u8 reserved_0[0x10];
3795 u8 reserved_1[0x10];
3798 u8 reserved_2[0x40];
3802 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3803 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3806 struct mlx5_ifc_query_vport_state_out_bits {
3808 u8 reserved_0[0x18];
3812 u8 reserved_1[0x20];
3814 u8 reserved_2[0x18];
3815 u8 admin_state[0x4];
3820 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3821 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3822 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
3825 struct mlx5_ifc_query_vport_state_in_bits {
3827 u8 reserved_0[0x10];
3829 u8 reserved_1[0x10];
3832 u8 other_vport[0x1];
3834 u8 vport_number[0x10];
3836 u8 reserved_3[0x20];
3839 struct mlx5_ifc_query_vport_counter_out_bits {
3841 u8 reserved_0[0x18];
3845 u8 reserved_1[0x40];
3847 struct mlx5_ifc_traffic_counter_bits received_errors;
3849 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3851 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3853 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3855 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3857 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3859 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3861 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3863 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3865 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3867 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3869 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3871 u8 reserved_2[0xa00];
3875 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3878 struct mlx5_ifc_query_vport_counter_in_bits {
3880 u8 reserved_0[0x10];
3882 u8 reserved_1[0x10];
3885 u8 other_vport[0x1];
3888 u8 vport_number[0x10];
3890 u8 reserved_3[0x60];
3893 u8 reserved_4[0x1f];
3895 u8 reserved_5[0x20];
3898 struct mlx5_ifc_query_tis_out_bits {
3900 u8 reserved_0[0x18];
3904 u8 reserved_1[0x40];
3906 struct mlx5_ifc_tisc_bits tis_context;
3909 struct mlx5_ifc_query_tis_in_bits {
3911 u8 reserved_0[0x10];
3913 u8 reserved_1[0x10];
3919 u8 reserved_3[0x20];
3922 struct mlx5_ifc_query_tir_out_bits {
3924 u8 reserved_0[0x18];
3928 u8 reserved_1[0xc0];
3930 struct mlx5_ifc_tirc_bits tir_context;
3933 struct mlx5_ifc_query_tir_in_bits {
3935 u8 reserved_0[0x10];
3937 u8 reserved_1[0x10];
3943 u8 reserved_3[0x20];
3946 struct mlx5_ifc_query_srq_out_bits {
3948 u8 reserved_0[0x18];
3952 u8 reserved_1[0x40];
3954 struct mlx5_ifc_srqc_bits srq_context_entry;
3956 u8 reserved_2[0x600];
3961 struct mlx5_ifc_query_srq_in_bits {
3963 u8 reserved_0[0x10];
3965 u8 reserved_1[0x10];
3971 u8 reserved_3[0x20];
3974 struct mlx5_ifc_query_sq_out_bits {
3976 u8 reserved_0[0x18];
3980 u8 reserved_1[0xc0];
3982 struct mlx5_ifc_sqc_bits sq_context;
3985 struct mlx5_ifc_query_sq_in_bits {
3987 u8 reserved_0[0x10];
3989 u8 reserved_1[0x10];
3995 u8 reserved_3[0x20];
3998 struct mlx5_ifc_query_special_contexts_out_bits {
4000 u8 reserved_0[0x18];
4004 u8 dump_fill_mkey[0x20];
4009 struct mlx5_ifc_query_special_contexts_in_bits {
4011 u8 reserved_0[0x10];
4013 u8 reserved_1[0x10];
4016 u8 reserved_2[0x40];
4019 struct mlx5_ifc_query_scheduling_element_out_bits {
4021 u8 reserved_at_8[0x18];
4025 u8 reserved_at_40[0xc0];
4027 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4029 u8 reserved_at_300[0x100];
4033 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4036 struct mlx5_ifc_query_scheduling_element_in_bits {
4038 u8 reserved_at_10[0x10];
4040 u8 reserved_at_20[0x10];
4043 u8 scheduling_hierarchy[0x8];
4044 u8 reserved_at_48[0x18];
4046 u8 scheduling_element_id[0x20];
4048 u8 reserved_at_80[0x180];
4051 struct mlx5_ifc_query_rqt_out_bits {
4053 u8 reserved_0[0x18];
4057 u8 reserved_1[0xc0];
4059 struct mlx5_ifc_rqtc_bits rqt_context;
4062 struct mlx5_ifc_query_rqt_in_bits {
4064 u8 reserved_0[0x10];
4066 u8 reserved_1[0x10];
4072 u8 reserved_3[0x20];
4075 struct mlx5_ifc_query_rq_out_bits {
4077 u8 reserved_0[0x18];
4081 u8 reserved_1[0xc0];
4083 struct mlx5_ifc_rqc_bits rq_context;
4086 struct mlx5_ifc_query_rq_in_bits {
4088 u8 reserved_0[0x10];
4090 u8 reserved_1[0x10];
4096 u8 reserved_3[0x20];
4099 struct mlx5_ifc_query_roce_address_out_bits {
4101 u8 reserved_0[0x18];
4105 u8 reserved_1[0x40];
4107 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4110 struct mlx5_ifc_query_roce_address_in_bits {
4112 u8 reserved_0[0x10];
4114 u8 reserved_1[0x10];
4117 u8 roce_address_index[0x10];
4118 u8 reserved_2[0x10];
4120 u8 reserved_3[0x20];
4123 struct mlx5_ifc_query_rmp_out_bits {
4125 u8 reserved_0[0x18];
4129 u8 reserved_1[0xc0];
4131 struct mlx5_ifc_rmpc_bits rmp_context;
4134 struct mlx5_ifc_query_rmp_in_bits {
4136 u8 reserved_0[0x10];
4138 u8 reserved_1[0x10];
4144 u8 reserved_3[0x20];
4147 struct mlx5_ifc_query_rdb_out_bits {
4149 u8 reserved_0[0x18];
4153 u8 reserved_1[0x20];
4155 u8 reserved_2[0x18];
4156 u8 rdb_list_size[0x8];
4158 struct mlx5_ifc_rdbc_bits rdb_context[0];
4161 struct mlx5_ifc_query_rdb_in_bits {
4163 u8 reserved_0[0x10];
4165 u8 reserved_1[0x10];
4171 u8 reserved_3[0x20];
4174 struct mlx5_ifc_query_qp_out_bits {
4176 u8 reserved_0[0x18];
4180 u8 reserved_1[0x40];
4182 u8 opt_param_mask[0x20];
4184 u8 reserved_2[0x20];
4186 struct mlx5_ifc_qpc_bits qpc;
4188 u8 reserved_3[0x80];
4193 struct mlx5_ifc_query_qp_in_bits {
4195 u8 reserved_0[0x10];
4197 u8 reserved_1[0x10];
4203 u8 reserved_3[0x20];
4206 struct mlx5_ifc_query_q_counter_out_bits {
4208 u8 reserved_0[0x18];
4212 u8 reserved_1[0x40];
4214 u8 rx_write_requests[0x20];
4216 u8 reserved_2[0x20];
4218 u8 rx_read_requests[0x20];
4220 u8 reserved_3[0x20];
4222 u8 rx_atomic_requests[0x20];
4224 u8 reserved_4[0x20];
4226 u8 rx_dct_connect[0x20];
4228 u8 reserved_5[0x20];
4230 u8 out_of_buffer[0x20];
4232 u8 reserved_7[0x20];
4234 u8 out_of_sequence[0x20];
4236 u8 reserved_8[0x20];
4238 u8 duplicate_request[0x20];
4240 u8 reserved_9[0x20];
4242 u8 rnr_nak_retry_err[0x20];
4244 u8 reserved_10[0x20];
4246 u8 packet_seq_err[0x20];
4248 u8 reserved_11[0x20];
4250 u8 implied_nak_seq_err[0x20];
4252 u8 reserved_12[0x20];
4254 u8 local_ack_timeout_err[0x20];
4256 u8 reserved_13[0x20];
4258 u8 resp_rnr_nak[0x20];
4260 u8 reserved_14[0x20];
4262 u8 req_rnr_retries_exceeded[0x20];
4264 u8 reserved_15[0x460];
4267 struct mlx5_ifc_query_q_counter_in_bits {
4269 u8 reserved_0[0x10];
4271 u8 reserved_1[0x10];
4274 u8 reserved_2[0x80];
4277 u8 reserved_3[0x1f];
4279 u8 reserved_4[0x18];
4280 u8 counter_set_id[0x8];
4283 struct mlx5_ifc_query_pages_out_bits {
4285 u8 reserved_0[0x18];
4289 u8 reserved_1[0x10];
4290 u8 function_id[0x10];
4296 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4297 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4298 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4301 struct mlx5_ifc_query_pages_in_bits {
4303 u8 reserved_0[0x10];
4305 u8 reserved_1[0x10];
4308 u8 reserved_2[0x10];
4309 u8 function_id[0x10];
4311 u8 reserved_3[0x20];
4314 struct mlx5_ifc_query_nic_vport_context_out_bits {
4316 u8 reserved_0[0x18];
4320 u8 reserved_1[0x40];
4322 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4325 struct mlx5_ifc_query_nic_vport_context_in_bits {
4327 u8 reserved_0[0x10];
4329 u8 reserved_1[0x10];
4332 u8 other_vport[0x1];
4334 u8 vport_number[0x10];
4337 u8 allowed_list_type[0x3];
4338 u8 reserved_4[0x18];
4341 struct mlx5_ifc_query_mkey_out_bits {
4343 u8 reserved_0[0x18];
4347 u8 reserved_1[0x40];
4349 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4351 u8 reserved_2[0x600];
4353 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4355 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4358 struct mlx5_ifc_query_mkey_in_bits {
4360 u8 reserved_0[0x10];
4362 u8 reserved_1[0x10];
4366 u8 mkey_index[0x18];
4369 u8 reserved_3[0x1f];
4372 struct mlx5_ifc_query_mad_demux_out_bits {
4374 u8 reserved_0[0x18];
4378 u8 reserved_1[0x40];
4380 u8 mad_dumux_parameters_block[0x20];
4383 struct mlx5_ifc_query_mad_demux_in_bits {
4385 u8 reserved_0[0x10];
4387 u8 reserved_1[0x10];
4390 u8 reserved_2[0x40];
4393 struct mlx5_ifc_query_l2_table_entry_out_bits {
4395 u8 reserved_0[0x18];
4399 u8 reserved_1[0xa0];
4401 u8 reserved_2[0x13];
4405 struct mlx5_ifc_mac_address_layout_bits mac_address;
4407 u8 reserved_3[0xc0];
4410 struct mlx5_ifc_query_l2_table_entry_in_bits {
4412 u8 reserved_0[0x10];
4414 u8 reserved_1[0x10];
4417 u8 reserved_2[0x60];
4420 u8 table_index[0x18];
4422 u8 reserved_4[0x140];
4425 struct mlx5_ifc_query_issi_out_bits {
4427 u8 reserved_0[0x18];
4431 u8 reserved_1[0x10];
4432 u8 current_issi[0x10];
4434 u8 reserved_2[0xa0];
4436 u8 supported_issi_reserved[76][0x8];
4437 u8 supported_issi_dw0[0x20];
4440 struct mlx5_ifc_query_issi_in_bits {
4442 u8 reserved_0[0x10];
4444 u8 reserved_1[0x10];
4447 u8 reserved_2[0x40];
4450 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4452 u8 reserved_0[0x18];
4456 u8 reserved_1[0x40];
4458 struct mlx5_ifc_pkey_bits pkey[0];
4461 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4463 u8 reserved_0[0x10];
4465 u8 reserved_1[0x10];
4468 u8 other_vport[0x1];
4471 u8 vport_number[0x10];
4473 u8 reserved_3[0x10];
4474 u8 pkey_index[0x10];
4477 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4479 u8 reserved_0[0x18];
4483 u8 reserved_1[0x20];
4486 u8 reserved_2[0x10];
4488 struct mlx5_ifc_array128_auto_bits gid[0];
4491 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4493 u8 reserved_0[0x10];
4495 u8 reserved_1[0x10];
4498 u8 other_vport[0x1];
4501 u8 vport_number[0x10];
4503 u8 reserved_3[0x10];
4507 struct mlx5_ifc_query_hca_vport_context_out_bits {
4509 u8 reserved_0[0x18];
4513 u8 reserved_1[0x40];
4515 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4518 struct mlx5_ifc_query_hca_vport_context_in_bits {
4520 u8 reserved_0[0x10];
4522 u8 reserved_1[0x10];
4525 u8 other_vport[0x1];
4528 u8 vport_number[0x10];
4530 u8 reserved_3[0x20];
4533 struct mlx5_ifc_query_hca_cap_out_bits {
4535 u8 reserved_0[0x18];
4539 u8 reserved_1[0x40];
4541 union mlx5_ifc_hca_cap_union_bits capability;
4544 struct mlx5_ifc_query_hca_cap_in_bits {
4546 u8 reserved_0[0x10];
4548 u8 reserved_1[0x10];
4551 u8 reserved_2[0x40];
4554 struct mlx5_ifc_query_flow_table_out_bits {
4556 u8 reserved_at_8[0x18];
4560 u8 reserved_at_40[0x80];
4562 struct mlx5_ifc_flow_table_context_bits flow_table_context;
4565 struct mlx5_ifc_query_flow_table_in_bits {
4567 u8 reserved_0[0x10];
4569 u8 reserved_1[0x10];
4572 u8 other_vport[0x1];
4574 u8 vport_number[0x10];
4576 u8 reserved_3[0x20];
4579 u8 reserved_4[0x18];
4584 u8 reserved_6[0x140];
4587 struct mlx5_ifc_query_fte_out_bits {
4589 u8 reserved_0[0x18];
4593 u8 reserved_1[0x1c0];
4595 struct mlx5_ifc_flow_context_bits flow_context;
4598 struct mlx5_ifc_query_fte_in_bits {
4600 u8 reserved_0[0x10];
4602 u8 reserved_1[0x10];
4605 u8 other_vport[0x1];
4607 u8 vport_number[0x10];
4609 u8 reserved_3[0x20];
4612 u8 reserved_4[0x18];
4617 u8 reserved_6[0x40];
4619 u8 flow_index[0x20];
4621 u8 reserved_7[0xe0];
4625 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4626 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4627 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4630 struct mlx5_ifc_query_flow_group_out_bits {
4632 u8 reserved_0[0x18];
4636 u8 reserved_1[0xa0];
4638 u8 start_flow_index[0x20];
4640 u8 reserved_2[0x20];
4642 u8 end_flow_index[0x20];
4644 u8 reserved_3[0xa0];
4646 u8 reserved_4[0x18];
4647 u8 match_criteria_enable[0x8];
4649 struct mlx5_ifc_fte_match_param_bits match_criteria;
4651 u8 reserved_5[0xe00];
4654 struct mlx5_ifc_query_flow_group_in_bits {
4656 u8 reserved_0[0x10];
4658 u8 reserved_1[0x10];
4661 u8 other_vport[0x1];
4663 u8 vport_number[0x10];
4665 u8 reserved_3[0x20];
4668 u8 reserved_4[0x18];
4675 u8 reserved_6[0x120];
4678 struct mlx5_ifc_query_flow_counter_out_bits {
4680 u8 reserved_at_8[0x18];
4684 u8 reserved_at_40[0x40];
4686 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4689 struct mlx5_ifc_query_flow_counter_in_bits {
4691 u8 reserved_at_10[0x10];
4693 u8 reserved_at_20[0x10];
4696 u8 reserved_at_40[0x80];
4699 u8 reserved_at_c1[0xf];
4700 u8 num_of_counters[0x10];
4702 u8 reserved_at_e0[0x10];
4703 u8 flow_counter_id[0x10];
4706 struct mlx5_ifc_query_esw_vport_context_out_bits {
4708 u8 reserved_0[0x18];
4712 u8 reserved_1[0x40];
4714 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4717 struct mlx5_ifc_query_esw_vport_context_in_bits {
4719 u8 reserved_0[0x10];
4721 u8 reserved_1[0x10];
4724 u8 other_vport[0x1];
4726 u8 vport_number[0x10];
4728 u8 reserved_3[0x20];
4731 struct mlx5_ifc_query_eq_out_bits {
4733 u8 reserved_0[0x18];
4737 u8 reserved_1[0x40];
4739 struct mlx5_ifc_eqc_bits eq_context_entry;
4741 u8 reserved_2[0x40];
4743 u8 event_bitmask[0x40];
4745 u8 reserved_3[0x580];
4750 struct mlx5_ifc_query_eq_in_bits {
4752 u8 reserved_0[0x10];
4754 u8 reserved_1[0x10];
4757 u8 reserved_2[0x18];
4760 u8 reserved_3[0x20];
4763 struct mlx5_ifc_query_dct_out_bits {
4765 u8 reserved_0[0x18];
4769 u8 reserved_1[0x40];
4771 struct mlx5_ifc_dctc_bits dct_context_entry;
4773 u8 reserved_2[0x180];
4776 struct mlx5_ifc_query_dct_in_bits {
4778 u8 reserved_0[0x10];
4780 u8 reserved_1[0x10];
4786 u8 reserved_3[0x20];
4789 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4791 u8 reserved_0[0x18];
4796 u8 reserved_1[0x1f];
4798 u8 reserved_2[0x160];
4800 struct mlx5_ifc_cmd_pas_bits pas;
4803 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4805 u8 reserved_0[0x10];
4807 u8 reserved_1[0x10];
4810 u8 reserved_2[0x40];
4813 struct mlx5_ifc_query_cq_out_bits {
4815 u8 reserved_0[0x18];
4819 u8 reserved_1[0x40];
4821 struct mlx5_ifc_cqc_bits cq_context;
4823 u8 reserved_2[0x600];
4828 struct mlx5_ifc_query_cq_in_bits {
4830 u8 reserved_0[0x10];
4832 u8 reserved_1[0x10];
4838 u8 reserved_3[0x20];
4841 struct mlx5_ifc_query_cong_status_out_bits {
4843 u8 reserved_0[0x18];
4847 u8 reserved_1[0x20];
4851 u8 reserved_2[0x1e];
4854 struct mlx5_ifc_query_cong_status_in_bits {
4856 u8 reserved_0[0x10];
4858 u8 reserved_1[0x10];
4861 u8 reserved_2[0x18];
4863 u8 cong_protocol[0x4];
4865 u8 reserved_3[0x20];
4868 struct mlx5_ifc_query_cong_statistics_out_bits {
4870 u8 reserved_0[0x18];
4874 u8 reserved_1[0x40];
4876 u8 rp_cur_flows[0x20];
4880 u8 rp_cnp_ignored_high[0x20];
4882 u8 rp_cnp_ignored_low[0x20];
4884 u8 rp_cnp_handled_high[0x20];
4886 u8 rp_cnp_handled_low[0x20];
4888 u8 reserved_2[0x100];
4890 u8 time_stamp_high[0x20];
4892 u8 time_stamp_low[0x20];
4894 u8 accumulators_period[0x20];
4896 u8 np_ecn_marked_roce_packets_high[0x20];
4898 u8 np_ecn_marked_roce_packets_low[0x20];
4900 u8 np_cnp_sent_high[0x20];
4902 u8 np_cnp_sent_low[0x20];
4904 u8 reserved_3[0x560];
4907 struct mlx5_ifc_query_cong_statistics_in_bits {
4909 u8 reserved_0[0x10];
4911 u8 reserved_1[0x10];
4915 u8 reserved_2[0x1f];
4917 u8 reserved_3[0x20];
4920 struct mlx5_ifc_query_cong_params_out_bits {
4922 u8 reserved_0[0x18];
4926 u8 reserved_1[0x40];
4928 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4931 struct mlx5_ifc_query_cong_params_in_bits {
4933 u8 reserved_0[0x10];
4935 u8 reserved_1[0x10];
4938 u8 reserved_2[0x1c];
4939 u8 cong_protocol[0x4];
4941 u8 reserved_3[0x20];
4944 struct mlx5_ifc_query_burst_size_out_bits {
4946 u8 reserved_0[0x18];
4950 u8 reserved_1[0x20];
4953 u8 device_burst_size[0x17];
4956 struct mlx5_ifc_query_burst_size_in_bits {
4958 u8 reserved_0[0x10];
4960 u8 reserved_1[0x10];
4963 u8 reserved_2[0x40];
4966 struct mlx5_ifc_query_adapter_out_bits {
4968 u8 reserved_0[0x18];
4972 u8 reserved_1[0x40];
4974 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4977 struct mlx5_ifc_query_adapter_in_bits {
4979 u8 reserved_0[0x10];
4981 u8 reserved_1[0x10];
4984 u8 reserved_2[0x40];
4987 struct mlx5_ifc_qp_2rst_out_bits {
4989 u8 reserved_0[0x18];
4993 u8 reserved_1[0x40];
4996 struct mlx5_ifc_qp_2rst_in_bits {
4998 u8 reserved_0[0x10];
5000 u8 reserved_1[0x10];
5006 u8 reserved_3[0x20];
5009 struct mlx5_ifc_qp_2err_out_bits {
5011 u8 reserved_0[0x18];
5015 u8 reserved_1[0x40];
5018 struct mlx5_ifc_qp_2err_in_bits {
5020 u8 reserved_0[0x10];
5022 u8 reserved_1[0x10];
5028 u8 reserved_3[0x20];
5031 struct mlx5_ifc_para_vport_element_bits {
5032 u8 reserved_at_0[0xc];
5033 u8 traffic_class[0x4];
5034 u8 qos_para_vport_number[0x10];
5037 struct mlx5_ifc_page_fault_resume_out_bits {
5039 u8 reserved_0[0x18];
5043 u8 reserved_1[0x40];
5046 struct mlx5_ifc_page_fault_resume_in_bits {
5048 u8 reserved_0[0x10];
5050 u8 reserved_1[0x10];
5060 u8 reserved_3[0x20];
5063 struct mlx5_ifc_nop_out_bits {
5065 u8 reserved_0[0x18];
5069 u8 reserved_1[0x40];
5072 struct mlx5_ifc_nop_in_bits {
5074 u8 reserved_0[0x10];
5076 u8 reserved_1[0x10];
5079 u8 reserved_2[0x40];
5082 struct mlx5_ifc_modify_vport_state_out_bits {
5084 u8 reserved_0[0x18];
5088 u8 reserved_1[0x40];
5092 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0,
5093 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
5094 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
5098 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0,
5099 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1,
5100 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2,
5103 struct mlx5_ifc_modify_vport_state_in_bits {
5105 u8 reserved_0[0x10];
5107 u8 reserved_1[0x10];
5110 u8 other_vport[0x1];
5112 u8 vport_number[0x10];
5114 u8 reserved_3[0x18];
5115 u8 admin_state[0x4];
5119 struct mlx5_ifc_modify_tis_out_bits {
5121 u8 reserved_0[0x18];
5125 u8 reserved_1[0x40];
5128 struct mlx5_ifc_modify_tis_bitmask_bits {
5129 u8 reserved_at_0[0x20];
5131 u8 reserved_at_20[0x1d];
5132 u8 lag_tx_port_affinity[0x1];
5133 u8 strict_lag_tx_port_affinity[0x1];
5137 struct mlx5_ifc_modify_tis_in_bits {
5139 u8 reserved_0[0x10];
5141 u8 reserved_1[0x10];
5147 u8 reserved_3[0x20];
5149 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5151 u8 reserved_4[0x40];
5153 struct mlx5_ifc_tisc_bits ctx;
5156 struct mlx5_ifc_modify_tir_out_bits {
5158 u8 reserved_0[0x18];
5162 u8 reserved_1[0x40];
5167 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5168 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1
5171 struct mlx5_ifc_modify_tir_in_bits {
5173 u8 reserved_0[0x10];
5175 u8 reserved_1[0x10];
5181 u8 reserved_3[0x20];
5183 u8 modify_bitmask[0x40];
5185 u8 reserved_4[0x40];
5187 struct mlx5_ifc_tirc_bits tir_context;
5190 struct mlx5_ifc_modify_sq_out_bits {
5192 u8 reserved_0[0x18];
5196 u8 reserved_1[0x40];
5199 struct mlx5_ifc_modify_sq_in_bits {
5201 u8 reserved_0[0x10];
5203 u8 reserved_1[0x10];
5210 u8 reserved_3[0x20];
5212 u8 modify_bitmask[0x40];
5214 u8 reserved_4[0x40];
5216 struct mlx5_ifc_sqc_bits ctx;
5219 struct mlx5_ifc_modify_scheduling_element_out_bits {
5221 u8 reserved_at_8[0x18];
5225 u8 reserved_at_40[0x1c0];
5229 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5233 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1,
5234 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2,
5237 struct mlx5_ifc_modify_scheduling_element_in_bits {
5239 u8 reserved_at_10[0x10];
5241 u8 reserved_at_20[0x10];
5244 u8 scheduling_hierarchy[0x8];
5245 u8 reserved_at_48[0x18];
5247 u8 scheduling_element_id[0x20];
5249 u8 reserved_at_80[0x20];
5251 u8 modify_bitmask[0x20];
5253 u8 reserved_at_c0[0x40];
5255 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5257 u8 reserved_at_300[0x100];
5260 struct mlx5_ifc_modify_rqt_out_bits {
5262 u8 reserved_0[0x18];
5266 u8 reserved_1[0x40];
5269 struct mlx5_ifc_modify_rqt_in_bits {
5271 u8 reserved_0[0x10];
5273 u8 reserved_1[0x10];
5279 u8 reserved_3[0x20];
5281 u8 modify_bitmask[0x40];
5283 u8 reserved_4[0x40];
5285 struct mlx5_ifc_rqtc_bits ctx;
5288 struct mlx5_ifc_modify_rq_out_bits {
5290 u8 reserved_0[0x18];
5294 u8 reserved_1[0x40];
5298 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5299 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5302 struct mlx5_ifc_modify_rq_in_bits {
5304 u8 reserved_0[0x10];
5306 u8 reserved_1[0x10];
5313 u8 reserved_3[0x20];
5315 u8 modify_bitmask[0x40];
5317 u8 reserved_4[0x40];
5319 struct mlx5_ifc_rqc_bits ctx;
5322 struct mlx5_ifc_modify_rmp_out_bits {
5324 u8 reserved_0[0x18];
5328 u8 reserved_1[0x40];
5331 struct mlx5_ifc_rmp_bitmask_bits {
5338 struct mlx5_ifc_modify_rmp_in_bits {
5340 u8 reserved_0[0x10];
5342 u8 reserved_1[0x10];
5349 u8 reserved_3[0x20];
5351 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5353 u8 reserved_4[0x40];
5355 struct mlx5_ifc_rmpc_bits ctx;
5358 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5360 u8 reserved_0[0x18];
5364 u8 reserved_1[0x40];
5367 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5368 u8 reserved_0[0x14];
5369 u8 disable_uc_local_lb[0x1];
5370 u8 disable_mc_local_lb[0x1];
5373 u8 min_wqe_inline_mode[0x1];
5375 u8 change_event[0x1];
5377 u8 permanent_address[0x1];
5378 u8 addresses_list[0x1];
5383 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5385 u8 reserved_0[0x10];
5387 u8 reserved_1[0x10];
5390 u8 other_vport[0x1];
5392 u8 vport_number[0x10];
5394 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5396 u8 reserved_3[0x780];
5398 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5401 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5403 u8 reserved_0[0x18];
5407 u8 reserved_1[0x40];
5410 struct mlx5_ifc_grh_bits {
5412 u8 traffic_class[8];
5414 u8 payload_length[16];
5421 struct mlx5_ifc_bth_bits {
5435 struct mlx5_ifc_aeth_bits {
5440 struct mlx5_ifc_dceth_bits {
5447 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5449 u8 reserved_0[0x10];
5451 u8 reserved_1[0x10];
5454 u8 other_vport[0x1];
5457 u8 vport_number[0x10];
5459 u8 reserved_3[0x20];
5461 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5464 struct mlx5_ifc_modify_flow_table_out_bits {
5466 u8 reserved_at_8[0x18];
5470 u8 reserved_at_40[0x40];
5474 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5475 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5478 struct mlx5_ifc_modify_flow_table_in_bits {
5480 u8 reserved_at_10[0x10];
5482 u8 reserved_at_20[0x10];
5485 u8 other_vport[0x1];
5486 u8 reserved_at_41[0xf];
5487 u8 vport_number[0x10];
5489 u8 reserved_at_60[0x10];
5490 u8 modify_field_select[0x10];
5493 u8 reserved_at_88[0x18];
5495 u8 reserved_at_a0[0x8];
5498 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5501 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5503 u8 reserved_0[0x18];
5507 u8 reserved_1[0x40];
5510 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5512 u8 vport_cvlan_insert[0x1];
5513 u8 vport_svlan_insert[0x1];
5514 u8 vport_cvlan_strip[0x1];
5515 u8 vport_svlan_strip[0x1];
5518 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5520 u8 reserved_0[0x10];
5522 u8 reserved_1[0x10];
5525 u8 other_vport[0x1];
5527 u8 vport_number[0x10];
5529 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5531 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5534 struct mlx5_ifc_modify_cq_out_bits {
5536 u8 reserved_0[0x18];
5540 u8 reserved_1[0x40];
5544 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5545 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5548 struct mlx5_ifc_modify_cq_in_bits {
5550 u8 reserved_0[0x10];
5552 u8 reserved_1[0x10];
5558 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5560 struct mlx5_ifc_cqc_bits cq_context;
5562 u8 reserved_3[0x600];
5567 struct mlx5_ifc_modify_cong_status_out_bits {
5569 u8 reserved_0[0x18];
5573 u8 reserved_1[0x40];
5576 struct mlx5_ifc_modify_cong_status_in_bits {
5578 u8 reserved_0[0x10];
5580 u8 reserved_1[0x10];
5583 u8 reserved_2[0x18];
5585 u8 cong_protocol[0x4];
5589 u8 reserved_3[0x1e];
5592 struct mlx5_ifc_modify_cong_params_out_bits {
5594 u8 reserved_0[0x18];
5598 u8 reserved_1[0x40];
5601 struct mlx5_ifc_modify_cong_params_in_bits {
5603 u8 reserved_0[0x10];
5605 u8 reserved_1[0x10];
5608 u8 reserved_2[0x1c];
5609 u8 cong_protocol[0x4];
5611 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5613 u8 reserved_3[0x80];
5615 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5618 struct mlx5_ifc_manage_pages_out_bits {
5620 u8 reserved_0[0x18];
5624 u8 output_num_entries[0x20];
5626 u8 reserved_1[0x20];
5632 MLX5_PAGES_CANT_GIVE = 0x0,
5633 MLX5_PAGES_GIVE = 0x1,
5634 MLX5_PAGES_TAKE = 0x2,
5637 struct mlx5_ifc_manage_pages_in_bits {
5639 u8 reserved_0[0x10];
5641 u8 reserved_1[0x10];
5644 u8 reserved_2[0x10];
5645 u8 function_id[0x10];
5647 u8 input_num_entries[0x20];
5652 struct mlx5_ifc_mad_ifc_out_bits {
5654 u8 reserved_0[0x18];
5658 u8 reserved_1[0x40];
5660 u8 response_mad_packet[256][0x8];
5663 struct mlx5_ifc_mad_ifc_in_bits {
5665 u8 reserved_0[0x10];
5667 u8 reserved_1[0x10];
5670 u8 remote_lid[0x10];
5674 u8 reserved_3[0x20];
5679 struct mlx5_ifc_init_hca_out_bits {
5681 u8 reserved_0[0x18];
5685 u8 reserved_1[0x40];
5689 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0,
5690 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1,
5693 struct mlx5_ifc_init_hca_in_bits {
5695 u8 reserved_0[0x10];
5697 u8 reserved_1[0x10];
5700 u8 reserved_2[0x40];
5703 struct mlx5_ifc_init2rtr_qp_out_bits {
5705 u8 reserved_0[0x18];
5709 u8 reserved_1[0x40];
5712 struct mlx5_ifc_init2rtr_qp_in_bits {
5714 u8 reserved_0[0x10];
5716 u8 reserved_1[0x10];
5722 u8 reserved_3[0x20];
5724 u8 opt_param_mask[0x20];
5726 u8 reserved_4[0x20];
5728 struct mlx5_ifc_qpc_bits qpc;
5730 u8 reserved_5[0x80];
5733 struct mlx5_ifc_init2init_qp_out_bits {
5735 u8 reserved_0[0x18];
5739 u8 reserved_1[0x40];
5742 struct mlx5_ifc_init2init_qp_in_bits {
5744 u8 reserved_0[0x10];
5746 u8 reserved_1[0x10];
5752 u8 reserved_3[0x20];
5754 u8 opt_param_mask[0x20];
5756 u8 reserved_4[0x20];
5758 struct mlx5_ifc_qpc_bits qpc;
5760 u8 reserved_5[0x80];
5763 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5765 u8 reserved_0[0x18];
5769 u8 reserved_1[0x40];
5771 u8 packet_headers_log[128][0x8];
5773 u8 packet_syndrome[64][0x8];
5776 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5778 u8 reserved_0[0x10];
5780 u8 reserved_1[0x10];
5783 u8 reserved_2[0x40];
5786 struct mlx5_ifc_gen_eqe_in_bits {
5788 u8 reserved_0[0x10];
5790 u8 reserved_1[0x10];
5793 u8 reserved_2[0x18];
5796 u8 reserved_3[0x20];
5801 struct mlx5_ifc_gen_eq_out_bits {
5803 u8 reserved_0[0x18];
5807 u8 reserved_1[0x40];
5810 struct mlx5_ifc_enable_hca_out_bits {
5812 u8 reserved_0[0x18];
5816 u8 reserved_1[0x20];
5819 struct mlx5_ifc_enable_hca_in_bits {
5821 u8 reserved_0[0x10];
5823 u8 reserved_1[0x10];
5826 u8 reserved_2[0x10];
5827 u8 function_id[0x10];
5829 u8 reserved_3[0x20];
5832 struct mlx5_ifc_drain_dct_out_bits {
5834 u8 reserved_0[0x18];
5838 u8 reserved_1[0x40];
5841 struct mlx5_ifc_drain_dct_in_bits {
5843 u8 reserved_0[0x10];
5845 u8 reserved_1[0x10];
5851 u8 reserved_3[0x20];
5854 struct mlx5_ifc_disable_hca_out_bits {
5856 u8 reserved_0[0x18];
5860 u8 reserved_1[0x20];
5863 struct mlx5_ifc_disable_hca_in_bits {
5865 u8 reserved_0[0x10];
5867 u8 reserved_1[0x10];
5870 u8 reserved_2[0x10];
5871 u8 function_id[0x10];
5873 u8 reserved_3[0x20];
5876 struct mlx5_ifc_detach_from_mcg_out_bits {
5878 u8 reserved_0[0x18];
5882 u8 reserved_1[0x40];
5885 struct mlx5_ifc_detach_from_mcg_in_bits {
5887 u8 reserved_0[0x10];
5889 u8 reserved_1[0x10];
5895 u8 reserved_3[0x20];
5897 u8 multicast_gid[16][0x8];
5900 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5902 u8 reserved_0[0x18];
5906 u8 reserved_1[0x40];
5909 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5911 u8 reserved_0[0x10];
5913 u8 reserved_1[0x10];
5919 u8 reserved_3[0x20];
5922 struct mlx5_ifc_destroy_tis_out_bits {
5924 u8 reserved_0[0x18];
5928 u8 reserved_1[0x40];
5931 struct mlx5_ifc_destroy_tis_in_bits {
5933 u8 reserved_0[0x10];
5935 u8 reserved_1[0x10];
5941 u8 reserved_3[0x20];
5944 struct mlx5_ifc_destroy_tir_out_bits {
5946 u8 reserved_0[0x18];
5950 u8 reserved_1[0x40];
5953 struct mlx5_ifc_destroy_tir_in_bits {
5955 u8 reserved_0[0x10];
5957 u8 reserved_1[0x10];
5963 u8 reserved_3[0x20];
5966 struct mlx5_ifc_destroy_srq_out_bits {
5968 u8 reserved_0[0x18];
5972 u8 reserved_1[0x40];
5975 struct mlx5_ifc_destroy_srq_in_bits {
5977 u8 reserved_0[0x10];
5979 u8 reserved_1[0x10];
5985 u8 reserved_3[0x20];
5988 struct mlx5_ifc_destroy_sq_out_bits {
5990 u8 reserved_0[0x18];
5994 u8 reserved_1[0x40];
5997 struct mlx5_ifc_destroy_sq_in_bits {
5999 u8 reserved_0[0x10];
6001 u8 reserved_1[0x10];
6007 u8 reserved_3[0x20];
6010 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6012 u8 reserved_at_8[0x18];
6016 u8 reserved_at_40[0x1c0];
6020 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6023 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6025 u8 reserved_at_10[0x10];
6027 u8 reserved_at_20[0x10];
6030 u8 scheduling_hierarchy[0x8];
6031 u8 reserved_at_48[0x18];
6033 u8 scheduling_element_id[0x20];
6035 u8 reserved_at_80[0x180];
6038 struct mlx5_ifc_destroy_rqt_out_bits {
6040 u8 reserved_0[0x18];
6044 u8 reserved_1[0x40];
6047 struct mlx5_ifc_destroy_rqt_in_bits {
6049 u8 reserved_0[0x10];
6051 u8 reserved_1[0x10];
6057 u8 reserved_3[0x20];
6060 struct mlx5_ifc_destroy_rq_out_bits {
6062 u8 reserved_0[0x18];
6066 u8 reserved_1[0x40];
6069 struct mlx5_ifc_destroy_rq_in_bits {
6071 u8 reserved_0[0x10];
6073 u8 reserved_1[0x10];
6079 u8 reserved_3[0x20];
6082 struct mlx5_ifc_destroy_rmp_out_bits {
6084 u8 reserved_0[0x18];
6088 u8 reserved_1[0x40];
6091 struct mlx5_ifc_destroy_rmp_in_bits {
6093 u8 reserved_0[0x10];
6095 u8 reserved_1[0x10];
6101 u8 reserved_3[0x20];
6104 struct mlx5_ifc_destroy_qp_out_bits {
6106 u8 reserved_0[0x18];
6110 u8 reserved_1[0x40];
6113 struct mlx5_ifc_destroy_qp_in_bits {
6115 u8 reserved_0[0x10];
6117 u8 reserved_1[0x10];
6123 u8 reserved_3[0x20];
6126 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6128 u8 reserved_at_8[0x18];
6132 u8 reserved_at_40[0x1c0];
6135 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6137 u8 reserved_at_10[0x10];
6139 u8 reserved_at_20[0x10];
6142 u8 reserved_at_40[0x20];
6144 u8 reserved_at_60[0x10];
6145 u8 qos_para_vport_number[0x10];
6147 u8 reserved_at_80[0x180];
6150 struct mlx5_ifc_destroy_psv_out_bits {
6152 u8 reserved_0[0x18];
6156 u8 reserved_1[0x40];
6159 struct mlx5_ifc_destroy_psv_in_bits {
6161 u8 reserved_0[0x10];
6163 u8 reserved_1[0x10];
6169 u8 reserved_3[0x20];
6172 struct mlx5_ifc_destroy_mkey_out_bits {
6174 u8 reserved_0[0x18];
6178 u8 reserved_1[0x40];
6181 struct mlx5_ifc_destroy_mkey_in_bits {
6183 u8 reserved_0[0x10];
6185 u8 reserved_1[0x10];
6189 u8 mkey_index[0x18];
6191 u8 reserved_3[0x20];
6194 struct mlx5_ifc_destroy_flow_table_out_bits {
6196 u8 reserved_0[0x18];
6200 u8 reserved_1[0x40];
6203 struct mlx5_ifc_destroy_flow_table_in_bits {
6205 u8 reserved_0[0x10];
6207 u8 reserved_1[0x10];
6210 u8 other_vport[0x1];
6212 u8 vport_number[0x10];
6214 u8 reserved_3[0x20];
6217 u8 reserved_4[0x18];
6222 u8 reserved_6[0x140];
6225 struct mlx5_ifc_destroy_flow_group_out_bits {
6227 u8 reserved_0[0x18];
6231 u8 reserved_1[0x40];
6234 struct mlx5_ifc_destroy_flow_group_in_bits {
6236 u8 reserved_0[0x10];
6238 u8 reserved_1[0x10];
6241 u8 other_vport[0x1];
6243 u8 vport_number[0x10];
6245 u8 reserved_3[0x20];
6248 u8 reserved_4[0x18];
6255 u8 reserved_6[0x120];
6258 struct mlx5_ifc_destroy_eq_out_bits {
6260 u8 reserved_0[0x18];
6264 u8 reserved_1[0x40];
6267 struct mlx5_ifc_destroy_eq_in_bits {
6269 u8 reserved_0[0x10];
6271 u8 reserved_1[0x10];
6274 u8 reserved_2[0x18];
6277 u8 reserved_3[0x20];
6280 struct mlx5_ifc_destroy_dct_out_bits {
6282 u8 reserved_0[0x18];
6286 u8 reserved_1[0x40];
6289 struct mlx5_ifc_destroy_dct_in_bits {
6291 u8 reserved_0[0x10];
6293 u8 reserved_1[0x10];
6299 u8 reserved_3[0x20];
6302 struct mlx5_ifc_destroy_cq_out_bits {
6304 u8 reserved_0[0x18];
6308 u8 reserved_1[0x40];
6311 struct mlx5_ifc_destroy_cq_in_bits {
6313 u8 reserved_0[0x10];
6315 u8 reserved_1[0x10];
6321 u8 reserved_3[0x20];
6324 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6326 u8 reserved_0[0x18];
6330 u8 reserved_1[0x40];
6333 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6335 u8 reserved_0[0x10];
6337 u8 reserved_1[0x10];
6340 u8 reserved_2[0x20];
6342 u8 reserved_3[0x10];
6343 u8 vxlan_udp_port[0x10];
6346 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6348 u8 reserved_0[0x18];
6352 u8 reserved_1[0x40];
6355 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6357 u8 reserved_0[0x10];
6359 u8 reserved_1[0x10];
6362 u8 reserved_2[0x60];
6365 u8 table_index[0x18];
6367 u8 reserved_4[0x140];
6370 struct mlx5_ifc_delete_fte_out_bits {
6372 u8 reserved_0[0x18];
6376 u8 reserved_1[0x40];
6379 struct mlx5_ifc_delete_fte_in_bits {
6381 u8 reserved_0[0x10];
6383 u8 reserved_1[0x10];
6386 u8 other_vport[0x1];
6388 u8 vport_number[0x10];
6390 u8 reserved_3[0x20];
6393 u8 reserved_4[0x18];
6398 u8 reserved_6[0x40];
6400 u8 flow_index[0x20];
6402 u8 reserved_7[0xe0];
6405 struct mlx5_ifc_dealloc_xrcd_out_bits {
6407 u8 reserved_0[0x18];
6411 u8 reserved_1[0x40];
6414 struct mlx5_ifc_dealloc_xrcd_in_bits {
6416 u8 reserved_0[0x10];
6418 u8 reserved_1[0x10];
6424 u8 reserved_3[0x20];
6427 struct mlx5_ifc_dealloc_uar_out_bits {
6429 u8 reserved_0[0x18];
6433 u8 reserved_1[0x40];
6436 struct mlx5_ifc_dealloc_uar_in_bits {
6438 u8 reserved_0[0x10];
6440 u8 reserved_1[0x10];
6446 u8 reserved_3[0x20];
6449 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6451 u8 reserved_0[0x18];
6455 u8 reserved_1[0x40];
6458 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6460 u8 reserved_0[0x10];
6462 u8 reserved_1[0x10];
6466 u8 transport_domain[0x18];
6468 u8 reserved_3[0x20];
6471 struct mlx5_ifc_dealloc_q_counter_out_bits {
6473 u8 reserved_0[0x18];
6477 u8 reserved_1[0x40];
6480 struct mlx5_ifc_counter_id_bits {
6482 u8 counter_id[0x10];
6485 struct mlx5_ifc_diagnostic_params_context_bits {
6486 u8 num_of_counters[0x10];
6488 u8 log_num_of_samples[0x8];
6496 u8 reserved_3[0x12];
6497 u8 log_sample_period[0x8];
6499 u8 reserved_4[0x80];
6501 struct mlx5_ifc_counter_id_bits counter_id[0];
6504 struct mlx5_ifc_set_diagnostic_params_in_bits {
6506 u8 reserved_0[0x10];
6508 u8 reserved_1[0x10];
6511 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6514 struct mlx5_ifc_set_diagnostic_params_out_bits {
6516 u8 reserved_0[0x18];
6520 u8 reserved_1[0x40];
6523 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6525 u8 reserved_0[0x10];
6527 u8 reserved_1[0x10];
6530 u8 num_of_samples[0x10];
6531 u8 sample_index[0x10];
6533 u8 reserved_2[0x20];
6536 struct mlx5_ifc_diagnostic_counter_bits {
6537 u8 counter_id[0x10];
6540 u8 time_stamp_31_0[0x20];
6542 u8 counter_value_h[0x20];
6544 u8 counter_value_l[0x20];
6547 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6549 u8 reserved_0[0x18];
6553 u8 reserved_1[0x40];
6555 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6558 struct mlx5_ifc_dealloc_q_counter_in_bits {
6560 u8 reserved_0[0x10];
6562 u8 reserved_1[0x10];
6565 u8 reserved_2[0x18];
6566 u8 counter_set_id[0x8];
6568 u8 reserved_3[0x20];
6571 struct mlx5_ifc_dealloc_pd_out_bits {
6573 u8 reserved_0[0x18];
6577 u8 reserved_1[0x40];
6580 struct mlx5_ifc_dealloc_pd_in_bits {
6582 u8 reserved_0[0x10];
6584 u8 reserved_1[0x10];
6590 u8 reserved_3[0x20];
6593 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6595 u8 reserved_0[0x18];
6599 u8 reserved_1[0x40];
6602 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6604 u8 reserved_0[0x10];
6606 u8 reserved_1[0x10];
6609 u8 reserved_2[0x10];
6610 u8 flow_counter_id[0x10];
6612 u8 reserved_3[0x20];
6615 struct mlx5_ifc_deactivate_tracer_out_bits {
6617 u8 reserved_0[0x18];
6621 u8 reserved_1[0x40];
6624 struct mlx5_ifc_deactivate_tracer_in_bits {
6626 u8 reserved_0[0x10];
6628 u8 reserved_1[0x10];
6633 u8 reserved_2[0x20];
6636 struct mlx5_ifc_create_xrc_srq_out_bits {
6638 u8 reserved_0[0x18];
6645 u8 reserved_2[0x20];
6648 struct mlx5_ifc_create_xrc_srq_in_bits {
6650 u8 reserved_0[0x10];
6652 u8 reserved_1[0x10];
6655 u8 reserved_2[0x40];
6657 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6659 u8 reserved_3[0x600];
6664 struct mlx5_ifc_create_tis_out_bits {
6666 u8 reserved_0[0x18];
6673 u8 reserved_2[0x20];
6676 struct mlx5_ifc_create_tis_in_bits {
6678 u8 reserved_0[0x10];
6680 u8 reserved_1[0x10];
6683 u8 reserved_2[0xc0];
6685 struct mlx5_ifc_tisc_bits ctx;
6688 struct mlx5_ifc_create_tir_out_bits {
6690 u8 reserved_0[0x18];
6697 u8 reserved_2[0x20];
6700 struct mlx5_ifc_create_tir_in_bits {
6702 u8 reserved_0[0x10];
6704 u8 reserved_1[0x10];
6707 u8 reserved_2[0xc0];
6709 struct mlx5_ifc_tirc_bits tir_context;
6712 struct mlx5_ifc_create_srq_out_bits {
6714 u8 reserved_0[0x18];
6721 u8 reserved_2[0x20];
6724 struct mlx5_ifc_create_srq_in_bits {
6726 u8 reserved_0[0x10];
6728 u8 reserved_1[0x10];
6731 u8 reserved_2[0x40];
6733 struct mlx5_ifc_srqc_bits srq_context_entry;
6735 u8 reserved_3[0x600];
6740 struct mlx5_ifc_create_sq_out_bits {
6742 u8 reserved_0[0x18];
6749 u8 reserved_2[0x20];
6752 struct mlx5_ifc_create_sq_in_bits {
6754 u8 reserved_0[0x10];
6756 u8 reserved_1[0x10];
6759 u8 reserved_2[0xc0];
6761 struct mlx5_ifc_sqc_bits ctx;
6764 struct mlx5_ifc_create_scheduling_element_out_bits {
6766 u8 reserved_at_8[0x18];
6770 u8 reserved_at_40[0x40];
6772 u8 scheduling_element_id[0x20];
6774 u8 reserved_at_a0[0x160];
6778 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6781 struct mlx5_ifc_create_scheduling_element_in_bits {
6783 u8 reserved_at_10[0x10];
6785 u8 reserved_at_20[0x10];
6788 u8 scheduling_hierarchy[0x8];
6789 u8 reserved_at_48[0x18];
6791 u8 reserved_at_60[0xa0];
6793 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6795 u8 reserved_at_300[0x100];
6798 struct mlx5_ifc_create_rqt_out_bits {
6800 u8 reserved_0[0x18];
6807 u8 reserved_2[0x20];
6810 struct mlx5_ifc_create_rqt_in_bits {
6812 u8 reserved_0[0x10];
6814 u8 reserved_1[0x10];
6817 u8 reserved_2[0xc0];
6819 struct mlx5_ifc_rqtc_bits rqt_context;
6822 struct mlx5_ifc_create_rq_out_bits {
6824 u8 reserved_0[0x18];
6831 u8 reserved_2[0x20];
6834 struct mlx5_ifc_create_rq_in_bits {
6836 u8 reserved_0[0x10];
6838 u8 reserved_1[0x10];
6841 u8 reserved_2[0xc0];
6843 struct mlx5_ifc_rqc_bits ctx;
6846 struct mlx5_ifc_create_rmp_out_bits {
6848 u8 reserved_0[0x18];
6855 u8 reserved_2[0x20];
6858 struct mlx5_ifc_create_rmp_in_bits {
6860 u8 reserved_0[0x10];
6862 u8 reserved_1[0x10];
6865 u8 reserved_2[0xc0];
6867 struct mlx5_ifc_rmpc_bits ctx;
6870 struct mlx5_ifc_create_qp_out_bits {
6872 u8 reserved_0[0x18];
6879 u8 reserved_2[0x20];
6882 struct mlx5_ifc_create_qp_in_bits {
6884 u8 reserved_0[0x10];
6886 u8 reserved_1[0x10];
6892 u8 reserved_3[0x20];
6894 u8 opt_param_mask[0x20];
6896 u8 reserved_4[0x20];
6898 struct mlx5_ifc_qpc_bits qpc;
6900 u8 reserved_5[0x80];
6905 struct mlx5_ifc_create_qos_para_vport_out_bits {
6907 u8 reserved_at_8[0x18];
6911 u8 reserved_at_40[0x20];
6913 u8 reserved_at_60[0x10];
6914 u8 qos_para_vport_number[0x10];
6916 u8 reserved_at_80[0x180];
6919 struct mlx5_ifc_create_qos_para_vport_in_bits {
6921 u8 reserved_at_10[0x10];
6923 u8 reserved_at_20[0x10];
6926 u8 reserved_at_40[0x1c0];
6929 struct mlx5_ifc_create_psv_out_bits {
6931 u8 reserved_0[0x18];
6935 u8 reserved_1[0x40];
6938 u8 psv0_index[0x18];
6941 u8 psv1_index[0x18];
6944 u8 psv2_index[0x18];
6947 u8 psv3_index[0x18];
6950 struct mlx5_ifc_create_psv_in_bits {
6952 u8 reserved_0[0x10];
6954 u8 reserved_1[0x10];
6961 u8 reserved_3[0x20];
6964 struct mlx5_ifc_create_mkey_out_bits {
6966 u8 reserved_0[0x18];
6971 u8 mkey_index[0x18];
6973 u8 reserved_2[0x20];
6976 struct mlx5_ifc_create_mkey_in_bits {
6978 u8 reserved_0[0x10];
6980 u8 reserved_1[0x10];
6983 u8 reserved_2[0x20];
6986 u8 reserved_3[0x1f];
6988 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6990 u8 reserved_4[0x80];
6992 u8 translations_octword_actual_size[0x20];
6994 u8 reserved_5[0x560];
6996 u8 klm_pas_mtt[0][0x20];
6999 struct mlx5_ifc_create_flow_table_out_bits {
7001 u8 reserved_0[0x18];
7008 u8 reserved_2[0x20];
7011 struct mlx5_ifc_create_flow_table_in_bits {
7013 u8 reserved_at_10[0x10];
7015 u8 reserved_at_20[0x10];
7018 u8 other_vport[0x1];
7019 u8 reserved_at_41[0xf];
7020 u8 vport_number[0x10];
7022 u8 reserved_at_60[0x20];
7025 u8 reserved_at_88[0x18];
7027 u8 reserved_at_a0[0x20];
7029 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7032 struct mlx5_ifc_create_flow_group_out_bits {
7034 u8 reserved_0[0x18];
7041 u8 reserved_2[0x20];
7045 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7046 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7047 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7050 struct mlx5_ifc_create_flow_group_in_bits {
7052 u8 reserved_0[0x10];
7054 u8 reserved_1[0x10];
7057 u8 other_vport[0x1];
7059 u8 vport_number[0x10];
7061 u8 reserved_3[0x20];
7064 u8 reserved_4[0x18];
7069 u8 reserved_6[0x20];
7071 u8 start_flow_index[0x20];
7073 u8 reserved_7[0x20];
7075 u8 end_flow_index[0x20];
7077 u8 reserved_8[0xa0];
7079 u8 reserved_9[0x18];
7080 u8 match_criteria_enable[0x8];
7082 struct mlx5_ifc_fte_match_param_bits match_criteria;
7084 u8 reserved_10[0xe00];
7087 struct mlx5_ifc_create_eq_out_bits {
7089 u8 reserved_0[0x18];
7093 u8 reserved_1[0x18];
7096 u8 reserved_2[0x20];
7099 struct mlx5_ifc_create_eq_in_bits {
7101 u8 reserved_0[0x10];
7103 u8 reserved_1[0x10];
7106 u8 reserved_2[0x40];
7108 struct mlx5_ifc_eqc_bits eq_context_entry;
7110 u8 reserved_3[0x40];
7112 u8 event_bitmask[0x40];
7114 u8 reserved_4[0x580];
7119 struct mlx5_ifc_create_dct_out_bits {
7121 u8 reserved_0[0x18];
7128 u8 reserved_2[0x20];
7131 struct mlx5_ifc_create_dct_in_bits {
7133 u8 reserved_0[0x10];
7135 u8 reserved_1[0x10];
7138 u8 reserved_2[0x40];
7140 struct mlx5_ifc_dctc_bits dct_context_entry;
7142 u8 reserved_3[0x180];
7145 struct mlx5_ifc_create_cq_out_bits {
7147 u8 reserved_0[0x18];
7154 u8 reserved_2[0x20];
7157 struct mlx5_ifc_create_cq_in_bits {
7159 u8 reserved_0[0x10];
7161 u8 reserved_1[0x10];
7164 u8 reserved_2[0x40];
7166 struct mlx5_ifc_cqc_bits cq_context;
7168 u8 reserved_3[0x600];
7173 struct mlx5_ifc_config_int_moderation_out_bits {
7175 u8 reserved_0[0x18];
7181 u8 int_vector[0x10];
7183 u8 reserved_2[0x20];
7187 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7188 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7191 struct mlx5_ifc_config_int_moderation_in_bits {
7193 u8 reserved_0[0x10];
7195 u8 reserved_1[0x10];
7200 u8 int_vector[0x10];
7202 u8 reserved_3[0x20];
7205 struct mlx5_ifc_attach_to_mcg_out_bits {
7207 u8 reserved_0[0x18];
7211 u8 reserved_1[0x40];
7214 struct mlx5_ifc_attach_to_mcg_in_bits {
7216 u8 reserved_0[0x10];
7218 u8 reserved_1[0x10];
7224 u8 reserved_3[0x20];
7226 u8 multicast_gid[16][0x8];
7229 struct mlx5_ifc_arm_xrc_srq_out_bits {
7231 u8 reserved_0[0x18];
7235 u8 reserved_1[0x40];
7239 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7242 struct mlx5_ifc_arm_xrc_srq_in_bits {
7244 u8 reserved_0[0x10];
7246 u8 reserved_1[0x10];
7252 u8 reserved_3[0x10];
7256 struct mlx5_ifc_arm_rq_out_bits {
7258 u8 reserved_0[0x18];
7262 u8 reserved_1[0x40];
7266 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7269 struct mlx5_ifc_arm_rq_in_bits {
7271 u8 reserved_0[0x10];
7273 u8 reserved_1[0x10];
7277 u8 srq_number[0x18];
7279 u8 reserved_3[0x10];
7283 struct mlx5_ifc_arm_dct_out_bits {
7285 u8 reserved_0[0x18];
7289 u8 reserved_1[0x40];
7292 struct mlx5_ifc_arm_dct_in_bits {
7294 u8 reserved_0[0x10];
7296 u8 reserved_1[0x10];
7302 u8 reserved_3[0x20];
7305 struct mlx5_ifc_alloc_xrcd_out_bits {
7307 u8 reserved_0[0x18];
7314 u8 reserved_2[0x20];
7317 struct mlx5_ifc_alloc_xrcd_in_bits {
7319 u8 reserved_0[0x10];
7321 u8 reserved_1[0x10];
7324 u8 reserved_2[0x40];
7327 struct mlx5_ifc_alloc_uar_out_bits {
7329 u8 reserved_0[0x18];
7336 u8 reserved_2[0x20];
7339 struct mlx5_ifc_alloc_uar_in_bits {
7341 u8 reserved_0[0x10];
7343 u8 reserved_1[0x10];
7346 u8 reserved_2[0x40];
7349 struct mlx5_ifc_alloc_transport_domain_out_bits {
7351 u8 reserved_0[0x18];
7356 u8 transport_domain[0x18];
7358 u8 reserved_2[0x20];
7361 struct mlx5_ifc_alloc_transport_domain_in_bits {
7363 u8 reserved_0[0x10];
7365 u8 reserved_1[0x10];
7368 u8 reserved_2[0x40];
7371 struct mlx5_ifc_alloc_q_counter_out_bits {
7373 u8 reserved_0[0x18];
7377 u8 reserved_1[0x18];
7378 u8 counter_set_id[0x8];
7380 u8 reserved_2[0x20];
7383 struct mlx5_ifc_alloc_q_counter_in_bits {
7385 u8 reserved_0[0x10];
7387 u8 reserved_1[0x10];
7390 u8 reserved_2[0x40];
7393 struct mlx5_ifc_alloc_pd_out_bits {
7395 u8 reserved_0[0x18];
7402 u8 reserved_2[0x20];
7405 struct mlx5_ifc_alloc_pd_in_bits {
7407 u8 reserved_0[0x10];
7409 u8 reserved_1[0x10];
7412 u8 reserved_2[0x40];
7415 struct mlx5_ifc_alloc_flow_counter_out_bits {
7417 u8 reserved_0[0x18];
7421 u8 reserved_1[0x10];
7422 u8 flow_counter_id[0x10];
7424 u8 reserved_2[0x20];
7427 struct mlx5_ifc_alloc_flow_counter_in_bits {
7429 u8 reserved_0[0x10];
7431 u8 reserved_1[0x10];
7434 u8 reserved_2[0x40];
7437 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7439 u8 reserved_0[0x18];
7443 u8 reserved_1[0x40];
7446 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7448 u8 reserved_0[0x10];
7450 u8 reserved_1[0x10];
7453 u8 reserved_2[0x20];
7455 u8 reserved_3[0x10];
7456 u8 vxlan_udp_port[0x10];
7459 struct mlx5_ifc_activate_tracer_out_bits {
7461 u8 reserved_0[0x18];
7465 u8 reserved_1[0x40];
7468 struct mlx5_ifc_activate_tracer_in_bits {
7470 u8 reserved_0[0x10];
7472 u8 reserved_1[0x10];
7477 u8 reserved_2[0x20];
7480 struct mlx5_ifc_set_rate_limit_out_bits {
7482 u8 reserved_at_8[0x18];
7486 u8 reserved_at_40[0x40];
7489 struct mlx5_ifc_set_rate_limit_in_bits {
7491 u8 reserved_at_10[0x10];
7493 u8 reserved_at_20[0x10];
7496 u8 reserved_at_40[0x10];
7497 u8 rate_limit_index[0x10];
7499 u8 reserved_at_60[0x20];
7501 u8 rate_limit[0x20];
7502 u8 burst_upper_bound[0x20];
7505 struct mlx5_ifc_access_register_out_bits {
7507 u8 reserved_0[0x18];
7511 u8 reserved_1[0x40];
7513 u8 register_data[0][0x20];
7517 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7518 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7521 struct mlx5_ifc_access_register_in_bits {
7523 u8 reserved_0[0x10];
7525 u8 reserved_1[0x10];
7528 u8 reserved_2[0x10];
7529 u8 register_id[0x10];
7533 u8 register_data[0][0x20];
7536 struct mlx5_ifc_sltp_reg_bits {
7545 u8 reserved_2[0x20];
7554 u8 ob_preemp_mode[0x4];
7558 u8 reserved_5[0x20];
7561 struct mlx5_ifc_slrp_reg_bits {
7571 u8 reserved_2[0x11];
7587 u8 mixerbias_tap_amp[0x8];
7591 u8 ffe_tap_offset0[0x8];
7592 u8 ffe_tap_offset1[0x8];
7593 u8 slicer_offset0[0x10];
7595 u8 mixer_offset0[0x10];
7596 u8 mixer_offset1[0x10];
7598 u8 mixerbgn_inp[0x8];
7599 u8 mixerbgn_inn[0x8];
7600 u8 mixerbgn_refp[0x8];
7601 u8 mixerbgn_refn[0x8];
7603 u8 sel_slicer_lctrl_h[0x1];
7604 u8 sel_slicer_lctrl_l[0x1];
7606 u8 ref_mixer_vreg[0x5];
7607 u8 slicer_gctrl[0x8];
7608 u8 lctrl_input[0x8];
7609 u8 mixer_offset_cm1[0x8];
7611 u8 common_mode[0x6];
7613 u8 mixer_offset_cm0[0x9];
7615 u8 slicer_offset_cm[0x9];
7618 struct mlx5_ifc_slrg_reg_bits {
7627 u8 time_to_link_up[0x10];
7629 u8 grade_lane_speed[0x4];
7631 u8 grade_version[0x8];
7635 u8 height_grade_type[0x4];
7636 u8 height_grade[0x18];
7641 u8 reserved_4[0x10];
7642 u8 height_sigma[0x10];
7644 u8 reserved_5[0x20];
7647 u8 phase_grade_type[0x4];
7648 u8 phase_grade[0x18];
7651 u8 phase_eo_pos[0x8];
7653 u8 phase_eo_neg[0x8];
7655 u8 ffe_set_tested[0x10];
7656 u8 test_errors_per_lane[0x10];
7659 struct mlx5_ifc_pvlc_reg_bits {
7662 u8 reserved_1[0x10];
7664 u8 reserved_2[0x1c];
7667 u8 reserved_3[0x1c];
7670 u8 reserved_4[0x1c];
7671 u8 vl_operational[0x4];
7674 struct mlx5_ifc_pude_reg_bits {
7678 u8 admin_status[0x4];
7680 u8 oper_status[0x4];
7682 u8 reserved_2[0x60];
7686 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1,
7687 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4,
7690 struct mlx5_ifc_ptys_reg_bits {
7692 u8 an_disable_admin[0x1];
7693 u8 an_disable_cap[0x1];
7695 u8 force_tx_aba_param[0x1];
7702 u8 data_rate_oper[0x10];
7704 u8 fc_proto_capability[0x20];
7706 u8 eth_proto_capability[0x20];
7708 u8 ib_link_width_capability[0x10];
7709 u8 ib_proto_capability[0x10];
7711 u8 fc_proto_admin[0x20];
7713 u8 eth_proto_admin[0x20];
7715 u8 ib_link_width_admin[0x10];
7716 u8 ib_proto_admin[0x10];
7718 u8 fc_proto_oper[0x20];
7720 u8 eth_proto_oper[0x20];
7722 u8 ib_link_width_oper[0x10];
7723 u8 ib_proto_oper[0x10];
7725 u8 reserved_4[0x20];
7727 u8 eth_proto_lp_advertise[0x20];
7729 u8 reserved_5[0x60];
7732 struct mlx5_ifc_ptas_reg_bits {
7733 u8 reserved_0[0x20];
7735 u8 algorithm_options[0x10];
7737 u8 repetitions_mode[0x4];
7738 u8 num_of_repetitions[0x8];
7740 u8 grade_version[0x8];
7741 u8 height_grade_type[0x4];
7742 u8 phase_grade_type[0x4];
7743 u8 height_grade_weight[0x8];
7744 u8 phase_grade_weight[0x8];
7746 u8 gisim_measure_bits[0x10];
7747 u8 adaptive_tap_measure_bits[0x10];
7749 u8 ber_bath_high_error_threshold[0x10];
7750 u8 ber_bath_mid_error_threshold[0x10];
7752 u8 ber_bath_low_error_threshold[0x10];
7753 u8 one_ratio_high_threshold[0x10];
7755 u8 one_ratio_high_mid_threshold[0x10];
7756 u8 one_ratio_low_mid_threshold[0x10];
7758 u8 one_ratio_low_threshold[0x10];
7759 u8 ndeo_error_threshold[0x10];
7761 u8 mixer_offset_step_size[0x10];
7763 u8 mix90_phase_for_voltage_bath[0x8];
7765 u8 mixer_offset_start[0x10];
7766 u8 mixer_offset_end[0x10];
7768 u8 reserved_3[0x15];
7769 u8 ber_test_time[0xb];
7772 struct mlx5_ifc_pspa_reg_bits {
7778 u8 reserved_1[0x20];
7781 struct mlx5_ifc_ppsc_reg_bits {
7784 u8 reserved_1[0x10];
7786 u8 reserved_2[0x60];
7788 u8 reserved_3[0x1c];
7791 u8 reserved_4[0x1c];
7792 u8 wrps_status[0x4];
7795 u8 down_th_vld[0x1];
7797 u8 up_threshold[0x8];
7799 u8 down_threshold[0x8];
7801 u8 reserved_7[0x20];
7803 u8 reserved_8[0x1c];
7806 u8 reserved_9[0x60];
7809 struct mlx5_ifc_pplr_reg_bits {
7812 u8 reserved_1[0x10];
7820 struct mlx5_ifc_pplm_reg_bits {
7823 u8 reserved_1[0x10];
7825 u8 reserved_2[0x20];
7827 u8 port_profile_mode[0x8];
7828 u8 static_port_profile[0x8];
7829 u8 active_port_profile[0x8];
7832 u8 retransmission_active[0x8];
7833 u8 fec_mode_active[0x18];
7835 u8 reserved_4[0x10];
7836 u8 v_100g_fec_override_cap[0x4];
7837 u8 v_50g_fec_override_cap[0x4];
7838 u8 v_25g_fec_override_cap[0x4];
7839 u8 v_10g_40g_fec_override_cap[0x4];
7841 u8 reserved_5[0x10];
7842 u8 v_100g_fec_override_admin[0x4];
7843 u8 v_50g_fec_override_admin[0x4];
7844 u8 v_25g_fec_override_admin[0x4];
7845 u8 v_10g_40g_fec_override_admin[0x4];
7848 struct mlx5_ifc_ppll_reg_bits {
7849 u8 num_pll_groups[0x8];
7855 u8 reserved_2[0x1f];
7858 u8 pll_status[4][0x40];
7861 struct mlx5_ifc_ppad_reg_bits {
7870 u8 reserved_2[0x40];
7873 struct mlx5_ifc_pmtu_reg_bits {
7876 u8 reserved_1[0x10];
7879 u8 reserved_2[0x10];
7882 u8 reserved_3[0x10];
7885 u8 reserved_4[0x10];
7888 struct mlx5_ifc_pmpr_reg_bits {
7891 u8 reserved_1[0x10];
7893 u8 reserved_2[0x18];
7894 u8 attenuation_5g[0x8];
7896 u8 reserved_3[0x18];
7897 u8 attenuation_7g[0x8];
7899 u8 reserved_4[0x18];
7900 u8 attenuation_12g[0x8];
7903 struct mlx5_ifc_pmpe_reg_bits {
7907 u8 module_status[0x4];
7909 u8 reserved_2[0x14];
7913 u8 reserved_4[0x40];
7916 struct mlx5_ifc_pmpc_reg_bits {
7917 u8 module_state_updated[32][0x8];
7920 struct mlx5_ifc_pmlpn_reg_bits {
7922 u8 mlpn_status[0x4];
7924 u8 reserved_1[0x10];
7927 u8 reserved_2[0x1f];
7930 struct mlx5_ifc_pmlp_reg_bits {
7937 u8 lane0_module_mapping[0x20];
7939 u8 lane1_module_mapping[0x20];
7941 u8 lane2_module_mapping[0x20];
7943 u8 lane3_module_mapping[0x20];
7945 u8 reserved_2[0x160];
7948 struct mlx5_ifc_pmaos_reg_bits {
7952 u8 admin_status[0x4];
7954 u8 oper_status[0x4];
7958 u8 reserved_3[0x12];
7963 u8 reserved_5[0x40];
7966 struct mlx5_ifc_plpc_reg_bits {
7973 u8 reserved_3[0x10];
7974 u8 lane_speed[0x10];
7976 u8 reserved_4[0x17];
7978 u8 fec_mode_policy[0x8];
7980 u8 retransmission_capability[0x8];
7981 u8 fec_mode_capability[0x18];
7983 u8 retransmission_support_admin[0x8];
7984 u8 fec_mode_support_admin[0x18];
7986 u8 retransmission_request_admin[0x8];
7987 u8 fec_mode_request_admin[0x18];
7989 u8 reserved_5[0x80];
7992 struct mlx5_ifc_pll_status_data_bits {
7995 u8 lock_status[0x2];
7997 u8 algo_f_ctrl[0xa];
7998 u8 analog_algo_num_var[0x6];
7999 u8 f_ctrl_measure[0xa];
8011 struct mlx5_ifc_plib_reg_bits {
8017 u8 reserved_2[0x60];
8020 struct mlx5_ifc_plbf_reg_bits {
8026 u8 reserved_2[0x20];
8029 struct mlx5_ifc_pipg_reg_bits {
8032 u8 reserved_1[0x10];
8035 u8 reserved_2[0x19];
8040 struct mlx5_ifc_pifr_reg_bits {
8043 u8 reserved_1[0x10];
8045 u8 reserved_2[0xe0];
8047 u8 port_filter[8][0x20];
8049 u8 port_filter_update_en[8][0x20];
8052 struct mlx5_ifc_phys_layer_cntrs_bits {
8053 u8 time_since_last_clear_high[0x20];
8055 u8 time_since_last_clear_low[0x20];
8057 u8 symbol_errors_high[0x20];
8059 u8 symbol_errors_low[0x20];
8061 u8 sync_headers_errors_high[0x20];
8063 u8 sync_headers_errors_low[0x20];
8065 u8 edpl_bip_errors_lane0_high[0x20];
8067 u8 edpl_bip_errors_lane0_low[0x20];
8069 u8 edpl_bip_errors_lane1_high[0x20];
8071 u8 edpl_bip_errors_lane1_low[0x20];
8073 u8 edpl_bip_errors_lane2_high[0x20];
8075 u8 edpl_bip_errors_lane2_low[0x20];
8077 u8 edpl_bip_errors_lane3_high[0x20];
8079 u8 edpl_bip_errors_lane3_low[0x20];
8081 u8 fc_fec_corrected_blocks_lane0_high[0x20];
8083 u8 fc_fec_corrected_blocks_lane0_low[0x20];
8085 u8 fc_fec_corrected_blocks_lane1_high[0x20];
8087 u8 fc_fec_corrected_blocks_lane1_low[0x20];
8089 u8 fc_fec_corrected_blocks_lane2_high[0x20];
8091 u8 fc_fec_corrected_blocks_lane2_low[0x20];
8093 u8 fc_fec_corrected_blocks_lane3_high[0x20];
8095 u8 fc_fec_corrected_blocks_lane3_low[0x20];
8097 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
8099 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
8101 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
8103 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
8105 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
8107 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
8109 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
8111 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
8113 u8 rs_fec_corrected_blocks_high[0x20];
8115 u8 rs_fec_corrected_blocks_low[0x20];
8117 u8 rs_fec_uncorrectable_blocks_high[0x20];
8119 u8 rs_fec_uncorrectable_blocks_low[0x20];
8121 u8 rs_fec_no_errors_blocks_high[0x20];
8123 u8 rs_fec_no_errors_blocks_low[0x20];
8125 u8 rs_fec_single_error_blocks_high[0x20];
8127 u8 rs_fec_single_error_blocks_low[0x20];
8129 u8 rs_fec_corrected_symbols_total_high[0x20];
8131 u8 rs_fec_corrected_symbols_total_low[0x20];
8133 u8 rs_fec_corrected_symbols_lane0_high[0x20];
8135 u8 rs_fec_corrected_symbols_lane0_low[0x20];
8137 u8 rs_fec_corrected_symbols_lane1_high[0x20];
8139 u8 rs_fec_corrected_symbols_lane1_low[0x20];
8141 u8 rs_fec_corrected_symbols_lane2_high[0x20];
8143 u8 rs_fec_corrected_symbols_lane2_low[0x20];
8145 u8 rs_fec_corrected_symbols_lane3_high[0x20];
8147 u8 rs_fec_corrected_symbols_lane3_low[0x20];
8149 u8 link_down_events[0x20];
8151 u8 successful_recovery_events[0x20];
8153 u8 reserved_0[0x180];
8156 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8157 u8 symbol_error_counter[0x10];
8159 u8 link_error_recovery_counter[0x8];
8161 u8 link_downed_counter[0x8];
8163 u8 port_rcv_errors[0x10];
8165 u8 port_rcv_remote_physical_errors[0x10];
8167 u8 port_rcv_switch_relay_errors[0x10];
8169 u8 port_xmit_discards[0x10];
8171 u8 port_xmit_constraint_errors[0x8];
8173 u8 port_rcv_constraint_errors[0x8];
8175 u8 reserved_at_70[0x8];
8177 u8 link_overrun_errors[0x8];
8179 u8 reserved_at_80[0x10];
8181 u8 vl_15_dropped[0x10];
8183 u8 reserved_at_a0[0xa0];
8186 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8187 u8 time_since_last_clear_high[0x20];
8189 u8 time_since_last_clear_low[0x20];
8191 u8 phy_received_bits_high[0x20];
8193 u8 phy_received_bits_low[0x20];
8195 u8 phy_symbol_errors_high[0x20];
8197 u8 phy_symbol_errors_low[0x20];
8199 u8 phy_corrected_bits_high[0x20];
8201 u8 phy_corrected_bits_low[0x20];
8203 u8 phy_corrected_bits_lane0_high[0x20];
8205 u8 phy_corrected_bits_lane0_low[0x20];
8207 u8 phy_corrected_bits_lane1_high[0x20];
8209 u8 phy_corrected_bits_lane1_low[0x20];
8211 u8 phy_corrected_bits_lane2_high[0x20];
8213 u8 phy_corrected_bits_lane2_low[0x20];
8215 u8 phy_corrected_bits_lane3_high[0x20];
8217 u8 phy_corrected_bits_lane3_low[0x20];
8219 u8 reserved_at_200[0x5c0];
8222 struct mlx5_ifc_infiniband_port_cntrs_bits {
8223 u8 symbol_error_counter[0x10];
8224 u8 link_error_recovery_counter[0x8];
8225 u8 link_downed_counter[0x8];
8227 u8 port_rcv_errors[0x10];
8228 u8 port_rcv_remote_physical_errors[0x10];
8230 u8 port_rcv_switch_relay_errors[0x10];
8231 u8 port_xmit_discards[0x10];
8233 u8 port_xmit_constraint_errors[0x8];
8234 u8 port_rcv_constraint_errors[0x8];
8236 u8 local_link_integrity_errors[0x4];
8237 u8 excessive_buffer_overrun_errors[0x4];
8239 u8 reserved_1[0x10];
8240 u8 vl_15_dropped[0x10];
8242 u8 port_xmit_data[0x20];
8244 u8 port_rcv_data[0x20];
8246 u8 port_xmit_pkts[0x20];
8248 u8 port_rcv_pkts[0x20];
8250 u8 port_xmit_wait[0x20];
8252 u8 reserved_2[0x680];
8255 struct mlx5_ifc_phrr_reg_bits {
8259 u8 reserved_1[0x10];
8262 u8 reserved_2[0x10];
8265 u8 reserved_3[0x40];
8267 u8 time_since_last_clear_high[0x20];
8269 u8 time_since_last_clear_low[0x20];
8274 struct mlx5_ifc_phbr_for_prio_reg_bits {
8275 u8 reserved_0[0x18];
8279 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8280 u8 reserved_0[0x18];
8284 struct mlx5_ifc_phbr_binding_reg_bits {
8292 u8 reserved_2[0x10];
8295 u8 reserved_3[0x10];
8298 u8 hist_parameters[0x20];
8300 u8 hist_min_value[0x20];
8302 u8 hist_max_value[0x20];
8304 u8 sample_time[0x20];
8308 MLX5_PFCC_REG_PPAN_DISABLED = 0x0,
8309 MLX5_PFCC_REG_PPAN_ENABLED = 0x1,
8312 struct mlx5_ifc_pfcc_reg_bits {
8313 u8 dcbx_operation_type[0x2];
8314 u8 cap_local_admin[0x1];
8315 u8 cap_remote_admin[0x1];
8325 u8 prio_mask_tx[0x8];
8327 u8 prio_mask_rx[0x8];
8343 u8 device_stall_minor_watermark[0x10];
8344 u8 device_stall_critical_watermark[0x10];
8346 u8 reserved_8[0x60];
8349 struct mlx5_ifc_pelc_reg_bits {
8353 u8 reserved_1[0x10];
8356 u8 op_capability[0x8];
8362 u8 capability[0x40];
8368 u8 reserved_2[0x80];
8371 struct mlx5_ifc_peir_reg_bits {
8374 u8 reserved_1[0x10];
8377 u8 error_count[0x4];
8378 u8 reserved_3[0x10];
8386 struct mlx5_ifc_pcap_reg_bits {
8389 u8 reserved_1[0x10];
8391 u8 port_capability_mask[4][0x20];
8394 struct mlx5_ifc_pbmc_reg_bits {
8397 u8 reserved_1[0x10];
8399 u8 xoff_timer_value[0x10];
8400 u8 xoff_refresh[0x10];
8402 u8 reserved_2[0x10];
8403 u8 port_buffer_size[0x10];
8405 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8407 u8 reserved_3[0x40];
8409 u8 port_shared_buffer[0x40];
8412 struct mlx5_ifc_paos_reg_bits {
8416 u8 admin_status[0x4];
8418 u8 oper_status[0x4];
8422 u8 reserved_2[0x1c];
8425 u8 reserved_3[0x40];
8428 struct mlx5_ifc_pamp_reg_bits {
8430 u8 opamp_group[0x8];
8432 u8 opamp_group_type[0x4];
8434 u8 start_index[0x10];
8436 u8 num_of_indices[0xc];
8438 u8 index_data[18][0x10];
8441 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8442 u8 llr_rx_cells_high[0x20];
8444 u8 llr_rx_cells_low[0x20];
8446 u8 llr_rx_error_high[0x20];
8448 u8 llr_rx_error_low[0x20];
8450 u8 llr_rx_crc_error_high[0x20];
8452 u8 llr_rx_crc_error_low[0x20];
8454 u8 llr_tx_cells_high[0x20];
8456 u8 llr_tx_cells_low[0x20];
8458 u8 llr_tx_ret_cells_high[0x20];
8460 u8 llr_tx_ret_cells_low[0x20];
8462 u8 llr_tx_ret_events_high[0x20];
8464 u8 llr_tx_ret_events_low[0x20];
8466 u8 reserved_0[0x640];
8469 struct mlx5_ifc_lane_2_module_mapping_bits {
8478 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8479 u8 transmit_queue_high[0x20];
8481 u8 transmit_queue_low[0x20];
8483 u8 reserved_0[0x780];
8486 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8487 u8 no_buffer_discard_uc_high[0x20];
8489 u8 no_buffer_discard_uc_low[0x20];
8491 u8 wred_discard_high[0x20];
8493 u8 wred_discard_low[0x20];
8495 u8 reserved_0[0x740];
8498 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8499 u8 rx_octets_high[0x20];
8501 u8 rx_octets_low[0x20];
8503 u8 reserved_0[0xc0];
8505 u8 rx_frames_high[0x20];
8507 u8 rx_frames_low[0x20];
8509 u8 tx_octets_high[0x20];
8511 u8 tx_octets_low[0x20];
8513 u8 reserved_1[0xc0];
8515 u8 tx_frames_high[0x20];
8517 u8 tx_frames_low[0x20];
8519 u8 rx_pause_high[0x20];
8521 u8 rx_pause_low[0x20];
8523 u8 rx_pause_duration_high[0x20];
8525 u8 rx_pause_duration_low[0x20];
8527 u8 tx_pause_high[0x20];
8529 u8 tx_pause_low[0x20];
8531 u8 tx_pause_duration_high[0x20];
8533 u8 tx_pause_duration_low[0x20];
8535 u8 rx_pause_transition_high[0x20];
8537 u8 rx_pause_transition_low[0x20];
8539 u8 rx_discards_high[0x20];
8541 u8 rx_discards_low[0x20];
8543 u8 device_stall_minor_watermark_cnt_high[0x20];
8545 u8 device_stall_minor_watermark_cnt_low[0x20];
8547 u8 device_stall_critical_watermark_cnt_high[0x20];
8549 u8 device_stall_critical_watermark_cnt_low[0x20];
8551 u8 reserved_2[0x340];
8554 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8555 u8 port_transmit_wait_high[0x20];
8557 u8 port_transmit_wait_low[0x20];
8559 u8 ecn_marked_high[0x20];
8561 u8 ecn_marked_low[0x20];
8563 u8 no_buffer_discard_mc_high[0x20];
8565 u8 no_buffer_discard_mc_low[0x20];
8567 u8 reserved_0[0x700];
8570 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8571 u8 a_frames_transmitted_ok_high[0x20];
8573 u8 a_frames_transmitted_ok_low[0x20];
8575 u8 a_frames_received_ok_high[0x20];
8577 u8 a_frames_received_ok_low[0x20];
8579 u8 a_frame_check_sequence_errors_high[0x20];
8581 u8 a_frame_check_sequence_errors_low[0x20];
8583 u8 a_alignment_errors_high[0x20];
8585 u8 a_alignment_errors_low[0x20];
8587 u8 a_octets_transmitted_ok_high[0x20];
8589 u8 a_octets_transmitted_ok_low[0x20];
8591 u8 a_octets_received_ok_high[0x20];
8593 u8 a_octets_received_ok_low[0x20];
8595 u8 a_multicast_frames_xmitted_ok_high[0x20];
8597 u8 a_multicast_frames_xmitted_ok_low[0x20];
8599 u8 a_broadcast_frames_xmitted_ok_high[0x20];
8601 u8 a_broadcast_frames_xmitted_ok_low[0x20];
8603 u8 a_multicast_frames_received_ok_high[0x20];
8605 u8 a_multicast_frames_received_ok_low[0x20];
8607 u8 a_broadcast_frames_recieved_ok_high[0x20];
8609 u8 a_broadcast_frames_recieved_ok_low[0x20];
8611 u8 a_in_range_length_errors_high[0x20];
8613 u8 a_in_range_length_errors_low[0x20];
8615 u8 a_out_of_range_length_field_high[0x20];
8617 u8 a_out_of_range_length_field_low[0x20];
8619 u8 a_frame_too_long_errors_high[0x20];
8621 u8 a_frame_too_long_errors_low[0x20];
8623 u8 a_symbol_error_during_carrier_high[0x20];
8625 u8 a_symbol_error_during_carrier_low[0x20];
8627 u8 a_mac_control_frames_transmitted_high[0x20];
8629 u8 a_mac_control_frames_transmitted_low[0x20];
8631 u8 a_mac_control_frames_received_high[0x20];
8633 u8 a_mac_control_frames_received_low[0x20];
8635 u8 a_unsupported_opcodes_received_high[0x20];
8637 u8 a_unsupported_opcodes_received_low[0x20];
8639 u8 a_pause_mac_ctrl_frames_received_high[0x20];
8641 u8 a_pause_mac_ctrl_frames_received_low[0x20];
8643 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
8645 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
8647 u8 reserved_0[0x300];
8650 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8651 u8 dot3stats_alignment_errors_high[0x20];
8653 u8 dot3stats_alignment_errors_low[0x20];
8655 u8 dot3stats_fcs_errors_high[0x20];
8657 u8 dot3stats_fcs_errors_low[0x20];
8659 u8 dot3stats_single_collision_frames_high[0x20];
8661 u8 dot3stats_single_collision_frames_low[0x20];
8663 u8 dot3stats_multiple_collision_frames_high[0x20];
8665 u8 dot3stats_multiple_collision_frames_low[0x20];
8667 u8 dot3stats_sqe_test_errors_high[0x20];
8669 u8 dot3stats_sqe_test_errors_low[0x20];
8671 u8 dot3stats_deferred_transmissions_high[0x20];
8673 u8 dot3stats_deferred_transmissions_low[0x20];
8675 u8 dot3stats_late_collisions_high[0x20];
8677 u8 dot3stats_late_collisions_low[0x20];
8679 u8 dot3stats_excessive_collisions_high[0x20];
8681 u8 dot3stats_excessive_collisions_low[0x20];
8683 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
8685 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
8687 u8 dot3stats_carrier_sense_errors_high[0x20];
8689 u8 dot3stats_carrier_sense_errors_low[0x20];
8691 u8 dot3stats_frame_too_longs_high[0x20];
8693 u8 dot3stats_frame_too_longs_low[0x20];
8695 u8 dot3stats_internal_mac_receive_errors_high[0x20];
8697 u8 dot3stats_internal_mac_receive_errors_low[0x20];
8699 u8 dot3stats_symbol_errors_high[0x20];
8701 u8 dot3stats_symbol_errors_low[0x20];
8703 u8 dot3control_in_unknown_opcodes_high[0x20];
8705 u8 dot3control_in_unknown_opcodes_low[0x20];
8707 u8 dot3in_pause_frames_high[0x20];
8709 u8 dot3in_pause_frames_low[0x20];
8711 u8 dot3out_pause_frames_high[0x20];
8713 u8 dot3out_pause_frames_low[0x20];
8715 u8 reserved_0[0x3c0];
8718 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8719 u8 if_in_octets_high[0x20];
8721 u8 if_in_octets_low[0x20];
8723 u8 if_in_ucast_pkts_high[0x20];
8725 u8 if_in_ucast_pkts_low[0x20];
8727 u8 if_in_discards_high[0x20];
8729 u8 if_in_discards_low[0x20];
8731 u8 if_in_errors_high[0x20];
8733 u8 if_in_errors_low[0x20];
8735 u8 if_in_unknown_protos_high[0x20];
8737 u8 if_in_unknown_protos_low[0x20];
8739 u8 if_out_octets_high[0x20];
8741 u8 if_out_octets_low[0x20];
8743 u8 if_out_ucast_pkts_high[0x20];
8745 u8 if_out_ucast_pkts_low[0x20];
8747 u8 if_out_discards_high[0x20];
8749 u8 if_out_discards_low[0x20];
8751 u8 if_out_errors_high[0x20];
8753 u8 if_out_errors_low[0x20];
8755 u8 if_in_multicast_pkts_high[0x20];
8757 u8 if_in_multicast_pkts_low[0x20];
8759 u8 if_in_broadcast_pkts_high[0x20];
8761 u8 if_in_broadcast_pkts_low[0x20];
8763 u8 if_out_multicast_pkts_high[0x20];
8765 u8 if_out_multicast_pkts_low[0x20];
8767 u8 if_out_broadcast_pkts_high[0x20];
8769 u8 if_out_broadcast_pkts_low[0x20];
8771 u8 reserved_0[0x480];
8774 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8775 u8 ether_stats_drop_events_high[0x20];
8777 u8 ether_stats_drop_events_low[0x20];
8779 u8 ether_stats_octets_high[0x20];
8781 u8 ether_stats_octets_low[0x20];
8783 u8 ether_stats_pkts_high[0x20];
8785 u8 ether_stats_pkts_low[0x20];
8787 u8 ether_stats_broadcast_pkts_high[0x20];
8789 u8 ether_stats_broadcast_pkts_low[0x20];
8791 u8 ether_stats_multicast_pkts_high[0x20];
8793 u8 ether_stats_multicast_pkts_low[0x20];
8795 u8 ether_stats_crc_align_errors_high[0x20];
8797 u8 ether_stats_crc_align_errors_low[0x20];
8799 u8 ether_stats_undersize_pkts_high[0x20];
8801 u8 ether_stats_undersize_pkts_low[0x20];
8803 u8 ether_stats_oversize_pkts_high[0x20];
8805 u8 ether_stats_oversize_pkts_low[0x20];
8807 u8 ether_stats_fragments_high[0x20];
8809 u8 ether_stats_fragments_low[0x20];
8811 u8 ether_stats_jabbers_high[0x20];
8813 u8 ether_stats_jabbers_low[0x20];
8815 u8 ether_stats_collisions_high[0x20];
8817 u8 ether_stats_collisions_low[0x20];
8819 u8 ether_stats_pkts64octets_high[0x20];
8821 u8 ether_stats_pkts64octets_low[0x20];
8823 u8 ether_stats_pkts65to127octets_high[0x20];
8825 u8 ether_stats_pkts65to127octets_low[0x20];
8827 u8 ether_stats_pkts128to255octets_high[0x20];
8829 u8 ether_stats_pkts128to255octets_low[0x20];
8831 u8 ether_stats_pkts256to511octets_high[0x20];
8833 u8 ether_stats_pkts256to511octets_low[0x20];
8835 u8 ether_stats_pkts512to1023octets_high[0x20];
8837 u8 ether_stats_pkts512to1023octets_low[0x20];
8839 u8 ether_stats_pkts1024to1518octets_high[0x20];
8841 u8 ether_stats_pkts1024to1518octets_low[0x20];
8843 u8 ether_stats_pkts1519to2047octets_high[0x20];
8845 u8 ether_stats_pkts1519to2047octets_low[0x20];
8847 u8 ether_stats_pkts2048to4095octets_high[0x20];
8849 u8 ether_stats_pkts2048to4095octets_low[0x20];
8851 u8 ether_stats_pkts4096to8191octets_high[0x20];
8853 u8 ether_stats_pkts4096to8191octets_low[0x20];
8855 u8 ether_stats_pkts8192to10239octets_high[0x20];
8857 u8 ether_stats_pkts8192to10239octets_low[0x20];
8859 u8 reserved_0[0x280];
8862 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8863 u8 symbol_error_counter[0x10];
8864 u8 link_error_recovery_counter[0x8];
8865 u8 link_downed_counter[0x8];
8867 u8 port_rcv_errors[0x10];
8868 u8 port_rcv_remote_physical_errors[0x10];
8870 u8 port_rcv_switch_relay_errors[0x10];
8871 u8 port_xmit_discards[0x10];
8873 u8 port_xmit_constraint_errors[0x8];
8874 u8 port_rcv_constraint_errors[0x8];
8876 u8 local_link_integrity_errors[0x4];
8877 u8 excessive_buffer_overrun_errors[0x4];
8879 u8 reserved_1[0x10];
8880 u8 vl_15_dropped[0x10];
8882 u8 port_xmit_data[0x20];
8884 u8 port_rcv_data[0x20];
8886 u8 port_xmit_pkts[0x20];
8888 u8 port_rcv_pkts[0x20];
8890 u8 port_xmit_wait[0x20];
8892 u8 reserved_2[0x680];
8895 struct mlx5_ifc_trc_tlb_reg_bits {
8896 u8 reserved_0[0x80];
8898 u8 tlb_addr[0][0x40];
8901 struct mlx5_ifc_trc_read_fifo_reg_bits {
8902 u8 reserved_0[0x10];
8903 u8 requested_event_num[0x10];
8905 u8 reserved_1[0x20];
8907 u8 reserved_2[0x10];
8908 u8 acual_event_num[0x10];
8910 u8 reserved_3[0x20];
8915 struct mlx5_ifc_trc_lock_reg_bits {
8916 u8 reserved_0[0x1f];
8919 u8 reserved_1[0x60];
8922 struct mlx5_ifc_trc_filter_reg_bits {
8925 u8 filter_index[0x10];
8927 u8 reserved_1[0x20];
8929 u8 filter_val[0x20];
8931 u8 reserved_2[0x1a0];
8934 struct mlx5_ifc_trc_event_reg_bits {
8937 u8 event_index[0x10];
8939 u8 reserved_1[0x20];
8943 u8 event_selector_val[0x10];
8944 u8 event_selector_size[0x10];
8946 u8 reserved_2[0x180];
8949 struct mlx5_ifc_trc_conf_reg_bits {
8953 u8 reserved_1[0x15];
8956 u8 reserved_2[0x20];
8958 u8 limit_event_index[0x20];
8962 u8 fifo_ready_ev_num[0x20];
8964 u8 reserved_3[0x160];
8967 struct mlx5_ifc_trc_cap_reg_bits {
8968 u8 reserved_0[0x18];
8971 u8 reserved_1[0x20];
8973 u8 num_of_events[0x10];
8974 u8 num_of_filters[0x10];
8979 u8 event_size[0x10];
8981 u8 reserved_2[0x160];
8984 struct mlx5_ifc_set_node_in_bits {
8985 u8 node_description[64][0x8];
8988 struct mlx5_ifc_register_power_settings_bits {
8989 u8 reserved_0[0x18];
8990 u8 power_settings_level[0x8];
8992 u8 reserved_1[0x60];
8995 struct mlx5_ifc_register_host_endianess_bits {
8997 u8 reserved_0[0x1f];
8999 u8 reserved_1[0x60];
9002 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9003 u8 physical_address[0x40];
9006 struct mlx5_ifc_qtct_reg_bits {
9007 u8 operation_type[0x2];
9008 u8 cap_local_admin[0x1];
9009 u8 cap_remote_admin[0x1];
9011 u8 port_number[0x8];
9015 u8 reserved_2[0x1d];
9019 struct mlx5_ifc_qpdp_reg_bits {
9021 u8 port_number[0x8];
9022 u8 reserved_1[0x10];
9024 u8 reserved_2[0x1d];
9028 struct mlx5_ifc_port_info_ro_fields_param_bits {
9033 u8 reserved_1[0x20];
9038 struct mlx5_ifc_nvqc_reg_bits {
9041 u8 reserved_0[0x18];
9048 struct mlx5_ifc_nvia_reg_bits {
9049 u8 reserved_0[0x1d];
9052 u8 reserved_1[0x20];
9055 struct mlx5_ifc_nvdi_reg_bits {
9056 struct mlx5_ifc_config_item_bits configuration_item_header;
9059 struct mlx5_ifc_nvda_reg_bits {
9060 struct mlx5_ifc_config_item_bits configuration_item_header;
9062 u8 configuration_item_data[0x20];
9065 struct mlx5_ifc_node_info_ro_fields_param_bits {
9066 u8 system_image_guid[0x40];
9068 u8 reserved_0[0x40];
9072 u8 reserved_1[0x10];
9075 u8 reserved_2[0x20];
9078 struct mlx5_ifc_ets_tcn_config_reg_bits {
9085 u8 bw_allocation[0x7];
9088 u8 max_bw_units[0x4];
9090 u8 max_bw_value[0x8];
9093 struct mlx5_ifc_ets_global_config_reg_bits {
9096 u8 reserved_1[0x1d];
9099 u8 max_bw_units[0x4];
9101 u8 max_bw_value[0x8];
9104 struct mlx5_ifc_qetc_reg_bits {
9105 u8 reserved_at_0[0x8];
9106 u8 port_number[0x8];
9107 u8 reserved_at_10[0x30];
9109 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9110 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9113 struct mlx5_ifc_nodnic_mac_filters_bits {
9114 struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9116 struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9118 struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9120 struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9122 struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9124 u8 reserved_0[0xc0];
9127 struct mlx5_ifc_nodnic_gid_filters_bits {
9128 u8 mgid_filter0[16][0x8];
9130 u8 mgid_filter1[16][0x8];
9132 u8 mgid_filter2[16][0x8];
9134 u8 mgid_filter3[16][0x8];
9138 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0,
9139 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1,
9143 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0,
9144 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1,
9147 struct mlx5_ifc_nodnic_config_reg_bits {
9148 u8 no_dram_nic_revision[0x8];
9149 u8 hardware_format[0x8];
9150 u8 support_receive_filter[0x1];
9151 u8 support_promisc_filter[0x1];
9152 u8 support_promisc_multicast_filter[0x1];
9154 u8 log_working_buffer_size[0x3];
9155 u8 log_pkey_table_size[0x4];
9160 u8 log_max_ring_size[0x6];
9161 u8 reserved_3[0x18];
9166 u8 reserved_4[0x1c];
9170 u8 reserved_5[0x740];
9172 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9174 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9177 struct mlx5_ifc_vlan_layout_bits {
9178 u8 reserved_0[0x14];
9181 u8 reserved_1[0x20];
9184 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9185 u8 reserved_0[0x20];
9189 u8 addressh_63_32[0x20];
9191 u8 addressl_31_0[0x20];
9194 struct mlx5_ifc_ud_adrs_vector_bits {
9199 u8 destination_qp_dct[0x18];
9201 u8 static_rate[0x4];
9202 u8 sl_eth_prio[0x4];
9205 u8 rlid_udp_sport[0x10];
9207 u8 reserved_1[0x20];
9209 u8 rmac_47_16[0x20];
9218 u8 src_addr_index[0x8];
9219 u8 flow_label[0x14];
9221 u8 rgid_rip[16][0x8];
9224 struct mlx5_ifc_port_module_event_bits {
9228 u8 module_status[0x4];
9230 u8 reserved_2[0x14];
9234 u8 reserved_4[0xa0];
9237 struct mlx5_ifc_icmd_control_bits {
9244 struct mlx5_ifc_eqe_bits {
9248 u8 event_sub_type[0x8];
9250 u8 reserved_2[0xe0];
9252 union mlx5_ifc_event_auto_bits event_data;
9254 u8 reserved_3[0x10];
9261 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9264 struct mlx5_ifc_cmd_queue_entry_bits {
9266 u8 reserved_0[0x18];
9268 u8 input_length[0x20];
9270 u8 input_mailbox_pointer_63_32[0x20];
9272 u8 input_mailbox_pointer_31_9[0x17];
9275 u8 command_input_inline_data[16][0x8];
9277 u8 command_output_inline_data[16][0x8];
9279 u8 output_mailbox_pointer_63_32[0x20];
9281 u8 output_mailbox_pointer_31_9[0x17];
9284 u8 output_length[0x20];
9293 struct mlx5_ifc_cmd_out_bits {
9295 u8 reserved_0[0x18];
9299 u8 command_output[0x20];
9302 struct mlx5_ifc_cmd_in_bits {
9304 u8 reserved_0[0x10];
9306 u8 reserved_1[0x10];
9309 u8 command[0][0x20];
9312 struct mlx5_ifc_cmd_if_box_bits {
9313 u8 mailbox_data[512][0x8];
9315 u8 reserved_0[0x180];
9317 u8 next_pointer_63_32[0x20];
9319 u8 next_pointer_31_10[0x16];
9322 u8 block_number[0x20];
9326 u8 ctrl_signature[0x8];
9330 struct mlx5_ifc_mtt_bits {
9331 u8 ptag_63_32[0x20];
9339 /* Vendor Specific Capabilities, VSC */
9341 MLX5_VSC_DOMAIN_ICMD = 0x1,
9342 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6,
9343 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA,
9346 struct mlx5_ifc_vendor_specific_cap_bits {
9349 u8 next_pointer[0x8];
9350 u8 capability_id[0x8];
9368 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9369 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9370 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9374 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9375 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9376 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9380 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
9381 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
9382 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
9383 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
9384 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
9385 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
9386 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
9387 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
9388 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
9389 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
9390 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10,
9393 struct mlx5_ifc_initial_seg_bits {
9394 u8 fw_rev_minor[0x10];
9395 u8 fw_rev_major[0x10];
9397 u8 cmd_interface_rev[0x10];
9398 u8 fw_rev_subminor[0x10];
9400 u8 reserved_0[0x40];
9402 u8 cmdq_phy_addr_63_32[0x20];
9404 u8 cmdq_phy_addr_31_12[0x14];
9406 u8 nic_interface[0x2];
9407 u8 log_cmdq_size[0x4];
9408 u8 log_cmdq_stride[0x4];
9410 u8 command_doorbell_vector[0x20];
9412 u8 reserved_2[0xf00];
9414 u8 initializing[0x1];
9416 u8 nic_interface_supported[0x3];
9417 u8 reserved_4[0x18];
9419 struct mlx5_ifc_health_buffer_bits health_buffer;
9421 u8 no_dram_nic_offset[0x20];
9423 u8 reserved_5[0x6de0];
9425 u8 internal_timer_h[0x20];
9427 u8 internal_timer_l[0x20];
9429 u8 reserved_6[0x20];
9431 u8 reserved_7[0x1f];
9434 u8 health_syndrome[0x8];
9435 u8 health_counter[0x18];
9437 u8 reserved_8[0x17fc0];
9440 union mlx5_ifc_icmd_interface_document_bits {
9441 struct mlx5_ifc_fw_version_bits fw_version;
9442 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9443 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9444 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9445 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9446 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9447 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9448 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9449 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9450 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9451 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9452 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9453 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9454 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9455 u8 reserved_0[0x42c0];
9458 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9459 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9460 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9461 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9462 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9463 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9464 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9465 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9466 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9467 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9468 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9469 u8 reserved_0[0x7c0];
9472 struct mlx5_ifc_ppcnt_reg_bits {
9480 u8 reserved_1[0x1c];
9483 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9486 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9487 u8 life_time_counter_high[0x20];
9489 u8 life_time_counter_low[0x20];
9495 u8 l0_to_recovery_eieos[0x20];
9497 u8 l0_to_recovery_ts[0x20];
9499 u8 l0_to_recovery_framing[0x20];
9501 u8 l0_to_recovery_retrain[0x20];
9503 u8 crc_error_dllp[0x20];
9505 u8 crc_error_tlp[0x20];
9507 u8 reserved_0[0x680];
9510 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9511 u8 life_time_counter_high[0x20];
9513 u8 life_time_counter_low[0x20];
9515 u8 time_to_boot_image_start[0x20];
9517 u8 time_to_link_image[0x20];
9519 u8 calibration_time[0x20];
9521 u8 time_to_first_perst[0x20];
9523 u8 time_to_detect_state[0x20];
9525 u8 time_to_l0[0x20];
9527 u8 time_to_crs_en[0x20];
9529 u8 time_to_plastic_image_start[0x20];
9531 u8 time_to_iron_image_start[0x20];
9533 u8 perst_handler[0x20];
9535 u8 times_in_l1[0x20];
9537 u8 times_in_l23[0x20];
9541 u8 config_cycle1usec[0x20];
9543 u8 config_cycle2to7usec[0x20];
9545 u8 config_cycle8to15usec[0x20];
9547 u8 config_cycle16to63usec[0x20];
9549 u8 config_cycle64usec[0x20];
9551 u8 correctable_err_msg_sent[0x20];
9553 u8 non_fatal_err_msg_sent[0x20];
9555 u8 fatal_err_msg_sent[0x20];
9557 u8 reserved_0[0x4e0];
9560 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9561 u8 life_time_counter_high[0x20];
9563 u8 life_time_counter_low[0x20];
9565 u8 error_counter_lane0[0x20];
9567 u8 error_counter_lane1[0x20];
9569 u8 error_counter_lane2[0x20];
9571 u8 error_counter_lane3[0x20];
9573 u8 error_counter_lane4[0x20];
9575 u8 error_counter_lane5[0x20];
9577 u8 error_counter_lane6[0x20];
9579 u8 error_counter_lane7[0x20];
9581 u8 error_counter_lane8[0x20];
9583 u8 error_counter_lane9[0x20];
9585 u8 error_counter_lane10[0x20];
9587 u8 error_counter_lane11[0x20];
9589 u8 error_counter_lane12[0x20];
9591 u8 error_counter_lane13[0x20];
9593 u8 error_counter_lane14[0x20];
9595 u8 error_counter_lane15[0x20];
9597 u8 reserved_0[0x580];
9600 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9601 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9602 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9603 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9604 u8 reserved_0[0xf8];
9607 struct mlx5_ifc_mpcnt_reg_bits {
9614 u8 reserved_2[0x1f];
9616 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9619 union mlx5_ifc_ports_control_registers_document_bits {
9620 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9621 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9622 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9623 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9624 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9625 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9626 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9627 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9628 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9629 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9630 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9631 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9632 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9633 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9634 struct mlx5_ifc_paos_reg_bits paos_reg;
9635 struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9636 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9637 struct mlx5_ifc_peir_reg_bits peir_reg;
9638 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9639 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9640 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9641 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9642 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9643 struct mlx5_ifc_phrr_reg_bits phrr_reg;
9644 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9645 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9646 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9647 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9648 struct mlx5_ifc_plib_reg_bits plib_reg;
9649 struct mlx5_ifc_pll_status_data_bits pll_status_data;
9650 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9651 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9652 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9653 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9654 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9655 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9656 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9657 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9658 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9659 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9660 struct mlx5_ifc_ppll_reg_bits ppll_reg;
9661 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9662 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9663 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9664 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9665 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9666 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9667 struct mlx5_ifc_pude_reg_bits pude_reg;
9668 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9669 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9670 struct mlx5_ifc_slrp_reg_bits slrp_reg;
9671 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9672 u8 reserved_0[0x7880];
9675 union mlx5_ifc_debug_enhancements_document_bits {
9676 struct mlx5_ifc_health_buffer_bits health_buffer;
9677 u8 reserved_0[0x200];
9680 union mlx5_ifc_no_dram_nic_document_bits {
9681 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9682 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9683 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9684 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9685 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9686 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9687 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9688 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9689 u8 reserved_0[0x3160];
9692 union mlx5_ifc_uplink_pci_interface_document_bits {
9693 struct mlx5_ifc_initial_seg_bits initial_seg;
9694 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9695 u8 reserved_0[0x20120];
9699 #endif /* MLX5_IFC_H */