sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26
  27    Autogenerated file.
  28    Date: 2015-04-13 14:59
  29    Source Document Name: Mellanox <Doc Name>
  30    Source Document Version: 0.28
  31    Generated by adb_to_c.py (EAT.ME Version: 1.0.70)
  32 */
  33 #ifndef MLX5_IFC_H
  34 #define MLX5_IFC_H
  35
  36 enum {
  37         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  38         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  39         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  40         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  41         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  42         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  43         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  44         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  45         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  46         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  47         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  48         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  49         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  50         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  51         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  52         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  53         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  54         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  55         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  56         MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
  57         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  58         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  59         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  60         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  61         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  62         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  63         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  64         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
  65 };
  66
  67 enum {
  68         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  69         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  70         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  71         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  72         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  73 };
  74
  75 enum {
  76         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  77 };
  78
  79 enum {
  80         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  81         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  82         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  83         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  84         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  85         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  86         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  87         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  88         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  89         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  90         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  91         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  92         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  93         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  94         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  95         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  96         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 132         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 133         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 153         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 154         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 155         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 156         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 157         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 158         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 159         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 160         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 161         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 162         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 163         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 164         MLX5_CMD_OP_NOP                           = 0x80d,
 165         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 166         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 167         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 168         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 169         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 170         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 171         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 172         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 173         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 174         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 188         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 189         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 190         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 191         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 192         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 193         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 194         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 195         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 196         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 197         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 198         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 199         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 200         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 201         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 202         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 203         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 204         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 205         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 206         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 207         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 208         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 209         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 210         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 211         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 212         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 213         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 214         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 215         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 216         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 217         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 219         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 220         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 221         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 222         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 223         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b
 224 };
 225
 226 enum {
 227         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 228         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 229         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 230         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 231         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 232         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 233         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 234         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 235         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 236         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 237         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 238         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 239 };
 240
 241 struct mlx5_ifc_flow_table_fields_supported_bits {
 242         u8         outer_dmac[0x1];
 243         u8         outer_smac[0x1];
 244         u8         outer_ether_type[0x1];
 245         u8         reserved_0[0x1];
 246         u8         outer_first_prio[0x1];
 247         u8         outer_first_cfi[0x1];
 248         u8         outer_first_vid[0x1];
 249         u8         reserved_1[0x1];
 250         u8         outer_second_prio[0x1];
 251         u8         outer_second_cfi[0x1];
 252         u8         outer_second_vid[0x1];
 253         u8         outer_ipv6_flow_label[0x1];
 254         u8         outer_sip[0x1];
 255         u8         outer_dip[0x1];
 256         u8         outer_frag[0x1];
 257         u8         outer_ip_protocol[0x1];
 258         u8         outer_ip_ecn[0x1];
 259         u8         outer_ip_dscp[0x1];
 260         u8         outer_udp_sport[0x1];
 261         u8         outer_udp_dport[0x1];
 262         u8         outer_tcp_sport[0x1];
 263         u8         outer_tcp_dport[0x1];
 264         u8         outer_tcp_flags[0x1];
 265         u8         outer_gre_protocol[0x1];
 266         u8         outer_gre_key[0x1];
 267         u8         outer_vxlan_vni[0x1];
 268         u8         reserved_2[0x5];
 269         u8         source_eswitch_port[0x1];
 270
 271         u8         inner_dmac[0x1];
 272         u8         inner_smac[0x1];
 273         u8         inner_ether_type[0x1];
 274         u8         reserved_3[0x1];
 275         u8         inner_first_prio[0x1];
 276         u8         inner_first_cfi[0x1];
 277         u8         inner_first_vid[0x1];
 278         u8         reserved_4[0x1];
 279         u8         inner_second_prio[0x1];
 280         u8         inner_second_cfi[0x1];
 281         u8         inner_second_vid[0x1];
 282         u8         inner_ipv6_flow_label[0x1];
 283         u8         inner_sip[0x1];
 284         u8         inner_dip[0x1];
 285         u8         inner_frag[0x1];
 286         u8         inner_ip_protocol[0x1];
 287         u8         inner_ip_ecn[0x1];
 288         u8         inner_ip_dscp[0x1];
 289         u8         inner_udp_sport[0x1];
 290         u8         inner_udp_dport[0x1];
 291         u8         inner_tcp_sport[0x1];
 292         u8         inner_tcp_dport[0x1];
 293         u8         inner_tcp_flags[0x1];
 294         u8         reserved_5[0x9];
 295
 296         u8         reserved_6[0x1f];
 297         u8         source_sqn[0x1];
 298
 299         u8         reserved_7[0x20];
 300 };
 301
 302 struct mlx5_ifc_flow_table_prop_layout_bits {
 303         u8         ft_support[0x1];
 304         u8         flow_tag[0x1];
 305         u8         flow_counter[0x1];
 306         u8         flow_modify_en[0x1];
 307         u8         modify_root[0x1];
 308         u8         reserved_0[0x1b];
 309
 310         u8         reserved_1[0x2];
 311         u8         log_max_ft_size[0x6];
 312         u8         reserved_2[0x10];
 313         u8         max_ft_level[0x8];
 314
 315         u8         reserved_3[0x20];
 316
 317         u8         reserved_4[0x18];
 318         u8         log_max_ft_num[0x8];
 319
 320         u8         reserved_5[0x10];
 321         u8         log_max_flow_counter[0x8];
 322         u8         log_max_destination[0x8];
 323
 324         u8         reserved_6[0x18];
 325         u8         log_max_flow[0x8];
 326
 327         u8         reserved_7[0x40];
 328
 329         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 330
 331         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 332 };
 333
 334 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 335         u8         send[0x1];
 336         u8         receive[0x1];
 337         u8         write[0x1];
 338         u8         read[0x1];
 339         u8         atomic[0x1];
 340         u8         srq_receive[0x1];
 341         u8         reserved_0[0x1a];
 342 };
 343
 344 struct mlx5_ifc_flow_counter_list_bits {
 345         u8         reserved_0[0x10];
 346         u8         flow_counter_id[0x10];
 347
 348         u8         reserved_1[0x20];
 349 };
 350
 351 enum {
 352         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 353         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 354         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 355 };
 356
 357 struct mlx5_ifc_dest_format_struct_bits {
 358         u8         destination_type[0x8];
 359         u8         destination_id[0x18];
 360
 361         u8         reserved_0[0x20];
 362 };
 363
 364 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 365         u8         smac_47_16[0x20];
 366
 367         u8         smac_15_0[0x10];
 368         u8         ethertype[0x10];
 369
 370         u8         dmac_47_16[0x20];
 371
 372         u8         dmac_15_0[0x10];
 373         u8         first_prio[0x3];
 374         u8         first_cfi[0x1];
 375         u8         first_vid[0xc];
 376
 377         u8         ip_protocol[0x8];
 378         u8         ip_dscp[0x6];
 379         u8         ip_ecn[0x2];
 380         u8         cvlan_tag[0x1];
 381         u8         svlan_tag[0x1];
 382         u8         frag[0x1];
 383         u8         reserved_1[0x4];
 384         u8         tcp_flags[0x9];
 385
 386         u8         tcp_sport[0x10];
 387         u8         tcp_dport[0x10];
 388
 389         u8         reserved_2[0x20];
 390
 391         u8         udp_sport[0x10];
 392         u8         udp_dport[0x10];
 393
 394         u8         src_ip[4][0x20];
 395
 396         u8         dst_ip[4][0x20];
 397 };
 398
 399 struct mlx5_ifc_fte_match_set_misc_bits {
 400         u8         reserved_0[0x8];
 401         u8         source_sqn[0x18];
 402
 403         u8         reserved_1[0x10];
 404         u8         source_port[0x10];
 405
 406         u8         outer_second_prio[0x3];
 407         u8         outer_second_cfi[0x1];
 408         u8         outer_second_vid[0xc];
 409         u8         inner_second_prio[0x3];
 410         u8         inner_second_cfi[0x1];
 411         u8         inner_second_vid[0xc];
 412
 413         u8         outer_second_vlan_tag[0x1];
 414         u8         inner_second_vlan_tag[0x1];
 415         u8         reserved_2[0xe];
 416         u8         gre_protocol[0x10];
 417
 418         u8         gre_key_h[0x18];
 419         u8         gre_key_l[0x8];
 420
 421         u8         vxlan_vni[0x18];
 422         u8         reserved_3[0x8];
 423
 424         u8         reserved_4[0x20];
 425
 426         u8         reserved_5[0xc];
 427         u8         outer_ipv6_flow_label[0x14];
 428
 429         u8         reserved_6[0xc];
 430         u8         inner_ipv6_flow_label[0x14];
 431
 432         u8         reserved_7[0xe0];
 433 };
 434
 435 struct mlx5_ifc_cmd_pas_bits {
 436         u8         pa_h[0x20];
 437
 438         u8         pa_l[0x14];
 439         u8         reserved_0[0xc];
 440 };
 441
 442 struct mlx5_ifc_uint64_bits {
 443         u8         hi[0x20];
 444
 445         u8         lo[0x20];
 446 };
 447
 448 struct mlx5_ifc_application_prio_entry_bits {
 449         u8         reserved_0[0x8];
 450         u8         priority[0x3];
 451         u8         reserved_1[0x2];
 452         u8         sel[0x3];
 453         u8         protocol_id[0x10];
 454 };
 455
 456 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 457         u8         reserved_0[0x8];
 458         u8         ring_pi[0x10];
 459         u8         reserved_1[0x8];
 460 };
 461
 462 enum {
 463         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 464         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 465         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 466         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 467         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 468         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 469         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 470         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 471         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 472         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 473 };
 474
 475 struct mlx5_ifc_ads_bits {
 476         u8         fl[0x1];
 477         u8         free_ar[0x1];
 478         u8         reserved_0[0xe];
 479         u8         pkey_index[0x10];
 480
 481         u8         reserved_1[0x8];
 482         u8         grh[0x1];
 483         u8         mlid[0x7];
 484         u8         rlid[0x10];
 485
 486         u8         ack_timeout[0x5];
 487         u8         reserved_2[0x3];
 488         u8         src_addr_index[0x8];
 489         u8         log_rtm[0x4];
 490         u8         stat_rate[0x4];
 491         u8         hop_limit[0x8];
 492
 493         u8         reserved_3[0x4];
 494         u8         tclass[0x8];
 495         u8         flow_label[0x14];
 496
 497         u8         rgid_rip[16][0x8];
 498
 499         u8         reserved_4[0x4];
 500         u8         f_dscp[0x1];
 501         u8         f_ecn[0x1];
 502         u8         reserved_5[0x1];
 503         u8         f_eth_prio[0x1];
 504         u8         ecn[0x2];
 505         u8         dscp[0x6];
 506         u8         udp_sport[0x10];
 507
 508         u8         dei_cfi[0x1];
 509         u8         eth_prio[0x3];
 510         u8         sl[0x4];
 511         u8         port[0x8];
 512         u8         rmac_47_32[0x10];
 513
 514         u8         rmac_31_0[0x20];
 515 };
 516
 517 struct mlx5_ifc_diagnostic_counter_cap_bits {
 518         u8         sync[0x1];
 519         u8         reserved_0[0xf];
 520         u8         counter_id[0x10];
 521 };
 522
 523 struct mlx5_ifc_debug_cap_bits {
 524         u8         reserved_0[0x18];
 525         u8         log_max_samples[0x8];
 526
 527         u8         single[0x1];
 528         u8         repetitive[0x1];
 529         u8         health_mon_rx_activity[0x1];
 530         u8         reserved_1[0x15];
 531         u8         log_min_sample_period[0x8];
 532
 533         u8         reserved_2[0x1c0];
 534
 535         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 536 };
 537
 538 struct mlx5_ifc_snapshot_cap_bits {
 539         u8         reserved_0[0x1d];
 540         u8         suspend_qp_uc[0x1];
 541         u8         suspend_qp_ud[0x1];
 542         u8         suspend_qp_rc[0x1];
 543
 544         u8         reserved_1[0x1c];
 545         u8         restore_pd[0x1];
 546         u8         restore_uar[0x1];
 547         u8         restore_mkey[0x1];
 548         u8         restore_qp[0x1];
 549
 550         u8         reserved_2[0x1e];
 551         u8         named_mkey[0x1];
 552         u8         named_qp[0x1];
 553
 554         u8         reserved_3[0x7a0];
 555 };
 556
 557 struct mlx5_ifc_e_switch_cap_bits {
 558         u8         vport_svlan_strip[0x1];
 559         u8         vport_cvlan_strip[0x1];
 560         u8         vport_svlan_insert[0x1];
 561         u8         vport_cvlan_insert_if_not_exist[0x1];
 562         u8         vport_cvlan_insert_overwrite[0x1];
 563
 564         u8         reserved_0[0x19];
 565
 566         u8         nic_vport_node_guid_modify[0x1];
 567         u8         nic_vport_port_guid_modify[0x1];
 568
 569         u8         reserved_1[0x7e0];
 570 };
 571
 572 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 573         u8         reserved_0[0x200];
 574
 575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 576
 577         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 580
 581         u8         reserved_1[0x7800];
 582 };
 583
 584 struct mlx5_ifc_flow_table_nic_cap_bits {
 585         u8         reserved_0[0x200];
 586
 587         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 588
 589         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 590
 591         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 592
 593         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 594
 595         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 596
 597         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 598
 599         u8         reserved_1[0x7200];
 600 };
 601
 602 struct mlx5_ifc_qos_cap_bits {
 603         u8         packet_pacing[0x1];
 604         u8         reserved_0[0x1f];
 605         u8         reserved_1[0x20];
 606         u8         packet_pacing_max_rate[0x20];
 607         u8         packet_pacing_min_rate[0x20];
 608         u8         reserved_2[0x10];
 609         u8         packet_pacing_rate_table_size[0x10];
 610         u8         reserved_3[0x760];
 611 };
 612
 613 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 614         u8         csum_cap[0x1];
 615         u8         vlan_cap[0x1];
 616         u8         lro_cap[0x1];
 617         u8         lro_psh_flag[0x1];
 618         u8         lro_time_stamp[0x1];
 619         u8         lro_max_msg_sz_mode[0x2];
 620         u8         reserved_0[0x2];
 621         u8         self_lb_mc[0x1];
 622         u8         self_lb_uc[0x1];
 623         u8         max_lso_cap[0x5];
 624         u8         multi_pkt_send_wqe[0x2];
 625         u8         wqe_inline_mode[0x2];
 626         u8         rss_ind_tbl_cap[0x4];
 627         u8         reserved_1[0x3];
 628         u8         tunnel_lso_const_out_ip_id[0x1];
 629         u8         tunnel_lro_gre[0x1];
 630         u8         tunnel_lro_vxlan[0x1];
 631         u8         tunnel_statless_gre[0x1];
 632         u8         tunnel_stateless_vxlan[0x1];
 633
 634         u8         reserved_2[0x20];
 635
 636         u8         reserved_3[0x10];
 637         u8         lro_min_mss_size[0x10];
 638
 639         u8         reserved_4[0x120];
 640
 641         u8         lro_timer_supported_periods[4][0x20];
 642
 643         u8         reserved_5[0x600];
 644 };
 645
 646 enum {
 647         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 648         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 649         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 650 };
 651
 652 struct mlx5_ifc_roce_cap_bits {
 653         u8         roce_apm[0x1];
 654         u8         rts2rts_primary_eth_prio[0x1];
 655         u8         roce_rx_allow_untagged[0x1];
 656         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 657
 658         u8         reserved_0[0x1c];
 659
 660         u8         reserved_1[0x60];
 661
 662         u8         reserved_2[0xc];
 663         u8         l3_type[0x4];
 664         u8         reserved_3[0x8];
 665         u8         roce_version[0x8];
 666
 667         u8         reserved_4[0x10];
 668         u8         r_roce_dest_udp_port[0x10];
 669
 670         u8         r_roce_max_src_udp_port[0x10];
 671         u8         r_roce_min_src_udp_port[0x10];
 672
 673         u8         reserved_5[0x10];
 674         u8         roce_address_table_size[0x10];
 675
 676         u8         reserved_6[0x700];
 677 };
 678
 679 enum {
 680         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 681         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 682         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 683         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 684         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 685         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 686         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 687         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 688         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 689 };
 690
 691 enum {
 692         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 693         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 694         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 695         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 696         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 701 };
 702
 703 struct mlx5_ifc_atomic_caps_bits {
 704         u8         reserved_0[0x40];
 705
 706         u8         atomic_req_8B_endianess_mode[0x2];
 707         u8         reserved_1[0x4];
 708         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 709
 710         u8         reserved_2[0x19];
 711
 712         u8         reserved_3[0x20];
 713
 714         u8         reserved_4[0x10];
 715         u8         atomic_operations[0x10];
 716
 717         u8         reserved_5[0x10];
 718         u8         atomic_size_qp[0x10];
 719
 720         u8         reserved_6[0x10];
 721         u8         atomic_size_dc[0x10];
 722
 723         u8         reserved_7[0x720];
 724 };
 725
 726 struct mlx5_ifc_odp_cap_bits {
 727         u8         reserved_0[0x40];
 728
 729         u8         sig[0x1];
 730         u8         reserved_1[0x1f];
 731
 732         u8         reserved_2[0x20];
 733
 734         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 735
 736         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 737
 738         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 739
 740         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 741
 742         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
 743
 744         u8         reserved_3[0x6e0];
 745 };
 746
 747 enum {
 748         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 749         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 750         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 751         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 752         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 753 };
 754
 755 enum {
 756         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 757         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 758         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 759         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 760         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 761         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 762 };
 763
 764 enum {
 765         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 766         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 767 };
 768
 769 enum {
 770         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 771         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 772         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 773 };
 774
 775 struct mlx5_ifc_cmd_hca_cap_bits {
 776         u8         reserved_0[0x80];
 777
 778         u8         log_max_srq_sz[0x8];
 779         u8         log_max_qp_sz[0x8];
 780         u8         reserved_1[0xb];
 781         u8         log_max_qp[0x5];
 782
 783         u8         reserved_2[0xb];
 784         u8         log_max_srq[0x5];
 785         u8         reserved_3[0x10];
 786
 787         u8         reserved_4[0x8];
 788         u8         log_max_cq_sz[0x8];
 789         u8         reserved_5[0xb];
 790         u8         log_max_cq[0x5];
 791
 792         u8         log_max_eq_sz[0x8];
 793         u8         reserved_6[0x2];
 794         u8         log_max_mkey[0x6];
 795         u8         reserved_7[0xc];
 796         u8         log_max_eq[0x4];
 797
 798         u8         max_indirection[0x8];
 799         u8         reserved_8[0x1];
 800         u8         log_max_mrw_sz[0x7];
 801         u8         reserved_9[0x2];
 802         u8         log_max_bsf_list_size[0x6];
 803         u8         reserved_10[0x2];
 804         u8         log_max_klm_list_size[0x6];
 805
 806         u8         reserved_11[0xa];
 807         u8         log_max_ra_req_dc[0x6];
 808         u8         reserved_12[0xa];
 809         u8         log_max_ra_res_dc[0x6];
 810
 811         u8         reserved_13[0xa];
 812         u8         log_max_ra_req_qp[0x6];
 813         u8         reserved_14[0xa];
 814         u8         log_max_ra_res_qp[0x6];
 815
 816         u8         pad_cap[0x1];
 817         u8         cc_query_allowed[0x1];
 818         u8         cc_modify_allowed[0x1];
 819         u8         start_pad[0x1];
 820         u8         cache_line_128byte[0x1];
 821         u8         reserved_15[0xb];
 822         u8         gid_table_size[0x10];
 823
 824         u8         out_of_seq_cnt[0x1];
 825         u8         vport_counters[0x1];
 826         u8         retransmission_q_counters[0x1];
 827         u8         debug[0x1];
 828         u8         reserved_16[0x2];
 829         u8         max_qp_cnt[0xa];
 830         u8         pkey_table_size[0x10];
 831
 832         u8         vport_group_manager[0x1];
 833         u8         vhca_group_manager[0x1];
 834         u8         ib_virt[0x1];
 835         u8         eth_virt[0x1];
 836         u8         reserved_17[0x1];
 837         u8         ets[0x1];
 838         u8         nic_flow_table[0x1];
 839         u8         eswitch_flow_table[0x1];
 840         u8         reserved_18[0x3];
 841         u8         local_ca_ack_delay[0x5];
 842         u8         port_module_event[0x1];
 843         u8         reserved_19[0x5];
 844         u8         port_type[0x2];
 845         u8         num_ports[0x8];
 846
 847         u8         snapshot[0x1];
 848         u8         reserved_20[0x2];
 849         u8         log_max_msg[0x5];
 850         u8         reserved_21[0x4];
 851         u8         max_tc[0x4];
 852         u8         temp_warn_event[0x1];
 853         u8         dcbx[0x1];
 854         u8         reserved_22[0x4];
 855         u8         rol_s[0x1];
 856         u8         rol_g[0x1];
 857         u8         reserved_23[0x1];
 858         u8         wol_s[0x1];
 859         u8         wol_g[0x1];
 860         u8         wol_a[0x1];
 861         u8         wol_b[0x1];
 862         u8         wol_m[0x1];
 863         u8         wol_u[0x1];
 864         u8         wol_p[0x1];
 865
 866         u8         stat_rate_support[0x10];
 867         u8         reserved_24[0xc];
 868         u8         cqe_version[0x4];
 869
 870         u8         compact_address_vector[0x1];
 871         u8         striding_rq[0x1];
 872         u8         reserved_25[0x1];
 873         u8         ipoib_enhanced_offloads[0x1];
 874         u8         ipoib_ipoib_offloads[0x1];
 875         u8         reserved_26[0x8];
 876         u8         dc_connect_qp[0x1];
 877         u8         dc_cnak_trace[0x1];
 878         u8         drain_sigerr[0x1];
 879         u8         cmdif_checksum[0x2];
 880         u8         sigerr_cqe[0x1];
 881         u8         reserved_27[0x1];
 882         u8         wq_signature[0x1];
 883         u8         sctr_data_cqe[0x1];
 884         u8         reserved_28[0x1];
 885         u8         sho[0x1];
 886         u8         tph[0x1];
 887         u8         rf[0x1];
 888         u8         dct[0x1];
 889         u8         qos[0x1];
 890         u8         eth_net_offloads[0x1];
 891         u8         roce[0x1];
 892         u8         atomic[0x1];
 893         u8         reserved_30[0x1];
 894
 895         u8         cq_oi[0x1];
 896         u8         cq_resize[0x1];
 897         u8         cq_moderation[0x1];
 898         u8         reserved_31[0x3];
 899         u8         cq_eq_remap[0x1];
 900         u8         pg[0x1];
 901         u8         block_lb_mc[0x1];
 902         u8         exponential_backoff[0x1];
 903         u8         scqe_break_moderation[0x1];
 904         u8         cq_period_start_from_cqe[0x1];
 905         u8         cd[0x1];
 906         u8         atm[0x1];
 907         u8         apm[0x1];
 908         u8         reserved_32[0x7];
 909         u8         qkv[0x1];
 910         u8         pkv[0x1];
 911         u8         reserved_33[0x4];
 912         u8         xrc[0x1];
 913         u8         ud[0x1];
 914         u8         uc[0x1];
 915         u8         rc[0x1];
 916
 917         u8         reserved_34[0xa];
 918         u8         uar_sz[0x6];
 919         u8         reserved_35[0x8];
 920         u8         log_pg_sz[0x8];
 921
 922         u8         bf[0x1];
 923         u8         driver_version[0x1];
 924         u8         pad_tx_eth_packet[0x1];
 925         u8         reserved_36[0x8];
 926         u8         log_bf_reg_size[0x5];
 927         u8         reserved_37[0x10];
 928
 929         u8         num_of_diagnostic_counters[0x10];
 930         u8         max_wqe_sz_sq[0x10];
 931
 932         u8         reserved_38[0x10];
 933         u8         max_wqe_sz_rq[0x10];
 934
 935         u8         reserved_39[0x10];
 936         u8         max_wqe_sz_sq_dc[0x10];
 937
 938         u8         reserved_40[0x7];
 939         u8         max_qp_mcg[0x19];
 940
 941         u8         reserved_41[0x18];
 942         u8         log_max_mcg[0x8];
 943
 944         u8         reserved_42[0x3];
 945         u8         log_max_transport_domain[0x5];
 946         u8         reserved_43[0x3];
 947         u8         log_max_pd[0x5];
 948         u8         reserved_44[0xb];
 949         u8         log_max_xrcd[0x5];
 950
 951         u8         reserved_45[0x10];
 952         u8         max_flow_counter[0x10];
 953
 954         u8         reserved_46[0x3];
 955         u8         log_max_rq[0x5];
 956         u8         reserved_47[0x3];
 957         u8         log_max_sq[0x5];
 958         u8         reserved_48[0x3];
 959         u8         log_max_tir[0x5];
 960         u8         reserved_49[0x3];
 961         u8         log_max_tis[0x5];
 962
 963         u8         basic_cyclic_rcv_wqe[0x1];
 964         u8         reserved_50[0x2];
 965         u8         log_max_rmp[0x5];
 966         u8         reserved_51[0x3];
 967         u8         log_max_rqt[0x5];
 968         u8         reserved_52[0x3];
 969         u8         log_max_rqt_size[0x5];
 970         u8         reserved_53[0x3];
 971         u8         log_max_tis_per_sq[0x5];
 972
 973         u8         reserved_54[0x3];
 974         u8         log_max_stride_sz_rq[0x5];
 975         u8         reserved_55[0x3];
 976         u8         log_min_stride_sz_rq[0x5];
 977         u8         reserved_56[0x3];
 978         u8         log_max_stride_sz_sq[0x5];
 979         u8         reserved_57[0x3];
 980         u8         log_min_stride_sz_sq[0x5];
 981
 982         u8         reserved_58[0x1b];
 983         u8         log_max_wq_sz[0x5];
 984
 985         u8         nic_vport_change_event[0x1];
 986         u8         reserved_59[0xa];
 987         u8         log_max_vlan_list[0x5];
 988         u8         reserved_60[0x3];
 989         u8         log_max_current_mc_list[0x5];
 990         u8         reserved_61[0x3];
 991         u8         log_max_current_uc_list[0x5];
 992
 993         u8         reserved_62[0x80];
 994
 995         u8         reserved_63[0x3];
 996         u8         log_max_l2_table[0x5];
 997         u8         reserved_64[0x8];
 998         u8         log_uar_page_sz[0x10];
 999
1000         u8         reserved_65[0x20];
1001
1002         u8         device_frequency_mhz[0x20];
1003
1004         u8         device_frequency_khz[0x20];
1005
1006         u8         reserved_66[0x80];
1007
1008         u8         log_max_atomic_size_qp[0x8];
1009         u8         reserved_67[0x10];
1010         u8         log_max_atomic_size_dc[0x8];
1011
1012         u8         reserved_68[0x1f];
1013         u8         cqe_compression[0x1];
1014
1015         u8         cqe_compression_timeout[0x10];
1016         u8         cqe_compression_max_num[0x10];
1017
1018         u8         reserved_69[0x220];
1019 };
1020
1021 enum mlx5_flow_destination_type {
1022         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1023         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1024         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1025 };
1026
1027 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1028         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1029         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1030         u8         reserved_0[0x40];
1031 };
1032
1033 struct mlx5_ifc_fte_match_param_bits {
1034         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1035
1036         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1037
1038         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1039
1040         u8         reserved_0[0xa00];
1041 };
1042
1043 enum {
1044         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1045         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1046         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1047         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1048         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1049 };
1050
1051 struct mlx5_ifc_rx_hash_field_select_bits {
1052         u8         l3_prot_type[0x1];
1053         u8         l4_prot_type[0x1];
1054         u8         selected_fields[0x1e];
1055 };
1056
1057 enum {
1058         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1059         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1060         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1061         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1062 };
1063
1064 enum rq_type {
1065         RQ_TYPE_NONE,
1066         RQ_TYPE_STRIDE,
1067 };
1068
1069 enum {
1070         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1071         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1072 };
1073
1074 struct mlx5_ifc_wq_bits {
1075         u8         wq_type[0x4];
1076         u8         wq_signature[0x1];
1077         u8         end_padding_mode[0x2];
1078         u8         cd_slave[0x1];
1079         u8         reserved_0[0x18];
1080
1081         u8         hds_skip_first_sge[0x1];
1082         u8         log2_hds_buf_size[0x3];
1083         u8         reserved_1[0x7];
1084         u8         page_offset[0x5];
1085         u8         lwm[0x10];
1086
1087         u8         reserved_2[0x8];
1088         u8         pd[0x18];
1089
1090         u8         reserved_3[0x8];
1091         u8         uar_page[0x18];
1092
1093         u8         dbr_addr[0x40];
1094
1095         u8         hw_counter[0x20];
1096
1097         u8         sw_counter[0x20];
1098
1099         u8         reserved_4[0xc];
1100         u8         log_wq_stride[0x4];
1101         u8         reserved_5[0x3];
1102         u8         log_wq_pg_sz[0x5];
1103         u8         reserved_6[0x3];
1104         u8         log_wq_sz[0x5];
1105
1106         u8         reserved_7[0x15];
1107         u8         single_wqe_log_num_of_strides[0x3];
1108         u8         two_byte_shift_en[0x1];
1109         u8         reserved_8[0x4];
1110         u8         single_stride_log_num_of_bytes[0x3];
1111
1112         u8         reserved_9[0x4c0];
1113
1114         struct mlx5_ifc_cmd_pas_bits pas[0];
1115 };
1116
1117 struct mlx5_ifc_rq_num_bits {
1118         u8         reserved_0[0x8];
1119         u8         rq_num[0x18];
1120 };
1121
1122 struct mlx5_ifc_mac_address_layout_bits {
1123         u8         reserved_0[0x10];
1124         u8         mac_addr_47_32[0x10];
1125
1126         u8         mac_addr_31_0[0x20];
1127 };
1128
1129 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1130         u8         reserved_0[0xa0];
1131
1132         u8         min_time_between_cnps[0x20];
1133
1134         u8         reserved_1[0x12];
1135         u8         cnp_dscp[0x6];
1136         u8         reserved_2[0x4];
1137         u8         cnp_prio_mode[0x1];
1138         u8         cnp_802p_prio[0x3];
1139
1140         u8         reserved_3[0x720];
1141 };
1142
1143 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1144         u8         reserved_0[0x60];
1145
1146         u8         reserved_1[0x4];
1147         u8         clamp_tgt_rate[0x1];
1148         u8         reserved_2[0x3];
1149         u8         clamp_tgt_rate_after_time_inc[0x1];
1150         u8         reserved_3[0x17];
1151
1152         u8         reserved_4[0x20];
1153
1154         u8         rpg_time_reset[0x20];
1155
1156         u8         rpg_byte_reset[0x20];
1157
1158         u8         rpg_threshold[0x20];
1159
1160         u8         rpg_max_rate[0x20];
1161
1162         u8         rpg_ai_rate[0x20];
1163
1164         u8         rpg_hai_rate[0x20];
1165
1166         u8         rpg_gd[0x20];
1167
1168         u8         rpg_min_dec_fac[0x20];
1169
1170         u8         rpg_min_rate[0x20];
1171
1172         u8         reserved_5[0xe0];
1173
1174         u8         rate_to_set_on_first_cnp[0x20];
1175
1176         u8         dce_tcp_g[0x20];
1177
1178         u8         dce_tcp_rtt[0x20];
1179
1180         u8         rate_reduce_monitor_period[0x20];
1181
1182         u8         reserved_6[0x20];
1183
1184         u8         initial_alpha_value[0x20];
1185
1186         u8         reserved_7[0x4a0];
1187 };
1188
1189 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1190         u8         reserved_0[0x80];
1191
1192         u8         rppp_max_rps[0x20];
1193
1194         u8         rpg_time_reset[0x20];
1195
1196         u8         rpg_byte_reset[0x20];
1197
1198         u8         rpg_threshold[0x20];
1199
1200         u8         rpg_max_rate[0x20];
1201
1202         u8         rpg_ai_rate[0x20];
1203
1204         u8         rpg_hai_rate[0x20];
1205
1206         u8         rpg_gd[0x20];
1207
1208         u8         rpg_min_dec_fac[0x20];
1209
1210         u8         rpg_min_rate[0x20];
1211
1212         u8         reserved_1[0x640];
1213 };
1214
1215 enum {
1216         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1217         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1218         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1219 };
1220
1221 struct mlx5_ifc_resize_field_select_bits {
1222         u8         resize_field_select[0x20];
1223 };
1224
1225 enum {
1226         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1227         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1228         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1229         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1230 };
1231
1232 struct mlx5_ifc_modify_field_select_bits {
1233         u8         modify_field_select[0x20];
1234 };
1235
1236 struct mlx5_ifc_field_select_r_roce_np_bits {
1237         u8         field_select_r_roce_np[0x20];
1238 };
1239
1240 enum {
1241         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1242         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1243         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1244         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1245         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1246         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1247         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1248         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1249         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1250         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1251         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1252         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1253         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1254         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1255         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1256 };
1257
1258 struct mlx5_ifc_field_select_r_roce_rp_bits {
1259         u8         field_select_r_roce_rp[0x20];
1260 };
1261
1262 enum {
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1268         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1269         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1270         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1272         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1273 };
1274
1275 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1276         u8         field_select_8021qaurp[0x20];
1277 };
1278
1279 struct mlx5_ifc_pptb_reg_bits {
1280         u8         reserved_0[0x2];
1281         u8         mm[0x2];
1282         u8         reserved_1[0x4];
1283         u8         local_port[0x8];
1284         u8         reserved_2[0x6];
1285         u8         cm[0x1];
1286         u8         um[0x1];
1287         u8         pm[0x8];
1288
1289         u8         prio7buff[0x4];
1290         u8         prio6buff[0x4];
1291         u8         prio5buff[0x4];
1292         u8         prio4buff[0x4];
1293         u8         prio3buff[0x4];
1294         u8         prio2buff[0x4];
1295         u8         prio1buff[0x4];
1296         u8         prio0buff[0x4];
1297
1298         u8         pm_msb[0x8];
1299         u8         reserved_3[0x10];
1300         u8         ctrl_buff[0x4];
1301         u8         untagged_buff[0x4];
1302 };
1303
1304 struct mlx5_ifc_dcbx_app_reg_bits {
1305         u8         reserved_0[0x8];
1306         u8         port_number[0x8];
1307         u8         reserved_1[0x10];
1308
1309         u8         reserved_2[0x1a];
1310         u8         num_app_prio[0x6];
1311
1312         u8         reserved_3[0x40];
1313
1314         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1315 };
1316
1317 struct mlx5_ifc_dcbx_param_reg_bits {
1318         u8         dcbx_cee_cap[0x1];
1319         u8         dcbx_ieee_cap[0x1];
1320         u8         dcbx_standby_cap[0x1];
1321         u8         reserved_0[0x5];
1322         u8         port_number[0x8];
1323         u8         reserved_1[0xa];
1324         u8         max_application_table_size[0x6];
1325
1326         u8         reserved_2[0x15];
1327         u8         version_oper[0x3];
1328         u8         reserved_3[0x5];
1329         u8         version_admin[0x3];
1330
1331         u8         willing_admin[0x1];
1332         u8         reserved_4[0x3];
1333         u8         pfc_cap_oper[0x4];
1334         u8         reserved_5[0x4];
1335         u8         pfc_cap_admin[0x4];
1336         u8         reserved_6[0x4];
1337         u8         num_of_tc_oper[0x4];
1338         u8         reserved_7[0x4];
1339         u8         num_of_tc_admin[0x4];
1340
1341         u8         remote_willing[0x1];
1342         u8         reserved_8[0x3];
1343         u8         remote_pfc_cap[0x4];
1344         u8         reserved_9[0x14];
1345         u8         remote_num_of_tc[0x4];
1346
1347         u8         reserved_10[0x18];
1348         u8         error[0x8];
1349
1350         u8         reserved_11[0x160];
1351 };
1352
1353 struct mlx5_ifc_qetcr_reg_bits {
1354         u8         operation_type[0x2];
1355         u8         cap_local_admin[0x1];
1356         u8         cap_remote_admin[0x1];
1357         u8         reserved_0[0x4];
1358         u8         port_number[0x8];
1359         u8         reserved_1[0x10];
1360
1361         u8         reserved_2[0x20];
1362
1363         u8         tc[8][0x40];
1364
1365         u8         global_configuration[0x40];
1366 };
1367
1368 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1369         u8         queue_address_63_32[0x20];
1370
1371         u8         queue_address_31_12[0x14];
1372         u8         reserved_0[0x6];
1373         u8         log_size[0x6];
1374
1375         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1376
1377         u8         reserved_1[0x8];
1378         u8         queue_number[0x18];
1379
1380         u8         q_key[0x20];
1381
1382         u8         reserved_2[0x10];
1383         u8         pkey_index[0x10];
1384
1385         u8         reserved_3[0x40];
1386 };
1387
1388 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1389         u8         reserved_0[0x8];
1390         u8         cq_ci[0x10];
1391         u8         reserved_1[0x8];
1392 };
1393
1394 enum {
1395         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1396         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1397 };
1398
1399 enum {
1400         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1401         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1402         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1403         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1404 };
1405
1406 struct mlx5_ifc_nodnic_event_word_bits {
1407         u8         driver_reset_needed[0x1];
1408         u8         port_management_change_event[0x1];
1409         u8         reserved_0[0x19];
1410         u8         link_type[0x1];
1411         u8         port_state[0x4];
1412 };
1413
1414 struct mlx5_ifc_nic_vport_change_event_bits {
1415         u8         reserved_0[0x10];
1416         u8         vport_num[0x10];
1417
1418         u8         reserved_1[0xc0];
1419 };
1420
1421 struct mlx5_ifc_pages_req_event_bits {
1422         u8         reserved_0[0x10];
1423         u8         function_id[0x10];
1424
1425         u8         num_pages[0x20];
1426
1427         u8         reserved_1[0xa0];
1428 };
1429
1430 struct mlx5_ifc_cmd_inter_comp_event_bits {
1431         u8         command_completion_vector[0x20];
1432
1433         u8         reserved_0[0xc0];
1434 };
1435
1436 struct mlx5_ifc_stall_vl_event_bits {
1437         u8         reserved_0[0x18];
1438         u8         port_num[0x1];
1439         u8         reserved_1[0x3];
1440         u8         vl[0x4];
1441
1442         u8         reserved_2[0xa0];
1443 };
1444
1445 struct mlx5_ifc_db_bf_congestion_event_bits {
1446         u8         event_subtype[0x8];
1447         u8         reserved_0[0x8];
1448         u8         congestion_level[0x8];
1449         u8         reserved_1[0x8];
1450
1451         u8         reserved_2[0xa0];
1452 };
1453
1454 struct mlx5_ifc_gpio_event_bits {
1455         u8         reserved_0[0x60];
1456
1457         u8         gpio_event_hi[0x20];
1458
1459         u8         gpio_event_lo[0x20];
1460
1461         u8         reserved_1[0x40];
1462 };
1463
1464 struct mlx5_ifc_port_state_change_event_bits {
1465         u8         reserved_0[0x40];
1466
1467         u8         port_num[0x4];
1468         u8         reserved_1[0x1c];
1469
1470         u8         reserved_2[0x80];
1471 };
1472
1473 struct mlx5_ifc_dropped_packet_logged_bits {
1474         u8         reserved_0[0xe0];
1475 };
1476
1477 enum {
1478         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1479         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1480 };
1481
1482 struct mlx5_ifc_cq_error_bits {
1483         u8         reserved_0[0x8];
1484         u8         cqn[0x18];
1485
1486         u8         reserved_1[0x20];
1487
1488         u8         reserved_2[0x18];
1489         u8         syndrome[0x8];
1490
1491         u8         reserved_3[0x80];
1492 };
1493
1494 struct mlx5_ifc_rdma_page_fault_event_bits {
1495         u8         bytes_commited[0x20];
1496
1497         u8         r_key[0x20];
1498
1499         u8         reserved_0[0x10];
1500         u8         packet_len[0x10];
1501
1502         u8         rdma_op_len[0x20];
1503
1504         u8         rdma_va[0x40];
1505
1506         u8         reserved_1[0x5];
1507         u8         rdma[0x1];
1508         u8         write[0x1];
1509         u8         requestor[0x1];
1510         u8         qp_number[0x18];
1511 };
1512
1513 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1514         u8         bytes_committed[0x20];
1515
1516         u8         reserved_0[0x10];
1517         u8         wqe_index[0x10];
1518
1519         u8         reserved_1[0x10];
1520         u8         len[0x10];
1521
1522         u8         reserved_2[0x60];
1523
1524         u8         reserved_3[0x5];
1525         u8         rdma[0x1];
1526         u8         write_read[0x1];
1527         u8         requestor[0x1];
1528         u8         qpn[0x18];
1529 };
1530
1531 enum {
1532         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1533         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1534         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1535 };
1536
1537 struct mlx5_ifc_qp_events_bits {
1538         u8         reserved_0[0xa0];
1539
1540         u8         type[0x8];
1541         u8         reserved_1[0x18];
1542
1543         u8         reserved_2[0x8];
1544         u8         qpn_rqn_sqn[0x18];
1545 };
1546
1547 struct mlx5_ifc_dct_events_bits {
1548         u8         reserved_0[0xc0];
1549
1550         u8         reserved_1[0x8];
1551         u8         dct_number[0x18];
1552 };
1553
1554 struct mlx5_ifc_comp_event_bits {
1555         u8         reserved_0[0xc0];
1556
1557         u8         reserved_1[0x8];
1558         u8         cq_number[0x18];
1559 };
1560
1561 struct mlx5_ifc_fw_version_bits {
1562         u8         major[0x10];
1563         u8         reserved_0[0x10];
1564
1565         u8         minor[0x10];
1566         u8         subminor[0x10];
1567
1568         u8         second[0x8];
1569         u8         minute[0x8];
1570         u8         hour[0x8];
1571         u8         reserved_1[0x8];
1572
1573         u8         year[0x10];
1574         u8         month[0x8];
1575         u8         day[0x8];
1576 };
1577
1578 enum {
1579         MLX5_QPC_STATE_RST        = 0x0,
1580         MLX5_QPC_STATE_INIT       = 0x1,
1581         MLX5_QPC_STATE_RTR        = 0x2,
1582         MLX5_QPC_STATE_RTS        = 0x3,
1583         MLX5_QPC_STATE_SQER       = 0x4,
1584         MLX5_QPC_STATE_SQD        = 0x5,
1585         MLX5_QPC_STATE_ERR        = 0x6,
1586         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1587 };
1588
1589 enum {
1590         MLX5_QPC_ST_RC            = 0x0,
1591         MLX5_QPC_ST_UC            = 0x1,
1592         MLX5_QPC_ST_UD            = 0x2,
1593         MLX5_QPC_ST_XRC           = 0x3,
1594         MLX5_QPC_ST_DCI           = 0x5,
1595         MLX5_QPC_ST_QP0           = 0x7,
1596         MLX5_QPC_ST_QP1           = 0x8,
1597         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1598         MLX5_QPC_ST_REG_UMR       = 0xc,
1599 };
1600
1601 enum {
1602         MLX5_QP_PM_ARMED            = 0x0,
1603         MLX5_QP_PM_REARM            = 0x1,
1604         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1605         MLX5_QP_PM_MIGRATED         = 0x3,
1606 };
1607
1608 enum {
1609         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1610         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1611 };
1612
1613 enum {
1614         MLX5_QPC_MTU_256_BYTES        = 0x1,
1615         MLX5_QPC_MTU_512_BYTES        = 0x2,
1616         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1617         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1618         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1619         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1620 };
1621
1622 enum {
1623         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1624         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1625         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1626         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1627         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1628         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1629         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1630         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1631 };
1632
1633 enum {
1634         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1635         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1636         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1637 };
1638
1639 enum {
1640         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1641         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1642         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1643 };
1644
1645 struct mlx5_ifc_qpc_bits {
1646         u8         state[0x4];
1647         u8         reserved_0[0x4];
1648         u8         st[0x8];
1649         u8         reserved_1[0x3];
1650         u8         pm_state[0x2];
1651         u8         reserved_2[0x7];
1652         u8         end_padding_mode[0x2];
1653         u8         reserved_3[0x2];
1654
1655         u8         wq_signature[0x1];
1656         u8         block_lb_mc[0x1];
1657         u8         atomic_like_write_en[0x1];
1658         u8         latency_sensitive[0x1];
1659         u8         reserved_4[0x1];
1660         u8         drain_sigerr[0x1];
1661         u8         reserved_5[0x2];
1662         u8         pd[0x18];
1663
1664         u8         mtu[0x3];
1665         u8         log_msg_max[0x5];
1666         u8         reserved_6[0x1];
1667         u8         log_rq_size[0x4];
1668         u8         log_rq_stride[0x3];
1669         u8         no_sq[0x1];
1670         u8         log_sq_size[0x4];
1671         u8         reserved_7[0x6];
1672         u8         rlky[0x1];
1673         u8         ulp_stateless_offload_mode[0x4];
1674
1675         u8         counter_set_id[0x8];
1676         u8         uar_page[0x18];
1677
1678         u8         reserved_8[0x8];
1679         u8         user_index[0x18];
1680
1681         u8         reserved_9[0x3];
1682         u8         log_page_size[0x5];
1683         u8         remote_qpn[0x18];
1684
1685         struct mlx5_ifc_ads_bits primary_address_path;
1686
1687         struct mlx5_ifc_ads_bits secondary_address_path;
1688
1689         u8         log_ack_req_freq[0x4];
1690         u8         reserved_10[0x4];
1691         u8         log_sra_max[0x3];
1692         u8         reserved_11[0x2];
1693         u8         retry_count[0x3];
1694         u8         rnr_retry[0x3];
1695         u8         reserved_12[0x1];
1696         u8         fre[0x1];
1697         u8         cur_rnr_retry[0x3];
1698         u8         cur_retry_count[0x3];
1699         u8         reserved_13[0x5];
1700
1701         u8         reserved_14[0x20];
1702
1703         u8         reserved_15[0x8];
1704         u8         next_send_psn[0x18];
1705
1706         u8         reserved_16[0x8];
1707         u8         cqn_snd[0x18];
1708
1709         u8         reserved_17[0x40];
1710
1711         u8         reserved_18[0x8];
1712         u8         last_acked_psn[0x18];
1713
1714         u8         reserved_19[0x8];
1715         u8         ssn[0x18];
1716
1717         u8         reserved_20[0x8];
1718         u8         log_rra_max[0x3];
1719         u8         reserved_21[0x1];
1720         u8         atomic_mode[0x4];
1721         u8         rre[0x1];
1722         u8         rwe[0x1];
1723         u8         rae[0x1];
1724         u8         reserved_22[0x1];
1725         u8         page_offset[0x6];
1726         u8         reserved_23[0x3];
1727         u8         cd_slave_receive[0x1];
1728         u8         cd_slave_send[0x1];
1729         u8         cd_master[0x1];
1730
1731         u8         reserved_24[0x3];
1732         u8         min_rnr_nak[0x5];
1733         u8         next_rcv_psn[0x18];
1734
1735         u8         reserved_25[0x8];
1736         u8         xrcd[0x18];
1737
1738         u8         reserved_26[0x8];
1739         u8         cqn_rcv[0x18];
1740
1741         u8         dbr_addr[0x40];
1742
1743         u8         q_key[0x20];
1744
1745         u8         reserved_27[0x5];
1746         u8         rq_type[0x3];
1747         u8         srqn_rmpn[0x18];
1748
1749         u8         reserved_28[0x8];
1750         u8         rmsn[0x18];
1751
1752         u8         hw_sq_wqebb_counter[0x10];
1753         u8         sw_sq_wqebb_counter[0x10];
1754
1755         u8         hw_rq_counter[0x20];
1756
1757         u8         sw_rq_counter[0x20];
1758
1759         u8         reserved_29[0x20];
1760
1761         u8         reserved_30[0xf];
1762         u8         cgs[0x1];
1763         u8         cs_req[0x8];
1764         u8         cs_res[0x8];
1765
1766         u8         dc_access_key[0x40];
1767
1768         u8         rdma_active[0x1];
1769         u8         comm_est[0x1];
1770         u8         suspended[0x1];
1771         u8         reserved_31[0x5];
1772         u8         send_msg_psn[0x18];
1773
1774         u8         reserved_32[0x8];
1775         u8         rcv_msg_psn[0x18];
1776
1777         u8         rdma_va[0x40];
1778
1779         u8         rdma_key[0x20];
1780
1781         u8         reserved_33[0x20];
1782 };
1783
1784 struct mlx5_ifc_roce_addr_layout_bits {
1785         u8         source_l3_address[16][0x8];
1786
1787         u8         reserved_0[0x3];
1788         u8         vlan_valid[0x1];
1789         u8         vlan_id[0xc];
1790         u8         source_mac_47_32[0x10];
1791
1792         u8         source_mac_31_0[0x20];
1793
1794         u8         reserved_1[0x14];
1795         u8         roce_l3_type[0x4];
1796         u8         roce_version[0x8];
1797
1798         u8         reserved_2[0x20];
1799 };
1800
1801 struct mlx5_ifc_rdbc_bits {
1802         u8         reserved_0[0x1c];
1803         u8         type[0x4];
1804
1805         u8         reserved_1[0x20];
1806
1807         u8         reserved_2[0x8];
1808         u8         psn[0x18];
1809
1810         u8         rkey[0x20];
1811
1812         u8         address[0x40];
1813
1814         u8         byte_count[0x20];
1815
1816         u8         reserved_3[0x20];
1817
1818         u8         atomic_resp[32][0x8];
1819 };
1820
1821 enum {
1822         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1823         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1824         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1825         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1826 };
1827
1828 struct mlx5_ifc_flow_context_bits {
1829         u8         reserved_0[0x20];
1830
1831         u8         group_id[0x20];
1832
1833         u8         reserved_1[0x8];
1834         u8         flow_tag[0x18];
1835
1836         u8         reserved_2[0x10];
1837         u8         action[0x10];
1838
1839         u8         reserved_3[0x8];
1840         u8         destination_list_size[0x18];
1841
1842         u8         reserved_4[0x8];
1843         u8         flow_counter_list_size[0x18];
1844
1845         u8         reserved_5[0x140];
1846
1847         struct mlx5_ifc_fte_match_param_bits match_value;
1848
1849         u8         reserved_6[0x600];
1850
1851         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
1852 };
1853
1854 enum {
1855         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1856         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1857 };
1858
1859 struct mlx5_ifc_xrc_srqc_bits {
1860         u8         state[0x4];
1861         u8         log_xrc_srq_size[0x4];
1862         u8         reserved_0[0x18];
1863
1864         u8         wq_signature[0x1];
1865         u8         cont_srq[0x1];
1866         u8         reserved_1[0x1];
1867         u8         rlky[0x1];
1868         u8         basic_cyclic_rcv_wqe[0x1];
1869         u8         log_rq_stride[0x3];
1870         u8         xrcd[0x18];
1871
1872         u8         page_offset[0x6];
1873         u8         reserved_2[0x2];
1874         u8         cqn[0x18];
1875
1876         u8         reserved_3[0x20];
1877
1878         u8         reserved_4[0x2];
1879         u8         log_page_size[0x6];
1880         u8         user_index[0x18];
1881
1882         u8         reserved_5[0x20];
1883
1884         u8         reserved_6[0x8];
1885         u8         pd[0x18];
1886
1887         u8         lwm[0x10];
1888         u8         wqe_cnt[0x10];
1889
1890         u8         reserved_7[0x40];
1891
1892         u8         db_record_addr_h[0x20];
1893
1894         u8         db_record_addr_l[0x1e];
1895         u8         reserved_8[0x2];
1896
1897         u8         reserved_9[0x80];
1898 };
1899
1900 struct mlx5_ifc_traffic_counter_bits {
1901         u8         packets[0x40];
1902
1903         u8         octets[0x40];
1904 };
1905
1906 struct mlx5_ifc_tisc_bits {
1907         u8         reserved_0[0xc];
1908         u8         prio[0x4];
1909         u8         reserved_1[0x10];
1910
1911         u8         reserved_2[0x100];
1912
1913         u8         reserved_3[0x8];
1914         u8         transport_domain[0x18];
1915
1916         u8         reserved_4[0x8];
1917         u8         underlay_qpn[0x18];
1918
1919         u8         reserved_5[0x3a0];
1920 };
1921
1922 enum {
1923         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1924         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1925 };
1926
1927 enum {
1928         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1929         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1930 };
1931
1932 enum {
1933         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
1934         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
1935         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
1936 };
1937
1938 enum {
1939         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
1940         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
1941 };
1942
1943 struct mlx5_ifc_tirc_bits {
1944         u8         reserved_0[0x20];
1945
1946         u8         disp_type[0x4];
1947         u8         reserved_1[0x1c];
1948
1949         u8         reserved_2[0x40];
1950
1951         u8         reserved_3[0x4];
1952         u8         lro_timeout_period_usecs[0x10];
1953         u8         lro_enable_mask[0x4];
1954         u8         lro_max_msg_sz[0x8];
1955
1956         u8         reserved_4[0x40];
1957
1958         u8         reserved_5[0x8];
1959         u8         inline_rqn[0x18];
1960
1961         u8         rx_hash_symmetric[0x1];
1962         u8         reserved_6[0x1];
1963         u8         tunneled_offload_en[0x1];
1964         u8         reserved_7[0x5];
1965         u8         indirect_table[0x18];
1966
1967         u8         rx_hash_fn[0x4];
1968         u8         reserved_8[0x2];
1969         u8         self_lb_en[0x2];
1970         u8         transport_domain[0x18];
1971
1972         u8         rx_hash_toeplitz_key[10][0x20];
1973
1974         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1975
1976         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1977
1978         u8         reserved_9[0x4c0];
1979 };
1980
1981 enum {
1982         MLX5_SRQC_STATE_GOOD   = 0x0,
1983         MLX5_SRQC_STATE_ERROR  = 0x1,
1984 };
1985
1986 struct mlx5_ifc_srqc_bits {
1987         u8         state[0x4];
1988         u8         log_srq_size[0x4];
1989         u8         reserved_0[0x18];
1990
1991         u8         wq_signature[0x1];
1992         u8         cont_srq[0x1];
1993         u8         reserved_1[0x1];
1994         u8         rlky[0x1];
1995         u8         reserved_2[0x1];
1996         u8         log_rq_stride[0x3];
1997         u8         xrcd[0x18];
1998
1999         u8         page_offset[0x6];
2000         u8         reserved_3[0x2];
2001         u8         cqn[0x18];
2002
2003         u8         reserved_4[0x20];
2004
2005         u8         reserved_5[0x2];
2006         u8         log_page_size[0x6];
2007         u8         reserved_6[0x18];
2008
2009         u8         reserved_7[0x20];
2010
2011         u8         reserved_8[0x8];
2012         u8         pd[0x18];
2013
2014         u8         lwm[0x10];
2015         u8         wqe_cnt[0x10];
2016
2017         u8         reserved_9[0x40];
2018
2019         u8         db_record_addr_h[0x20];
2020
2021         u8         db_record_addr_l[0x1e];
2022         u8         reserved_10[0x2];
2023
2024         u8         reserved_11[0x80];
2025 };
2026
2027 enum {
2028         MLX5_SQC_STATE_RST  = 0x0,
2029         MLX5_SQC_STATE_RDY  = 0x1,
2030         MLX5_SQC_STATE_ERR  = 0x3,
2031 };
2032
2033 struct mlx5_ifc_sqc_bits {
2034         u8         rlky[0x1];
2035         u8         cd_master[0x1];
2036         u8         fre[0x1];
2037         u8         flush_in_error_en[0x1];
2038         u8         allow_multi_pkt_send_wqe[0x1];
2039         u8         min_wqe_inline_mode[0x3];
2040         u8         state[0x4];
2041         u8         reserved_0[0x14];
2042
2043         u8         reserved_1[0x8];
2044         u8         user_index[0x18];
2045
2046         u8         reserved_2[0x8];
2047         u8         cqn[0x18];
2048
2049         u8         reserved_3[0x90];
2050         u8         packet_pacing_rate_limit_index[0x10];
2051
2052         u8         tis_lst_sz[0x10];
2053         u8         reserved_4[0x10];
2054
2055         u8         reserved_5[0x40];
2056
2057         u8         reserved_6[0x8];
2058         u8         tis_num_0[0x18];
2059
2060         struct mlx5_ifc_wq_bits wq;
2061 };
2062
2063 struct mlx5_ifc_rqtc_bits {
2064         u8         reserved_0[0xa0];
2065
2066         u8         reserved_1[0x10];
2067         u8         rqt_max_size[0x10];
2068
2069         u8         reserved_2[0x10];
2070         u8         rqt_actual_size[0x10];
2071
2072         u8         reserved_3[0x6a0];
2073
2074         struct mlx5_ifc_rq_num_bits rq_num[0];
2075 };
2076
2077 enum {
2078         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2079         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2080 };
2081
2082 enum {
2083         MLX5_RQC_STATE_RST  = 0x0,
2084         MLX5_RQC_STATE_RDY  = 0x1,
2085         MLX5_RQC_STATE_ERR  = 0x3,
2086 };
2087
2088 struct mlx5_ifc_rqc_bits {
2089         u8         rlky[0x1];
2090         u8         reserved_0[0x2];
2091         u8         vlan_strip_disable[0x1];
2092         u8         mem_rq_type[0x4];
2093         u8         state[0x4];
2094         u8         reserved_1[0x1];
2095         u8         flush_in_error_en[0x1];
2096         u8         reserved_2[0x12];
2097
2098         u8         reserved_3[0x8];
2099         u8         user_index[0x18];
2100
2101         u8         reserved_4[0x8];
2102         u8         cqn[0x18];
2103
2104         u8         counter_set_id[0x8];
2105         u8         reserved_5[0x18];
2106
2107         u8         reserved_6[0x8];
2108         u8         rmpn[0x18];
2109
2110         u8         reserved_7[0xe0];
2111
2112         struct mlx5_ifc_wq_bits wq;
2113 };
2114
2115 enum {
2116         MLX5_RMPC_STATE_RDY  = 0x1,
2117         MLX5_RMPC_STATE_ERR  = 0x3,
2118 };
2119
2120 struct mlx5_ifc_rmpc_bits {
2121         u8         reserved_0[0x8];
2122         u8         state[0x4];
2123         u8         reserved_1[0x14];
2124
2125         u8         basic_cyclic_rcv_wqe[0x1];
2126         u8         reserved_2[0x1f];
2127
2128         u8         reserved_3[0x140];
2129
2130         struct mlx5_ifc_wq_bits wq;
2131 };
2132
2133 enum {
2134         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2135         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2136         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2137 };
2138
2139 struct mlx5_ifc_nic_vport_context_bits {
2140         u8         reserved_0[0x5];
2141         u8         min_wqe_inline_mode[0x3];
2142         u8         reserved_1[0x17];
2143         u8         roce_en[0x1];
2144
2145         u8         arm_change_event[0x1];
2146         u8         reserved_2[0x1a];
2147         u8         event_on_mtu[0x1];
2148         u8         event_on_promisc_change[0x1];
2149         u8         event_on_vlan_change[0x1];
2150         u8         event_on_mc_address_change[0x1];
2151         u8         event_on_uc_address_change[0x1];
2152
2153         u8         reserved_3[0xe0];
2154
2155         u8         reserved_4[0x10];
2156         u8         mtu[0x10];
2157
2158         u8         system_image_guid[0x40];
2159
2160         u8         port_guid[0x40];
2161
2162         u8         node_guid[0x40];
2163
2164         u8         reserved_5[0x140];
2165
2166         u8         qkey_violation_counter[0x10];
2167         u8         reserved_6[0x10];
2168
2169         u8         reserved_7[0x420];
2170
2171         u8         promisc_uc[0x1];
2172         u8         promisc_mc[0x1];
2173         u8         promisc_all[0x1];
2174         u8         reserved_8[0x2];
2175         u8         allowed_list_type[0x3];
2176         u8         reserved_9[0xc];
2177         u8         allowed_list_size[0xc];
2178
2179         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2180
2181         u8         reserved_10[0x20];
2182
2183         u8         current_uc_mac_address[0][0x40];
2184 };
2185
2186 enum {
2187         MLX5_ACCESS_MODE_PA        = 0x0,
2188         MLX5_ACCESS_MODE_MTT       = 0x1,
2189         MLX5_ACCESS_MODE_KLM       = 0x2,
2190 };
2191
2192 struct mlx5_ifc_mkc_bits {
2193         u8         reserved_0[0x1];
2194         u8         free[0x1];
2195         u8         reserved_1[0xd];
2196         u8         small_fence_on_rdma_read_response[0x1];
2197         u8         umr_en[0x1];
2198         u8         a[0x1];
2199         u8         rw[0x1];
2200         u8         rr[0x1];
2201         u8         lw[0x1];
2202         u8         lr[0x1];
2203         u8         access_mode[0x2];
2204         u8         reserved_2[0x8];
2205
2206         u8         qpn[0x18];
2207         u8         mkey_7_0[0x8];
2208
2209         u8         reserved_3[0x20];
2210
2211         u8         length64[0x1];
2212         u8         bsf_en[0x1];
2213         u8         sync_umr[0x1];
2214         u8         reserved_4[0x2];
2215         u8         expected_sigerr_count[0x1];
2216         u8         reserved_5[0x1];
2217         u8         en_rinval[0x1];
2218         u8         pd[0x18];
2219
2220         u8         start_addr[0x40];
2221
2222         u8         len[0x40];
2223
2224         u8         bsf_octword_size[0x20];
2225
2226         u8         reserved_6[0x80];
2227
2228         u8         translations_octword_size[0x20];
2229
2230         u8         reserved_7[0x1b];
2231         u8         log_page_size[0x5];
2232
2233         u8         reserved_8[0x20];
2234 };
2235
2236 struct mlx5_ifc_pkey_bits {
2237         u8         reserved_0[0x10];
2238         u8         pkey[0x10];
2239 };
2240
2241 struct mlx5_ifc_array128_auto_bits {
2242         u8         array128_auto[16][0x8];
2243 };
2244
2245 enum {
2246         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2247         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2248         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2249 };
2250
2251 enum {
2252         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2253         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2254         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2255         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2256         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2257         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2258         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2259 };
2260
2261 enum {
2262         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2263         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2264         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2265 };
2266
2267 enum {
2268         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2269         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2270         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2271         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2272 };
2273
2274 enum {
2275         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2276         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2277         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2278         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2279 };
2280
2281 struct mlx5_ifc_hca_vport_context_bits {
2282         u8         field_select[0x20];
2283
2284         u8         reserved_0[0xe0];
2285
2286         u8         sm_virt_aware[0x1];
2287         u8         has_smi[0x1];
2288         u8         has_raw[0x1];
2289         u8         grh_required[0x1];
2290         u8         reserved_1[0x1];
2291         u8         min_wqe_inline_mode[0x3];
2292         u8         reserved_2[0x8];
2293         u8         port_physical_state[0x4];
2294         u8         vport_state_policy[0x4];
2295         u8         port_state[0x4];
2296         u8         vport_state[0x4];
2297
2298         u8         reserved_3[0x20];
2299
2300         u8         system_image_guid[0x40];
2301
2302         u8         port_guid[0x40];
2303
2304         u8         node_guid[0x40];
2305
2306         u8         cap_mask1[0x20];
2307
2308         u8         cap_mask1_field_select[0x20];
2309
2310         u8         cap_mask2[0x20];
2311
2312         u8         cap_mask2_field_select[0x20];
2313
2314         u8         reserved_4[0x80];
2315
2316         u8         lid[0x10];
2317         u8         reserved_5[0x4];
2318         u8         init_type_reply[0x4];
2319         u8         lmc[0x3];
2320         u8         subnet_timeout[0x5];
2321
2322         u8         sm_lid[0x10];
2323         u8         sm_sl[0x4];
2324         u8         reserved_6[0xc];
2325
2326         u8         qkey_violation_counter[0x10];
2327         u8         pkey_violation_counter[0x10];
2328
2329         u8         reserved_7[0xca0];
2330 };
2331
2332 union mlx5_ifc_hca_cap_union_bits {
2333         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2334         struct mlx5_ifc_odp_cap_bits odp_cap;
2335         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2336         struct mlx5_ifc_roce_cap_bits roce_cap;
2337         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2338         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2339         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2340         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2341         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2342         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2343         struct mlx5_ifc_qos_cap_bits qos_cap;
2344         u8         reserved_0[0x8000];
2345 };
2346
2347 struct mlx5_ifc_esw_vport_context_bits {
2348         u8         reserved_0[0x3];
2349         u8         vport_svlan_strip[0x1];
2350         u8         vport_cvlan_strip[0x1];
2351         u8         vport_svlan_insert[0x1];
2352         u8         vport_cvlan_insert[0x2];
2353         u8         reserved_1[0x18];
2354
2355         u8         reserved_2[0x20];
2356
2357         u8         svlan_cfi[0x1];
2358         u8         svlan_pcp[0x3];
2359         u8         svlan_id[0xc];
2360         u8         cvlan_cfi[0x1];
2361         u8         cvlan_pcp[0x3];
2362         u8         cvlan_id[0xc];
2363
2364         u8         reserved_3[0x7a0];
2365 };
2366
2367 enum {
2368         MLX5_EQC_STATUS_OK                = 0x0,
2369         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2370 };
2371
2372 enum {
2373         MLX5_EQ_STATE_ARMED = 0x9,
2374         MLX5_EQ_STATE_FIRED = 0xa,
2375 };
2376
2377 struct mlx5_ifc_eqc_bits {
2378         u8         status[0x4];
2379         u8         reserved_0[0x9];
2380         u8         ec[0x1];
2381         u8         oi[0x1];
2382         u8         reserved_1[0x5];
2383         u8         st[0x4];
2384         u8         reserved_2[0x8];
2385
2386         u8         reserved_3[0x20];
2387
2388         u8         reserved_4[0x14];
2389         u8         page_offset[0x6];
2390         u8         reserved_5[0x6];
2391
2392         u8         reserved_6[0x3];
2393         u8         log_eq_size[0x5];
2394         u8         uar_page[0x18];
2395
2396         u8         reserved_7[0x20];
2397
2398         u8         reserved_8[0x18];
2399         u8         intr[0x8];
2400
2401         u8         reserved_9[0x3];
2402         u8         log_page_size[0x5];
2403         u8         reserved_10[0x18];
2404
2405         u8         reserved_11[0x60];
2406
2407         u8         reserved_12[0x8];
2408         u8         consumer_counter[0x18];
2409
2410         u8         reserved_13[0x8];
2411         u8         producer_counter[0x18];
2412
2413         u8         reserved_14[0x80];
2414 };
2415
2416 enum {
2417         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2418         MLX5_DCTC_STATE_DRAINING  = 0x1,
2419         MLX5_DCTC_STATE_DRAINED   = 0x2,
2420 };
2421
2422 enum {
2423         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2424         MLX5_DCTC_CS_RES_NA         = 0x1,
2425         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2426 };
2427
2428 enum {
2429         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2430         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2431         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2432         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2433         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2434 };
2435
2436 struct mlx5_ifc_dctc_bits {
2437         u8         reserved_0[0x4];
2438         u8         state[0x4];
2439         u8         reserved_1[0x18];
2440
2441         u8         reserved_2[0x8];
2442         u8         user_index[0x18];
2443
2444         u8         reserved_3[0x8];
2445         u8         cqn[0x18];
2446
2447         u8         counter_set_id[0x8];
2448         u8         atomic_mode[0x4];
2449         u8         rre[0x1];
2450         u8         rwe[0x1];
2451         u8         rae[0x1];
2452         u8         atomic_like_write_en[0x1];
2453         u8         latency_sensitive[0x1];
2454         u8         rlky[0x1];
2455         u8         reserved_4[0xe];
2456
2457         u8         reserved_5[0x8];
2458         u8         cs_res[0x8];
2459         u8         reserved_6[0x3];
2460         u8         min_rnr_nak[0x5];
2461         u8         reserved_7[0x8];
2462
2463         u8         reserved_8[0x8];
2464         u8         srqn[0x18];
2465
2466         u8         reserved_9[0x8];
2467         u8         pd[0x18];
2468
2469         u8         tclass[0x8];
2470         u8         reserved_10[0x4];
2471         u8         flow_label[0x14];
2472
2473         u8         dc_access_key[0x40];
2474
2475         u8         reserved_11[0x5];
2476         u8         mtu[0x3];
2477         u8         port[0x8];
2478         u8         pkey_index[0x10];
2479
2480         u8         reserved_12[0x8];
2481         u8         my_addr_index[0x8];
2482         u8         reserved_13[0x8];
2483         u8         hop_limit[0x8];
2484
2485         u8         dc_access_key_violation_count[0x20];
2486
2487         u8         reserved_14[0x14];
2488         u8         dei_cfi[0x1];
2489         u8         eth_prio[0x3];
2490         u8         ecn[0x2];
2491         u8         dscp[0x6];
2492
2493         u8         reserved_15[0x40];
2494 };
2495
2496 enum {
2497         MLX5_CQC_STATUS_OK             = 0x0,
2498         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2499         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2500 };
2501
2502 enum {
2503         CQE_SIZE_64                = 0x0,
2504         CQE_SIZE_128               = 0x1,
2505 };
2506
2507 enum {
2508         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2509         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2510 };
2511
2512 enum {
2513         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2514         MLX5_CQ_STATE_ARMED                               = 0x9,
2515         MLX5_CQ_STATE_FIRED                               = 0xa,
2516 };
2517
2518 struct mlx5_ifc_cqc_bits {
2519         u8         status[0x4];
2520         u8         reserved_0[0x4];
2521         u8         cqe_sz[0x3];
2522         u8         cc[0x1];
2523         u8         reserved_1[0x1];
2524         u8         scqe_break_moderation_en[0x1];
2525         u8         oi[0x1];
2526         u8         cq_period_mode[0x2];
2527         u8         cqe_compression_en[0x1];
2528         u8         mini_cqe_res_format[0x2];
2529         u8         st[0x4];
2530         u8         reserved_2[0x8];
2531
2532         u8         reserved_3[0x20];
2533
2534         u8         reserved_4[0x14];
2535         u8         page_offset[0x6];
2536         u8         reserved_5[0x6];
2537
2538         u8         reserved_6[0x3];
2539         u8         log_cq_size[0x5];
2540         u8         uar_page[0x18];
2541
2542         u8         reserved_7[0x4];
2543         u8         cq_period[0xc];
2544         u8         cq_max_count[0x10];
2545
2546         u8         reserved_8[0x18];
2547         u8         c_eqn[0x8];
2548
2549         u8         reserved_9[0x3];
2550         u8         log_page_size[0x5];
2551         u8         reserved_10[0x18];
2552
2553         u8         reserved_11[0x20];
2554
2555         u8         reserved_12[0x8];
2556         u8         last_notified_index[0x18];
2557
2558         u8         reserved_13[0x8];
2559         u8         last_solicit_index[0x18];
2560
2561         u8         reserved_14[0x8];
2562         u8         consumer_counter[0x18];
2563
2564         u8         reserved_15[0x8];
2565         u8         producer_counter[0x18];
2566
2567         u8         reserved_16[0x40];
2568
2569         u8         dbr_addr[0x40];
2570 };
2571
2572 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2573         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2574         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2575         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2576         u8         reserved_0[0x800];
2577 };
2578
2579 struct mlx5_ifc_query_adapter_param_block_bits {
2580         u8         reserved_0[0xc0];
2581
2582         u8         reserved_1[0x8];
2583         u8         ieee_vendor_id[0x18];
2584
2585         u8         reserved_2[0x10];
2586         u8         vsd_vendor_id[0x10];
2587
2588         u8         vsd[208][0x8];
2589
2590         u8         vsd_contd_psid[16][0x8];
2591 };
2592
2593 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2594         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2595         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2596         u8         reserved_0[0x20];
2597 };
2598
2599 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2600         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2601         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2602         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2603         u8         reserved_0[0x20];
2604 };
2605
2606 struct mlx5_ifc_bufferx_reg_bits {
2607         u8         reserved_0[0x6];
2608         u8         lossy[0x1];
2609         u8         epsb[0x1];
2610         u8         reserved_1[0xc];
2611         u8         size[0xc];
2612
2613         u8         xoff_threshold[0x10];
2614         u8         xon_threshold[0x10];
2615 };
2616
2617 struct mlx5_ifc_config_item_bits {
2618         u8         valid[0x2];
2619         u8         reserved_0[0x2];
2620         u8         header_type[0x2];
2621         u8         reserved_1[0x2];
2622         u8         default_location[0x1];
2623         u8         reserved_2[0x7];
2624         u8         version[0x4];
2625         u8         reserved_3[0x3];
2626         u8         length[0x9];
2627
2628         u8         type[0x20];
2629
2630         u8         reserved_4[0x10];
2631         u8         crc16[0x10];
2632 };
2633
2634 struct mlx5_ifc_nodnic_port_config_reg_bits {
2635         struct mlx5_ifc_nodnic_event_word_bits event;
2636
2637         u8         network_en[0x1];
2638         u8         dma_en[0x1];
2639         u8         promisc_en[0x1];
2640         u8         promisc_multicast_en[0x1];
2641         u8         reserved_0[0x17];
2642         u8         receive_filter_en[0x5];
2643
2644         u8         reserved_1[0x10];
2645         u8         mac_47_32[0x10];
2646
2647         u8         mac_31_0[0x20];
2648
2649         u8         receive_filters_mgid_mac[64][0x8];
2650
2651         u8         gid[16][0x8];
2652
2653         u8         reserved_2[0x10];
2654         u8         lid[0x10];
2655
2656         u8         reserved_3[0xc];
2657         u8         sm_sl[0x4];
2658         u8         sm_lid[0x10];
2659
2660         u8         completion_address_63_32[0x20];
2661
2662         u8         completion_address_31_12[0x14];
2663         u8         reserved_4[0x6];
2664         u8         log_cq_size[0x6];
2665
2666         u8         working_buffer_address_63_32[0x20];
2667
2668         u8         working_buffer_address_31_12[0x14];
2669         u8         reserved_5[0xc];
2670
2671         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2672
2673         u8         pkey_index[0x10];
2674         u8         pkey[0x10];
2675
2676         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2677
2678         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2679
2680         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2681
2682         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2683
2684         u8         reserved_6[0x400];
2685 };
2686
2687 union mlx5_ifc_event_auto_bits {
2688         struct mlx5_ifc_comp_event_bits comp_event;
2689         struct mlx5_ifc_dct_events_bits dct_events;
2690         struct mlx5_ifc_qp_events_bits qp_events;
2691         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2692         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2693         struct mlx5_ifc_cq_error_bits cq_error;
2694         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2695         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2696         struct mlx5_ifc_gpio_event_bits gpio_event;
2697         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2698         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2699         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2700         struct mlx5_ifc_pages_req_event_bits pages_req_event;
2701         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2702         u8         reserved_0[0xe0];
2703 };
2704
2705 struct mlx5_ifc_health_buffer_bits {
2706         u8         reserved_0[0x100];
2707
2708         u8         assert_existptr[0x20];
2709
2710         u8         assert_callra[0x20];
2711
2712         u8         reserved_1[0x40];
2713
2714         u8         fw_version[0x20];
2715
2716         u8         hw_id[0x20];
2717
2718         u8         reserved_2[0x20];
2719
2720         u8         irisc_index[0x8];
2721         u8         synd[0x8];
2722         u8         ext_synd[0x10];
2723 };
2724
2725 struct mlx5_ifc_register_loopback_control_bits {
2726         u8         no_lb[0x1];
2727         u8         reserved_0[0x7];
2728         u8         port[0x8];
2729         u8         reserved_1[0x10];
2730
2731         u8         reserved_2[0x60];
2732 };
2733
2734 struct mlx5_ifc_lrh_bits {
2735         u8      vl[4];
2736         u8      lver[4];
2737         u8      sl[4];
2738         u8      reserved2[2];
2739         u8      lnh[2];
2740         u8      dlid[16];
2741         u8      reserved5[5];
2742         u8      pkt_len[11];
2743         u8      slid[16];
2744 };
2745
2746 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
2747         u8         reserved_0[0x40];
2748
2749         u8         reserved_1[0x10];
2750         u8         rol_mode[0x8];
2751         u8         wol_mode[0x8];
2752 };
2753
2754 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
2755         u8         reserved_0[0x40];
2756
2757         u8         rol_mode_valid[0x1];
2758         u8         wol_mode_valid[0x1];
2759         u8         reserved_1[0xe];
2760         u8         rol_mode[0x8];
2761         u8         wol_mode[0x8];
2762
2763         u8         reserved_2[0x7a0];
2764 };
2765
2766 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
2767         u8         virtual_mac_en[0x1];
2768         u8         mac_aux_v[0x1];
2769         u8         reserved_0[0x1e];
2770
2771         u8         reserved_1[0x40];
2772
2773         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2774
2775         u8         reserved_2[0x760];
2776 };
2777
2778 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
2779         u8         virtual_mac_en[0x1];
2780         u8         mac_aux_v[0x1];
2781         u8         reserved_0[0x1e];
2782
2783         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
2784
2785         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2786
2787         u8         reserved_1[0x760];
2788 };
2789
2790 struct mlx5_ifc_icmd_query_fw_info_out_bits {
2791         struct mlx5_ifc_fw_version_bits fw_version;
2792
2793         u8         reserved_0[0x10];
2794         u8         hash_signature[0x10];
2795
2796         u8         psid[16][0x8];
2797
2798         u8         reserved_1[0x6e0];
2799 };
2800
2801 struct mlx5_ifc_icmd_query_cap_in_bits {
2802         u8         reserved_0[0x10];
2803         u8         capability_group[0x10];
2804 };
2805
2806 struct mlx5_ifc_icmd_query_cap_general_bits {
2807         u8         nv_access[0x1];
2808         u8         fw_info_psid[0x1];
2809         u8         reserved_0[0x1e];
2810
2811         u8         reserved_1[0x16];
2812         u8         rol_s[0x1];
2813         u8         rol_g[0x1];
2814         u8         reserved_2[0x1];
2815         u8         wol_s[0x1];
2816         u8         wol_g[0x1];
2817         u8         wol_a[0x1];
2818         u8         wol_b[0x1];
2819         u8         wol_m[0x1];
2820         u8         wol_u[0x1];
2821         u8         wol_p[0x1];
2822 };
2823
2824 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
2825         u8         status[0x8];
2826         u8         reserved_0[0x18];
2827
2828         u8         reserved_1[0x7e0];
2829 };
2830
2831 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
2832         u8         status[0x8];
2833         u8         reserved_0[0x18];
2834
2835         u8         reserved_1[0x7e0];
2836 };
2837
2838 struct mlx5_ifc_icmd_ocbb_init_in_bits {
2839         u8         address_hi[0x20];
2840
2841         u8         address_lo[0x20];
2842
2843         u8         reserved_0[0x7c0];
2844 };
2845
2846 struct mlx5_ifc_icmd_init_ocsd_in_bits {
2847         u8         reserved_0[0x20];
2848
2849         u8         address_hi[0x20];
2850
2851         u8         address_lo[0x20];
2852
2853         u8         reserved_1[0x7a0];
2854 };
2855
2856 struct mlx5_ifc_icmd_access_reg_out_bits {
2857         u8         reserved_0[0x11];
2858         u8         status[0x7];
2859         u8         reserved_1[0x8];
2860
2861         u8         register_id[0x10];
2862         u8         reserved_2[0x10];
2863
2864         u8         reserved_3[0x40];
2865
2866         u8         reserved_4[0x5];
2867         u8         len[0xb];
2868         u8         reserved_5[0x10];
2869
2870         u8         register_data[0][0x20];
2871 };
2872
2873 enum {
2874         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
2875         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
2876 };
2877
2878 struct mlx5_ifc_icmd_access_reg_in_bits {
2879         u8         constant_1[0x5];
2880         u8         constant_2[0xb];
2881         u8         reserved_0[0x10];
2882
2883         u8         register_id[0x10];
2884         u8         reserved_1[0x1];
2885         u8         method[0x7];
2886         u8         constant_3[0x8];
2887
2888         u8         reserved_2[0x40];
2889
2890         u8         constant_4[0x5];
2891         u8         len[0xb];
2892         u8         reserved_3[0x10];
2893
2894         u8         register_data[0][0x20];
2895 };
2896
2897 struct mlx5_ifc_teardown_hca_out_bits {
2898         u8         status[0x8];
2899         u8         reserved_0[0x18];
2900
2901         u8         syndrome[0x20];
2902
2903         u8         reserved_1[0x40];
2904 };
2905
2906 enum {
2907         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2908         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2909 };
2910
2911 struct mlx5_ifc_teardown_hca_in_bits {
2912         u8         opcode[0x10];
2913         u8         reserved_0[0x10];
2914
2915         u8         reserved_1[0x10];
2916         u8         op_mod[0x10];
2917
2918         u8         reserved_2[0x10];
2919         u8         profile[0x10];
2920
2921         u8         reserved_3[0x20];
2922 };
2923
2924 struct mlx5_ifc_suspend_qp_out_bits {
2925         u8         status[0x8];
2926         u8         reserved_0[0x18];
2927
2928         u8         syndrome[0x20];
2929
2930         u8         reserved_1[0x40];
2931 };
2932
2933 struct mlx5_ifc_suspend_qp_in_bits {
2934         u8         opcode[0x10];
2935         u8         reserved_0[0x10];
2936
2937         u8         reserved_1[0x10];
2938         u8         op_mod[0x10];
2939
2940         u8         reserved_2[0x8];
2941         u8         qpn[0x18];
2942
2943         u8         reserved_3[0x20];
2944 };
2945
2946 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2947         u8         status[0x8];
2948         u8         reserved_0[0x18];
2949
2950         u8         syndrome[0x20];
2951
2952         u8         reserved_1[0x40];
2953 };
2954
2955 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2956         u8         opcode[0x10];
2957         u8         reserved_0[0x10];
2958
2959         u8         reserved_1[0x10];
2960         u8         op_mod[0x10];
2961
2962         u8         reserved_2[0x8];
2963         u8         qpn[0x18];
2964
2965         u8         reserved_3[0x20];
2966
2967         u8         opt_param_mask[0x20];
2968
2969         u8         reserved_4[0x20];
2970
2971         struct mlx5_ifc_qpc_bits qpc;
2972
2973         u8         reserved_5[0x80];
2974 };
2975
2976 struct mlx5_ifc_sqd2rts_qp_out_bits {
2977         u8         status[0x8];
2978         u8         reserved_0[0x18];
2979
2980         u8         syndrome[0x20];
2981
2982         u8         reserved_1[0x40];
2983 };
2984
2985 struct mlx5_ifc_sqd2rts_qp_in_bits {
2986         u8         opcode[0x10];
2987         u8         reserved_0[0x10];
2988
2989         u8         reserved_1[0x10];
2990         u8         op_mod[0x10];
2991
2992         u8         reserved_2[0x8];
2993         u8         qpn[0x18];
2994
2995         u8         reserved_3[0x20];
2996
2997         u8         opt_param_mask[0x20];
2998
2999         u8         reserved_4[0x20];
3000
3001         struct mlx5_ifc_qpc_bits qpc;
3002
3003         u8         reserved_5[0x80];
3004 };
3005
3006 struct mlx5_ifc_set_wol_rol_out_bits {
3007         u8         status[0x8];
3008         u8         reserved_0[0x18];
3009
3010         u8         syndrome[0x20];
3011
3012         u8         reserved_1[0x40];
3013 };
3014
3015 struct mlx5_ifc_set_wol_rol_in_bits {
3016         u8         opcode[0x10];
3017         u8         reserved_0[0x10];
3018
3019         u8         reserved_1[0x10];
3020         u8         op_mod[0x10];
3021
3022         u8         rol_mode_valid[0x1];
3023         u8         wol_mode_valid[0x1];
3024         u8         reserved_2[0xe];
3025         u8         rol_mode[0x8];
3026         u8         wol_mode[0x8];
3027
3028         u8         reserved_3[0x20];
3029 };
3030
3031 struct mlx5_ifc_set_roce_address_out_bits {
3032         u8         status[0x8];
3033         u8         reserved_0[0x18];
3034
3035         u8         syndrome[0x20];
3036
3037         u8         reserved_1[0x40];
3038 };
3039
3040 struct mlx5_ifc_set_roce_address_in_bits {
3041         u8         opcode[0x10];
3042         u8         reserved_0[0x10];
3043
3044         u8         reserved_1[0x10];
3045         u8         op_mod[0x10];
3046
3047         u8         roce_address_index[0x10];
3048         u8         reserved_2[0x10];
3049
3050         u8         reserved_3[0x20];
3051
3052         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3053 };
3054
3055 struct mlx5_ifc_set_rdb_out_bits {
3056         u8         status[0x8];
3057         u8         reserved_0[0x18];
3058
3059         u8         syndrome[0x20];
3060
3061         u8         reserved_1[0x40];
3062 };
3063
3064 struct mlx5_ifc_set_rdb_in_bits {
3065         u8         opcode[0x10];
3066         u8         reserved_0[0x10];
3067
3068         u8         reserved_1[0x10];
3069         u8         op_mod[0x10];
3070
3071         u8         reserved_2[0x8];
3072         u8         qpn[0x18];
3073
3074         u8         reserved_3[0x18];
3075         u8         rdb_list_size[0x8];
3076
3077         struct mlx5_ifc_rdbc_bits rdb_context[0];
3078 };
3079
3080 struct mlx5_ifc_set_mad_demux_out_bits {
3081         u8         status[0x8];
3082         u8         reserved_0[0x18];
3083
3084         u8         syndrome[0x20];
3085
3086         u8         reserved_1[0x40];
3087 };
3088
3089 enum {
3090         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3091         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3092 };
3093
3094 struct mlx5_ifc_set_mad_demux_in_bits {
3095         u8         opcode[0x10];
3096         u8         reserved_0[0x10];
3097
3098         u8         reserved_1[0x10];
3099         u8         op_mod[0x10];
3100
3101         u8         reserved_2[0x20];
3102
3103         u8         reserved_3[0x6];
3104         u8         demux_mode[0x2];
3105         u8         reserved_4[0x18];
3106 };
3107
3108 struct mlx5_ifc_set_l2_table_entry_out_bits {
3109         u8         status[0x8];
3110         u8         reserved_0[0x18];
3111
3112         u8         syndrome[0x20];
3113
3114         u8         reserved_1[0x40];
3115 };
3116
3117 struct mlx5_ifc_set_l2_table_entry_in_bits {
3118         u8         opcode[0x10];
3119         u8         reserved_0[0x10];
3120
3121         u8         reserved_1[0x10];
3122         u8         op_mod[0x10];
3123
3124         u8         reserved_2[0x60];
3125
3126         u8         reserved_3[0x8];
3127         u8         table_index[0x18];
3128
3129         u8         reserved_4[0x20];
3130
3131         u8         reserved_5[0x13];
3132         u8         vlan_valid[0x1];
3133         u8         vlan[0xc];
3134
3135         struct mlx5_ifc_mac_address_layout_bits mac_address;
3136
3137         u8         reserved_6[0xc0];
3138 };
3139
3140 struct mlx5_ifc_set_issi_out_bits {
3141         u8         status[0x8];
3142         u8         reserved_0[0x18];
3143
3144         u8         syndrome[0x20];
3145
3146         u8         reserved_1[0x40];
3147 };
3148
3149 struct mlx5_ifc_set_issi_in_bits {
3150         u8         opcode[0x10];
3151         u8         reserved_0[0x10];
3152
3153         u8         reserved_1[0x10];
3154         u8         op_mod[0x10];
3155
3156         u8         reserved_2[0x10];
3157         u8         current_issi[0x10];
3158
3159         u8         reserved_3[0x20];
3160 };
3161
3162 struct mlx5_ifc_set_hca_cap_out_bits {
3163         u8         status[0x8];
3164         u8         reserved_0[0x18];
3165
3166         u8         syndrome[0x20];
3167
3168         u8         reserved_1[0x40];
3169 };
3170
3171 struct mlx5_ifc_set_hca_cap_in_bits {
3172         u8         opcode[0x10];
3173         u8         reserved_0[0x10];
3174
3175         u8         reserved_1[0x10];
3176         u8         op_mod[0x10];
3177
3178         u8         reserved_2[0x40];
3179
3180         union mlx5_ifc_hca_cap_union_bits capability;
3181 };
3182
3183 enum {
3184         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3185         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3186         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3187         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3188 };
3189
3190 struct mlx5_ifc_set_flow_table_root_out_bits {
3191         u8         status[0x8];
3192         u8         reserved_0[0x18];
3193
3194         u8         syndrome[0x20];
3195
3196         u8         reserved_1[0x40];
3197 };
3198
3199 struct mlx5_ifc_set_flow_table_root_in_bits {
3200         u8         opcode[0x10];
3201         u8         reserved_0[0x10];
3202
3203         u8         reserved_1[0x10];
3204         u8         op_mod[0x10];
3205
3206         u8         other_vport[0x1];
3207         u8         reserved_2[0xf];
3208         u8         vport_number[0x10];
3209
3210         u8         reserved_3[0x20];
3211
3212         u8         table_type[0x8];
3213         u8         reserved_4[0x18];
3214
3215         u8         reserved_5[0x8];
3216         u8         table_id[0x18];
3217
3218         u8         reserved_6[0x8];
3219         u8         underlay_qpn[0x18];
3220
3221         u8         reserved_7[0x120];
3222 };
3223
3224 struct mlx5_ifc_set_fte_out_bits {
3225         u8         status[0x8];
3226         u8         reserved_0[0x18];
3227
3228         u8         syndrome[0x20];
3229
3230         u8         reserved_1[0x40];
3231 };
3232
3233 struct mlx5_ifc_set_fte_in_bits {
3234         u8         opcode[0x10];
3235         u8         reserved_0[0x10];
3236
3237         u8         reserved_1[0x10];
3238         u8         op_mod[0x10];
3239
3240         u8         other_vport[0x1];
3241         u8         reserved_2[0xf];
3242         u8         vport_number[0x10];
3243
3244         u8         reserved_3[0x20];
3245
3246         u8         table_type[0x8];
3247         u8         reserved_4[0x18];
3248
3249         u8         reserved_5[0x8];
3250         u8         table_id[0x18];
3251
3252         u8         reserved_6[0x18];
3253         u8         modify_enable_mask[0x8];
3254
3255         u8         reserved_7[0x20];
3256
3257         u8         flow_index[0x20];
3258
3259         u8         reserved_8[0xe0];
3260
3261         struct mlx5_ifc_flow_context_bits flow_context;
3262 };
3263
3264 struct mlx5_ifc_set_driver_version_out_bits {
3265         u8         status[0x8];
3266         u8         reserved_0[0x18];
3267
3268         u8         syndrome[0x20];
3269
3270         u8         reserved_1[0x40];
3271 };
3272
3273 struct mlx5_ifc_set_driver_version_in_bits {
3274         u8         opcode[0x10];
3275         u8         reserved_0[0x10];
3276
3277         u8         reserved_1[0x10];
3278         u8         op_mod[0x10];
3279
3280         u8         reserved_2[0x40];
3281
3282         u8         driver_version[64][0x8];
3283 };
3284
3285 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_0[0x18];
3288
3289         u8         syndrome[0x20];
3290
3291         u8         reserved_1[0x40];
3292 };
3293
3294 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3295         u8         opcode[0x10];
3296         u8         reserved_0[0x10];
3297
3298         u8         reserved_1[0x10];
3299         u8         op_mod[0x10];
3300
3301         u8         enable[0x1];
3302         u8         reserved_2[0x1f];
3303
3304         u8         reserved_3[0x160];
3305
3306         struct mlx5_ifc_cmd_pas_bits pas;
3307 };
3308
3309 struct mlx5_ifc_set_burst_size_out_bits {
3310         u8         status[0x8];
3311         u8         reserved_0[0x18];
3312
3313         u8         syndrome[0x20];
3314
3315         u8         reserved_1[0x40];
3316 };
3317
3318 struct mlx5_ifc_set_burst_size_in_bits {
3319         u8         opcode[0x10];
3320         u8         reserved_0[0x10];
3321
3322         u8         reserved_1[0x10];
3323         u8         op_mod[0x10];
3324
3325         u8         reserved_2[0x20];
3326
3327         u8         reserved_3[0x9];
3328         u8         device_burst_size[0x17];
3329 };
3330
3331 struct mlx5_ifc_rts2rts_qp_out_bits {
3332         u8         status[0x8];
3333         u8         reserved_0[0x18];
3334
3335         u8         syndrome[0x20];
3336
3337         u8         reserved_1[0x40];
3338 };
3339
3340 struct mlx5_ifc_rts2rts_qp_in_bits {
3341         u8         opcode[0x10];
3342         u8         reserved_0[0x10];
3343
3344         u8         reserved_1[0x10];
3345         u8         op_mod[0x10];
3346
3347         u8         reserved_2[0x8];
3348         u8         qpn[0x18];
3349
3350         u8         reserved_3[0x20];
3351
3352         u8         opt_param_mask[0x20];
3353
3354         u8         reserved_4[0x20];
3355
3356         struct mlx5_ifc_qpc_bits qpc;
3357
3358         u8         reserved_5[0x80];
3359 };
3360
3361 struct mlx5_ifc_rtr2rts_qp_out_bits {
3362         u8         status[0x8];
3363         u8         reserved_0[0x18];
3364
3365         u8         syndrome[0x20];
3366
3367         u8         reserved_1[0x40];
3368 };
3369
3370 struct mlx5_ifc_rtr2rts_qp_in_bits {
3371         u8         opcode[0x10];
3372         u8         reserved_0[0x10];
3373
3374         u8         reserved_1[0x10];
3375         u8         op_mod[0x10];
3376
3377         u8         reserved_2[0x8];
3378         u8         qpn[0x18];
3379
3380         u8         reserved_3[0x20];
3381
3382         u8         opt_param_mask[0x20];
3383
3384         u8         reserved_4[0x20];
3385
3386         struct mlx5_ifc_qpc_bits qpc;
3387
3388         u8         reserved_5[0x80];
3389 };
3390
3391 struct mlx5_ifc_rst2init_qp_out_bits {
3392         u8         status[0x8];
3393         u8         reserved_0[0x18];
3394
3395         u8         syndrome[0x20];
3396
3397         u8         reserved_1[0x40];
3398 };
3399
3400 struct mlx5_ifc_rst2init_qp_in_bits {
3401         u8         opcode[0x10];
3402         u8         reserved_0[0x10];
3403
3404         u8         reserved_1[0x10];
3405         u8         op_mod[0x10];
3406
3407         u8         reserved_2[0x8];
3408         u8         qpn[0x18];
3409
3410         u8         reserved_3[0x20];
3411
3412         u8         opt_param_mask[0x20];
3413
3414         u8         reserved_4[0x20];
3415
3416         struct mlx5_ifc_qpc_bits qpc;
3417
3418         u8         reserved_5[0x80];
3419 };
3420
3421 struct mlx5_ifc_resume_qp_out_bits {
3422         u8         status[0x8];
3423         u8         reserved_0[0x18];
3424
3425         u8         syndrome[0x20];
3426
3427         u8         reserved_1[0x40];
3428 };
3429
3430 struct mlx5_ifc_resume_qp_in_bits {
3431         u8         opcode[0x10];
3432         u8         reserved_0[0x10];
3433
3434         u8         reserved_1[0x10];
3435         u8         op_mod[0x10];
3436
3437         u8         reserved_2[0x8];
3438         u8         qpn[0x18];
3439
3440         u8         reserved_3[0x20];
3441 };
3442
3443 struct mlx5_ifc_query_xrc_srq_out_bits {
3444         u8         status[0x8];
3445         u8         reserved_0[0x18];
3446
3447         u8         syndrome[0x20];
3448
3449         u8         reserved_1[0x40];
3450
3451         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3452
3453         u8         reserved_2[0x600];
3454
3455         u8         pas[0][0x40];
3456 };
3457
3458 struct mlx5_ifc_query_xrc_srq_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_0[0x10];
3461
3462         u8         reserved_1[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_2[0x8];
3466         u8         xrc_srqn[0x18];
3467
3468         u8         reserved_3[0x20];
3469 };
3470
3471 struct mlx5_ifc_query_wol_rol_out_bits {
3472         u8         status[0x8];
3473         u8         reserved_0[0x18];
3474
3475         u8         syndrome[0x20];
3476
3477         u8         reserved_1[0x10];
3478         u8         rol_mode[0x8];
3479         u8         wol_mode[0x8];
3480
3481         u8         reserved_2[0x20];
3482 };
3483
3484 struct mlx5_ifc_query_wol_rol_in_bits {
3485         u8         opcode[0x10];
3486         u8         reserved_0[0x10];
3487
3488         u8         reserved_1[0x10];
3489         u8         op_mod[0x10];
3490
3491         u8         reserved_2[0x40];
3492 };
3493
3494 enum {
3495         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3496         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3497 };
3498
3499 struct mlx5_ifc_query_vport_state_out_bits {
3500         u8         status[0x8];
3501         u8         reserved_0[0x18];
3502
3503         u8         syndrome[0x20];
3504
3505         u8         reserved_1[0x20];
3506
3507         u8         reserved_2[0x18];
3508         u8         admin_state[0x4];
3509         u8         state[0x4];
3510 };
3511
3512 enum {
3513         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3514         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3515         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3516 };
3517
3518 struct mlx5_ifc_query_vport_state_in_bits {
3519         u8         opcode[0x10];
3520         u8         reserved_0[0x10];
3521
3522         u8         reserved_1[0x10];
3523         u8         op_mod[0x10];
3524
3525         u8         other_vport[0x1];
3526         u8         reserved_2[0xf];
3527         u8         vport_number[0x10];
3528
3529         u8         reserved_3[0x20];
3530 };
3531
3532 struct mlx5_ifc_query_vport_counter_out_bits {
3533         u8         status[0x8];
3534         u8         reserved_0[0x18];
3535
3536         u8         syndrome[0x20];
3537
3538         u8         reserved_1[0x40];
3539
3540         struct mlx5_ifc_traffic_counter_bits received_errors;
3541
3542         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3543
3544         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3545
3546         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3547
3548         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3549
3550         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3551
3552         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3553
3554         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3555
3556         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3557
3558         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3559
3560         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3561
3562         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3563
3564         u8         reserved_2[0xa00];
3565 };
3566
3567 enum {
3568         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3569 };
3570
3571 struct mlx5_ifc_query_vport_counter_in_bits {
3572         u8         opcode[0x10];
3573         u8         reserved_0[0x10];
3574
3575         u8         reserved_1[0x10];
3576         u8         op_mod[0x10];
3577
3578         u8         other_vport[0x1];
3579         u8         reserved_2[0xb];
3580         u8         port_num[0x4];
3581         u8         vport_number[0x10];
3582
3583         u8         reserved_3[0x60];
3584
3585         u8         clear[0x1];
3586         u8         reserved_4[0x1f];
3587
3588         u8         reserved_5[0x20];
3589 };
3590
3591 struct mlx5_ifc_query_tis_out_bits {
3592         u8         status[0x8];
3593         u8         reserved_0[0x18];
3594
3595         u8         syndrome[0x20];
3596
3597         u8         reserved_1[0x40];
3598
3599         struct mlx5_ifc_tisc_bits tis_context;
3600 };
3601
3602 struct mlx5_ifc_query_tis_in_bits {
3603         u8         opcode[0x10];
3604         u8         reserved_0[0x10];
3605
3606         u8         reserved_1[0x10];
3607         u8         op_mod[0x10];
3608
3609         u8         reserved_2[0x8];
3610         u8         tisn[0x18];
3611
3612         u8         reserved_3[0x20];
3613 };
3614
3615 struct mlx5_ifc_query_tir_out_bits {
3616         u8         status[0x8];
3617         u8         reserved_0[0x18];
3618
3619         u8         syndrome[0x20];
3620
3621         u8         reserved_1[0xc0];
3622
3623         struct mlx5_ifc_tirc_bits tir_context;
3624 };
3625
3626 struct mlx5_ifc_query_tir_in_bits {
3627         u8         opcode[0x10];
3628         u8         reserved_0[0x10];
3629
3630         u8         reserved_1[0x10];
3631         u8         op_mod[0x10];
3632
3633         u8         reserved_2[0x8];
3634         u8         tirn[0x18];
3635
3636         u8         reserved_3[0x20];
3637 };
3638
3639 struct mlx5_ifc_query_srq_out_bits {
3640         u8         status[0x8];
3641         u8         reserved_0[0x18];
3642
3643         u8         syndrome[0x20];
3644
3645         u8         reserved_1[0x40];
3646
3647         struct mlx5_ifc_srqc_bits srq_context_entry;
3648
3649         u8         reserved_2[0x600];
3650
3651         u8         pas[0][0x40];
3652 };
3653
3654 struct mlx5_ifc_query_srq_in_bits {
3655         u8         opcode[0x10];
3656         u8         reserved_0[0x10];
3657
3658         u8         reserved_1[0x10];
3659         u8         op_mod[0x10];
3660
3661         u8         reserved_2[0x8];
3662         u8         srqn[0x18];
3663
3664         u8         reserved_3[0x20];
3665 };
3666
3667 struct mlx5_ifc_query_sq_out_bits {
3668         u8         status[0x8];
3669         u8         reserved_0[0x18];
3670
3671         u8         syndrome[0x20];
3672
3673         u8         reserved_1[0xc0];
3674
3675         struct mlx5_ifc_sqc_bits sq_context;
3676 };
3677
3678 struct mlx5_ifc_query_sq_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_0[0x10];
3681
3682         u8         reserved_1[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         reserved_2[0x8];
3686         u8         sqn[0x18];
3687
3688         u8         reserved_3[0x20];
3689 };
3690
3691 struct mlx5_ifc_query_special_contexts_out_bits {
3692         u8         status[0x8];
3693         u8         reserved_0[0x18];
3694
3695         u8         syndrome[0x20];
3696
3697         u8         reserved_1[0x20];
3698
3699         u8         resd_lkey[0x20];
3700 };
3701
3702 struct mlx5_ifc_query_special_contexts_in_bits {
3703         u8         opcode[0x10];
3704         u8         reserved_0[0x10];
3705
3706         u8         reserved_1[0x10];
3707         u8         op_mod[0x10];
3708
3709         u8         reserved_2[0x40];
3710 };
3711
3712 struct mlx5_ifc_query_rqt_out_bits {
3713         u8         status[0x8];
3714         u8         reserved_0[0x18];
3715
3716         u8         syndrome[0x20];
3717
3718         u8         reserved_1[0xc0];
3719
3720         struct mlx5_ifc_rqtc_bits rqt_context;
3721 };
3722
3723 struct mlx5_ifc_query_rqt_in_bits {
3724         u8         opcode[0x10];
3725         u8         reserved_0[0x10];
3726
3727         u8         reserved_1[0x10];
3728         u8         op_mod[0x10];
3729
3730         u8         reserved_2[0x8];
3731         u8         rqtn[0x18];
3732
3733         u8         reserved_3[0x20];
3734 };
3735
3736 struct mlx5_ifc_query_rq_out_bits {
3737         u8         status[0x8];
3738         u8         reserved_0[0x18];
3739
3740         u8         syndrome[0x20];
3741
3742         u8         reserved_1[0xc0];
3743
3744         struct mlx5_ifc_rqc_bits rq_context;
3745 };
3746
3747 struct mlx5_ifc_query_rq_in_bits {
3748         u8         opcode[0x10];
3749         u8         reserved_0[0x10];
3750
3751         u8         reserved_1[0x10];
3752         u8         op_mod[0x10];
3753
3754         u8         reserved_2[0x8];
3755         u8         rqn[0x18];
3756
3757         u8         reserved_3[0x20];
3758 };
3759
3760 struct mlx5_ifc_query_roce_address_out_bits {
3761         u8         status[0x8];
3762         u8         reserved_0[0x18];
3763
3764         u8         syndrome[0x20];
3765
3766         u8         reserved_1[0x40];
3767
3768         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3769 };
3770
3771 struct mlx5_ifc_query_roce_address_in_bits {
3772         u8         opcode[0x10];
3773         u8         reserved_0[0x10];
3774
3775         u8         reserved_1[0x10];
3776         u8         op_mod[0x10];
3777
3778         u8         roce_address_index[0x10];
3779         u8         reserved_2[0x10];
3780
3781         u8         reserved_3[0x20];
3782 };
3783
3784 struct mlx5_ifc_query_rmp_out_bits {
3785         u8         status[0x8];
3786         u8         reserved_0[0x18];
3787
3788         u8         syndrome[0x20];
3789
3790         u8         reserved_1[0xc0];
3791
3792         struct mlx5_ifc_rmpc_bits rmp_context;
3793 };
3794
3795 struct mlx5_ifc_query_rmp_in_bits {
3796         u8         opcode[0x10];
3797         u8         reserved_0[0x10];
3798
3799         u8         reserved_1[0x10];
3800         u8         op_mod[0x10];
3801
3802         u8         reserved_2[0x8];
3803         u8         rmpn[0x18];
3804
3805         u8         reserved_3[0x20];
3806 };
3807
3808 struct mlx5_ifc_query_rdb_out_bits {
3809         u8         status[0x8];
3810         u8         reserved_0[0x18];
3811
3812         u8         syndrome[0x20];
3813
3814         u8         reserved_1[0x20];
3815
3816         u8         reserved_2[0x18];
3817         u8         rdb_list_size[0x8];
3818
3819         struct mlx5_ifc_rdbc_bits rdb_context[0];
3820 };
3821
3822 struct mlx5_ifc_query_rdb_in_bits {
3823         u8         opcode[0x10];
3824         u8         reserved_0[0x10];
3825
3826         u8         reserved_1[0x10];
3827         u8         op_mod[0x10];
3828
3829         u8         reserved_2[0x8];
3830         u8         qpn[0x18];
3831
3832         u8         reserved_3[0x20];
3833 };
3834
3835 struct mlx5_ifc_query_qp_out_bits {
3836         u8         status[0x8];
3837         u8         reserved_0[0x18];
3838
3839         u8         syndrome[0x20];
3840
3841         u8         reserved_1[0x40];
3842
3843         u8         opt_param_mask[0x20];
3844
3845         u8         reserved_2[0x20];
3846
3847         struct mlx5_ifc_qpc_bits qpc;
3848
3849         u8         reserved_3[0x80];
3850
3851         u8         pas[0][0x40];
3852 };
3853
3854 struct mlx5_ifc_query_qp_in_bits {
3855         u8         opcode[0x10];
3856         u8         reserved_0[0x10];
3857
3858         u8         reserved_1[0x10];
3859         u8         op_mod[0x10];
3860
3861         u8         reserved_2[0x8];
3862         u8         qpn[0x18];
3863
3864         u8         reserved_3[0x20];
3865 };
3866
3867 struct mlx5_ifc_query_q_counter_out_bits {
3868         u8         status[0x8];
3869         u8         reserved_0[0x18];
3870
3871         u8         syndrome[0x20];
3872
3873         u8         reserved_1[0x40];
3874
3875         u8         rx_write_requests[0x20];
3876
3877         u8         reserved_2[0x20];
3878
3879         u8         rx_read_requests[0x20];
3880
3881         u8         reserved_3[0x20];
3882
3883         u8         rx_atomic_requests[0x20];
3884
3885         u8         reserved_4[0x20];
3886
3887         u8         rx_dct_connect[0x20];
3888
3889         u8         reserved_5[0x20];
3890
3891         u8         out_of_buffer[0x20];
3892
3893         u8         reserved_7[0x20];
3894
3895         u8         out_of_sequence[0x20];
3896
3897         u8         reserved_8[0x20];
3898
3899         u8         duplicate_request[0x20];
3900
3901         u8         reserved_9[0x20];
3902
3903         u8         rnr_nak_retry_err[0x20];
3904
3905         u8         reserved_10[0x20];
3906
3907         u8         packet_seq_err[0x20];
3908
3909         u8         reserved_11[0x20];
3910
3911         u8         implied_nak_seq_err[0x20];
3912
3913         u8         reserved_12[0x20];
3914
3915         u8         local_ack_timeout_err[0x20];
3916
3917         u8         reserved_13[0x4e0];
3918 };
3919
3920 struct mlx5_ifc_query_q_counter_in_bits {
3921         u8         opcode[0x10];
3922         u8         reserved_0[0x10];
3923
3924         u8         reserved_1[0x10];
3925         u8         op_mod[0x10];
3926
3927         u8         reserved_2[0x80];
3928
3929         u8         clear[0x1];
3930         u8         reserved_3[0x1f];
3931
3932         u8         reserved_4[0x18];
3933         u8         counter_set_id[0x8];
3934 };
3935
3936 struct mlx5_ifc_query_pages_out_bits {
3937         u8         status[0x8];
3938         u8         reserved_0[0x18];
3939
3940         u8         syndrome[0x20];
3941
3942         u8         reserved_1[0x10];
3943         u8         function_id[0x10];
3944
3945         u8         num_pages[0x20];
3946 };
3947
3948 enum {
3949         MLX5_BOOT_PAGES                           = 0x1,
3950         MLX5_INIT_PAGES                           = 0x2,
3951         MLX5_POST_INIT_PAGES                      = 0x3,
3952 };
3953
3954 struct mlx5_ifc_query_pages_in_bits {
3955         u8         opcode[0x10];
3956         u8         reserved_0[0x10];
3957
3958         u8         reserved_1[0x10];
3959         u8         op_mod[0x10];
3960
3961         u8         reserved_2[0x10];
3962         u8         function_id[0x10];
3963
3964         u8         reserved_3[0x20];
3965 };
3966
3967 struct mlx5_ifc_query_nic_vport_context_out_bits {
3968         u8         status[0x8];
3969         u8         reserved_0[0x18];
3970
3971         u8         syndrome[0x20];
3972
3973         u8         reserved_1[0x40];
3974
3975         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3976 };
3977
3978 struct mlx5_ifc_query_nic_vport_context_in_bits {
3979         u8         opcode[0x10];
3980         u8         reserved_0[0x10];
3981
3982         u8         reserved_1[0x10];
3983         u8         op_mod[0x10];
3984
3985         u8         other_vport[0x1];
3986         u8         reserved_2[0xf];
3987         u8         vport_number[0x10];
3988
3989         u8         reserved_3[0x5];
3990         u8         allowed_list_type[0x3];
3991         u8         reserved_4[0x18];
3992 };
3993
3994 struct mlx5_ifc_query_mkey_out_bits {
3995         u8         status[0x8];
3996         u8         reserved_0[0x18];
3997
3998         u8         syndrome[0x20];
3999
4000         u8         reserved_1[0x40];
4001
4002         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4003
4004         u8         reserved_2[0x600];
4005
4006         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4007
4008         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4009 };
4010
4011 struct mlx5_ifc_query_mkey_in_bits {
4012         u8         opcode[0x10];
4013         u8         reserved_0[0x10];
4014
4015         u8         reserved_1[0x10];
4016         u8         op_mod[0x10];
4017
4018         u8         reserved_2[0x8];
4019         u8         mkey_index[0x18];
4020
4021         u8         pg_access[0x1];
4022         u8         reserved_3[0x1f];
4023 };
4024
4025 struct mlx5_ifc_query_mad_demux_out_bits {
4026         u8         status[0x8];
4027         u8         reserved_0[0x18];
4028
4029         u8         syndrome[0x20];
4030
4031         u8         reserved_1[0x40];
4032
4033         u8         mad_dumux_parameters_block[0x20];
4034 };
4035
4036 struct mlx5_ifc_query_mad_demux_in_bits {
4037         u8         opcode[0x10];
4038         u8         reserved_0[0x10];
4039
4040         u8         reserved_1[0x10];
4041         u8         op_mod[0x10];
4042
4043         u8         reserved_2[0x40];
4044 };
4045
4046 struct mlx5_ifc_query_l2_table_entry_out_bits {
4047         u8         status[0x8];
4048         u8         reserved_0[0x18];
4049
4050         u8         syndrome[0x20];
4051
4052         u8         reserved_1[0xa0];
4053
4054         u8         reserved_2[0x13];
4055         u8         vlan_valid[0x1];
4056         u8         vlan[0xc];
4057
4058         struct mlx5_ifc_mac_address_layout_bits mac_address;
4059
4060         u8         reserved_3[0xc0];
4061 };
4062
4063 struct mlx5_ifc_query_l2_table_entry_in_bits {
4064         u8         opcode[0x10];
4065         u8         reserved_0[0x10];
4066
4067         u8         reserved_1[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_2[0x60];
4071
4072         u8         reserved_3[0x8];
4073         u8         table_index[0x18];
4074
4075         u8         reserved_4[0x140];
4076 };
4077
4078 struct mlx5_ifc_query_issi_out_bits {
4079         u8         status[0x8];
4080         u8         reserved_0[0x18];
4081
4082         u8         syndrome[0x20];
4083
4084         u8         reserved_1[0x10];
4085         u8         current_issi[0x10];
4086
4087         u8         reserved_2[0xa0];
4088
4089         u8         supported_issi_reserved[76][0x8];
4090         u8         supported_issi_dw0[0x20];
4091 };
4092
4093 struct mlx5_ifc_query_issi_in_bits {
4094         u8         opcode[0x10];
4095         u8         reserved_0[0x10];
4096
4097         u8         reserved_1[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         reserved_2[0x40];
4101 };
4102
4103 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4104         u8         status[0x8];
4105         u8         reserved_0[0x18];
4106
4107         u8         syndrome[0x20];
4108
4109         u8         reserved_1[0x40];
4110
4111         struct mlx5_ifc_pkey_bits pkey[0];
4112 };
4113
4114 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4115         u8         opcode[0x10];
4116         u8         reserved_0[0x10];
4117
4118         u8         reserved_1[0x10];
4119         u8         op_mod[0x10];
4120
4121         u8         other_vport[0x1];
4122         u8         reserved_2[0xb];
4123         u8         port_num[0x4];
4124         u8         vport_number[0x10];
4125
4126         u8         reserved_3[0x10];
4127         u8         pkey_index[0x10];
4128 };
4129
4130 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4131         u8         status[0x8];
4132         u8         reserved_0[0x18];
4133
4134         u8         syndrome[0x20];
4135
4136         u8         reserved_1[0x20];
4137
4138         u8         gids_num[0x10];
4139         u8         reserved_2[0x10];
4140
4141         struct mlx5_ifc_array128_auto_bits gid[0];
4142 };
4143
4144 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4145         u8         opcode[0x10];
4146         u8         reserved_0[0x10];
4147
4148         u8         reserved_1[0x10];
4149         u8         op_mod[0x10];
4150
4151         u8         other_vport[0x1];
4152         u8         reserved_2[0xb];
4153         u8         port_num[0x4];
4154         u8         vport_number[0x10];
4155
4156         u8         reserved_3[0x10];
4157         u8         gid_index[0x10];
4158 };
4159
4160 struct mlx5_ifc_query_hca_vport_context_out_bits {
4161         u8         status[0x8];
4162         u8         reserved_0[0x18];
4163
4164         u8         syndrome[0x20];
4165
4166         u8         reserved_1[0x40];
4167
4168         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4169 };
4170
4171 struct mlx5_ifc_query_hca_vport_context_in_bits {
4172         u8         opcode[0x10];
4173         u8         reserved_0[0x10];
4174
4175         u8         reserved_1[0x10];
4176         u8         op_mod[0x10];
4177
4178         u8         other_vport[0x1];
4179         u8         reserved_2[0xb];
4180         u8         port_num[0x4];
4181         u8         vport_number[0x10];
4182
4183         u8         reserved_3[0x20];
4184 };
4185
4186 struct mlx5_ifc_query_hca_cap_out_bits {
4187         u8         status[0x8];
4188         u8         reserved_0[0x18];
4189
4190         u8         syndrome[0x20];
4191
4192         u8         reserved_1[0x40];
4193
4194         union mlx5_ifc_hca_cap_union_bits capability;
4195 };
4196
4197 struct mlx5_ifc_query_hca_cap_in_bits {
4198         u8         opcode[0x10];
4199         u8         reserved_0[0x10];
4200
4201         u8         reserved_1[0x10];
4202         u8         op_mod[0x10];
4203
4204         u8         reserved_2[0x40];
4205 };
4206
4207 struct mlx5_ifc_query_flow_table_out_bits {
4208         u8         status[0x8];
4209         u8         reserved_0[0x18];
4210
4211         u8         syndrome[0x20];
4212
4213         u8         reserved_1[0x80];
4214
4215         u8         reserved_2[0x8];
4216         u8         level[0x8];
4217         u8         reserved_3[0x8];
4218         u8         log_size[0x8];
4219
4220         u8         reserved_4[0x120];
4221 };
4222
4223 struct mlx5_ifc_query_flow_table_in_bits {
4224         u8         opcode[0x10];
4225         u8         reserved_0[0x10];
4226
4227         u8         reserved_1[0x10];
4228         u8         op_mod[0x10];
4229
4230         u8         other_vport[0x1];
4231         u8         reserved_2[0xf];
4232         u8         vport_number[0x10];
4233
4234         u8         reserved_3[0x20];
4235
4236         u8         table_type[0x8];
4237         u8         reserved_4[0x18];
4238
4239         u8         reserved_5[0x8];
4240         u8         table_id[0x18];
4241
4242         u8         reserved_6[0x140];
4243 };
4244
4245 struct mlx5_ifc_query_fte_out_bits {
4246         u8         status[0x8];
4247         u8         reserved_0[0x18];
4248
4249         u8         syndrome[0x20];
4250
4251         u8         reserved_1[0x1c0];
4252
4253         struct mlx5_ifc_flow_context_bits flow_context;
4254 };
4255
4256 struct mlx5_ifc_query_fte_in_bits {
4257         u8         opcode[0x10];
4258         u8         reserved_0[0x10];
4259
4260         u8         reserved_1[0x10];
4261         u8         op_mod[0x10];
4262
4263         u8         other_vport[0x1];
4264         u8         reserved_2[0xf];
4265         u8         vport_number[0x10];
4266
4267         u8         reserved_3[0x20];
4268
4269         u8         table_type[0x8];
4270         u8         reserved_4[0x18];
4271
4272         u8         reserved_5[0x8];
4273         u8         table_id[0x18];
4274
4275         u8         reserved_6[0x40];
4276
4277         u8         flow_index[0x20];
4278
4279         u8         reserved_7[0xe0];
4280 };
4281
4282 enum {
4283         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4284         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4285         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4286 };
4287
4288 struct mlx5_ifc_query_flow_group_out_bits {
4289         u8         status[0x8];
4290         u8         reserved_0[0x18];
4291
4292         u8         syndrome[0x20];
4293
4294         u8         reserved_1[0xa0];
4295
4296         u8         start_flow_index[0x20];
4297
4298         u8         reserved_2[0x20];
4299
4300         u8         end_flow_index[0x20];
4301
4302         u8         reserved_3[0xa0];
4303
4304         u8         reserved_4[0x18];
4305         u8         match_criteria_enable[0x8];
4306
4307         struct mlx5_ifc_fte_match_param_bits match_criteria;
4308
4309         u8         reserved_5[0xe00];
4310 };
4311
4312 struct mlx5_ifc_query_flow_group_in_bits {
4313         u8         opcode[0x10];
4314         u8         reserved_0[0x10];
4315
4316         u8         reserved_1[0x10];
4317         u8         op_mod[0x10];
4318
4319         u8         other_vport[0x1];
4320         u8         reserved_2[0xf];
4321         u8         vport_number[0x10];
4322
4323         u8         reserved_3[0x20];
4324
4325         u8         table_type[0x8];
4326         u8         reserved_4[0x18];
4327
4328         u8         reserved_5[0x8];
4329         u8         table_id[0x18];
4330
4331         u8         group_id[0x20];
4332
4333         u8         reserved_6[0x120];
4334 };
4335
4336 struct mlx5_ifc_query_flow_counter_out_bits {
4337         u8         status[0x8];
4338         u8         reserved_0[0x18];
4339
4340         u8         syndrome[0x20];
4341
4342         u8         reserved_1[0x40];
4343
4344         struct mlx5_ifc_traffic_counter_bits flow_statistics;
4345
4346         u8         reserved_2[0x700];
4347 };
4348
4349 struct mlx5_ifc_query_flow_counter_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_0[0x10];
4352
4353         u8         reserved_1[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         reserved_2[0x80];
4357
4358         u8         clear[0x1];
4359         u8         reserved_3[0x1f];
4360
4361         u8         reserved_4[0x10];
4362         u8         flow_counter_id[0x10];
4363 };
4364
4365 struct mlx5_ifc_query_esw_vport_context_out_bits {
4366         u8         status[0x8];
4367         u8         reserved_0[0x18];
4368
4369         u8         syndrome[0x20];
4370
4371         u8         reserved_1[0x40];
4372
4373         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4374 };
4375
4376 struct mlx5_ifc_query_esw_vport_context_in_bits {
4377         u8         opcode[0x10];
4378         u8         reserved_0[0x10];
4379
4380         u8         reserved_1[0x10];
4381         u8         op_mod[0x10];
4382
4383         u8         other_vport[0x1];
4384         u8         reserved_2[0xf];
4385         u8         vport_number[0x10];
4386
4387         u8         reserved_3[0x20];
4388 };
4389
4390 struct mlx5_ifc_query_eq_out_bits {
4391         u8         status[0x8];
4392         u8         reserved_0[0x18];
4393
4394         u8         syndrome[0x20];
4395
4396         u8         reserved_1[0x40];
4397
4398         struct mlx5_ifc_eqc_bits eq_context_entry;
4399
4400         u8         reserved_2[0x40];
4401
4402         u8         event_bitmask[0x40];
4403
4404         u8         reserved_3[0x580];
4405
4406         u8         pas[0][0x40];
4407 };
4408
4409 struct mlx5_ifc_query_eq_in_bits {
4410         u8         opcode[0x10];
4411         u8         reserved_0[0x10];
4412
4413         u8         reserved_1[0x10];
4414         u8         op_mod[0x10];
4415
4416         u8         reserved_2[0x18];
4417         u8         eq_number[0x8];
4418
4419         u8         reserved_3[0x20];
4420 };
4421
4422 struct mlx5_ifc_query_dct_out_bits {
4423         u8         status[0x8];
4424         u8         reserved_0[0x18];
4425
4426         u8         syndrome[0x20];
4427
4428         u8         reserved_1[0x40];
4429
4430         struct mlx5_ifc_dctc_bits dct_context_entry;
4431
4432         u8         reserved_2[0x180];
4433 };
4434
4435 struct mlx5_ifc_query_dct_in_bits {
4436         u8         opcode[0x10];
4437         u8         reserved_0[0x10];
4438
4439         u8         reserved_1[0x10];
4440         u8         op_mod[0x10];
4441
4442         u8         reserved_2[0x8];
4443         u8         dctn[0x18];
4444
4445         u8         reserved_3[0x20];
4446 };
4447
4448 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4449         u8         status[0x8];
4450         u8         reserved_0[0x18];
4451
4452         u8         syndrome[0x20];
4453
4454         u8         enable[0x1];
4455         u8         reserved_1[0x1f];
4456
4457         u8         reserved_2[0x160];
4458
4459         struct mlx5_ifc_cmd_pas_bits pas;
4460 };
4461
4462 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4463         u8         opcode[0x10];
4464         u8         reserved_0[0x10];
4465
4466         u8         reserved_1[0x10];
4467         u8         op_mod[0x10];
4468
4469         u8         reserved_2[0x40];
4470 };
4471
4472 struct mlx5_ifc_query_cq_out_bits {
4473         u8         status[0x8];
4474         u8         reserved_0[0x18];
4475
4476         u8         syndrome[0x20];
4477
4478         u8         reserved_1[0x40];
4479
4480         struct mlx5_ifc_cqc_bits cq_context;
4481
4482         u8         reserved_2[0x600];
4483
4484         u8         pas[0][0x40];
4485 };
4486
4487 struct mlx5_ifc_query_cq_in_bits {
4488         u8         opcode[0x10];
4489         u8         reserved_0[0x10];
4490
4491         u8         reserved_1[0x10];
4492         u8         op_mod[0x10];
4493
4494         u8         reserved_2[0x8];
4495         u8         cqn[0x18];
4496
4497         u8         reserved_3[0x20];
4498 };
4499
4500 struct mlx5_ifc_query_cong_status_out_bits {
4501         u8         status[0x8];
4502         u8         reserved_0[0x18];
4503
4504         u8         syndrome[0x20];
4505
4506         u8         reserved_1[0x20];
4507
4508         u8         enable[0x1];
4509         u8         tag_enable[0x1];
4510         u8         reserved_2[0x1e];
4511 };
4512
4513 struct mlx5_ifc_query_cong_status_in_bits {
4514         u8         opcode[0x10];
4515         u8         reserved_0[0x10];
4516
4517         u8         reserved_1[0x10];
4518         u8         op_mod[0x10];
4519
4520         u8         reserved_2[0x18];
4521         u8         priority[0x4];
4522         u8         cong_protocol[0x4];
4523
4524         u8         reserved_3[0x20];
4525 };
4526
4527 struct mlx5_ifc_query_cong_statistics_out_bits {
4528         u8         status[0x8];
4529         u8         reserved_0[0x18];
4530
4531         u8         syndrome[0x20];
4532
4533         u8         reserved_1[0x40];
4534
4535         u8         cur_flows[0x20];
4536
4537         u8         sum_flows[0x20];
4538
4539         u8         cnp_ignored_high[0x20];
4540
4541         u8         cnp_ignored_low[0x20];
4542
4543         u8         cnp_handled_high[0x20];
4544
4545         u8         cnp_handled_low[0x20];
4546
4547         u8         reserved_2[0x100];
4548
4549         u8         time_stamp_high[0x20];
4550
4551         u8         time_stamp_low[0x20];
4552
4553         u8         accumulators_period[0x20];
4554
4555         u8         ecn_marked_roce_packets_high[0x20];
4556
4557         u8         ecn_marked_roce_packets_low[0x20];
4558
4559         u8         cnps_sent_high[0x20];
4560
4561         u8         cnps_sent_low[0x20];
4562
4563         u8         reserved_3[0x560];
4564 };
4565
4566 struct mlx5_ifc_query_cong_statistics_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_0[0x10];
4569
4570         u8         reserved_1[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         clear[0x1];
4574         u8         reserved_2[0x1f];
4575
4576         u8         reserved_3[0x20];
4577 };
4578
4579 struct mlx5_ifc_query_cong_params_out_bits {
4580         u8         status[0x8];
4581         u8         reserved_0[0x18];
4582
4583         u8         syndrome[0x20];
4584
4585         u8         reserved_1[0x40];
4586
4587         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4588 };
4589
4590 struct mlx5_ifc_query_cong_params_in_bits {
4591         u8         opcode[0x10];
4592         u8         reserved_0[0x10];
4593
4594         u8         reserved_1[0x10];
4595         u8         op_mod[0x10];
4596
4597         u8         reserved_2[0x1c];
4598         u8         cong_protocol[0x4];
4599
4600         u8         reserved_3[0x20];
4601 };
4602
4603 struct mlx5_ifc_query_burst_size_out_bits {
4604         u8         status[0x8];
4605         u8         reserved_0[0x18];
4606
4607         u8         syndrome[0x20];
4608
4609         u8         reserved_1[0x20];
4610
4611         u8         reserved_2[0x9];
4612         u8         device_burst_size[0x17];
4613 };
4614
4615 struct mlx5_ifc_query_burst_size_in_bits {
4616         u8         opcode[0x10];
4617         u8         reserved_0[0x10];
4618
4619         u8         reserved_1[0x10];
4620         u8         op_mod[0x10];
4621
4622         u8         reserved_2[0x40];
4623 };
4624
4625 struct mlx5_ifc_query_adapter_out_bits {
4626         u8         status[0x8];
4627         u8         reserved_0[0x18];
4628
4629         u8         syndrome[0x20];
4630
4631         u8         reserved_1[0x40];
4632
4633         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4634 };
4635
4636 struct mlx5_ifc_query_adapter_in_bits {
4637         u8         opcode[0x10];
4638         u8         reserved_0[0x10];
4639
4640         u8         reserved_1[0x10];
4641         u8         op_mod[0x10];
4642
4643         u8         reserved_2[0x40];
4644 };
4645
4646 struct mlx5_ifc_qp_2rst_out_bits {
4647         u8         status[0x8];
4648         u8         reserved_0[0x18];
4649
4650         u8         syndrome[0x20];
4651
4652         u8         reserved_1[0x40];
4653 };
4654
4655 struct mlx5_ifc_qp_2rst_in_bits {
4656         u8         opcode[0x10];
4657         u8         reserved_0[0x10];
4658
4659         u8         reserved_1[0x10];
4660         u8         op_mod[0x10];
4661
4662         u8         reserved_2[0x8];
4663         u8         qpn[0x18];
4664
4665         u8         reserved_3[0x20];
4666 };
4667
4668 struct mlx5_ifc_qp_2err_out_bits {
4669         u8         status[0x8];
4670         u8         reserved_0[0x18];
4671
4672         u8         syndrome[0x20];
4673
4674         u8         reserved_1[0x40];
4675 };
4676
4677 struct mlx5_ifc_qp_2err_in_bits {
4678         u8         opcode[0x10];
4679         u8         reserved_0[0x10];
4680
4681         u8         reserved_1[0x10];
4682         u8         op_mod[0x10];
4683
4684         u8         reserved_2[0x8];
4685         u8         qpn[0x18];
4686
4687         u8         reserved_3[0x20];
4688 };
4689
4690 struct mlx5_ifc_page_fault_resume_out_bits {
4691         u8         status[0x8];
4692         u8         reserved_0[0x18];
4693
4694         u8         syndrome[0x20];
4695
4696         u8         reserved_1[0x40];
4697 };
4698
4699 struct mlx5_ifc_page_fault_resume_in_bits {
4700         u8         opcode[0x10];
4701         u8         reserved_0[0x10];
4702
4703         u8         reserved_1[0x10];
4704         u8         op_mod[0x10];
4705
4706         u8         error[0x1];
4707         u8         reserved_2[0x4];
4708         u8         rdma[0x1];
4709         u8         read_write[0x1];
4710         u8         req_res[0x1];
4711         u8         qpn[0x18];
4712
4713         u8         reserved_3[0x20];
4714 };
4715
4716 struct mlx5_ifc_nop_out_bits {
4717         u8         status[0x8];
4718         u8         reserved_0[0x18];
4719
4720         u8         syndrome[0x20];
4721
4722         u8         reserved_1[0x40];
4723 };
4724
4725 struct mlx5_ifc_nop_in_bits {
4726         u8         opcode[0x10];
4727         u8         reserved_0[0x10];
4728
4729         u8         reserved_1[0x10];
4730         u8         op_mod[0x10];
4731
4732         u8         reserved_2[0x40];
4733 };
4734
4735 struct mlx5_ifc_modify_vport_state_out_bits {
4736         u8         status[0x8];
4737         u8         reserved_0[0x18];
4738
4739         u8         syndrome[0x20];
4740
4741         u8         reserved_1[0x40];
4742 };
4743
4744 enum {
4745         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
4746         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
4747         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
4748 };
4749
4750 enum {
4751         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
4752         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
4753         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
4754 };
4755
4756 struct mlx5_ifc_modify_vport_state_in_bits {
4757         u8         opcode[0x10];
4758         u8         reserved_0[0x10];
4759
4760         u8         reserved_1[0x10];
4761         u8         op_mod[0x10];
4762
4763         u8         other_vport[0x1];
4764         u8         reserved_2[0xf];
4765         u8         vport_number[0x10];
4766
4767         u8         reserved_3[0x18];
4768         u8         admin_state[0x4];
4769         u8         reserved_4[0x4];
4770 };
4771
4772 struct mlx5_ifc_modify_tis_out_bits {
4773         u8         status[0x8];
4774         u8         reserved_0[0x18];
4775
4776         u8         syndrome[0x20];
4777
4778         u8         reserved_1[0x40];
4779 };
4780
4781 struct mlx5_ifc_modify_tis_in_bits {
4782         u8         opcode[0x10];
4783         u8         reserved_0[0x10];
4784
4785         u8         reserved_1[0x10];
4786         u8         op_mod[0x10];
4787
4788         u8         reserved_2[0x8];
4789         u8         tisn[0x18];
4790
4791         u8         reserved_3[0x20];
4792
4793         u8         modify_bitmask[0x40];
4794
4795         u8         reserved_4[0x40];
4796
4797         struct mlx5_ifc_tisc_bits ctx;
4798 };
4799
4800 struct mlx5_ifc_modify_tir_out_bits {
4801         u8         status[0x8];
4802         u8         reserved_0[0x18];
4803
4804         u8         syndrome[0x20];
4805
4806         u8         reserved_1[0x40];
4807 };
4808
4809 struct mlx5_ifc_modify_tir_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_0[0x10];
4812
4813         u8         reserved_1[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         reserved_2[0x8];
4817         u8         tirn[0x18];
4818
4819         u8         reserved_3[0x20];
4820
4821         u8         modify_bitmask[0x40];
4822
4823         u8         reserved_4[0x40];
4824
4825         struct mlx5_ifc_tirc_bits tir_context;
4826 };
4827
4828 struct mlx5_ifc_modify_sq_out_bits {
4829         u8         status[0x8];
4830         u8         reserved_0[0x18];
4831
4832         u8         syndrome[0x20];
4833
4834         u8         reserved_1[0x40];
4835 };
4836
4837 struct mlx5_ifc_modify_sq_in_bits {
4838         u8         opcode[0x10];
4839         u8         reserved_0[0x10];
4840
4841         u8         reserved_1[0x10];
4842         u8         op_mod[0x10];
4843
4844         u8         sq_state[0x4];
4845         u8         reserved_2[0x4];
4846         u8         sqn[0x18];
4847
4848         u8         reserved_3[0x20];
4849
4850         u8         modify_bitmask[0x40];
4851
4852         u8         reserved_4[0x40];
4853
4854         struct mlx5_ifc_sqc_bits ctx;
4855 };
4856
4857 struct mlx5_ifc_modify_rqt_out_bits {
4858         u8         status[0x8];
4859         u8         reserved_0[0x18];
4860
4861         u8         syndrome[0x20];
4862
4863         u8         reserved_1[0x40];
4864 };
4865
4866 struct mlx5_ifc_modify_rqt_in_bits {
4867         u8         opcode[0x10];
4868         u8         reserved_0[0x10];
4869
4870         u8         reserved_1[0x10];
4871         u8         op_mod[0x10];
4872
4873         u8         reserved_2[0x8];
4874         u8         rqtn[0x18];
4875
4876         u8         reserved_3[0x20];
4877
4878         u8         modify_bitmask[0x40];
4879
4880         u8         reserved_4[0x40];
4881
4882         struct mlx5_ifc_rqtc_bits ctx;
4883 };
4884
4885 struct mlx5_ifc_modify_rq_out_bits {
4886         u8         status[0x8];
4887         u8         reserved_0[0x18];
4888
4889         u8         syndrome[0x20];
4890
4891         u8         reserved_1[0x40];
4892 };
4893
4894 struct mlx5_ifc_rq_bitmask_bits {
4895         u8         reserved[0x20];
4896
4897         u8         reserved1[0x1e];
4898         u8         vlan_strip_disable[0x1];
4899         u8         reserved2[0x1];
4900 };
4901
4902 struct mlx5_ifc_modify_rq_in_bits {
4903         u8         opcode[0x10];
4904         u8         reserved_0[0x10];
4905
4906         u8         reserved_1[0x10];
4907         u8         op_mod[0x10];
4908
4909         u8         rq_state[0x4];
4910         u8         reserved_2[0x4];
4911         u8         rqn[0x18];
4912
4913         u8         reserved_3[0x20];
4914
4915         struct mlx5_ifc_rq_bitmask_bits bitmask;
4916
4917         u8         reserved_4[0x40];
4918
4919         struct mlx5_ifc_rqc_bits ctx;
4920 };
4921
4922 struct mlx5_ifc_modify_rmp_out_bits {
4923         u8         status[0x8];
4924         u8         reserved_0[0x18];
4925
4926         u8         syndrome[0x20];
4927
4928         u8         reserved_1[0x40];
4929 };
4930
4931 struct mlx5_ifc_rmp_bitmask_bits {
4932         u8         reserved[0x20];
4933
4934         u8         reserved1[0x1f];
4935         u8         lwm[0x1];
4936 };
4937
4938 struct mlx5_ifc_modify_rmp_in_bits {
4939         u8         opcode[0x10];
4940         u8         reserved_0[0x10];
4941
4942         u8         reserved_1[0x10];
4943         u8         op_mod[0x10];
4944
4945         u8         rmp_state[0x4];
4946         u8         reserved_2[0x4];
4947         u8         rmpn[0x18];
4948
4949         u8         reserved_3[0x20];
4950
4951         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4952
4953         u8         reserved_4[0x40];
4954
4955         struct mlx5_ifc_rmpc_bits ctx;
4956 };
4957
4958 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4959         u8         status[0x8];
4960         u8         reserved_0[0x18];
4961
4962         u8         syndrome[0x20];
4963
4964         u8         reserved_1[0x40];
4965 };
4966
4967 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4968         u8         reserved_0[0x16];
4969         u8         node_guid[0x1];
4970         u8         port_guid[0x1];
4971         u8         min_wqe_inline_mode[0x1];
4972         u8         mtu[0x1];
4973         u8         change_event[0x1];
4974         u8         promisc[0x1];
4975         u8         permanent_address[0x1];
4976         u8         addresses_list[0x1];
4977         u8         roce_en[0x1];
4978         u8         reserved_1[0x1];
4979 };
4980
4981 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4982         u8         opcode[0x10];
4983         u8         reserved_0[0x10];
4984
4985         u8         reserved_1[0x10];
4986         u8         op_mod[0x10];
4987
4988         u8         other_vport[0x1];
4989         u8         reserved_2[0xf];
4990         u8         vport_number[0x10];
4991
4992         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4993
4994         u8         reserved_3[0x780];
4995
4996         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4997 };
4998
4999 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5000         u8         status[0x8];
5001         u8         reserved_0[0x18];
5002
5003         u8         syndrome[0x20];
5004
5005         u8         reserved_1[0x40];
5006 };
5007
5008 struct mlx5_ifc_grh_bits {
5009         u8      ip_version[4];
5010         u8      traffic_class[8];
5011         u8      flow_label[20];
5012         u8      payload_length[16];
5013         u8      next_header[8];
5014         u8      hop_limit[8];
5015         u8      sgid[128];
5016         u8      dgid[128];
5017 };
5018
5019 struct mlx5_ifc_bth_bits {
5020         u8      opcode[8];
5021         u8      se[1];
5022         u8      migreq[1];
5023         u8      pad_count[2];
5024         u8      tver[4];
5025         u8      p_key[16];
5026         u8      reserved8[8];
5027         u8      dest_qp[24];
5028         u8      ack_req[1];
5029         u8      reserved7[7];
5030         u8      psn[24];
5031 };
5032
5033 struct mlx5_ifc_aeth_bits {
5034         u8      syndrome[8];
5035         u8      msn[24];
5036 };
5037
5038 struct mlx5_ifc_dceth_bits {
5039         u8      reserved0[8];
5040         u8      session_id[24];
5041         u8      reserved1[8];
5042         u8      dci_dct[24];
5043 };
5044
5045 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5046         u8         opcode[0x10];
5047         u8         reserved_0[0x10];
5048
5049         u8         reserved_1[0x10];
5050         u8         op_mod[0x10];
5051
5052         u8         other_vport[0x1];
5053         u8         reserved_2[0xb];
5054         u8         port_num[0x4];
5055         u8         vport_number[0x10];
5056
5057         u8         reserved_3[0x20];
5058
5059         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5060 };
5061
5062 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5063         u8         status[0x8];
5064         u8         reserved_0[0x18];
5065
5066         u8         syndrome[0x20];
5067
5068         u8         reserved_1[0x40];
5069 };
5070
5071 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5072         u8         reserved[0x1c];
5073         u8         vport_cvlan_insert[0x1];
5074         u8         vport_svlan_insert[0x1];
5075         u8         vport_cvlan_strip[0x1];
5076         u8         vport_svlan_strip[0x1];
5077 };
5078
5079 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5080         u8         opcode[0x10];
5081         u8         reserved_0[0x10];
5082
5083         u8         reserved_1[0x10];
5084         u8         op_mod[0x10];
5085
5086         u8         other_vport[0x1];
5087         u8         reserved_2[0xf];
5088         u8         vport_number[0x10];
5089
5090         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5091
5092         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5093 };
5094
5095 struct mlx5_ifc_modify_cq_out_bits {
5096         u8         status[0x8];
5097         u8         reserved_0[0x18];
5098
5099         u8         syndrome[0x20];
5100
5101         u8         reserved_1[0x40];
5102 };
5103
5104 enum {
5105         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5106         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5107 };
5108
5109 struct mlx5_ifc_modify_cq_in_bits {
5110         u8         opcode[0x10];
5111         u8         reserved_0[0x10];
5112
5113         u8         reserved_1[0x10];
5114         u8         op_mod[0x10];
5115
5116         u8         reserved_2[0x8];
5117         u8         cqn[0x18];
5118
5119         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5120
5121         struct mlx5_ifc_cqc_bits cq_context;
5122
5123         u8         reserved_3[0x600];
5124
5125         u8         pas[0][0x40];
5126 };
5127
5128 struct mlx5_ifc_modify_cong_status_out_bits {
5129         u8         status[0x8];
5130         u8         reserved_0[0x18];
5131
5132         u8         syndrome[0x20];
5133
5134         u8         reserved_1[0x40];
5135 };
5136
5137 struct mlx5_ifc_modify_cong_status_in_bits {
5138         u8         opcode[0x10];
5139         u8         reserved_0[0x10];
5140
5141         u8         reserved_1[0x10];
5142         u8         op_mod[0x10];
5143
5144         u8         reserved_2[0x18];
5145         u8         priority[0x4];
5146         u8         cong_protocol[0x4];
5147
5148         u8         enable[0x1];
5149         u8         tag_enable[0x1];
5150         u8         reserved_3[0x1e];
5151 };
5152
5153 struct mlx5_ifc_modify_cong_params_out_bits {
5154         u8         status[0x8];
5155         u8         reserved_0[0x18];
5156
5157         u8         syndrome[0x20];
5158
5159         u8         reserved_1[0x40];
5160 };
5161
5162 struct mlx5_ifc_modify_cong_params_in_bits {
5163         u8         opcode[0x10];
5164         u8         reserved_0[0x10];
5165
5166         u8         reserved_1[0x10];
5167         u8         op_mod[0x10];
5168
5169         u8         reserved_2[0x1c];
5170         u8         cong_protocol[0x4];
5171
5172         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5173
5174         u8         reserved_3[0x80];
5175
5176         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5177 };
5178
5179 struct mlx5_ifc_manage_pages_out_bits {
5180         u8         status[0x8];
5181         u8         reserved_0[0x18];
5182
5183         u8         syndrome[0x20];
5184
5185         u8         output_num_entries[0x20];
5186
5187         u8         reserved_1[0x20];
5188
5189         u8         pas[0][0x40];
5190 };
5191
5192 enum {
5193         MLX5_PAGES_CANT_GIVE                            = 0x0,
5194         MLX5_PAGES_GIVE                                 = 0x1,
5195         MLX5_PAGES_TAKE                                 = 0x2,
5196 };
5197
5198 struct mlx5_ifc_manage_pages_in_bits {
5199         u8         opcode[0x10];
5200         u8         reserved_0[0x10];
5201
5202         u8         reserved_1[0x10];
5203         u8         op_mod[0x10];
5204
5205         u8         reserved_2[0x10];
5206         u8         function_id[0x10];
5207
5208         u8         input_num_entries[0x20];
5209
5210         u8         pas[0][0x40];
5211 };
5212
5213 struct mlx5_ifc_mad_ifc_out_bits {
5214         u8         status[0x8];
5215         u8         reserved_0[0x18];
5216
5217         u8         syndrome[0x20];
5218
5219         u8         reserved_1[0x40];
5220
5221         u8         response_mad_packet[256][0x8];
5222 };
5223
5224 struct mlx5_ifc_mad_ifc_in_bits {
5225         u8         opcode[0x10];
5226         u8         reserved_0[0x10];
5227
5228         u8         reserved_1[0x10];
5229         u8         op_mod[0x10];
5230
5231         u8         remote_lid[0x10];
5232         u8         reserved_2[0x8];
5233         u8         port[0x8];
5234
5235         u8         reserved_3[0x20];
5236
5237         u8         mad[256][0x8];
5238 };
5239
5240 struct mlx5_ifc_init_hca_out_bits {
5241         u8         status[0x8];
5242         u8         reserved_0[0x18];
5243
5244         u8         syndrome[0x20];
5245
5246         u8         reserved_1[0x40];
5247 };
5248
5249 enum {
5250         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5251         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5252 };
5253
5254 struct mlx5_ifc_init_hca_in_bits {
5255         u8         opcode[0x10];
5256         u8         reserved_0[0x10];
5257
5258         u8         reserved_1[0x10];
5259         u8         op_mod[0x10];
5260
5261         u8         reserved_2[0x40];
5262 };
5263
5264 struct mlx5_ifc_init2rtr_qp_out_bits {
5265         u8         status[0x8];
5266         u8         reserved_0[0x18];
5267
5268         u8         syndrome[0x20];
5269
5270         u8         reserved_1[0x40];
5271 };
5272
5273 struct mlx5_ifc_init2rtr_qp_in_bits {
5274         u8         opcode[0x10];
5275         u8         reserved_0[0x10];
5276
5277         u8         reserved_1[0x10];
5278         u8         op_mod[0x10];
5279
5280         u8         reserved_2[0x8];
5281         u8         qpn[0x18];
5282
5283         u8         reserved_3[0x20];
5284
5285         u8         opt_param_mask[0x20];
5286
5287         u8         reserved_4[0x20];
5288
5289         struct mlx5_ifc_qpc_bits qpc;
5290
5291         u8         reserved_5[0x80];
5292 };
5293
5294 struct mlx5_ifc_init2init_qp_out_bits {
5295         u8         status[0x8];
5296         u8         reserved_0[0x18];
5297
5298         u8         syndrome[0x20];
5299
5300         u8         reserved_1[0x40];
5301 };
5302
5303 struct mlx5_ifc_init2init_qp_in_bits {
5304         u8         opcode[0x10];
5305         u8         reserved_0[0x10];
5306
5307         u8         reserved_1[0x10];
5308         u8         op_mod[0x10];
5309
5310         u8         reserved_2[0x8];
5311         u8         qpn[0x18];
5312
5313         u8         reserved_3[0x20];
5314
5315         u8         opt_param_mask[0x20];
5316
5317         u8         reserved_4[0x20];
5318
5319         struct mlx5_ifc_qpc_bits qpc;
5320
5321         u8         reserved_5[0x80];
5322 };
5323
5324 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5325         u8         status[0x8];
5326         u8         reserved_0[0x18];
5327
5328         u8         syndrome[0x20];
5329
5330         u8         reserved_1[0x40];
5331
5332         u8         packet_headers_log[128][0x8];
5333
5334         u8         packet_syndrome[64][0x8];
5335 };
5336
5337 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5338         u8         opcode[0x10];
5339         u8         reserved_0[0x10];
5340
5341         u8         reserved_1[0x10];
5342         u8         op_mod[0x10];
5343
5344         u8         reserved_2[0x40];
5345 };
5346
5347 struct mlx5_ifc_gen_eqe_in_bits {
5348         u8         opcode[0x10];
5349         u8         reserved_0[0x10];
5350
5351         u8         reserved_1[0x10];
5352         u8         op_mod[0x10];
5353
5354         u8         reserved_2[0x18];
5355         u8         eq_number[0x8];
5356
5357         u8         reserved_3[0x20];
5358
5359         u8         eqe[64][0x8];
5360 };
5361
5362 struct mlx5_ifc_gen_eq_out_bits {
5363         u8         status[0x8];
5364         u8         reserved_0[0x18];
5365
5366         u8         syndrome[0x20];
5367
5368         u8         reserved_1[0x40];
5369 };
5370
5371 struct mlx5_ifc_enable_hca_out_bits {
5372         u8         status[0x8];
5373         u8         reserved_0[0x18];
5374
5375         u8         syndrome[0x20];
5376
5377         u8         reserved_1[0x20];
5378 };
5379
5380 struct mlx5_ifc_enable_hca_in_bits {
5381         u8         opcode[0x10];
5382         u8         reserved_0[0x10];
5383
5384         u8         reserved_1[0x10];
5385         u8         op_mod[0x10];
5386
5387         u8         reserved_2[0x10];
5388         u8         function_id[0x10];
5389
5390         u8         reserved_3[0x20];
5391 };
5392
5393 struct mlx5_ifc_drain_dct_out_bits {
5394         u8         status[0x8];
5395         u8         reserved_0[0x18];
5396
5397         u8         syndrome[0x20];
5398
5399         u8         reserved_1[0x40];
5400 };
5401
5402 struct mlx5_ifc_drain_dct_in_bits {
5403         u8         opcode[0x10];
5404         u8         reserved_0[0x10];
5405
5406         u8         reserved_1[0x10];
5407         u8         op_mod[0x10];
5408
5409         u8         reserved_2[0x8];
5410         u8         dctn[0x18];
5411
5412         u8         reserved_3[0x20];
5413 };
5414
5415 struct mlx5_ifc_disable_hca_out_bits {
5416         u8         status[0x8];
5417         u8         reserved_0[0x18];
5418
5419         u8         syndrome[0x20];
5420
5421         u8         reserved_1[0x20];
5422 };
5423
5424 struct mlx5_ifc_disable_hca_in_bits {
5425         u8         opcode[0x10];
5426         u8         reserved_0[0x10];
5427
5428         u8         reserved_1[0x10];
5429         u8         op_mod[0x10];
5430
5431         u8         reserved_2[0x10];
5432         u8         function_id[0x10];
5433
5434         u8         reserved_3[0x20];
5435 };
5436
5437 struct mlx5_ifc_detach_from_mcg_out_bits {
5438         u8         status[0x8];
5439         u8         reserved_0[0x18];
5440
5441         u8         syndrome[0x20];
5442
5443         u8         reserved_1[0x40];
5444 };
5445
5446 struct mlx5_ifc_detach_from_mcg_in_bits {
5447         u8         opcode[0x10];
5448         u8         reserved_0[0x10];
5449
5450         u8         reserved_1[0x10];
5451         u8         op_mod[0x10];
5452
5453         u8         reserved_2[0x8];
5454         u8         qpn[0x18];
5455
5456         u8         reserved_3[0x20];
5457
5458         u8         multicast_gid[16][0x8];
5459 };
5460
5461 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5462         u8         status[0x8];
5463         u8         reserved_0[0x18];
5464
5465         u8         syndrome[0x20];
5466
5467         u8         reserved_1[0x40];
5468 };
5469
5470 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5471         u8         opcode[0x10];
5472         u8         reserved_0[0x10];
5473
5474         u8         reserved_1[0x10];
5475         u8         op_mod[0x10];
5476
5477         u8         reserved_2[0x8];
5478         u8         xrc_srqn[0x18];
5479
5480         u8         reserved_3[0x20];
5481 };
5482
5483 struct mlx5_ifc_destroy_tis_out_bits {
5484         u8         status[0x8];
5485         u8         reserved_0[0x18];
5486
5487         u8         syndrome[0x20];
5488
5489         u8         reserved_1[0x40];
5490 };
5491
5492 struct mlx5_ifc_destroy_tis_in_bits {
5493         u8         opcode[0x10];
5494         u8         reserved_0[0x10];
5495
5496         u8         reserved_1[0x10];
5497         u8         op_mod[0x10];
5498
5499         u8         reserved_2[0x8];
5500         u8         tisn[0x18];
5501
5502         u8         reserved_3[0x20];
5503 };
5504
5505 struct mlx5_ifc_destroy_tir_out_bits {
5506         u8         status[0x8];
5507         u8         reserved_0[0x18];
5508
5509         u8         syndrome[0x20];
5510
5511         u8         reserved_1[0x40];
5512 };
5513
5514 struct mlx5_ifc_destroy_tir_in_bits {
5515         u8         opcode[0x10];
5516         u8         reserved_0[0x10];
5517
5518         u8         reserved_1[0x10];
5519         u8         op_mod[0x10];
5520
5521         u8         reserved_2[0x8];
5522         u8         tirn[0x18];
5523
5524         u8         reserved_3[0x20];
5525 };
5526
5527 struct mlx5_ifc_destroy_srq_out_bits {
5528         u8         status[0x8];
5529         u8         reserved_0[0x18];
5530
5531         u8         syndrome[0x20];
5532
5533         u8         reserved_1[0x40];
5534 };
5535
5536 struct mlx5_ifc_destroy_srq_in_bits {
5537         u8         opcode[0x10];
5538         u8         reserved_0[0x10];
5539
5540         u8         reserved_1[0x10];
5541         u8         op_mod[0x10];
5542
5543         u8         reserved_2[0x8];
5544         u8         srqn[0x18];
5545
5546         u8         reserved_3[0x20];
5547 };
5548
5549 struct mlx5_ifc_destroy_sq_out_bits {
5550         u8         status[0x8];
5551         u8         reserved_0[0x18];
5552
5553         u8         syndrome[0x20];
5554
5555         u8         reserved_1[0x40];
5556 };
5557
5558 struct mlx5_ifc_destroy_sq_in_bits {
5559         u8         opcode[0x10];
5560         u8         reserved_0[0x10];
5561
5562         u8         reserved_1[0x10];
5563         u8         op_mod[0x10];
5564
5565         u8         reserved_2[0x8];
5566         u8         sqn[0x18];
5567
5568         u8         reserved_3[0x20];
5569 };
5570
5571 struct mlx5_ifc_destroy_rqt_out_bits {
5572         u8         status[0x8];
5573         u8         reserved_0[0x18];
5574
5575         u8         syndrome[0x20];
5576
5577         u8         reserved_1[0x40];
5578 };
5579
5580 struct mlx5_ifc_destroy_rqt_in_bits {
5581         u8         opcode[0x10];
5582         u8         reserved_0[0x10];
5583
5584         u8         reserved_1[0x10];
5585         u8         op_mod[0x10];
5586
5587         u8         reserved_2[0x8];
5588         u8         rqtn[0x18];
5589
5590         u8         reserved_3[0x20];
5591 };
5592
5593 struct mlx5_ifc_destroy_rq_out_bits {
5594         u8         status[0x8];
5595         u8         reserved_0[0x18];
5596
5597         u8         syndrome[0x20];
5598
5599         u8         reserved_1[0x40];
5600 };
5601
5602 struct mlx5_ifc_destroy_rq_in_bits {
5603         u8         opcode[0x10];
5604         u8         reserved_0[0x10];
5605
5606         u8         reserved_1[0x10];
5607         u8         op_mod[0x10];
5608
5609         u8         reserved_2[0x8];
5610         u8         rqn[0x18];
5611
5612         u8         reserved_3[0x20];
5613 };
5614
5615 struct mlx5_ifc_destroy_rmp_out_bits {
5616         u8         status[0x8];
5617         u8         reserved_0[0x18];
5618
5619         u8         syndrome[0x20];
5620
5621         u8         reserved_1[0x40];
5622 };
5623
5624 struct mlx5_ifc_destroy_rmp_in_bits {
5625         u8         opcode[0x10];
5626         u8         reserved_0[0x10];
5627
5628         u8         reserved_1[0x10];
5629         u8         op_mod[0x10];
5630
5631         u8         reserved_2[0x8];
5632         u8         rmpn[0x18];
5633
5634         u8         reserved_3[0x20];
5635 };
5636
5637 struct mlx5_ifc_destroy_qp_out_bits {
5638         u8         status[0x8];
5639         u8         reserved_0[0x18];
5640
5641         u8         syndrome[0x20];
5642
5643         u8         reserved_1[0x40];
5644 };
5645
5646 struct mlx5_ifc_destroy_qp_in_bits {
5647         u8         opcode[0x10];
5648         u8         reserved_0[0x10];
5649
5650         u8         reserved_1[0x10];
5651         u8         op_mod[0x10];
5652
5653         u8         reserved_2[0x8];
5654         u8         qpn[0x18];
5655
5656         u8         reserved_3[0x20];
5657 };
5658
5659 struct mlx5_ifc_destroy_psv_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_0[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_1[0x40];
5666 };
5667
5668 struct mlx5_ifc_destroy_psv_in_bits {
5669         u8         opcode[0x10];
5670         u8         reserved_0[0x10];
5671
5672         u8         reserved_1[0x10];
5673         u8         op_mod[0x10];
5674
5675         u8         reserved_2[0x8];
5676         u8         psvn[0x18];
5677
5678         u8         reserved_3[0x20];
5679 };
5680
5681 struct mlx5_ifc_destroy_mkey_out_bits {
5682         u8         status[0x8];
5683         u8         reserved_0[0x18];
5684
5685         u8         syndrome[0x20];
5686
5687         u8         reserved_1[0x40];
5688 };
5689
5690 struct mlx5_ifc_destroy_mkey_in_bits {
5691         u8         opcode[0x10];
5692         u8         reserved_0[0x10];
5693
5694         u8         reserved_1[0x10];
5695         u8         op_mod[0x10];
5696
5697         u8         reserved_2[0x8];
5698         u8         mkey_index[0x18];
5699
5700         u8         reserved_3[0x20];
5701 };
5702
5703 struct mlx5_ifc_destroy_flow_table_out_bits {
5704         u8         status[0x8];
5705         u8         reserved_0[0x18];
5706
5707         u8         syndrome[0x20];
5708
5709         u8         reserved_1[0x40];
5710 };
5711
5712 struct mlx5_ifc_destroy_flow_table_in_bits {
5713         u8         opcode[0x10];
5714         u8         reserved_0[0x10];
5715
5716         u8         reserved_1[0x10];
5717         u8         op_mod[0x10];
5718
5719         u8         other_vport[0x1];
5720         u8         reserved_2[0xf];
5721         u8         vport_number[0x10];
5722
5723         u8         reserved_3[0x20];
5724
5725         u8         table_type[0x8];
5726         u8         reserved_4[0x18];
5727
5728         u8         reserved_5[0x8];
5729         u8         table_id[0x18];
5730
5731         u8         reserved_6[0x140];
5732 };
5733
5734 struct mlx5_ifc_destroy_flow_group_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_0[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_1[0x40];
5741 };
5742
5743 struct mlx5_ifc_destroy_flow_group_in_bits {
5744         u8         opcode[0x10];
5745         u8         reserved_0[0x10];
5746
5747         u8         reserved_1[0x10];
5748         u8         op_mod[0x10];
5749
5750         u8         other_vport[0x1];
5751         u8         reserved_2[0xf];
5752         u8         vport_number[0x10];
5753
5754         u8         reserved_3[0x20];
5755
5756         u8         table_type[0x8];
5757         u8         reserved_4[0x18];
5758
5759         u8         reserved_5[0x8];
5760         u8         table_id[0x18];
5761
5762         u8         group_id[0x20];
5763
5764         u8         reserved_6[0x120];
5765 };
5766
5767 struct mlx5_ifc_destroy_eq_out_bits {
5768         u8         status[0x8];
5769         u8         reserved_0[0x18];
5770
5771         u8         syndrome[0x20];
5772
5773         u8         reserved_1[0x40];
5774 };
5775
5776 struct mlx5_ifc_destroy_eq_in_bits {
5777         u8         opcode[0x10];
5778         u8         reserved_0[0x10];
5779
5780         u8         reserved_1[0x10];
5781         u8         op_mod[0x10];
5782
5783         u8         reserved_2[0x18];
5784         u8         eq_number[0x8];
5785
5786         u8         reserved_3[0x20];
5787 };
5788
5789 struct mlx5_ifc_destroy_dct_out_bits {
5790         u8         status[0x8];
5791         u8         reserved_0[0x18];
5792
5793         u8         syndrome[0x20];
5794
5795         u8         reserved_1[0x40];
5796 };
5797
5798 struct mlx5_ifc_destroy_dct_in_bits {
5799         u8         opcode[0x10];
5800         u8         reserved_0[0x10];
5801
5802         u8         reserved_1[0x10];
5803         u8         op_mod[0x10];
5804
5805         u8         reserved_2[0x8];
5806         u8         dctn[0x18];
5807
5808         u8         reserved_3[0x20];
5809 };
5810
5811 struct mlx5_ifc_destroy_cq_out_bits {
5812         u8         status[0x8];
5813         u8         reserved_0[0x18];
5814
5815         u8         syndrome[0x20];
5816
5817         u8         reserved_1[0x40];
5818 };
5819
5820 struct mlx5_ifc_destroy_cq_in_bits {
5821         u8         opcode[0x10];
5822         u8         reserved_0[0x10];
5823
5824         u8         reserved_1[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         reserved_2[0x8];
5828         u8         cqn[0x18];
5829
5830         u8         reserved_3[0x20];
5831 };
5832
5833 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5834         u8         status[0x8];
5835         u8         reserved_0[0x18];
5836
5837         u8         syndrome[0x20];
5838
5839         u8         reserved_1[0x40];
5840 };
5841
5842 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5843         u8         opcode[0x10];
5844         u8         reserved_0[0x10];
5845
5846         u8         reserved_1[0x10];
5847         u8         op_mod[0x10];
5848
5849         u8         reserved_2[0x20];
5850
5851         u8         reserved_3[0x10];
5852         u8         vxlan_udp_port[0x10];
5853 };
5854
5855 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5856         u8         status[0x8];
5857         u8         reserved_0[0x18];
5858
5859         u8         syndrome[0x20];
5860
5861         u8         reserved_1[0x40];
5862 };
5863
5864 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5865         u8         opcode[0x10];
5866         u8         reserved_0[0x10];
5867
5868         u8         reserved_1[0x10];
5869         u8         op_mod[0x10];
5870
5871         u8         reserved_2[0x60];
5872
5873         u8         reserved_3[0x8];
5874         u8         table_index[0x18];
5875
5876         u8         reserved_4[0x140];
5877 };
5878
5879 struct mlx5_ifc_delete_fte_out_bits {
5880         u8         status[0x8];
5881         u8         reserved_0[0x18];
5882
5883         u8         syndrome[0x20];
5884
5885         u8         reserved_1[0x40];
5886 };
5887
5888 struct mlx5_ifc_delete_fte_in_bits {
5889         u8         opcode[0x10];
5890         u8         reserved_0[0x10];
5891
5892         u8         reserved_1[0x10];
5893         u8         op_mod[0x10];
5894
5895         u8         other_vport[0x1];
5896         u8         reserved_2[0xf];
5897         u8         vport_number[0x10];
5898
5899         u8         reserved_3[0x20];
5900
5901         u8         table_type[0x8];
5902         u8         reserved_4[0x18];
5903
5904         u8         reserved_5[0x8];
5905         u8         table_id[0x18];
5906
5907         u8         reserved_6[0x40];
5908
5909         u8         flow_index[0x20];
5910
5911         u8         reserved_7[0xe0];
5912 };
5913
5914 struct mlx5_ifc_dealloc_xrcd_out_bits {
5915         u8         status[0x8];
5916         u8         reserved_0[0x18];
5917
5918         u8         syndrome[0x20];
5919
5920         u8         reserved_1[0x40];
5921 };
5922
5923 struct mlx5_ifc_dealloc_xrcd_in_bits {
5924         u8         opcode[0x10];
5925         u8         reserved_0[0x10];
5926
5927         u8         reserved_1[0x10];
5928         u8         op_mod[0x10];
5929
5930         u8         reserved_2[0x8];
5931         u8         xrcd[0x18];
5932
5933         u8         reserved_3[0x20];
5934 };
5935
5936 struct mlx5_ifc_dealloc_uar_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_0[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_1[0x40];
5943 };
5944
5945 struct mlx5_ifc_dealloc_uar_in_bits {
5946         u8         opcode[0x10];
5947         u8         reserved_0[0x10];
5948
5949         u8         reserved_1[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_2[0x8];
5953         u8         uar[0x18];
5954
5955         u8         reserved_3[0x20];
5956 };
5957
5958 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5959         u8         status[0x8];
5960         u8         reserved_0[0x18];
5961
5962         u8         syndrome[0x20];
5963
5964         u8         reserved_1[0x40];
5965 };
5966
5967 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5968         u8         opcode[0x10];
5969         u8         reserved_0[0x10];
5970
5971         u8         reserved_1[0x10];
5972         u8         op_mod[0x10];
5973
5974         u8         reserved_2[0x8];
5975         u8         transport_domain[0x18];
5976
5977         u8         reserved_3[0x20];
5978 };
5979
5980 struct mlx5_ifc_dealloc_q_counter_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_0[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_1[0x40];
5987 };
5988
5989 struct mlx5_ifc_counter_id_bits {
5990         u8         reserved[0x10];
5991         u8         counter_id[0x10];
5992 };
5993
5994 struct mlx5_ifc_set_diagnostics_in_bits {
5995         u8         opcode[0x10];
5996         u8         reserved_0[0x10];
5997
5998         u8         reserved_1[0x10];
5999         u8         op_mod[0x10];
6000
6001         u8         num_of_counters[0x10];
6002         u8         reserved_2[0x8];
6003         u8         log_num_of_samples[0x8];
6004
6005         u8         single[0x1];
6006         u8         repetitive[0x1];
6007         u8         sync[0x1];
6008         u8         clear[0x1];
6009         u8         on_demand[0x1];
6010         u8         enable[0x1];
6011         u8         reserved_3[0x12];
6012         u8         log_sample_period[0x8];
6013
6014         u8         reserved_4[0x80];
6015
6016         struct mlx5_ifc_counter_id_bits counter_id[0];
6017 };
6018
6019 struct mlx5_ifc_set_diagnostics_out_bits {
6020         u8         status[0x8];
6021         u8         reserved_0[0x18];
6022
6023         u8         syndrome[0x20];
6024
6025         u8         reserved_1[0x40];
6026 };
6027
6028 struct mlx5_ifc_query_diagnostics_in_bits {
6029         u8         opcode[0x10];
6030         u8         reserved_0[0x10];
6031
6032         u8         reserved_1[0x10];
6033         u8         op_mod[0x10];
6034
6035         u8         num_of_samples[0x10];
6036         u8         sample_index[0x10];
6037
6038         u8         reserved_2[0x20];
6039 };
6040
6041 struct mlx5_ifc_diagnostic_counter_bits {
6042         u8         counter_id[0x10];
6043         u8         sample_id[0x10];
6044
6045         u8         time_stamp_31_0[0x20];
6046
6047         u8         counter_value_h[0x20];
6048
6049         u8         counter_value_l[0x20];
6050 };
6051
6052 struct mlx5_ifc_query_diagnostics_out_bits {
6053         u8         status[0x8];
6054         u8         reserved_0[0x18];
6055
6056         u8         syndrome[0x20];
6057
6058         u8         reserved_1[0x40];
6059
6060         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6061 };
6062
6063 struct mlx5_ifc_dealloc_q_counter_in_bits {
6064         u8         opcode[0x10];
6065         u8         reserved_0[0x10];
6066
6067         u8         reserved_1[0x10];
6068         u8         op_mod[0x10];
6069
6070         u8         reserved_2[0x18];
6071         u8         counter_set_id[0x8];
6072
6073         u8         reserved_3[0x20];
6074 };
6075
6076 struct mlx5_ifc_dealloc_pd_out_bits {
6077         u8         status[0x8];
6078         u8         reserved_0[0x18];
6079
6080         u8         syndrome[0x20];
6081
6082         u8         reserved_1[0x40];
6083 };
6084
6085 struct mlx5_ifc_dealloc_pd_in_bits {
6086         u8         opcode[0x10];
6087         u8         reserved_0[0x10];
6088
6089         u8         reserved_1[0x10];
6090         u8         op_mod[0x10];
6091
6092         u8         reserved_2[0x8];
6093         u8         pd[0x18];
6094
6095         u8         reserved_3[0x20];
6096 };
6097
6098 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6099         u8         status[0x8];
6100         u8         reserved_0[0x18];
6101
6102         u8         syndrome[0x20];
6103
6104         u8         reserved_1[0x40];
6105 };
6106
6107 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6108         u8         opcode[0x10];
6109         u8         reserved_0[0x10];
6110
6111         u8         reserved_1[0x10];
6112         u8         op_mod[0x10];
6113
6114         u8         reserved_2[0x10];
6115         u8         flow_counter_id[0x10];
6116
6117         u8         reserved_3[0x20];
6118 };
6119
6120 struct mlx5_ifc_deactivate_tracer_out_bits {
6121         u8         status[0x8];
6122         u8         reserved_0[0x18];
6123
6124         u8         syndrome[0x20];
6125
6126         u8         reserved_1[0x40];
6127 };
6128
6129 struct mlx5_ifc_deactivate_tracer_in_bits {
6130         u8         opcode[0x10];
6131         u8         reserved_0[0x10];
6132
6133         u8         reserved_1[0x10];
6134         u8         op_mod[0x10];
6135
6136         u8         mkey[0x20];
6137
6138         u8         reserved_2[0x20];
6139 };
6140
6141 struct mlx5_ifc_create_xrc_srq_out_bits {
6142         u8         status[0x8];
6143         u8         reserved_0[0x18];
6144
6145         u8         syndrome[0x20];
6146
6147         u8         reserved_1[0x8];
6148         u8         xrc_srqn[0x18];
6149
6150         u8         reserved_2[0x20];
6151 };
6152
6153 struct mlx5_ifc_create_xrc_srq_in_bits {
6154         u8         opcode[0x10];
6155         u8         reserved_0[0x10];
6156
6157         u8         reserved_1[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         reserved_2[0x40];
6161
6162         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6163
6164         u8         reserved_3[0x600];
6165
6166         u8         pas[0][0x40];
6167 };
6168
6169 struct mlx5_ifc_create_tis_out_bits {
6170         u8         status[0x8];
6171         u8         reserved_0[0x18];
6172
6173         u8         syndrome[0x20];
6174
6175         u8         reserved_1[0x8];
6176         u8         tisn[0x18];
6177
6178         u8         reserved_2[0x20];
6179 };
6180
6181 struct mlx5_ifc_create_tis_in_bits {
6182         u8         opcode[0x10];
6183         u8         reserved_0[0x10];
6184
6185         u8         reserved_1[0x10];
6186         u8         op_mod[0x10];
6187
6188         u8         reserved_2[0xc0];
6189
6190         struct mlx5_ifc_tisc_bits ctx;
6191 };
6192
6193 struct mlx5_ifc_create_tir_out_bits {
6194         u8         status[0x8];
6195         u8         reserved_0[0x18];
6196
6197         u8         syndrome[0x20];
6198
6199         u8         reserved_1[0x8];
6200         u8         tirn[0x18];
6201
6202         u8         reserved_2[0x20];
6203 };
6204
6205 struct mlx5_ifc_create_tir_in_bits {
6206         u8         opcode[0x10];
6207         u8         reserved_0[0x10];
6208
6209         u8         reserved_1[0x10];
6210         u8         op_mod[0x10];
6211
6212         u8         reserved_2[0xc0];
6213
6214         struct mlx5_ifc_tirc_bits tir_context;
6215 };
6216
6217 struct mlx5_ifc_create_srq_out_bits {
6218         u8         status[0x8];
6219         u8         reserved_0[0x18];
6220
6221         u8         syndrome[0x20];
6222
6223         u8         reserved_1[0x8];
6224         u8         srqn[0x18];
6225
6226         u8         reserved_2[0x20];
6227 };
6228
6229 struct mlx5_ifc_create_srq_in_bits {
6230         u8         opcode[0x10];
6231         u8         reserved_0[0x10];
6232
6233         u8         reserved_1[0x10];
6234         u8         op_mod[0x10];
6235
6236         u8         reserved_2[0x40];
6237
6238         struct mlx5_ifc_srqc_bits srq_context_entry;
6239
6240         u8         reserved_3[0x600];
6241
6242         u8         pas[0][0x40];
6243 };
6244
6245 struct mlx5_ifc_create_sq_out_bits {
6246         u8         status[0x8];
6247         u8         reserved_0[0x18];
6248
6249         u8         syndrome[0x20];
6250
6251         u8         reserved_1[0x8];
6252         u8         sqn[0x18];
6253
6254         u8         reserved_2[0x20];
6255 };
6256
6257 struct mlx5_ifc_create_sq_in_bits {
6258         u8         opcode[0x10];
6259         u8         reserved_0[0x10];
6260
6261         u8         reserved_1[0x10];
6262         u8         op_mod[0x10];
6263
6264         u8         reserved_2[0xc0];
6265
6266         struct mlx5_ifc_sqc_bits ctx;
6267 };
6268
6269 struct mlx5_ifc_create_rqt_out_bits {
6270         u8         status[0x8];
6271         u8         reserved_0[0x18];
6272
6273         u8         syndrome[0x20];
6274
6275         u8         reserved_1[0x8];
6276         u8         rqtn[0x18];
6277
6278         u8         reserved_2[0x20];
6279 };
6280
6281 struct mlx5_ifc_create_rqt_in_bits {
6282         u8         opcode[0x10];
6283         u8         reserved_0[0x10];
6284
6285         u8         reserved_1[0x10];
6286         u8         op_mod[0x10];
6287
6288         u8         reserved_2[0xc0];
6289
6290         struct mlx5_ifc_rqtc_bits rqt_context;
6291 };
6292
6293 struct mlx5_ifc_create_rq_out_bits {
6294         u8         status[0x8];
6295         u8         reserved_0[0x18];
6296
6297         u8         syndrome[0x20];
6298
6299         u8         reserved_1[0x8];
6300         u8         rqn[0x18];
6301
6302         u8         reserved_2[0x20];
6303 };
6304
6305 struct mlx5_ifc_create_rq_in_bits {
6306         u8         opcode[0x10];
6307         u8         reserved_0[0x10];
6308
6309         u8         reserved_1[0x10];
6310         u8         op_mod[0x10];
6311
6312         u8         reserved_2[0xc0];
6313
6314         struct mlx5_ifc_rqc_bits ctx;
6315 };
6316
6317 struct mlx5_ifc_create_rmp_out_bits {
6318         u8         status[0x8];
6319         u8         reserved_0[0x18];
6320
6321         u8         syndrome[0x20];
6322
6323         u8         reserved_1[0x8];
6324         u8         rmpn[0x18];
6325
6326         u8         reserved_2[0x20];
6327 };
6328
6329 struct mlx5_ifc_create_rmp_in_bits {
6330         u8         opcode[0x10];
6331         u8         reserved_0[0x10];
6332
6333         u8         reserved_1[0x10];
6334         u8         op_mod[0x10];
6335
6336         u8         reserved_2[0xc0];
6337
6338         struct mlx5_ifc_rmpc_bits ctx;
6339 };
6340
6341 struct mlx5_ifc_create_qp_out_bits {
6342         u8         status[0x8];
6343         u8         reserved_0[0x18];
6344
6345         u8         syndrome[0x20];
6346
6347         u8         reserved_1[0x8];
6348         u8         qpn[0x18];
6349
6350         u8         reserved_2[0x20];
6351 };
6352
6353 struct mlx5_ifc_create_qp_in_bits {
6354         u8         opcode[0x10];
6355         u8         reserved_0[0x10];
6356
6357         u8         reserved_1[0x10];
6358         u8         op_mod[0x10];
6359
6360         u8         reserved_2[0x8];
6361         u8         input_qpn[0x18];
6362
6363         u8         reserved_3[0x20];
6364
6365         u8         opt_param_mask[0x20];
6366
6367         u8         reserved_4[0x20];
6368
6369         struct mlx5_ifc_qpc_bits qpc;
6370
6371         u8         reserved_5[0x80];
6372
6373         u8         pas[0][0x40];
6374 };
6375
6376 struct mlx5_ifc_create_psv_out_bits {
6377         u8         status[0x8];
6378         u8         reserved_0[0x18];
6379
6380         u8         syndrome[0x20];
6381
6382         u8         reserved_1[0x40];
6383
6384         u8         reserved_2[0x8];
6385         u8         psv0_index[0x18];
6386
6387         u8         reserved_3[0x8];
6388         u8         psv1_index[0x18];
6389
6390         u8         reserved_4[0x8];
6391         u8         psv2_index[0x18];
6392
6393         u8         reserved_5[0x8];
6394         u8         psv3_index[0x18];
6395 };
6396
6397 struct mlx5_ifc_create_psv_in_bits {
6398         u8         opcode[0x10];
6399         u8         reserved_0[0x10];
6400
6401         u8         reserved_1[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         num_psv[0x4];
6405         u8         reserved_2[0x4];
6406         u8         pd[0x18];
6407
6408         u8         reserved_3[0x20];
6409 };
6410
6411 struct mlx5_ifc_create_mkey_out_bits {
6412         u8         status[0x8];
6413         u8         reserved_0[0x18];
6414
6415         u8         syndrome[0x20];
6416
6417         u8         reserved_1[0x8];
6418         u8         mkey_index[0x18];
6419
6420         u8         reserved_2[0x20];
6421 };
6422
6423 struct mlx5_ifc_create_mkey_in_bits {
6424         u8         opcode[0x10];
6425         u8         reserved_0[0x10];
6426
6427         u8         reserved_1[0x10];
6428         u8         op_mod[0x10];
6429
6430         u8         reserved_2[0x20];
6431
6432         u8         pg_access[0x1];
6433         u8         reserved_3[0x1f];
6434
6435         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6436
6437         u8         reserved_4[0x80];
6438
6439         u8         translations_octword_actual_size[0x20];
6440
6441         u8         reserved_5[0x560];
6442
6443         u8         klm_pas_mtt[0][0x20];
6444 };
6445
6446 struct mlx5_ifc_create_flow_table_out_bits {
6447         u8         status[0x8];
6448         u8         reserved_0[0x18];
6449
6450         u8         syndrome[0x20];
6451
6452         u8         reserved_1[0x8];
6453         u8         table_id[0x18];
6454
6455         u8         reserved_2[0x20];
6456 };
6457
6458 struct mlx5_ifc_create_flow_table_in_bits {
6459         u8         opcode[0x10];
6460         u8         reserved_0[0x10];
6461
6462         u8         reserved_1[0x10];
6463         u8         op_mod[0x10];
6464
6465         u8         other_vport[0x1];
6466         u8         reserved_2[0xf];
6467         u8         vport_number[0x10];
6468
6469         u8         reserved_3[0x20];
6470
6471         u8         table_type[0x8];
6472         u8         reserved_4[0x18];
6473
6474         u8         reserved_5[0x20];
6475
6476         u8         reserved_6[0x8];
6477         u8         level[0x8];
6478         u8         reserved_7[0x8];
6479         u8         log_size[0x8];
6480
6481         u8         reserved_8[0x120];
6482 };
6483
6484 struct mlx5_ifc_create_flow_group_out_bits {
6485         u8         status[0x8];
6486         u8         reserved_0[0x18];
6487
6488         u8         syndrome[0x20];
6489
6490         u8         reserved_1[0x8];
6491         u8         group_id[0x18];
6492
6493         u8         reserved_2[0x20];
6494 };
6495
6496 enum {
6497         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6498         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6499         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6500 };
6501
6502 struct mlx5_ifc_create_flow_group_in_bits {
6503         u8         opcode[0x10];
6504         u8         reserved_0[0x10];
6505
6506         u8         reserved_1[0x10];
6507         u8         op_mod[0x10];
6508
6509         u8         other_vport[0x1];
6510         u8         reserved_2[0xf];
6511         u8         vport_number[0x10];
6512
6513         u8         reserved_3[0x20];
6514
6515         u8         table_type[0x8];
6516         u8         reserved_4[0x18];
6517
6518         u8         reserved_5[0x8];
6519         u8         table_id[0x18];
6520
6521         u8         reserved_6[0x20];
6522
6523         u8         start_flow_index[0x20];
6524
6525         u8         reserved_7[0x20];
6526
6527         u8         end_flow_index[0x20];
6528
6529         u8         reserved_8[0xa0];
6530
6531         u8         reserved_9[0x18];
6532         u8         match_criteria_enable[0x8];
6533
6534         struct mlx5_ifc_fte_match_param_bits match_criteria;
6535
6536         u8         reserved_10[0xe00];
6537 };
6538
6539 struct mlx5_ifc_create_eq_out_bits {
6540         u8         status[0x8];
6541         u8         reserved_0[0x18];
6542
6543         u8         syndrome[0x20];
6544
6545         u8         reserved_1[0x18];
6546         u8         eq_number[0x8];
6547
6548         u8         reserved_2[0x20];
6549 };
6550
6551 struct mlx5_ifc_create_eq_in_bits {
6552         u8         opcode[0x10];
6553         u8         reserved_0[0x10];
6554
6555         u8         reserved_1[0x10];
6556         u8         op_mod[0x10];
6557
6558         u8         reserved_2[0x40];
6559
6560         struct mlx5_ifc_eqc_bits eq_context_entry;
6561
6562         u8         reserved_3[0x40];
6563
6564         u8         event_bitmask[0x40];
6565
6566         u8         reserved_4[0x580];
6567
6568         u8         pas[0][0x40];
6569 };
6570
6571 struct mlx5_ifc_create_dct_out_bits {
6572         u8         status[0x8];
6573         u8         reserved_0[0x18];
6574
6575         u8         syndrome[0x20];
6576
6577         u8         reserved_1[0x8];
6578         u8         dctn[0x18];
6579
6580         u8         reserved_2[0x20];
6581 };
6582
6583 struct mlx5_ifc_create_dct_in_bits {
6584         u8         opcode[0x10];
6585         u8         reserved_0[0x10];
6586
6587         u8         reserved_1[0x10];
6588         u8         op_mod[0x10];
6589
6590         u8         reserved_2[0x40];
6591
6592         struct mlx5_ifc_dctc_bits dct_context_entry;
6593
6594         u8         reserved_3[0x180];
6595 };
6596
6597 struct mlx5_ifc_create_cq_out_bits {
6598         u8         status[0x8];
6599         u8         reserved_0[0x18];
6600
6601         u8         syndrome[0x20];
6602
6603         u8         reserved_1[0x8];
6604         u8         cqn[0x18];
6605
6606         u8         reserved_2[0x20];
6607 };
6608
6609 struct mlx5_ifc_create_cq_in_bits {
6610         u8         opcode[0x10];
6611         u8         reserved_0[0x10];
6612
6613         u8         reserved_1[0x10];
6614         u8         op_mod[0x10];
6615
6616         u8         reserved_2[0x40];
6617
6618         struct mlx5_ifc_cqc_bits cq_context;
6619
6620         u8         reserved_3[0x600];
6621
6622         u8         pas[0][0x40];
6623 };
6624
6625 struct mlx5_ifc_config_int_moderation_out_bits {
6626         u8         status[0x8];
6627         u8         reserved_0[0x18];
6628
6629         u8         syndrome[0x20];
6630
6631         u8         reserved_1[0x4];
6632         u8         min_delay[0xc];
6633         u8         int_vector[0x10];
6634
6635         u8         reserved_2[0x20];
6636 };
6637
6638 enum {
6639         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6640         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6641 };
6642
6643 struct mlx5_ifc_config_int_moderation_in_bits {
6644         u8         opcode[0x10];
6645         u8         reserved_0[0x10];
6646
6647         u8         reserved_1[0x10];
6648         u8         op_mod[0x10];
6649
6650         u8         reserved_2[0x4];
6651         u8         min_delay[0xc];
6652         u8         int_vector[0x10];
6653
6654         u8         reserved_3[0x20];
6655 };
6656
6657 struct mlx5_ifc_attach_to_mcg_out_bits {
6658         u8         status[0x8];
6659         u8         reserved_0[0x18];
6660
6661         u8         syndrome[0x20];
6662
6663         u8         reserved_1[0x40];
6664 };
6665
6666 struct mlx5_ifc_attach_to_mcg_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_0[0x10];
6669
6670         u8         reserved_1[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         reserved_2[0x8];
6674         u8         qpn[0x18];
6675
6676         u8         reserved_3[0x20];
6677
6678         u8         multicast_gid[16][0x8];
6679 };
6680
6681 struct mlx5_ifc_arm_xrc_srq_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_0[0x18];
6684
6685         u8         syndrome[0x20];
6686
6687         u8         reserved_1[0x40];
6688 };
6689
6690 enum {
6691         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6692 };
6693
6694 struct mlx5_ifc_arm_xrc_srq_in_bits {
6695         u8         opcode[0x10];
6696         u8         reserved_0[0x10];
6697
6698         u8         reserved_1[0x10];
6699         u8         op_mod[0x10];
6700
6701         u8         reserved_2[0x8];
6702         u8         xrc_srqn[0x18];
6703
6704         u8         reserved_3[0x10];
6705         u8         lwm[0x10];
6706 };
6707
6708 struct mlx5_ifc_arm_rq_out_bits {
6709         u8         status[0x8];
6710         u8         reserved_0[0x18];
6711
6712         u8         syndrome[0x20];
6713
6714         u8         reserved_1[0x40];
6715 };
6716
6717 enum {
6718         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
6719 };
6720
6721 struct mlx5_ifc_arm_rq_in_bits {
6722         u8         opcode[0x10];
6723         u8         reserved_0[0x10];
6724
6725         u8         reserved_1[0x10];
6726         u8         op_mod[0x10];
6727
6728         u8         reserved_2[0x8];
6729         u8         srq_number[0x18];
6730
6731         u8         reserved_3[0x10];
6732         u8         lwm[0x10];
6733 };
6734
6735 struct mlx5_ifc_arm_dct_out_bits {
6736         u8         status[0x8];
6737         u8         reserved_0[0x18];
6738
6739         u8         syndrome[0x20];
6740
6741         u8         reserved_1[0x40];
6742 };
6743
6744 struct mlx5_ifc_arm_dct_in_bits {
6745         u8         opcode[0x10];
6746         u8         reserved_0[0x10];
6747
6748         u8         reserved_1[0x10];
6749         u8         op_mod[0x10];
6750
6751         u8         reserved_2[0x8];
6752         u8         dctn[0x18];
6753
6754         u8         reserved_3[0x20];
6755 };
6756
6757 struct mlx5_ifc_alloc_xrcd_out_bits {
6758         u8         status[0x8];
6759         u8         reserved_0[0x18];
6760
6761         u8         syndrome[0x20];
6762
6763         u8         reserved_1[0x8];
6764         u8         xrcd[0x18];
6765
6766         u8         reserved_2[0x20];
6767 };
6768
6769 struct mlx5_ifc_alloc_xrcd_in_bits {
6770         u8         opcode[0x10];
6771         u8         reserved_0[0x10];
6772
6773         u8         reserved_1[0x10];
6774         u8         op_mod[0x10];
6775
6776         u8         reserved_2[0x40];
6777 };
6778
6779 struct mlx5_ifc_alloc_uar_out_bits {
6780         u8         status[0x8];
6781         u8         reserved_0[0x18];
6782
6783         u8         syndrome[0x20];
6784
6785         u8         reserved_1[0x8];
6786         u8         uar[0x18];
6787
6788         u8         reserved_2[0x20];
6789 };
6790
6791 struct mlx5_ifc_alloc_uar_in_bits {
6792         u8         opcode[0x10];
6793         u8         reserved_0[0x10];
6794
6795         u8         reserved_1[0x10];
6796         u8         op_mod[0x10];
6797
6798         u8         reserved_2[0x40];
6799 };
6800
6801 struct mlx5_ifc_alloc_transport_domain_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_0[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_1[0x8];
6808         u8         transport_domain[0x18];
6809
6810         u8         reserved_2[0x20];
6811 };
6812
6813 struct mlx5_ifc_alloc_transport_domain_in_bits {
6814         u8         opcode[0x10];
6815         u8         reserved_0[0x10];
6816
6817         u8         reserved_1[0x10];
6818         u8         op_mod[0x10];
6819
6820         u8         reserved_2[0x40];
6821 };
6822
6823 struct mlx5_ifc_alloc_q_counter_out_bits {
6824         u8         status[0x8];
6825         u8         reserved_0[0x18];
6826
6827         u8         syndrome[0x20];
6828
6829         u8         reserved_1[0x18];
6830         u8         counter_set_id[0x8];
6831
6832         u8         reserved_2[0x20];
6833 };
6834
6835 struct mlx5_ifc_alloc_q_counter_in_bits {
6836         u8         opcode[0x10];
6837         u8         reserved_0[0x10];
6838
6839         u8         reserved_1[0x10];
6840         u8         op_mod[0x10];
6841
6842         u8         reserved_2[0x40];
6843 };
6844
6845 struct mlx5_ifc_alloc_pd_out_bits {
6846         u8         status[0x8];
6847         u8         reserved_0[0x18];
6848
6849         u8         syndrome[0x20];
6850
6851         u8         reserved_1[0x8];
6852         u8         pd[0x18];
6853
6854         u8         reserved_2[0x20];
6855 };
6856
6857 struct mlx5_ifc_alloc_pd_in_bits {
6858         u8         opcode[0x10];
6859         u8         reserved_0[0x10];
6860
6861         u8         reserved_1[0x10];
6862         u8         op_mod[0x10];
6863
6864         u8         reserved_2[0x40];
6865 };
6866
6867 struct mlx5_ifc_alloc_flow_counter_out_bits {
6868         u8         status[0x8];
6869         u8         reserved_0[0x18];
6870
6871         u8         syndrome[0x20];
6872
6873         u8         reserved_1[0x10];
6874         u8         flow_counter_id[0x10];
6875
6876         u8         reserved_2[0x20];
6877 };
6878
6879 struct mlx5_ifc_alloc_flow_counter_in_bits {
6880         u8         opcode[0x10];
6881         u8         reserved_0[0x10];
6882
6883         u8         reserved_1[0x10];
6884         u8         op_mod[0x10];
6885
6886         u8         reserved_2[0x40];
6887 };
6888
6889 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6890         u8         status[0x8];
6891         u8         reserved_0[0x18];
6892
6893         u8         syndrome[0x20];
6894
6895         u8         reserved_1[0x40];
6896 };
6897
6898 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6899         u8         opcode[0x10];
6900         u8         reserved_0[0x10];
6901
6902         u8         reserved_1[0x10];
6903         u8         op_mod[0x10];
6904
6905         u8         reserved_2[0x20];
6906
6907         u8         reserved_3[0x10];
6908         u8         vxlan_udp_port[0x10];
6909 };
6910
6911 struct mlx5_ifc_activate_tracer_out_bits {
6912         u8         status[0x8];
6913         u8         reserved_0[0x18];
6914
6915         u8         syndrome[0x20];
6916
6917         u8         reserved_1[0x40];
6918 };
6919
6920 struct mlx5_ifc_activate_tracer_in_bits {
6921         u8         opcode[0x10];
6922         u8         reserved_0[0x10];
6923
6924         u8         reserved_1[0x10];
6925         u8         op_mod[0x10];
6926
6927         u8         mkey[0x20];
6928
6929         u8         reserved_2[0x20];
6930 };
6931
6932 struct mlx5_ifc_set_rate_limit_out_bits {
6933         u8         status[0x8];
6934         u8         reserved_at_8[0x18];
6935
6936         u8         syndrome[0x20];
6937
6938         u8         reserved_at_40[0x40];
6939 };
6940
6941 struct mlx5_ifc_set_rate_limit_in_bits {
6942         u8         opcode[0x10];
6943         u8         reserved_at_10[0x10];
6944
6945         u8         reserved_at_20[0x10];
6946         u8         op_mod[0x10];
6947
6948         u8         reserved_at_40[0x10];
6949         u8         rate_limit_index[0x10];
6950
6951         u8         reserved_at_60[0x20];
6952
6953         u8         rate_limit[0x20];
6954 };
6955
6956 struct mlx5_ifc_access_register_out_bits {
6957         u8         status[0x8];
6958         u8         reserved_0[0x18];
6959
6960         u8         syndrome[0x20];
6961
6962         u8         reserved_1[0x40];
6963
6964         u8         register_data[0][0x20];
6965 };
6966
6967 enum {
6968         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6969         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6970 };
6971
6972 struct mlx5_ifc_access_register_in_bits {
6973         u8         opcode[0x10];
6974         u8         reserved_0[0x10];
6975
6976         u8         reserved_1[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_2[0x10];
6980         u8         register_id[0x10];
6981
6982         u8         argument[0x20];
6983
6984         u8         register_data[0][0x20];
6985 };
6986
6987 struct mlx5_ifc_sltp_reg_bits {
6988         u8         status[0x4];
6989         u8         version[0x4];
6990         u8         local_port[0x8];
6991         u8         pnat[0x2];
6992         u8         reserved_0[0x2];
6993         u8         lane[0x4];
6994         u8         reserved_1[0x8];
6995
6996         u8         reserved_2[0x20];
6997
6998         u8         reserved_3[0x7];
6999         u8         polarity[0x1];
7000         u8         ob_tap0[0x8];
7001         u8         ob_tap1[0x8];
7002         u8         ob_tap2[0x8];
7003
7004         u8         reserved_4[0xc];
7005         u8         ob_preemp_mode[0x4];
7006         u8         ob_reg[0x8];
7007         u8         ob_bias[0x8];
7008
7009         u8         reserved_5[0x20];
7010 };
7011
7012 struct mlx5_ifc_slrp_reg_bits {
7013         u8         status[0x4];
7014         u8         version[0x4];
7015         u8         local_port[0x8];
7016         u8         pnat[0x2];
7017         u8         reserved_0[0x2];
7018         u8         lane[0x4];
7019         u8         reserved_1[0x8];
7020
7021         u8         ib_sel[0x2];
7022         u8         reserved_2[0x11];
7023         u8         dp_sel[0x1];
7024         u8         dp90sel[0x4];
7025         u8         mix90phase[0x8];
7026
7027         u8         ffe_tap0[0x8];
7028         u8         ffe_tap1[0x8];
7029         u8         ffe_tap2[0x8];
7030         u8         ffe_tap3[0x8];
7031
7032         u8         ffe_tap4[0x8];
7033         u8         ffe_tap5[0x8];
7034         u8         ffe_tap6[0x8];
7035         u8         ffe_tap7[0x8];
7036
7037         u8         ffe_tap8[0x8];
7038         u8         mixerbias_tap_amp[0x8];
7039         u8         reserved_3[0x7];
7040         u8         ffe_tap_en[0x9];
7041
7042         u8         ffe_tap_offset0[0x8];
7043         u8         ffe_tap_offset1[0x8];
7044         u8         slicer_offset0[0x10];
7045
7046         u8         mixer_offset0[0x10];
7047         u8         mixer_offset1[0x10];
7048
7049         u8         mixerbgn_inp[0x8];
7050         u8         mixerbgn_inn[0x8];
7051         u8         mixerbgn_refp[0x8];
7052         u8         mixerbgn_refn[0x8];
7053
7054         u8         sel_slicer_lctrl_h[0x1];
7055         u8         sel_slicer_lctrl_l[0x1];
7056         u8         reserved_4[0x1];
7057         u8         ref_mixer_vreg[0x5];
7058         u8         slicer_gctrl[0x8];
7059         u8         lctrl_input[0x8];
7060         u8         mixer_offset_cm1[0x8];
7061
7062         u8         common_mode[0x6];
7063         u8         reserved_5[0x1];
7064         u8         mixer_offset_cm0[0x9];
7065         u8         reserved_6[0x7];
7066         u8         slicer_offset_cm[0x9];
7067 };
7068
7069 struct mlx5_ifc_slrg_reg_bits {
7070         u8         status[0x4];
7071         u8         version[0x4];
7072         u8         local_port[0x8];
7073         u8         pnat[0x2];
7074         u8         reserved_0[0x2];
7075         u8         lane[0x4];
7076         u8         reserved_1[0x8];
7077
7078         u8         time_to_link_up[0x10];
7079         u8         reserved_2[0xc];
7080         u8         grade_lane_speed[0x4];
7081
7082         u8         grade_version[0x8];
7083         u8         grade[0x18];
7084
7085         u8         reserved_3[0x4];
7086         u8         height_grade_type[0x4];
7087         u8         height_grade[0x18];
7088
7089         u8         height_dz[0x10];
7090         u8         height_dv[0x10];
7091
7092         u8         reserved_4[0x10];
7093         u8         height_sigma[0x10];
7094
7095         u8         reserved_5[0x20];
7096
7097         u8         reserved_6[0x4];
7098         u8         phase_grade_type[0x4];
7099         u8         phase_grade[0x18];
7100
7101         u8         reserved_7[0x8];
7102         u8         phase_eo_pos[0x8];
7103         u8         reserved_8[0x8];
7104         u8         phase_eo_neg[0x8];
7105
7106         u8         ffe_set_tested[0x10];
7107         u8         test_errors_per_lane[0x10];
7108 };
7109
7110 struct mlx5_ifc_pvlc_reg_bits {
7111         u8         reserved_0[0x8];
7112         u8         local_port[0x8];
7113         u8         reserved_1[0x10];
7114
7115         u8         reserved_2[0x1c];
7116         u8         vl_hw_cap[0x4];
7117
7118         u8         reserved_3[0x1c];
7119         u8         vl_admin[0x4];
7120
7121         u8         reserved_4[0x1c];
7122         u8         vl_operational[0x4];
7123 };
7124
7125 struct mlx5_ifc_pude_reg_bits {
7126         u8         swid[0x8];
7127         u8         local_port[0x8];
7128         u8         reserved_0[0x4];
7129         u8         admin_status[0x4];
7130         u8         reserved_1[0x4];
7131         u8         oper_status[0x4];
7132
7133         u8         reserved_2[0x60];
7134 };
7135
7136 enum {
7137         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7138         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7139 };
7140
7141 struct mlx5_ifc_ptys_reg_bits {
7142         u8         reserved_0[0x1];
7143         u8         an_disable_admin[0x1];
7144         u8         an_disable_cap[0x1];
7145         u8         reserved_1[0x4];
7146         u8         force_tx_aba_param[0x1];
7147         u8         local_port[0x8];
7148         u8         reserved_2[0xd];
7149         u8         proto_mask[0x3];
7150
7151         u8         an_status[0x4];
7152         u8         reserved_3[0xc];
7153         u8         data_rate_oper[0x10];
7154
7155         u8         fc_proto_capability[0x20];
7156
7157         u8         eth_proto_capability[0x20];
7158
7159         u8         ib_link_width_capability[0x10];
7160         u8         ib_proto_capability[0x10];
7161
7162         u8         fc_proto_admin[0x20];
7163
7164         u8         eth_proto_admin[0x20];
7165
7166         u8         ib_link_width_admin[0x10];
7167         u8         ib_proto_admin[0x10];
7168
7169         u8         fc_proto_oper[0x20];
7170
7171         u8         eth_proto_oper[0x20];
7172
7173         u8         ib_link_width_oper[0x10];
7174         u8         ib_proto_oper[0x10];
7175
7176         u8         reserved_4[0x20];
7177
7178         u8         eth_proto_lp_advertise[0x20];
7179
7180         u8         reserved_5[0x60];
7181 };
7182
7183 struct mlx5_ifc_ptas_reg_bits {
7184         u8         reserved_0[0x20];
7185
7186         u8         algorithm_options[0x10];
7187         u8         reserved_1[0x4];
7188         u8         repetitions_mode[0x4];
7189         u8         num_of_repetitions[0x8];
7190
7191         u8         grade_version[0x8];
7192         u8         height_grade_type[0x4];
7193         u8         phase_grade_type[0x4];
7194         u8         height_grade_weight[0x8];
7195         u8         phase_grade_weight[0x8];
7196
7197         u8         gisim_measure_bits[0x10];
7198         u8         adaptive_tap_measure_bits[0x10];
7199
7200         u8         ber_bath_high_error_threshold[0x10];
7201         u8         ber_bath_mid_error_threshold[0x10];
7202
7203         u8         ber_bath_low_error_threshold[0x10];
7204         u8         one_ratio_high_threshold[0x10];
7205
7206         u8         one_ratio_high_mid_threshold[0x10];
7207         u8         one_ratio_low_mid_threshold[0x10];
7208
7209         u8         one_ratio_low_threshold[0x10];
7210         u8         ndeo_error_threshold[0x10];
7211
7212         u8         mixer_offset_step_size[0x10];
7213         u8         reserved_2[0x8];
7214         u8         mix90_phase_for_voltage_bath[0x8];
7215
7216         u8         mixer_offset_start[0x10];
7217         u8         mixer_offset_end[0x10];
7218
7219         u8         reserved_3[0x15];
7220         u8         ber_test_time[0xb];
7221 };
7222
7223 struct mlx5_ifc_pspa_reg_bits {
7224         u8         swid[0x8];
7225         u8         local_port[0x8];
7226         u8         sub_port[0x8];
7227         u8         reserved_0[0x8];
7228
7229         u8         reserved_1[0x20];
7230 };
7231
7232 struct mlx5_ifc_ppsc_reg_bits {
7233         u8         reserved_0[0x8];
7234         u8         local_port[0x8];
7235         u8         reserved_1[0x10];
7236
7237         u8         reserved_2[0x60];
7238
7239         u8         reserved_3[0x1c];
7240         u8         wrps_admin[0x4];
7241
7242         u8         reserved_4[0x1c];
7243         u8         wrps_status[0x4];
7244
7245         u8         up_th_vld[0x1];
7246         u8         down_th_vld[0x1];
7247         u8         reserved_5[0x6];
7248         u8         up_threshold[0x8];
7249         u8         reserved_6[0x8];
7250         u8         down_threshold[0x8];
7251
7252         u8         reserved_7[0x20];
7253
7254         u8         reserved_8[0x1c];
7255         u8         srps_admin[0x4];
7256
7257         u8         reserved_9[0x60];
7258 };
7259
7260 struct mlx5_ifc_pplr_reg_bits {
7261         u8         reserved_0[0x8];
7262         u8         local_port[0x8];
7263         u8         reserved_1[0x10];
7264
7265         u8         reserved_2[0x8];
7266         u8         lb_cap[0x8];
7267         u8         reserved_3[0x8];
7268         u8         lb_en[0x8];
7269 };
7270
7271 struct mlx5_ifc_pplm_reg_bits {
7272         u8         reserved_0[0x8];
7273         u8         local_port[0x8];
7274         u8         reserved_1[0x10];
7275
7276         u8         reserved_2[0x20];
7277
7278         u8         port_profile_mode[0x8];
7279         u8         static_port_profile[0x8];
7280         u8         active_port_profile[0x8];
7281         u8         reserved_3[0x8];
7282
7283         u8         retransmission_active[0x8];
7284         u8         fec_mode_active[0x18];
7285
7286         u8         reserved_4[0x10];
7287         u8         v_100g_fec_override_cap[0x4];
7288         u8         v_50g_fec_override_cap[0x4];
7289         u8         v_25g_fec_override_cap[0x4];
7290         u8         v_10g_40g_fec_override_cap[0x4];
7291
7292         u8         reserved_5[0x10];
7293         u8         v_100g_fec_override_admin[0x4];
7294         u8         v_50g_fec_override_admin[0x4];
7295         u8         v_25g_fec_override_admin[0x4];
7296         u8         v_10g_40g_fec_override_admin[0x4];
7297 };
7298
7299 struct mlx5_ifc_ppll_reg_bits {
7300         u8         num_pll_groups[0x8];
7301         u8         pll_group[0x8];
7302         u8         reserved_0[0x4];
7303         u8         num_plls[0x4];
7304         u8         reserved_1[0x8];
7305
7306         u8         reserved_2[0x1f];
7307         u8         ae[0x1];
7308
7309         u8         pll_status[4][0x40];
7310 };
7311
7312 struct mlx5_ifc_ppad_reg_bits {
7313         u8         reserved_0[0x3];
7314         u8         single_mac[0x1];
7315         u8         reserved_1[0x4];
7316         u8         local_port[0x8];
7317         u8         mac_47_32[0x10];
7318
7319         u8         mac_31_0[0x20];
7320
7321         u8         reserved_2[0x40];
7322 };
7323
7324 struct mlx5_ifc_pmtu_reg_bits {
7325         u8         reserved_0[0x8];
7326         u8         local_port[0x8];
7327         u8         reserved_1[0x10];
7328
7329         u8         max_mtu[0x10];
7330         u8         reserved_2[0x10];
7331
7332         u8         admin_mtu[0x10];
7333         u8         reserved_3[0x10];
7334
7335         u8         oper_mtu[0x10];
7336         u8         reserved_4[0x10];
7337 };
7338
7339 struct mlx5_ifc_pmpr_reg_bits {
7340         u8         reserved_0[0x8];
7341         u8         module[0x8];
7342         u8         reserved_1[0x10];
7343
7344         u8         reserved_2[0x18];
7345         u8         attenuation_5g[0x8];
7346
7347         u8         reserved_3[0x18];
7348         u8         attenuation_7g[0x8];
7349
7350         u8         reserved_4[0x18];
7351         u8         attenuation_12g[0x8];
7352 };
7353
7354 struct mlx5_ifc_pmpe_reg_bits {
7355         u8         reserved_0[0x8];
7356         u8         module[0x8];
7357         u8         reserved_1[0xc];
7358         u8         module_status[0x4];
7359
7360         u8         reserved_2[0x14];
7361         u8         error_type[0x4];
7362         u8         reserved_3[0x8];
7363
7364         u8         reserved_4[0x40];
7365 };
7366
7367 struct mlx5_ifc_pmpc_reg_bits {
7368         u8         module_state_updated[32][0x8];
7369 };
7370
7371 struct mlx5_ifc_pmlpn_reg_bits {
7372         u8         reserved_0[0x4];
7373         u8         mlpn_status[0x4];
7374         u8         local_port[0x8];
7375         u8         reserved_1[0x10];
7376
7377         u8         e[0x1];
7378         u8         reserved_2[0x1f];
7379 };
7380
7381 struct mlx5_ifc_pmlp_reg_bits {
7382         u8         rxtx[0x1];
7383         u8         reserved_0[0x7];
7384         u8         local_port[0x8];
7385         u8         reserved_1[0x8];
7386         u8         width[0x8];
7387
7388         u8         lane0_module_mapping[0x20];
7389
7390         u8         lane1_module_mapping[0x20];
7391
7392         u8         lane2_module_mapping[0x20];
7393
7394         u8         lane3_module_mapping[0x20];
7395
7396         u8         reserved_2[0x160];
7397 };
7398
7399 struct mlx5_ifc_pmaos_reg_bits {
7400         u8         reserved_0[0x8];
7401         u8         module[0x8];
7402         u8         reserved_1[0x4];
7403         u8         admin_status[0x4];
7404         u8         reserved_2[0x4];
7405         u8         oper_status[0x4];
7406
7407         u8         ase[0x1];
7408         u8         ee[0x1];
7409         u8         reserved_3[0x12];
7410         u8         error_type[0x4];
7411         u8         reserved_4[0x6];
7412         u8         e[0x2];
7413
7414         u8         reserved_5[0x40];
7415 };
7416
7417 struct mlx5_ifc_plpc_reg_bits {
7418         u8         reserved_0[0x4];
7419         u8         profile_id[0xc];
7420         u8         reserved_1[0x4];
7421         u8         proto_mask[0x4];
7422         u8         reserved_2[0x8];
7423
7424         u8         reserved_3[0x10];
7425         u8         lane_speed[0x10];
7426
7427         u8         reserved_4[0x17];
7428         u8         lpbf[0x1];
7429         u8         fec_mode_policy[0x8];
7430
7431         u8         retransmission_capability[0x8];
7432         u8         fec_mode_capability[0x18];
7433
7434         u8         retransmission_support_admin[0x8];
7435         u8         fec_mode_support_admin[0x18];
7436
7437         u8         retransmission_request_admin[0x8];
7438         u8         fec_mode_request_admin[0x18];
7439
7440         u8         reserved_5[0x80];
7441 };
7442
7443 struct mlx5_ifc_pll_status_data_bits {
7444         u8         reserved_0[0x1];
7445         u8         lock_cal[0x1];
7446         u8         lock_status[0x2];
7447         u8         reserved_1[0x2];
7448         u8         algo_f_ctrl[0xa];
7449         u8         analog_algo_num_var[0x6];
7450         u8         f_ctrl_measure[0xa];
7451
7452         u8         reserved_2[0x2];
7453         u8         analog_var[0x6];
7454         u8         reserved_3[0x2];
7455         u8         high_var[0x6];
7456         u8         reserved_4[0x2];
7457         u8         low_var[0x6];
7458         u8         reserved_5[0x2];
7459         u8         mid_val[0x6];
7460 };
7461
7462 struct mlx5_ifc_plib_reg_bits {
7463         u8         reserved_0[0x8];
7464         u8         local_port[0x8];
7465         u8         reserved_1[0x8];
7466         u8         ib_port[0x8];
7467
7468         u8         reserved_2[0x60];
7469 };
7470
7471 struct mlx5_ifc_plbf_reg_bits {
7472         u8         reserved_0[0x8];
7473         u8         local_port[0x8];
7474         u8         reserved_1[0xd];
7475         u8         lbf_mode[0x3];
7476
7477         u8         reserved_2[0x20];
7478 };
7479
7480 struct mlx5_ifc_pipg_reg_bits {
7481         u8         reserved_0[0x8];
7482         u8         local_port[0x8];
7483         u8         reserved_1[0x10];
7484
7485         u8         dic[0x1];
7486         u8         reserved_2[0x19];
7487         u8         ipg[0x4];
7488         u8         reserved_3[0x2];
7489 };
7490
7491 struct mlx5_ifc_pifr_reg_bits {
7492         u8         reserved_0[0x8];
7493         u8         local_port[0x8];
7494         u8         reserved_1[0x10];
7495
7496         u8         reserved_2[0xe0];
7497
7498         u8         port_filter[8][0x20];
7499
7500         u8         port_filter_update_en[8][0x20];
7501 };
7502
7503 struct mlx5_ifc_phys_layer_cntrs_bits {
7504         u8         time_since_last_clear_high[0x20];
7505
7506         u8         time_since_last_clear_low[0x20];
7507
7508         u8         symbol_errors_high[0x20];
7509
7510         u8         symbol_errors_low[0x20];
7511
7512         u8         sync_headers_errors_high[0x20];
7513
7514         u8         sync_headers_errors_low[0x20];
7515
7516         u8         edpl_bip_errors_lane0_high[0x20];
7517
7518         u8         edpl_bip_errors_lane0_low[0x20];
7519
7520         u8         edpl_bip_errors_lane1_high[0x20];
7521
7522         u8         edpl_bip_errors_lane1_low[0x20];
7523
7524         u8         edpl_bip_errors_lane2_high[0x20];
7525
7526         u8         edpl_bip_errors_lane2_low[0x20];
7527
7528         u8         edpl_bip_errors_lane3_high[0x20];
7529
7530         u8         edpl_bip_errors_lane3_low[0x20];
7531
7532         u8         fc_fec_corrected_blocks_lane0_high[0x20];
7533
7534         u8         fc_fec_corrected_blocks_lane0_low[0x20];
7535
7536         u8         fc_fec_corrected_blocks_lane1_high[0x20];
7537
7538         u8         fc_fec_corrected_blocks_lane1_low[0x20];
7539
7540         u8         fc_fec_corrected_blocks_lane2_high[0x20];
7541
7542         u8         fc_fec_corrected_blocks_lane2_low[0x20];
7543
7544         u8         fc_fec_corrected_blocks_lane3_high[0x20];
7545
7546         u8         fc_fec_corrected_blocks_lane3_low[0x20];
7547
7548         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
7549
7550         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
7551
7552         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
7553
7554         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
7555
7556         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
7557
7558         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
7559
7560         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
7561
7562         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
7563
7564         u8         rs_fec_corrected_blocks_high[0x20];
7565
7566         u8         rs_fec_corrected_blocks_low[0x20];
7567
7568         u8         rs_fec_uncorrectable_blocks_high[0x20];
7569
7570         u8         rs_fec_uncorrectable_blocks_low[0x20];
7571
7572         u8         rs_fec_no_errors_blocks_high[0x20];
7573
7574         u8         rs_fec_no_errors_blocks_low[0x20];
7575
7576         u8         rs_fec_single_error_blocks_high[0x20];
7577
7578         u8         rs_fec_single_error_blocks_low[0x20];
7579
7580         u8         rs_fec_corrected_symbols_total_high[0x20];
7581
7582         u8         rs_fec_corrected_symbols_total_low[0x20];
7583
7584         u8         rs_fec_corrected_symbols_lane0_high[0x20];
7585
7586         u8         rs_fec_corrected_symbols_lane0_low[0x20];
7587
7588         u8         rs_fec_corrected_symbols_lane1_high[0x20];
7589
7590         u8         rs_fec_corrected_symbols_lane1_low[0x20];
7591
7592         u8         rs_fec_corrected_symbols_lane2_high[0x20];
7593
7594         u8         rs_fec_corrected_symbols_lane2_low[0x20];
7595
7596         u8         rs_fec_corrected_symbols_lane3_high[0x20];
7597
7598         u8         rs_fec_corrected_symbols_lane3_low[0x20];
7599
7600         u8         link_down_events[0x20];
7601
7602         u8         successful_recovery_events[0x20];
7603
7604         u8         reserved_0[0x180];
7605 };
7606
7607 struct mlx5_ifc_phrr_reg_bits {
7608         u8         clr[0x1];
7609         u8         reserved_0[0x7];
7610         u8         local_port[0x8];
7611         u8         reserved_1[0x10];
7612
7613         u8         hist_group[0x8];
7614         u8         reserved_2[0x10];
7615         u8         hist_id[0x8];
7616
7617         u8         reserved_3[0x40];
7618
7619         u8         time_since_last_clear_high[0x20];
7620
7621         u8         time_since_last_clear_low[0x20];
7622
7623         u8         bin[10][0x20];
7624 };
7625
7626 struct mlx5_ifc_phbr_for_prio_reg_bits {
7627         u8         reserved_0[0x18];
7628         u8         prio[0x8];
7629 };
7630
7631 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
7632         u8         reserved_0[0x18];
7633         u8         tclass[0x8];
7634 };
7635
7636 struct mlx5_ifc_phbr_binding_reg_bits {
7637         u8         opcode[0x4];
7638         u8         reserved_0[0x4];
7639         u8         local_port[0x8];
7640         u8         pnat[0x2];
7641         u8         reserved_1[0xe];
7642
7643         u8         hist_group[0x8];
7644         u8         reserved_2[0x10];
7645         u8         hist_id[0x8];
7646
7647         u8         reserved_3[0x10];
7648         u8         hist_type[0x10];
7649
7650         u8         hist_parameters[0x20];
7651
7652         u8         hist_min_value[0x20];
7653
7654         u8         hist_max_value[0x20];
7655
7656         u8         sample_time[0x20];
7657 };
7658
7659 enum {
7660         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
7661         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
7662 };
7663
7664 struct mlx5_ifc_pfcc_reg_bits {
7665         u8         dcbx_operation_type[0x2];
7666         u8         cap_local_admin[0x1];
7667         u8         cap_remote_admin[0x1];
7668         u8         reserved_0[0x4];
7669         u8         local_port[0x8];
7670         u8         pnat[0x2];
7671         u8         reserved_1[0xc];
7672         u8         shl_cap[0x1];
7673         u8         shl_opr[0x1];
7674
7675         u8         ppan[0x4];
7676         u8         reserved_2[0x4];
7677         u8         prio_mask_tx[0x8];
7678         u8         reserved_3[0x8];
7679         u8         prio_mask_rx[0x8];
7680
7681         u8         pptx[0x1];
7682         u8         aptx[0x1];
7683         u8         reserved_4[0x6];
7684         u8         pfctx[0x8];
7685         u8         reserved_5[0x8];
7686         u8         cbftx[0x8];
7687
7688         u8         pprx[0x1];
7689         u8         aprx[0x1];
7690         u8         reserved_6[0x6];
7691         u8         pfcrx[0x8];
7692         u8         reserved_7[0x8];
7693         u8         cbfrx[0x8];
7694
7695         u8         reserved_8[0x80];
7696 };
7697
7698 struct mlx5_ifc_pelc_reg_bits {
7699         u8         op[0x4];
7700         u8         reserved_0[0x4];
7701         u8         local_port[0x8];
7702         u8         reserved_1[0x10];
7703
7704         u8         op_admin[0x8];
7705         u8         op_capability[0x8];
7706         u8         op_request[0x8];
7707         u8         op_active[0x8];
7708
7709         u8         admin[0x40];
7710
7711         u8         capability[0x40];
7712
7713         u8         request[0x40];
7714
7715         u8         active[0x40];
7716
7717         u8         reserved_2[0x80];
7718 };
7719
7720 struct mlx5_ifc_peir_reg_bits {
7721         u8         reserved_0[0x8];
7722         u8         local_port[0x8];
7723         u8         reserved_1[0x10];
7724
7725         u8         reserved_2[0xc];
7726         u8         error_count[0x4];
7727         u8         reserved_3[0x10];
7728
7729         u8         reserved_4[0xc];
7730         u8         lane[0x4];
7731         u8         reserved_5[0x8];
7732         u8         error_type[0x8];
7733 };
7734
7735 struct mlx5_ifc_pcap_reg_bits {
7736         u8         reserved_0[0x8];
7737         u8         local_port[0x8];
7738         u8         reserved_1[0x10];
7739
7740         u8         port_capability_mask[4][0x20];
7741 };
7742
7743 struct mlx5_ifc_pbmc_reg_bits {
7744         u8         reserved_0[0x8];
7745         u8         local_port[0x8];
7746         u8         reserved_1[0x10];
7747
7748         u8         xoff_timer_value[0x10];
7749         u8         xoff_refresh[0x10];
7750
7751         u8         reserved_2[0x10];
7752         u8         port_buffer_size[0x10];
7753
7754         struct mlx5_ifc_bufferx_reg_bits buffer[10];
7755
7756         u8         reserved_3[0x40];
7757
7758         u8         port_shared_buffer[0x40];
7759 };
7760
7761 struct mlx5_ifc_paos_reg_bits {
7762         u8         swid[0x8];
7763         u8         local_port[0x8];
7764         u8         reserved_0[0x4];
7765         u8         admin_status[0x4];
7766         u8         reserved_1[0x4];
7767         u8         oper_status[0x4];
7768
7769         u8         ase[0x1];
7770         u8         ee[0x1];
7771         u8         reserved_2[0x1c];
7772         u8         e[0x2];
7773
7774         u8         reserved_3[0x40];
7775 };
7776
7777 struct mlx5_ifc_pamp_reg_bits {
7778         u8         reserved_0[0x8];
7779         u8         opamp_group[0x8];
7780         u8         reserved_1[0xc];
7781         u8         opamp_group_type[0x4];
7782
7783         u8         start_index[0x10];
7784         u8         reserved_2[0x4];
7785         u8         num_of_indices[0xc];
7786
7787         u8         index_data[18][0x10];
7788 };
7789
7790 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
7791         u8         llr_rx_cells_high[0x20];
7792
7793         u8         llr_rx_cells_low[0x20];
7794
7795         u8         llr_rx_error_high[0x20];
7796
7797         u8         llr_rx_error_low[0x20];
7798
7799         u8         llr_rx_crc_error_high[0x20];
7800
7801         u8         llr_rx_crc_error_low[0x20];
7802
7803         u8         llr_tx_cells_high[0x20];
7804
7805         u8         llr_tx_cells_low[0x20];
7806
7807         u8         llr_tx_ret_cells_high[0x20];
7808
7809         u8         llr_tx_ret_cells_low[0x20];
7810
7811         u8         llr_tx_ret_events_high[0x20];
7812
7813         u8         llr_tx_ret_events_low[0x20];
7814
7815         u8         reserved_0[0x640];
7816 };
7817
7818 struct mlx5_ifc_lane_2_module_mapping_bits {
7819         u8         reserved_0[0x6];
7820         u8         rx_lane[0x2];
7821         u8         reserved_1[0x6];
7822         u8         tx_lane[0x2];
7823         u8         reserved_2[0x8];
7824         u8         module[0x8];
7825 };
7826
7827 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
7828         u8         transmit_queue_high[0x20];
7829
7830         u8         transmit_queue_low[0x20];
7831
7832         u8         reserved_0[0x780];
7833 };
7834
7835 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
7836         u8         no_buffer_discard_uc_high[0x20];
7837
7838         u8         no_buffer_discard_uc_low[0x20];
7839
7840         u8         wred_discard_high[0x20];
7841
7842         u8         wred_discard_low[0x20];
7843
7844         u8         reserved_0[0x740];
7845 };
7846
7847 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
7848         u8         rx_octets_high[0x20];
7849
7850         u8         rx_octets_low[0x20];
7851
7852         u8         reserved_0[0xc0];
7853
7854         u8         rx_frames_high[0x20];
7855
7856         u8         rx_frames_low[0x20];
7857
7858         u8         tx_octets_high[0x20];
7859
7860         u8         tx_octets_low[0x20];
7861
7862         u8         reserved_1[0xc0];
7863
7864         u8         tx_frames_high[0x20];
7865
7866         u8         tx_frames_low[0x20];
7867
7868         u8         rx_pause_high[0x20];
7869
7870         u8         rx_pause_low[0x20];
7871
7872         u8         rx_pause_duration_high[0x20];
7873
7874         u8         rx_pause_duration_low[0x20];
7875
7876         u8         tx_pause_high[0x20];
7877
7878         u8         tx_pause_low[0x20];
7879
7880         u8         tx_pause_duration_high[0x20];
7881
7882         u8         tx_pause_duration_low[0x20];
7883
7884         u8         rx_pause_transition_high[0x20];
7885
7886         u8         rx_pause_transition_low[0x20];
7887
7888         u8         reserved_2[0x400];
7889 };
7890
7891 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
7892         u8         port_transmit_wait_high[0x20];
7893
7894         u8         port_transmit_wait_low[0x20];
7895
7896         u8         ecn_marked_high[0x20];
7897
7898         u8         ecn_marked_low[0x20];
7899
7900         u8         no_buffer_discard_mc_high[0x20];
7901
7902         u8         no_buffer_discard_mc_low[0x20];
7903
7904         u8         reserved_0[0x700];
7905 };
7906
7907 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
7908         u8         a_frames_transmitted_ok_high[0x20];
7909
7910         u8         a_frames_transmitted_ok_low[0x20];
7911
7912         u8         a_frames_received_ok_high[0x20];
7913
7914         u8         a_frames_received_ok_low[0x20];
7915
7916         u8         a_frame_check_sequence_errors_high[0x20];
7917
7918         u8         a_frame_check_sequence_errors_low[0x20];
7919
7920         u8         a_alignment_errors_high[0x20];
7921
7922         u8         a_alignment_errors_low[0x20];
7923
7924         u8         a_octets_transmitted_ok_high[0x20];
7925
7926         u8         a_octets_transmitted_ok_low[0x20];
7927
7928         u8         a_octets_received_ok_high[0x20];
7929
7930         u8         a_octets_received_ok_low[0x20];
7931
7932         u8         a_multicast_frames_xmitted_ok_high[0x20];
7933
7934         u8         a_multicast_frames_xmitted_ok_low[0x20];
7935
7936         u8         a_broadcast_frames_xmitted_ok_high[0x20];
7937
7938         u8         a_broadcast_frames_xmitted_ok_low[0x20];
7939
7940         u8         a_multicast_frames_received_ok_high[0x20];
7941
7942         u8         a_multicast_frames_received_ok_low[0x20];
7943
7944         u8         a_broadcast_frames_recieved_ok_high[0x20];
7945
7946         u8         a_broadcast_frames_recieved_ok_low[0x20];
7947
7948         u8         a_in_range_length_errors_high[0x20];
7949
7950         u8         a_in_range_length_errors_low[0x20];
7951
7952         u8         a_out_of_range_length_field_high[0x20];
7953
7954         u8         a_out_of_range_length_field_low[0x20];
7955
7956         u8         a_frame_too_long_errors_high[0x20];
7957
7958         u8         a_frame_too_long_errors_low[0x20];
7959
7960         u8         a_symbol_error_during_carrier_high[0x20];
7961
7962         u8         a_symbol_error_during_carrier_low[0x20];
7963
7964         u8         a_mac_control_frames_transmitted_high[0x20];
7965
7966         u8         a_mac_control_frames_transmitted_low[0x20];
7967
7968         u8         a_mac_control_frames_received_high[0x20];
7969
7970         u8         a_mac_control_frames_received_low[0x20];
7971
7972         u8         a_unsupported_opcodes_received_high[0x20];
7973
7974         u8         a_unsupported_opcodes_received_low[0x20];
7975
7976         u8         a_pause_mac_ctrl_frames_received_high[0x20];
7977
7978         u8         a_pause_mac_ctrl_frames_received_low[0x20];
7979
7980         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
7981
7982         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
7983
7984         u8         reserved_0[0x300];
7985 };
7986
7987 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
7988         u8         dot3stats_alignment_errors_high[0x20];
7989
7990         u8         dot3stats_alignment_errors_low[0x20];
7991
7992         u8         dot3stats_fcs_errors_high[0x20];
7993
7994         u8         dot3stats_fcs_errors_low[0x20];
7995
7996         u8         dot3stats_single_collision_frames_high[0x20];
7997
7998         u8         dot3stats_single_collision_frames_low[0x20];
7999
8000         u8         dot3stats_multiple_collision_frames_high[0x20];
8001
8002         u8         dot3stats_multiple_collision_frames_low[0x20];
8003
8004         u8         dot3stats_sqe_test_errors_high[0x20];
8005
8006         u8         dot3stats_sqe_test_errors_low[0x20];
8007
8008         u8         dot3stats_deferred_transmissions_high[0x20];
8009
8010         u8         dot3stats_deferred_transmissions_low[0x20];
8011
8012         u8         dot3stats_late_collisions_high[0x20];
8013
8014         u8         dot3stats_late_collisions_low[0x20];
8015
8016         u8         dot3stats_excessive_collisions_high[0x20];
8017
8018         u8         dot3stats_excessive_collisions_low[0x20];
8019
8020         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8021
8022         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8023
8024         u8         dot3stats_carrier_sense_errors_high[0x20];
8025
8026         u8         dot3stats_carrier_sense_errors_low[0x20];
8027
8028         u8         dot3stats_frame_too_longs_high[0x20];
8029
8030         u8         dot3stats_frame_too_longs_low[0x20];
8031
8032         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8033
8034         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8035
8036         u8         dot3stats_symbol_errors_high[0x20];
8037
8038         u8         dot3stats_symbol_errors_low[0x20];
8039
8040         u8         dot3control_in_unknown_opcodes_high[0x20];
8041
8042         u8         dot3control_in_unknown_opcodes_low[0x20];
8043
8044         u8         dot3in_pause_frames_high[0x20];
8045
8046         u8         dot3in_pause_frames_low[0x20];
8047
8048         u8         dot3out_pause_frames_high[0x20];
8049
8050         u8         dot3out_pause_frames_low[0x20];
8051
8052         u8         reserved_0[0x3c0];
8053 };
8054
8055 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8056         u8         if_in_octets_high[0x20];
8057
8058         u8         if_in_octets_low[0x20];
8059
8060         u8         if_in_ucast_pkts_high[0x20];
8061
8062         u8         if_in_ucast_pkts_low[0x20];
8063
8064         u8         if_in_discards_high[0x20];
8065
8066         u8         if_in_discards_low[0x20];
8067
8068         u8         if_in_errors_high[0x20];
8069
8070         u8         if_in_errors_low[0x20];
8071
8072         u8         if_in_unknown_protos_high[0x20];
8073
8074         u8         if_in_unknown_protos_low[0x20];
8075
8076         u8         if_out_octets_high[0x20];
8077
8078         u8         if_out_octets_low[0x20];
8079
8080         u8         if_out_ucast_pkts_high[0x20];
8081
8082         u8         if_out_ucast_pkts_low[0x20];
8083
8084         u8         if_out_discards_high[0x20];
8085
8086         u8         if_out_discards_low[0x20];
8087
8088         u8         if_out_errors_high[0x20];
8089
8090         u8         if_out_errors_low[0x20];
8091
8092         u8         if_in_multicast_pkts_high[0x20];
8093
8094         u8         if_in_multicast_pkts_low[0x20];
8095
8096         u8         if_in_broadcast_pkts_high[0x20];
8097
8098         u8         if_in_broadcast_pkts_low[0x20];
8099
8100         u8         if_out_multicast_pkts_high[0x20];
8101
8102         u8         if_out_multicast_pkts_low[0x20];
8103
8104         u8         if_out_broadcast_pkts_high[0x20];
8105
8106         u8         if_out_broadcast_pkts_low[0x20];
8107
8108         u8         reserved_0[0x480];
8109 };
8110
8111 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8112         u8         ether_stats_drop_events_high[0x20];
8113
8114         u8         ether_stats_drop_events_low[0x20];
8115
8116         u8         ether_stats_octets_high[0x20];
8117
8118         u8         ether_stats_octets_low[0x20];
8119
8120         u8         ether_stats_pkts_high[0x20];
8121
8122         u8         ether_stats_pkts_low[0x20];
8123
8124         u8         ether_stats_broadcast_pkts_high[0x20];
8125
8126         u8         ether_stats_broadcast_pkts_low[0x20];
8127
8128         u8         ether_stats_multicast_pkts_high[0x20];
8129
8130         u8         ether_stats_multicast_pkts_low[0x20];
8131
8132         u8         ether_stats_crc_align_errors_high[0x20];
8133
8134         u8         ether_stats_crc_align_errors_low[0x20];
8135
8136         u8         ether_stats_undersize_pkts_high[0x20];
8137
8138         u8         ether_stats_undersize_pkts_low[0x20];
8139
8140         u8         ether_stats_oversize_pkts_high[0x20];
8141
8142         u8         ether_stats_oversize_pkts_low[0x20];
8143
8144         u8         ether_stats_fragments_high[0x20];
8145
8146         u8         ether_stats_fragments_low[0x20];
8147
8148         u8         ether_stats_jabbers_high[0x20];
8149
8150         u8         ether_stats_jabbers_low[0x20];
8151
8152         u8         ether_stats_collisions_high[0x20];
8153
8154         u8         ether_stats_collisions_low[0x20];
8155
8156         u8         ether_stats_pkts64octets_high[0x20];
8157
8158         u8         ether_stats_pkts64octets_low[0x20];
8159
8160         u8         ether_stats_pkts65to127octets_high[0x20];
8161
8162         u8         ether_stats_pkts65to127octets_low[0x20];
8163
8164         u8         ether_stats_pkts128to255octets_high[0x20];
8165
8166         u8         ether_stats_pkts128to255octets_low[0x20];
8167
8168         u8         ether_stats_pkts256to511octets_high[0x20];
8169
8170         u8         ether_stats_pkts256to511octets_low[0x20];
8171
8172         u8         ether_stats_pkts512to1023octets_high[0x20];
8173
8174         u8         ether_stats_pkts512to1023octets_low[0x20];
8175
8176         u8         ether_stats_pkts1024to1518octets_high[0x20];
8177
8178         u8         ether_stats_pkts1024to1518octets_low[0x20];
8179
8180         u8         ether_stats_pkts1519to2047octets_high[0x20];
8181
8182         u8         ether_stats_pkts1519to2047octets_low[0x20];
8183
8184         u8         ether_stats_pkts2048to4095octets_high[0x20];
8185
8186         u8         ether_stats_pkts2048to4095octets_low[0x20];
8187
8188         u8         ether_stats_pkts4096to8191octets_high[0x20];
8189
8190         u8         ether_stats_pkts4096to8191octets_low[0x20];
8191
8192         u8         ether_stats_pkts8192to10239octets_high[0x20];
8193
8194         u8         ether_stats_pkts8192to10239octets_low[0x20];
8195
8196         u8         reserved_0[0x280];
8197 };
8198
8199 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8200         u8         symbol_error_counter[0x10];
8201         u8         link_error_recovery_counter[0x8];
8202         u8         link_downed_counter[0x8];
8203
8204         u8         port_rcv_errors[0x10];
8205         u8         port_rcv_remote_physical_errors[0x10];
8206
8207         u8         port_rcv_switch_relay_errors[0x10];
8208         u8         port_xmit_discards[0x10];
8209
8210         u8         port_xmit_constraint_errors[0x8];
8211         u8         port_rcv_constraint_errors[0x8];
8212         u8         reserved_0[0x8];
8213         u8         local_link_integrity_errors[0x4];
8214         u8         excessive_buffer_overrun_errors[0x4];
8215
8216         u8         reserved_1[0x10];
8217         u8         vl_15_dropped[0x10];
8218
8219         u8         port_xmit_data[0x20];
8220
8221         u8         port_rcv_data[0x20];
8222
8223         u8         port_xmit_pkts[0x20];
8224
8225         u8         port_rcv_pkts[0x20];
8226
8227         u8         port_xmit_wait[0x20];
8228
8229         u8         reserved_2[0x680];
8230 };
8231
8232 struct mlx5_ifc_trc_tlb_reg_bits {
8233         u8         reserved_0[0x80];
8234
8235         u8         tlb_addr[0][0x40];
8236 };
8237
8238 struct mlx5_ifc_trc_read_fifo_reg_bits {
8239         u8         reserved_0[0x10];
8240         u8         requested_event_num[0x10];
8241
8242         u8         reserved_1[0x20];
8243
8244         u8         reserved_2[0x10];
8245         u8         acual_event_num[0x10];
8246
8247         u8         reserved_3[0x20];
8248
8249         u8         event[0][0x40];
8250 };
8251
8252 struct mlx5_ifc_trc_lock_reg_bits {
8253         u8         reserved_0[0x1f];
8254         u8         lock[0x1];
8255
8256         u8         reserved_1[0x60];
8257 };
8258
8259 struct mlx5_ifc_trc_filter_reg_bits {
8260         u8         status[0x1];
8261         u8         reserved_0[0xf];
8262         u8         filter_index[0x10];
8263
8264         u8         reserved_1[0x20];
8265
8266         u8         filter_val[0x20];
8267
8268         u8         reserved_2[0x1a0];
8269 };
8270
8271 struct mlx5_ifc_trc_event_reg_bits {
8272         u8         status[0x1];
8273         u8         reserved_0[0xf];
8274         u8         event_index[0x10];
8275
8276         u8         reserved_1[0x20];
8277
8278         u8         event_id[0x20];
8279
8280         u8         event_selector_val[0x10];
8281         u8         event_selector_size[0x10];
8282
8283         u8         reserved_2[0x180];
8284 };
8285
8286 struct mlx5_ifc_trc_conf_reg_bits {
8287         u8         limit_en[0x1];
8288         u8         reserved_0[0x3];
8289         u8         dump_mode[0x4];
8290         u8         reserved_1[0x15];
8291         u8         state[0x3];
8292
8293         u8         reserved_2[0x20];
8294
8295         u8         limit_event_index[0x20];
8296
8297         u8         mkey[0x20];
8298
8299         u8         fifo_ready_ev_num[0x20];
8300
8301         u8         reserved_3[0x160];
8302 };
8303
8304 struct mlx5_ifc_trc_cap_reg_bits {
8305         u8         reserved_0[0x18];
8306         u8         dump_mode[0x8];
8307
8308         u8         reserved_1[0x20];
8309
8310         u8         num_of_events[0x10];
8311         u8         num_of_filters[0x10];
8312
8313         u8         fifo_size[0x20];
8314
8315         u8         tlb_size[0x10];
8316         u8         event_size[0x10];
8317
8318         u8         reserved_2[0x160];
8319 };
8320
8321 struct mlx5_ifc_set_node_in_bits {
8322         u8         node_description[64][0x8];
8323 };
8324
8325 struct mlx5_ifc_register_power_settings_bits {
8326         u8         reserved_0[0x18];
8327         u8         power_settings_level[0x8];
8328
8329         u8         reserved_1[0x60];
8330 };
8331
8332 struct mlx5_ifc_register_host_endianess_bits {
8333         u8         he[0x1];
8334         u8         reserved_0[0x1f];
8335
8336         u8         reserved_1[0x60];
8337 };
8338
8339 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
8340         u8         physical_address[0x40];
8341 };
8342
8343 struct mlx5_ifc_qtct_reg_bits {
8344         u8         operation_type[0x2];
8345         u8         cap_local_admin[0x1];
8346         u8         cap_remote_admin[0x1];
8347         u8         reserved_0[0x4];
8348         u8         port_number[0x8];
8349         u8         reserved_1[0xd];
8350         u8         prio[0x3];
8351
8352         u8         reserved_2[0x1d];
8353         u8         tclass[0x3];
8354 };
8355
8356 struct mlx5_ifc_qpdp_reg_bits {
8357         u8         reserved_0[0x8];
8358         u8         port_number[0x8];
8359         u8         reserved_1[0x10];
8360
8361         u8         reserved_2[0x1d];
8362         u8         pprio[0x3];
8363 };
8364
8365 struct mlx5_ifc_port_info_ro_fields_param_bits {
8366         u8         reserved_0[0x8];
8367         u8         port[0x8];
8368         u8         max_gid[0x10];
8369
8370         u8         reserved_1[0x20];
8371
8372         u8         port_guid[0x40];
8373 };
8374
8375 struct mlx5_ifc_nvqc_reg_bits {
8376         u8         type[0x20];
8377
8378         u8         reserved_0[0x18];
8379         u8         version[0x4];
8380         u8         reserved_1[0x2];
8381         u8         support_wr[0x1];
8382         u8         support_rd[0x1];
8383 };
8384
8385 struct mlx5_ifc_nvia_reg_bits {
8386         u8         reserved_0[0x1d];
8387         u8         target[0x3];
8388
8389         u8         reserved_1[0x20];
8390 };
8391
8392 struct mlx5_ifc_nvdi_reg_bits {
8393         struct mlx5_ifc_config_item_bits configuration_item_header;
8394 };
8395
8396 struct mlx5_ifc_nvda_reg_bits {
8397         struct mlx5_ifc_config_item_bits configuration_item_header;
8398
8399         u8         configuration_item_data[0x20];
8400 };
8401
8402 struct mlx5_ifc_node_info_ro_fields_param_bits {
8403         u8         system_image_guid[0x40];
8404
8405         u8         reserved_0[0x40];
8406
8407         u8         node_guid[0x40];
8408
8409         u8         reserved_1[0x10];
8410         u8         max_pkey[0x10];
8411
8412         u8         reserved_2[0x20];
8413 };
8414
8415 struct mlx5_ifc_ets_tcn_config_reg_bits {
8416         u8         g[0x1];
8417         u8         b[0x1];
8418         u8         r[0x1];
8419         u8         reserved_0[0x9];
8420         u8         group[0x4];
8421         u8         reserved_1[0x9];
8422         u8         bw_allocation[0x7];
8423
8424         u8         reserved_2[0xc];
8425         u8         max_bw_units[0x4];
8426         u8         reserved_3[0x8];
8427         u8         max_bw_value[0x8];
8428 };
8429
8430 struct mlx5_ifc_ets_global_config_reg_bits {
8431         u8         reserved_0[0x2];
8432         u8         r[0x1];
8433         u8         reserved_1[0x1d];
8434
8435         u8         reserved_2[0xc];
8436         u8         max_bw_units[0x4];
8437         u8         reserved_3[0x8];
8438         u8         max_bw_value[0x8];
8439 };
8440
8441 struct mlx5_ifc_nodnic_mac_filters_bits {
8442         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
8443
8444         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
8445
8446         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
8447
8448         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
8449
8450         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
8451
8452         u8         reserved_0[0xc0];
8453 };
8454
8455 struct mlx5_ifc_nodnic_gid_filters_bits {
8456         u8         mgid_filter0[16][0x8];
8457
8458         u8         mgid_filter1[16][0x8];
8459
8460         u8         mgid_filter2[16][0x8];
8461
8462         u8         mgid_filter3[16][0x8];
8463 };
8464
8465 enum {
8466         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
8467         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
8468 };
8469
8470 enum {
8471         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
8472         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
8473 };
8474
8475 struct mlx5_ifc_nodnic_config_reg_bits {
8476         u8         no_dram_nic_revision[0x8];
8477         u8         hardware_format[0x8];
8478         u8         support_receive_filter[0x1];
8479         u8         support_promisc_filter[0x1];
8480         u8         support_promisc_multicast_filter[0x1];
8481         u8         reserved_0[0x2];
8482         u8         log_working_buffer_size[0x3];
8483         u8         log_pkey_table_size[0x4];
8484         u8         reserved_1[0x3];
8485         u8         num_ports[0x1];
8486
8487         u8         reserved_2[0x2];
8488         u8         log_max_ring_size[0x6];
8489         u8         reserved_3[0x18];
8490
8491         u8         lkey[0x20];
8492
8493         u8         cqe_format[0x4];
8494         u8         reserved_4[0x1c];
8495
8496         u8         node_guid[0x40];
8497
8498         u8         reserved_5[0x740];
8499
8500         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
8501
8502         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
8503 };
8504
8505 struct mlx5_ifc_vlan_layout_bits {
8506         u8         reserved_0[0x14];
8507         u8         vlan[0xc];
8508
8509         u8         reserved_1[0x20];
8510 };
8511
8512 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8513         u8         reserved_0[0x20];
8514
8515         u8         mkey[0x20];
8516
8517         u8         addressh_63_32[0x20];
8518
8519         u8         addressl_31_0[0x20];
8520 };
8521
8522 struct mlx5_ifc_ud_adrs_vector_bits {
8523         u8         dc_key[0x40];
8524
8525         u8         ext[0x1];
8526         u8         reserved_0[0x7];
8527         u8         destination_qp_dct[0x18];
8528
8529         u8         static_rate[0x4];
8530         u8         sl_eth_prio[0x4];
8531         u8         fl[0x1];
8532         u8         mlid[0x7];
8533         u8         rlid_udp_sport[0x10];
8534
8535         u8         reserved_1[0x20];
8536
8537         u8         rmac_47_16[0x20];
8538
8539         u8         rmac_15_0[0x10];
8540         u8         tclass[0x8];
8541         u8         hop_limit[0x8];
8542
8543         u8         reserved_2[0x1];
8544         u8         grh[0x1];
8545         u8         reserved_3[0x2];
8546         u8         src_addr_index[0x8];
8547         u8         flow_label[0x14];
8548
8549         u8         rgid_rip[16][0x8];
8550 };
8551
8552 struct mlx5_ifc_port_module_event_bits {
8553         u8         reserved_0[0x8];
8554         u8         module[0x8];
8555         u8         reserved_1[0xc];
8556         u8         module_status[0x4];
8557
8558         u8         reserved_2[0x14];
8559         u8         error_type[0x4];
8560         u8         reserved_3[0x8];
8561
8562         u8         reserved_4[0xa0];
8563 };
8564
8565 struct mlx5_ifc_icmd_control_bits {
8566         u8         opcode[0x10];
8567         u8         status[0x8];
8568         u8         reserved_0[0x7];
8569         u8         busy[0x1];
8570 };
8571
8572 struct mlx5_ifc_eqe_bits {
8573         u8         reserved_0[0x8];
8574         u8         event_type[0x8];
8575         u8         reserved_1[0x8];
8576         u8         event_sub_type[0x8];
8577
8578         u8         reserved_2[0xe0];
8579
8580         union mlx5_ifc_event_auto_bits event_data;
8581
8582         u8         reserved_3[0x10];
8583         u8         signature[0x8];
8584         u8         reserved_4[0x7];
8585         u8         owner[0x1];
8586 };
8587
8588 enum {
8589         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8590 };
8591
8592 struct mlx5_ifc_cmd_queue_entry_bits {
8593         u8         type[0x8];
8594         u8         reserved_0[0x18];
8595
8596         u8         input_length[0x20];
8597
8598         u8         input_mailbox_pointer_63_32[0x20];
8599
8600         u8         input_mailbox_pointer_31_9[0x17];
8601         u8         reserved_1[0x9];
8602
8603         u8         command_input_inline_data[16][0x8];
8604
8605         u8         command_output_inline_data[16][0x8];
8606
8607         u8         output_mailbox_pointer_63_32[0x20];
8608
8609         u8         output_mailbox_pointer_31_9[0x17];
8610         u8         reserved_2[0x9];
8611
8612         u8         output_length[0x20];
8613
8614         u8         token[0x8];
8615         u8         signature[0x8];
8616         u8         reserved_3[0x8];
8617         u8         status[0x7];
8618         u8         ownership[0x1];
8619 };
8620
8621 struct mlx5_ifc_cmd_out_bits {
8622         u8         status[0x8];
8623         u8         reserved_0[0x18];
8624
8625         u8         syndrome[0x20];
8626
8627         u8         command_output[0x20];
8628 };
8629
8630 struct mlx5_ifc_cmd_in_bits {
8631         u8         opcode[0x10];
8632         u8         reserved_0[0x10];
8633
8634         u8         reserved_1[0x10];
8635         u8         op_mod[0x10];
8636
8637         u8         command[0][0x20];
8638 };
8639
8640 struct mlx5_ifc_cmd_if_box_bits {
8641         u8         mailbox_data[512][0x8];
8642
8643         u8         reserved_0[0x180];
8644
8645         u8         next_pointer_63_32[0x20];
8646
8647         u8         next_pointer_31_10[0x16];
8648         u8         reserved_1[0xa];
8649
8650         u8         block_number[0x20];
8651
8652         u8         reserved_2[0x8];
8653         u8         token[0x8];
8654         u8         ctrl_signature[0x8];
8655         u8         signature[0x8];
8656 };
8657
8658 struct mlx5_ifc_mtt_bits {
8659         u8         ptag_63_32[0x20];
8660
8661         u8         ptag_31_8[0x18];
8662         u8         reserved_0[0x6];
8663         u8         wr_en[0x1];
8664         u8         rd_en[0x1];
8665 };
8666
8667 struct mlx5_ifc_vendor_specific_cap_bits {
8668         u8         type[0x8];
8669         u8         length[0x8];
8670         u8         next_pointer[0x8];
8671         u8         capability_id[0x8];
8672
8673         u8         status[0x3];
8674         u8         reserved_0[0xd];
8675         u8         space[0x10];
8676
8677         u8         counter[0x20];
8678
8679         u8         semaphore[0x20];
8680
8681         u8         flag[0x1];
8682         u8         reserved_1[0x1];
8683         u8         address[0x1e];
8684
8685         u8         data[0x20];
8686 };
8687
8688 enum {
8689         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8690         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8691         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8692 };
8693
8694 enum {
8695         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8696         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8697         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8698 };
8699
8700 enum {
8701         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
8702         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
8703         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
8704         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
8705         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
8706         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
8707         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
8708         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
8709         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
8710         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
8711         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
8712 };
8713
8714 struct mlx5_ifc_initial_seg_bits {
8715         u8         fw_rev_minor[0x10];
8716         u8         fw_rev_major[0x10];
8717
8718         u8         cmd_interface_rev[0x10];
8719         u8         fw_rev_subminor[0x10];
8720
8721         u8         reserved_0[0x40];
8722
8723         u8         cmdq_phy_addr_63_32[0x20];
8724
8725         u8         cmdq_phy_addr_31_12[0x14];
8726         u8         reserved_1[0x2];
8727         u8         nic_interface[0x2];
8728         u8         log_cmdq_size[0x4];
8729         u8         log_cmdq_stride[0x4];
8730
8731         u8         command_doorbell_vector[0x20];
8732
8733         u8         reserved_2[0xf00];
8734
8735         u8         initializing[0x1];
8736         u8         reserved_3[0x4];
8737         u8         nic_interface_supported[0x3];
8738         u8         reserved_4[0x18];
8739
8740         struct mlx5_ifc_health_buffer_bits health_buffer;
8741
8742         u8         no_dram_nic_offset[0x20];
8743
8744         u8         reserved_5[0x6de0];
8745
8746         u8         internal_timer_h[0x20];
8747
8748         u8         internal_timer_l[0x20];
8749
8750         u8         reserved_6[0x20];
8751
8752         u8         reserved_7[0x1f];
8753         u8         clear_int[0x1];
8754
8755         u8         health_syndrome[0x8];
8756         u8         health_counter[0x18];
8757
8758         u8         reserved_8[0x17fc0];
8759 };
8760
8761 union mlx5_ifc_icmd_interface_document_bits {
8762         struct mlx5_ifc_fw_version_bits fw_version;
8763         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
8764         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
8765         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
8766         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
8767         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
8768         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
8769         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
8770         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
8771         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
8772         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
8773         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
8774         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
8775         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
8776         u8         reserved_0[0x42c0];
8777 };
8778
8779 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
8780         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8781         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8782         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8783         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8784         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8785         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8786         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8787         u8         reserved_0[0x7c0];
8788 };
8789
8790 struct mlx5_ifc_ppcnt_reg_bits {
8791         u8         swid[0x8];
8792         u8         local_port[0x8];
8793         u8         pnat[0x2];
8794         u8         reserved_0[0x8];
8795         u8         grp[0x6];
8796
8797         u8         clr[0x1];
8798         u8         reserved_1[0x1c];
8799         u8         prio_tc[0x3];
8800
8801         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8802 };
8803
8804 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
8805         u8         life_time_counter_high[0x20];
8806
8807         u8         life_time_counter_low[0x20];
8808
8809         u8         rx_errors[0x20];
8810
8811         u8         tx_errors[0x20];
8812
8813         u8         l0_to_recovery_eieos[0x20];
8814
8815         u8         l0_to_recovery_ts[0x20];
8816
8817         u8         l0_to_recovery_framing[0x20];
8818
8819         u8         l0_to_recovery_retrain[0x20];
8820
8821         u8         crc_error_dllp[0x20];
8822
8823         u8         crc_error_tlp[0x20];
8824
8825         u8         reserved_0[0x680];
8826 };
8827
8828 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
8829         u8         life_time_counter_high[0x20];
8830
8831         u8         life_time_counter_low[0x20];
8832
8833         u8         time_to_boot_image_start[0x20];
8834
8835         u8         time_to_link_image[0x20];
8836
8837         u8         calibration_time[0x20];
8838
8839         u8         time_to_first_perst[0x20];
8840
8841         u8         time_to_detect_state[0x20];
8842
8843         u8         time_to_l0[0x20];
8844
8845         u8         time_to_crs_en[0x20];
8846
8847         u8         time_to_plastic_image_start[0x20];
8848
8849         u8         time_to_iron_image_start[0x20];
8850
8851         u8         perst_handler[0x20];
8852
8853         u8         times_in_l1[0x20];
8854
8855         u8         times_in_l23[0x20];
8856
8857         u8         dl_down[0x20];
8858
8859         u8         config_cycle1usec[0x20];
8860
8861         u8         config_cycle2to7usec[0x20];
8862
8863         u8         config_cycle8to15usec[0x20];
8864
8865         u8         config_cycle16to63usec[0x20];
8866
8867         u8         config_cycle64usec[0x20];
8868
8869         u8         correctable_err_msg_sent[0x20];
8870
8871         u8         non_fatal_err_msg_sent[0x20];
8872
8873         u8         fatal_err_msg_sent[0x20];
8874
8875         u8         reserved_0[0x4e0];
8876 };
8877
8878 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
8879         u8         life_time_counter_high[0x20];
8880
8881         u8         life_time_counter_low[0x20];
8882
8883         u8         error_counter_lane0[0x20];
8884
8885         u8         error_counter_lane1[0x20];
8886
8887         u8         error_counter_lane2[0x20];
8888
8889         u8         error_counter_lane3[0x20];
8890
8891         u8         error_counter_lane4[0x20];
8892
8893         u8         error_counter_lane5[0x20];
8894
8895         u8         error_counter_lane6[0x20];
8896
8897         u8         error_counter_lane7[0x20];
8898
8899         u8         error_counter_lane8[0x20];
8900
8901         u8         error_counter_lane9[0x20];
8902
8903         u8         error_counter_lane10[0x20];
8904
8905         u8         error_counter_lane11[0x20];
8906
8907         u8         error_counter_lane12[0x20];
8908
8909         u8         error_counter_lane13[0x20];
8910
8911         u8         error_counter_lane14[0x20];
8912
8913         u8         error_counter_lane15[0x20];
8914
8915         u8         reserved_0[0x580];
8916 };
8917
8918 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
8919         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
8920         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
8921         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
8922         u8         reserved_0[0xf8];
8923 };
8924
8925 struct mlx5_ifc_mpcnt_reg_bits {
8926         u8         reserved_0[0x8];
8927         u8         pcie_index[0x8];
8928         u8         reserved_1[0xa];
8929         u8         grp[0x6];
8930
8931         u8         clr[0x1];
8932         u8         reserved_2[0x1f];
8933
8934         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
8935 };
8936
8937 union mlx5_ifc_ports_control_registers_document_bits {
8938         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
8939         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8940         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8941         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8942         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8943         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8944         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8945         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8946         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
8947         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
8948         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8949         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
8950         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8951         struct mlx5_ifc_paos_reg_bits paos_reg;
8952         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
8953         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8954         struct mlx5_ifc_peir_reg_bits peir_reg;
8955         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8956         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8957         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
8958         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
8959         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
8960         struct mlx5_ifc_phrr_reg_bits phrr_reg;
8961         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8962         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8963         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8964         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8965         struct mlx5_ifc_plib_reg_bits plib_reg;
8966         struct mlx5_ifc_pll_status_data_bits pll_status_data;
8967         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8968         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8969         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8970         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8971         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8972         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8973         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8974         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8975         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8976         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8977         struct mlx5_ifc_ppll_reg_bits ppll_reg;
8978         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8979         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8980         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8981         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8982         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8983         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8984         struct mlx5_ifc_pude_reg_bits pude_reg;
8985         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8986         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8987         struct mlx5_ifc_slrp_reg_bits slrp_reg;
8988         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8989         u8         reserved_0[0x7880];
8990 };
8991
8992 union mlx5_ifc_debug_enhancements_document_bits {
8993         struct mlx5_ifc_health_buffer_bits health_buffer;
8994         u8         reserved_0[0x200];
8995 };
8996
8997 union mlx5_ifc_no_dram_nic_document_bits {
8998         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
8999         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9000         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9001         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9002         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9003         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9004         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9005         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9006         u8         reserved_0[0x3160];
9007 };
9008
9009 union mlx5_ifc_uplink_pci_interface_document_bits {
9010         struct mlx5_ifc_initial_seg_bits initial_seg;
9011         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9012         u8         reserved_0[0x20120];
9013 };
9014
9015
9016 #endif /* MLX5_IFC_H */