sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
  32
  33 enum {
  34         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  35         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  36         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  37         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  38         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  39         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  40         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  41         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  42         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  43         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  44         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  45         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  46         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  47         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  48         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  49         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  50         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  51         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  52         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  53         MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
  54         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  56         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  57         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  58         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  59         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  60         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  61         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  62         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  63         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
  64         MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
  65         MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
  66 };
  67
  68 enum {
  69         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  70         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  71         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  72         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  73         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  74 };
  75
  76 enum {
  77         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  78 };
  79
  80 enum {
  81         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  82         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  83 };
  84
  85 enum {
  86         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  87         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  88         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  89         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  90         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  91         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  92         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  93         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  94         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  95         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  96         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  97         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  98         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
  99         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 100         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 101         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 102         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 103         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 104         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 105         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 106         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 107         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 108         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 109         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 110         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 111         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 112         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 113         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 114         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 115         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 116         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 117         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 118         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 119         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 120         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 121         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 122         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 123         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 124         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 125         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 126         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 127         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 128         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 129         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 130         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 131         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 132         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 133         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 134         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 135         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 136         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 137         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 138         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 139         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 140         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 141         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 142         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 143         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 144         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 145         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 146         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 147         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 148         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 149         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 150         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 151         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 152         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 153         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 154         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 155         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 156         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 157         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 158         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 159         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 160         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 161         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 162         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 163         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 164         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 165         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 166         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 167         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 168         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 169         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 170         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 171         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 172         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 173         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 174         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 175         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 176         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 177         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 178         MLX5_CMD_OP_NOP                           = 0x80d,
 179         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 180         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 181         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 182         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 183         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 184         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 185         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 186         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 187         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 188         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 218         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 219         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 220         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 221         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 222         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 223         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 224         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 225         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 226         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 227         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 228         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 229         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 230         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 231         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 232         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 233         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 234         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 235         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 236         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 237         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 238         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 239         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 240         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 241         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 242         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 243         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 244         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 245         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 246         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 247         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 248         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 249         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 250         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 251         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 252         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 253         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 254 };
 255
 256 enum {
 257         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 258         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 259         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 260         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 261         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 262         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 263         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 264         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 265         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 266         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 267         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 268         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 269 };
 270
 271 struct mlx5_ifc_flow_table_fields_supported_bits {
 272         u8         outer_dmac[0x1];
 273         u8         outer_smac[0x1];
 274         u8         outer_ether_type[0x1];
 275         u8         reserved_0[0x1];
 276         u8         outer_first_prio[0x1];
 277         u8         outer_first_cfi[0x1];
 278         u8         outer_first_vid[0x1];
 279         u8         reserved_1[0x1];
 280         u8         outer_second_prio[0x1];
 281         u8         outer_second_cfi[0x1];
 282         u8         outer_second_vid[0x1];
 283         u8         outer_ipv6_flow_label[0x1];
 284         u8         outer_sip[0x1];
 285         u8         outer_dip[0x1];
 286         u8         outer_frag[0x1];
 287         u8         outer_ip_protocol[0x1];
 288         u8         outer_ip_ecn[0x1];
 289         u8         outer_ip_dscp[0x1];
 290         u8         outer_udp_sport[0x1];
 291         u8         outer_udp_dport[0x1];
 292         u8         outer_tcp_sport[0x1];
 293         u8         outer_tcp_dport[0x1];
 294         u8         outer_tcp_flags[0x1];
 295         u8         outer_gre_protocol[0x1];
 296         u8         outer_gre_key[0x1];
 297         u8         outer_vxlan_vni[0x1];
 298         u8         outer_geneve_vni[0x1];
 299         u8         outer_geneve_oam[0x1];
 300         u8         outer_geneve_protocol_type[0x1];
 301         u8         outer_geneve_opt_len[0x1];
 302         u8         reserved_2[0x1];
 303         u8         source_eswitch_port[0x1];
 304
 305         u8         inner_dmac[0x1];
 306         u8         inner_smac[0x1];
 307         u8         inner_ether_type[0x1];
 308         u8         reserved_3[0x1];
 309         u8         inner_first_prio[0x1];
 310         u8         inner_first_cfi[0x1];
 311         u8         inner_first_vid[0x1];
 312         u8         reserved_4[0x1];
 313         u8         inner_second_prio[0x1];
 314         u8         inner_second_cfi[0x1];
 315         u8         inner_second_vid[0x1];
 316         u8         inner_ipv6_flow_label[0x1];
 317         u8         inner_sip[0x1];
 318         u8         inner_dip[0x1];
 319         u8         inner_frag[0x1];
 320         u8         inner_ip_protocol[0x1];
 321         u8         inner_ip_ecn[0x1];
 322         u8         inner_ip_dscp[0x1];
 323         u8         inner_udp_sport[0x1];
 324         u8         inner_udp_dport[0x1];
 325         u8         inner_tcp_sport[0x1];
 326         u8         inner_tcp_dport[0x1];
 327         u8         inner_tcp_flags[0x1];
 328         u8         reserved_5[0x9];
 329
 330         u8         reserved_6[0x1a];
 331         u8         bth_dst_qp[0x1];
 332         u8         reserved_7[0x4];
 333         u8         source_sqn[0x1];
 334
 335         u8         reserved_8[0x20];
 336 };
 337
 338 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 339         u8         ingress_general_high[0x20];
 340
 341         u8         ingress_general_low[0x20];
 342
 343         u8         ingress_policy_engine_high[0x20];
 344
 345         u8         ingress_policy_engine_low[0x20];
 346
 347         u8         ingress_vlan_membership_high[0x20];
 348
 349         u8         ingress_vlan_membership_low[0x20];
 350
 351         u8         ingress_tag_frame_type_high[0x20];
 352
 353         u8         ingress_tag_frame_type_low[0x20];
 354
 355         u8         egress_vlan_membership_high[0x20];
 356
 357         u8         egress_vlan_membership_low[0x20];
 358
 359         u8         loopback_filter_high[0x20];
 360
 361         u8         loopback_filter_low[0x20];
 362
 363         u8         egress_general_high[0x20];
 364
 365         u8         egress_general_low[0x20];
 366
 367         u8         reserved_at_1c0[0x40];
 368
 369         u8         egress_hoq_high[0x20];
 370
 371         u8         egress_hoq_low[0x20];
 372
 373         u8         port_isolation_high[0x20];
 374
 375         u8         port_isolation_low[0x20];
 376
 377         u8         egress_policy_engine_high[0x20];
 378
 379         u8         egress_policy_engine_low[0x20];
 380
 381         u8         ingress_tx_link_down_high[0x20];
 382
 383         u8         ingress_tx_link_down_low[0x20];
 384
 385         u8         egress_stp_filter_high[0x20];
 386
 387         u8         egress_stp_filter_low[0x20];
 388
 389         u8         egress_hoq_stall_high[0x20];
 390
 391         u8         egress_hoq_stall_low[0x20];
 392
 393         u8         reserved_at_340[0x440];
 394 };
 395 struct mlx5_ifc_flow_table_prop_layout_bits {
 396         u8         ft_support[0x1];
 397         u8         flow_tag[0x1];
 398         u8         flow_counter[0x1];
 399         u8         flow_modify_en[0x1];
 400         u8         modify_root[0x1];
 401         u8         identified_miss_table[0x1];
 402         u8         flow_table_modify[0x1];
 403         u8         encap[0x1];
 404         u8         decap[0x1];
 405         u8         reset_root_to_default[0x1];
 406         u8         reserved_at_a[0x16];
 407
 408         u8         reserved_at_20[0x2];
 409         u8         log_max_ft_size[0x6];
 410         u8         reserved_at_28[0x10];
 411         u8         max_ft_level[0x8];
 412
 413         u8         reserved_at_40[0x20];
 414
 415         u8         reserved_at_60[0x18];
 416         u8         log_max_ft_num[0x8];
 417
 418         u8         reserved_at_80[0x10];
 419         u8         log_max_flow_counter[0x8];
 420         u8         log_max_destination[0x8];
 421
 422         u8         reserved_at_a0[0x18];
 423         u8         log_max_flow[0x8];
 424
 425         u8         reserved_at_c0[0x40];
 426
 427         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 428
 429         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 430 };
 431
 432 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 433         u8         send[0x1];
 434         u8         receive[0x1];
 435         u8         write[0x1];
 436         u8         read[0x1];
 437         u8         atomic[0x1];
 438         u8         srq_receive[0x1];
 439         u8         reserved_0[0x1a];
 440 };
 441
 442 struct mlx5_ifc_flow_counter_list_bits {
 443         u8         reserved_0[0x10];
 444         u8         flow_counter_id[0x10];
 445
 446         u8         reserved_1[0x20];
 447 };
 448
 449 enum {
 450         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 451         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 452         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 453         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 454 };
 455
 456 struct mlx5_ifc_dest_format_struct_bits {
 457         u8         destination_type[0x8];
 458         u8         destination_id[0x18];
 459
 460         u8         reserved_0[0x20];
 461 };
 462
 463 struct mlx5_ifc_ipv4_layout_bits {
 464         u8         reserved_at_0[0x60];
 465
 466         u8         ipv4[0x20];
 467 };
 468
 469 struct mlx5_ifc_ipv6_layout_bits {
 470         u8         ipv6[16][0x8];
 471 };
 472
 473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 474         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 475         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 476         u8         reserved_at_0[0x80];
 477 };
 478
 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 480         u8         smac_47_16[0x20];
 481
 482         u8         smac_15_0[0x10];
 483         u8         ethertype[0x10];
 484
 485         u8         dmac_47_16[0x20];
 486
 487         u8         dmac_15_0[0x10];
 488         u8         first_prio[0x3];
 489         u8         first_cfi[0x1];
 490         u8         first_vid[0xc];
 491
 492         u8         ip_protocol[0x8];
 493         u8         ip_dscp[0x6];
 494         u8         ip_ecn[0x2];
 495         u8         cvlan_tag[0x1];
 496         u8         svlan_tag[0x1];
 497         u8         frag[0x1];
 498         u8         reserved_1[0x4];
 499         u8         tcp_flags[0x9];
 500
 501         u8         tcp_sport[0x10];
 502         u8         tcp_dport[0x10];
 503
 504         u8         reserved_2[0x20];
 505
 506         u8         udp_sport[0x10];
 507         u8         udp_dport[0x10];
 508
 509         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 510
 511         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 512 };
 513
 514 struct mlx5_ifc_fte_match_set_misc_bits {
 515         u8         reserved_0[0x8];
 516         u8         source_sqn[0x18];
 517
 518         u8         reserved_1[0x10];
 519         u8         source_port[0x10];
 520
 521         u8         outer_second_prio[0x3];
 522         u8         outer_second_cfi[0x1];
 523         u8         outer_second_vid[0xc];
 524         u8         inner_second_prio[0x3];
 525         u8         inner_second_cfi[0x1];
 526         u8         inner_second_vid[0xc];
 527
 528         u8         outer_second_vlan_tag[0x1];
 529         u8         inner_second_vlan_tag[0x1];
 530         u8         reserved_2[0xe];
 531         u8         gre_protocol[0x10];
 532
 533         u8         gre_key_h[0x18];
 534         u8         gre_key_l[0x8];
 535
 536         u8         vxlan_vni[0x18];
 537         u8         reserved_3[0x8];
 538
 539         u8         geneve_vni[0x18];
 540         u8         reserved4[0x7];
 541         u8         geneve_oam[0x1];
 542
 543         u8         reserved_5[0xc];
 544         u8         outer_ipv6_flow_label[0x14];
 545
 546         u8         reserved_6[0xc];
 547         u8         inner_ipv6_flow_label[0x14];
 548
 549         u8         reserved_7[0xa];
 550         u8         geneve_opt_len[0x6];
 551         u8         geneve_protocol_type[0x10];
 552
 553         u8         reserved_8[0x8];
 554         u8         bth_dst_qp[0x18];
 555
 556         u8         reserved_9[0xa0];
 557 };
 558
 559 struct mlx5_ifc_cmd_pas_bits {
 560         u8         pa_h[0x20];
 561
 562         u8         pa_l[0x14];
 563         u8         reserved_0[0xc];
 564 };
 565
 566 struct mlx5_ifc_uint64_bits {
 567         u8         hi[0x20];
 568
 569         u8         lo[0x20];
 570 };
 571
 572 struct mlx5_ifc_application_prio_entry_bits {
 573         u8         reserved_0[0x8];
 574         u8         priority[0x3];
 575         u8         reserved_1[0x2];
 576         u8         sel[0x3];
 577         u8         protocol_id[0x10];
 578 };
 579
 580 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 581         u8         reserved_0[0x8];
 582         u8         ring_pi[0x10];
 583         u8         reserved_1[0x8];
 584 };
 585
 586 enum {
 587         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 588         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 589         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 590         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 591         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 592         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 593         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 594         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 595         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 596         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 597 };
 598
 599 struct mlx5_ifc_ads_bits {
 600         u8         fl[0x1];
 601         u8         free_ar[0x1];
 602         u8         reserved_0[0xe];
 603         u8         pkey_index[0x10];
 604
 605         u8         reserved_1[0x8];
 606         u8         grh[0x1];
 607         u8         mlid[0x7];
 608         u8         rlid[0x10];
 609
 610         u8         ack_timeout[0x5];
 611         u8         reserved_2[0x3];
 612         u8         src_addr_index[0x8];
 613         u8         log_rtm[0x4];
 614         u8         stat_rate[0x4];
 615         u8         hop_limit[0x8];
 616
 617         u8         reserved_3[0x4];
 618         u8         tclass[0x8];
 619         u8         flow_label[0x14];
 620
 621         u8         rgid_rip[16][0x8];
 622
 623         u8         reserved_4[0x4];
 624         u8         f_dscp[0x1];
 625         u8         f_ecn[0x1];
 626         u8         reserved_5[0x1];
 627         u8         f_eth_prio[0x1];
 628         u8         ecn[0x2];
 629         u8         dscp[0x6];
 630         u8         udp_sport[0x10];
 631
 632         u8         dei_cfi[0x1];
 633         u8         eth_prio[0x3];
 634         u8         sl[0x4];
 635         u8         port[0x8];
 636         u8         rmac_47_32[0x10];
 637
 638         u8         rmac_31_0[0x20];
 639 };
 640
 641 struct mlx5_ifc_diagnostic_counter_cap_bits {
 642         u8         sync[0x1];
 643         u8         reserved_0[0xf];
 644         u8         counter_id[0x10];
 645 };
 646
 647 struct mlx5_ifc_debug_cap_bits {
 648         u8         reserved_0[0x18];
 649         u8         log_max_samples[0x8];
 650
 651         u8         single[0x1];
 652         u8         repetitive[0x1];
 653         u8         health_mon_rx_activity[0x1];
 654         u8         reserved_1[0x15];
 655         u8         log_min_sample_period[0x8];
 656
 657         u8         reserved_2[0x1c0];
 658
 659         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 660 };
 661
 662 struct mlx5_ifc_qos_cap_bits {
 663         u8         packet_pacing[0x1];
 664         u8         esw_scheduling[0x1];
 665         u8         esw_bw_share[0x1];
 666         u8         esw_rate_limit[0x1];
 667         u8         hll[0x1];
 668         u8         packet_pacing_burst_bound[0x1];
 669         u8         reserved_at_6[0x1a];
 670
 671         u8         reserved_at_20[0x20];
 672
 673         u8         packet_pacing_max_rate[0x20];
 674
 675         u8         packet_pacing_min_rate[0x20];
 676
 677         u8         reserved_at_80[0x10];
 678         u8         packet_pacing_rate_table_size[0x10];
 679
 680         u8         esw_element_type[0x10];
 681         u8         esw_tsar_type[0x10];
 682
 683         u8         reserved_at_c0[0x10];
 684         u8         max_qos_para_vport[0x10];
 685
 686         u8         max_tsar_bw_share[0x20];
 687
 688         u8         reserved_at_100[0x700];
 689 };
 690
 691 struct mlx5_ifc_snapshot_cap_bits {
 692         u8         reserved_0[0x1d];
 693         u8         suspend_qp_uc[0x1];
 694         u8         suspend_qp_ud[0x1];
 695         u8         suspend_qp_rc[0x1];
 696
 697         u8         reserved_1[0x1c];
 698         u8         restore_pd[0x1];
 699         u8         restore_uar[0x1];
 700         u8         restore_mkey[0x1];
 701         u8         restore_qp[0x1];
 702
 703         u8         reserved_2[0x1e];
 704         u8         named_mkey[0x1];
 705         u8         named_qp[0x1];
 706
 707         u8         reserved_3[0x7a0];
 708 };
 709
 710 struct mlx5_ifc_e_switch_cap_bits {
 711         u8         vport_svlan_strip[0x1];
 712         u8         vport_cvlan_strip[0x1];
 713         u8         vport_svlan_insert[0x1];
 714         u8         vport_cvlan_insert_if_not_exist[0x1];
 715         u8         vport_cvlan_insert_overwrite[0x1];
 716
 717         u8         reserved_0[0x19];
 718
 719         u8         nic_vport_node_guid_modify[0x1];
 720         u8         nic_vport_port_guid_modify[0x1];
 721
 722         u8         reserved_1[0x7e0];
 723 };
 724
 725 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 726         u8         reserved_0[0x200];
 727
 728         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 729
 730         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 731
 732         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 733
 734         u8         reserved_1[0x7800];
 735 };
 736
 737 struct mlx5_ifc_flow_table_nic_cap_bits {
 738         u8         nic_rx_multi_path_tirs[0x1];
 739         u8         nic_rx_multi_path_tirs_fts[0x1];
 740         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 741         u8         reserved_at_3[0x1fd];
 742
 743         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 744
 745         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 746
 747         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 748
 749         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 754
 755         u8         reserved_1[0x7200];
 756 };
 757
 758 enum {
 759         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR                   = 0x5031,
 760 };
 761
 762 struct mlx5_ifc_pddr_module_info_bits {
 763         u8         cable_technology[0x8];
 764         u8         cable_breakout[0x8];
 765         u8         ext_ethernet_compliance_code[0x8];
 766         u8         ethernet_compliance_code[0x8];
 767
 768         u8         cable_type[0x4];
 769         u8         cable_vendor[0x4];
 770         u8         cable_length[0x8];
 771         u8         cable_identifier[0x8];
 772         u8         cable_power_class[0x8];
 773
 774         u8         reserved_at_40[0x8];
 775         u8         cable_rx_amp[0x8];
 776         u8         cable_rx_emphasis[0x8];
 777         u8         cable_tx_equalization[0x8];
 778
 779         u8         reserved_at_60[0x8];
 780         u8         cable_attenuation_12g[0x8];
 781         u8         cable_attenuation_7g[0x8];
 782         u8         cable_attenuation_5g[0x8];
 783
 784         u8         reserved_at_80[0x8];
 785         u8         rx_cdr_cap[0x4];
 786         u8         tx_cdr_cap[0x4];
 787         u8         reserved_at_90[0x4];
 788         u8         rx_cdr_state[0x4];
 789         u8         reserved_at_98[0x4];
 790         u8         tx_cdr_state[0x4];
 791
 792         u8         vendor_name[16][0x8];
 793
 794         u8         vendor_pn[16][0x8];
 795
 796         u8         vendor_rev[0x20];
 797
 798         u8         fw_version[0x20];
 799
 800         u8         vendor_sn[16][0x8];
 801
 802         u8         temperature[0x10];
 803         u8         voltage[0x10];
 804
 805         u8         rx_power_lane0[0x10];
 806         u8         rx_power_lane1[0x10];
 807
 808         u8         rx_power_lane2[0x10];
 809         u8         rx_power_lane3[0x10];
 810
 811         u8         reserved_at_2c0[0x40];
 812
 813         u8         tx_power_lane0[0x10];
 814         u8         tx_power_lane1[0x10];
 815
 816         u8         tx_power_lane2[0x10];
 817         u8         tx_power_lane3[0x10];
 818
 819         u8         reserved_at_340[0x40];
 820
 821         u8         tx_bias_lane0[0x10];
 822         u8         tx_bias_lane1[0x10];
 823
 824         u8         tx_bias_lane2[0x10];
 825         u8         tx_bias_lane3[0x10];
 826
 827         u8         reserved_at_3c0[0x40];
 828
 829         u8         temperature_high_th[0x10];
 830         u8         temperature_low_th[0x10];
 831
 832         u8         voltage_high_th[0x10];
 833         u8         voltage_low_th[0x10];
 834
 835         u8         rx_power_high_th[0x10];
 836         u8         rx_power_low_th[0x10];
 837
 838         u8         tx_power_high_th[0x10];
 839         u8         tx_power_low_th[0x10];
 840
 841         u8         tx_bias_high_th[0x10];
 842         u8         tx_bias_low_th[0x10];
 843
 844         u8         reserved_at_4a0[0x10];
 845         u8         wavelength[0x10];
 846
 847         u8         reserved_at_4c0[0x300];
 848 };
 849
 850 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
 851         struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
 852         u8         reserved_at_0[0x7c0];
 853 };
 854
 855 struct mlx5_ifc_pddr_reg_bits {
 856         u8         reserved_at_0[0x8];
 857         u8         local_port[0x8];
 858         u8         pnat[0x2];
 859         u8         reserved_at_12[0xe];
 860
 861         u8         reserved_at_20[0x18];
 862         u8         page_select[0x8];
 863
 864         union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
 865 };
 866
 867 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 868         u8         csum_cap[0x1];
 869         u8         vlan_cap[0x1];
 870         u8         lro_cap[0x1];
 871         u8         lro_psh_flag[0x1];
 872         u8         lro_time_stamp[0x1];
 873         u8         lro_max_msg_sz_mode[0x2];
 874         u8         wqe_vlan_insert[0x1];
 875         u8         self_lb_en_modifiable[0x1];
 876         u8         self_lb_mc[0x1];
 877         u8         self_lb_uc[0x1];
 878         u8         max_lso_cap[0x5];
 879         u8         multi_pkt_send_wqe[0x2];
 880         u8         wqe_inline_mode[0x2];
 881         u8         rss_ind_tbl_cap[0x4];
 882         u8         scatter_fcs[0x1];
 883         u8         reserved_1[0x2];
 884         u8         tunnel_lso_const_out_ip_id[0x1];
 885         u8         tunnel_lro_gre[0x1];
 886         u8         tunnel_lro_vxlan[0x1];
 887         u8         tunnel_statless_gre[0x1];
 888         u8         tunnel_stateless_vxlan[0x1];
 889
 890         u8         swp[0x1];
 891         u8         swp_csum[0x1];
 892         u8         swp_lso[0x1];
 893         u8         reserved_2[0x1b];
 894         u8         max_geneve_opt_len[0x1];
 895         u8         tunnel_stateless_geneve_rx[0x1];
 896
 897         u8         reserved_3[0x10];
 898         u8         lro_min_mss_size[0x10];
 899
 900         u8         reserved_4[0x120];
 901
 902         u8         lro_timer_supported_periods[4][0x20];
 903
 904         u8         reserved_5[0x600];
 905 };
 906
 907 enum {
 908         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 909         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 910         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 911 };
 912
 913 struct mlx5_ifc_roce_cap_bits {
 914         u8         roce_apm[0x1];
 915         u8         rts2rts_primary_eth_prio[0x1];
 916         u8         roce_rx_allow_untagged[0x1];
 917         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 918
 919         u8         reserved_0[0x1c];
 920
 921         u8         reserved_1[0x60];
 922
 923         u8         reserved_2[0xc];
 924         u8         l3_type[0x4];
 925         u8         reserved_3[0x8];
 926         u8         roce_version[0x8];
 927
 928         u8         reserved_4[0x10];
 929         u8         r_roce_dest_udp_port[0x10];
 930
 931         u8         r_roce_max_src_udp_port[0x10];
 932         u8         r_roce_min_src_udp_port[0x10];
 933
 934         u8         reserved_5[0x10];
 935         u8         roce_address_table_size[0x10];
 936
 937         u8         reserved_6[0x700];
 938 };
 939
 940 enum {
 941         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 942         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 943         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 944         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 945         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 946         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 947         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 948         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 949         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 950 };
 951
 952 enum {
 953         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 954         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 955         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 956         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 957         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 958         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 959         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 960         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 961         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 962 };
 963
 964 struct mlx5_ifc_atomic_caps_bits {
 965         u8         reserved_0[0x40];
 966
 967         u8         atomic_req_8B_endianess_mode[0x2];
 968         u8         reserved_1[0x4];
 969         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 970
 971         u8         reserved_2[0x19];
 972
 973         u8         reserved_3[0x20];
 974
 975         u8         reserved_4[0x10];
 976         u8         atomic_operations[0x10];
 977
 978         u8         reserved_5[0x10];
 979         u8         atomic_size_qp[0x10];
 980
 981         u8         reserved_6[0x10];
 982         u8         atomic_size_dc[0x10];
 983
 984         u8         reserved_7[0x720];
 985 };
 986
 987 struct mlx5_ifc_odp_cap_bits {
 988         u8         reserved_0[0x40];
 989
 990         u8         sig[0x1];
 991         u8         reserved_1[0x1f];
 992
 993         u8         reserved_2[0x20];
 994
 995         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 996
 997         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 998
 999         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1000
1001         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1002
1003         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1004
1005         u8         reserved_3[0x6e0];
1006 };
1007
1008 enum {
1009         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1010         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1011         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1012         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1013         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1014 };
1015
1016 enum {
1017         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1018         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1019         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1020         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1021         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1022         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1023 };
1024
1025 enum {
1026         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1027         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1028 };
1029
1030 enum {
1031         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1032         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1033         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1034 };
1035
1036 struct mlx5_ifc_cmd_hca_cap_bits {
1037         u8         reserved_0[0x80];
1038
1039         u8         log_max_srq_sz[0x8];
1040         u8         log_max_qp_sz[0x8];
1041         u8         reserved_1[0xb];
1042         u8         log_max_qp[0x5];
1043
1044         u8         reserved_2[0xb];
1045         u8         log_max_srq[0x5];
1046         u8         reserved_3[0x10];
1047
1048         u8         reserved_4[0x8];
1049         u8         log_max_cq_sz[0x8];
1050         u8         reserved_5[0xb];
1051         u8         log_max_cq[0x5];
1052
1053         u8         log_max_eq_sz[0x8];
1054         u8         relaxed_ordering_write[1];
1055         u8         reserved_6[0x1];
1056         u8         log_max_mkey[0x6];
1057         u8         reserved_7[0xc];
1058         u8         log_max_eq[0x4];
1059
1060         u8         max_indirection[0x8];
1061         u8         reserved_8[0x1];
1062         u8         log_max_mrw_sz[0x7];
1063         u8         force_teardown[0x1];
1064         u8         reserved_9[0x1];
1065         u8         log_max_bsf_list_size[0x6];
1066         u8         reserved_10[0x2];
1067         u8         log_max_klm_list_size[0x6];
1068
1069         u8         reserved_11[0xa];
1070         u8         log_max_ra_req_dc[0x6];
1071         u8         reserved_12[0xa];
1072         u8         log_max_ra_res_dc[0x6];
1073
1074         u8         reserved_13[0xa];
1075         u8         log_max_ra_req_qp[0x6];
1076         u8         reserved_14[0xa];
1077         u8         log_max_ra_res_qp[0x6];
1078
1079         u8         pad_cap[0x1];
1080         u8         cc_query_allowed[0x1];
1081         u8         cc_modify_allowed[0x1];
1082         u8         start_pad[0x1];
1083         u8         cache_line_128byte[0x1];
1084         u8         reserved_at_165[0xa];
1085         u8         qcam_reg[0x1];
1086         u8         gid_table_size[0x10];
1087
1088         u8         out_of_seq_cnt[0x1];
1089         u8         vport_counters[0x1];
1090         u8         retransmission_q_counters[0x1];
1091         u8         debug[0x1];
1092         u8         modify_rq_counters_set_id[0x1];
1093         u8         rq_delay_drop[0x1];
1094         u8         max_qp_cnt[0xa];
1095         u8         pkey_table_size[0x10];
1096
1097         u8         vport_group_manager[0x1];
1098         u8         vhca_group_manager[0x1];
1099         u8         ib_virt[0x1];
1100         u8         eth_virt[0x1];
1101         u8         reserved_17[0x1];
1102         u8         ets[0x1];
1103         u8         nic_flow_table[0x1];
1104         u8         eswitch_flow_table[0x1];
1105         u8         reserved_18[0x3];
1106         u8         local_ca_ack_delay[0x5];
1107         u8         port_module_event[0x1];
1108         u8         reserved_19[0x5];
1109         u8         port_type[0x2];
1110         u8         num_ports[0x8];
1111
1112         u8         snapshot[0x1];
1113         u8         reserved_20[0x2];
1114         u8         log_max_msg[0x5];
1115         u8         reserved_21[0x4];
1116         u8         max_tc[0x4];
1117         u8         temp_warn_event[0x1];
1118         u8         dcbx[0x1];
1119         u8         general_notification_event[0x1];
1120         u8         reserved_at_1d3[0x2];
1121         u8         fpga[0x1];
1122         u8         rol_s[0x1];
1123         u8         rol_g[0x1];
1124         u8         reserved_23[0x1];
1125         u8         wol_s[0x1];
1126         u8         wol_g[0x1];
1127         u8         wol_a[0x1];
1128         u8         wol_b[0x1];
1129         u8         wol_m[0x1];
1130         u8         wol_u[0x1];
1131         u8         wol_p[0x1];
1132
1133         u8         stat_rate_support[0x10];
1134         u8         reserved_24[0xc];
1135         u8         cqe_version[0x4];
1136
1137         u8         compact_address_vector[0x1];
1138         u8         striding_rq[0x1];
1139         u8         reserved_25[0x1];
1140         u8         ipoib_enhanced_offloads[0x1];
1141         u8         ipoib_ipoib_offloads[0x1];
1142         u8         reserved_26[0x8];
1143         u8         dc_connect_qp[0x1];
1144         u8         dc_cnak_trace[0x1];
1145         u8         drain_sigerr[0x1];
1146         u8         cmdif_checksum[0x2];
1147         u8         sigerr_cqe[0x1];
1148         u8         reserved_27[0x1];
1149         u8         wq_signature[0x1];
1150         u8         sctr_data_cqe[0x1];
1151         u8         reserved_28[0x1];
1152         u8         sho[0x1];
1153         u8         tph[0x1];
1154         u8         rf[0x1];
1155         u8         dct[0x1];
1156         u8         qos[0x1];
1157         u8         eth_net_offloads[0x1];
1158         u8         roce[0x1];
1159         u8         atomic[0x1];
1160         u8         reserved_30[0x1];
1161
1162         u8         cq_oi[0x1];
1163         u8         cq_resize[0x1];
1164         u8         cq_moderation[0x1];
1165         u8         cq_period_mode_modify[0x1];
1166         u8         cq_invalidate[0x1];
1167         u8         reserved_at_225[0x1];
1168         u8         cq_eq_remap[0x1];
1169         u8         pg[0x1];
1170         u8         block_lb_mc[0x1];
1171         u8         exponential_backoff[0x1];
1172         u8         scqe_break_moderation[0x1];
1173         u8         cq_period_start_from_cqe[0x1];
1174         u8         cd[0x1];
1175         u8         atm[0x1];
1176         u8         apm[0x1];
1177         u8         imaicl[0x1];
1178         u8         reserved_32[0x6];
1179         u8         qkv[0x1];
1180         u8         pkv[0x1];
1181         u8         set_deth_sqpn[0x1];
1182         u8         reserved_33[0x3];
1183         u8         xrc[0x1];
1184         u8         ud[0x1];
1185         u8         uc[0x1];
1186         u8         rc[0x1];
1187
1188         u8         reserved_34[0xa];
1189         u8         uar_sz[0x6];
1190         u8         reserved_35[0x8];
1191         u8         log_pg_sz[0x8];
1192
1193         u8         bf[0x1];
1194         u8         driver_version[0x1];
1195         u8         pad_tx_eth_packet[0x1];
1196         u8         reserved_36[0x8];
1197         u8         log_bf_reg_size[0x5];
1198         u8         reserved_37[0x10];
1199
1200         u8         num_of_diagnostic_counters[0x10];
1201         u8         max_wqe_sz_sq[0x10];
1202
1203         u8         reserved_38[0x10];
1204         u8         max_wqe_sz_rq[0x10];
1205
1206         u8         reserved_39[0x10];
1207         u8         max_wqe_sz_sq_dc[0x10];
1208
1209         u8         reserved_40[0x7];
1210         u8         max_qp_mcg[0x19];
1211
1212         u8         reserved_41[0x18];
1213         u8         log_max_mcg[0x8];
1214
1215         u8         reserved_42[0x3];
1216         u8         log_max_transport_domain[0x5];
1217         u8         reserved_43[0x3];
1218         u8         log_max_pd[0x5];
1219         u8         reserved_44[0xb];
1220         u8         log_max_xrcd[0x5];
1221
1222         u8         reserved_45[0x10];
1223         u8         max_flow_counter[0x10];
1224
1225         u8         reserved_46[0x3];
1226         u8         log_max_rq[0x5];
1227         u8         reserved_47[0x3];
1228         u8         log_max_sq[0x5];
1229         u8         reserved_48[0x3];
1230         u8         log_max_tir[0x5];
1231         u8         reserved_49[0x3];
1232         u8         log_max_tis[0x5];
1233
1234         u8         basic_cyclic_rcv_wqe[0x1];
1235         u8         reserved_50[0x2];
1236         u8         log_max_rmp[0x5];
1237         u8         reserved_51[0x3];
1238         u8         log_max_rqt[0x5];
1239         u8         reserved_52[0x3];
1240         u8         log_max_rqt_size[0x5];
1241         u8         reserved_53[0x3];
1242         u8         log_max_tis_per_sq[0x5];
1243
1244         u8         reserved_54[0x3];
1245         u8         log_max_stride_sz_rq[0x5];
1246         u8         reserved_55[0x3];
1247         u8         log_min_stride_sz_rq[0x5];
1248         u8         reserved_56[0x3];
1249         u8         log_max_stride_sz_sq[0x5];
1250         u8         reserved_57[0x3];
1251         u8         log_min_stride_sz_sq[0x5];
1252
1253         u8         reserved_58[0x1b];
1254         u8         log_max_wq_sz[0x5];
1255
1256         u8         nic_vport_change_event[0x1];
1257         u8         disable_local_lb[0x1];
1258         u8         reserved_59[0x9];
1259         u8         log_max_vlan_list[0x5];
1260         u8         reserved_60[0x3];
1261         u8         log_max_current_mc_list[0x5];
1262         u8         reserved_61[0x3];
1263         u8         log_max_current_uc_list[0x5];
1264
1265         u8         reserved_62[0x80];
1266
1267         u8         reserved_63[0x3];
1268         u8         log_max_l2_table[0x5];
1269         u8         reserved_64[0x8];
1270         u8         log_uar_page_sz[0x10];
1271
1272         u8         reserved_65[0x20];
1273
1274         u8         device_frequency_mhz[0x20];
1275
1276         u8         device_frequency_khz[0x20];
1277
1278         u8         reserved_66[0x80];
1279
1280         u8         log_max_atomic_size_qp[0x8];
1281         u8         reserved_67[0x10];
1282         u8         log_max_atomic_size_dc[0x8];
1283
1284         u8         reserved_68[0x1f];
1285         u8         cqe_compression[0x1];
1286
1287         u8         cqe_compression_timeout[0x10];
1288         u8         cqe_compression_max_num[0x10];
1289
1290         u8         reserved_69[0x220];
1291 };
1292
1293 enum mlx5_flow_destination_type {
1294         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1295         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1296         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1297 };
1298
1299 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1300         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1301         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1302         u8         reserved_0[0x40];
1303 };
1304
1305 struct mlx5_ifc_fte_match_param_bits {
1306         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1307
1308         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1309
1310         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1311
1312         u8         reserved_0[0xa00];
1313 };
1314
1315 enum {
1316         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1317         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1318         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1319         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1320         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1321 };
1322
1323 struct mlx5_ifc_rx_hash_field_select_bits {
1324         u8         l3_prot_type[0x1];
1325         u8         l4_prot_type[0x1];
1326         u8         selected_fields[0x1e];
1327 };
1328
1329 enum {
1330         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1331         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1332         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1333         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1334 };
1335
1336 enum rq_type {
1337         RQ_TYPE_NONE,
1338         RQ_TYPE_STRIDE,
1339 };
1340
1341 enum {
1342         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1343         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1344 };
1345
1346 struct mlx5_ifc_wq_bits {
1347         u8         wq_type[0x4];
1348         u8         wq_signature[0x1];
1349         u8         end_padding_mode[0x2];
1350         u8         cd_slave[0x1];
1351         u8         reserved_0[0x18];
1352
1353         u8         hds_skip_first_sge[0x1];
1354         u8         log2_hds_buf_size[0x3];
1355         u8         reserved_1[0x7];
1356         u8         page_offset[0x5];
1357         u8         lwm[0x10];
1358
1359         u8         reserved_2[0x8];
1360         u8         pd[0x18];
1361
1362         u8         reserved_3[0x8];
1363         u8         uar_page[0x18];
1364
1365         u8         dbr_addr[0x40];
1366
1367         u8         hw_counter[0x20];
1368
1369         u8         sw_counter[0x20];
1370
1371         u8         reserved_4[0xc];
1372         u8         log_wq_stride[0x4];
1373         u8         reserved_5[0x3];
1374         u8         log_wq_pg_sz[0x5];
1375         u8         reserved_6[0x3];
1376         u8         log_wq_sz[0x5];
1377
1378         u8         reserved_7[0x15];
1379         u8         single_wqe_log_num_of_strides[0x3];
1380         u8         two_byte_shift_en[0x1];
1381         u8         reserved_8[0x4];
1382         u8         single_stride_log_num_of_bytes[0x3];
1383
1384         u8         reserved_9[0x4c0];
1385
1386         struct mlx5_ifc_cmd_pas_bits pas[0];
1387 };
1388
1389 struct mlx5_ifc_rq_num_bits {
1390         u8         reserved_0[0x8];
1391         u8         rq_num[0x18];
1392 };
1393
1394 struct mlx5_ifc_mac_address_layout_bits {
1395         u8         reserved_0[0x10];
1396         u8         mac_addr_47_32[0x10];
1397
1398         u8         mac_addr_31_0[0x20];
1399 };
1400
1401 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1402         u8         reserved_0[0xa0];
1403
1404         u8         min_time_between_cnps[0x20];
1405
1406         u8         reserved_1[0x12];
1407         u8         cnp_dscp[0x6];
1408         u8         reserved_2[0x4];
1409         u8         cnp_prio_mode[0x1];
1410         u8         cnp_802p_prio[0x3];
1411
1412         u8         reserved_3[0x720];
1413 };
1414
1415 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1416         u8         reserved_0[0x60];
1417
1418         u8         reserved_1[0x4];
1419         u8         clamp_tgt_rate[0x1];
1420         u8         reserved_2[0x3];
1421         u8         clamp_tgt_rate_after_time_inc[0x1];
1422         u8         reserved_3[0x17];
1423
1424         u8         reserved_4[0x20];
1425
1426         u8         rpg_time_reset[0x20];
1427
1428         u8         rpg_byte_reset[0x20];
1429
1430         u8         rpg_threshold[0x20];
1431
1432         u8         rpg_max_rate[0x20];
1433
1434         u8         rpg_ai_rate[0x20];
1435
1436         u8         rpg_hai_rate[0x20];
1437
1438         u8         rpg_gd[0x20];
1439
1440         u8         rpg_min_dec_fac[0x20];
1441
1442         u8         rpg_min_rate[0x20];
1443
1444         u8         reserved_5[0xe0];
1445
1446         u8         rate_to_set_on_first_cnp[0x20];
1447
1448         u8         dce_tcp_g[0x20];
1449
1450         u8         dce_tcp_rtt[0x20];
1451
1452         u8         rate_reduce_monitor_period[0x20];
1453
1454         u8         reserved_6[0x20];
1455
1456         u8         initial_alpha_value[0x20];
1457
1458         u8         reserved_7[0x4a0];
1459 };
1460
1461 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1462         u8         reserved_0[0x80];
1463
1464         u8         rppp_max_rps[0x20];
1465
1466         u8         rpg_time_reset[0x20];
1467
1468         u8         rpg_byte_reset[0x20];
1469
1470         u8         rpg_threshold[0x20];
1471
1472         u8         rpg_max_rate[0x20];
1473
1474         u8         rpg_ai_rate[0x20];
1475
1476         u8         rpg_hai_rate[0x20];
1477
1478         u8         rpg_gd[0x20];
1479
1480         u8         rpg_min_dec_fac[0x20];
1481
1482         u8         rpg_min_rate[0x20];
1483
1484         u8         reserved_1[0x640];
1485 };
1486
1487 enum {
1488         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1489         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1490         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1491 };
1492
1493 struct mlx5_ifc_resize_field_select_bits {
1494         u8         resize_field_select[0x20];
1495 };
1496
1497 enum {
1498         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1499         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1500         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1501         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1502         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1503         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1504 };
1505
1506 struct mlx5_ifc_modify_field_select_bits {
1507         u8         modify_field_select[0x20];
1508 };
1509
1510 struct mlx5_ifc_field_select_r_roce_np_bits {
1511         u8         field_select_r_roce_np[0x20];
1512 };
1513
1514 enum {
1515         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1516         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1517         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1518         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1519         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1520         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1521         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1522         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1523         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1524         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1525         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1526         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1527         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1528         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1529         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1530 };
1531
1532 struct mlx5_ifc_field_select_r_roce_rp_bits {
1533         u8         field_select_r_roce_rp[0x20];
1534 };
1535
1536 enum {
1537         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1538         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1539         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1540         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1541         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1542         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1543         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1544         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1545         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1546         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1547 };
1548
1549 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1550         u8         field_select_8021qaurp[0x20];
1551 };
1552
1553 struct mlx5_ifc_pptb_reg_bits {
1554         u8         reserved_0[0x2];
1555         u8         mm[0x2];
1556         u8         reserved_1[0x4];
1557         u8         local_port[0x8];
1558         u8         reserved_2[0x6];
1559         u8         cm[0x1];
1560         u8         um[0x1];
1561         u8         pm[0x8];
1562
1563         u8         prio7buff[0x4];
1564         u8         prio6buff[0x4];
1565         u8         prio5buff[0x4];
1566         u8         prio4buff[0x4];
1567         u8         prio3buff[0x4];
1568         u8         prio2buff[0x4];
1569         u8         prio1buff[0x4];
1570         u8         prio0buff[0x4];
1571
1572         u8         pm_msb[0x8];
1573         u8         reserved_3[0x10];
1574         u8         ctrl_buff[0x4];
1575         u8         untagged_buff[0x4];
1576 };
1577
1578 struct mlx5_ifc_dcbx_app_reg_bits {
1579         u8         reserved_0[0x8];
1580         u8         port_number[0x8];
1581         u8         reserved_1[0x10];
1582
1583         u8         reserved_2[0x1a];
1584         u8         num_app_prio[0x6];
1585
1586         u8         reserved_3[0x40];
1587
1588         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1589 };
1590
1591 struct mlx5_ifc_dcbx_param_reg_bits {
1592         u8         dcbx_cee_cap[0x1];
1593         u8         dcbx_ieee_cap[0x1];
1594         u8         dcbx_standby_cap[0x1];
1595         u8         reserved_0[0x5];
1596         u8         port_number[0x8];
1597         u8         reserved_1[0xa];
1598         u8         max_application_table_size[0x6];
1599
1600         u8         reserved_2[0x15];
1601         u8         version_oper[0x3];
1602         u8         reserved_3[0x5];
1603         u8         version_admin[0x3];
1604
1605         u8         willing_admin[0x1];
1606         u8         reserved_4[0x3];
1607         u8         pfc_cap_oper[0x4];
1608         u8         reserved_5[0x4];
1609         u8         pfc_cap_admin[0x4];
1610         u8         reserved_6[0x4];
1611         u8         num_of_tc_oper[0x4];
1612         u8         reserved_7[0x4];
1613         u8         num_of_tc_admin[0x4];
1614
1615         u8         remote_willing[0x1];
1616         u8         reserved_8[0x3];
1617         u8         remote_pfc_cap[0x4];
1618         u8         reserved_9[0x14];
1619         u8         remote_num_of_tc[0x4];
1620
1621         u8         reserved_10[0x18];
1622         u8         error[0x8];
1623
1624         u8         reserved_11[0x160];
1625 };
1626
1627 struct mlx5_ifc_qhll_bits {
1628         u8         reserved_at_0[0x8];
1629         u8         local_port[0x8];
1630         u8         reserved_at_10[0x10];
1631
1632         u8         reserved_at_20[0x1b];
1633         u8         hll_time[0x5];
1634
1635         u8         stall_en[0x1];
1636         u8         reserved_at_41[0x1c];
1637         u8         stall_cnt[0x3];
1638 };
1639
1640 struct mlx5_ifc_qetcr_reg_bits {
1641         u8         operation_type[0x2];
1642         u8         cap_local_admin[0x1];
1643         u8         cap_remote_admin[0x1];
1644         u8         reserved_0[0x4];
1645         u8         port_number[0x8];
1646         u8         reserved_1[0x10];
1647
1648         u8         reserved_2[0x20];
1649
1650         u8         tc[8][0x40];
1651
1652         u8         global_configuration[0x40];
1653 };
1654
1655 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1656         u8         queue_address_63_32[0x20];
1657
1658         u8         queue_address_31_12[0x14];
1659         u8         reserved_0[0x6];
1660         u8         log_size[0x6];
1661
1662         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1663
1664         u8         reserved_1[0x8];
1665         u8         queue_number[0x18];
1666
1667         u8         q_key[0x20];
1668
1669         u8         reserved_2[0x10];
1670         u8         pkey_index[0x10];
1671
1672         u8         reserved_3[0x40];
1673 };
1674
1675 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1676         u8         reserved_0[0x8];
1677         u8         cq_ci[0x10];
1678         u8         reserved_1[0x8];
1679 };
1680
1681 enum {
1682         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1683         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1684 };
1685
1686 enum {
1687         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1688         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1689         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1690         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1691 };
1692
1693 struct mlx5_ifc_nodnic_event_word_bits {
1694         u8         driver_reset_needed[0x1];
1695         u8         port_management_change_event[0x1];
1696         u8         reserved_0[0x19];
1697         u8         link_type[0x1];
1698         u8         port_state[0x4];
1699 };
1700
1701 struct mlx5_ifc_nic_vport_change_event_bits {
1702         u8         reserved_0[0x10];
1703         u8         vport_num[0x10];
1704
1705         u8         reserved_1[0xc0];
1706 };
1707
1708 struct mlx5_ifc_pages_req_event_bits {
1709         u8         reserved_0[0x10];
1710         u8         function_id[0x10];
1711
1712         u8         num_pages[0x20];
1713
1714         u8         reserved_1[0xa0];
1715 };
1716
1717 struct mlx5_ifc_cmd_inter_comp_event_bits {
1718         u8         command_completion_vector[0x20];
1719
1720         u8         reserved_0[0xc0];
1721 };
1722
1723 struct mlx5_ifc_stall_vl_event_bits {
1724         u8         reserved_0[0x18];
1725         u8         port_num[0x1];
1726         u8         reserved_1[0x3];
1727         u8         vl[0x4];
1728
1729         u8         reserved_2[0xa0];
1730 };
1731
1732 struct mlx5_ifc_db_bf_congestion_event_bits {
1733         u8         event_subtype[0x8];
1734         u8         reserved_0[0x8];
1735         u8         congestion_level[0x8];
1736         u8         reserved_1[0x8];
1737
1738         u8         reserved_2[0xa0];
1739 };
1740
1741 struct mlx5_ifc_gpio_event_bits {
1742         u8         reserved_0[0x60];
1743
1744         u8         gpio_event_hi[0x20];
1745
1746         u8         gpio_event_lo[0x20];
1747
1748         u8         reserved_1[0x40];
1749 };
1750
1751 struct mlx5_ifc_port_state_change_event_bits {
1752         u8         reserved_0[0x40];
1753
1754         u8         port_num[0x4];
1755         u8         reserved_1[0x1c];
1756
1757         u8         reserved_2[0x80];
1758 };
1759
1760 struct mlx5_ifc_dropped_packet_logged_bits {
1761         u8         reserved_0[0xe0];
1762 };
1763
1764 enum {
1765         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1766         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1767 };
1768
1769 struct mlx5_ifc_cq_error_bits {
1770         u8         reserved_0[0x8];
1771         u8         cqn[0x18];
1772
1773         u8         reserved_1[0x20];
1774
1775         u8         reserved_2[0x18];
1776         u8         syndrome[0x8];
1777
1778         u8         reserved_3[0x80];
1779 };
1780
1781 struct mlx5_ifc_rdma_page_fault_event_bits {
1782         u8         bytes_commited[0x20];
1783
1784         u8         r_key[0x20];
1785
1786         u8         reserved_0[0x10];
1787         u8         packet_len[0x10];
1788
1789         u8         rdma_op_len[0x20];
1790
1791         u8         rdma_va[0x40];
1792
1793         u8         reserved_1[0x5];
1794         u8         rdma[0x1];
1795         u8         write[0x1];
1796         u8         requestor[0x1];
1797         u8         qp_number[0x18];
1798 };
1799
1800 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1801         u8         bytes_committed[0x20];
1802
1803         u8         reserved_0[0x10];
1804         u8         wqe_index[0x10];
1805
1806         u8         reserved_1[0x10];
1807         u8         len[0x10];
1808
1809         u8         reserved_2[0x60];
1810
1811         u8         reserved_3[0x5];
1812         u8         rdma[0x1];
1813         u8         write_read[0x1];
1814         u8         requestor[0x1];
1815         u8         qpn[0x18];
1816 };
1817
1818 enum {
1819         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1820         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1821         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1822 };
1823
1824 struct mlx5_ifc_qp_events_bits {
1825         u8         reserved_0[0xa0];
1826
1827         u8         type[0x8];
1828         u8         reserved_1[0x18];
1829
1830         u8         reserved_2[0x8];
1831         u8         qpn_rqn_sqn[0x18];
1832 };
1833
1834 struct mlx5_ifc_dct_events_bits {
1835         u8         reserved_0[0xc0];
1836
1837         u8         reserved_1[0x8];
1838         u8         dct_number[0x18];
1839 };
1840
1841 struct mlx5_ifc_comp_event_bits {
1842         u8         reserved_0[0xc0];
1843
1844         u8         reserved_1[0x8];
1845         u8         cq_number[0x18];
1846 };
1847
1848 struct mlx5_ifc_fw_version_bits {
1849         u8         major[0x10];
1850         u8         reserved_0[0x10];
1851
1852         u8         minor[0x10];
1853         u8         subminor[0x10];
1854
1855         u8         second[0x8];
1856         u8         minute[0x8];
1857         u8         hour[0x8];
1858         u8         reserved_1[0x8];
1859
1860         u8         year[0x10];
1861         u8         month[0x8];
1862         u8         day[0x8];
1863 };
1864
1865 enum {
1866         MLX5_QPC_STATE_RST        = 0x0,
1867         MLX5_QPC_STATE_INIT       = 0x1,
1868         MLX5_QPC_STATE_RTR        = 0x2,
1869         MLX5_QPC_STATE_RTS        = 0x3,
1870         MLX5_QPC_STATE_SQER       = 0x4,
1871         MLX5_QPC_STATE_SQD        = 0x5,
1872         MLX5_QPC_STATE_ERR        = 0x6,
1873         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1874 };
1875
1876 enum {
1877         MLX5_QPC_ST_RC            = 0x0,
1878         MLX5_QPC_ST_UC            = 0x1,
1879         MLX5_QPC_ST_UD            = 0x2,
1880         MLX5_QPC_ST_XRC           = 0x3,
1881         MLX5_QPC_ST_DCI           = 0x5,
1882         MLX5_QPC_ST_QP0           = 0x7,
1883         MLX5_QPC_ST_QP1           = 0x8,
1884         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1885         MLX5_QPC_ST_REG_UMR       = 0xc,
1886 };
1887
1888 enum {
1889         MLX5_QP_PM_ARMED            = 0x0,
1890         MLX5_QP_PM_REARM            = 0x1,
1891         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1892         MLX5_QP_PM_MIGRATED         = 0x3,
1893 };
1894
1895 enum {
1896         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1897         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1898 };
1899
1900 enum {
1901         MLX5_QPC_MTU_256_BYTES        = 0x1,
1902         MLX5_QPC_MTU_512_BYTES        = 0x2,
1903         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1904         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1905         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1906         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1907 };
1908
1909 enum {
1910         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1911         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1912         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1913         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1914         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1915         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1916         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1917         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1918 };
1919
1920 enum {
1921         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1922         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1923         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1924 };
1925
1926 enum {
1927         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1928         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1929         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1930 };
1931
1932 struct mlx5_ifc_qpc_bits {
1933         u8         state[0x4];
1934         u8         lag_tx_port_affinity[0x4];
1935         u8         st[0x8];
1936         u8         reserved_1[0x3];
1937         u8         pm_state[0x2];
1938         u8         reserved_2[0x7];
1939         u8         end_padding_mode[0x2];
1940         u8         reserved_3[0x2];
1941
1942         u8         wq_signature[0x1];
1943         u8         block_lb_mc[0x1];
1944         u8         atomic_like_write_en[0x1];
1945         u8         latency_sensitive[0x1];
1946         u8         reserved_4[0x1];
1947         u8         drain_sigerr[0x1];
1948         u8         reserved_5[0x2];
1949         u8         pd[0x18];
1950
1951         u8         mtu[0x3];
1952         u8         log_msg_max[0x5];
1953         u8         reserved_6[0x1];
1954         u8         log_rq_size[0x4];
1955         u8         log_rq_stride[0x3];
1956         u8         no_sq[0x1];
1957         u8         log_sq_size[0x4];
1958         u8         reserved_7[0x6];
1959         u8         rlky[0x1];
1960         u8         ulp_stateless_offload_mode[0x4];
1961
1962         u8         counter_set_id[0x8];
1963         u8         uar_page[0x18];
1964
1965         u8         reserved_8[0x8];
1966         u8         user_index[0x18];
1967
1968         u8         reserved_9[0x3];
1969         u8         log_page_size[0x5];
1970         u8         remote_qpn[0x18];
1971
1972         struct mlx5_ifc_ads_bits primary_address_path;
1973
1974         struct mlx5_ifc_ads_bits secondary_address_path;
1975
1976         u8         log_ack_req_freq[0x4];
1977         u8         reserved_10[0x4];
1978         u8         log_sra_max[0x3];
1979         u8         reserved_11[0x2];
1980         u8         retry_count[0x3];
1981         u8         rnr_retry[0x3];
1982         u8         reserved_12[0x1];
1983         u8         fre[0x1];
1984         u8         cur_rnr_retry[0x3];
1985         u8         cur_retry_count[0x3];
1986         u8         reserved_13[0x5];
1987
1988         u8         reserved_14[0x20];
1989
1990         u8         reserved_15[0x8];
1991         u8         next_send_psn[0x18];
1992
1993         u8         reserved_16[0x8];
1994         u8         cqn_snd[0x18];
1995
1996         u8         reserved_at_400[0x8];
1997
1998         u8         deth_sqpn[0x18];
1999         u8         reserved_17[0x20];
2000
2001         u8         reserved_18[0x8];
2002         u8         last_acked_psn[0x18];
2003
2004         u8         reserved_19[0x8];
2005         u8         ssn[0x18];
2006
2007         u8         reserved_20[0x8];
2008         u8         log_rra_max[0x3];
2009         u8         reserved_21[0x1];
2010         u8         atomic_mode[0x4];
2011         u8         rre[0x1];
2012         u8         rwe[0x1];
2013         u8         rae[0x1];
2014         u8         reserved_22[0x1];
2015         u8         page_offset[0x6];
2016         u8         reserved_23[0x3];
2017         u8         cd_slave_receive[0x1];
2018         u8         cd_slave_send[0x1];
2019         u8         cd_master[0x1];
2020
2021         u8         reserved_24[0x3];
2022         u8         min_rnr_nak[0x5];
2023         u8         next_rcv_psn[0x18];
2024
2025         u8         reserved_25[0x8];
2026         u8         xrcd[0x18];
2027
2028         u8         reserved_26[0x8];
2029         u8         cqn_rcv[0x18];
2030
2031         u8         dbr_addr[0x40];
2032
2033         u8         q_key[0x20];
2034
2035         u8         reserved_27[0x5];
2036         u8         rq_type[0x3];
2037         u8         srqn_rmpn[0x18];
2038
2039         u8         reserved_28[0x8];
2040         u8         rmsn[0x18];
2041
2042         u8         hw_sq_wqebb_counter[0x10];
2043         u8         sw_sq_wqebb_counter[0x10];
2044
2045         u8         hw_rq_counter[0x20];
2046
2047         u8         sw_rq_counter[0x20];
2048
2049         u8         reserved_29[0x20];
2050
2051         u8         reserved_30[0xf];
2052         u8         cgs[0x1];
2053         u8         cs_req[0x8];
2054         u8         cs_res[0x8];
2055
2056         u8         dc_access_key[0x40];
2057
2058         u8         rdma_active[0x1];
2059         u8         comm_est[0x1];
2060         u8         suspended[0x1];
2061         u8         reserved_31[0x5];
2062         u8         send_msg_psn[0x18];
2063
2064         u8         reserved_32[0x8];
2065         u8         rcv_msg_psn[0x18];
2066
2067         u8         rdma_va[0x40];
2068
2069         u8         rdma_key[0x20];
2070
2071         u8         reserved_33[0x20];
2072 };
2073
2074 struct mlx5_ifc_roce_addr_layout_bits {
2075         u8         source_l3_address[16][0x8];
2076
2077         u8         reserved_0[0x3];
2078         u8         vlan_valid[0x1];
2079         u8         vlan_id[0xc];
2080         u8         source_mac_47_32[0x10];
2081
2082         u8         source_mac_31_0[0x20];
2083
2084         u8         reserved_1[0x14];
2085         u8         roce_l3_type[0x4];
2086         u8         roce_version[0x8];
2087
2088         u8         reserved_2[0x20];
2089 };
2090
2091 struct mlx5_ifc_rdbc_bits {
2092         u8         reserved_0[0x1c];
2093         u8         type[0x4];
2094
2095         u8         reserved_1[0x20];
2096
2097         u8         reserved_2[0x8];
2098         u8         psn[0x18];
2099
2100         u8         rkey[0x20];
2101
2102         u8         address[0x40];
2103
2104         u8         byte_count[0x20];
2105
2106         u8         reserved_3[0x20];
2107
2108         u8         atomic_resp[32][0x8];
2109 };
2110
2111 enum {
2112         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2113         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2114         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2115         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2116 };
2117
2118 struct mlx5_ifc_flow_context_bits {
2119         u8         reserved_0[0x20];
2120
2121         u8         group_id[0x20];
2122
2123         u8         reserved_1[0x8];
2124         u8         flow_tag[0x18];
2125
2126         u8         reserved_2[0x10];
2127         u8         action[0x10];
2128
2129         u8         reserved_3[0x8];
2130         u8         destination_list_size[0x18];
2131
2132         u8         reserved_4[0x8];
2133         u8         flow_counter_list_size[0x18];
2134
2135         u8         reserved_5[0x140];
2136
2137         struct mlx5_ifc_fte_match_param_bits match_value;
2138
2139         u8         reserved_6[0x600];
2140
2141         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2142 };
2143
2144 enum {
2145         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2146         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2147 };
2148
2149 struct mlx5_ifc_xrc_srqc_bits {
2150         u8         state[0x4];
2151         u8         log_xrc_srq_size[0x4];
2152         u8         reserved_0[0x18];
2153
2154         u8         wq_signature[0x1];
2155         u8         cont_srq[0x1];
2156         u8         reserved_1[0x1];
2157         u8         rlky[0x1];
2158         u8         basic_cyclic_rcv_wqe[0x1];
2159         u8         log_rq_stride[0x3];
2160         u8         xrcd[0x18];
2161
2162         u8         page_offset[0x6];
2163         u8         reserved_2[0x2];
2164         u8         cqn[0x18];
2165
2166         u8         reserved_3[0x20];
2167
2168         u8         reserved_4[0x2];
2169         u8         log_page_size[0x6];
2170         u8         user_index[0x18];
2171
2172         u8         reserved_5[0x20];
2173
2174         u8         reserved_6[0x8];
2175         u8         pd[0x18];
2176
2177         u8         lwm[0x10];
2178         u8         wqe_cnt[0x10];
2179
2180         u8         reserved_7[0x40];
2181
2182         u8         db_record_addr_h[0x20];
2183
2184         u8         db_record_addr_l[0x1e];
2185         u8         reserved_8[0x2];
2186
2187         u8         reserved_9[0x80];
2188 };
2189
2190 struct mlx5_ifc_traffic_counter_bits {
2191         u8         packets[0x40];
2192
2193         u8         octets[0x40];
2194 };
2195
2196 struct mlx5_ifc_tisc_bits {
2197         u8         strict_lag_tx_port_affinity[0x1];
2198         u8         reserved_at_1[0x3];
2199         u8         lag_tx_port_affinity[0x04];
2200
2201         u8         reserved_at_8[0x4];
2202         u8         prio[0x4];
2203         u8         reserved_1[0x10];
2204
2205         u8         reserved_2[0x100];
2206
2207         u8         reserved_3[0x8];
2208         u8         transport_domain[0x18];
2209
2210         u8         reserved_4[0x8];
2211         u8         underlay_qpn[0x18];
2212
2213         u8         reserved_5[0x3a0];
2214 };
2215
2216 enum {
2217         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2218         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2219 };
2220
2221 enum {
2222         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2223         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2224 };
2225
2226 enum {
2227         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2228         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2229         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2230 };
2231
2232 enum {
2233         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2234         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2235 };
2236
2237 struct mlx5_ifc_tirc_bits {
2238         u8         reserved_0[0x20];
2239
2240         u8         disp_type[0x4];
2241         u8         reserved_1[0x1c];
2242
2243         u8         reserved_2[0x40];
2244
2245         u8         reserved_3[0x4];
2246         u8         lro_timeout_period_usecs[0x10];
2247         u8         lro_enable_mask[0x4];
2248         u8         lro_max_msg_sz[0x8];
2249
2250         u8         reserved_4[0x40];
2251
2252         u8         reserved_5[0x8];
2253         u8         inline_rqn[0x18];
2254
2255         u8         rx_hash_symmetric[0x1];
2256         u8         reserved_6[0x1];
2257         u8         tunneled_offload_en[0x1];
2258         u8         reserved_7[0x5];
2259         u8         indirect_table[0x18];
2260
2261         u8         rx_hash_fn[0x4];
2262         u8         reserved_8[0x2];
2263         u8         self_lb_en[0x2];
2264         u8         transport_domain[0x18];
2265
2266         u8         rx_hash_toeplitz_key[10][0x20];
2267
2268         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2269
2270         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2271
2272         u8         reserved_9[0x4c0];
2273 };
2274
2275 enum {
2276         MLX5_SRQC_STATE_GOOD   = 0x0,
2277         MLX5_SRQC_STATE_ERROR  = 0x1,
2278 };
2279
2280 struct mlx5_ifc_srqc_bits {
2281         u8         state[0x4];
2282         u8         log_srq_size[0x4];
2283         u8         reserved_0[0x18];
2284
2285         u8         wq_signature[0x1];
2286         u8         cont_srq[0x1];
2287         u8         reserved_1[0x1];
2288         u8         rlky[0x1];
2289         u8         reserved_2[0x1];
2290         u8         log_rq_stride[0x3];
2291         u8         xrcd[0x18];
2292
2293         u8         page_offset[0x6];
2294         u8         reserved_3[0x2];
2295         u8         cqn[0x18];
2296
2297         u8         reserved_4[0x20];
2298
2299         u8         reserved_5[0x2];
2300         u8         log_page_size[0x6];
2301         u8         reserved_6[0x18];
2302
2303         u8         reserved_7[0x20];
2304
2305         u8         reserved_8[0x8];
2306         u8         pd[0x18];
2307
2308         u8         lwm[0x10];
2309         u8         wqe_cnt[0x10];
2310
2311         u8         reserved_9[0x40];
2312
2313         u8         dbr_addr[0x40];
2314
2315         u8         reserved_10[0x80];
2316 };
2317
2318 enum {
2319         MLX5_SQC_STATE_RST  = 0x0,
2320         MLX5_SQC_STATE_RDY  = 0x1,
2321         MLX5_SQC_STATE_ERR  = 0x3,
2322 };
2323
2324 struct mlx5_ifc_sqc_bits {
2325         u8         rlkey[0x1];
2326         u8         cd_master[0x1];
2327         u8         fre[0x1];
2328         u8         flush_in_error_en[0x1];
2329         u8         allow_multi_pkt_send_wqe[0x1];
2330         u8         min_wqe_inline_mode[0x3];
2331         u8         state[0x4];
2332         u8         reg_umr[0x1];
2333         u8         allow_swp[0x1];
2334         u8         reserved_0[0x12];
2335
2336         u8         reserved_1[0x8];
2337         u8         user_index[0x18];
2338
2339         u8         reserved_2[0x8];
2340         u8         cqn[0x18];
2341
2342         u8         reserved_3[0x80];
2343
2344         u8         qos_para_vport_number[0x10];
2345         u8         packet_pacing_rate_limit_index[0x10];
2346
2347         u8         tis_lst_sz[0x10];
2348         u8         reserved_4[0x10];
2349
2350         u8         reserved_5[0x40];
2351
2352         u8         reserved_6[0x8];
2353         u8         tis_num_0[0x18];
2354
2355         struct mlx5_ifc_wq_bits wq;
2356 };
2357
2358 enum {
2359         MLX5_TSAR_TYPE_DWRR = 0,
2360         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2361         MLX5_TSAR_TYPE_ETS = 2
2362 };
2363
2364 struct mlx5_ifc_tsar_element_attributes_bits {
2365         u8         reserved_0[0x8];
2366         u8         tsar_type[0x8];
2367         u8         reserved_1[0x10];
2368 };
2369
2370 struct mlx5_ifc_vport_element_attributes_bits {
2371         u8         reserved_0[0x10];
2372         u8         vport_number[0x10];
2373 };
2374
2375 struct mlx5_ifc_vport_tc_element_attributes_bits {
2376         u8         traffic_class[0x10];
2377         u8         vport_number[0x10];
2378 };
2379
2380 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2381         u8         reserved_0[0x0C];
2382         u8         traffic_class[0x04];
2383         u8         qos_para_vport_number[0x10];
2384 };
2385
2386 enum {
2387         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2388         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2389         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2390         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2391 };
2392
2393 struct mlx5_ifc_scheduling_context_bits {
2394         u8         element_type[0x8];
2395         u8         reserved_at_8[0x18];
2396
2397         u8         element_attributes[0x20];
2398
2399         u8         parent_element_id[0x20];
2400
2401         u8         reserved_at_60[0x40];
2402
2403         u8         bw_share[0x20];
2404
2405         u8         max_average_bw[0x20];
2406
2407         u8         reserved_at_e0[0x120];
2408 };
2409
2410 struct mlx5_ifc_rqtc_bits {
2411         u8         reserved_0[0xa0];
2412
2413         u8         reserved_1[0x10];
2414         u8         rqt_max_size[0x10];
2415
2416         u8         reserved_2[0x10];
2417         u8         rqt_actual_size[0x10];
2418
2419         u8         reserved_3[0x6a0];
2420
2421         struct mlx5_ifc_rq_num_bits rq_num[0];
2422 };
2423
2424 enum {
2425         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2426         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2427 };
2428
2429 enum {
2430         MLX5_RQC_STATE_RST  = 0x0,
2431         MLX5_RQC_STATE_RDY  = 0x1,
2432         MLX5_RQC_STATE_ERR  = 0x3,
2433 };
2434
2435 enum {
2436         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2437         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2438 };
2439
2440 struct mlx5_ifc_rqc_bits {
2441         u8         rlkey[0x1];
2442         u8         delay_drop_en[0x1];
2443         u8         scatter_fcs[0x1];
2444         u8         vlan_strip_disable[0x1];
2445         u8         mem_rq_type[0x4];
2446         u8         state[0x4];
2447         u8         reserved_1[0x1];
2448         u8         flush_in_error_en[0x1];
2449         u8         reserved_2[0x12];
2450
2451         u8         reserved_3[0x8];
2452         u8         user_index[0x18];
2453
2454         u8         reserved_4[0x8];
2455         u8         cqn[0x18];
2456
2457         u8         counter_set_id[0x8];
2458         u8         reserved_5[0x18];
2459
2460         u8         reserved_6[0x8];
2461         u8         rmpn[0x18];
2462
2463         u8         reserved_7[0xe0];
2464
2465         struct mlx5_ifc_wq_bits wq;
2466 };
2467
2468 enum {
2469         MLX5_RMPC_STATE_RDY  = 0x1,
2470         MLX5_RMPC_STATE_ERR  = 0x3,
2471 };
2472
2473 struct mlx5_ifc_rmpc_bits {
2474         u8         reserved_0[0x8];
2475         u8         state[0x4];
2476         u8         reserved_1[0x14];
2477
2478         u8         basic_cyclic_rcv_wqe[0x1];
2479         u8         reserved_2[0x1f];
2480
2481         u8         reserved_3[0x140];
2482
2483         struct mlx5_ifc_wq_bits wq;
2484 };
2485
2486 enum {
2487         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2488         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2489         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2490 };
2491
2492 struct mlx5_ifc_nic_vport_context_bits {
2493         u8         reserved_0[0x5];
2494         u8         min_wqe_inline_mode[0x3];
2495         u8         reserved_1[0x15];
2496         u8         disable_mc_local_lb[0x1];
2497         u8         disable_uc_local_lb[0x1];
2498         u8         roce_en[0x1];
2499
2500         u8         arm_change_event[0x1];
2501         u8         reserved_2[0x1a];
2502         u8         event_on_mtu[0x1];
2503         u8         event_on_promisc_change[0x1];
2504         u8         event_on_vlan_change[0x1];
2505         u8         event_on_mc_address_change[0x1];
2506         u8         event_on_uc_address_change[0x1];
2507
2508         u8         reserved_3[0xe0];
2509
2510         u8         reserved_4[0x10];
2511         u8         mtu[0x10];
2512
2513         u8         system_image_guid[0x40];
2514
2515         u8         port_guid[0x40];
2516
2517         u8         node_guid[0x40];
2518
2519         u8         reserved_5[0x140];
2520
2521         u8         qkey_violation_counter[0x10];
2522         u8         reserved_6[0x10];
2523
2524         u8         reserved_7[0x420];
2525
2526         u8         promisc_uc[0x1];
2527         u8         promisc_mc[0x1];
2528         u8         promisc_all[0x1];
2529         u8         reserved_8[0x2];
2530         u8         allowed_list_type[0x3];
2531         u8         reserved_9[0xc];
2532         u8         allowed_list_size[0xc];
2533
2534         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2535
2536         u8         reserved_10[0x20];
2537
2538         u8         current_uc_mac_address[0][0x40];
2539 };
2540
2541 enum {
2542         MLX5_ACCESS_MODE_PA        = 0x0,
2543         MLX5_ACCESS_MODE_MTT       = 0x1,
2544         MLX5_ACCESS_MODE_KLM       = 0x2,
2545 };
2546
2547 struct mlx5_ifc_mkc_bits {
2548         u8         reserved_at_0[0x1];
2549         u8         free[0x1];
2550         u8         reserved_at_2[0x1];
2551         u8         access_mode_4_2[0x3];
2552         u8         reserved_at_6[0x7];
2553         u8         relaxed_ordering_write[0x1];
2554         u8         reserved_at_e[0x1];
2555         u8         small_fence_on_rdma_read_response[0x1];
2556         u8         umr_en[0x1];
2557         u8         a[0x1];
2558         u8         rw[0x1];
2559         u8         rr[0x1];
2560         u8         lw[0x1];
2561         u8         lr[0x1];
2562         u8         access_mode[0x2];
2563         u8         reserved_2[0x8];
2564
2565         u8         qpn[0x18];
2566         u8         mkey_7_0[0x8];
2567
2568         u8         reserved_3[0x20];
2569
2570         u8         length64[0x1];
2571         u8         bsf_en[0x1];
2572         u8         sync_umr[0x1];
2573         u8         reserved_4[0x2];
2574         u8         expected_sigerr_count[0x1];
2575         u8         reserved_5[0x1];
2576         u8         en_rinval[0x1];
2577         u8         pd[0x18];
2578
2579         u8         start_addr[0x40];
2580
2581         u8         len[0x40];
2582
2583         u8         bsf_octword_size[0x20];
2584
2585         u8         reserved_6[0x80];
2586
2587         u8         translations_octword_size[0x20];
2588
2589         u8         reserved_7[0x1b];
2590         u8         log_page_size[0x5];
2591
2592         u8         reserved_8[0x20];
2593 };
2594
2595 struct mlx5_ifc_pkey_bits {
2596         u8         reserved_0[0x10];
2597         u8         pkey[0x10];
2598 };
2599
2600 struct mlx5_ifc_array128_auto_bits {
2601         u8         array128_auto[16][0x8];
2602 };
2603
2604 enum {
2605         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2606         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2607         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2608 };
2609
2610 enum {
2611         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2612         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2613         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2614         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2615         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2616         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2617         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2618 };
2619
2620 enum {
2621         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2622         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2623         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2624 };
2625
2626 enum {
2627         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2628         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2629         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2630         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2631 };
2632
2633 enum {
2634         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2635         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2636         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2637         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2638 };
2639
2640 struct mlx5_ifc_hca_vport_context_bits {
2641         u8         field_select[0x20];
2642
2643         u8         reserved_0[0xe0];
2644
2645         u8         sm_virt_aware[0x1];
2646         u8         has_smi[0x1];
2647         u8         has_raw[0x1];
2648         u8         grh_required[0x1];
2649         u8         reserved_1[0x1];
2650         u8         min_wqe_inline_mode[0x3];
2651         u8         reserved_2[0x8];
2652         u8         port_physical_state[0x4];
2653         u8         vport_state_policy[0x4];
2654         u8         port_state[0x4];
2655         u8         vport_state[0x4];
2656
2657         u8         reserved_3[0x20];
2658
2659         u8         system_image_guid[0x40];
2660
2661         u8         port_guid[0x40];
2662
2663         u8         node_guid[0x40];
2664
2665         u8         cap_mask1[0x20];
2666
2667         u8         cap_mask1_field_select[0x20];
2668
2669         u8         cap_mask2[0x20];
2670
2671         u8         cap_mask2_field_select[0x20];
2672
2673         u8         reserved_4[0x80];
2674
2675         u8         lid[0x10];
2676         u8         reserved_5[0x4];
2677         u8         init_type_reply[0x4];
2678         u8         lmc[0x3];
2679         u8         subnet_timeout[0x5];
2680
2681         u8         sm_lid[0x10];
2682         u8         sm_sl[0x4];
2683         u8         reserved_6[0xc];
2684
2685         u8         qkey_violation_counter[0x10];
2686         u8         pkey_violation_counter[0x10];
2687
2688         u8         reserved_7[0xca0];
2689 };
2690
2691 union mlx5_ifc_hca_cap_union_bits {
2692         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2693         struct mlx5_ifc_odp_cap_bits odp_cap;
2694         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2695         struct mlx5_ifc_roce_cap_bits roce_cap;
2696         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2697         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2698         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2699         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2700         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2701         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2702         struct mlx5_ifc_qos_cap_bits qos_cap;
2703         u8         reserved_0[0x8000];
2704 };
2705
2706 enum {
2707         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2708         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2709 };
2710
2711 struct mlx5_ifc_flow_table_context_bits {
2712         u8         encap_en[0x1];
2713         u8         decap_en[0x1];
2714         u8         reserved_at_2[0x2];
2715         u8         table_miss_action[0x4];
2716         u8         level[0x8];
2717         u8         reserved_at_10[0x8];
2718         u8         log_size[0x8];
2719
2720         u8         reserved_at_20[0x8];
2721         u8         table_miss_id[0x18];
2722
2723         u8         reserved_at_40[0x8];
2724         u8         lag_master_next_table_id[0x18];
2725
2726         u8         reserved_at_60[0xe0];
2727 };
2728
2729 struct mlx5_ifc_esw_vport_context_bits {
2730         u8         reserved_0[0x3];
2731         u8         vport_svlan_strip[0x1];
2732         u8         vport_cvlan_strip[0x1];
2733         u8         vport_svlan_insert[0x1];
2734         u8         vport_cvlan_insert[0x2];
2735         u8         reserved_1[0x18];
2736
2737         u8         reserved_2[0x20];
2738
2739         u8         svlan_cfi[0x1];
2740         u8         svlan_pcp[0x3];
2741         u8         svlan_id[0xc];
2742         u8         cvlan_cfi[0x1];
2743         u8         cvlan_pcp[0x3];
2744         u8         cvlan_id[0xc];
2745
2746         u8         reserved_3[0x7a0];
2747 };
2748
2749 enum {
2750         MLX5_EQC_STATUS_OK                = 0x0,
2751         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2752 };
2753
2754 enum {
2755         MLX5_EQ_STATE_ARMED = 0x9,
2756         MLX5_EQ_STATE_FIRED = 0xa,
2757 };
2758
2759 struct mlx5_ifc_eqc_bits {
2760         u8         status[0x4];
2761         u8         reserved_0[0x9];
2762         u8         ec[0x1];
2763         u8         oi[0x1];
2764         u8         reserved_1[0x5];
2765         u8         st[0x4];
2766         u8         reserved_2[0x8];
2767
2768         u8         reserved_3[0x20];
2769
2770         u8         reserved_4[0x14];
2771         u8         page_offset[0x6];
2772         u8         reserved_5[0x6];
2773
2774         u8         reserved_6[0x3];
2775         u8         log_eq_size[0x5];
2776         u8         uar_page[0x18];
2777
2778         u8         reserved_7[0x20];
2779
2780         u8         reserved_8[0x18];
2781         u8         intr[0x8];
2782
2783         u8         reserved_9[0x3];
2784         u8         log_page_size[0x5];
2785         u8         reserved_10[0x18];
2786
2787         u8         reserved_11[0x60];
2788
2789         u8         reserved_12[0x8];
2790         u8         consumer_counter[0x18];
2791
2792         u8         reserved_13[0x8];
2793         u8         producer_counter[0x18];
2794
2795         u8         reserved_14[0x80];
2796 };
2797
2798 enum {
2799         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2800         MLX5_DCTC_STATE_DRAINING  = 0x1,
2801         MLX5_DCTC_STATE_DRAINED   = 0x2,
2802 };
2803
2804 enum {
2805         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2806         MLX5_DCTC_CS_RES_NA         = 0x1,
2807         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2808 };
2809
2810 enum {
2811         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2812         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2813         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2814         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2815         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2816 };
2817
2818 struct mlx5_ifc_dctc_bits {
2819         u8         reserved_0[0x4];
2820         u8         state[0x4];
2821         u8         reserved_1[0x18];
2822
2823         u8         reserved_2[0x8];
2824         u8         user_index[0x18];
2825
2826         u8         reserved_3[0x8];
2827         u8         cqn[0x18];
2828
2829         u8         counter_set_id[0x8];
2830         u8         atomic_mode[0x4];
2831         u8         rre[0x1];
2832         u8         rwe[0x1];
2833         u8         rae[0x1];
2834         u8         atomic_like_write_en[0x1];
2835         u8         latency_sensitive[0x1];
2836         u8         rlky[0x1];
2837         u8         reserved_4[0xe];
2838
2839         u8         reserved_5[0x8];
2840         u8         cs_res[0x8];
2841         u8         reserved_6[0x3];
2842         u8         min_rnr_nak[0x5];
2843         u8         reserved_7[0x8];
2844
2845         u8         reserved_8[0x8];
2846         u8         srqn[0x18];
2847
2848         u8         reserved_9[0x8];
2849         u8         pd[0x18];
2850
2851         u8         tclass[0x8];
2852         u8         reserved_10[0x4];
2853         u8         flow_label[0x14];
2854
2855         u8         dc_access_key[0x40];
2856
2857         u8         reserved_11[0x5];
2858         u8         mtu[0x3];
2859         u8         port[0x8];
2860         u8         pkey_index[0x10];
2861
2862         u8         reserved_12[0x8];
2863         u8         my_addr_index[0x8];
2864         u8         reserved_13[0x8];
2865         u8         hop_limit[0x8];
2866
2867         u8         dc_access_key_violation_count[0x20];
2868
2869         u8         reserved_14[0x14];
2870         u8         dei_cfi[0x1];
2871         u8         eth_prio[0x3];
2872         u8         ecn[0x2];
2873         u8         dscp[0x6];
2874
2875         u8         reserved_15[0x40];
2876 };
2877
2878 enum {
2879         MLX5_CQC_STATUS_OK             = 0x0,
2880         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2881         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2882 };
2883
2884 enum {
2885         CQE_SIZE_64                = 0x0,
2886         CQE_SIZE_128               = 0x1,
2887 };
2888
2889 enum {
2890         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2891         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2892 };
2893
2894 enum {
2895         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2896         MLX5_CQ_STATE_ARMED                               = 0x9,
2897         MLX5_CQ_STATE_FIRED                               = 0xa,
2898 };
2899
2900 struct mlx5_ifc_cqc_bits {
2901         u8         status[0x4];
2902         u8         reserved_0[0x4];
2903         u8         cqe_sz[0x3];
2904         u8         cc[0x1];
2905         u8         reserved_1[0x1];
2906         u8         scqe_break_moderation_en[0x1];
2907         u8         oi[0x1];
2908         u8         cq_period_mode[0x2];
2909         u8         cqe_compression_en[0x1];
2910         u8         mini_cqe_res_format[0x2];
2911         u8         st[0x4];
2912         u8         reserved_2[0x8];
2913
2914         u8         reserved_3[0x20];
2915
2916         u8         reserved_4[0x14];
2917         u8         page_offset[0x6];
2918         u8         reserved_5[0x6];
2919
2920         u8         reserved_6[0x3];
2921         u8         log_cq_size[0x5];
2922         u8         uar_page[0x18];
2923
2924         u8         reserved_7[0x4];
2925         u8         cq_period[0xc];
2926         u8         cq_max_count[0x10];
2927
2928         u8         reserved_8[0x18];
2929         u8         c_eqn[0x8];
2930
2931         u8         reserved_9[0x3];
2932         u8         log_page_size[0x5];
2933         u8         reserved_10[0x18];
2934
2935         u8         reserved_11[0x20];
2936
2937         u8         reserved_12[0x8];
2938         u8         last_notified_index[0x18];
2939
2940         u8         reserved_13[0x8];
2941         u8         last_solicit_index[0x18];
2942
2943         u8         reserved_14[0x8];
2944         u8         consumer_counter[0x18];
2945
2946         u8         reserved_15[0x8];
2947         u8         producer_counter[0x18];
2948
2949         u8         reserved_16[0x40];
2950
2951         u8         dbr_addr[0x40];
2952 };
2953
2954 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2955         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2956         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2957         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2958         u8         reserved_0[0x800];
2959 };
2960
2961 struct mlx5_ifc_query_adapter_param_block_bits {
2962         u8         reserved_0[0xc0];
2963
2964         u8         reserved_1[0x8];
2965         u8         ieee_vendor_id[0x18];
2966
2967         u8         reserved_2[0x10];
2968         u8         vsd_vendor_id[0x10];
2969
2970         u8         vsd[208][0x8];
2971
2972         u8         vsd_contd_psid[16][0x8];
2973 };
2974
2975 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2976         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2977         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2978         u8         reserved_0[0x20];
2979 };
2980
2981 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2982         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2983         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2984         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2985         u8         reserved_0[0x20];
2986 };
2987
2988 struct mlx5_ifc_bufferx_reg_bits {
2989         u8         reserved_0[0x6];
2990         u8         lossy[0x1];
2991         u8         epsb[0x1];
2992         u8         reserved_1[0xc];
2993         u8         size[0xc];
2994
2995         u8         xoff_threshold[0x10];
2996         u8         xon_threshold[0x10];
2997 };
2998
2999 struct mlx5_ifc_config_item_bits {
3000         u8         valid[0x2];
3001         u8         reserved_0[0x2];
3002         u8         header_type[0x2];
3003         u8         reserved_1[0x2];
3004         u8         default_location[0x1];
3005         u8         reserved_2[0x7];
3006         u8         version[0x4];
3007         u8         reserved_3[0x3];
3008         u8         length[0x9];
3009
3010         u8         type[0x20];
3011
3012         u8         reserved_4[0x10];
3013         u8         crc16[0x10];
3014 };
3015
3016 struct mlx5_ifc_nodnic_port_config_reg_bits {
3017         struct mlx5_ifc_nodnic_event_word_bits event;
3018
3019         u8         network_en[0x1];
3020         u8         dma_en[0x1];
3021         u8         promisc_en[0x1];
3022         u8         promisc_multicast_en[0x1];
3023         u8         reserved_0[0x17];
3024         u8         receive_filter_en[0x5];
3025
3026         u8         reserved_1[0x10];
3027         u8         mac_47_32[0x10];
3028
3029         u8         mac_31_0[0x20];
3030
3031         u8         receive_filters_mgid_mac[64][0x8];
3032
3033         u8         gid[16][0x8];
3034
3035         u8         reserved_2[0x10];
3036         u8         lid[0x10];
3037
3038         u8         reserved_3[0xc];
3039         u8         sm_sl[0x4];
3040         u8         sm_lid[0x10];
3041
3042         u8         completion_address_63_32[0x20];
3043
3044         u8         completion_address_31_12[0x14];
3045         u8         reserved_4[0x6];
3046         u8         log_cq_size[0x6];
3047
3048         u8         working_buffer_address_63_32[0x20];
3049
3050         u8         working_buffer_address_31_12[0x14];
3051         u8         reserved_5[0xc];
3052
3053         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3054
3055         u8         pkey_index[0x10];
3056         u8         pkey[0x10];
3057
3058         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3059
3060         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3061
3062         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3063
3064         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3065
3066         u8         reserved_6[0x400];
3067 };
3068
3069 union mlx5_ifc_event_auto_bits {
3070         struct mlx5_ifc_comp_event_bits comp_event;
3071         struct mlx5_ifc_dct_events_bits dct_events;
3072         struct mlx5_ifc_qp_events_bits qp_events;
3073         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3074         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3075         struct mlx5_ifc_cq_error_bits cq_error;
3076         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3077         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3078         struct mlx5_ifc_gpio_event_bits gpio_event;
3079         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3080         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3081         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3082         struct mlx5_ifc_pages_req_event_bits pages_req_event;
3083         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3084         u8         reserved_0[0xe0];
3085 };
3086
3087 struct mlx5_ifc_health_buffer_bits {
3088         u8         reserved_0[0x100];
3089
3090         u8         assert_existptr[0x20];
3091
3092         u8         assert_callra[0x20];
3093
3094         u8         reserved_1[0x40];
3095
3096         u8         fw_version[0x20];
3097
3098         u8         hw_id[0x20];
3099
3100         u8         reserved_2[0x20];
3101
3102         u8         irisc_index[0x8];
3103         u8         synd[0x8];
3104         u8         ext_synd[0x10];
3105 };
3106
3107 struct mlx5_ifc_register_loopback_control_bits {
3108         u8         no_lb[0x1];
3109         u8         reserved_0[0x7];
3110         u8         port[0x8];
3111         u8         reserved_1[0x10];
3112
3113         u8         reserved_2[0x60];
3114 };
3115
3116 struct mlx5_ifc_lrh_bits {
3117         u8      vl[4];
3118         u8      lver[4];
3119         u8      sl[4];
3120         u8      reserved2[2];
3121         u8      lnh[2];
3122         u8      dlid[16];
3123         u8      reserved5[5];
3124         u8      pkt_len[11];
3125         u8      slid[16];
3126 };
3127
3128 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3129         u8         reserved_0[0x40];
3130
3131         u8         reserved_1[0x10];
3132         u8         rol_mode[0x8];
3133         u8         wol_mode[0x8];
3134 };
3135
3136 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3137         u8         reserved_0[0x40];
3138
3139         u8         rol_mode_valid[0x1];
3140         u8         wol_mode_valid[0x1];
3141         u8         reserved_1[0xe];
3142         u8         rol_mode[0x8];
3143         u8         wol_mode[0x8];
3144
3145         u8         reserved_2[0x7a0];
3146 };
3147
3148 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3149         u8         virtual_mac_en[0x1];
3150         u8         mac_aux_v[0x1];
3151         u8         reserved_0[0x1e];
3152
3153         u8         reserved_1[0x40];
3154
3155         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3156
3157         u8         reserved_2[0x760];
3158 };
3159
3160 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3161         u8         virtual_mac_en[0x1];
3162         u8         mac_aux_v[0x1];
3163         u8         reserved_0[0x1e];
3164
3165         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3166
3167         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3168
3169         u8         reserved_1[0x760];
3170 };
3171
3172 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3173         struct mlx5_ifc_fw_version_bits fw_version;
3174
3175         u8         reserved_0[0x10];
3176         u8         hash_signature[0x10];
3177
3178         u8         psid[16][0x8];
3179
3180         u8         reserved_1[0x6e0];
3181 };
3182
3183 struct mlx5_ifc_icmd_query_cap_in_bits {
3184         u8         reserved_0[0x10];
3185         u8         capability_group[0x10];
3186 };
3187
3188 struct mlx5_ifc_icmd_query_cap_general_bits {
3189         u8         nv_access[0x1];
3190         u8         fw_info_psid[0x1];
3191         u8         reserved_0[0x1e];
3192
3193         u8         reserved_1[0x16];
3194         u8         rol_s[0x1];
3195         u8         rol_g[0x1];
3196         u8         reserved_2[0x1];
3197         u8         wol_s[0x1];
3198         u8         wol_g[0x1];
3199         u8         wol_a[0x1];
3200         u8         wol_b[0x1];
3201         u8         wol_m[0x1];
3202         u8         wol_u[0x1];
3203         u8         wol_p[0x1];
3204 };
3205
3206 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3207         u8         status[0x8];
3208         u8         reserved_0[0x18];
3209
3210         u8         reserved_1[0x7e0];
3211 };
3212
3213 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3214         u8         status[0x8];
3215         u8         reserved_0[0x18];
3216
3217         u8         reserved_1[0x7e0];
3218 };
3219
3220 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3221         u8         address_hi[0x20];
3222
3223         u8         address_lo[0x20];
3224
3225         u8         reserved_0[0x7c0];
3226 };
3227
3228 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3229         u8         reserved_0[0x20];
3230
3231         u8         address_hi[0x20];
3232
3233         u8         address_lo[0x20];
3234
3235         u8         reserved_1[0x7a0];
3236 };
3237
3238 struct mlx5_ifc_icmd_access_reg_out_bits {
3239         u8         reserved_0[0x11];
3240         u8         status[0x7];
3241         u8         reserved_1[0x8];
3242
3243         u8         register_id[0x10];
3244         u8         reserved_2[0x10];
3245
3246         u8         reserved_3[0x40];
3247
3248         u8         reserved_4[0x5];
3249         u8         len[0xb];
3250         u8         reserved_5[0x10];
3251
3252         u8         register_data[0][0x20];
3253 };
3254
3255 enum {
3256         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3257         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3258 };
3259
3260 struct mlx5_ifc_icmd_access_reg_in_bits {
3261         u8         constant_1[0x5];
3262         u8         constant_2[0xb];
3263         u8         reserved_0[0x10];
3264
3265         u8         register_id[0x10];
3266         u8         reserved_1[0x1];
3267         u8         method[0x7];
3268         u8         constant_3[0x8];
3269
3270         u8         reserved_2[0x40];
3271
3272         u8         constant_4[0x5];
3273         u8         len[0xb];
3274         u8         reserved_3[0x10];
3275
3276         u8         register_data[0][0x20];
3277 };
3278
3279 enum {
3280         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3281         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3282 };
3283
3284 struct mlx5_ifc_teardown_hca_out_bits {
3285         u8         status[0x8];
3286         u8         reserved_0[0x18];
3287
3288         u8         syndrome[0x20];
3289
3290         u8         reserved_1[0x3f];
3291
3292         u8         force_state[0x1];
3293 };
3294
3295 enum {
3296         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3297         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3298 };
3299
3300 struct mlx5_ifc_teardown_hca_in_bits {
3301         u8         opcode[0x10];
3302         u8         reserved_0[0x10];
3303
3304         u8         reserved_1[0x10];
3305         u8         op_mod[0x10];
3306
3307         u8         reserved_2[0x10];
3308         u8         profile[0x10];
3309
3310         u8         reserved_3[0x20];
3311 };
3312
3313 struct mlx5_ifc_set_delay_drop_params_out_bits {
3314         u8         status[0x8];
3315         u8         reserved_at_8[0x18];
3316
3317         u8         syndrome[0x20];
3318
3319         u8         reserved_at_40[0x40];
3320 };
3321
3322 struct mlx5_ifc_set_delay_drop_params_in_bits {
3323         u8         opcode[0x10];
3324         u8         reserved_at_10[0x10];
3325
3326         u8         reserved_at_20[0x10];
3327         u8         op_mod[0x10];
3328
3329         u8         reserved_at_40[0x20];
3330
3331         u8         reserved_at_60[0x10];
3332         u8         delay_drop_timeout[0x10];
3333 };
3334
3335 struct mlx5_ifc_query_delay_drop_params_out_bits {
3336         u8         status[0x8];
3337         u8         reserved_at_8[0x18];
3338
3339         u8         syndrome[0x20];
3340
3341         u8         reserved_at_40[0x20];
3342
3343         u8         reserved_at_60[0x10];
3344         u8         delay_drop_timeout[0x10];
3345 };
3346
3347 struct mlx5_ifc_query_delay_drop_params_in_bits {
3348         u8         opcode[0x10];
3349         u8         reserved_at_10[0x10];
3350
3351         u8         reserved_at_20[0x10];
3352         u8         op_mod[0x10];
3353
3354         u8         reserved_at_40[0x40];
3355 };
3356
3357 struct mlx5_ifc_suspend_qp_out_bits {
3358         u8         status[0x8];
3359         u8         reserved_0[0x18];
3360
3361         u8         syndrome[0x20];
3362
3363         u8         reserved_1[0x40];
3364 };
3365
3366 struct mlx5_ifc_suspend_qp_in_bits {
3367         u8         opcode[0x10];
3368         u8         reserved_0[0x10];
3369
3370         u8         reserved_1[0x10];
3371         u8         op_mod[0x10];
3372
3373         u8         reserved_2[0x8];
3374         u8         qpn[0x18];
3375
3376         u8         reserved_3[0x20];
3377 };
3378
3379 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3380         u8         status[0x8];
3381         u8         reserved_0[0x18];
3382
3383         u8         syndrome[0x20];
3384
3385         u8         reserved_1[0x40];
3386 };
3387
3388 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3389         u8         opcode[0x10];
3390         u8         reserved_0[0x10];
3391
3392         u8         reserved_1[0x10];
3393         u8         op_mod[0x10];
3394
3395         u8         reserved_2[0x8];
3396         u8         qpn[0x18];
3397
3398         u8         reserved_3[0x20];
3399
3400         u8         opt_param_mask[0x20];
3401
3402         u8         reserved_4[0x20];
3403
3404         struct mlx5_ifc_qpc_bits qpc;
3405
3406         u8         reserved_5[0x80];
3407 };
3408
3409 struct mlx5_ifc_sqd2rts_qp_out_bits {
3410         u8         status[0x8];
3411         u8         reserved_0[0x18];
3412
3413         u8         syndrome[0x20];
3414
3415         u8         reserved_1[0x40];
3416 };
3417
3418 struct mlx5_ifc_sqd2rts_qp_in_bits {
3419         u8         opcode[0x10];
3420         u8         reserved_0[0x10];
3421
3422         u8         reserved_1[0x10];
3423         u8         op_mod[0x10];
3424
3425         u8         reserved_2[0x8];
3426         u8         qpn[0x18];
3427
3428         u8         reserved_3[0x20];
3429
3430         u8         opt_param_mask[0x20];
3431
3432         u8         reserved_4[0x20];
3433
3434         struct mlx5_ifc_qpc_bits qpc;
3435
3436         u8         reserved_5[0x80];
3437 };
3438
3439 struct mlx5_ifc_set_wol_rol_out_bits {
3440         u8         status[0x8];
3441         u8         reserved_0[0x18];
3442
3443         u8         syndrome[0x20];
3444
3445         u8         reserved_1[0x40];
3446 };
3447
3448 struct mlx5_ifc_set_wol_rol_in_bits {
3449         u8         opcode[0x10];
3450         u8         reserved_0[0x10];
3451
3452         u8         reserved_1[0x10];
3453         u8         op_mod[0x10];
3454
3455         u8         rol_mode_valid[0x1];
3456         u8         wol_mode_valid[0x1];
3457         u8         reserved_2[0xe];
3458         u8         rol_mode[0x8];
3459         u8         wol_mode[0x8];
3460
3461         u8         reserved_3[0x20];
3462 };
3463
3464 struct mlx5_ifc_set_roce_address_out_bits {
3465         u8         status[0x8];
3466         u8         reserved_0[0x18];
3467
3468         u8         syndrome[0x20];
3469
3470         u8         reserved_1[0x40];
3471 };
3472
3473 struct mlx5_ifc_set_roce_address_in_bits {
3474         u8         opcode[0x10];
3475         u8         reserved_0[0x10];
3476
3477         u8         reserved_1[0x10];
3478         u8         op_mod[0x10];
3479
3480         u8         roce_address_index[0x10];
3481         u8         reserved_2[0x10];
3482
3483         u8         reserved_3[0x20];
3484
3485         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3486 };
3487
3488 struct mlx5_ifc_set_rdb_out_bits {
3489         u8         status[0x8];
3490         u8         reserved_0[0x18];
3491
3492         u8         syndrome[0x20];
3493
3494         u8         reserved_1[0x40];
3495 };
3496
3497 struct mlx5_ifc_set_rdb_in_bits {
3498         u8         opcode[0x10];
3499         u8         reserved_0[0x10];
3500
3501         u8         reserved_1[0x10];
3502         u8         op_mod[0x10];
3503
3504         u8         reserved_2[0x8];
3505         u8         qpn[0x18];
3506
3507         u8         reserved_3[0x18];
3508         u8         rdb_list_size[0x8];
3509
3510         struct mlx5_ifc_rdbc_bits rdb_context[0];
3511 };
3512
3513 struct mlx5_ifc_set_mad_demux_out_bits {
3514         u8         status[0x8];
3515         u8         reserved_0[0x18];
3516
3517         u8         syndrome[0x20];
3518
3519         u8         reserved_1[0x40];
3520 };
3521
3522 enum {
3523         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3524         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3525 };
3526
3527 struct mlx5_ifc_set_mad_demux_in_bits {
3528         u8         opcode[0x10];
3529         u8         reserved_0[0x10];
3530
3531         u8         reserved_1[0x10];
3532         u8         op_mod[0x10];
3533
3534         u8         reserved_2[0x20];
3535
3536         u8         reserved_3[0x6];
3537         u8         demux_mode[0x2];
3538         u8         reserved_4[0x18];
3539 };
3540
3541 struct mlx5_ifc_set_l2_table_entry_out_bits {
3542         u8         status[0x8];
3543         u8         reserved_0[0x18];
3544
3545         u8         syndrome[0x20];
3546
3547         u8         reserved_1[0x40];
3548 };
3549
3550 struct mlx5_ifc_set_l2_table_entry_in_bits {
3551         u8         opcode[0x10];
3552         u8         reserved_0[0x10];
3553
3554         u8         reserved_1[0x10];
3555         u8         op_mod[0x10];
3556
3557         u8         reserved_2[0x60];
3558
3559         u8         reserved_3[0x8];
3560         u8         table_index[0x18];
3561
3562         u8         reserved_4[0x20];
3563
3564         u8         reserved_5[0x13];
3565         u8         vlan_valid[0x1];
3566         u8         vlan[0xc];
3567
3568         struct mlx5_ifc_mac_address_layout_bits mac_address;
3569
3570         u8         reserved_6[0xc0];
3571 };
3572
3573 struct mlx5_ifc_set_issi_out_bits {
3574         u8         status[0x8];
3575         u8         reserved_0[0x18];
3576
3577         u8         syndrome[0x20];
3578
3579         u8         reserved_1[0x40];
3580 };
3581
3582 struct mlx5_ifc_set_issi_in_bits {
3583         u8         opcode[0x10];
3584         u8         reserved_0[0x10];
3585
3586         u8         reserved_1[0x10];
3587         u8         op_mod[0x10];
3588
3589         u8         reserved_2[0x10];
3590         u8         current_issi[0x10];
3591
3592         u8         reserved_3[0x20];
3593 };
3594
3595 struct mlx5_ifc_set_hca_cap_out_bits {
3596         u8         status[0x8];
3597         u8         reserved_0[0x18];
3598
3599         u8         syndrome[0x20];
3600
3601         u8         reserved_1[0x40];
3602 };
3603
3604 struct mlx5_ifc_set_hca_cap_in_bits {
3605         u8         opcode[0x10];
3606         u8         reserved_0[0x10];
3607
3608         u8         reserved_1[0x10];
3609         u8         op_mod[0x10];
3610
3611         u8         reserved_2[0x40];
3612
3613         union mlx5_ifc_hca_cap_union_bits capability;
3614 };
3615
3616 enum {
3617         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3618         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3619         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3620         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3621 };
3622
3623 struct mlx5_ifc_set_flow_table_root_out_bits {
3624         u8         status[0x8];
3625         u8         reserved_0[0x18];
3626
3627         u8         syndrome[0x20];
3628
3629         u8         reserved_1[0x40];
3630 };
3631
3632 struct mlx5_ifc_set_flow_table_root_in_bits {
3633         u8         opcode[0x10];
3634         u8         reserved_0[0x10];
3635
3636         u8         reserved_1[0x10];
3637         u8         op_mod[0x10];
3638
3639         u8         other_vport[0x1];
3640         u8         reserved_2[0xf];
3641         u8         vport_number[0x10];
3642
3643         u8         reserved_3[0x20];
3644
3645         u8         table_type[0x8];
3646         u8         reserved_4[0x18];
3647
3648         u8         reserved_5[0x8];
3649         u8         table_id[0x18];
3650
3651         u8         reserved_6[0x8];
3652         u8         underlay_qpn[0x18];
3653
3654         u8         reserved_7[0x120];
3655 };
3656
3657 struct mlx5_ifc_set_fte_out_bits {
3658         u8         status[0x8];
3659         u8         reserved_0[0x18];
3660
3661         u8         syndrome[0x20];
3662
3663         u8         reserved_1[0x40];
3664 };
3665
3666 struct mlx5_ifc_set_fte_in_bits {
3667         u8         opcode[0x10];
3668         u8         reserved_0[0x10];
3669
3670         u8         reserved_1[0x10];
3671         u8         op_mod[0x10];
3672
3673         u8         other_vport[0x1];
3674         u8         reserved_2[0xf];
3675         u8         vport_number[0x10];
3676
3677         u8         reserved_3[0x20];
3678
3679         u8         table_type[0x8];
3680         u8         reserved_4[0x18];
3681
3682         u8         reserved_5[0x8];
3683         u8         table_id[0x18];
3684
3685         u8         reserved_6[0x18];
3686         u8         modify_enable_mask[0x8];
3687
3688         u8         reserved_7[0x20];
3689
3690         u8         flow_index[0x20];
3691
3692         u8         reserved_8[0xe0];
3693
3694         struct mlx5_ifc_flow_context_bits flow_context;
3695 };
3696
3697 struct mlx5_ifc_set_driver_version_out_bits {
3698         u8         status[0x8];
3699         u8         reserved_0[0x18];
3700
3701         u8         syndrome[0x20];
3702
3703         u8         reserved_1[0x40];
3704 };
3705
3706 struct mlx5_ifc_set_driver_version_in_bits {
3707         u8         opcode[0x10];
3708         u8         reserved_0[0x10];
3709
3710         u8         reserved_1[0x10];
3711         u8         op_mod[0x10];
3712
3713         u8         reserved_2[0x40];
3714
3715         u8         driver_version[64][0x8];
3716 };
3717
3718 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3719         u8         status[0x8];
3720         u8         reserved_0[0x18];
3721
3722         u8         syndrome[0x20];
3723
3724         u8         reserved_1[0x40];
3725 };
3726
3727 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3728         u8         opcode[0x10];
3729         u8         reserved_0[0x10];
3730
3731         u8         reserved_1[0x10];
3732         u8         op_mod[0x10];
3733
3734         u8         enable[0x1];
3735         u8         reserved_2[0x1f];
3736
3737         u8         reserved_3[0x160];
3738
3739         struct mlx5_ifc_cmd_pas_bits pas;
3740 };
3741
3742 struct mlx5_ifc_set_burst_size_out_bits {
3743         u8         status[0x8];
3744         u8         reserved_0[0x18];
3745
3746         u8         syndrome[0x20];
3747
3748         u8         reserved_1[0x40];
3749 };
3750
3751 struct mlx5_ifc_set_burst_size_in_bits {
3752         u8         opcode[0x10];
3753         u8         reserved_0[0x10];
3754
3755         u8         reserved_1[0x10];
3756         u8         op_mod[0x10];
3757
3758         u8         reserved_2[0x20];
3759
3760         u8         reserved_3[0x9];
3761         u8         device_burst_size[0x17];
3762 };
3763
3764 struct mlx5_ifc_rts2rts_qp_out_bits {
3765         u8         status[0x8];
3766         u8         reserved_0[0x18];
3767
3768         u8         syndrome[0x20];
3769
3770         u8         reserved_1[0x40];
3771 };
3772
3773 struct mlx5_ifc_rts2rts_qp_in_bits {
3774         u8         opcode[0x10];
3775         u8         reserved_0[0x10];
3776
3777         u8         reserved_1[0x10];
3778         u8         op_mod[0x10];
3779
3780         u8         reserved_2[0x8];
3781         u8         qpn[0x18];
3782
3783         u8         reserved_3[0x20];
3784
3785         u8         opt_param_mask[0x20];
3786
3787         u8         reserved_4[0x20];
3788
3789         struct mlx5_ifc_qpc_bits qpc;
3790
3791         u8         reserved_5[0x80];
3792 };
3793
3794 struct mlx5_ifc_rtr2rts_qp_out_bits {
3795         u8         status[0x8];
3796         u8         reserved_0[0x18];
3797
3798         u8         syndrome[0x20];
3799
3800         u8         reserved_1[0x40];
3801 };
3802
3803 struct mlx5_ifc_rtr2rts_qp_in_bits {
3804         u8         opcode[0x10];
3805         u8         reserved_0[0x10];
3806
3807         u8         reserved_1[0x10];
3808         u8         op_mod[0x10];
3809
3810         u8         reserved_2[0x8];
3811         u8         qpn[0x18];
3812
3813         u8         reserved_3[0x20];
3814
3815         u8         opt_param_mask[0x20];
3816
3817         u8         reserved_4[0x20];
3818
3819         struct mlx5_ifc_qpc_bits qpc;
3820
3821         u8         reserved_5[0x80];
3822 };
3823
3824 struct mlx5_ifc_rst2init_qp_out_bits {
3825         u8         status[0x8];
3826         u8         reserved_0[0x18];
3827
3828         u8         syndrome[0x20];
3829
3830         u8         reserved_1[0x40];
3831 };
3832
3833 struct mlx5_ifc_rst2init_qp_in_bits {
3834         u8         opcode[0x10];
3835         u8         reserved_0[0x10];
3836
3837         u8         reserved_1[0x10];
3838         u8         op_mod[0x10];
3839
3840         u8         reserved_2[0x8];
3841         u8         qpn[0x18];
3842
3843         u8         reserved_3[0x20];
3844
3845         u8         opt_param_mask[0x20];
3846
3847         u8         reserved_4[0x20];
3848
3849         struct mlx5_ifc_qpc_bits qpc;
3850
3851         u8         reserved_5[0x80];
3852 };
3853
3854 struct mlx5_ifc_resume_qp_out_bits {
3855         u8         status[0x8];
3856         u8         reserved_0[0x18];
3857
3858         u8         syndrome[0x20];
3859
3860         u8         reserved_1[0x40];
3861 };
3862
3863 struct mlx5_ifc_resume_qp_in_bits {
3864         u8         opcode[0x10];
3865         u8         reserved_0[0x10];
3866
3867         u8         reserved_1[0x10];
3868         u8         op_mod[0x10];
3869
3870         u8         reserved_2[0x8];
3871         u8         qpn[0x18];
3872
3873         u8         reserved_3[0x20];
3874 };
3875
3876 struct mlx5_ifc_query_xrc_srq_out_bits {
3877         u8         status[0x8];
3878         u8         reserved_0[0x18];
3879
3880         u8         syndrome[0x20];
3881
3882         u8         reserved_1[0x40];
3883
3884         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3885
3886         u8         reserved_2[0x600];
3887
3888         u8         pas[0][0x40];
3889 };
3890
3891 struct mlx5_ifc_query_xrc_srq_in_bits {
3892         u8         opcode[0x10];
3893         u8         reserved_0[0x10];
3894
3895         u8         reserved_1[0x10];
3896         u8         op_mod[0x10];
3897
3898         u8         reserved_2[0x8];
3899         u8         xrc_srqn[0x18];
3900
3901         u8         reserved_3[0x20];
3902 };
3903
3904 struct mlx5_ifc_query_wol_rol_out_bits {
3905         u8         status[0x8];
3906         u8         reserved_0[0x18];
3907
3908         u8         syndrome[0x20];
3909
3910         u8         reserved_1[0x10];
3911         u8         rol_mode[0x8];
3912         u8         wol_mode[0x8];
3913
3914         u8         reserved_2[0x20];
3915 };
3916
3917 struct mlx5_ifc_query_wol_rol_in_bits {
3918         u8         opcode[0x10];
3919         u8         reserved_0[0x10];
3920
3921         u8         reserved_1[0x10];
3922         u8         op_mod[0x10];
3923
3924         u8         reserved_2[0x40];
3925 };
3926
3927 enum {
3928         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3929         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3930 };
3931
3932 struct mlx5_ifc_query_vport_state_out_bits {
3933         u8         status[0x8];
3934         u8         reserved_0[0x18];
3935
3936         u8         syndrome[0x20];
3937
3938         u8         reserved_1[0x20];
3939
3940         u8         reserved_2[0x18];
3941         u8         admin_state[0x4];
3942         u8         state[0x4];
3943 };
3944
3945 enum {
3946         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3947         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3948         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3949 };
3950
3951 struct mlx5_ifc_query_vport_state_in_bits {
3952         u8         opcode[0x10];
3953         u8         reserved_0[0x10];
3954
3955         u8         reserved_1[0x10];
3956         u8         op_mod[0x10];
3957
3958         u8         other_vport[0x1];
3959         u8         reserved_2[0xf];
3960         u8         vport_number[0x10];
3961
3962         u8         reserved_3[0x20];
3963 };
3964
3965 struct mlx5_ifc_query_vport_counter_out_bits {
3966         u8         status[0x8];
3967         u8         reserved_0[0x18];
3968
3969         u8         syndrome[0x20];
3970
3971         u8         reserved_1[0x40];
3972
3973         struct mlx5_ifc_traffic_counter_bits received_errors;
3974
3975         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3976
3977         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3978
3979         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3980
3981         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3982
3983         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3984
3985         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3986
3987         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3988
3989         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3990
3991         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3992
3993         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3994
3995         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3996
3997         u8         reserved_2[0xa00];
3998 };
3999
4000 enum {
4001         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4002 };
4003
4004 struct mlx5_ifc_query_vport_counter_in_bits {
4005         u8         opcode[0x10];
4006         u8         reserved_0[0x10];
4007
4008         u8         reserved_1[0x10];
4009         u8         op_mod[0x10];
4010
4011         u8         other_vport[0x1];
4012         u8         reserved_2[0xb];
4013         u8         port_num[0x4];
4014         u8         vport_number[0x10];
4015
4016         u8         reserved_3[0x60];
4017
4018         u8         clear[0x1];
4019         u8         reserved_4[0x1f];
4020
4021         u8         reserved_5[0x20];
4022 };
4023
4024 struct mlx5_ifc_query_tis_out_bits {
4025         u8         status[0x8];
4026         u8         reserved_0[0x18];
4027
4028         u8         syndrome[0x20];
4029
4030         u8         reserved_1[0x40];
4031
4032         struct mlx5_ifc_tisc_bits tis_context;
4033 };
4034
4035 struct mlx5_ifc_query_tis_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_0[0x10];
4038
4039         u8         reserved_1[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_2[0x8];
4043         u8         tisn[0x18];
4044
4045         u8         reserved_3[0x20];
4046 };
4047
4048 struct mlx5_ifc_query_tir_out_bits {
4049         u8         status[0x8];
4050         u8         reserved_0[0x18];
4051
4052         u8         syndrome[0x20];
4053
4054         u8         reserved_1[0xc0];
4055
4056         struct mlx5_ifc_tirc_bits tir_context;
4057 };
4058
4059 struct mlx5_ifc_query_tir_in_bits {
4060         u8         opcode[0x10];
4061         u8         reserved_0[0x10];
4062
4063         u8         reserved_1[0x10];
4064         u8         op_mod[0x10];
4065
4066         u8         reserved_2[0x8];
4067         u8         tirn[0x18];
4068
4069         u8         reserved_3[0x20];
4070 };
4071
4072 struct mlx5_ifc_query_srq_out_bits {
4073         u8         status[0x8];
4074         u8         reserved_0[0x18];
4075
4076         u8         syndrome[0x20];
4077
4078         u8         reserved_1[0x40];
4079
4080         struct mlx5_ifc_srqc_bits srq_context_entry;
4081
4082         u8         reserved_2[0x600];
4083
4084         u8         pas[0][0x40];
4085 };
4086
4087 struct mlx5_ifc_query_srq_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_0[0x10];
4090
4091         u8         reserved_1[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         reserved_2[0x8];
4095         u8         srqn[0x18];
4096
4097         u8         reserved_3[0x20];
4098 };
4099
4100 struct mlx5_ifc_query_sq_out_bits {
4101         u8         status[0x8];
4102         u8         reserved_0[0x18];
4103
4104         u8         syndrome[0x20];
4105
4106         u8         reserved_1[0xc0];
4107
4108         struct mlx5_ifc_sqc_bits sq_context;
4109 };
4110
4111 struct mlx5_ifc_query_sq_in_bits {
4112         u8         opcode[0x10];
4113         u8         reserved_0[0x10];
4114
4115         u8         reserved_1[0x10];
4116         u8         op_mod[0x10];
4117
4118         u8         reserved_2[0x8];
4119         u8         sqn[0x18];
4120
4121         u8         reserved_3[0x20];
4122 };
4123
4124 struct mlx5_ifc_query_special_contexts_out_bits {
4125         u8         status[0x8];
4126         u8         reserved_0[0x18];
4127
4128         u8         syndrome[0x20];
4129
4130         u8         dump_fill_mkey[0x20];
4131
4132         u8         resd_lkey[0x20];
4133 };
4134
4135 struct mlx5_ifc_query_special_contexts_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_0[0x10];
4138
4139         u8         reserved_1[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_2[0x40];
4143 };
4144
4145 struct mlx5_ifc_query_scheduling_element_out_bits {
4146         u8         status[0x8];
4147         u8         reserved_at_8[0x18];
4148
4149         u8         syndrome[0x20];
4150
4151         u8         reserved_at_40[0xc0];
4152
4153         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4154
4155         u8         reserved_at_300[0x100];
4156 };
4157
4158 enum {
4159         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4160 };
4161
4162 struct mlx5_ifc_query_scheduling_element_in_bits {
4163         u8         opcode[0x10];
4164         u8         reserved_at_10[0x10];
4165
4166         u8         reserved_at_20[0x10];
4167         u8         op_mod[0x10];
4168
4169         u8         scheduling_hierarchy[0x8];
4170         u8         reserved_at_48[0x18];
4171
4172         u8         scheduling_element_id[0x20];
4173
4174         u8         reserved_at_80[0x180];
4175 };
4176
4177 struct mlx5_ifc_query_rqt_out_bits {
4178         u8         status[0x8];
4179         u8         reserved_0[0x18];
4180
4181         u8         syndrome[0x20];
4182
4183         u8         reserved_1[0xc0];
4184
4185         struct mlx5_ifc_rqtc_bits rqt_context;
4186 };
4187
4188 struct mlx5_ifc_query_rqt_in_bits {
4189         u8         opcode[0x10];
4190         u8         reserved_0[0x10];
4191
4192         u8         reserved_1[0x10];
4193         u8         op_mod[0x10];
4194
4195         u8         reserved_2[0x8];
4196         u8         rqtn[0x18];
4197
4198         u8         reserved_3[0x20];
4199 };
4200
4201 struct mlx5_ifc_query_rq_out_bits {
4202         u8         status[0x8];
4203         u8         reserved_0[0x18];
4204
4205         u8         syndrome[0x20];
4206
4207         u8         reserved_1[0xc0];
4208
4209         struct mlx5_ifc_rqc_bits rq_context;
4210 };
4211
4212 struct mlx5_ifc_query_rq_in_bits {
4213         u8         opcode[0x10];
4214         u8         reserved_0[0x10];
4215
4216         u8         reserved_1[0x10];
4217         u8         op_mod[0x10];
4218
4219         u8         reserved_2[0x8];
4220         u8         rqn[0x18];
4221
4222         u8         reserved_3[0x20];
4223 };
4224
4225 struct mlx5_ifc_query_roce_address_out_bits {
4226         u8         status[0x8];
4227         u8         reserved_0[0x18];
4228
4229         u8         syndrome[0x20];
4230
4231         u8         reserved_1[0x40];
4232
4233         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4234 };
4235
4236 struct mlx5_ifc_query_roce_address_in_bits {
4237         u8         opcode[0x10];
4238         u8         reserved_0[0x10];
4239
4240         u8         reserved_1[0x10];
4241         u8         op_mod[0x10];
4242
4243         u8         roce_address_index[0x10];
4244         u8         reserved_2[0x10];
4245
4246         u8         reserved_3[0x20];
4247 };
4248
4249 struct mlx5_ifc_query_rmp_out_bits {
4250         u8         status[0x8];
4251         u8         reserved_0[0x18];
4252
4253         u8         syndrome[0x20];
4254
4255         u8         reserved_1[0xc0];
4256
4257         struct mlx5_ifc_rmpc_bits rmp_context;
4258 };
4259
4260 struct mlx5_ifc_query_rmp_in_bits {
4261         u8         opcode[0x10];
4262         u8         reserved_0[0x10];
4263
4264         u8         reserved_1[0x10];
4265         u8         op_mod[0x10];
4266
4267         u8         reserved_2[0x8];
4268         u8         rmpn[0x18];
4269
4270         u8         reserved_3[0x20];
4271 };
4272
4273 struct mlx5_ifc_query_rdb_out_bits {
4274         u8         status[0x8];
4275         u8         reserved_0[0x18];
4276
4277         u8         syndrome[0x20];
4278
4279         u8         reserved_1[0x20];
4280
4281         u8         reserved_2[0x18];
4282         u8         rdb_list_size[0x8];
4283
4284         struct mlx5_ifc_rdbc_bits rdb_context[0];
4285 };
4286
4287 struct mlx5_ifc_query_rdb_in_bits {
4288         u8         opcode[0x10];
4289         u8         reserved_0[0x10];
4290
4291         u8         reserved_1[0x10];
4292         u8         op_mod[0x10];
4293
4294         u8         reserved_2[0x8];
4295         u8         qpn[0x18];
4296
4297         u8         reserved_3[0x20];
4298 };
4299
4300 struct mlx5_ifc_query_qp_out_bits {
4301         u8         status[0x8];
4302         u8         reserved_0[0x18];
4303
4304         u8         syndrome[0x20];
4305
4306         u8         reserved_1[0x40];
4307
4308         u8         opt_param_mask[0x20];
4309
4310         u8         reserved_2[0x20];
4311
4312         struct mlx5_ifc_qpc_bits qpc;
4313
4314         u8         reserved_3[0x80];
4315
4316         u8         pas[0][0x40];
4317 };
4318
4319 struct mlx5_ifc_query_qp_in_bits {
4320         u8         opcode[0x10];
4321         u8         reserved_0[0x10];
4322
4323         u8         reserved_1[0x10];
4324         u8         op_mod[0x10];
4325
4326         u8         reserved_2[0x8];
4327         u8         qpn[0x18];
4328
4329         u8         reserved_3[0x20];
4330 };
4331
4332 struct mlx5_ifc_query_q_counter_out_bits {
4333         u8         status[0x8];
4334         u8         reserved_0[0x18];
4335
4336         u8         syndrome[0x20];
4337
4338         u8         reserved_1[0x40];
4339
4340         u8         rx_write_requests[0x20];
4341
4342         u8         reserved_2[0x20];
4343
4344         u8         rx_read_requests[0x20];
4345
4346         u8         reserved_3[0x20];
4347
4348         u8         rx_atomic_requests[0x20];
4349
4350         u8         reserved_4[0x20];
4351
4352         u8         rx_dct_connect[0x20];
4353
4354         u8         reserved_5[0x20];
4355
4356         u8         out_of_buffer[0x20];
4357
4358         u8         reserved_7[0x20];
4359
4360         u8         out_of_sequence[0x20];
4361
4362         u8         reserved_8[0x20];
4363
4364         u8         duplicate_request[0x20];
4365
4366         u8         reserved_9[0x20];
4367
4368         u8         rnr_nak_retry_err[0x20];
4369
4370         u8         reserved_10[0x20];
4371
4372         u8         packet_seq_err[0x20];
4373
4374         u8         reserved_11[0x20];
4375
4376         u8         implied_nak_seq_err[0x20];
4377
4378         u8         reserved_12[0x20];
4379
4380         u8         local_ack_timeout_err[0x20];
4381
4382         u8         reserved_13[0x20];
4383
4384         u8         resp_rnr_nak[0x20];
4385
4386         u8         reserved_14[0x20];
4387
4388         u8         req_rnr_retries_exceeded[0x20];
4389
4390         u8         reserved_15[0x460];
4391 };
4392
4393 struct mlx5_ifc_query_q_counter_in_bits {
4394         u8         opcode[0x10];
4395         u8         reserved_0[0x10];
4396
4397         u8         reserved_1[0x10];
4398         u8         op_mod[0x10];
4399
4400         u8         reserved_2[0x80];
4401
4402         u8         clear[0x1];
4403         u8         reserved_3[0x1f];
4404
4405         u8         reserved_4[0x18];
4406         u8         counter_set_id[0x8];
4407 };
4408
4409 struct mlx5_ifc_query_pages_out_bits {
4410         u8         status[0x8];
4411         u8         reserved_0[0x18];
4412
4413         u8         syndrome[0x20];
4414
4415         u8         reserved_1[0x10];
4416         u8         function_id[0x10];
4417
4418         u8         num_pages[0x20];
4419 };
4420
4421 enum {
4422         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4423         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4424         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4425 };
4426
4427 struct mlx5_ifc_query_pages_in_bits {
4428         u8         opcode[0x10];
4429         u8         reserved_0[0x10];
4430
4431         u8         reserved_1[0x10];
4432         u8         op_mod[0x10];
4433
4434         u8         reserved_2[0x10];
4435         u8         function_id[0x10];
4436
4437         u8         reserved_3[0x20];
4438 };
4439
4440 struct mlx5_ifc_query_nic_vport_context_out_bits {
4441         u8         status[0x8];
4442         u8         reserved_0[0x18];
4443
4444         u8         syndrome[0x20];
4445
4446         u8         reserved_1[0x40];
4447
4448         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4449 };
4450
4451 struct mlx5_ifc_query_nic_vport_context_in_bits {
4452         u8         opcode[0x10];
4453         u8         reserved_0[0x10];
4454
4455         u8         reserved_1[0x10];
4456         u8         op_mod[0x10];
4457
4458         u8         other_vport[0x1];
4459         u8         reserved_2[0xf];
4460         u8         vport_number[0x10];
4461
4462         u8         reserved_3[0x5];
4463         u8         allowed_list_type[0x3];
4464         u8         reserved_4[0x18];
4465 };
4466
4467 struct mlx5_ifc_query_mkey_out_bits {
4468         u8         status[0x8];
4469         u8         reserved_0[0x18];
4470
4471         u8         syndrome[0x20];
4472
4473         u8         reserved_1[0x40];
4474
4475         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4476
4477         u8         reserved_2[0x600];
4478
4479         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4480
4481         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4482 };
4483
4484 struct mlx5_ifc_query_mkey_in_bits {
4485         u8         opcode[0x10];
4486         u8         reserved_0[0x10];
4487
4488         u8         reserved_1[0x10];
4489         u8         op_mod[0x10];
4490
4491         u8         reserved_2[0x8];
4492         u8         mkey_index[0x18];
4493
4494         u8         pg_access[0x1];
4495         u8         reserved_3[0x1f];
4496 };
4497
4498 struct mlx5_ifc_query_mad_demux_out_bits {
4499         u8         status[0x8];
4500         u8         reserved_0[0x18];
4501
4502         u8         syndrome[0x20];
4503
4504         u8         reserved_1[0x40];
4505
4506         u8         mad_dumux_parameters_block[0x20];
4507 };
4508
4509 struct mlx5_ifc_query_mad_demux_in_bits {
4510         u8         opcode[0x10];
4511         u8         reserved_0[0x10];
4512
4513         u8         reserved_1[0x10];
4514         u8         op_mod[0x10];
4515
4516         u8         reserved_2[0x40];
4517 };
4518
4519 struct mlx5_ifc_query_l2_table_entry_out_bits {
4520         u8         status[0x8];
4521         u8         reserved_0[0x18];
4522
4523         u8         syndrome[0x20];
4524
4525         u8         reserved_1[0xa0];
4526
4527         u8         reserved_2[0x13];
4528         u8         vlan_valid[0x1];
4529         u8         vlan[0xc];
4530
4531         struct mlx5_ifc_mac_address_layout_bits mac_address;
4532
4533         u8         reserved_3[0xc0];
4534 };
4535
4536 struct mlx5_ifc_query_l2_table_entry_in_bits {
4537         u8         opcode[0x10];
4538         u8         reserved_0[0x10];
4539
4540         u8         reserved_1[0x10];
4541         u8         op_mod[0x10];
4542
4543         u8         reserved_2[0x60];
4544
4545         u8         reserved_3[0x8];
4546         u8         table_index[0x18];
4547
4548         u8         reserved_4[0x140];
4549 };
4550
4551 struct mlx5_ifc_query_issi_out_bits {
4552         u8         status[0x8];
4553         u8         reserved_0[0x18];
4554
4555         u8         syndrome[0x20];
4556
4557         u8         reserved_1[0x10];
4558         u8         current_issi[0x10];
4559
4560         u8         reserved_2[0xa0];
4561
4562         u8         supported_issi_reserved[76][0x8];
4563         u8         supported_issi_dw0[0x20];
4564 };
4565
4566 struct mlx5_ifc_query_issi_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_0[0x10];
4569
4570         u8         reserved_1[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         reserved_2[0x40];
4574 };
4575
4576 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4577         u8         status[0x8];
4578         u8         reserved_0[0x18];
4579
4580         u8         syndrome[0x20];
4581
4582         u8         reserved_1[0x40];
4583
4584         struct mlx5_ifc_pkey_bits pkey[0];
4585 };
4586
4587 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4588         u8         opcode[0x10];
4589         u8         reserved_0[0x10];
4590
4591         u8         reserved_1[0x10];
4592         u8         op_mod[0x10];
4593
4594         u8         other_vport[0x1];
4595         u8         reserved_2[0xb];
4596         u8         port_num[0x4];
4597         u8         vport_number[0x10];
4598
4599         u8         reserved_3[0x10];
4600         u8         pkey_index[0x10];
4601 };
4602
4603 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4604         u8         status[0x8];
4605         u8         reserved_0[0x18];
4606
4607         u8         syndrome[0x20];
4608
4609         u8         reserved_1[0x20];
4610
4611         u8         gids_num[0x10];
4612         u8         reserved_2[0x10];
4613
4614         struct mlx5_ifc_array128_auto_bits gid[0];
4615 };
4616
4617 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4618         u8         opcode[0x10];
4619         u8         reserved_0[0x10];
4620
4621         u8         reserved_1[0x10];
4622         u8         op_mod[0x10];
4623
4624         u8         other_vport[0x1];
4625         u8         reserved_2[0xb];
4626         u8         port_num[0x4];
4627         u8         vport_number[0x10];
4628
4629         u8         reserved_3[0x10];
4630         u8         gid_index[0x10];
4631 };
4632
4633 struct mlx5_ifc_query_hca_vport_context_out_bits {
4634         u8         status[0x8];
4635         u8         reserved_0[0x18];
4636
4637         u8         syndrome[0x20];
4638
4639         u8         reserved_1[0x40];
4640
4641         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4642 };
4643
4644 struct mlx5_ifc_query_hca_vport_context_in_bits {
4645         u8         opcode[0x10];
4646         u8         reserved_0[0x10];
4647
4648         u8         reserved_1[0x10];
4649         u8         op_mod[0x10];
4650
4651         u8         other_vport[0x1];
4652         u8         reserved_2[0xb];
4653         u8         port_num[0x4];
4654         u8         vport_number[0x10];
4655
4656         u8         reserved_3[0x20];
4657 };
4658
4659 struct mlx5_ifc_query_hca_cap_out_bits {
4660         u8         status[0x8];
4661         u8         reserved_0[0x18];
4662
4663         u8         syndrome[0x20];
4664
4665         u8         reserved_1[0x40];
4666
4667         union mlx5_ifc_hca_cap_union_bits capability;
4668 };
4669
4670 struct mlx5_ifc_query_hca_cap_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_0[0x10];
4673
4674         u8         reserved_1[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         reserved_2[0x40];
4678 };
4679
4680 struct mlx5_ifc_query_flow_table_out_bits {
4681         u8         status[0x8];
4682         u8         reserved_at_8[0x18];
4683
4684         u8         syndrome[0x20];
4685
4686         u8         reserved_at_40[0x80];
4687
4688         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4689 };
4690
4691 struct mlx5_ifc_query_flow_table_in_bits {
4692         u8         opcode[0x10];
4693         u8         reserved_0[0x10];
4694
4695         u8         reserved_1[0x10];
4696         u8         op_mod[0x10];
4697
4698         u8         other_vport[0x1];
4699         u8         reserved_2[0xf];
4700         u8         vport_number[0x10];
4701
4702         u8         reserved_3[0x20];
4703
4704         u8         table_type[0x8];
4705         u8         reserved_4[0x18];
4706
4707         u8         reserved_5[0x8];
4708         u8         table_id[0x18];
4709
4710         u8         reserved_6[0x140];
4711 };
4712
4713 struct mlx5_ifc_query_fte_out_bits {
4714         u8         status[0x8];
4715         u8         reserved_0[0x18];
4716
4717         u8         syndrome[0x20];
4718
4719         u8         reserved_1[0x1c0];
4720
4721         struct mlx5_ifc_flow_context_bits flow_context;
4722 };
4723
4724 struct mlx5_ifc_query_fte_in_bits {
4725         u8         opcode[0x10];
4726         u8         reserved_0[0x10];
4727
4728         u8         reserved_1[0x10];
4729         u8         op_mod[0x10];
4730
4731         u8         other_vport[0x1];
4732         u8         reserved_2[0xf];
4733         u8         vport_number[0x10];
4734
4735         u8         reserved_3[0x20];
4736
4737         u8         table_type[0x8];
4738         u8         reserved_4[0x18];
4739
4740         u8         reserved_5[0x8];
4741         u8         table_id[0x18];
4742
4743         u8         reserved_6[0x40];
4744
4745         u8         flow_index[0x20];
4746
4747         u8         reserved_7[0xe0];
4748 };
4749
4750 enum {
4751         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4752         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4753         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4754 };
4755
4756 struct mlx5_ifc_query_flow_group_out_bits {
4757         u8         status[0x8];
4758         u8         reserved_0[0x18];
4759
4760         u8         syndrome[0x20];
4761
4762         u8         reserved_1[0xa0];
4763
4764         u8         start_flow_index[0x20];
4765
4766         u8         reserved_2[0x20];
4767
4768         u8         end_flow_index[0x20];
4769
4770         u8         reserved_3[0xa0];
4771
4772         u8         reserved_4[0x18];
4773         u8         match_criteria_enable[0x8];
4774
4775         struct mlx5_ifc_fte_match_param_bits match_criteria;
4776
4777         u8         reserved_5[0xe00];
4778 };
4779
4780 struct mlx5_ifc_query_flow_group_in_bits {
4781         u8         opcode[0x10];
4782         u8         reserved_0[0x10];
4783
4784         u8         reserved_1[0x10];
4785         u8         op_mod[0x10];
4786
4787         u8         other_vport[0x1];
4788         u8         reserved_2[0xf];
4789         u8         vport_number[0x10];
4790
4791         u8         reserved_3[0x20];
4792
4793         u8         table_type[0x8];
4794         u8         reserved_4[0x18];
4795
4796         u8         reserved_5[0x8];
4797         u8         table_id[0x18];
4798
4799         u8         group_id[0x20];
4800
4801         u8         reserved_6[0x120];
4802 };
4803
4804 struct mlx5_ifc_query_flow_counter_out_bits {
4805         u8         status[0x8];
4806         u8         reserved_at_8[0x18];
4807
4808         u8         syndrome[0x20];
4809
4810         u8         reserved_at_40[0x40];
4811
4812         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4813 };
4814
4815 struct mlx5_ifc_query_flow_counter_in_bits {
4816         u8         opcode[0x10];
4817         u8         reserved_at_10[0x10];
4818
4819         u8         reserved_at_20[0x10];
4820         u8         op_mod[0x10];
4821
4822         u8         reserved_at_40[0x80];
4823
4824         u8         clear[0x1];
4825         u8         reserved_at_c1[0xf];
4826         u8         num_of_counters[0x10];
4827
4828         u8         reserved_at_e0[0x10];
4829         u8         flow_counter_id[0x10];
4830 };
4831
4832 struct mlx5_ifc_query_esw_vport_context_out_bits {
4833         u8         status[0x8];
4834         u8         reserved_0[0x18];
4835
4836         u8         syndrome[0x20];
4837
4838         u8         reserved_1[0x40];
4839
4840         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4841 };
4842
4843 struct mlx5_ifc_query_esw_vport_context_in_bits {
4844         u8         opcode[0x10];
4845         u8         reserved_0[0x10];
4846
4847         u8         reserved_1[0x10];
4848         u8         op_mod[0x10];
4849
4850         u8         other_vport[0x1];
4851         u8         reserved_2[0xf];
4852         u8         vport_number[0x10];
4853
4854         u8         reserved_3[0x20];
4855 };
4856
4857 struct mlx5_ifc_query_eq_out_bits {
4858         u8         status[0x8];
4859         u8         reserved_0[0x18];
4860
4861         u8         syndrome[0x20];
4862
4863         u8         reserved_1[0x40];
4864
4865         struct mlx5_ifc_eqc_bits eq_context_entry;
4866
4867         u8         reserved_2[0x40];
4868
4869         u8         event_bitmask[0x40];
4870
4871         u8         reserved_3[0x580];
4872
4873         u8         pas[0][0x40];
4874 };
4875
4876 struct mlx5_ifc_query_eq_in_bits {
4877         u8         opcode[0x10];
4878         u8         reserved_0[0x10];
4879
4880         u8         reserved_1[0x10];
4881         u8         op_mod[0x10];
4882
4883         u8         reserved_2[0x18];
4884         u8         eq_number[0x8];
4885
4886         u8         reserved_3[0x20];
4887 };
4888
4889 struct mlx5_ifc_query_dct_out_bits {
4890         u8         status[0x8];
4891         u8         reserved_0[0x18];
4892
4893         u8         syndrome[0x20];
4894
4895         u8         reserved_1[0x40];
4896
4897         struct mlx5_ifc_dctc_bits dct_context_entry;
4898
4899         u8         reserved_2[0x180];
4900 };
4901
4902 struct mlx5_ifc_query_dct_in_bits {
4903         u8         opcode[0x10];
4904         u8         reserved_0[0x10];
4905
4906         u8         reserved_1[0x10];
4907         u8         op_mod[0x10];
4908
4909         u8         reserved_2[0x8];
4910         u8         dctn[0x18];
4911
4912         u8         reserved_3[0x20];
4913 };
4914
4915 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4916         u8         status[0x8];
4917         u8         reserved_0[0x18];
4918
4919         u8         syndrome[0x20];
4920
4921         u8         enable[0x1];
4922         u8         reserved_1[0x1f];
4923
4924         u8         reserved_2[0x160];
4925
4926         struct mlx5_ifc_cmd_pas_bits pas;
4927 };
4928
4929 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4930         u8         opcode[0x10];
4931         u8         reserved_0[0x10];
4932
4933         u8         reserved_1[0x10];
4934         u8         op_mod[0x10];
4935
4936         u8         reserved_2[0x40];
4937 };
4938
4939 struct mlx5_ifc_query_cq_out_bits {
4940         u8         status[0x8];
4941         u8         reserved_0[0x18];
4942
4943         u8         syndrome[0x20];
4944
4945         u8         reserved_1[0x40];
4946
4947         struct mlx5_ifc_cqc_bits cq_context;
4948
4949         u8         reserved_2[0x600];
4950
4951         u8         pas[0][0x40];
4952 };
4953
4954 struct mlx5_ifc_query_cq_in_bits {
4955         u8         opcode[0x10];
4956         u8         reserved_0[0x10];
4957
4958         u8         reserved_1[0x10];
4959         u8         op_mod[0x10];
4960
4961         u8         reserved_2[0x8];
4962         u8         cqn[0x18];
4963
4964         u8         reserved_3[0x20];
4965 };
4966
4967 struct mlx5_ifc_query_cong_status_out_bits {
4968         u8         status[0x8];
4969         u8         reserved_0[0x18];
4970
4971         u8         syndrome[0x20];
4972
4973         u8         reserved_1[0x20];
4974
4975         u8         enable[0x1];
4976         u8         tag_enable[0x1];
4977         u8         reserved_2[0x1e];
4978 };
4979
4980 struct mlx5_ifc_query_cong_status_in_bits {
4981         u8         opcode[0x10];
4982         u8         reserved_0[0x10];
4983
4984         u8         reserved_1[0x10];
4985         u8         op_mod[0x10];
4986
4987         u8         reserved_2[0x18];
4988         u8         priority[0x4];
4989         u8         cong_protocol[0x4];
4990
4991         u8         reserved_3[0x20];
4992 };
4993
4994 struct mlx5_ifc_query_cong_statistics_out_bits {
4995         u8         status[0x8];
4996         u8         reserved_0[0x18];
4997
4998         u8         syndrome[0x20];
4999
5000         u8         reserved_1[0x40];
5001
5002         u8         rp_cur_flows[0x20];
5003
5004         u8         sum_flows[0x20];
5005
5006         u8         rp_cnp_ignored_high[0x20];
5007
5008         u8         rp_cnp_ignored_low[0x20];
5009
5010         u8         rp_cnp_handled_high[0x20];
5011
5012         u8         rp_cnp_handled_low[0x20];
5013
5014         u8         reserved_2[0x100];
5015
5016         u8         time_stamp_high[0x20];
5017
5018         u8         time_stamp_low[0x20];
5019
5020         u8         accumulators_period[0x20];
5021
5022         u8         np_ecn_marked_roce_packets_high[0x20];
5023
5024         u8         np_ecn_marked_roce_packets_low[0x20];
5025
5026         u8         np_cnp_sent_high[0x20];
5027
5028         u8         np_cnp_sent_low[0x20];
5029
5030         u8         reserved_3[0x560];
5031 };
5032
5033 struct mlx5_ifc_query_cong_statistics_in_bits {
5034         u8         opcode[0x10];
5035         u8         reserved_0[0x10];
5036
5037         u8         reserved_1[0x10];
5038         u8         op_mod[0x10];
5039
5040         u8         clear[0x1];
5041         u8         reserved_2[0x1f];
5042
5043         u8         reserved_3[0x20];
5044 };
5045
5046 struct mlx5_ifc_query_cong_params_out_bits {
5047         u8         status[0x8];
5048         u8         reserved_0[0x18];
5049
5050         u8         syndrome[0x20];
5051
5052         u8         reserved_1[0x40];
5053
5054         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5055 };
5056
5057 struct mlx5_ifc_query_cong_params_in_bits {
5058         u8         opcode[0x10];
5059         u8         reserved_0[0x10];
5060
5061         u8         reserved_1[0x10];
5062         u8         op_mod[0x10];
5063
5064         u8         reserved_2[0x1c];
5065         u8         cong_protocol[0x4];
5066
5067         u8         reserved_3[0x20];
5068 };
5069
5070 struct mlx5_ifc_query_burst_size_out_bits {
5071         u8         status[0x8];
5072         u8         reserved_0[0x18];
5073
5074         u8         syndrome[0x20];
5075
5076         u8         reserved_1[0x20];
5077
5078         u8         reserved_2[0x9];
5079         u8         device_burst_size[0x17];
5080 };
5081
5082 struct mlx5_ifc_query_burst_size_in_bits {
5083         u8         opcode[0x10];
5084         u8         reserved_0[0x10];
5085
5086         u8         reserved_1[0x10];
5087         u8         op_mod[0x10];
5088
5089         u8         reserved_2[0x40];
5090 };
5091
5092 struct mlx5_ifc_query_adapter_out_bits {
5093         u8         status[0x8];
5094         u8         reserved_0[0x18];
5095
5096         u8         syndrome[0x20];
5097
5098         u8         reserved_1[0x40];
5099
5100         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5101 };
5102
5103 struct mlx5_ifc_query_adapter_in_bits {
5104         u8         opcode[0x10];
5105         u8         reserved_0[0x10];
5106
5107         u8         reserved_1[0x10];
5108         u8         op_mod[0x10];
5109
5110         u8         reserved_2[0x40];
5111 };
5112
5113 struct mlx5_ifc_qp_2rst_out_bits {
5114         u8         status[0x8];
5115         u8         reserved_0[0x18];
5116
5117         u8         syndrome[0x20];
5118
5119         u8         reserved_1[0x40];
5120 };
5121
5122 struct mlx5_ifc_qp_2rst_in_bits {
5123         u8         opcode[0x10];
5124         u8         reserved_0[0x10];
5125
5126         u8         reserved_1[0x10];
5127         u8         op_mod[0x10];
5128
5129         u8         reserved_2[0x8];
5130         u8         qpn[0x18];
5131
5132         u8         reserved_3[0x20];
5133 };
5134
5135 struct mlx5_ifc_qp_2err_out_bits {
5136         u8         status[0x8];
5137         u8         reserved_0[0x18];
5138
5139         u8         syndrome[0x20];
5140
5141         u8         reserved_1[0x40];
5142 };
5143
5144 struct mlx5_ifc_qp_2err_in_bits {
5145         u8         opcode[0x10];
5146         u8         reserved_0[0x10];
5147
5148         u8         reserved_1[0x10];
5149         u8         op_mod[0x10];
5150
5151         u8         reserved_2[0x8];
5152         u8         qpn[0x18];
5153
5154         u8         reserved_3[0x20];
5155 };
5156
5157 struct mlx5_ifc_para_vport_element_bits {
5158         u8         reserved_at_0[0xc];
5159         u8         traffic_class[0x4];
5160         u8         qos_para_vport_number[0x10];
5161 };
5162
5163 struct mlx5_ifc_page_fault_resume_out_bits {
5164         u8         status[0x8];
5165         u8         reserved_0[0x18];
5166
5167         u8         syndrome[0x20];
5168
5169         u8         reserved_1[0x40];
5170 };
5171
5172 struct mlx5_ifc_page_fault_resume_in_bits {
5173         u8         opcode[0x10];
5174         u8         reserved_0[0x10];
5175
5176         u8         reserved_1[0x10];
5177         u8         op_mod[0x10];
5178
5179         u8         error[0x1];
5180         u8         reserved_2[0x4];
5181         u8         rdma[0x1];
5182         u8         read_write[0x1];
5183         u8         req_res[0x1];
5184         u8         qpn[0x18];
5185
5186         u8         reserved_3[0x20];
5187 };
5188
5189 struct mlx5_ifc_nop_out_bits {
5190         u8         status[0x8];
5191         u8         reserved_0[0x18];
5192
5193         u8         syndrome[0x20];
5194
5195         u8         reserved_1[0x40];
5196 };
5197
5198 struct mlx5_ifc_nop_in_bits {
5199         u8         opcode[0x10];
5200         u8         reserved_0[0x10];
5201
5202         u8         reserved_1[0x10];
5203         u8         op_mod[0x10];
5204
5205         u8         reserved_2[0x40];
5206 };
5207
5208 struct mlx5_ifc_modify_vport_state_out_bits {
5209         u8         status[0x8];
5210         u8         reserved_0[0x18];
5211
5212         u8         syndrome[0x20];
5213
5214         u8         reserved_1[0x40];
5215 };
5216
5217 enum {
5218         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5219         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5220         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5221 };
5222
5223 enum {
5224         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5225         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5226         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5227 };
5228
5229 struct mlx5_ifc_modify_vport_state_in_bits {
5230         u8         opcode[0x10];
5231         u8         reserved_0[0x10];
5232
5233         u8         reserved_1[0x10];
5234         u8         op_mod[0x10];
5235
5236         u8         other_vport[0x1];
5237         u8         reserved_2[0xf];
5238         u8         vport_number[0x10];
5239
5240         u8         reserved_3[0x18];
5241         u8         admin_state[0x4];
5242         u8         reserved_4[0x4];
5243 };
5244
5245 struct mlx5_ifc_modify_tis_out_bits {
5246         u8         status[0x8];
5247         u8         reserved_0[0x18];
5248
5249         u8         syndrome[0x20];
5250
5251         u8         reserved_1[0x40];
5252 };
5253
5254 struct mlx5_ifc_modify_tis_bitmask_bits {
5255         u8         reserved_at_0[0x20];
5256
5257         u8         reserved_at_20[0x1d];
5258         u8         lag_tx_port_affinity[0x1];
5259         u8         strict_lag_tx_port_affinity[0x1];
5260         u8         prio[0x1];
5261 };
5262
5263 struct mlx5_ifc_modify_tis_in_bits {
5264         u8         opcode[0x10];
5265         u8         reserved_0[0x10];
5266
5267         u8         reserved_1[0x10];
5268         u8         op_mod[0x10];
5269
5270         u8         reserved_2[0x8];
5271         u8         tisn[0x18];
5272
5273         u8         reserved_3[0x20];
5274
5275         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5276
5277         u8         reserved_4[0x40];
5278
5279         struct mlx5_ifc_tisc_bits ctx;
5280 };
5281
5282 struct mlx5_ifc_modify_tir_out_bits {
5283         u8         status[0x8];
5284         u8         reserved_0[0x18];
5285
5286         u8         syndrome[0x20];
5287
5288         u8         reserved_1[0x40];
5289 };
5290
5291 enum
5292 {
5293         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5294         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5295 };
5296
5297 struct mlx5_ifc_modify_tir_in_bits {
5298         u8         opcode[0x10];
5299         u8         reserved_0[0x10];
5300
5301         u8         reserved_1[0x10];
5302         u8         op_mod[0x10];
5303
5304         u8         reserved_2[0x8];
5305         u8         tirn[0x18];
5306
5307         u8         reserved_3[0x20];
5308
5309         u8         modify_bitmask[0x40];
5310
5311         u8         reserved_4[0x40];
5312
5313         struct mlx5_ifc_tirc_bits tir_context;
5314 };
5315
5316 struct mlx5_ifc_modify_sq_out_bits {
5317         u8         status[0x8];
5318         u8         reserved_0[0x18];
5319
5320         u8         syndrome[0x20];
5321
5322         u8         reserved_1[0x40];
5323 };
5324
5325 struct mlx5_ifc_modify_sq_in_bits {
5326         u8         opcode[0x10];
5327         u8         reserved_0[0x10];
5328
5329         u8         reserved_1[0x10];
5330         u8         op_mod[0x10];
5331
5332         u8         sq_state[0x4];
5333         u8         reserved_2[0x4];
5334         u8         sqn[0x18];
5335
5336         u8         reserved_3[0x20];
5337
5338         u8         modify_bitmask[0x40];
5339
5340         u8         reserved_4[0x40];
5341
5342         struct mlx5_ifc_sqc_bits ctx;
5343 };
5344
5345 struct mlx5_ifc_modify_scheduling_element_out_bits {
5346         u8         status[0x8];
5347         u8         reserved_at_8[0x18];
5348
5349         u8         syndrome[0x20];
5350
5351         u8         reserved_at_40[0x1c0];
5352 };
5353
5354 enum {
5355         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5356 };
5357
5358 enum {
5359         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5360         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5361 };
5362
5363 struct mlx5_ifc_modify_scheduling_element_in_bits {
5364         u8         opcode[0x10];
5365         u8         reserved_at_10[0x10];
5366
5367         u8         reserved_at_20[0x10];
5368         u8         op_mod[0x10];
5369
5370         u8         scheduling_hierarchy[0x8];
5371         u8         reserved_at_48[0x18];
5372
5373         u8         scheduling_element_id[0x20];
5374
5375         u8         reserved_at_80[0x20];
5376
5377         u8         modify_bitmask[0x20];
5378
5379         u8         reserved_at_c0[0x40];
5380
5381         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5382
5383         u8         reserved_at_300[0x100];
5384 };
5385
5386 struct mlx5_ifc_modify_rqt_out_bits {
5387         u8         status[0x8];
5388         u8         reserved_0[0x18];
5389
5390         u8         syndrome[0x20];
5391
5392         u8         reserved_1[0x40];
5393 };
5394
5395 struct mlx5_ifc_modify_rqt_in_bits {
5396         u8         opcode[0x10];
5397         u8         reserved_0[0x10];
5398
5399         u8         reserved_1[0x10];
5400         u8         op_mod[0x10];
5401
5402         u8         reserved_2[0x8];
5403         u8         rqtn[0x18];
5404
5405         u8         reserved_3[0x20];
5406
5407         u8         modify_bitmask[0x40];
5408
5409         u8         reserved_4[0x40];
5410
5411         struct mlx5_ifc_rqtc_bits ctx;
5412 };
5413
5414 struct mlx5_ifc_modify_rq_out_bits {
5415         u8         status[0x8];
5416         u8         reserved_0[0x18];
5417
5418         u8         syndrome[0x20];
5419
5420         u8         reserved_1[0x40];
5421 };
5422
5423 enum {
5424         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5425         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5426 };
5427
5428 struct mlx5_ifc_modify_rq_in_bits {
5429         u8         opcode[0x10];
5430         u8         reserved_0[0x10];
5431
5432         u8         reserved_1[0x10];
5433         u8         op_mod[0x10];
5434
5435         u8         rq_state[0x4];
5436         u8         reserved_2[0x4];
5437         u8         rqn[0x18];
5438
5439         u8         reserved_3[0x20];
5440
5441         u8         modify_bitmask[0x40];
5442
5443         u8         reserved_4[0x40];
5444
5445         struct mlx5_ifc_rqc_bits ctx;
5446 };
5447
5448 struct mlx5_ifc_modify_rmp_out_bits {
5449         u8         status[0x8];
5450         u8         reserved_0[0x18];
5451
5452         u8         syndrome[0x20];
5453
5454         u8         reserved_1[0x40];
5455 };
5456
5457 struct mlx5_ifc_rmp_bitmask_bits {
5458         u8         reserved[0x20];
5459
5460         u8         reserved1[0x1f];
5461         u8         lwm[0x1];
5462 };
5463
5464 struct mlx5_ifc_modify_rmp_in_bits {
5465         u8         opcode[0x10];
5466         u8         reserved_0[0x10];
5467
5468         u8         reserved_1[0x10];
5469         u8         op_mod[0x10];
5470
5471         u8         rmp_state[0x4];
5472         u8         reserved_2[0x4];
5473         u8         rmpn[0x18];
5474
5475         u8         reserved_3[0x20];
5476
5477         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5478
5479         u8         reserved_4[0x40];
5480
5481         struct mlx5_ifc_rmpc_bits ctx;
5482 };
5483
5484 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5485         u8         status[0x8];
5486         u8         reserved_0[0x18];
5487
5488         u8         syndrome[0x20];
5489
5490         u8         reserved_1[0x40];
5491 };
5492
5493 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5494         u8         reserved_0[0x14];
5495         u8         disable_uc_local_lb[0x1];
5496         u8         disable_mc_local_lb[0x1];
5497         u8         node_guid[0x1];
5498         u8         port_guid[0x1];
5499         u8         min_wqe_inline_mode[0x1];
5500         u8         mtu[0x1];
5501         u8         change_event[0x1];
5502         u8         promisc[0x1];
5503         u8         permanent_address[0x1];
5504         u8         addresses_list[0x1];
5505         u8         roce_en[0x1];
5506         u8         reserved_1[0x1];
5507 };
5508
5509 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5510         u8         opcode[0x10];
5511         u8         reserved_0[0x10];
5512
5513         u8         reserved_1[0x10];
5514         u8         op_mod[0x10];
5515
5516         u8         other_vport[0x1];
5517         u8         reserved_2[0xf];
5518         u8         vport_number[0x10];
5519
5520         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5521
5522         u8         reserved_3[0x780];
5523
5524         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5525 };
5526
5527 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5528         u8         status[0x8];
5529         u8         reserved_0[0x18];
5530
5531         u8         syndrome[0x20];
5532
5533         u8         reserved_1[0x40];
5534 };
5535
5536 struct mlx5_ifc_grh_bits {
5537         u8      ip_version[4];
5538         u8      traffic_class[8];
5539         u8      flow_label[20];
5540         u8      payload_length[16];
5541         u8      next_header[8];
5542         u8      hop_limit[8];
5543         u8      sgid[128];
5544         u8      dgid[128];
5545 };
5546
5547 struct mlx5_ifc_bth_bits {
5548         u8      opcode[8];
5549         u8      se[1];
5550         u8      migreq[1];
5551         u8      pad_count[2];
5552         u8      tver[4];
5553         u8      p_key[16];
5554         u8      reserved8[8];
5555         u8      dest_qp[24];
5556         u8      ack_req[1];
5557         u8      reserved7[7];
5558         u8      psn[24];
5559 };
5560
5561 struct mlx5_ifc_aeth_bits {
5562         u8      syndrome[8];
5563         u8      msn[24];
5564 };
5565
5566 struct mlx5_ifc_dceth_bits {
5567         u8      reserved0[8];
5568         u8      session_id[24];
5569         u8      reserved1[8];
5570         u8      dci_dct[24];
5571 };
5572
5573 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5574         u8         opcode[0x10];
5575         u8         reserved_0[0x10];
5576
5577         u8         reserved_1[0x10];
5578         u8         op_mod[0x10];
5579
5580         u8         other_vport[0x1];
5581         u8         reserved_2[0xb];
5582         u8         port_num[0x4];
5583         u8         vport_number[0x10];
5584
5585         u8         reserved_3[0x20];
5586
5587         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5588 };
5589
5590 struct mlx5_ifc_modify_flow_table_out_bits {
5591         u8         status[0x8];
5592         u8         reserved_at_8[0x18];
5593
5594         u8         syndrome[0x20];
5595
5596         u8         reserved_at_40[0x40];
5597 };
5598
5599 enum {
5600         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5601         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5602 };
5603
5604 struct mlx5_ifc_modify_flow_table_in_bits {
5605         u8         opcode[0x10];
5606         u8         reserved_at_10[0x10];
5607
5608         u8         reserved_at_20[0x10];
5609         u8         op_mod[0x10];
5610
5611         u8         other_vport[0x1];
5612         u8         reserved_at_41[0xf];
5613         u8         vport_number[0x10];
5614
5615         u8         reserved_at_60[0x10];
5616         u8         modify_field_select[0x10];
5617
5618         u8         table_type[0x8];
5619         u8         reserved_at_88[0x18];
5620
5621         u8         reserved_at_a0[0x8];
5622         u8         table_id[0x18];
5623
5624         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5625 };
5626
5627 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5628         u8         status[0x8];
5629         u8         reserved_0[0x18];
5630
5631         u8         syndrome[0x20];
5632
5633         u8         reserved_1[0x40];
5634 };
5635
5636 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5637         u8         reserved[0x1c];
5638         u8         vport_cvlan_insert[0x1];
5639         u8         vport_svlan_insert[0x1];
5640         u8         vport_cvlan_strip[0x1];
5641         u8         vport_svlan_strip[0x1];
5642 };
5643
5644 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5645         u8         opcode[0x10];
5646         u8         reserved_0[0x10];
5647
5648         u8         reserved_1[0x10];
5649         u8         op_mod[0x10];
5650
5651         u8         other_vport[0x1];
5652         u8         reserved_2[0xf];
5653         u8         vport_number[0x10];
5654
5655         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5656
5657         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5658 };
5659
5660 struct mlx5_ifc_modify_cq_out_bits {
5661         u8         status[0x8];
5662         u8         reserved_0[0x18];
5663
5664         u8         syndrome[0x20];
5665
5666         u8         reserved_1[0x40];
5667 };
5668
5669 enum {
5670         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5671         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5672 };
5673
5674 struct mlx5_ifc_modify_cq_in_bits {
5675         u8         opcode[0x10];
5676         u8         reserved_0[0x10];
5677
5678         u8         reserved_1[0x10];
5679         u8         op_mod[0x10];
5680
5681         u8         reserved_2[0x8];
5682         u8         cqn[0x18];
5683
5684         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5685
5686         struct mlx5_ifc_cqc_bits cq_context;
5687
5688         u8         reserved_3[0x600];
5689
5690         u8         pas[0][0x40];
5691 };
5692
5693 struct mlx5_ifc_modify_cong_status_out_bits {
5694         u8         status[0x8];
5695         u8         reserved_0[0x18];
5696
5697         u8         syndrome[0x20];
5698
5699         u8         reserved_1[0x40];
5700 };
5701
5702 struct mlx5_ifc_modify_cong_status_in_bits {
5703         u8         opcode[0x10];
5704         u8         reserved_0[0x10];
5705
5706         u8         reserved_1[0x10];
5707         u8         op_mod[0x10];
5708
5709         u8         reserved_2[0x18];
5710         u8         priority[0x4];
5711         u8         cong_protocol[0x4];
5712
5713         u8         enable[0x1];
5714         u8         tag_enable[0x1];
5715         u8         reserved_3[0x1e];
5716 };
5717
5718 struct mlx5_ifc_modify_cong_params_out_bits {
5719         u8         status[0x8];
5720         u8         reserved_0[0x18];
5721
5722         u8         syndrome[0x20];
5723
5724         u8         reserved_1[0x40];
5725 };
5726
5727 struct mlx5_ifc_modify_cong_params_in_bits {
5728         u8         opcode[0x10];
5729         u8         reserved_0[0x10];
5730
5731         u8         reserved_1[0x10];
5732         u8         op_mod[0x10];
5733
5734         u8         reserved_2[0x1c];
5735         u8         cong_protocol[0x4];
5736
5737         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5738
5739         u8         reserved_3[0x80];
5740
5741         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5742 };
5743
5744 struct mlx5_ifc_manage_pages_out_bits {
5745         u8         status[0x8];
5746         u8         reserved_0[0x18];
5747
5748         u8         syndrome[0x20];
5749
5750         u8         output_num_entries[0x20];
5751
5752         u8         reserved_1[0x20];
5753
5754         u8         pas[0][0x40];
5755 };
5756
5757 enum {
5758         MLX5_PAGES_CANT_GIVE                            = 0x0,
5759         MLX5_PAGES_GIVE                                 = 0x1,
5760         MLX5_PAGES_TAKE                                 = 0x2,
5761 };
5762
5763 struct mlx5_ifc_manage_pages_in_bits {
5764         u8         opcode[0x10];
5765         u8         reserved_0[0x10];
5766
5767         u8         reserved_1[0x10];
5768         u8         op_mod[0x10];
5769
5770         u8         reserved_2[0x10];
5771         u8         function_id[0x10];
5772
5773         u8         input_num_entries[0x20];
5774
5775         u8         pas[0][0x40];
5776 };
5777
5778 struct mlx5_ifc_mad_ifc_out_bits {
5779         u8         status[0x8];
5780         u8         reserved_0[0x18];
5781
5782         u8         syndrome[0x20];
5783
5784         u8         reserved_1[0x40];
5785
5786         u8         response_mad_packet[256][0x8];
5787 };
5788
5789 struct mlx5_ifc_mad_ifc_in_bits {
5790         u8         opcode[0x10];
5791         u8         reserved_0[0x10];
5792
5793         u8         reserved_1[0x10];
5794         u8         op_mod[0x10];
5795
5796         u8         remote_lid[0x10];
5797         u8         reserved_2[0x8];
5798         u8         port[0x8];
5799
5800         u8         reserved_3[0x20];
5801
5802         u8         mad[256][0x8];
5803 };
5804
5805 struct mlx5_ifc_init_hca_out_bits {
5806         u8         status[0x8];
5807         u8         reserved_0[0x18];
5808
5809         u8         syndrome[0x20];
5810
5811         u8         reserved_1[0x40];
5812 };
5813
5814 enum {
5815         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5816         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5817 };
5818
5819 struct mlx5_ifc_init_hca_in_bits {
5820         u8         opcode[0x10];
5821         u8         reserved_0[0x10];
5822
5823         u8         reserved_1[0x10];
5824         u8         op_mod[0x10];
5825
5826         u8         reserved_2[0x40];
5827 };
5828
5829 struct mlx5_ifc_init2rtr_qp_out_bits {
5830         u8         status[0x8];
5831         u8         reserved_0[0x18];
5832
5833         u8         syndrome[0x20];
5834
5835         u8         reserved_1[0x40];
5836 };
5837
5838 struct mlx5_ifc_init2rtr_qp_in_bits {
5839         u8         opcode[0x10];
5840         u8         reserved_0[0x10];
5841
5842         u8         reserved_1[0x10];
5843         u8         op_mod[0x10];
5844
5845         u8         reserved_2[0x8];
5846         u8         qpn[0x18];
5847
5848         u8         reserved_3[0x20];
5849
5850         u8         opt_param_mask[0x20];
5851
5852         u8         reserved_4[0x20];
5853
5854         struct mlx5_ifc_qpc_bits qpc;
5855
5856         u8         reserved_5[0x80];
5857 };
5858
5859 struct mlx5_ifc_init2init_qp_out_bits {
5860         u8         status[0x8];
5861         u8         reserved_0[0x18];
5862
5863         u8         syndrome[0x20];
5864
5865         u8         reserved_1[0x40];
5866 };
5867
5868 struct mlx5_ifc_init2init_qp_in_bits {
5869         u8         opcode[0x10];
5870         u8         reserved_0[0x10];
5871
5872         u8         reserved_1[0x10];
5873         u8         op_mod[0x10];
5874
5875         u8         reserved_2[0x8];
5876         u8         qpn[0x18];
5877
5878         u8         reserved_3[0x20];
5879
5880         u8         opt_param_mask[0x20];
5881
5882         u8         reserved_4[0x20];
5883
5884         struct mlx5_ifc_qpc_bits qpc;
5885
5886         u8         reserved_5[0x80];
5887 };
5888
5889 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5890         u8         status[0x8];
5891         u8         reserved_0[0x18];
5892
5893         u8         syndrome[0x20];
5894
5895         u8         reserved_1[0x40];
5896
5897         u8         packet_headers_log[128][0x8];
5898
5899         u8         packet_syndrome[64][0x8];
5900 };
5901
5902 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5903         u8         opcode[0x10];
5904         u8         reserved_0[0x10];
5905
5906         u8         reserved_1[0x10];
5907         u8         op_mod[0x10];
5908
5909         u8         reserved_2[0x40];
5910 };
5911
5912 struct mlx5_ifc_gen_eqe_in_bits {
5913         u8         opcode[0x10];
5914         u8         reserved_0[0x10];
5915
5916         u8         reserved_1[0x10];
5917         u8         op_mod[0x10];
5918
5919         u8         reserved_2[0x18];
5920         u8         eq_number[0x8];
5921
5922         u8         reserved_3[0x20];
5923
5924         u8         eqe[64][0x8];
5925 };
5926
5927 struct mlx5_ifc_gen_eq_out_bits {
5928         u8         status[0x8];
5929         u8         reserved_0[0x18];
5930
5931         u8         syndrome[0x20];
5932
5933         u8         reserved_1[0x40];
5934 };
5935
5936 struct mlx5_ifc_enable_hca_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_0[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_1[0x20];
5943 };
5944
5945 struct mlx5_ifc_enable_hca_in_bits {
5946         u8         opcode[0x10];
5947         u8         reserved_0[0x10];
5948
5949         u8         reserved_1[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_2[0x10];
5953         u8         function_id[0x10];
5954
5955         u8         reserved_3[0x20];
5956 };
5957
5958 struct mlx5_ifc_drain_dct_out_bits {
5959         u8         status[0x8];
5960         u8         reserved_0[0x18];
5961
5962         u8         syndrome[0x20];
5963
5964         u8         reserved_1[0x40];
5965 };
5966
5967 struct mlx5_ifc_drain_dct_in_bits {
5968         u8         opcode[0x10];
5969         u8         reserved_0[0x10];
5970
5971         u8         reserved_1[0x10];
5972         u8         op_mod[0x10];
5973
5974         u8         reserved_2[0x8];
5975         u8         dctn[0x18];
5976
5977         u8         reserved_3[0x20];
5978 };
5979
5980 struct mlx5_ifc_disable_hca_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_0[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_1[0x20];
5987 };
5988
5989 struct mlx5_ifc_disable_hca_in_bits {
5990         u8         opcode[0x10];
5991         u8         reserved_0[0x10];
5992
5993         u8         reserved_1[0x10];
5994         u8         op_mod[0x10];
5995
5996         u8         reserved_2[0x10];
5997         u8         function_id[0x10];
5998
5999         u8         reserved_3[0x20];
6000 };
6001
6002 struct mlx5_ifc_detach_from_mcg_out_bits {
6003         u8         status[0x8];
6004         u8         reserved_0[0x18];
6005
6006         u8         syndrome[0x20];
6007
6008         u8         reserved_1[0x40];
6009 };
6010
6011 struct mlx5_ifc_detach_from_mcg_in_bits {
6012         u8         opcode[0x10];
6013         u8         reserved_0[0x10];
6014
6015         u8         reserved_1[0x10];
6016         u8         op_mod[0x10];
6017
6018         u8         reserved_2[0x8];
6019         u8         qpn[0x18];
6020
6021         u8         reserved_3[0x20];
6022
6023         u8         multicast_gid[16][0x8];
6024 };
6025
6026 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_0[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_1[0x40];
6033 };
6034
6035 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_0[0x10];
6038
6039         u8         reserved_1[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_2[0x8];
6043         u8         xrc_srqn[0x18];
6044
6045         u8         reserved_3[0x20];
6046 };
6047
6048 struct mlx5_ifc_destroy_tis_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_0[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_1[0x40];
6055 };
6056
6057 struct mlx5_ifc_destroy_tis_in_bits {
6058         u8         opcode[0x10];
6059         u8         reserved_0[0x10];
6060
6061         u8         reserved_1[0x10];
6062         u8         op_mod[0x10];
6063
6064         u8         reserved_2[0x8];
6065         u8         tisn[0x18];
6066
6067         u8         reserved_3[0x20];
6068 };
6069
6070 struct mlx5_ifc_destroy_tir_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_0[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_1[0x40];
6077 };
6078
6079 struct mlx5_ifc_destroy_tir_in_bits {
6080         u8         opcode[0x10];
6081         u8         reserved_0[0x10];
6082
6083         u8         reserved_1[0x10];
6084         u8         op_mod[0x10];
6085
6086         u8         reserved_2[0x8];
6087         u8         tirn[0x18];
6088
6089         u8         reserved_3[0x20];
6090 };
6091
6092 struct mlx5_ifc_destroy_srq_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_0[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_1[0x40];
6099 };
6100
6101 struct mlx5_ifc_destroy_srq_in_bits {
6102         u8         opcode[0x10];
6103         u8         reserved_0[0x10];
6104
6105         u8         reserved_1[0x10];
6106         u8         op_mod[0x10];
6107
6108         u8         reserved_2[0x8];
6109         u8         srqn[0x18];
6110
6111         u8         reserved_3[0x20];
6112 };
6113
6114 struct mlx5_ifc_destroy_sq_out_bits {
6115         u8         status[0x8];
6116         u8         reserved_0[0x18];
6117
6118         u8         syndrome[0x20];
6119
6120         u8         reserved_1[0x40];
6121 };
6122
6123 struct mlx5_ifc_destroy_sq_in_bits {
6124         u8         opcode[0x10];
6125         u8         reserved_0[0x10];
6126
6127         u8         reserved_1[0x10];
6128         u8         op_mod[0x10];
6129
6130         u8         reserved_2[0x8];
6131         u8         sqn[0x18];
6132
6133         u8         reserved_3[0x20];
6134 };
6135
6136 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6137         u8         status[0x8];
6138         u8         reserved_at_8[0x18];
6139
6140         u8         syndrome[0x20];
6141
6142         u8         reserved_at_40[0x1c0];
6143 };
6144
6145 enum {
6146         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6147 };
6148
6149 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6150         u8         opcode[0x10];
6151         u8         reserved_at_10[0x10];
6152
6153         u8         reserved_at_20[0x10];
6154         u8         op_mod[0x10];
6155
6156         u8         scheduling_hierarchy[0x8];
6157         u8         reserved_at_48[0x18];
6158
6159         u8         scheduling_element_id[0x20];
6160
6161         u8         reserved_at_80[0x180];
6162 };
6163
6164 struct mlx5_ifc_destroy_rqt_out_bits {
6165         u8         status[0x8];
6166         u8         reserved_0[0x18];
6167
6168         u8         syndrome[0x20];
6169
6170         u8         reserved_1[0x40];
6171 };
6172
6173 struct mlx5_ifc_destroy_rqt_in_bits {
6174         u8         opcode[0x10];
6175         u8         reserved_0[0x10];
6176
6177         u8         reserved_1[0x10];
6178         u8         op_mod[0x10];
6179
6180         u8         reserved_2[0x8];
6181         u8         rqtn[0x18];
6182
6183         u8         reserved_3[0x20];
6184 };
6185
6186 struct mlx5_ifc_destroy_rq_out_bits {
6187         u8         status[0x8];
6188         u8         reserved_0[0x18];
6189
6190         u8         syndrome[0x20];
6191
6192         u8         reserved_1[0x40];
6193 };
6194
6195 struct mlx5_ifc_destroy_rq_in_bits {
6196         u8         opcode[0x10];
6197         u8         reserved_0[0x10];
6198
6199         u8         reserved_1[0x10];
6200         u8         op_mod[0x10];
6201
6202         u8         reserved_2[0x8];
6203         u8         rqn[0x18];
6204
6205         u8         reserved_3[0x20];
6206 };
6207
6208 struct mlx5_ifc_destroy_rmp_out_bits {
6209         u8         status[0x8];
6210         u8         reserved_0[0x18];
6211
6212         u8         syndrome[0x20];
6213
6214         u8         reserved_1[0x40];
6215 };
6216
6217 struct mlx5_ifc_destroy_rmp_in_bits {
6218         u8         opcode[0x10];
6219         u8         reserved_0[0x10];
6220
6221         u8         reserved_1[0x10];
6222         u8         op_mod[0x10];
6223
6224         u8         reserved_2[0x8];
6225         u8         rmpn[0x18];
6226
6227         u8         reserved_3[0x20];
6228 };
6229
6230 struct mlx5_ifc_destroy_qp_out_bits {
6231         u8         status[0x8];
6232         u8         reserved_0[0x18];
6233
6234         u8         syndrome[0x20];
6235
6236         u8         reserved_1[0x40];
6237 };
6238
6239 struct mlx5_ifc_destroy_qp_in_bits {
6240         u8         opcode[0x10];
6241         u8         reserved_0[0x10];
6242
6243         u8         reserved_1[0x10];
6244         u8         op_mod[0x10];
6245
6246         u8         reserved_2[0x8];
6247         u8         qpn[0x18];
6248
6249         u8         reserved_3[0x20];
6250 };
6251
6252 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6253         u8         status[0x8];
6254         u8         reserved_at_8[0x18];
6255
6256         u8         syndrome[0x20];
6257
6258         u8         reserved_at_40[0x1c0];
6259 };
6260
6261 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6262         u8         opcode[0x10];
6263         u8         reserved_at_10[0x10];
6264
6265         u8         reserved_at_20[0x10];
6266         u8         op_mod[0x10];
6267
6268         u8         reserved_at_40[0x20];
6269
6270         u8         reserved_at_60[0x10];
6271         u8         qos_para_vport_number[0x10];
6272
6273         u8         reserved_at_80[0x180];
6274 };
6275
6276 struct mlx5_ifc_destroy_psv_out_bits {
6277         u8         status[0x8];
6278         u8         reserved_0[0x18];
6279
6280         u8         syndrome[0x20];
6281
6282         u8         reserved_1[0x40];
6283 };
6284
6285 struct mlx5_ifc_destroy_psv_in_bits {
6286         u8         opcode[0x10];
6287         u8         reserved_0[0x10];
6288
6289         u8         reserved_1[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         reserved_2[0x8];
6293         u8         psvn[0x18];
6294
6295         u8         reserved_3[0x20];
6296 };
6297
6298 struct mlx5_ifc_destroy_mkey_out_bits {
6299         u8         status[0x8];
6300         u8         reserved_0[0x18];
6301
6302         u8         syndrome[0x20];
6303
6304         u8         reserved_1[0x40];
6305 };
6306
6307 struct mlx5_ifc_destroy_mkey_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_0[0x10];
6310
6311         u8         reserved_1[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         reserved_2[0x8];
6315         u8         mkey_index[0x18];
6316
6317         u8         reserved_3[0x20];
6318 };
6319
6320 struct mlx5_ifc_destroy_flow_table_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_0[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_1[0x40];
6327 };
6328
6329 struct mlx5_ifc_destroy_flow_table_in_bits {
6330         u8         opcode[0x10];
6331         u8         reserved_0[0x10];
6332
6333         u8         reserved_1[0x10];
6334         u8         op_mod[0x10];
6335
6336         u8         other_vport[0x1];
6337         u8         reserved_2[0xf];
6338         u8         vport_number[0x10];
6339
6340         u8         reserved_3[0x20];
6341
6342         u8         table_type[0x8];
6343         u8         reserved_4[0x18];
6344
6345         u8         reserved_5[0x8];
6346         u8         table_id[0x18];
6347
6348         u8         reserved_6[0x140];
6349 };
6350
6351 struct mlx5_ifc_destroy_flow_group_out_bits {
6352         u8         status[0x8];
6353         u8         reserved_0[0x18];
6354
6355         u8         syndrome[0x20];
6356
6357         u8         reserved_1[0x40];
6358 };
6359
6360 struct mlx5_ifc_destroy_flow_group_in_bits {
6361         u8         opcode[0x10];
6362         u8         reserved_0[0x10];
6363
6364         u8         reserved_1[0x10];
6365         u8         op_mod[0x10];
6366
6367         u8         other_vport[0x1];
6368         u8         reserved_2[0xf];
6369         u8         vport_number[0x10];
6370
6371         u8         reserved_3[0x20];
6372
6373         u8         table_type[0x8];
6374         u8         reserved_4[0x18];
6375
6376         u8         reserved_5[0x8];
6377         u8         table_id[0x18];
6378
6379         u8         group_id[0x20];
6380
6381         u8         reserved_6[0x120];
6382 };
6383
6384 struct mlx5_ifc_destroy_eq_out_bits {
6385         u8         status[0x8];
6386         u8         reserved_0[0x18];
6387
6388         u8         syndrome[0x20];
6389
6390         u8         reserved_1[0x40];
6391 };
6392
6393 struct mlx5_ifc_destroy_eq_in_bits {
6394         u8         opcode[0x10];
6395         u8         reserved_0[0x10];
6396
6397         u8         reserved_1[0x10];
6398         u8         op_mod[0x10];
6399
6400         u8         reserved_2[0x18];
6401         u8         eq_number[0x8];
6402
6403         u8         reserved_3[0x20];
6404 };
6405
6406 struct mlx5_ifc_destroy_dct_out_bits {
6407         u8         status[0x8];
6408         u8         reserved_0[0x18];
6409
6410         u8         syndrome[0x20];
6411
6412         u8         reserved_1[0x40];
6413 };
6414
6415 struct mlx5_ifc_destroy_dct_in_bits {
6416         u8         opcode[0x10];
6417         u8         reserved_0[0x10];
6418
6419         u8         reserved_1[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_2[0x8];
6423         u8         dctn[0x18];
6424
6425         u8         reserved_3[0x20];
6426 };
6427
6428 struct mlx5_ifc_destroy_cq_out_bits {
6429         u8         status[0x8];
6430         u8         reserved_0[0x18];
6431
6432         u8         syndrome[0x20];
6433
6434         u8         reserved_1[0x40];
6435 };
6436
6437 struct mlx5_ifc_destroy_cq_in_bits {
6438         u8         opcode[0x10];
6439         u8         reserved_0[0x10];
6440
6441         u8         reserved_1[0x10];
6442         u8         op_mod[0x10];
6443
6444         u8         reserved_2[0x8];
6445         u8         cqn[0x18];
6446
6447         u8         reserved_3[0x20];
6448 };
6449
6450 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6451         u8         status[0x8];
6452         u8         reserved_0[0x18];
6453
6454         u8         syndrome[0x20];
6455
6456         u8         reserved_1[0x40];
6457 };
6458
6459 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6460         u8         opcode[0x10];
6461         u8         reserved_0[0x10];
6462
6463         u8         reserved_1[0x10];
6464         u8         op_mod[0x10];
6465
6466         u8         reserved_2[0x20];
6467
6468         u8         reserved_3[0x10];
6469         u8         vxlan_udp_port[0x10];
6470 };
6471
6472 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6473         u8         status[0x8];
6474         u8         reserved_0[0x18];
6475
6476         u8         syndrome[0x20];
6477
6478         u8         reserved_1[0x40];
6479 };
6480
6481 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6482         u8         opcode[0x10];
6483         u8         reserved_0[0x10];
6484
6485         u8         reserved_1[0x10];
6486         u8         op_mod[0x10];
6487
6488         u8         reserved_2[0x60];
6489
6490         u8         reserved_3[0x8];
6491         u8         table_index[0x18];
6492
6493         u8         reserved_4[0x140];
6494 };
6495
6496 struct mlx5_ifc_delete_fte_out_bits {
6497         u8         status[0x8];
6498         u8         reserved_0[0x18];
6499
6500         u8         syndrome[0x20];
6501
6502         u8         reserved_1[0x40];
6503 };
6504
6505 struct mlx5_ifc_delete_fte_in_bits {
6506         u8         opcode[0x10];
6507         u8         reserved_0[0x10];
6508
6509         u8         reserved_1[0x10];
6510         u8         op_mod[0x10];
6511
6512         u8         other_vport[0x1];
6513         u8         reserved_2[0xf];
6514         u8         vport_number[0x10];
6515
6516         u8         reserved_3[0x20];
6517
6518         u8         table_type[0x8];
6519         u8         reserved_4[0x18];
6520
6521         u8         reserved_5[0x8];
6522         u8         table_id[0x18];
6523
6524         u8         reserved_6[0x40];
6525
6526         u8         flow_index[0x20];
6527
6528         u8         reserved_7[0xe0];
6529 };
6530
6531 struct mlx5_ifc_dealloc_xrcd_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_0[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_1[0x40];
6538 };
6539
6540 struct mlx5_ifc_dealloc_xrcd_in_bits {
6541         u8         opcode[0x10];
6542         u8         reserved_0[0x10];
6543
6544         u8         reserved_1[0x10];
6545         u8         op_mod[0x10];
6546
6547         u8         reserved_2[0x8];
6548         u8         xrcd[0x18];
6549
6550         u8         reserved_3[0x20];
6551 };
6552
6553 struct mlx5_ifc_dealloc_uar_out_bits {
6554         u8         status[0x8];
6555         u8         reserved_0[0x18];
6556
6557         u8         syndrome[0x20];
6558
6559         u8         reserved_1[0x40];
6560 };
6561
6562 struct mlx5_ifc_dealloc_uar_in_bits {
6563         u8         opcode[0x10];
6564         u8         reserved_0[0x10];
6565
6566         u8         reserved_1[0x10];
6567         u8         op_mod[0x10];
6568
6569         u8         reserved_2[0x8];
6570         u8         uar[0x18];
6571
6572         u8         reserved_3[0x20];
6573 };
6574
6575 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6576         u8         status[0x8];
6577         u8         reserved_0[0x18];
6578
6579         u8         syndrome[0x20];
6580
6581         u8         reserved_1[0x40];
6582 };
6583
6584 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6585         u8         opcode[0x10];
6586         u8         reserved_0[0x10];
6587
6588         u8         reserved_1[0x10];
6589         u8         op_mod[0x10];
6590
6591         u8         reserved_2[0x8];
6592         u8         transport_domain[0x18];
6593
6594         u8         reserved_3[0x20];
6595 };
6596
6597 struct mlx5_ifc_dealloc_q_counter_out_bits {
6598         u8         status[0x8];
6599         u8         reserved_0[0x18];
6600
6601         u8         syndrome[0x20];
6602
6603         u8         reserved_1[0x40];
6604 };
6605
6606 struct mlx5_ifc_counter_id_bits {
6607         u8         reserved[0x10];
6608         u8         counter_id[0x10];
6609 };
6610
6611 struct mlx5_ifc_diagnostic_params_context_bits {
6612         u8         num_of_counters[0x10];
6613         u8         reserved_2[0x8];
6614         u8         log_num_of_samples[0x8];
6615
6616         u8         single[0x1];
6617         u8         repetitive[0x1];
6618         u8         sync[0x1];
6619         u8         clear[0x1];
6620         u8         on_demand[0x1];
6621         u8         enable[0x1];
6622         u8         reserved_3[0x12];
6623         u8         log_sample_period[0x8];
6624
6625         u8         reserved_4[0x80];
6626
6627         struct mlx5_ifc_counter_id_bits counter_id[0];
6628 };
6629
6630 struct mlx5_ifc_set_diagnostic_params_in_bits {
6631         u8         opcode[0x10];
6632         u8         reserved_0[0x10];
6633
6634         u8         reserved_1[0x10];
6635         u8         op_mod[0x10];
6636
6637         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6638 };
6639
6640 struct mlx5_ifc_set_diagnostic_params_out_bits {
6641         u8         status[0x8];
6642         u8         reserved_0[0x18];
6643
6644         u8         syndrome[0x20];
6645
6646         u8         reserved_1[0x40];
6647 };
6648
6649 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6650         u8         opcode[0x10];
6651         u8         reserved_0[0x10];
6652
6653         u8         reserved_1[0x10];
6654         u8         op_mod[0x10];
6655
6656         u8         num_of_samples[0x10];
6657         u8         sample_index[0x10];
6658
6659         u8         reserved_2[0x20];
6660 };
6661
6662 struct mlx5_ifc_diagnostic_counter_bits {
6663         u8         counter_id[0x10];
6664         u8         sample_id[0x10];
6665
6666         u8         time_stamp_31_0[0x20];
6667
6668         u8         counter_value_h[0x20];
6669
6670         u8         counter_value_l[0x20];
6671 };
6672
6673 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6674         u8         status[0x8];
6675         u8         reserved_0[0x18];
6676
6677         u8         syndrome[0x20];
6678
6679         u8         reserved_1[0x40];
6680
6681         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6682 };
6683
6684 struct mlx5_ifc_dealloc_q_counter_in_bits {
6685         u8         opcode[0x10];
6686         u8         reserved_0[0x10];
6687
6688         u8         reserved_1[0x10];
6689         u8         op_mod[0x10];
6690
6691         u8         reserved_2[0x18];
6692         u8         counter_set_id[0x8];
6693
6694         u8         reserved_3[0x20];
6695 };
6696
6697 struct mlx5_ifc_dealloc_pd_out_bits {
6698         u8         status[0x8];
6699         u8         reserved_0[0x18];
6700
6701         u8         syndrome[0x20];
6702
6703         u8         reserved_1[0x40];
6704 };
6705
6706 struct mlx5_ifc_dealloc_pd_in_bits {
6707         u8         opcode[0x10];
6708         u8         reserved_0[0x10];
6709
6710         u8         reserved_1[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         reserved_2[0x8];
6714         u8         pd[0x18];
6715
6716         u8         reserved_3[0x20];
6717 };
6718
6719 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6720         u8         status[0x8];
6721         u8         reserved_0[0x18];
6722
6723         u8         syndrome[0x20];
6724
6725         u8         reserved_1[0x40];
6726 };
6727
6728 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6729         u8         opcode[0x10];
6730         u8         reserved_0[0x10];
6731
6732         u8         reserved_1[0x10];
6733         u8         op_mod[0x10];
6734
6735         u8         reserved_2[0x10];
6736         u8         flow_counter_id[0x10];
6737
6738         u8         reserved_3[0x20];
6739 };
6740
6741 struct mlx5_ifc_deactivate_tracer_out_bits {
6742         u8         status[0x8];
6743         u8         reserved_0[0x18];
6744
6745         u8         syndrome[0x20];
6746
6747         u8         reserved_1[0x40];
6748 };
6749
6750 struct mlx5_ifc_deactivate_tracer_in_bits {
6751         u8         opcode[0x10];
6752         u8         reserved_0[0x10];
6753
6754         u8         reserved_1[0x10];
6755         u8         op_mod[0x10];
6756
6757         u8         mkey[0x20];
6758
6759         u8         reserved_2[0x20];
6760 };
6761
6762 struct mlx5_ifc_create_xrc_srq_out_bits {
6763         u8         status[0x8];
6764         u8         reserved_0[0x18];
6765
6766         u8         syndrome[0x20];
6767
6768         u8         reserved_1[0x8];
6769         u8         xrc_srqn[0x18];
6770
6771         u8         reserved_2[0x20];
6772 };
6773
6774 struct mlx5_ifc_create_xrc_srq_in_bits {
6775         u8         opcode[0x10];
6776         u8         reserved_0[0x10];
6777
6778         u8         reserved_1[0x10];
6779         u8         op_mod[0x10];
6780
6781         u8         reserved_2[0x40];
6782
6783         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6784
6785         u8         reserved_3[0x600];
6786
6787         u8         pas[0][0x40];
6788 };
6789
6790 struct mlx5_ifc_create_tis_out_bits {
6791         u8         status[0x8];
6792         u8         reserved_0[0x18];
6793
6794         u8         syndrome[0x20];
6795
6796         u8         reserved_1[0x8];
6797         u8         tisn[0x18];
6798
6799         u8         reserved_2[0x20];
6800 };
6801
6802 struct mlx5_ifc_create_tis_in_bits {
6803         u8         opcode[0x10];
6804         u8         reserved_0[0x10];
6805
6806         u8         reserved_1[0x10];
6807         u8         op_mod[0x10];
6808
6809         u8         reserved_2[0xc0];
6810
6811         struct mlx5_ifc_tisc_bits ctx;
6812 };
6813
6814 struct mlx5_ifc_create_tir_out_bits {
6815         u8         status[0x8];
6816         u8         reserved_0[0x18];
6817
6818         u8         syndrome[0x20];
6819
6820         u8         reserved_1[0x8];
6821         u8         tirn[0x18];
6822
6823         u8         reserved_2[0x20];
6824 };
6825
6826 struct mlx5_ifc_create_tir_in_bits {
6827         u8         opcode[0x10];
6828         u8         reserved_0[0x10];
6829
6830         u8         reserved_1[0x10];
6831         u8         op_mod[0x10];
6832
6833         u8         reserved_2[0xc0];
6834
6835         struct mlx5_ifc_tirc_bits tir_context;
6836 };
6837
6838 struct mlx5_ifc_create_srq_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_0[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_1[0x8];
6845         u8         srqn[0x18];
6846
6847         u8         reserved_2[0x20];
6848 };
6849
6850 struct mlx5_ifc_create_srq_in_bits {
6851         u8         opcode[0x10];
6852         u8         reserved_0[0x10];
6853
6854         u8         reserved_1[0x10];
6855         u8         op_mod[0x10];
6856
6857         u8         reserved_2[0x40];
6858
6859         struct mlx5_ifc_srqc_bits srq_context_entry;
6860
6861         u8         reserved_3[0x600];
6862
6863         u8         pas[0][0x40];
6864 };
6865
6866 struct mlx5_ifc_create_sq_out_bits {
6867         u8         status[0x8];
6868         u8         reserved_0[0x18];
6869
6870         u8         syndrome[0x20];
6871
6872         u8         reserved_1[0x8];
6873         u8         sqn[0x18];
6874
6875         u8         reserved_2[0x20];
6876 };
6877
6878 struct mlx5_ifc_create_sq_in_bits {
6879         u8         opcode[0x10];
6880         u8         reserved_0[0x10];
6881
6882         u8         reserved_1[0x10];
6883         u8         op_mod[0x10];
6884
6885         u8         reserved_2[0xc0];
6886
6887         struct mlx5_ifc_sqc_bits ctx;
6888 };
6889
6890 struct mlx5_ifc_create_scheduling_element_out_bits {
6891         u8         status[0x8];
6892         u8         reserved_at_8[0x18];
6893
6894         u8         syndrome[0x20];
6895
6896         u8         reserved_at_40[0x40];
6897
6898         u8         scheduling_element_id[0x20];
6899
6900         u8         reserved_at_a0[0x160];
6901 };
6902
6903 enum {
6904         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6905 };
6906
6907 struct mlx5_ifc_create_scheduling_element_in_bits {
6908         u8         opcode[0x10];
6909         u8         reserved_at_10[0x10];
6910
6911         u8         reserved_at_20[0x10];
6912         u8         op_mod[0x10];
6913
6914         u8         scheduling_hierarchy[0x8];
6915         u8         reserved_at_48[0x18];
6916
6917         u8         reserved_at_60[0xa0];
6918
6919         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6920
6921         u8         reserved_at_300[0x100];
6922 };
6923
6924 struct mlx5_ifc_create_rqt_out_bits {
6925         u8         status[0x8];
6926         u8         reserved_0[0x18];
6927
6928         u8         syndrome[0x20];
6929
6930         u8         reserved_1[0x8];
6931         u8         rqtn[0x18];
6932
6933         u8         reserved_2[0x20];
6934 };
6935
6936 struct mlx5_ifc_create_rqt_in_bits {
6937         u8         opcode[0x10];
6938         u8         reserved_0[0x10];
6939
6940         u8         reserved_1[0x10];
6941         u8         op_mod[0x10];
6942
6943         u8         reserved_2[0xc0];
6944
6945         struct mlx5_ifc_rqtc_bits rqt_context;
6946 };
6947
6948 struct mlx5_ifc_create_rq_out_bits {
6949         u8         status[0x8];
6950         u8         reserved_0[0x18];
6951
6952         u8         syndrome[0x20];
6953
6954         u8         reserved_1[0x8];
6955         u8         rqn[0x18];
6956
6957         u8         reserved_2[0x20];
6958 };
6959
6960 struct mlx5_ifc_create_rq_in_bits {
6961         u8         opcode[0x10];
6962         u8         reserved_0[0x10];
6963
6964         u8         reserved_1[0x10];
6965         u8         op_mod[0x10];
6966
6967         u8         reserved_2[0xc0];
6968
6969         struct mlx5_ifc_rqc_bits ctx;
6970 };
6971
6972 struct mlx5_ifc_create_rmp_out_bits {
6973         u8         status[0x8];
6974         u8         reserved_0[0x18];
6975
6976         u8         syndrome[0x20];
6977
6978         u8         reserved_1[0x8];
6979         u8         rmpn[0x18];
6980
6981         u8         reserved_2[0x20];
6982 };
6983
6984 struct mlx5_ifc_create_rmp_in_bits {
6985         u8         opcode[0x10];
6986         u8         reserved_0[0x10];
6987
6988         u8         reserved_1[0x10];
6989         u8         op_mod[0x10];
6990
6991         u8         reserved_2[0xc0];
6992
6993         struct mlx5_ifc_rmpc_bits ctx;
6994 };
6995
6996 struct mlx5_ifc_create_qp_out_bits {
6997         u8         status[0x8];
6998         u8         reserved_0[0x18];
6999
7000         u8         syndrome[0x20];
7001
7002         u8         reserved_1[0x8];
7003         u8         qpn[0x18];
7004
7005         u8         reserved_2[0x20];
7006 };
7007
7008 struct mlx5_ifc_create_qp_in_bits {
7009         u8         opcode[0x10];
7010         u8         reserved_0[0x10];
7011
7012         u8         reserved_1[0x10];
7013         u8         op_mod[0x10];
7014
7015         u8         reserved_2[0x8];
7016         u8         input_qpn[0x18];
7017
7018         u8         reserved_3[0x20];
7019
7020         u8         opt_param_mask[0x20];
7021
7022         u8         reserved_4[0x20];
7023
7024         struct mlx5_ifc_qpc_bits qpc;
7025
7026         u8         reserved_5[0x80];
7027
7028         u8         pas[0][0x40];
7029 };
7030
7031 struct mlx5_ifc_create_qos_para_vport_out_bits {
7032         u8         status[0x8];
7033         u8         reserved_at_8[0x18];
7034
7035         u8         syndrome[0x20];
7036
7037         u8         reserved_at_40[0x20];
7038
7039         u8         reserved_at_60[0x10];
7040         u8         qos_para_vport_number[0x10];
7041
7042         u8         reserved_at_80[0x180];
7043 };
7044
7045 struct mlx5_ifc_create_qos_para_vport_in_bits {
7046         u8         opcode[0x10];
7047         u8         reserved_at_10[0x10];
7048
7049         u8         reserved_at_20[0x10];
7050         u8         op_mod[0x10];
7051
7052         u8         reserved_at_40[0x1c0];
7053 };
7054
7055 struct mlx5_ifc_create_psv_out_bits {
7056         u8         status[0x8];
7057         u8         reserved_0[0x18];
7058
7059         u8         syndrome[0x20];
7060
7061         u8         reserved_1[0x40];
7062
7063         u8         reserved_2[0x8];
7064         u8         psv0_index[0x18];
7065
7066         u8         reserved_3[0x8];
7067         u8         psv1_index[0x18];
7068
7069         u8         reserved_4[0x8];
7070         u8         psv2_index[0x18];
7071
7072         u8         reserved_5[0x8];
7073         u8         psv3_index[0x18];
7074 };
7075
7076 struct mlx5_ifc_create_psv_in_bits {
7077         u8         opcode[0x10];
7078         u8         reserved_0[0x10];
7079
7080         u8         reserved_1[0x10];
7081         u8         op_mod[0x10];
7082
7083         u8         num_psv[0x4];
7084         u8         reserved_2[0x4];
7085         u8         pd[0x18];
7086
7087         u8         reserved_3[0x20];
7088 };
7089
7090 struct mlx5_ifc_create_mkey_out_bits {
7091         u8         status[0x8];
7092         u8         reserved_0[0x18];
7093
7094         u8         syndrome[0x20];
7095
7096         u8         reserved_1[0x8];
7097         u8         mkey_index[0x18];
7098
7099         u8         reserved_2[0x20];
7100 };
7101
7102 struct mlx5_ifc_create_mkey_in_bits {
7103         u8         opcode[0x10];
7104         u8         reserved_0[0x10];
7105
7106         u8         reserved_1[0x10];
7107         u8         op_mod[0x10];
7108
7109         u8         reserved_2[0x20];
7110
7111         u8         pg_access[0x1];
7112         u8         reserved_3[0x1f];
7113
7114         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7115
7116         u8         reserved_4[0x80];
7117
7118         u8         translations_octword_actual_size[0x20];
7119
7120         u8         reserved_5[0x560];
7121
7122         u8         klm_pas_mtt[0][0x20];
7123 };
7124
7125 struct mlx5_ifc_create_flow_table_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_0[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_1[0x8];
7132         u8         table_id[0x18];
7133
7134         u8         reserved_2[0x20];
7135 };
7136
7137 struct mlx5_ifc_create_flow_table_in_bits {
7138         u8         opcode[0x10];
7139         u8         reserved_at_10[0x10];
7140
7141         u8         reserved_at_20[0x10];
7142         u8         op_mod[0x10];
7143
7144         u8         other_vport[0x1];
7145         u8         reserved_at_41[0xf];
7146         u8         vport_number[0x10];
7147
7148         u8         reserved_at_60[0x20];
7149
7150         u8         table_type[0x8];
7151         u8         reserved_at_88[0x18];
7152
7153         u8         reserved_at_a0[0x20];
7154
7155         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7156 };
7157
7158 struct mlx5_ifc_create_flow_group_out_bits {
7159         u8         status[0x8];
7160         u8         reserved_0[0x18];
7161
7162         u8         syndrome[0x20];
7163
7164         u8         reserved_1[0x8];
7165         u8         group_id[0x18];
7166
7167         u8         reserved_2[0x20];
7168 };
7169
7170 enum {
7171         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7172         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7173         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7174 };
7175
7176 struct mlx5_ifc_create_flow_group_in_bits {
7177         u8         opcode[0x10];
7178         u8         reserved_0[0x10];
7179
7180         u8         reserved_1[0x10];
7181         u8         op_mod[0x10];
7182
7183         u8         other_vport[0x1];
7184         u8         reserved_2[0xf];
7185         u8         vport_number[0x10];
7186
7187         u8         reserved_3[0x20];
7188
7189         u8         table_type[0x8];
7190         u8         reserved_4[0x18];
7191
7192         u8         reserved_5[0x8];
7193         u8         table_id[0x18];
7194
7195         u8         reserved_6[0x20];
7196
7197         u8         start_flow_index[0x20];
7198
7199         u8         reserved_7[0x20];
7200
7201         u8         end_flow_index[0x20];
7202
7203         u8         reserved_8[0xa0];
7204
7205         u8         reserved_9[0x18];
7206         u8         match_criteria_enable[0x8];
7207
7208         struct mlx5_ifc_fte_match_param_bits match_criteria;
7209
7210         u8         reserved_10[0xe00];
7211 };
7212
7213 struct mlx5_ifc_create_eq_out_bits {
7214         u8         status[0x8];
7215         u8         reserved_0[0x18];
7216
7217         u8         syndrome[0x20];
7218
7219         u8         reserved_1[0x18];
7220         u8         eq_number[0x8];
7221
7222         u8         reserved_2[0x20];
7223 };
7224
7225 struct mlx5_ifc_create_eq_in_bits {
7226         u8         opcode[0x10];
7227         u8         reserved_0[0x10];
7228
7229         u8         reserved_1[0x10];
7230         u8         op_mod[0x10];
7231
7232         u8         reserved_2[0x40];
7233
7234         struct mlx5_ifc_eqc_bits eq_context_entry;
7235
7236         u8         reserved_3[0x40];
7237
7238         u8         event_bitmask[0x40];
7239
7240         u8         reserved_4[0x580];
7241
7242         u8         pas[0][0x40];
7243 };
7244
7245 struct mlx5_ifc_create_dct_out_bits {
7246         u8         status[0x8];
7247         u8         reserved_0[0x18];
7248
7249         u8         syndrome[0x20];
7250
7251         u8         reserved_1[0x8];
7252         u8         dctn[0x18];
7253
7254         u8         reserved_2[0x20];
7255 };
7256
7257 struct mlx5_ifc_create_dct_in_bits {
7258         u8         opcode[0x10];
7259         u8         reserved_0[0x10];
7260
7261         u8         reserved_1[0x10];
7262         u8         op_mod[0x10];
7263
7264         u8         reserved_2[0x40];
7265
7266         struct mlx5_ifc_dctc_bits dct_context_entry;
7267
7268         u8         reserved_3[0x180];
7269 };
7270
7271 struct mlx5_ifc_create_cq_out_bits {
7272         u8         status[0x8];
7273         u8         reserved_0[0x18];
7274
7275         u8         syndrome[0x20];
7276
7277         u8         reserved_1[0x8];
7278         u8         cqn[0x18];
7279
7280         u8         reserved_2[0x20];
7281 };
7282
7283 struct mlx5_ifc_create_cq_in_bits {
7284         u8         opcode[0x10];
7285         u8         reserved_0[0x10];
7286
7287         u8         reserved_1[0x10];
7288         u8         op_mod[0x10];
7289
7290         u8         reserved_2[0x40];
7291
7292         struct mlx5_ifc_cqc_bits cq_context;
7293
7294         u8         reserved_3[0x600];
7295
7296         u8         pas[0][0x40];
7297 };
7298
7299 struct mlx5_ifc_config_int_moderation_out_bits {
7300         u8         status[0x8];
7301         u8         reserved_0[0x18];
7302
7303         u8         syndrome[0x20];
7304
7305         u8         reserved_1[0x4];
7306         u8         min_delay[0xc];
7307         u8         int_vector[0x10];
7308
7309         u8         reserved_2[0x20];
7310 };
7311
7312 enum {
7313         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7314         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7315 };
7316
7317 struct mlx5_ifc_config_int_moderation_in_bits {
7318         u8         opcode[0x10];
7319         u8         reserved_0[0x10];
7320
7321         u8         reserved_1[0x10];
7322         u8         op_mod[0x10];
7323
7324         u8         reserved_2[0x4];
7325         u8         min_delay[0xc];
7326         u8         int_vector[0x10];
7327
7328         u8         reserved_3[0x20];
7329 };
7330
7331 struct mlx5_ifc_attach_to_mcg_out_bits {
7332         u8         status[0x8];
7333         u8         reserved_0[0x18];
7334
7335         u8         syndrome[0x20];
7336
7337         u8         reserved_1[0x40];
7338 };
7339
7340 struct mlx5_ifc_attach_to_mcg_in_bits {
7341         u8         opcode[0x10];
7342         u8         reserved_0[0x10];
7343
7344         u8         reserved_1[0x10];
7345         u8         op_mod[0x10];
7346
7347         u8         reserved_2[0x8];
7348         u8         qpn[0x18];
7349
7350         u8         reserved_3[0x20];
7351
7352         u8         multicast_gid[16][0x8];
7353 };
7354
7355 struct mlx5_ifc_arm_xrc_srq_out_bits {
7356         u8         status[0x8];
7357         u8         reserved_0[0x18];
7358
7359         u8         syndrome[0x20];
7360
7361         u8         reserved_1[0x40];
7362 };
7363
7364 enum {
7365         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7366 };
7367
7368 struct mlx5_ifc_arm_xrc_srq_in_bits {
7369         u8         opcode[0x10];
7370         u8         reserved_0[0x10];
7371
7372         u8         reserved_1[0x10];
7373         u8         op_mod[0x10];
7374
7375         u8         reserved_2[0x8];
7376         u8         xrc_srqn[0x18];
7377
7378         u8         reserved_3[0x10];
7379         u8         lwm[0x10];
7380 };
7381
7382 struct mlx5_ifc_arm_rq_out_bits {
7383         u8         status[0x8];
7384         u8         reserved_0[0x18];
7385
7386         u8         syndrome[0x20];
7387
7388         u8         reserved_1[0x40];
7389 };
7390
7391 enum {
7392         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7393 };
7394
7395 struct mlx5_ifc_arm_rq_in_bits {
7396         u8         opcode[0x10];
7397         u8         reserved_0[0x10];
7398
7399         u8         reserved_1[0x10];
7400         u8         op_mod[0x10];
7401
7402         u8         reserved_2[0x8];
7403         u8         srq_number[0x18];
7404
7405         u8         reserved_3[0x10];
7406         u8         lwm[0x10];
7407 };
7408
7409 struct mlx5_ifc_arm_dct_out_bits {
7410         u8         status[0x8];
7411         u8         reserved_0[0x18];
7412
7413         u8         syndrome[0x20];
7414
7415         u8         reserved_1[0x40];
7416 };
7417
7418 struct mlx5_ifc_arm_dct_in_bits {
7419         u8         opcode[0x10];
7420         u8         reserved_0[0x10];
7421
7422         u8         reserved_1[0x10];
7423         u8         op_mod[0x10];
7424
7425         u8         reserved_2[0x8];
7426         u8         dctn[0x18];
7427
7428         u8         reserved_3[0x20];
7429 };
7430
7431 struct mlx5_ifc_alloc_xrcd_out_bits {
7432         u8         status[0x8];
7433         u8         reserved_0[0x18];
7434
7435         u8         syndrome[0x20];
7436
7437         u8         reserved_1[0x8];
7438         u8         xrcd[0x18];
7439
7440         u8         reserved_2[0x20];
7441 };
7442
7443 struct mlx5_ifc_alloc_xrcd_in_bits {
7444         u8         opcode[0x10];
7445         u8         reserved_0[0x10];
7446
7447         u8         reserved_1[0x10];
7448         u8         op_mod[0x10];
7449
7450         u8         reserved_2[0x40];
7451 };
7452
7453 struct mlx5_ifc_alloc_uar_out_bits {
7454         u8         status[0x8];
7455         u8         reserved_0[0x18];
7456
7457         u8         syndrome[0x20];
7458
7459         u8         reserved_1[0x8];
7460         u8         uar[0x18];
7461
7462         u8         reserved_2[0x20];
7463 };
7464
7465 struct mlx5_ifc_alloc_uar_in_bits {
7466         u8         opcode[0x10];
7467         u8         reserved_0[0x10];
7468
7469         u8         reserved_1[0x10];
7470         u8         op_mod[0x10];
7471
7472         u8         reserved_2[0x40];
7473 };
7474
7475 struct mlx5_ifc_alloc_transport_domain_out_bits {
7476         u8         status[0x8];
7477         u8         reserved_0[0x18];
7478
7479         u8         syndrome[0x20];
7480
7481         u8         reserved_1[0x8];
7482         u8         transport_domain[0x18];
7483
7484         u8         reserved_2[0x20];
7485 };
7486
7487 struct mlx5_ifc_alloc_transport_domain_in_bits {
7488         u8         opcode[0x10];
7489         u8         reserved_0[0x10];
7490
7491         u8         reserved_1[0x10];
7492         u8         op_mod[0x10];
7493
7494         u8         reserved_2[0x40];
7495 };
7496
7497 struct mlx5_ifc_alloc_q_counter_out_bits {
7498         u8         status[0x8];
7499         u8         reserved_0[0x18];
7500
7501         u8         syndrome[0x20];
7502
7503         u8         reserved_1[0x18];
7504         u8         counter_set_id[0x8];
7505
7506         u8         reserved_2[0x20];
7507 };
7508
7509 struct mlx5_ifc_alloc_q_counter_in_bits {
7510         u8         opcode[0x10];
7511         u8         reserved_0[0x10];
7512
7513         u8         reserved_1[0x10];
7514         u8         op_mod[0x10];
7515
7516         u8         reserved_2[0x40];
7517 };
7518
7519 struct mlx5_ifc_alloc_pd_out_bits {
7520         u8         status[0x8];
7521         u8         reserved_0[0x18];
7522
7523         u8         syndrome[0x20];
7524
7525         u8         reserved_1[0x8];
7526         u8         pd[0x18];
7527
7528         u8         reserved_2[0x20];
7529 };
7530
7531 struct mlx5_ifc_alloc_pd_in_bits {
7532         u8         opcode[0x10];
7533         u8         reserved_0[0x10];
7534
7535         u8         reserved_1[0x10];
7536         u8         op_mod[0x10];
7537
7538         u8         reserved_2[0x40];
7539 };
7540
7541 struct mlx5_ifc_alloc_flow_counter_out_bits {
7542         u8         status[0x8];
7543         u8         reserved_0[0x18];
7544
7545         u8         syndrome[0x20];
7546
7547         u8         reserved_1[0x10];
7548         u8         flow_counter_id[0x10];
7549
7550         u8         reserved_2[0x20];
7551 };
7552
7553 struct mlx5_ifc_alloc_flow_counter_in_bits {
7554         u8         opcode[0x10];
7555         u8         reserved_0[0x10];
7556
7557         u8         reserved_1[0x10];
7558         u8         op_mod[0x10];
7559
7560         u8         reserved_2[0x40];
7561 };
7562
7563 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7564         u8         status[0x8];
7565         u8         reserved_0[0x18];
7566
7567         u8         syndrome[0x20];
7568
7569         u8         reserved_1[0x40];
7570 };
7571
7572 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7573         u8         opcode[0x10];
7574         u8         reserved_0[0x10];
7575
7576         u8         reserved_1[0x10];
7577         u8         op_mod[0x10];
7578
7579         u8         reserved_2[0x20];
7580
7581         u8         reserved_3[0x10];
7582         u8         vxlan_udp_port[0x10];
7583 };
7584
7585 struct mlx5_ifc_activate_tracer_out_bits {
7586         u8         status[0x8];
7587         u8         reserved_0[0x18];
7588
7589         u8         syndrome[0x20];
7590
7591         u8         reserved_1[0x40];
7592 };
7593
7594 struct mlx5_ifc_activate_tracer_in_bits {
7595         u8         opcode[0x10];
7596         u8         reserved_0[0x10];
7597
7598         u8         reserved_1[0x10];
7599         u8         op_mod[0x10];
7600
7601         u8         mkey[0x20];
7602
7603         u8         reserved_2[0x20];
7604 };
7605
7606 struct mlx5_ifc_set_rate_limit_out_bits {
7607         u8         status[0x8];
7608         u8         reserved_at_8[0x18];
7609
7610         u8         syndrome[0x20];
7611
7612         u8         reserved_at_40[0x40];
7613 };
7614
7615 struct mlx5_ifc_set_rate_limit_in_bits {
7616         u8         opcode[0x10];
7617         u8         reserved_at_10[0x10];
7618
7619         u8         reserved_at_20[0x10];
7620         u8         op_mod[0x10];
7621
7622         u8         reserved_at_40[0x10];
7623         u8         rate_limit_index[0x10];
7624
7625         u8         reserved_at_60[0x20];
7626
7627         u8         rate_limit[0x20];
7628         u8         burst_upper_bound[0x20];
7629 };
7630
7631 struct mlx5_ifc_access_register_out_bits {
7632         u8         status[0x8];
7633         u8         reserved_0[0x18];
7634
7635         u8         syndrome[0x20];
7636
7637         u8         reserved_1[0x40];
7638
7639         u8         register_data[0][0x20];
7640 };
7641
7642 enum {
7643         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7644         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7645 };
7646
7647 struct mlx5_ifc_access_register_in_bits {
7648         u8         opcode[0x10];
7649         u8         reserved_0[0x10];
7650
7651         u8         reserved_1[0x10];
7652         u8         op_mod[0x10];
7653
7654         u8         reserved_2[0x10];
7655         u8         register_id[0x10];
7656
7657         u8         argument[0x20];
7658
7659         u8         register_data[0][0x20];
7660 };
7661
7662 struct mlx5_ifc_sltp_reg_bits {
7663         u8         status[0x4];
7664         u8         version[0x4];
7665         u8         local_port[0x8];
7666         u8         pnat[0x2];
7667         u8         reserved_0[0x2];
7668         u8         lane[0x4];
7669         u8         reserved_1[0x8];
7670
7671         u8         reserved_2[0x20];
7672
7673         u8         reserved_3[0x7];
7674         u8         polarity[0x1];
7675         u8         ob_tap0[0x8];
7676         u8         ob_tap1[0x8];
7677         u8         ob_tap2[0x8];
7678
7679         u8         reserved_4[0xc];
7680         u8         ob_preemp_mode[0x4];
7681         u8         ob_reg[0x8];
7682         u8         ob_bias[0x8];
7683
7684         u8         reserved_5[0x20];
7685 };
7686
7687 struct mlx5_ifc_slrp_reg_bits {
7688         u8         status[0x4];
7689         u8         version[0x4];
7690         u8         local_port[0x8];
7691         u8         pnat[0x2];
7692         u8         reserved_0[0x2];
7693         u8         lane[0x4];
7694         u8         reserved_1[0x8];
7695
7696         u8         ib_sel[0x2];
7697         u8         reserved_2[0x11];
7698         u8         dp_sel[0x1];
7699         u8         dp90sel[0x4];
7700         u8         mix90phase[0x8];
7701
7702         u8         ffe_tap0[0x8];
7703         u8         ffe_tap1[0x8];
7704         u8         ffe_tap2[0x8];
7705         u8         ffe_tap3[0x8];
7706
7707         u8         ffe_tap4[0x8];
7708         u8         ffe_tap5[0x8];
7709         u8         ffe_tap6[0x8];
7710         u8         ffe_tap7[0x8];
7711
7712         u8         ffe_tap8[0x8];
7713         u8         mixerbias_tap_amp[0x8];
7714         u8         reserved_3[0x7];
7715         u8         ffe_tap_en[0x9];
7716
7717         u8         ffe_tap_offset0[0x8];
7718         u8         ffe_tap_offset1[0x8];
7719         u8         slicer_offset0[0x10];
7720
7721         u8         mixer_offset0[0x10];
7722         u8         mixer_offset1[0x10];
7723
7724         u8         mixerbgn_inp[0x8];
7725         u8         mixerbgn_inn[0x8];
7726         u8         mixerbgn_refp[0x8];
7727         u8         mixerbgn_refn[0x8];
7728
7729         u8         sel_slicer_lctrl_h[0x1];
7730         u8         sel_slicer_lctrl_l[0x1];
7731         u8         reserved_4[0x1];
7732         u8         ref_mixer_vreg[0x5];
7733         u8         slicer_gctrl[0x8];
7734         u8         lctrl_input[0x8];
7735         u8         mixer_offset_cm1[0x8];
7736
7737         u8         common_mode[0x6];
7738         u8         reserved_5[0x1];
7739         u8         mixer_offset_cm0[0x9];
7740         u8         reserved_6[0x7];
7741         u8         slicer_offset_cm[0x9];
7742 };
7743
7744 struct mlx5_ifc_slrg_reg_bits {
7745         u8         status[0x4];
7746         u8         version[0x4];
7747         u8         local_port[0x8];
7748         u8         pnat[0x2];
7749         u8         reserved_0[0x2];
7750         u8         lane[0x4];
7751         u8         reserved_1[0x8];
7752
7753         u8         time_to_link_up[0x10];
7754         u8         reserved_2[0xc];
7755         u8         grade_lane_speed[0x4];
7756
7757         u8         grade_version[0x8];
7758         u8         grade[0x18];
7759
7760         u8         reserved_3[0x4];
7761         u8         height_grade_type[0x4];
7762         u8         height_grade[0x18];
7763
7764         u8         height_dz[0x10];
7765         u8         height_dv[0x10];
7766
7767         u8         reserved_4[0x10];
7768         u8         height_sigma[0x10];
7769
7770         u8         reserved_5[0x20];
7771
7772         u8         reserved_6[0x4];
7773         u8         phase_grade_type[0x4];
7774         u8         phase_grade[0x18];
7775
7776         u8         reserved_7[0x8];
7777         u8         phase_eo_pos[0x8];
7778         u8         reserved_8[0x8];
7779         u8         phase_eo_neg[0x8];
7780
7781         u8         ffe_set_tested[0x10];
7782         u8         test_errors_per_lane[0x10];
7783 };
7784
7785 struct mlx5_ifc_pvlc_reg_bits {
7786         u8         reserved_0[0x8];
7787         u8         local_port[0x8];
7788         u8         reserved_1[0x10];
7789
7790         u8         reserved_2[0x1c];
7791         u8         vl_hw_cap[0x4];
7792
7793         u8         reserved_3[0x1c];
7794         u8         vl_admin[0x4];
7795
7796         u8         reserved_4[0x1c];
7797         u8         vl_operational[0x4];
7798 };
7799
7800 struct mlx5_ifc_pude_reg_bits {
7801         u8         swid[0x8];
7802         u8         local_port[0x8];
7803         u8         reserved_0[0x4];
7804         u8         admin_status[0x4];
7805         u8         reserved_1[0x4];
7806         u8         oper_status[0x4];
7807
7808         u8         reserved_2[0x60];
7809 };
7810
7811 enum {
7812         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7813         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7814 };
7815
7816 struct mlx5_ifc_ptys_reg_bits {
7817         u8         reserved_0[0x1];
7818         u8         an_disable_admin[0x1];
7819         u8         an_disable_cap[0x1];
7820         u8         reserved_1[0x4];
7821         u8         force_tx_aba_param[0x1];
7822         u8         local_port[0x8];
7823         u8         reserved_2[0xd];
7824         u8         proto_mask[0x3];
7825
7826         u8         an_status[0x4];
7827         u8         reserved_3[0xc];
7828         u8         data_rate_oper[0x10];
7829
7830         u8         fc_proto_capability[0x20];
7831
7832         u8         eth_proto_capability[0x20];
7833
7834         u8         ib_link_width_capability[0x10];
7835         u8         ib_proto_capability[0x10];
7836
7837         u8         fc_proto_admin[0x20];
7838
7839         u8         eth_proto_admin[0x20];
7840
7841         u8         ib_link_width_admin[0x10];
7842         u8         ib_proto_admin[0x10];
7843
7844         u8         fc_proto_oper[0x20];
7845
7846         u8         eth_proto_oper[0x20];
7847
7848         u8         ib_link_width_oper[0x10];
7849         u8         ib_proto_oper[0x10];
7850
7851         u8         reserved_4[0x20];
7852
7853         u8         eth_proto_lp_advertise[0x20];
7854
7855         u8         reserved_5[0x60];
7856 };
7857
7858 struct mlx5_ifc_ptas_reg_bits {
7859         u8         reserved_0[0x20];
7860
7861         u8         algorithm_options[0x10];
7862         u8         reserved_1[0x4];
7863         u8         repetitions_mode[0x4];
7864         u8         num_of_repetitions[0x8];
7865
7866         u8         grade_version[0x8];
7867         u8         height_grade_type[0x4];
7868         u8         phase_grade_type[0x4];
7869         u8         height_grade_weight[0x8];
7870         u8         phase_grade_weight[0x8];
7871
7872         u8         gisim_measure_bits[0x10];
7873         u8         adaptive_tap_measure_bits[0x10];
7874
7875         u8         ber_bath_high_error_threshold[0x10];
7876         u8         ber_bath_mid_error_threshold[0x10];
7877
7878         u8         ber_bath_low_error_threshold[0x10];
7879         u8         one_ratio_high_threshold[0x10];
7880
7881         u8         one_ratio_high_mid_threshold[0x10];
7882         u8         one_ratio_low_mid_threshold[0x10];
7883
7884         u8         one_ratio_low_threshold[0x10];
7885         u8         ndeo_error_threshold[0x10];
7886
7887         u8         mixer_offset_step_size[0x10];
7888         u8         reserved_2[0x8];
7889         u8         mix90_phase_for_voltage_bath[0x8];
7890
7891         u8         mixer_offset_start[0x10];
7892         u8         mixer_offset_end[0x10];
7893
7894         u8         reserved_3[0x15];
7895         u8         ber_test_time[0xb];
7896 };
7897
7898 struct mlx5_ifc_pspa_reg_bits {
7899         u8         swid[0x8];
7900         u8         local_port[0x8];
7901         u8         sub_port[0x8];
7902         u8         reserved_0[0x8];
7903
7904         u8         reserved_1[0x20];
7905 };
7906
7907 struct mlx5_ifc_ppsc_reg_bits {
7908         u8         reserved_0[0x8];
7909         u8         local_port[0x8];
7910         u8         reserved_1[0x10];
7911
7912         u8         reserved_2[0x60];
7913
7914         u8         reserved_3[0x1c];
7915         u8         wrps_admin[0x4];
7916
7917         u8         reserved_4[0x1c];
7918         u8         wrps_status[0x4];
7919
7920         u8         up_th_vld[0x1];
7921         u8         down_th_vld[0x1];
7922         u8         reserved_5[0x6];
7923         u8         up_threshold[0x8];
7924         u8         reserved_6[0x8];
7925         u8         down_threshold[0x8];
7926
7927         u8         reserved_7[0x20];
7928
7929         u8         reserved_8[0x1c];
7930         u8         srps_admin[0x4];
7931
7932         u8         reserved_9[0x60];
7933 };
7934
7935 struct mlx5_ifc_pplr_reg_bits {
7936         u8         reserved_0[0x8];
7937         u8         local_port[0x8];
7938         u8         reserved_1[0x10];
7939
7940         u8         reserved_2[0x8];
7941         u8         lb_cap[0x8];
7942         u8         reserved_3[0x8];
7943         u8         lb_en[0x8];
7944 };
7945
7946 struct mlx5_ifc_pplm_reg_bits {
7947         u8         reserved_0[0x8];
7948         u8         local_port[0x8];
7949         u8         reserved_1[0x10];
7950
7951         u8         reserved_2[0x20];
7952
7953         u8         port_profile_mode[0x8];
7954         u8         static_port_profile[0x8];
7955         u8         active_port_profile[0x8];
7956         u8         reserved_3[0x8];
7957
7958         u8         retransmission_active[0x8];
7959         u8         fec_mode_active[0x18];
7960
7961         u8         reserved_4[0x10];
7962         u8         v_100g_fec_override_cap[0x4];
7963         u8         v_50g_fec_override_cap[0x4];
7964         u8         v_25g_fec_override_cap[0x4];
7965         u8         v_10g_40g_fec_override_cap[0x4];
7966
7967         u8         reserved_5[0x10];
7968         u8         v_100g_fec_override_admin[0x4];
7969         u8         v_50g_fec_override_admin[0x4];
7970         u8         v_25g_fec_override_admin[0x4];
7971         u8         v_10g_40g_fec_override_admin[0x4];
7972 };
7973
7974 struct mlx5_ifc_ppll_reg_bits {
7975         u8         num_pll_groups[0x8];
7976         u8         pll_group[0x8];
7977         u8         reserved_0[0x4];
7978         u8         num_plls[0x4];
7979         u8         reserved_1[0x8];
7980
7981         u8         reserved_2[0x1f];
7982         u8         ae[0x1];
7983
7984         u8         pll_status[4][0x40];
7985 };
7986
7987 struct mlx5_ifc_ppad_reg_bits {
7988         u8         reserved_0[0x3];
7989         u8         single_mac[0x1];
7990         u8         reserved_1[0x4];
7991         u8         local_port[0x8];
7992         u8         mac_47_32[0x10];
7993
7994         u8         mac_31_0[0x20];
7995
7996         u8         reserved_2[0x40];
7997 };
7998
7999 struct mlx5_ifc_pmtu_reg_bits {
8000         u8         reserved_0[0x8];
8001         u8         local_port[0x8];
8002         u8         reserved_1[0x10];
8003
8004         u8         max_mtu[0x10];
8005         u8         reserved_2[0x10];
8006
8007         u8         admin_mtu[0x10];
8008         u8         reserved_3[0x10];
8009
8010         u8         oper_mtu[0x10];
8011         u8         reserved_4[0x10];
8012 };
8013
8014 struct mlx5_ifc_pmpr_reg_bits {
8015         u8         reserved_0[0x8];
8016         u8         module[0x8];
8017         u8         reserved_1[0x10];
8018
8019         u8         reserved_2[0x18];
8020         u8         attenuation_5g[0x8];
8021
8022         u8         reserved_3[0x18];
8023         u8         attenuation_7g[0x8];
8024
8025         u8         reserved_4[0x18];
8026         u8         attenuation_12g[0x8];
8027 };
8028
8029 struct mlx5_ifc_pmpe_reg_bits {
8030         u8         reserved_0[0x8];
8031         u8         module[0x8];
8032         u8         reserved_1[0xc];
8033         u8         module_status[0x4];
8034
8035         u8         reserved_2[0x14];
8036         u8         error_type[0x4];
8037         u8         reserved_3[0x8];
8038
8039         u8         reserved_4[0x40];
8040 };
8041
8042 struct mlx5_ifc_pmpc_reg_bits {
8043         u8         module_state_updated[32][0x8];
8044 };
8045
8046 struct mlx5_ifc_pmlpn_reg_bits {
8047         u8         reserved_0[0x4];
8048         u8         mlpn_status[0x4];
8049         u8         local_port[0x8];
8050         u8         reserved_1[0x10];
8051
8052         u8         e[0x1];
8053         u8         reserved_2[0x1f];
8054 };
8055
8056 struct mlx5_ifc_pmlp_reg_bits {
8057         u8         rxtx[0x1];
8058         u8         reserved_0[0x7];
8059         u8         local_port[0x8];
8060         u8         reserved_1[0x8];
8061         u8         width[0x8];
8062
8063         u8         lane0_module_mapping[0x20];
8064
8065         u8         lane1_module_mapping[0x20];
8066
8067         u8         lane2_module_mapping[0x20];
8068
8069         u8         lane3_module_mapping[0x20];
8070
8071         u8         reserved_2[0x160];
8072 };
8073
8074 struct mlx5_ifc_pmaos_reg_bits {
8075         u8         reserved_0[0x8];
8076         u8         module[0x8];
8077         u8         reserved_1[0x4];
8078         u8         admin_status[0x4];
8079         u8         reserved_2[0x4];
8080         u8         oper_status[0x4];
8081
8082         u8         ase[0x1];
8083         u8         ee[0x1];
8084         u8         reserved_3[0x12];
8085         u8         error_type[0x4];
8086         u8         reserved_4[0x6];
8087         u8         e[0x2];
8088
8089         u8         reserved_5[0x40];
8090 };
8091
8092 struct mlx5_ifc_plpc_reg_bits {
8093         u8         reserved_0[0x4];
8094         u8         profile_id[0xc];
8095         u8         reserved_1[0x4];
8096         u8         proto_mask[0x4];
8097         u8         reserved_2[0x8];
8098
8099         u8         reserved_3[0x10];
8100         u8         lane_speed[0x10];
8101
8102         u8         reserved_4[0x17];
8103         u8         lpbf[0x1];
8104         u8         fec_mode_policy[0x8];
8105
8106         u8         retransmission_capability[0x8];
8107         u8         fec_mode_capability[0x18];
8108
8109         u8         retransmission_support_admin[0x8];
8110         u8         fec_mode_support_admin[0x18];
8111
8112         u8         retransmission_request_admin[0x8];
8113         u8         fec_mode_request_admin[0x18];
8114
8115         u8         reserved_5[0x80];
8116 };
8117
8118 struct mlx5_ifc_pll_status_data_bits {
8119         u8         reserved_0[0x1];
8120         u8         lock_cal[0x1];
8121         u8         lock_status[0x2];
8122         u8         reserved_1[0x2];
8123         u8         algo_f_ctrl[0xa];
8124         u8         analog_algo_num_var[0x6];
8125         u8         f_ctrl_measure[0xa];
8126
8127         u8         reserved_2[0x2];
8128         u8         analog_var[0x6];
8129         u8         reserved_3[0x2];
8130         u8         high_var[0x6];
8131         u8         reserved_4[0x2];
8132         u8         low_var[0x6];
8133         u8         reserved_5[0x2];
8134         u8         mid_val[0x6];
8135 };
8136
8137 struct mlx5_ifc_plib_reg_bits {
8138         u8         reserved_0[0x8];
8139         u8         local_port[0x8];
8140         u8         reserved_1[0x8];
8141         u8         ib_port[0x8];
8142
8143         u8         reserved_2[0x60];
8144 };
8145
8146 struct mlx5_ifc_plbf_reg_bits {
8147         u8         reserved_0[0x8];
8148         u8         local_port[0x8];
8149         u8         reserved_1[0xd];
8150         u8         lbf_mode[0x3];
8151
8152         u8         reserved_2[0x20];
8153 };
8154
8155 struct mlx5_ifc_pipg_reg_bits {
8156         u8         reserved_0[0x8];
8157         u8         local_port[0x8];
8158         u8         reserved_1[0x10];
8159
8160         u8         dic[0x1];
8161         u8         reserved_2[0x19];
8162         u8         ipg[0x4];
8163         u8         reserved_3[0x2];
8164 };
8165
8166 struct mlx5_ifc_pifr_reg_bits {
8167         u8         reserved_0[0x8];
8168         u8         local_port[0x8];
8169         u8         reserved_1[0x10];
8170
8171         u8         reserved_2[0xe0];
8172
8173         u8         port_filter[8][0x20];
8174
8175         u8         port_filter_update_en[8][0x20];
8176 };
8177
8178 struct mlx5_ifc_phys_layer_cntrs_bits {
8179         u8         time_since_last_clear_high[0x20];
8180
8181         u8         time_since_last_clear_low[0x20];
8182
8183         u8         symbol_errors_high[0x20];
8184
8185         u8         symbol_errors_low[0x20];
8186
8187         u8         sync_headers_errors_high[0x20];
8188
8189         u8         sync_headers_errors_low[0x20];
8190
8191         u8         edpl_bip_errors_lane0_high[0x20];
8192
8193         u8         edpl_bip_errors_lane0_low[0x20];
8194
8195         u8         edpl_bip_errors_lane1_high[0x20];
8196
8197         u8         edpl_bip_errors_lane1_low[0x20];
8198
8199         u8         edpl_bip_errors_lane2_high[0x20];
8200
8201         u8         edpl_bip_errors_lane2_low[0x20];
8202
8203         u8         edpl_bip_errors_lane3_high[0x20];
8204
8205         u8         edpl_bip_errors_lane3_low[0x20];
8206
8207         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8208
8209         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8210
8211         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8212
8213         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8214
8215         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8216
8217         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8218
8219         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8220
8221         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8222
8223         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8224
8225         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8226
8227         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8228
8229         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8230
8231         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8232
8233         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8234
8235         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8236
8237         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8238
8239         u8         rs_fec_corrected_blocks_high[0x20];
8240
8241         u8         rs_fec_corrected_blocks_low[0x20];
8242
8243         u8         rs_fec_uncorrectable_blocks_high[0x20];
8244
8245         u8         rs_fec_uncorrectable_blocks_low[0x20];
8246
8247         u8         rs_fec_no_errors_blocks_high[0x20];
8248
8249         u8         rs_fec_no_errors_blocks_low[0x20];
8250
8251         u8         rs_fec_single_error_blocks_high[0x20];
8252
8253         u8         rs_fec_single_error_blocks_low[0x20];
8254
8255         u8         rs_fec_corrected_symbols_total_high[0x20];
8256
8257         u8         rs_fec_corrected_symbols_total_low[0x20];
8258
8259         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8260
8261         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8262
8263         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8264
8265         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8266
8267         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8268
8269         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8270
8271         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8272
8273         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8274
8275         u8         link_down_events[0x20];
8276
8277         u8         successful_recovery_events[0x20];
8278
8279         u8         reserved_0[0x180];
8280 };
8281
8282 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8283         u8         symbol_error_counter[0x10];
8284
8285         u8         link_error_recovery_counter[0x8];
8286
8287         u8         link_downed_counter[0x8];
8288
8289         u8         port_rcv_errors[0x10];
8290
8291         u8         port_rcv_remote_physical_errors[0x10];
8292
8293         u8         port_rcv_switch_relay_errors[0x10];
8294
8295         u8         port_xmit_discards[0x10];
8296
8297         u8         port_xmit_constraint_errors[0x8];
8298
8299         u8         port_rcv_constraint_errors[0x8];
8300
8301         u8         reserved_at_70[0x8];
8302
8303         u8         link_overrun_errors[0x8];
8304
8305         u8         reserved_at_80[0x10];
8306
8307         u8         vl_15_dropped[0x10];
8308
8309         u8         reserved_at_a0[0xa0];
8310 };
8311
8312 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8313         u8         time_since_last_clear_high[0x20];
8314
8315         u8         time_since_last_clear_low[0x20];
8316
8317         u8         phy_received_bits_high[0x20];
8318
8319         u8         phy_received_bits_low[0x20];
8320
8321         u8         phy_symbol_errors_high[0x20];
8322
8323         u8         phy_symbol_errors_low[0x20];
8324
8325         u8         phy_corrected_bits_high[0x20];
8326
8327         u8         phy_corrected_bits_low[0x20];
8328
8329         u8         phy_corrected_bits_lane0_high[0x20];
8330
8331         u8         phy_corrected_bits_lane0_low[0x20];
8332
8333         u8         phy_corrected_bits_lane1_high[0x20];
8334
8335         u8         phy_corrected_bits_lane1_low[0x20];
8336
8337         u8         phy_corrected_bits_lane2_high[0x20];
8338
8339         u8         phy_corrected_bits_lane2_low[0x20];
8340
8341         u8         phy_corrected_bits_lane3_high[0x20];
8342
8343         u8         phy_corrected_bits_lane3_low[0x20];
8344
8345         u8         reserved_at_200[0x5c0];
8346 };
8347
8348 struct mlx5_ifc_infiniband_port_cntrs_bits {
8349         u8         symbol_error_counter[0x10];
8350         u8         link_error_recovery_counter[0x8];
8351         u8         link_downed_counter[0x8];
8352
8353         u8         port_rcv_errors[0x10];
8354         u8         port_rcv_remote_physical_errors[0x10];
8355
8356         u8         port_rcv_switch_relay_errors[0x10];
8357         u8         port_xmit_discards[0x10];
8358
8359         u8         port_xmit_constraint_errors[0x8];
8360         u8         port_rcv_constraint_errors[0x8];
8361         u8         reserved_0[0x8];
8362         u8         local_link_integrity_errors[0x4];
8363         u8         excessive_buffer_overrun_errors[0x4];
8364
8365         u8         reserved_1[0x10];
8366         u8         vl_15_dropped[0x10];
8367
8368         u8         port_xmit_data[0x20];
8369
8370         u8         port_rcv_data[0x20];
8371
8372         u8         port_xmit_pkts[0x20];
8373
8374         u8         port_rcv_pkts[0x20];
8375
8376         u8         port_xmit_wait[0x20];
8377
8378         u8         reserved_2[0x680];
8379 };
8380
8381 struct mlx5_ifc_phrr_reg_bits {
8382         u8         clr[0x1];
8383         u8         reserved_0[0x7];
8384         u8         local_port[0x8];
8385         u8         reserved_1[0x10];
8386
8387         u8         hist_group[0x8];
8388         u8         reserved_2[0x10];
8389         u8         hist_id[0x8];
8390
8391         u8         reserved_3[0x40];
8392
8393         u8         time_since_last_clear_high[0x20];
8394
8395         u8         time_since_last_clear_low[0x20];
8396
8397         u8         bin[10][0x20];
8398 };
8399
8400 struct mlx5_ifc_phbr_for_prio_reg_bits {
8401         u8         reserved_0[0x18];
8402         u8         prio[0x8];
8403 };
8404
8405 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8406         u8         reserved_0[0x18];
8407         u8         tclass[0x8];
8408 };
8409
8410 struct mlx5_ifc_phbr_binding_reg_bits {
8411         u8         opcode[0x4];
8412         u8         reserved_0[0x4];
8413         u8         local_port[0x8];
8414         u8         pnat[0x2];
8415         u8         reserved_1[0xe];
8416
8417         u8         hist_group[0x8];
8418         u8         reserved_2[0x10];
8419         u8         hist_id[0x8];
8420
8421         u8         reserved_3[0x10];
8422         u8         hist_type[0x10];
8423
8424         u8         hist_parameters[0x20];
8425
8426         u8         hist_min_value[0x20];
8427
8428         u8         hist_max_value[0x20];
8429
8430         u8         sample_time[0x20];
8431 };
8432
8433 enum {
8434         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8435         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8436 };
8437
8438 struct mlx5_ifc_pfcc_reg_bits {
8439         u8         dcbx_operation_type[0x2];
8440         u8         cap_local_admin[0x1];
8441         u8         cap_remote_admin[0x1];
8442         u8         reserved_0[0x4];
8443         u8         local_port[0x8];
8444         u8         pnat[0x2];
8445         u8         reserved_1[0xc];
8446         u8         shl_cap[0x1];
8447         u8         shl_opr[0x1];
8448
8449         u8         ppan[0x4];
8450         u8         reserved_2[0x4];
8451         u8         prio_mask_tx[0x8];
8452         u8         reserved_3[0x8];
8453         u8         prio_mask_rx[0x8];
8454
8455         u8         pptx[0x1];
8456         u8         aptx[0x1];
8457         u8         reserved_4[0x6];
8458         u8         pfctx[0x8];
8459         u8         reserved_5[0x8];
8460         u8         cbftx[0x8];
8461
8462         u8         pprx[0x1];
8463         u8         aprx[0x1];
8464         u8         reserved_6[0x6];
8465         u8         pfcrx[0x8];
8466         u8         reserved_7[0x8];
8467         u8         cbfrx[0x8];
8468
8469         u8         device_stall_minor_watermark[0x10];
8470         u8         device_stall_critical_watermark[0x10];
8471
8472         u8         reserved_8[0x60];
8473 };
8474
8475 struct mlx5_ifc_pelc_reg_bits {
8476         u8         op[0x4];
8477         u8         reserved_0[0x4];
8478         u8         local_port[0x8];
8479         u8         reserved_1[0x10];
8480
8481         u8         op_admin[0x8];
8482         u8         op_capability[0x8];
8483         u8         op_request[0x8];
8484         u8         op_active[0x8];
8485
8486         u8         admin[0x40];
8487
8488         u8         capability[0x40];
8489
8490         u8         request[0x40];
8491
8492         u8         active[0x40];
8493
8494         u8         reserved_2[0x80];
8495 };
8496
8497 struct mlx5_ifc_peir_reg_bits {
8498         u8         reserved_0[0x8];
8499         u8         local_port[0x8];
8500         u8         reserved_1[0x10];
8501
8502         u8         reserved_2[0xc];
8503         u8         error_count[0x4];
8504         u8         reserved_3[0x10];
8505
8506         u8         reserved_4[0xc];
8507         u8         lane[0x4];
8508         u8         reserved_5[0x8];
8509         u8         error_type[0x8];
8510 };
8511
8512 struct mlx5_ifc_qcam_access_reg_cap_mask {
8513         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8514         u8         qpdpm[0x1];
8515         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8516         u8         qdpm[0x1];
8517         u8         qpts[0x1];
8518         u8         qcap[0x1];
8519         u8         qcam_access_reg_cap_mask_0[0x1];
8520 };
8521
8522 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8523         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8524         u8         qpts_trust_both[0x1];
8525 };
8526
8527 struct mlx5_ifc_qcam_reg_bits {
8528         u8         reserved_at_0[0x8];
8529         u8         feature_group[0x8];
8530         u8         reserved_at_10[0x8];
8531         u8         access_reg_group[0x8];
8532         u8         reserved_at_20[0x20];
8533
8534         union {
8535                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8536                 u8  reserved_at_0[0x80];
8537         } qos_access_reg_cap_mask;
8538
8539         u8         reserved_at_c0[0x80];
8540
8541         union {
8542                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8543                 u8  reserved_at_0[0x80];
8544         } qos_feature_cap_mask;
8545
8546         u8         reserved_at_1c0[0x80];
8547 };
8548
8549 struct mlx5_ifc_pcap_reg_bits {
8550         u8         reserved_0[0x8];
8551         u8         local_port[0x8];
8552         u8         reserved_1[0x10];
8553
8554         u8         port_capability_mask[4][0x20];
8555 };
8556
8557 struct mlx5_ifc_pbmc_reg_bits {
8558         u8         reserved_0[0x8];
8559         u8         local_port[0x8];
8560         u8         reserved_1[0x10];
8561
8562         u8         xoff_timer_value[0x10];
8563         u8         xoff_refresh[0x10];
8564
8565         u8         reserved_2[0x10];
8566         u8         port_buffer_size[0x10];
8567
8568         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8569
8570         u8         reserved_3[0x40];
8571
8572         u8         port_shared_buffer[0x40];
8573 };
8574
8575 struct mlx5_ifc_paos_reg_bits {
8576         u8         swid[0x8];
8577         u8         local_port[0x8];
8578         u8         reserved_0[0x4];
8579         u8         admin_status[0x4];
8580         u8         reserved_1[0x4];
8581         u8         oper_status[0x4];
8582
8583         u8         ase[0x1];
8584         u8         ee[0x1];
8585         u8         reserved_2[0x1c];
8586         u8         e[0x2];
8587
8588         u8         reserved_3[0x40];
8589 };
8590
8591 struct mlx5_ifc_pamp_reg_bits {
8592         u8         reserved_0[0x8];
8593         u8         opamp_group[0x8];
8594         u8         reserved_1[0xc];
8595         u8         opamp_group_type[0x4];
8596
8597         u8         start_index[0x10];
8598         u8         reserved_2[0x4];
8599         u8         num_of_indices[0xc];
8600
8601         u8         index_data[18][0x10];
8602 };
8603
8604 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8605         u8         llr_rx_cells_high[0x20];
8606
8607         u8         llr_rx_cells_low[0x20];
8608
8609         u8         llr_rx_error_high[0x20];
8610
8611         u8         llr_rx_error_low[0x20];
8612
8613         u8         llr_rx_crc_error_high[0x20];
8614
8615         u8         llr_rx_crc_error_low[0x20];
8616
8617         u8         llr_tx_cells_high[0x20];
8618
8619         u8         llr_tx_cells_low[0x20];
8620
8621         u8         llr_tx_ret_cells_high[0x20];
8622
8623         u8         llr_tx_ret_cells_low[0x20];
8624
8625         u8         llr_tx_ret_events_high[0x20];
8626
8627         u8         llr_tx_ret_events_low[0x20];
8628
8629         u8         reserved_0[0x640];
8630 };
8631
8632 struct mlx5_ifc_mtmp_reg_bits {
8633         u8         i[0x1];
8634         u8         reserved_at_1[0x18];
8635         u8         sensor_index[0x7];
8636
8637         u8         reserved_at_20[0x10];
8638         u8         temperature[0x10];
8639
8640         u8         mte[0x1];
8641         u8         mtr[0x1];
8642         u8         reserved_at_42[0x0e];
8643         u8         max_temperature[0x10];
8644
8645         u8         tee[0x2];
8646         u8         reserved_at_62[0x0e];
8647         u8         temperature_threshold_hi[0x10];
8648
8649         u8         reserved_at_80[0x10];
8650         u8         temperature_threshold_lo[0x10];
8651
8652         u8         reserved_at_100[0x20];
8653
8654         u8         sensor_name[0x40];
8655 };
8656
8657 struct mlx5_ifc_lane_2_module_mapping_bits {
8658         u8         reserved_0[0x6];
8659         u8         rx_lane[0x2];
8660         u8         reserved_1[0x6];
8661         u8         tx_lane[0x2];
8662         u8         reserved_2[0x8];
8663         u8         module[0x8];
8664 };
8665
8666 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8667         u8         transmit_queue_high[0x20];
8668
8669         u8         transmit_queue_low[0x20];
8670
8671         u8         reserved_0[0x780];
8672 };
8673
8674 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8675         u8         no_buffer_discard_uc_high[0x20];
8676
8677         u8         no_buffer_discard_uc_low[0x20];
8678
8679         u8         wred_discard_high[0x20];
8680
8681         u8         wred_discard_low[0x20];
8682
8683         u8         reserved_0[0x740];
8684 };
8685
8686 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8687         u8         rx_octets_high[0x20];
8688
8689         u8         rx_octets_low[0x20];
8690
8691         u8         reserved_0[0xc0];
8692
8693         u8         rx_frames_high[0x20];
8694
8695         u8         rx_frames_low[0x20];
8696
8697         u8         tx_octets_high[0x20];
8698
8699         u8         tx_octets_low[0x20];
8700
8701         u8         reserved_1[0xc0];
8702
8703         u8         tx_frames_high[0x20];
8704
8705         u8         tx_frames_low[0x20];
8706
8707         u8         rx_pause_high[0x20];
8708
8709         u8         rx_pause_low[0x20];
8710
8711         u8         rx_pause_duration_high[0x20];
8712
8713         u8         rx_pause_duration_low[0x20];
8714
8715         u8         tx_pause_high[0x20];
8716
8717         u8         tx_pause_low[0x20];
8718
8719         u8         tx_pause_duration_high[0x20];
8720
8721         u8         tx_pause_duration_low[0x20];
8722
8723         u8         rx_pause_transition_high[0x20];
8724
8725         u8         rx_pause_transition_low[0x20];
8726
8727         u8         rx_discards_high[0x20];
8728
8729         u8         rx_discards_low[0x20];
8730
8731         u8         device_stall_minor_watermark_cnt_high[0x20];
8732
8733         u8         device_stall_minor_watermark_cnt_low[0x20];
8734
8735         u8         device_stall_critical_watermark_cnt_high[0x20];
8736
8737         u8         device_stall_critical_watermark_cnt_low[0x20];
8738
8739         u8         reserved_2[0x340];
8740 };
8741
8742 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8743         u8         port_transmit_wait_high[0x20];
8744
8745         u8         port_transmit_wait_low[0x20];
8746
8747         u8         ecn_marked_high[0x20];
8748
8749         u8         ecn_marked_low[0x20];
8750
8751         u8         no_buffer_discard_mc_high[0x20];
8752
8753         u8         no_buffer_discard_mc_low[0x20];
8754
8755         u8         reserved_0[0x700];
8756 };
8757
8758 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8759         u8         a_frames_transmitted_ok_high[0x20];
8760
8761         u8         a_frames_transmitted_ok_low[0x20];
8762
8763         u8         a_frames_received_ok_high[0x20];
8764
8765         u8         a_frames_received_ok_low[0x20];
8766
8767         u8         a_frame_check_sequence_errors_high[0x20];
8768
8769         u8         a_frame_check_sequence_errors_low[0x20];
8770
8771         u8         a_alignment_errors_high[0x20];
8772
8773         u8         a_alignment_errors_low[0x20];
8774
8775         u8         a_octets_transmitted_ok_high[0x20];
8776
8777         u8         a_octets_transmitted_ok_low[0x20];
8778
8779         u8         a_octets_received_ok_high[0x20];
8780
8781         u8         a_octets_received_ok_low[0x20];
8782
8783         u8         a_multicast_frames_xmitted_ok_high[0x20];
8784
8785         u8         a_multicast_frames_xmitted_ok_low[0x20];
8786
8787         u8         a_broadcast_frames_xmitted_ok_high[0x20];
8788
8789         u8         a_broadcast_frames_xmitted_ok_low[0x20];
8790
8791         u8         a_multicast_frames_received_ok_high[0x20];
8792
8793         u8         a_multicast_frames_received_ok_low[0x20];
8794
8795         u8         a_broadcast_frames_recieved_ok_high[0x20];
8796
8797         u8         a_broadcast_frames_recieved_ok_low[0x20];
8798
8799         u8         a_in_range_length_errors_high[0x20];
8800
8801         u8         a_in_range_length_errors_low[0x20];
8802
8803         u8         a_out_of_range_length_field_high[0x20];
8804
8805         u8         a_out_of_range_length_field_low[0x20];
8806
8807         u8         a_frame_too_long_errors_high[0x20];
8808
8809         u8         a_frame_too_long_errors_low[0x20];
8810
8811         u8         a_symbol_error_during_carrier_high[0x20];
8812
8813         u8         a_symbol_error_during_carrier_low[0x20];
8814
8815         u8         a_mac_control_frames_transmitted_high[0x20];
8816
8817         u8         a_mac_control_frames_transmitted_low[0x20];
8818
8819         u8         a_mac_control_frames_received_high[0x20];
8820
8821         u8         a_mac_control_frames_received_low[0x20];
8822
8823         u8         a_unsupported_opcodes_received_high[0x20];
8824
8825         u8         a_unsupported_opcodes_received_low[0x20];
8826
8827         u8         a_pause_mac_ctrl_frames_received_high[0x20];
8828
8829         u8         a_pause_mac_ctrl_frames_received_low[0x20];
8830
8831         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8832
8833         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8834
8835         u8         reserved_0[0x300];
8836 };
8837
8838 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8839         u8         dot3stats_alignment_errors_high[0x20];
8840
8841         u8         dot3stats_alignment_errors_low[0x20];
8842
8843         u8         dot3stats_fcs_errors_high[0x20];
8844
8845         u8         dot3stats_fcs_errors_low[0x20];
8846
8847         u8         dot3stats_single_collision_frames_high[0x20];
8848
8849         u8         dot3stats_single_collision_frames_low[0x20];
8850
8851         u8         dot3stats_multiple_collision_frames_high[0x20];
8852
8853         u8         dot3stats_multiple_collision_frames_low[0x20];
8854
8855         u8         dot3stats_sqe_test_errors_high[0x20];
8856
8857         u8         dot3stats_sqe_test_errors_low[0x20];
8858
8859         u8         dot3stats_deferred_transmissions_high[0x20];
8860
8861         u8         dot3stats_deferred_transmissions_low[0x20];
8862
8863         u8         dot3stats_late_collisions_high[0x20];
8864
8865         u8         dot3stats_late_collisions_low[0x20];
8866
8867         u8         dot3stats_excessive_collisions_high[0x20];
8868
8869         u8         dot3stats_excessive_collisions_low[0x20];
8870
8871         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8872
8873         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8874
8875         u8         dot3stats_carrier_sense_errors_high[0x20];
8876
8877         u8         dot3stats_carrier_sense_errors_low[0x20];
8878
8879         u8         dot3stats_frame_too_longs_high[0x20];
8880
8881         u8         dot3stats_frame_too_longs_low[0x20];
8882
8883         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8884
8885         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8886
8887         u8         dot3stats_symbol_errors_high[0x20];
8888
8889         u8         dot3stats_symbol_errors_low[0x20];
8890
8891         u8         dot3control_in_unknown_opcodes_high[0x20];
8892
8893         u8         dot3control_in_unknown_opcodes_low[0x20];
8894
8895         u8         dot3in_pause_frames_high[0x20];
8896
8897         u8         dot3in_pause_frames_low[0x20];
8898
8899         u8         dot3out_pause_frames_high[0x20];
8900
8901         u8         dot3out_pause_frames_low[0x20];
8902
8903         u8         reserved_0[0x3c0];
8904 };
8905
8906 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8907         u8         if_in_octets_high[0x20];
8908
8909         u8         if_in_octets_low[0x20];
8910
8911         u8         if_in_ucast_pkts_high[0x20];
8912
8913         u8         if_in_ucast_pkts_low[0x20];
8914
8915         u8         if_in_discards_high[0x20];
8916
8917         u8         if_in_discards_low[0x20];
8918
8919         u8         if_in_errors_high[0x20];
8920
8921         u8         if_in_errors_low[0x20];
8922
8923         u8         if_in_unknown_protos_high[0x20];
8924
8925         u8         if_in_unknown_protos_low[0x20];
8926
8927         u8         if_out_octets_high[0x20];
8928
8929         u8         if_out_octets_low[0x20];
8930
8931         u8         if_out_ucast_pkts_high[0x20];
8932
8933         u8         if_out_ucast_pkts_low[0x20];
8934
8935         u8         if_out_discards_high[0x20];
8936
8937         u8         if_out_discards_low[0x20];
8938
8939         u8         if_out_errors_high[0x20];
8940
8941         u8         if_out_errors_low[0x20];
8942
8943         u8         if_in_multicast_pkts_high[0x20];
8944
8945         u8         if_in_multicast_pkts_low[0x20];
8946
8947         u8         if_in_broadcast_pkts_high[0x20];
8948
8949         u8         if_in_broadcast_pkts_low[0x20];
8950
8951         u8         if_out_multicast_pkts_high[0x20];
8952
8953         u8         if_out_multicast_pkts_low[0x20];
8954
8955         u8         if_out_broadcast_pkts_high[0x20];
8956
8957         u8         if_out_broadcast_pkts_low[0x20];
8958
8959         u8         reserved_0[0x480];
8960 };
8961
8962 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8963         u8         ether_stats_drop_events_high[0x20];
8964
8965         u8         ether_stats_drop_events_low[0x20];
8966
8967         u8         ether_stats_octets_high[0x20];
8968
8969         u8         ether_stats_octets_low[0x20];
8970
8971         u8         ether_stats_pkts_high[0x20];
8972
8973         u8         ether_stats_pkts_low[0x20];
8974
8975         u8         ether_stats_broadcast_pkts_high[0x20];
8976
8977         u8         ether_stats_broadcast_pkts_low[0x20];
8978
8979         u8         ether_stats_multicast_pkts_high[0x20];
8980
8981         u8         ether_stats_multicast_pkts_low[0x20];
8982
8983         u8         ether_stats_crc_align_errors_high[0x20];
8984
8985         u8         ether_stats_crc_align_errors_low[0x20];
8986
8987         u8         ether_stats_undersize_pkts_high[0x20];
8988
8989         u8         ether_stats_undersize_pkts_low[0x20];
8990
8991         u8         ether_stats_oversize_pkts_high[0x20];
8992
8993         u8         ether_stats_oversize_pkts_low[0x20];
8994
8995         u8         ether_stats_fragments_high[0x20];
8996
8997         u8         ether_stats_fragments_low[0x20];
8998
8999         u8         ether_stats_jabbers_high[0x20];
9000
9001         u8         ether_stats_jabbers_low[0x20];
9002
9003         u8         ether_stats_collisions_high[0x20];
9004
9005         u8         ether_stats_collisions_low[0x20];
9006
9007         u8         ether_stats_pkts64octets_high[0x20];
9008
9009         u8         ether_stats_pkts64octets_low[0x20];
9010
9011         u8         ether_stats_pkts65to127octets_high[0x20];
9012
9013         u8         ether_stats_pkts65to127octets_low[0x20];
9014
9015         u8         ether_stats_pkts128to255octets_high[0x20];
9016
9017         u8         ether_stats_pkts128to255octets_low[0x20];
9018
9019         u8         ether_stats_pkts256to511octets_high[0x20];
9020
9021         u8         ether_stats_pkts256to511octets_low[0x20];
9022
9023         u8         ether_stats_pkts512to1023octets_high[0x20];
9024
9025         u8         ether_stats_pkts512to1023octets_low[0x20];
9026
9027         u8         ether_stats_pkts1024to1518octets_high[0x20];
9028
9029         u8         ether_stats_pkts1024to1518octets_low[0x20];
9030
9031         u8         ether_stats_pkts1519to2047octets_high[0x20];
9032
9033         u8         ether_stats_pkts1519to2047octets_low[0x20];
9034
9035         u8         ether_stats_pkts2048to4095octets_high[0x20];
9036
9037         u8         ether_stats_pkts2048to4095octets_low[0x20];
9038
9039         u8         ether_stats_pkts4096to8191octets_high[0x20];
9040
9041         u8         ether_stats_pkts4096to8191octets_low[0x20];
9042
9043         u8         ether_stats_pkts8192to10239octets_high[0x20];
9044
9045         u8         ether_stats_pkts8192to10239octets_low[0x20];
9046
9047         u8         reserved_0[0x280];
9048 };
9049
9050 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9051         u8         symbol_error_counter[0x10];
9052         u8         link_error_recovery_counter[0x8];
9053         u8         link_downed_counter[0x8];
9054
9055         u8         port_rcv_errors[0x10];
9056         u8         port_rcv_remote_physical_errors[0x10];
9057
9058         u8         port_rcv_switch_relay_errors[0x10];
9059         u8         port_xmit_discards[0x10];
9060
9061         u8         port_xmit_constraint_errors[0x8];
9062         u8         port_rcv_constraint_errors[0x8];
9063         u8         reserved_0[0x8];
9064         u8         local_link_integrity_errors[0x4];
9065         u8         excessive_buffer_overrun_errors[0x4];
9066
9067         u8         reserved_1[0x10];
9068         u8         vl_15_dropped[0x10];
9069
9070         u8         port_xmit_data[0x20];
9071
9072         u8         port_rcv_data[0x20];
9073
9074         u8         port_xmit_pkts[0x20];
9075
9076         u8         port_rcv_pkts[0x20];
9077
9078         u8         port_xmit_wait[0x20];
9079
9080         u8         reserved_2[0x680];
9081 };
9082
9083 struct mlx5_ifc_trc_tlb_reg_bits {
9084         u8         reserved_0[0x80];
9085
9086         u8         tlb_addr[0][0x40];
9087 };
9088
9089 struct mlx5_ifc_trc_read_fifo_reg_bits {
9090         u8         reserved_0[0x10];
9091         u8         requested_event_num[0x10];
9092
9093         u8         reserved_1[0x20];
9094
9095         u8         reserved_2[0x10];
9096         u8         acual_event_num[0x10];
9097
9098         u8         reserved_3[0x20];
9099
9100         u8         event[0][0x40];
9101 };
9102
9103 struct mlx5_ifc_trc_lock_reg_bits {
9104         u8         reserved_0[0x1f];
9105         u8         lock[0x1];
9106
9107         u8         reserved_1[0x60];
9108 };
9109
9110 struct mlx5_ifc_trc_filter_reg_bits {
9111         u8         status[0x1];
9112         u8         reserved_0[0xf];
9113         u8         filter_index[0x10];
9114
9115         u8         reserved_1[0x20];
9116
9117         u8         filter_val[0x20];
9118
9119         u8         reserved_2[0x1a0];
9120 };
9121
9122 struct mlx5_ifc_trc_event_reg_bits {
9123         u8         status[0x1];
9124         u8         reserved_0[0xf];
9125         u8         event_index[0x10];
9126
9127         u8         reserved_1[0x20];
9128
9129         u8         event_id[0x20];
9130
9131         u8         event_selector_val[0x10];
9132         u8         event_selector_size[0x10];
9133
9134         u8         reserved_2[0x180];
9135 };
9136
9137 struct mlx5_ifc_trc_conf_reg_bits {
9138         u8         limit_en[0x1];
9139         u8         reserved_0[0x3];
9140         u8         dump_mode[0x4];
9141         u8         reserved_1[0x15];
9142         u8         state[0x3];
9143
9144         u8         reserved_2[0x20];
9145
9146         u8         limit_event_index[0x20];
9147
9148         u8         mkey[0x20];
9149
9150         u8         fifo_ready_ev_num[0x20];
9151
9152         u8         reserved_3[0x160];
9153 };
9154
9155 struct mlx5_ifc_trc_cap_reg_bits {
9156         u8         reserved_0[0x18];
9157         u8         dump_mode[0x8];
9158
9159         u8         reserved_1[0x20];
9160
9161         u8         num_of_events[0x10];
9162         u8         num_of_filters[0x10];
9163
9164         u8         fifo_size[0x20];
9165
9166         u8         tlb_size[0x10];
9167         u8         event_size[0x10];
9168
9169         u8         reserved_2[0x160];
9170 };
9171
9172 struct mlx5_ifc_set_node_in_bits {
9173         u8         node_description[64][0x8];
9174 };
9175
9176 struct mlx5_ifc_register_power_settings_bits {
9177         u8         reserved_0[0x18];
9178         u8         power_settings_level[0x8];
9179
9180         u8         reserved_1[0x60];
9181 };
9182
9183 struct mlx5_ifc_register_host_endianess_bits {
9184         u8         he[0x1];
9185         u8         reserved_0[0x1f];
9186
9187         u8         reserved_1[0x60];
9188 };
9189
9190 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9191         u8         physical_address[0x40];
9192 };
9193
9194 struct mlx5_ifc_qtct_reg_bits {
9195         u8         operation_type[0x2];
9196         u8         cap_local_admin[0x1];
9197         u8         cap_remote_admin[0x1];
9198         u8         reserved_0[0x4];
9199         u8         port_number[0x8];
9200         u8         reserved_1[0xd];
9201         u8         prio[0x3];
9202
9203         u8         reserved_2[0x1d];
9204         u8         tclass[0x3];
9205 };
9206
9207 struct mlx5_ifc_qpdp_reg_bits {
9208         u8         reserved_0[0x8];
9209         u8         port_number[0x8];
9210         u8         reserved_1[0x10];
9211
9212         u8         reserved_2[0x1d];
9213         u8         pprio[0x3];
9214 };
9215
9216 struct mlx5_ifc_port_info_ro_fields_param_bits {
9217         u8         reserved_0[0x8];
9218         u8         port[0x8];
9219         u8         max_gid[0x10];
9220
9221         u8         reserved_1[0x20];
9222
9223         u8         port_guid[0x40];
9224 };
9225
9226 struct mlx5_ifc_nvqc_reg_bits {
9227         u8         type[0x20];
9228
9229         u8         reserved_0[0x18];
9230         u8         version[0x4];
9231         u8         reserved_1[0x2];
9232         u8         support_wr[0x1];
9233         u8         support_rd[0x1];
9234 };
9235
9236 struct mlx5_ifc_nvia_reg_bits {
9237         u8         reserved_0[0x1d];
9238         u8         target[0x3];
9239
9240         u8         reserved_1[0x20];
9241 };
9242
9243 struct mlx5_ifc_nvdi_reg_bits {
9244         struct mlx5_ifc_config_item_bits configuration_item_header;
9245 };
9246
9247 struct mlx5_ifc_nvda_reg_bits {
9248         struct mlx5_ifc_config_item_bits configuration_item_header;
9249
9250         u8         configuration_item_data[0x20];
9251 };
9252
9253 struct mlx5_ifc_node_info_ro_fields_param_bits {
9254         u8         system_image_guid[0x40];
9255
9256         u8         reserved_0[0x40];
9257
9258         u8         node_guid[0x40];
9259
9260         u8         reserved_1[0x10];
9261         u8         max_pkey[0x10];
9262
9263         u8         reserved_2[0x20];
9264 };
9265
9266 struct mlx5_ifc_ets_tcn_config_reg_bits {
9267         u8         g[0x1];
9268         u8         b[0x1];
9269         u8         r[0x1];
9270         u8         reserved_0[0x9];
9271         u8         group[0x4];
9272         u8         reserved_1[0x9];
9273         u8         bw_allocation[0x7];
9274
9275         u8         reserved_2[0xc];
9276         u8         max_bw_units[0x4];
9277         u8         reserved_3[0x8];
9278         u8         max_bw_value[0x8];
9279 };
9280
9281 struct mlx5_ifc_ets_global_config_reg_bits {
9282         u8         reserved_0[0x2];
9283         u8         r[0x1];
9284         u8         reserved_1[0x1d];
9285
9286         u8         reserved_2[0xc];
9287         u8         max_bw_units[0x4];
9288         u8         reserved_3[0x8];
9289         u8         max_bw_value[0x8];
9290 };
9291
9292 struct mlx5_ifc_qetc_reg_bits {
9293         u8                                         reserved_at_0[0x8];
9294         u8                                         port_number[0x8];
9295         u8                                         reserved_at_10[0x30];
9296
9297         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9298         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9299 };
9300
9301 struct mlx5_ifc_nodnic_mac_filters_bits {
9302         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9303
9304         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9305
9306         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9307
9308         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9309
9310         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9311
9312         u8         reserved_0[0xc0];
9313 };
9314
9315 struct mlx5_ifc_nodnic_gid_filters_bits {
9316         u8         mgid_filter0[16][0x8];
9317
9318         u8         mgid_filter1[16][0x8];
9319
9320         u8         mgid_filter2[16][0x8];
9321
9322         u8         mgid_filter3[16][0x8];
9323 };
9324
9325 enum {
9326         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9327         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9328 };
9329
9330 enum {
9331         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9332         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9333 };
9334
9335 struct mlx5_ifc_nodnic_config_reg_bits {
9336         u8         no_dram_nic_revision[0x8];
9337         u8         hardware_format[0x8];
9338         u8         support_receive_filter[0x1];
9339         u8         support_promisc_filter[0x1];
9340         u8         support_promisc_multicast_filter[0x1];
9341         u8         reserved_0[0x2];
9342         u8         log_working_buffer_size[0x3];
9343         u8         log_pkey_table_size[0x4];
9344         u8         reserved_1[0x3];
9345         u8         num_ports[0x1];
9346
9347         u8         reserved_2[0x2];
9348         u8         log_max_ring_size[0x6];
9349         u8         reserved_3[0x18];
9350
9351         u8         lkey[0x20];
9352
9353         u8         cqe_format[0x4];
9354         u8         reserved_4[0x1c];
9355
9356         u8         node_guid[0x40];
9357
9358         u8         reserved_5[0x740];
9359
9360         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9361
9362         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9363 };
9364
9365 struct mlx5_ifc_vlan_layout_bits {
9366         u8         reserved_0[0x14];
9367         u8         vlan[0xc];
9368
9369         u8         reserved_1[0x20];
9370 };
9371
9372 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9373         u8         reserved_0[0x20];
9374
9375         u8         mkey[0x20];
9376
9377         u8         addressh_63_32[0x20];
9378
9379         u8         addressl_31_0[0x20];
9380 };
9381
9382 struct mlx5_ifc_ud_adrs_vector_bits {
9383         u8         dc_key[0x40];
9384
9385         u8         ext[0x1];
9386         u8         reserved_0[0x7];
9387         u8         destination_qp_dct[0x18];
9388
9389         u8         static_rate[0x4];
9390         u8         sl_eth_prio[0x4];
9391         u8         fl[0x1];
9392         u8         mlid[0x7];
9393         u8         rlid_udp_sport[0x10];
9394
9395         u8         reserved_1[0x20];
9396
9397         u8         rmac_47_16[0x20];
9398
9399         u8         rmac_15_0[0x10];
9400         u8         tclass[0x8];
9401         u8         hop_limit[0x8];
9402
9403         u8         reserved_2[0x1];
9404         u8         grh[0x1];
9405         u8         reserved_3[0x2];
9406         u8         src_addr_index[0x8];
9407         u8         flow_label[0x14];
9408
9409         u8         rgid_rip[16][0x8];
9410 };
9411
9412 struct mlx5_ifc_port_module_event_bits {
9413         u8         reserved_0[0x8];
9414         u8         module[0x8];
9415         u8         reserved_1[0xc];
9416         u8         module_status[0x4];
9417
9418         u8         reserved_2[0x14];
9419         u8         error_type[0x4];
9420         u8         reserved_3[0x8];
9421
9422         u8         reserved_4[0xa0];
9423 };
9424
9425 struct mlx5_ifc_icmd_control_bits {
9426         u8         opcode[0x10];
9427         u8         status[0x8];
9428         u8         reserved_0[0x7];
9429         u8         busy[0x1];
9430 };
9431
9432 struct mlx5_ifc_eqe_bits {
9433         u8         reserved_0[0x8];
9434         u8         event_type[0x8];
9435         u8         reserved_1[0x8];
9436         u8         event_sub_type[0x8];
9437
9438         u8         reserved_2[0xe0];
9439
9440         union mlx5_ifc_event_auto_bits event_data;
9441
9442         u8         reserved_3[0x10];
9443         u8         signature[0x8];
9444         u8         reserved_4[0x7];
9445         u8         owner[0x1];
9446 };
9447
9448 enum {
9449         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9450 };
9451
9452 struct mlx5_ifc_cmd_queue_entry_bits {
9453         u8         type[0x8];
9454         u8         reserved_0[0x18];
9455
9456         u8         input_length[0x20];
9457
9458         u8         input_mailbox_pointer_63_32[0x20];
9459
9460         u8         input_mailbox_pointer_31_9[0x17];
9461         u8         reserved_1[0x9];
9462
9463         u8         command_input_inline_data[16][0x8];
9464
9465         u8         command_output_inline_data[16][0x8];
9466
9467         u8         output_mailbox_pointer_63_32[0x20];
9468
9469         u8         output_mailbox_pointer_31_9[0x17];
9470         u8         reserved_2[0x9];
9471
9472         u8         output_length[0x20];
9473
9474         u8         token[0x8];
9475         u8         signature[0x8];
9476         u8         reserved_3[0x8];
9477         u8         status[0x7];
9478         u8         ownership[0x1];
9479 };
9480
9481 struct mlx5_ifc_cmd_out_bits {
9482         u8         status[0x8];
9483         u8         reserved_0[0x18];
9484
9485         u8         syndrome[0x20];
9486
9487         u8         command_output[0x20];
9488 };
9489
9490 struct mlx5_ifc_cmd_in_bits {
9491         u8         opcode[0x10];
9492         u8         reserved_0[0x10];
9493
9494         u8         reserved_1[0x10];
9495         u8         op_mod[0x10];
9496
9497         u8         command[0][0x20];
9498 };
9499
9500 struct mlx5_ifc_cmd_if_box_bits {
9501         u8         mailbox_data[512][0x8];
9502
9503         u8         reserved_0[0x180];
9504
9505         u8         next_pointer_63_32[0x20];
9506
9507         u8         next_pointer_31_10[0x16];
9508         u8         reserved_1[0xa];
9509
9510         u8         block_number[0x20];
9511
9512         u8         reserved_2[0x8];
9513         u8         token[0x8];
9514         u8         ctrl_signature[0x8];
9515         u8         signature[0x8];
9516 };
9517
9518 struct mlx5_ifc_mtt_bits {
9519         u8         ptag_63_32[0x20];
9520
9521         u8         ptag_31_8[0x18];
9522         u8         reserved_0[0x6];
9523         u8         wr_en[0x1];
9524         u8         rd_en[0x1];
9525 };
9526
9527 /* Vendor Specific Capabilities, VSC */
9528 enum {
9529         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9530         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9531         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9532 };
9533
9534 struct mlx5_ifc_vendor_specific_cap_bits {
9535         u8         type[0x8];
9536         u8         length[0x8];
9537         u8         next_pointer[0x8];
9538         u8         capability_id[0x8];
9539
9540         u8         status[0x3];
9541         u8         reserved_0[0xd];
9542         u8         space[0x10];
9543
9544         u8         counter[0x20];
9545
9546         u8         semaphore[0x20];
9547
9548         u8         flag[0x1];
9549         u8         reserved_1[0x1];
9550         u8         address[0x1e];
9551
9552         u8         data[0x20];
9553 };
9554
9555 enum {
9556         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9557         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9558         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9559 };
9560
9561 enum {
9562         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9563         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9564         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9565 };
9566
9567 enum {
9568         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9569         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9570         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9571         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9572         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9573         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9574         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9575         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9576         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9577         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9578         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9579 };
9580
9581 struct mlx5_ifc_initial_seg_bits {
9582         u8         fw_rev_minor[0x10];
9583         u8         fw_rev_major[0x10];
9584
9585         u8         cmd_interface_rev[0x10];
9586         u8         fw_rev_subminor[0x10];
9587
9588         u8         reserved_0[0x40];
9589
9590         u8         cmdq_phy_addr_63_32[0x20];
9591
9592         u8         cmdq_phy_addr_31_12[0x14];
9593         u8         reserved_1[0x2];
9594         u8         nic_interface[0x2];
9595         u8         log_cmdq_size[0x4];
9596         u8         log_cmdq_stride[0x4];
9597
9598         u8         command_doorbell_vector[0x20];
9599
9600         u8         reserved_2[0xf00];
9601
9602         u8         initializing[0x1];
9603         u8         reserved_3[0x4];
9604         u8         nic_interface_supported[0x3];
9605         u8         reserved_4[0x18];
9606
9607         struct mlx5_ifc_health_buffer_bits health_buffer;
9608
9609         u8         no_dram_nic_offset[0x20];
9610
9611         u8         reserved_5[0x6de0];
9612
9613         u8         internal_timer_h[0x20];
9614
9615         u8         internal_timer_l[0x20];
9616
9617         u8         reserved_6[0x20];
9618
9619         u8         reserved_7[0x1f];
9620         u8         clear_int[0x1];
9621
9622         u8         health_syndrome[0x8];
9623         u8         health_counter[0x18];
9624
9625         u8         reserved_8[0x17fc0];
9626 };
9627
9628 union mlx5_ifc_icmd_interface_document_bits {
9629         struct mlx5_ifc_fw_version_bits fw_version;
9630         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9631         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9632         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9633         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9634         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9635         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9636         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9637         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9638         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9639         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9640         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9641         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9642         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9643         u8         reserved_0[0x42c0];
9644 };
9645
9646 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9647         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9648         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9649         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9650         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9651         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9652         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9653         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9654         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9655         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9656         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9657         u8         reserved_0[0x7c0];
9658 };
9659
9660 struct mlx5_ifc_ppcnt_reg_bits {
9661         u8         swid[0x8];
9662         u8         local_port[0x8];
9663         u8         pnat[0x2];
9664         u8         reserved_0[0x8];
9665         u8         grp[0x6];
9666
9667         u8         clr[0x1];
9668         u8         reserved_1[0x1c];
9669         u8         prio_tc[0x3];
9670
9671         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9672 };
9673
9674 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9675         u8         life_time_counter_high[0x20];
9676
9677         u8         life_time_counter_low[0x20];
9678
9679         u8         rx_errors[0x20];
9680
9681         u8         tx_errors[0x20];
9682
9683         u8         l0_to_recovery_eieos[0x20];
9684
9685         u8         l0_to_recovery_ts[0x20];
9686
9687         u8         l0_to_recovery_framing[0x20];
9688
9689         u8         l0_to_recovery_retrain[0x20];
9690
9691         u8         crc_error_dllp[0x20];
9692
9693         u8         crc_error_tlp[0x20];
9694
9695         u8         reserved_0[0x680];
9696 };
9697
9698 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9699         u8         life_time_counter_high[0x20];
9700
9701         u8         life_time_counter_low[0x20];
9702
9703         u8         time_to_boot_image_start[0x20];
9704
9705         u8         time_to_link_image[0x20];
9706
9707         u8         calibration_time[0x20];
9708
9709         u8         time_to_first_perst[0x20];
9710
9711         u8         time_to_detect_state[0x20];
9712
9713         u8         time_to_l0[0x20];
9714
9715         u8         time_to_crs_en[0x20];
9716
9717         u8         time_to_plastic_image_start[0x20];
9718
9719         u8         time_to_iron_image_start[0x20];
9720
9721         u8         perst_handler[0x20];
9722
9723         u8         times_in_l1[0x20];
9724
9725         u8         times_in_l23[0x20];
9726
9727         u8         dl_down[0x20];
9728
9729         u8         config_cycle1usec[0x20];
9730
9731         u8         config_cycle2to7usec[0x20];
9732
9733         u8         config_cycle8to15usec[0x20];
9734
9735         u8         config_cycle16to63usec[0x20];
9736
9737         u8         config_cycle64usec[0x20];
9738
9739         u8         correctable_err_msg_sent[0x20];
9740
9741         u8         non_fatal_err_msg_sent[0x20];
9742
9743         u8         fatal_err_msg_sent[0x20];
9744
9745         u8         reserved_0[0x4e0];
9746 };
9747
9748 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9749         u8         life_time_counter_high[0x20];
9750
9751         u8         life_time_counter_low[0x20];
9752
9753         u8         error_counter_lane0[0x20];
9754
9755         u8         error_counter_lane1[0x20];
9756
9757         u8         error_counter_lane2[0x20];
9758
9759         u8         error_counter_lane3[0x20];
9760
9761         u8         error_counter_lane4[0x20];
9762
9763         u8         error_counter_lane5[0x20];
9764
9765         u8         error_counter_lane6[0x20];
9766
9767         u8         error_counter_lane7[0x20];
9768
9769         u8         error_counter_lane8[0x20];
9770
9771         u8         error_counter_lane9[0x20];
9772
9773         u8         error_counter_lane10[0x20];
9774
9775         u8         error_counter_lane11[0x20];
9776
9777         u8         error_counter_lane12[0x20];
9778
9779         u8         error_counter_lane13[0x20];
9780
9781         u8         error_counter_lane14[0x20];
9782
9783         u8         error_counter_lane15[0x20];
9784
9785         u8         reserved_0[0x580];
9786 };
9787
9788 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9789         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9790         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9791         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9792         u8         reserved_0[0xf8];
9793 };
9794
9795 struct mlx5_ifc_mpcnt_reg_bits {
9796         u8         reserved_0[0x8];
9797         u8         pcie_index[0x8];
9798         u8         reserved_1[0xa];
9799         u8         grp[0x6];
9800
9801         u8         clr[0x1];
9802         u8         reserved_2[0x1f];
9803
9804         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9805 };
9806
9807 union mlx5_ifc_ports_control_registers_document_bits {
9808         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9809         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9810         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9811         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9812         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9813         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9814         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9815         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9816         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9817         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9818         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9819         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9820         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9821         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9822         struct mlx5_ifc_paos_reg_bits paos_reg;
9823         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9824         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9825         struct mlx5_ifc_peir_reg_bits peir_reg;
9826         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9827         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9828         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9829         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9830         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9831         struct mlx5_ifc_phrr_reg_bits phrr_reg;
9832         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9833         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9834         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9835         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9836         struct mlx5_ifc_plib_reg_bits plib_reg;
9837         struct mlx5_ifc_pll_status_data_bits pll_status_data;
9838         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9839         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9840         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9841         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9842         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9843         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9844         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9845         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9846         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9847         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9848         struct mlx5_ifc_ppll_reg_bits ppll_reg;
9849         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9850         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9851         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9852         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9853         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9854         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9855         struct mlx5_ifc_pude_reg_bits pude_reg;
9856         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9857         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9858         struct mlx5_ifc_slrp_reg_bits slrp_reg;
9859         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9860         u8         reserved_0[0x7880];
9861 };
9862
9863 union mlx5_ifc_debug_enhancements_document_bits {
9864         struct mlx5_ifc_health_buffer_bits health_buffer;
9865         u8         reserved_0[0x200];
9866 };
9867
9868 union mlx5_ifc_no_dram_nic_document_bits {
9869         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9870         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9871         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9872         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9873         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9874         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9875         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9876         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9877         u8         reserved_0[0x3160];
9878 };
9879
9880 union mlx5_ifc_uplink_pci_interface_document_bits {
9881         struct mlx5_ifc_initial_seg_bits initial_seg;
9882         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9883         u8         reserved_0[0x20120];
9884 };
9885
9886 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9887         u8         e[0x1];
9888         u8         reserved_at_01[0x0b];
9889         u8         prio[0x04];
9890 };
9891
9892 struct mlx5_ifc_qpdpm_reg_bits {
9893         u8                                     reserved_at_0[0x8];
9894         u8                                     local_port[0x8];
9895         u8                                     reserved_at_10[0x10];
9896         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9897 };
9898
9899 struct mlx5_ifc_qpts_reg_bits {
9900         u8         reserved_at_0[0x8];
9901         u8         local_port[0x8];
9902         u8         reserved_at_10[0x2d];
9903         u8         trust_state[0x3];
9904 };
9905
9906 #endif /* MLX5_IFC_H */