sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 enum {
  32         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  33         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  34         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  35         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  36         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  37         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  38         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  39         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  40         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  41         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  42         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  43         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  44         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  45         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  46         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  47         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  48         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  49         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  50         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  51         MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
  52         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  53         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  54         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  55         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  56         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  57         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  58         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  59         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  60         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  61         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
  62 };
  63
  64 enum {
  65         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  66         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  67         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  68         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  69         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  70 };
  71
  72 enum {
  73         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  74 };
  75
  76 enum {
  77         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  78         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  79 };
  80
  81 enum {
  82         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  83         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  84         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  85         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  86         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  87         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  88         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  89         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  90         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  91         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  92         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  93         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  94         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
  95         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
  96         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  97         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  98         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  99         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 100         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 101         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 102         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 103         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 104         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 105         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 106         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 107         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 108         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 109         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 110         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 111         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 112         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 113         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 114         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 115         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 116         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 117         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 118         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 119         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 120         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 121         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 122         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 123         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 124         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 125         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 126         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 127         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 128         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 129         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 130         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 131         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 132         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 133         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 134         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 135         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 136         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 137         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 138         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 139         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 140         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 141         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 142         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 143         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 144         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 145         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 146         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 147         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 148         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 149         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 150         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 151         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 152         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 153         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 154         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 155         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 156         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 157         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 158         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 159         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 160         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 161         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 162         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 163         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 164         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 165         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 166         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 167         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 168         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 169         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 170         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 171         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 172         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 173         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 174         MLX5_CMD_OP_NOP                           = 0x80d,
 175         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 176         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 177         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 178         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 179         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 180         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 181         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 182         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 183         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 184         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 185         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 186         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 187         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 188         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 189         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 190         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 191         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 192         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 193         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 194         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 195         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 196         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 197         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 198         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 199         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 200         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 201         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 202         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 203         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 204         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 205         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 206         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 207         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 208         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 209         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 210         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 211         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 212         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 213         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 214         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 215         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 216         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 217         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 218         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 219         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 220         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 221         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 222         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 223         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 224         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 225         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 226         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 227         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 228         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 229         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 230         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 231         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 232         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 233         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 234         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 235         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 236         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 237         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 238         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 239         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 240         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 241         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 242         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 243         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 244         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 245 };
 246
 247 enum {
 248         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 249         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 250         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 251         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 252         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 253         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 254         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 255         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 256         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 257         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 258         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 259         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 260 };
 261
 262 struct mlx5_ifc_flow_table_fields_supported_bits {
 263         u8         outer_dmac[0x1];
 264         u8         outer_smac[0x1];
 265         u8         outer_ether_type[0x1];
 266         u8         reserved_0[0x1];
 267         u8         outer_first_prio[0x1];
 268         u8         outer_first_cfi[0x1];
 269         u8         outer_first_vid[0x1];
 270         u8         reserved_1[0x1];
 271         u8         outer_second_prio[0x1];
 272         u8         outer_second_cfi[0x1];
 273         u8         outer_second_vid[0x1];
 274         u8         outer_ipv6_flow_label[0x1];
 275         u8         outer_sip[0x1];
 276         u8         outer_dip[0x1];
 277         u8         outer_frag[0x1];
 278         u8         outer_ip_protocol[0x1];
 279         u8         outer_ip_ecn[0x1];
 280         u8         outer_ip_dscp[0x1];
 281         u8         outer_udp_sport[0x1];
 282         u8         outer_udp_dport[0x1];
 283         u8         outer_tcp_sport[0x1];
 284         u8         outer_tcp_dport[0x1];
 285         u8         outer_tcp_flags[0x1];
 286         u8         outer_gre_protocol[0x1];
 287         u8         outer_gre_key[0x1];
 288         u8         outer_vxlan_vni[0x1];
 289         u8         outer_geneve_vni[0x1];
 290         u8         outer_geneve_oam[0x1];
 291         u8         outer_geneve_protocol_type[0x1];
 292         u8         outer_geneve_opt_len[0x1];
 293         u8         reserved_2[0x1];
 294         u8         source_eswitch_port[0x1];
 295
 296         u8         inner_dmac[0x1];
 297         u8         inner_smac[0x1];
 298         u8         inner_ether_type[0x1];
 299         u8         reserved_3[0x1];
 300         u8         inner_first_prio[0x1];
 301         u8         inner_first_cfi[0x1];
 302         u8         inner_first_vid[0x1];
 303         u8         reserved_4[0x1];
 304         u8         inner_second_prio[0x1];
 305         u8         inner_second_cfi[0x1];
 306         u8         inner_second_vid[0x1];
 307         u8         inner_ipv6_flow_label[0x1];
 308         u8         inner_sip[0x1];
 309         u8         inner_dip[0x1];
 310         u8         inner_frag[0x1];
 311         u8         inner_ip_protocol[0x1];
 312         u8         inner_ip_ecn[0x1];
 313         u8         inner_ip_dscp[0x1];
 314         u8         inner_udp_sport[0x1];
 315         u8         inner_udp_dport[0x1];
 316         u8         inner_tcp_sport[0x1];
 317         u8         inner_tcp_dport[0x1];
 318         u8         inner_tcp_flags[0x1];
 319         u8         reserved_5[0x9];
 320
 321         u8         reserved_6[0x1a];
 322         u8         bth_dst_qp[0x1];
 323         u8         reserved_7[0x4];
 324         u8         source_sqn[0x1];
 325
 326         u8         reserved_8[0x20];
 327 };
 328
 329 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 330         u8         ingress_general_high[0x20];
 331
 332         u8         ingress_general_low[0x20];
 333
 334         u8         ingress_policy_engine_high[0x20];
 335
 336         u8         ingress_policy_engine_low[0x20];
 337
 338         u8         ingress_vlan_membership_high[0x20];
 339
 340         u8         ingress_vlan_membership_low[0x20];
 341
 342         u8         ingress_tag_frame_type_high[0x20];
 343
 344         u8         ingress_tag_frame_type_low[0x20];
 345
 346         u8         egress_vlan_membership_high[0x20];
 347
 348         u8         egress_vlan_membership_low[0x20];
 349
 350         u8         loopback_filter_high[0x20];
 351
 352         u8         loopback_filter_low[0x20];
 353
 354         u8         egress_general_high[0x20];
 355
 356         u8         egress_general_low[0x20];
 357
 358         u8         reserved_at_1c0[0x40];
 359
 360         u8         egress_hoq_high[0x20];
 361
 362         u8         egress_hoq_low[0x20];
 363
 364         u8         port_isolation_high[0x20];
 365
 366         u8         port_isolation_low[0x20];
 367
 368         u8         egress_policy_engine_high[0x20];
 369
 370         u8         egress_policy_engine_low[0x20];
 371
 372         u8         ingress_tx_link_down_high[0x20];
 373
 374         u8         ingress_tx_link_down_low[0x20];
 375
 376         u8         egress_stp_filter_high[0x20];
 377
 378         u8         egress_stp_filter_low[0x20];
 379
 380         u8         egress_hoq_stall_high[0x20];
 381
 382         u8         egress_hoq_stall_low[0x20];
 383
 384         u8         reserved_at_340[0x440];
 385 };
 386 struct mlx5_ifc_flow_table_prop_layout_bits {
 387         u8         ft_support[0x1];
 388         u8         flow_tag[0x1];
 389         u8         flow_counter[0x1];
 390         u8         flow_modify_en[0x1];
 391         u8         modify_root[0x1];
 392         u8         identified_miss_table[0x1];
 393         u8         flow_table_modify[0x1];
 394         u8         encap[0x1];
 395         u8         decap[0x1];
 396         u8         reset_root_to_default[0x1];
 397         u8         reserved_at_a[0x16];
 398
 399         u8         reserved_at_20[0x2];
 400         u8         log_max_ft_size[0x6];
 401         u8         reserved_at_28[0x10];
 402         u8         max_ft_level[0x8];
 403
 404         u8         reserved_at_40[0x20];
 405
 406         u8         reserved_at_60[0x18];
 407         u8         log_max_ft_num[0x8];
 408
 409         u8         reserved_at_80[0x10];
 410         u8         log_max_flow_counter[0x8];
 411         u8         log_max_destination[0x8];
 412
 413         u8         reserved_at_a0[0x18];
 414         u8         log_max_flow[0x8];
 415
 416         u8         reserved_at_c0[0x40];
 417
 418         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 419
 420         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 421 };
 422
 423 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 424         u8         send[0x1];
 425         u8         receive[0x1];
 426         u8         write[0x1];
 427         u8         read[0x1];
 428         u8         atomic[0x1];
 429         u8         srq_receive[0x1];
 430         u8         reserved_0[0x1a];
 431 };
 432
 433 struct mlx5_ifc_flow_counter_list_bits {
 434         u8         reserved_0[0x10];
 435         u8         flow_counter_id[0x10];
 436
 437         u8         reserved_1[0x20];
 438 };
 439
 440 enum {
 441         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 442         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 443         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 444         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 445 };
 446
 447 struct mlx5_ifc_dest_format_struct_bits {
 448         u8         destination_type[0x8];
 449         u8         destination_id[0x18];
 450
 451         u8         reserved_0[0x20];
 452 };
 453
 454 struct mlx5_ifc_ipv4_layout_bits {
 455         u8         reserved_at_0[0x60];
 456
 457         u8         ipv4[0x20];
 458 };
 459
 460 struct mlx5_ifc_ipv6_layout_bits {
 461         u8         ipv6[16][0x8];
 462 };
 463
 464 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 465         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 466         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 467         u8         reserved_at_0[0x80];
 468 };
 469
 470 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 471         u8         smac_47_16[0x20];
 472
 473         u8         smac_15_0[0x10];
 474         u8         ethertype[0x10];
 475
 476         u8         dmac_47_16[0x20];
 477
 478         u8         dmac_15_0[0x10];
 479         u8         first_prio[0x3];
 480         u8         first_cfi[0x1];
 481         u8         first_vid[0xc];
 482
 483         u8         ip_protocol[0x8];
 484         u8         ip_dscp[0x6];
 485         u8         ip_ecn[0x2];
 486         u8         cvlan_tag[0x1];
 487         u8         svlan_tag[0x1];
 488         u8         frag[0x1];
 489         u8         reserved_1[0x4];
 490         u8         tcp_flags[0x9];
 491
 492         u8         tcp_sport[0x10];
 493         u8         tcp_dport[0x10];
 494
 495         u8         reserved_2[0x20];
 496
 497         u8         udp_sport[0x10];
 498         u8         udp_dport[0x10];
 499
 500         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 501
 502         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 503 };
 504
 505 struct mlx5_ifc_fte_match_set_misc_bits {
 506         u8         reserved_0[0x8];
 507         u8         source_sqn[0x18];
 508
 509         u8         reserved_1[0x10];
 510         u8         source_port[0x10];
 511
 512         u8         outer_second_prio[0x3];
 513         u8         outer_second_cfi[0x1];
 514         u8         outer_second_vid[0xc];
 515         u8         inner_second_prio[0x3];
 516         u8         inner_second_cfi[0x1];
 517         u8         inner_second_vid[0xc];
 518
 519         u8         outer_second_vlan_tag[0x1];
 520         u8         inner_second_vlan_tag[0x1];
 521         u8         reserved_2[0xe];
 522         u8         gre_protocol[0x10];
 523
 524         u8         gre_key_h[0x18];
 525         u8         gre_key_l[0x8];
 526
 527         u8         vxlan_vni[0x18];
 528         u8         reserved_3[0x8];
 529
 530         u8         geneve_vni[0x18];
 531         u8         reserved4[0x7];
 532         u8         geneve_oam[0x1];
 533
 534         u8         reserved_5[0xc];
 535         u8         outer_ipv6_flow_label[0x14];
 536
 537         u8         reserved_6[0xc];
 538         u8         inner_ipv6_flow_label[0x14];
 539
 540         u8         reserved_7[0xa];
 541         u8         geneve_opt_len[0x6];
 542         u8         geneve_protocol_type[0x10];
 543
 544         u8         reserved_8[0x8];
 545         u8         bth_dst_qp[0x18];
 546
 547         u8         reserved_9[0xa0];
 548 };
 549
 550 struct mlx5_ifc_cmd_pas_bits {
 551         u8         pa_h[0x20];
 552
 553         u8         pa_l[0x14];
 554         u8         reserved_0[0xc];
 555 };
 556
 557 struct mlx5_ifc_uint64_bits {
 558         u8         hi[0x20];
 559
 560         u8         lo[0x20];
 561 };
 562
 563 struct mlx5_ifc_application_prio_entry_bits {
 564         u8         reserved_0[0x8];
 565         u8         priority[0x3];
 566         u8         reserved_1[0x2];
 567         u8         sel[0x3];
 568         u8         protocol_id[0x10];
 569 };
 570
 571 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 572         u8         reserved_0[0x8];
 573         u8         ring_pi[0x10];
 574         u8         reserved_1[0x8];
 575 };
 576
 577 enum {
 578         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 579         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 580         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 581         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 582         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 583         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 584         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 585         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 586         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 587         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 588 };
 589
 590 struct mlx5_ifc_ads_bits {
 591         u8         fl[0x1];
 592         u8         free_ar[0x1];
 593         u8         reserved_0[0xe];
 594         u8         pkey_index[0x10];
 595
 596         u8         reserved_1[0x8];
 597         u8         grh[0x1];
 598         u8         mlid[0x7];
 599         u8         rlid[0x10];
 600
 601         u8         ack_timeout[0x5];
 602         u8         reserved_2[0x3];
 603         u8         src_addr_index[0x8];
 604         u8         log_rtm[0x4];
 605         u8         stat_rate[0x4];
 606         u8         hop_limit[0x8];
 607
 608         u8         reserved_3[0x4];
 609         u8         tclass[0x8];
 610         u8         flow_label[0x14];
 611
 612         u8         rgid_rip[16][0x8];
 613
 614         u8         reserved_4[0x4];
 615         u8         f_dscp[0x1];
 616         u8         f_ecn[0x1];
 617         u8         reserved_5[0x1];
 618         u8         f_eth_prio[0x1];
 619         u8         ecn[0x2];
 620         u8         dscp[0x6];
 621         u8         udp_sport[0x10];
 622
 623         u8         dei_cfi[0x1];
 624         u8         eth_prio[0x3];
 625         u8         sl[0x4];
 626         u8         port[0x8];
 627         u8         rmac_47_32[0x10];
 628
 629         u8         rmac_31_0[0x20];
 630 };
 631
 632 struct mlx5_ifc_diagnostic_counter_cap_bits {
 633         u8         sync[0x1];
 634         u8         reserved_0[0xf];
 635         u8         counter_id[0x10];
 636 };
 637
 638 struct mlx5_ifc_debug_cap_bits {
 639         u8         reserved_0[0x18];
 640         u8         log_max_samples[0x8];
 641
 642         u8         single[0x1];
 643         u8         repetitive[0x1];
 644         u8         health_mon_rx_activity[0x1];
 645         u8         reserved_1[0x15];
 646         u8         log_min_sample_period[0x8];
 647
 648         u8         reserved_2[0x1c0];
 649
 650         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 651 };
 652
 653 struct mlx5_ifc_qos_cap_bits {
 654         u8         packet_pacing[0x1];
 655         u8         esw_scheduling[0x1];
 656         u8         esw_bw_share[0x1];
 657         u8         esw_rate_limit[0x1];
 658         u8         hll[0x1];
 659         u8         packet_pacing_burst_bound[0x1];
 660         u8         reserved_at_6[0x1a];
 661
 662         u8         reserved_at_20[0x20];
 663
 664         u8         packet_pacing_max_rate[0x20];
 665
 666         u8         packet_pacing_min_rate[0x20];
 667
 668         u8         reserved_at_80[0x10];
 669         u8         packet_pacing_rate_table_size[0x10];
 670
 671         u8         esw_element_type[0x10];
 672         u8         esw_tsar_type[0x10];
 673
 674         u8         reserved_at_c0[0x10];
 675         u8         max_qos_para_vport[0x10];
 676
 677         u8         max_tsar_bw_share[0x20];
 678
 679         u8         reserved_at_100[0x700];
 680 };
 681
 682 struct mlx5_ifc_snapshot_cap_bits {
 683         u8         reserved_0[0x1d];
 684         u8         suspend_qp_uc[0x1];
 685         u8         suspend_qp_ud[0x1];
 686         u8         suspend_qp_rc[0x1];
 687
 688         u8         reserved_1[0x1c];
 689         u8         restore_pd[0x1];
 690         u8         restore_uar[0x1];
 691         u8         restore_mkey[0x1];
 692         u8         restore_qp[0x1];
 693
 694         u8         reserved_2[0x1e];
 695         u8         named_mkey[0x1];
 696         u8         named_qp[0x1];
 697
 698         u8         reserved_3[0x7a0];
 699 };
 700
 701 struct mlx5_ifc_e_switch_cap_bits {
 702         u8         vport_svlan_strip[0x1];
 703         u8         vport_cvlan_strip[0x1];
 704         u8         vport_svlan_insert[0x1];
 705         u8         vport_cvlan_insert_if_not_exist[0x1];
 706         u8         vport_cvlan_insert_overwrite[0x1];
 707
 708         u8         reserved_0[0x19];
 709
 710         u8         nic_vport_node_guid_modify[0x1];
 711         u8         nic_vport_port_guid_modify[0x1];
 712
 713         u8         reserved_1[0x7e0];
 714 };
 715
 716 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 717         u8         reserved_0[0x200];
 718
 719         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 720
 721         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 722
 723         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 724
 725         u8         reserved_1[0x7800];
 726 };
 727
 728 struct mlx5_ifc_flow_table_nic_cap_bits {
 729         u8         nic_rx_multi_path_tirs[0x1];
 730         u8         nic_rx_multi_path_tirs_fts[0x1];
 731         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 732         u8         reserved_at_3[0x1fd];
 733
 734         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 735
 736         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 737
 738         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 739
 740         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 741
 742         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 743
 744         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 745
 746         u8         reserved_1[0x7200];
 747 };
 748
 749 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 750         u8         csum_cap[0x1];
 751         u8         vlan_cap[0x1];
 752         u8         lro_cap[0x1];
 753         u8         lro_psh_flag[0x1];
 754         u8         lro_time_stamp[0x1];
 755         u8         lro_max_msg_sz_mode[0x2];
 756         u8         wqe_vlan_insert[0x1];
 757         u8         self_lb_en_modifiable[0x1];
 758         u8         self_lb_mc[0x1];
 759         u8         self_lb_uc[0x1];
 760         u8         max_lso_cap[0x5];
 761         u8         multi_pkt_send_wqe[0x2];
 762         u8         wqe_inline_mode[0x2];
 763         u8         rss_ind_tbl_cap[0x4];
 764         u8         reserved_1[0x3];
 765         u8         tunnel_lso_const_out_ip_id[0x1];
 766         u8         tunnel_lro_gre[0x1];
 767         u8         tunnel_lro_vxlan[0x1];
 768         u8         tunnel_statless_gre[0x1];
 769         u8         tunnel_stateless_vxlan[0x1];
 770
 771         u8         swp[0x1];
 772         u8         swp_csum[0x1];
 773         u8         swp_lso[0x1];
 774         u8         reserved_2[0x1b];
 775         u8         max_geneve_opt_len[0x1];
 776         u8         tunnel_stateless_geneve_rx[0x1];
 777
 778         u8         reserved_3[0x10];
 779         u8         lro_min_mss_size[0x10];
 780
 781         u8         reserved_4[0x120];
 782
 783         u8         lro_timer_supported_periods[4][0x20];
 784
 785         u8         reserved_5[0x600];
 786 };
 787
 788 enum {
 789         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 790         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 791         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 792 };
 793
 794 struct mlx5_ifc_roce_cap_bits {
 795         u8         roce_apm[0x1];
 796         u8         rts2rts_primary_eth_prio[0x1];
 797         u8         roce_rx_allow_untagged[0x1];
 798         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 799
 800         u8         reserved_0[0x1c];
 801
 802         u8         reserved_1[0x60];
 803
 804         u8         reserved_2[0xc];
 805         u8         l3_type[0x4];
 806         u8         reserved_3[0x8];
 807         u8         roce_version[0x8];
 808
 809         u8         reserved_4[0x10];
 810         u8         r_roce_dest_udp_port[0x10];
 811
 812         u8         r_roce_max_src_udp_port[0x10];
 813         u8         r_roce_min_src_udp_port[0x10];
 814
 815         u8         reserved_5[0x10];
 816         u8         roce_address_table_size[0x10];
 817
 818         u8         reserved_6[0x700];
 819 };
 820
 821 enum {
 822         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 823         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 824         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 825         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 826         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 827         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 828         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 829         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 830         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 831 };
 832
 833 enum {
 834         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 835         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 836         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 837         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 838         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 839         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 840         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 841         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 842         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 843 };
 844
 845 struct mlx5_ifc_atomic_caps_bits {
 846         u8         reserved_0[0x40];
 847
 848         u8         atomic_req_8B_endianess_mode[0x2];
 849         u8         reserved_1[0x4];
 850         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 851
 852         u8         reserved_2[0x19];
 853
 854         u8         reserved_3[0x20];
 855
 856         u8         reserved_4[0x10];
 857         u8         atomic_operations[0x10];
 858
 859         u8         reserved_5[0x10];
 860         u8         atomic_size_qp[0x10];
 861
 862         u8         reserved_6[0x10];
 863         u8         atomic_size_dc[0x10];
 864
 865         u8         reserved_7[0x720];
 866 };
 867
 868 struct mlx5_ifc_odp_cap_bits {
 869         u8         reserved_0[0x40];
 870
 871         u8         sig[0x1];
 872         u8         reserved_1[0x1f];
 873
 874         u8         reserved_2[0x20];
 875
 876         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 877
 878         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 879
 880         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 881
 882         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 883
 884         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
 885
 886         u8         reserved_3[0x6e0];
 887 };
 888
 889 enum {
 890         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 891         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 892         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 893         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 894         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 895 };
 896
 897 enum {
 898         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 899         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 900         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 901         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 902         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 903         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 904 };
 905
 906 enum {
 907         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 908         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 909 };
 910
 911 enum {
 912         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 913         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 914         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 915 };
 916
 917 struct mlx5_ifc_cmd_hca_cap_bits {
 918         u8         reserved_0[0x80];
 919
 920         u8         log_max_srq_sz[0x8];
 921         u8         log_max_qp_sz[0x8];
 922         u8         reserved_1[0xb];
 923         u8         log_max_qp[0x5];
 924
 925         u8         reserved_2[0xb];
 926         u8         log_max_srq[0x5];
 927         u8         reserved_3[0x10];
 928
 929         u8         reserved_4[0x8];
 930         u8         log_max_cq_sz[0x8];
 931         u8         reserved_5[0xb];
 932         u8         log_max_cq[0x5];
 933
 934         u8         log_max_eq_sz[0x8];
 935         u8         reserved_6[0x2];
 936         u8         log_max_mkey[0x6];
 937         u8         reserved_7[0xc];
 938         u8         log_max_eq[0x4];
 939
 940         u8         max_indirection[0x8];
 941         u8         reserved_8[0x1];
 942         u8         log_max_mrw_sz[0x7];
 943         u8         reserved_9[0x2];
 944         u8         log_max_bsf_list_size[0x6];
 945         u8         reserved_10[0x2];
 946         u8         log_max_klm_list_size[0x6];
 947
 948         u8         reserved_11[0xa];
 949         u8         log_max_ra_req_dc[0x6];
 950         u8         reserved_12[0xa];
 951         u8         log_max_ra_res_dc[0x6];
 952
 953         u8         reserved_13[0xa];
 954         u8         log_max_ra_req_qp[0x6];
 955         u8         reserved_14[0xa];
 956         u8         log_max_ra_res_qp[0x6];
 957
 958         u8         pad_cap[0x1];
 959         u8         cc_query_allowed[0x1];
 960         u8         cc_modify_allowed[0x1];
 961         u8         start_pad[0x1];
 962         u8         cache_line_128byte[0x1];
 963         u8         reserved_15[0xb];
 964         u8         gid_table_size[0x10];
 965
 966         u8         out_of_seq_cnt[0x1];
 967         u8         vport_counters[0x1];
 968         u8         retransmission_q_counters[0x1];
 969         u8         debug[0x1];
 970         u8         modify_rq_counters_set_id[0x1];
 971         u8         rq_delay_drop[0x1];
 972         u8         max_qp_cnt[0xa];
 973         u8         pkey_table_size[0x10];
 974
 975         u8         vport_group_manager[0x1];
 976         u8         vhca_group_manager[0x1];
 977         u8         ib_virt[0x1];
 978         u8         eth_virt[0x1];
 979         u8         reserved_17[0x1];
 980         u8         ets[0x1];
 981         u8         nic_flow_table[0x1];
 982         u8         eswitch_flow_table[0x1];
 983         u8         reserved_18[0x3];
 984         u8         local_ca_ack_delay[0x5];
 985         u8         port_module_event[0x1];
 986         u8         reserved_19[0x5];
 987         u8         port_type[0x2];
 988         u8         num_ports[0x8];
 989
 990         u8         snapshot[0x1];
 991         u8         reserved_20[0x2];
 992         u8         log_max_msg[0x5];
 993         u8         reserved_21[0x4];
 994         u8         max_tc[0x4];
 995         u8         temp_warn_event[0x1];
 996         u8         dcbx[0x1];
 997         u8         reserved_22[0x4];
 998         u8         rol_s[0x1];
 999         u8         rol_g[0x1];
1000         u8         reserved_23[0x1];
1001         u8         wol_s[0x1];
1002         u8         wol_g[0x1];
1003         u8         wol_a[0x1];
1004         u8         wol_b[0x1];
1005         u8         wol_m[0x1];
1006         u8         wol_u[0x1];
1007         u8         wol_p[0x1];
1008
1009         u8         stat_rate_support[0x10];
1010         u8         reserved_24[0xc];
1011         u8         cqe_version[0x4];
1012
1013         u8         compact_address_vector[0x1];
1014         u8         striding_rq[0x1];
1015         u8         reserved_25[0x1];
1016         u8         ipoib_enhanced_offloads[0x1];
1017         u8         ipoib_ipoib_offloads[0x1];
1018         u8         reserved_26[0x8];
1019         u8         dc_connect_qp[0x1];
1020         u8         dc_cnak_trace[0x1];
1021         u8         drain_sigerr[0x1];
1022         u8         cmdif_checksum[0x2];
1023         u8         sigerr_cqe[0x1];
1024         u8         reserved_27[0x1];
1025         u8         wq_signature[0x1];
1026         u8         sctr_data_cqe[0x1];
1027         u8         reserved_28[0x1];
1028         u8         sho[0x1];
1029         u8         tph[0x1];
1030         u8         rf[0x1];
1031         u8         dct[0x1];
1032         u8         qos[0x1];
1033         u8         eth_net_offloads[0x1];
1034         u8         roce[0x1];
1035         u8         atomic[0x1];
1036         u8         reserved_30[0x1];
1037
1038         u8         cq_oi[0x1];
1039         u8         cq_resize[0x1];
1040         u8         cq_moderation[0x1];
1041         u8         cq_period_mode_modify[0x1];
1042         u8         cq_invalidate[0x1];
1043         u8         reserved_at_225[0x1];
1044         u8         cq_eq_remap[0x1];
1045         u8         pg[0x1];
1046         u8         block_lb_mc[0x1];
1047         u8         exponential_backoff[0x1];
1048         u8         scqe_break_moderation[0x1];
1049         u8         cq_period_start_from_cqe[0x1];
1050         u8         cd[0x1];
1051         u8         atm[0x1];
1052         u8         apm[0x1];
1053         u8         reserved_32[0x7];
1054         u8         qkv[0x1];
1055         u8         pkv[0x1];
1056         u8         reserved_33[0x4];
1057         u8         xrc[0x1];
1058         u8         ud[0x1];
1059         u8         uc[0x1];
1060         u8         rc[0x1];
1061
1062         u8         reserved_34[0xa];
1063         u8         uar_sz[0x6];
1064         u8         reserved_35[0x8];
1065         u8         log_pg_sz[0x8];
1066
1067         u8         bf[0x1];
1068         u8         driver_version[0x1];
1069         u8         pad_tx_eth_packet[0x1];
1070         u8         reserved_36[0x8];
1071         u8         log_bf_reg_size[0x5];
1072         u8         reserved_37[0x10];
1073
1074         u8         num_of_diagnostic_counters[0x10];
1075         u8         max_wqe_sz_sq[0x10];
1076
1077         u8         reserved_38[0x10];
1078         u8         max_wqe_sz_rq[0x10];
1079
1080         u8         reserved_39[0x10];
1081         u8         max_wqe_sz_sq_dc[0x10];
1082
1083         u8         reserved_40[0x7];
1084         u8         max_qp_mcg[0x19];
1085
1086         u8         reserved_41[0x18];
1087         u8         log_max_mcg[0x8];
1088
1089         u8         reserved_42[0x3];
1090         u8         log_max_transport_domain[0x5];
1091         u8         reserved_43[0x3];
1092         u8         log_max_pd[0x5];
1093         u8         reserved_44[0xb];
1094         u8         log_max_xrcd[0x5];
1095
1096         u8         reserved_45[0x10];
1097         u8         max_flow_counter[0x10];
1098
1099         u8         reserved_46[0x3];
1100         u8         log_max_rq[0x5];
1101         u8         reserved_47[0x3];
1102         u8         log_max_sq[0x5];
1103         u8         reserved_48[0x3];
1104         u8         log_max_tir[0x5];
1105         u8         reserved_49[0x3];
1106         u8         log_max_tis[0x5];
1107
1108         u8         basic_cyclic_rcv_wqe[0x1];
1109         u8         reserved_50[0x2];
1110         u8         log_max_rmp[0x5];
1111         u8         reserved_51[0x3];
1112         u8         log_max_rqt[0x5];
1113         u8         reserved_52[0x3];
1114         u8         log_max_rqt_size[0x5];
1115         u8         reserved_53[0x3];
1116         u8         log_max_tis_per_sq[0x5];
1117
1118         u8         reserved_54[0x3];
1119         u8         log_max_stride_sz_rq[0x5];
1120         u8         reserved_55[0x3];
1121         u8         log_min_stride_sz_rq[0x5];
1122         u8         reserved_56[0x3];
1123         u8         log_max_stride_sz_sq[0x5];
1124         u8         reserved_57[0x3];
1125         u8         log_min_stride_sz_sq[0x5];
1126
1127         u8         reserved_58[0x1b];
1128         u8         log_max_wq_sz[0x5];
1129
1130         u8         nic_vport_change_event[0x1];
1131         u8         disable_local_lb[0x1];
1132         u8         reserved_59[0x9];
1133         u8         log_max_vlan_list[0x5];
1134         u8         reserved_60[0x3];
1135         u8         log_max_current_mc_list[0x5];
1136         u8         reserved_61[0x3];
1137         u8         log_max_current_uc_list[0x5];
1138
1139         u8         reserved_62[0x80];
1140
1141         u8         reserved_63[0x3];
1142         u8         log_max_l2_table[0x5];
1143         u8         reserved_64[0x8];
1144         u8         log_uar_page_sz[0x10];
1145
1146         u8         reserved_65[0x20];
1147
1148         u8         device_frequency_mhz[0x20];
1149
1150         u8         device_frequency_khz[0x20];
1151
1152         u8         reserved_66[0x80];
1153
1154         u8         log_max_atomic_size_qp[0x8];
1155         u8         reserved_67[0x10];
1156         u8         log_max_atomic_size_dc[0x8];
1157
1158         u8         reserved_68[0x1f];
1159         u8         cqe_compression[0x1];
1160
1161         u8         cqe_compression_timeout[0x10];
1162         u8         cqe_compression_max_num[0x10];
1163
1164         u8         reserved_69[0x220];
1165 };
1166
1167 enum mlx5_flow_destination_type {
1168         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1169         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1170         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1171 };
1172
1173 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1174         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1175         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1176         u8         reserved_0[0x40];
1177 };
1178
1179 struct mlx5_ifc_fte_match_param_bits {
1180         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1181
1182         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1183
1184         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1185
1186         u8         reserved_0[0xa00];
1187 };
1188
1189 enum {
1190         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1191         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1192         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1193         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1194         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1195 };
1196
1197 struct mlx5_ifc_rx_hash_field_select_bits {
1198         u8         l3_prot_type[0x1];
1199         u8         l4_prot_type[0x1];
1200         u8         selected_fields[0x1e];
1201 };
1202
1203 enum {
1204         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1205         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1206         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1207         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1208 };
1209
1210 enum rq_type {
1211         RQ_TYPE_NONE,
1212         RQ_TYPE_STRIDE,
1213 };
1214
1215 enum {
1216         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1217         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1218 };
1219
1220 struct mlx5_ifc_wq_bits {
1221         u8         wq_type[0x4];
1222         u8         wq_signature[0x1];
1223         u8         end_padding_mode[0x2];
1224         u8         cd_slave[0x1];
1225         u8         reserved_0[0x18];
1226
1227         u8         hds_skip_first_sge[0x1];
1228         u8         log2_hds_buf_size[0x3];
1229         u8         reserved_1[0x7];
1230         u8         page_offset[0x5];
1231         u8         lwm[0x10];
1232
1233         u8         reserved_2[0x8];
1234         u8         pd[0x18];
1235
1236         u8         reserved_3[0x8];
1237         u8         uar_page[0x18];
1238
1239         u8         dbr_addr[0x40];
1240
1241         u8         hw_counter[0x20];
1242
1243         u8         sw_counter[0x20];
1244
1245         u8         reserved_4[0xc];
1246         u8         log_wq_stride[0x4];
1247         u8         reserved_5[0x3];
1248         u8         log_wq_pg_sz[0x5];
1249         u8         reserved_6[0x3];
1250         u8         log_wq_sz[0x5];
1251
1252         u8         reserved_7[0x15];
1253         u8         single_wqe_log_num_of_strides[0x3];
1254         u8         two_byte_shift_en[0x1];
1255         u8         reserved_8[0x4];
1256         u8         single_stride_log_num_of_bytes[0x3];
1257
1258         u8         reserved_9[0x4c0];
1259
1260         struct mlx5_ifc_cmd_pas_bits pas[0];
1261 };
1262
1263 struct mlx5_ifc_rq_num_bits {
1264         u8         reserved_0[0x8];
1265         u8         rq_num[0x18];
1266 };
1267
1268 struct mlx5_ifc_mac_address_layout_bits {
1269         u8         reserved_0[0x10];
1270         u8         mac_addr_47_32[0x10];
1271
1272         u8         mac_addr_31_0[0x20];
1273 };
1274
1275 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1276         u8         reserved_0[0xa0];
1277
1278         u8         min_time_between_cnps[0x20];
1279
1280         u8         reserved_1[0x12];
1281         u8         cnp_dscp[0x6];
1282         u8         reserved_2[0x4];
1283         u8         cnp_prio_mode[0x1];
1284         u8         cnp_802p_prio[0x3];
1285
1286         u8         reserved_3[0x720];
1287 };
1288
1289 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1290         u8         reserved_0[0x60];
1291
1292         u8         reserved_1[0x4];
1293         u8         clamp_tgt_rate[0x1];
1294         u8         reserved_2[0x3];
1295         u8         clamp_tgt_rate_after_time_inc[0x1];
1296         u8         reserved_3[0x17];
1297
1298         u8         reserved_4[0x20];
1299
1300         u8         rpg_time_reset[0x20];
1301
1302         u8         rpg_byte_reset[0x20];
1303
1304         u8         rpg_threshold[0x20];
1305
1306         u8         rpg_max_rate[0x20];
1307
1308         u8         rpg_ai_rate[0x20];
1309
1310         u8         rpg_hai_rate[0x20];
1311
1312         u8         rpg_gd[0x20];
1313
1314         u8         rpg_min_dec_fac[0x20];
1315
1316         u8         rpg_min_rate[0x20];
1317
1318         u8         reserved_5[0xe0];
1319
1320         u8         rate_to_set_on_first_cnp[0x20];
1321
1322         u8         dce_tcp_g[0x20];
1323
1324         u8         dce_tcp_rtt[0x20];
1325
1326         u8         rate_reduce_monitor_period[0x20];
1327
1328         u8         reserved_6[0x20];
1329
1330         u8         initial_alpha_value[0x20];
1331
1332         u8         reserved_7[0x4a0];
1333 };
1334
1335 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1336         u8         reserved_0[0x80];
1337
1338         u8         rppp_max_rps[0x20];
1339
1340         u8         rpg_time_reset[0x20];
1341
1342         u8         rpg_byte_reset[0x20];
1343
1344         u8         rpg_threshold[0x20];
1345
1346         u8         rpg_max_rate[0x20];
1347
1348         u8         rpg_ai_rate[0x20];
1349
1350         u8         rpg_hai_rate[0x20];
1351
1352         u8         rpg_gd[0x20];
1353
1354         u8         rpg_min_dec_fac[0x20];
1355
1356         u8         rpg_min_rate[0x20];
1357
1358         u8         reserved_1[0x640];
1359 };
1360
1361 enum {
1362         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1363         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1364         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1365 };
1366
1367 struct mlx5_ifc_resize_field_select_bits {
1368         u8         resize_field_select[0x20];
1369 };
1370
1371 enum {
1372         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1373         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1374         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1375         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1376         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1377         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1378 };
1379
1380 struct mlx5_ifc_modify_field_select_bits {
1381         u8         modify_field_select[0x20];
1382 };
1383
1384 struct mlx5_ifc_field_select_r_roce_np_bits {
1385         u8         field_select_r_roce_np[0x20];
1386 };
1387
1388 enum {
1389         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1390         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1391         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1392         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1393         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1394         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1395         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1396         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1397         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1398         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1399         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1400         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1401         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1402         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1403         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1404 };
1405
1406 struct mlx5_ifc_field_select_r_roce_rp_bits {
1407         u8         field_select_r_roce_rp[0x20];
1408 };
1409
1410 enum {
1411         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1412         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1413         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1414         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1415         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1416         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1417         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1418         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1419         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1420         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1421 };
1422
1423 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1424         u8         field_select_8021qaurp[0x20];
1425 };
1426
1427 struct mlx5_ifc_pptb_reg_bits {
1428         u8         reserved_0[0x2];
1429         u8         mm[0x2];
1430         u8         reserved_1[0x4];
1431         u8         local_port[0x8];
1432         u8         reserved_2[0x6];
1433         u8         cm[0x1];
1434         u8         um[0x1];
1435         u8         pm[0x8];
1436
1437         u8         prio7buff[0x4];
1438         u8         prio6buff[0x4];
1439         u8         prio5buff[0x4];
1440         u8         prio4buff[0x4];
1441         u8         prio3buff[0x4];
1442         u8         prio2buff[0x4];
1443         u8         prio1buff[0x4];
1444         u8         prio0buff[0x4];
1445
1446         u8         pm_msb[0x8];
1447         u8         reserved_3[0x10];
1448         u8         ctrl_buff[0x4];
1449         u8         untagged_buff[0x4];
1450 };
1451
1452 struct mlx5_ifc_dcbx_app_reg_bits {
1453         u8         reserved_0[0x8];
1454         u8         port_number[0x8];
1455         u8         reserved_1[0x10];
1456
1457         u8         reserved_2[0x1a];
1458         u8         num_app_prio[0x6];
1459
1460         u8         reserved_3[0x40];
1461
1462         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1463 };
1464
1465 struct mlx5_ifc_dcbx_param_reg_bits {
1466         u8         dcbx_cee_cap[0x1];
1467         u8         dcbx_ieee_cap[0x1];
1468         u8         dcbx_standby_cap[0x1];
1469         u8         reserved_0[0x5];
1470         u8         port_number[0x8];
1471         u8         reserved_1[0xa];
1472         u8         max_application_table_size[0x6];
1473
1474         u8         reserved_2[0x15];
1475         u8         version_oper[0x3];
1476         u8         reserved_3[0x5];
1477         u8         version_admin[0x3];
1478
1479         u8         willing_admin[0x1];
1480         u8         reserved_4[0x3];
1481         u8         pfc_cap_oper[0x4];
1482         u8         reserved_5[0x4];
1483         u8         pfc_cap_admin[0x4];
1484         u8         reserved_6[0x4];
1485         u8         num_of_tc_oper[0x4];
1486         u8         reserved_7[0x4];
1487         u8         num_of_tc_admin[0x4];
1488
1489         u8         remote_willing[0x1];
1490         u8         reserved_8[0x3];
1491         u8         remote_pfc_cap[0x4];
1492         u8         reserved_9[0x14];
1493         u8         remote_num_of_tc[0x4];
1494
1495         u8         reserved_10[0x18];
1496         u8         error[0x8];
1497
1498         u8         reserved_11[0x160];
1499 };
1500
1501 struct mlx5_ifc_qhll_bits {
1502         u8         reserved_at_0[0x8];
1503         u8         local_port[0x8];
1504         u8         reserved_at_10[0x10];
1505
1506         u8         reserved_at_20[0x1b];
1507         u8         hll_time[0x5];
1508
1509         u8         stall_en[0x1];
1510         u8         reserved_at_41[0x1c];
1511         u8         stall_cnt[0x3];
1512 };
1513
1514 struct mlx5_ifc_qetcr_reg_bits {
1515         u8         operation_type[0x2];
1516         u8         cap_local_admin[0x1];
1517         u8         cap_remote_admin[0x1];
1518         u8         reserved_0[0x4];
1519         u8         port_number[0x8];
1520         u8         reserved_1[0x10];
1521
1522         u8         reserved_2[0x20];
1523
1524         u8         tc[8][0x40];
1525
1526         u8         global_configuration[0x40];
1527 };
1528
1529 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1530         u8         queue_address_63_32[0x20];
1531
1532         u8         queue_address_31_12[0x14];
1533         u8         reserved_0[0x6];
1534         u8         log_size[0x6];
1535
1536         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1537
1538         u8         reserved_1[0x8];
1539         u8         queue_number[0x18];
1540
1541         u8         q_key[0x20];
1542
1543         u8         reserved_2[0x10];
1544         u8         pkey_index[0x10];
1545
1546         u8         reserved_3[0x40];
1547 };
1548
1549 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1550         u8         reserved_0[0x8];
1551         u8         cq_ci[0x10];
1552         u8         reserved_1[0x8];
1553 };
1554
1555 enum {
1556         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1557         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1558 };
1559
1560 enum {
1561         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1562         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1563         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1564         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1565 };
1566
1567 struct mlx5_ifc_nodnic_event_word_bits {
1568         u8         driver_reset_needed[0x1];
1569         u8         port_management_change_event[0x1];
1570         u8         reserved_0[0x19];
1571         u8         link_type[0x1];
1572         u8         port_state[0x4];
1573 };
1574
1575 struct mlx5_ifc_nic_vport_change_event_bits {
1576         u8         reserved_0[0x10];
1577         u8         vport_num[0x10];
1578
1579         u8         reserved_1[0xc0];
1580 };
1581
1582 struct mlx5_ifc_pages_req_event_bits {
1583         u8         reserved_0[0x10];
1584         u8         function_id[0x10];
1585
1586         u8         num_pages[0x20];
1587
1588         u8         reserved_1[0xa0];
1589 };
1590
1591 struct mlx5_ifc_cmd_inter_comp_event_bits {
1592         u8         command_completion_vector[0x20];
1593
1594         u8         reserved_0[0xc0];
1595 };
1596
1597 struct mlx5_ifc_stall_vl_event_bits {
1598         u8         reserved_0[0x18];
1599         u8         port_num[0x1];
1600         u8         reserved_1[0x3];
1601         u8         vl[0x4];
1602
1603         u8         reserved_2[0xa0];
1604 };
1605
1606 struct mlx5_ifc_db_bf_congestion_event_bits {
1607         u8         event_subtype[0x8];
1608         u8         reserved_0[0x8];
1609         u8         congestion_level[0x8];
1610         u8         reserved_1[0x8];
1611
1612         u8         reserved_2[0xa0];
1613 };
1614
1615 struct mlx5_ifc_gpio_event_bits {
1616         u8         reserved_0[0x60];
1617
1618         u8         gpio_event_hi[0x20];
1619
1620         u8         gpio_event_lo[0x20];
1621
1622         u8         reserved_1[0x40];
1623 };
1624
1625 struct mlx5_ifc_port_state_change_event_bits {
1626         u8         reserved_0[0x40];
1627
1628         u8         port_num[0x4];
1629         u8         reserved_1[0x1c];
1630
1631         u8         reserved_2[0x80];
1632 };
1633
1634 struct mlx5_ifc_dropped_packet_logged_bits {
1635         u8         reserved_0[0xe0];
1636 };
1637
1638 enum {
1639         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1640         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1641 };
1642
1643 struct mlx5_ifc_cq_error_bits {
1644         u8         reserved_0[0x8];
1645         u8         cqn[0x18];
1646
1647         u8         reserved_1[0x20];
1648
1649         u8         reserved_2[0x18];
1650         u8         syndrome[0x8];
1651
1652         u8         reserved_3[0x80];
1653 };
1654
1655 struct mlx5_ifc_rdma_page_fault_event_bits {
1656         u8         bytes_commited[0x20];
1657
1658         u8         r_key[0x20];
1659
1660         u8         reserved_0[0x10];
1661         u8         packet_len[0x10];
1662
1663         u8         rdma_op_len[0x20];
1664
1665         u8         rdma_va[0x40];
1666
1667         u8         reserved_1[0x5];
1668         u8         rdma[0x1];
1669         u8         write[0x1];
1670         u8         requestor[0x1];
1671         u8         qp_number[0x18];
1672 };
1673
1674 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1675         u8         bytes_committed[0x20];
1676
1677         u8         reserved_0[0x10];
1678         u8         wqe_index[0x10];
1679
1680         u8         reserved_1[0x10];
1681         u8         len[0x10];
1682
1683         u8         reserved_2[0x60];
1684
1685         u8         reserved_3[0x5];
1686         u8         rdma[0x1];
1687         u8         write_read[0x1];
1688         u8         requestor[0x1];
1689         u8         qpn[0x18];
1690 };
1691
1692 enum {
1693         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1694         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1695         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1696 };
1697
1698 struct mlx5_ifc_qp_events_bits {
1699         u8         reserved_0[0xa0];
1700
1701         u8         type[0x8];
1702         u8         reserved_1[0x18];
1703
1704         u8         reserved_2[0x8];
1705         u8         qpn_rqn_sqn[0x18];
1706 };
1707
1708 struct mlx5_ifc_dct_events_bits {
1709         u8         reserved_0[0xc0];
1710
1711         u8         reserved_1[0x8];
1712         u8         dct_number[0x18];
1713 };
1714
1715 struct mlx5_ifc_comp_event_bits {
1716         u8         reserved_0[0xc0];
1717
1718         u8         reserved_1[0x8];
1719         u8         cq_number[0x18];
1720 };
1721
1722 struct mlx5_ifc_fw_version_bits {
1723         u8         major[0x10];
1724         u8         reserved_0[0x10];
1725
1726         u8         minor[0x10];
1727         u8         subminor[0x10];
1728
1729         u8         second[0x8];
1730         u8         minute[0x8];
1731         u8         hour[0x8];
1732         u8         reserved_1[0x8];
1733
1734         u8         year[0x10];
1735         u8         month[0x8];
1736         u8         day[0x8];
1737 };
1738
1739 enum {
1740         MLX5_QPC_STATE_RST        = 0x0,
1741         MLX5_QPC_STATE_INIT       = 0x1,
1742         MLX5_QPC_STATE_RTR        = 0x2,
1743         MLX5_QPC_STATE_RTS        = 0x3,
1744         MLX5_QPC_STATE_SQER       = 0x4,
1745         MLX5_QPC_STATE_SQD        = 0x5,
1746         MLX5_QPC_STATE_ERR        = 0x6,
1747         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1748 };
1749
1750 enum {
1751         MLX5_QPC_ST_RC            = 0x0,
1752         MLX5_QPC_ST_UC            = 0x1,
1753         MLX5_QPC_ST_UD            = 0x2,
1754         MLX5_QPC_ST_XRC           = 0x3,
1755         MLX5_QPC_ST_DCI           = 0x5,
1756         MLX5_QPC_ST_QP0           = 0x7,
1757         MLX5_QPC_ST_QP1           = 0x8,
1758         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1759         MLX5_QPC_ST_REG_UMR       = 0xc,
1760 };
1761
1762 enum {
1763         MLX5_QP_PM_ARMED            = 0x0,
1764         MLX5_QP_PM_REARM            = 0x1,
1765         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1766         MLX5_QP_PM_MIGRATED         = 0x3,
1767 };
1768
1769 enum {
1770         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1771         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1772 };
1773
1774 enum {
1775         MLX5_QPC_MTU_256_BYTES        = 0x1,
1776         MLX5_QPC_MTU_512_BYTES        = 0x2,
1777         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1778         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1779         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1780         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1781 };
1782
1783 enum {
1784         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1785         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1786         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1787         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1788         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1789         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1790         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1791         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1792 };
1793
1794 enum {
1795         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1796         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1797         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1798 };
1799
1800 enum {
1801         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1802         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1803         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1804 };
1805
1806 struct mlx5_ifc_qpc_bits {
1807         u8         state[0x4];
1808         u8         reserved_0[0x4];
1809         u8         st[0x8];
1810         u8         reserved_1[0x3];
1811         u8         pm_state[0x2];
1812         u8         reserved_2[0x7];
1813         u8         end_padding_mode[0x2];
1814         u8         reserved_3[0x2];
1815
1816         u8         wq_signature[0x1];
1817         u8         block_lb_mc[0x1];
1818         u8         atomic_like_write_en[0x1];
1819         u8         latency_sensitive[0x1];
1820         u8         reserved_4[0x1];
1821         u8         drain_sigerr[0x1];
1822         u8         reserved_5[0x2];
1823         u8         pd[0x18];
1824
1825         u8         mtu[0x3];
1826         u8         log_msg_max[0x5];
1827         u8         reserved_6[0x1];
1828         u8         log_rq_size[0x4];
1829         u8         log_rq_stride[0x3];
1830         u8         no_sq[0x1];
1831         u8         log_sq_size[0x4];
1832         u8         reserved_7[0x6];
1833         u8         rlky[0x1];
1834         u8         ulp_stateless_offload_mode[0x4];
1835
1836         u8         counter_set_id[0x8];
1837         u8         uar_page[0x18];
1838
1839         u8         reserved_8[0x8];
1840         u8         user_index[0x18];
1841
1842         u8         reserved_9[0x3];
1843         u8         log_page_size[0x5];
1844         u8         remote_qpn[0x18];
1845
1846         struct mlx5_ifc_ads_bits primary_address_path;
1847
1848         struct mlx5_ifc_ads_bits secondary_address_path;
1849
1850         u8         log_ack_req_freq[0x4];
1851         u8         reserved_10[0x4];
1852         u8         log_sra_max[0x3];
1853         u8         reserved_11[0x2];
1854         u8         retry_count[0x3];
1855         u8         rnr_retry[0x3];
1856         u8         reserved_12[0x1];
1857         u8         fre[0x1];
1858         u8         cur_rnr_retry[0x3];
1859         u8         cur_retry_count[0x3];
1860         u8         reserved_13[0x5];
1861
1862         u8         reserved_14[0x20];
1863
1864         u8         reserved_15[0x8];
1865         u8         next_send_psn[0x18];
1866
1867         u8         reserved_16[0x8];
1868         u8         cqn_snd[0x18];
1869
1870         u8         reserved_17[0x40];
1871
1872         u8         reserved_18[0x8];
1873         u8         last_acked_psn[0x18];
1874
1875         u8         reserved_19[0x8];
1876         u8         ssn[0x18];
1877
1878         u8         reserved_20[0x8];
1879         u8         log_rra_max[0x3];
1880         u8         reserved_21[0x1];
1881         u8         atomic_mode[0x4];
1882         u8         rre[0x1];
1883         u8         rwe[0x1];
1884         u8         rae[0x1];
1885         u8         reserved_22[0x1];
1886         u8         page_offset[0x6];
1887         u8         reserved_23[0x3];
1888         u8         cd_slave_receive[0x1];
1889         u8         cd_slave_send[0x1];
1890         u8         cd_master[0x1];
1891
1892         u8         reserved_24[0x3];
1893         u8         min_rnr_nak[0x5];
1894         u8         next_rcv_psn[0x18];
1895
1896         u8         reserved_25[0x8];
1897         u8         xrcd[0x18];
1898
1899         u8         reserved_26[0x8];
1900         u8         cqn_rcv[0x18];
1901
1902         u8         dbr_addr[0x40];
1903
1904         u8         q_key[0x20];
1905
1906         u8         reserved_27[0x5];
1907         u8         rq_type[0x3];
1908         u8         srqn_rmpn[0x18];
1909
1910         u8         reserved_28[0x8];
1911         u8         rmsn[0x18];
1912
1913         u8         hw_sq_wqebb_counter[0x10];
1914         u8         sw_sq_wqebb_counter[0x10];
1915
1916         u8         hw_rq_counter[0x20];
1917
1918         u8         sw_rq_counter[0x20];
1919
1920         u8         reserved_29[0x20];
1921
1922         u8         reserved_30[0xf];
1923         u8         cgs[0x1];
1924         u8         cs_req[0x8];
1925         u8         cs_res[0x8];
1926
1927         u8         dc_access_key[0x40];
1928
1929         u8         rdma_active[0x1];
1930         u8         comm_est[0x1];
1931         u8         suspended[0x1];
1932         u8         reserved_31[0x5];
1933         u8         send_msg_psn[0x18];
1934
1935         u8         reserved_32[0x8];
1936         u8         rcv_msg_psn[0x18];
1937
1938         u8         rdma_va[0x40];
1939
1940         u8         rdma_key[0x20];
1941
1942         u8         reserved_33[0x20];
1943 };
1944
1945 struct mlx5_ifc_roce_addr_layout_bits {
1946         u8         source_l3_address[16][0x8];
1947
1948         u8         reserved_0[0x3];
1949         u8         vlan_valid[0x1];
1950         u8         vlan_id[0xc];
1951         u8         source_mac_47_32[0x10];
1952
1953         u8         source_mac_31_0[0x20];
1954
1955         u8         reserved_1[0x14];
1956         u8         roce_l3_type[0x4];
1957         u8         roce_version[0x8];
1958
1959         u8         reserved_2[0x20];
1960 };
1961
1962 struct mlx5_ifc_rdbc_bits {
1963         u8         reserved_0[0x1c];
1964         u8         type[0x4];
1965
1966         u8         reserved_1[0x20];
1967
1968         u8         reserved_2[0x8];
1969         u8         psn[0x18];
1970
1971         u8         rkey[0x20];
1972
1973         u8         address[0x40];
1974
1975         u8         byte_count[0x20];
1976
1977         u8         reserved_3[0x20];
1978
1979         u8         atomic_resp[32][0x8];
1980 };
1981
1982 enum {
1983         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1984         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1985         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1986         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1987 };
1988
1989 struct mlx5_ifc_flow_context_bits {
1990         u8         reserved_0[0x20];
1991
1992         u8         group_id[0x20];
1993
1994         u8         reserved_1[0x8];
1995         u8         flow_tag[0x18];
1996
1997         u8         reserved_2[0x10];
1998         u8         action[0x10];
1999
2000         u8         reserved_3[0x8];
2001         u8         destination_list_size[0x18];
2002
2003         u8         reserved_4[0x8];
2004         u8         flow_counter_list_size[0x18];
2005
2006         u8         reserved_5[0x140];
2007
2008         struct mlx5_ifc_fte_match_param_bits match_value;
2009
2010         u8         reserved_6[0x600];
2011
2012         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2013 };
2014
2015 enum {
2016         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2017         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2018 };
2019
2020 struct mlx5_ifc_xrc_srqc_bits {
2021         u8         state[0x4];
2022         u8         log_xrc_srq_size[0x4];
2023         u8         reserved_0[0x18];
2024
2025         u8         wq_signature[0x1];
2026         u8         cont_srq[0x1];
2027         u8         reserved_1[0x1];
2028         u8         rlky[0x1];
2029         u8         basic_cyclic_rcv_wqe[0x1];
2030         u8         log_rq_stride[0x3];
2031         u8         xrcd[0x18];
2032
2033         u8         page_offset[0x6];
2034         u8         reserved_2[0x2];
2035         u8         cqn[0x18];
2036
2037         u8         reserved_3[0x20];
2038
2039         u8         reserved_4[0x2];
2040         u8         log_page_size[0x6];
2041         u8         user_index[0x18];
2042
2043         u8         reserved_5[0x20];
2044
2045         u8         reserved_6[0x8];
2046         u8         pd[0x18];
2047
2048         u8         lwm[0x10];
2049         u8         wqe_cnt[0x10];
2050
2051         u8         reserved_7[0x40];
2052
2053         u8         db_record_addr_h[0x20];
2054
2055         u8         db_record_addr_l[0x1e];
2056         u8         reserved_8[0x2];
2057
2058         u8         reserved_9[0x80];
2059 };
2060
2061 struct mlx5_ifc_traffic_counter_bits {
2062         u8         packets[0x40];
2063
2064         u8         octets[0x40];
2065 };
2066
2067 struct mlx5_ifc_tisc_bits {
2068         u8         reserved_0[0xc];
2069         u8         prio[0x4];
2070         u8         reserved_1[0x10];
2071
2072         u8         reserved_2[0x100];
2073
2074         u8         reserved_3[0x8];
2075         u8         transport_domain[0x18];
2076
2077         u8         reserved_4[0x8];
2078         u8         underlay_qpn[0x18];
2079
2080         u8         reserved_5[0x3a0];
2081 };
2082
2083 enum {
2084         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2085         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2086 };
2087
2088 enum {
2089         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2090         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2091 };
2092
2093 enum {
2094         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2095         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2096         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2097 };
2098
2099 enum {
2100         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2101         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2102 };
2103
2104 struct mlx5_ifc_tirc_bits {
2105         u8         reserved_0[0x20];
2106
2107         u8         disp_type[0x4];
2108         u8         reserved_1[0x1c];
2109
2110         u8         reserved_2[0x40];
2111
2112         u8         reserved_3[0x4];
2113         u8         lro_timeout_period_usecs[0x10];
2114         u8         lro_enable_mask[0x4];
2115         u8         lro_max_msg_sz[0x8];
2116
2117         u8         reserved_4[0x40];
2118
2119         u8         reserved_5[0x8];
2120         u8         inline_rqn[0x18];
2121
2122         u8         rx_hash_symmetric[0x1];
2123         u8         reserved_6[0x1];
2124         u8         tunneled_offload_en[0x1];
2125         u8         reserved_7[0x5];
2126         u8         indirect_table[0x18];
2127
2128         u8         rx_hash_fn[0x4];
2129         u8         reserved_8[0x2];
2130         u8         self_lb_en[0x2];
2131         u8         transport_domain[0x18];
2132
2133         u8         rx_hash_toeplitz_key[10][0x20];
2134
2135         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2136
2137         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2138
2139         u8         reserved_9[0x4c0];
2140 };
2141
2142 enum {
2143         MLX5_SRQC_STATE_GOOD   = 0x0,
2144         MLX5_SRQC_STATE_ERROR  = 0x1,
2145 };
2146
2147 struct mlx5_ifc_srqc_bits {
2148         u8         state[0x4];
2149         u8         log_srq_size[0x4];
2150         u8         reserved_0[0x18];
2151
2152         u8         wq_signature[0x1];
2153         u8         cont_srq[0x1];
2154         u8         reserved_1[0x1];
2155         u8         rlky[0x1];
2156         u8         reserved_2[0x1];
2157         u8         log_rq_stride[0x3];
2158         u8         xrcd[0x18];
2159
2160         u8         page_offset[0x6];
2161         u8         reserved_3[0x2];
2162         u8         cqn[0x18];
2163
2164         u8         reserved_4[0x20];
2165
2166         u8         reserved_5[0x2];
2167         u8         log_page_size[0x6];
2168         u8         reserved_6[0x18];
2169
2170         u8         reserved_7[0x20];
2171
2172         u8         reserved_8[0x8];
2173         u8         pd[0x18];
2174
2175         u8         lwm[0x10];
2176         u8         wqe_cnt[0x10];
2177
2178         u8         reserved_9[0x40];
2179
2180         u8         db_record_addr_h[0x20];
2181
2182         u8         db_record_addr_l[0x1e];
2183         u8         reserved_10[0x2];
2184
2185         u8         reserved_11[0x80];
2186 };
2187
2188 enum {
2189         MLX5_SQC_STATE_RST  = 0x0,
2190         MLX5_SQC_STATE_RDY  = 0x1,
2191         MLX5_SQC_STATE_ERR  = 0x3,
2192 };
2193
2194 struct mlx5_ifc_sqc_bits {
2195         u8         rlkey[0x1];
2196         u8         cd_master[0x1];
2197         u8         fre[0x1];
2198         u8         flush_in_error_en[0x1];
2199         u8         allow_multi_pkt_send_wqe[0x1];
2200         u8         min_wqe_inline_mode[0x3];
2201         u8         state[0x4];
2202         u8         reg_umr[0x1];
2203         u8         allow_swp[0x1];
2204         u8         reserved_0[0x12];
2205
2206         u8         reserved_1[0x8];
2207         u8         user_index[0x18];
2208
2209         u8         reserved_2[0x8];
2210         u8         cqn[0x18];
2211
2212         u8         reserved_3[0x80];
2213
2214         u8         qos_para_vport_number[0x10];
2215         u8         packet_pacing_rate_limit_index[0x10];
2216
2217         u8         tis_lst_sz[0x10];
2218         u8         reserved_4[0x10];
2219
2220         u8         reserved_5[0x40];
2221
2222         u8         reserved_6[0x8];
2223         u8         tis_num_0[0x18];
2224
2225         struct mlx5_ifc_wq_bits wq;
2226 };
2227
2228 enum {
2229         MLX5_TSAR_TYPE_DWRR = 0,
2230         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2231         MLX5_TSAR_TYPE_ETS = 2
2232 };
2233
2234 struct mlx5_ifc_tsar_element_attributes_bits {
2235         u8         reserved_0[0x8];
2236         u8         tsar_type[0x8];
2237         u8         reserved_1[0x10];
2238 };
2239
2240 struct mlx5_ifc_vport_element_attributes_bits {
2241         u8         reserved_0[0x10];
2242         u8         vport_number[0x10];
2243 };
2244
2245 struct mlx5_ifc_vport_tc_element_attributes_bits {
2246         u8         traffic_class[0x10];
2247         u8         vport_number[0x10];
2248 };
2249
2250 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2251         u8         reserved_0[0x0C];
2252         u8         traffic_class[0x04];
2253         u8         qos_para_vport_number[0x10];
2254 };
2255
2256 enum {
2257         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2258         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2259         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2260         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2261 };
2262
2263 struct mlx5_ifc_scheduling_context_bits {
2264         u8         element_type[0x8];
2265         u8         reserved_at_8[0x18];
2266
2267         u8         element_attributes[0x20];
2268
2269         u8         parent_element_id[0x20];
2270
2271         u8         reserved_at_60[0x40];
2272
2273         u8         bw_share[0x20];
2274
2275         u8         max_average_bw[0x20];
2276
2277         u8         reserved_at_e0[0x120];
2278 };
2279
2280 struct mlx5_ifc_rqtc_bits {
2281         u8         reserved_0[0xa0];
2282
2283         u8         reserved_1[0x10];
2284         u8         rqt_max_size[0x10];
2285
2286         u8         reserved_2[0x10];
2287         u8         rqt_actual_size[0x10];
2288
2289         u8         reserved_3[0x6a0];
2290
2291         struct mlx5_ifc_rq_num_bits rq_num[0];
2292 };
2293
2294 enum {
2295         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2296         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2297 };
2298
2299 enum {
2300         MLX5_RQC_STATE_RST  = 0x0,
2301         MLX5_RQC_STATE_RDY  = 0x1,
2302         MLX5_RQC_STATE_ERR  = 0x3,
2303 };
2304
2305 enum {
2306         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2307         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2308 };
2309
2310 struct mlx5_ifc_rqc_bits {
2311         u8         rlkey[0x1];
2312         u8         delay_drop_en[0x1];
2313         u8         scatter_fcs[0x1];
2314         u8         vlan_strip_disable[0x1];
2315         u8         mem_rq_type[0x4];
2316         u8         state[0x4];
2317         u8         reserved_1[0x1];
2318         u8         flush_in_error_en[0x1];
2319         u8         reserved_2[0x12];
2320
2321         u8         reserved_3[0x8];
2322         u8         user_index[0x18];
2323
2324         u8         reserved_4[0x8];
2325         u8         cqn[0x18];
2326
2327         u8         counter_set_id[0x8];
2328         u8         reserved_5[0x18];
2329
2330         u8         reserved_6[0x8];
2331         u8         rmpn[0x18];
2332
2333         u8         reserved_7[0xe0];
2334
2335         struct mlx5_ifc_wq_bits wq;
2336 };
2337
2338 enum {
2339         MLX5_RMPC_STATE_RDY  = 0x1,
2340         MLX5_RMPC_STATE_ERR  = 0x3,
2341 };
2342
2343 struct mlx5_ifc_rmpc_bits {
2344         u8         reserved_0[0x8];
2345         u8         state[0x4];
2346         u8         reserved_1[0x14];
2347
2348         u8         basic_cyclic_rcv_wqe[0x1];
2349         u8         reserved_2[0x1f];
2350
2351         u8         reserved_3[0x140];
2352
2353         struct mlx5_ifc_wq_bits wq;
2354 };
2355
2356 enum {
2357         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2358         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2359         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2360 };
2361
2362 struct mlx5_ifc_nic_vport_context_bits {
2363         u8         reserved_0[0x5];
2364         u8         min_wqe_inline_mode[0x3];
2365         u8         reserved_1[0x15];
2366         u8         disable_mc_local_lb[0x1];
2367         u8         disable_uc_local_lb[0x1];
2368         u8         roce_en[0x1];
2369
2370         u8         arm_change_event[0x1];
2371         u8         reserved_2[0x1a];
2372         u8         event_on_mtu[0x1];
2373         u8         event_on_promisc_change[0x1];
2374         u8         event_on_vlan_change[0x1];
2375         u8         event_on_mc_address_change[0x1];
2376         u8         event_on_uc_address_change[0x1];
2377
2378         u8         reserved_3[0xe0];
2379
2380         u8         reserved_4[0x10];
2381         u8         mtu[0x10];
2382
2383         u8         system_image_guid[0x40];
2384
2385         u8         port_guid[0x40];
2386
2387         u8         node_guid[0x40];
2388
2389         u8         reserved_5[0x140];
2390
2391         u8         qkey_violation_counter[0x10];
2392         u8         reserved_6[0x10];
2393
2394         u8         reserved_7[0x420];
2395
2396         u8         promisc_uc[0x1];
2397         u8         promisc_mc[0x1];
2398         u8         promisc_all[0x1];
2399         u8         reserved_8[0x2];
2400         u8         allowed_list_type[0x3];
2401         u8         reserved_9[0xc];
2402         u8         allowed_list_size[0xc];
2403
2404         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2405
2406         u8         reserved_10[0x20];
2407
2408         u8         current_uc_mac_address[0][0x40];
2409 };
2410
2411 enum {
2412         MLX5_ACCESS_MODE_PA        = 0x0,
2413         MLX5_ACCESS_MODE_MTT       = 0x1,
2414         MLX5_ACCESS_MODE_KLM       = 0x2,
2415 };
2416
2417 struct mlx5_ifc_mkc_bits {
2418         u8         reserved_0[0x1];
2419         u8         free[0x1];
2420         u8         reserved_1[0xd];
2421         u8         small_fence_on_rdma_read_response[0x1];
2422         u8         umr_en[0x1];
2423         u8         a[0x1];
2424         u8         rw[0x1];
2425         u8         rr[0x1];
2426         u8         lw[0x1];
2427         u8         lr[0x1];
2428         u8         access_mode[0x2];
2429         u8         reserved_2[0x8];
2430
2431         u8         qpn[0x18];
2432         u8         mkey_7_0[0x8];
2433
2434         u8         reserved_3[0x20];
2435
2436         u8         length64[0x1];
2437         u8         bsf_en[0x1];
2438         u8         sync_umr[0x1];
2439         u8         reserved_4[0x2];
2440         u8         expected_sigerr_count[0x1];
2441         u8         reserved_5[0x1];
2442         u8         en_rinval[0x1];
2443         u8         pd[0x18];
2444
2445         u8         start_addr[0x40];
2446
2447         u8         len[0x40];
2448
2449         u8         bsf_octword_size[0x20];
2450
2451         u8         reserved_6[0x80];
2452
2453         u8         translations_octword_size[0x20];
2454
2455         u8         reserved_7[0x1b];
2456         u8         log_page_size[0x5];
2457
2458         u8         reserved_8[0x20];
2459 };
2460
2461 struct mlx5_ifc_pkey_bits {
2462         u8         reserved_0[0x10];
2463         u8         pkey[0x10];
2464 };
2465
2466 struct mlx5_ifc_array128_auto_bits {
2467         u8         array128_auto[16][0x8];
2468 };
2469
2470 enum {
2471         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2472         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2473         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2474 };
2475
2476 enum {
2477         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2478         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2479         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2480         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2481         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2482         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2483         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2484 };
2485
2486 enum {
2487         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2488         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2489         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2490 };
2491
2492 enum {
2493         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2494         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2495         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2496         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2497 };
2498
2499 enum {
2500         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2501         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2502         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2503         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2504 };
2505
2506 struct mlx5_ifc_hca_vport_context_bits {
2507         u8         field_select[0x20];
2508
2509         u8         reserved_0[0xe0];
2510
2511         u8         sm_virt_aware[0x1];
2512         u8         has_smi[0x1];
2513         u8         has_raw[0x1];
2514         u8         grh_required[0x1];
2515         u8         reserved_1[0x1];
2516         u8         min_wqe_inline_mode[0x3];
2517         u8         reserved_2[0x8];
2518         u8         port_physical_state[0x4];
2519         u8         vport_state_policy[0x4];
2520         u8         port_state[0x4];
2521         u8         vport_state[0x4];
2522
2523         u8         reserved_3[0x20];
2524
2525         u8         system_image_guid[0x40];
2526
2527         u8         port_guid[0x40];
2528
2529         u8         node_guid[0x40];
2530
2531         u8         cap_mask1[0x20];
2532
2533         u8         cap_mask1_field_select[0x20];
2534
2535         u8         cap_mask2[0x20];
2536
2537         u8         cap_mask2_field_select[0x20];
2538
2539         u8         reserved_4[0x80];
2540
2541         u8         lid[0x10];
2542         u8         reserved_5[0x4];
2543         u8         init_type_reply[0x4];
2544         u8         lmc[0x3];
2545         u8         subnet_timeout[0x5];
2546
2547         u8         sm_lid[0x10];
2548         u8         sm_sl[0x4];
2549         u8         reserved_6[0xc];
2550
2551         u8         qkey_violation_counter[0x10];
2552         u8         pkey_violation_counter[0x10];
2553
2554         u8         reserved_7[0xca0];
2555 };
2556
2557 union mlx5_ifc_hca_cap_union_bits {
2558         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2559         struct mlx5_ifc_odp_cap_bits odp_cap;
2560         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2561         struct mlx5_ifc_roce_cap_bits roce_cap;
2562         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2563         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2564         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2565         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2566         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2567         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2568         struct mlx5_ifc_qos_cap_bits qos_cap;
2569         u8         reserved_0[0x8000];
2570 };
2571
2572 enum {
2573         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2574         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2575 };
2576
2577 struct mlx5_ifc_flow_table_context_bits {
2578         u8         encap_en[0x1];
2579         u8         decap_en[0x1];
2580         u8         reserved_at_2[0x2];
2581         u8         table_miss_action[0x4];
2582         u8         level[0x8];
2583         u8         reserved_at_10[0x8];
2584         u8         log_size[0x8];
2585
2586         u8         reserved_at_20[0x8];
2587         u8         table_miss_id[0x18];
2588
2589         u8         reserved_at_40[0x8];
2590         u8         lag_master_next_table_id[0x18];
2591
2592         u8         reserved_at_60[0xe0];
2593 };
2594
2595 struct mlx5_ifc_esw_vport_context_bits {
2596         u8         reserved_0[0x3];
2597         u8         vport_svlan_strip[0x1];
2598         u8         vport_cvlan_strip[0x1];
2599         u8         vport_svlan_insert[0x1];
2600         u8         vport_cvlan_insert[0x2];
2601         u8         reserved_1[0x18];
2602
2603         u8         reserved_2[0x20];
2604
2605         u8         svlan_cfi[0x1];
2606         u8         svlan_pcp[0x3];
2607         u8         svlan_id[0xc];
2608         u8         cvlan_cfi[0x1];
2609         u8         cvlan_pcp[0x3];
2610         u8         cvlan_id[0xc];
2611
2612         u8         reserved_3[0x7a0];
2613 };
2614
2615 enum {
2616         MLX5_EQC_STATUS_OK                = 0x0,
2617         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2618 };
2619
2620 enum {
2621         MLX5_EQ_STATE_ARMED = 0x9,
2622         MLX5_EQ_STATE_FIRED = 0xa,
2623 };
2624
2625 struct mlx5_ifc_eqc_bits {
2626         u8         status[0x4];
2627         u8         reserved_0[0x9];
2628         u8         ec[0x1];
2629         u8         oi[0x1];
2630         u8         reserved_1[0x5];
2631         u8         st[0x4];
2632         u8         reserved_2[0x8];
2633
2634         u8         reserved_3[0x20];
2635
2636         u8         reserved_4[0x14];
2637         u8         page_offset[0x6];
2638         u8         reserved_5[0x6];
2639
2640         u8         reserved_6[0x3];
2641         u8         log_eq_size[0x5];
2642         u8         uar_page[0x18];
2643
2644         u8         reserved_7[0x20];
2645
2646         u8         reserved_8[0x18];
2647         u8         intr[0x8];
2648
2649         u8         reserved_9[0x3];
2650         u8         log_page_size[0x5];
2651         u8         reserved_10[0x18];
2652
2653         u8         reserved_11[0x60];
2654
2655         u8         reserved_12[0x8];
2656         u8         consumer_counter[0x18];
2657
2658         u8         reserved_13[0x8];
2659         u8         producer_counter[0x18];
2660
2661         u8         reserved_14[0x80];
2662 };
2663
2664 enum {
2665         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2666         MLX5_DCTC_STATE_DRAINING  = 0x1,
2667         MLX5_DCTC_STATE_DRAINED   = 0x2,
2668 };
2669
2670 enum {
2671         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2672         MLX5_DCTC_CS_RES_NA         = 0x1,
2673         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2674 };
2675
2676 enum {
2677         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2678         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2679         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2680         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2681         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2682 };
2683
2684 struct mlx5_ifc_dctc_bits {
2685         u8         reserved_0[0x4];
2686         u8         state[0x4];
2687         u8         reserved_1[0x18];
2688
2689         u8         reserved_2[0x8];
2690         u8         user_index[0x18];
2691
2692         u8         reserved_3[0x8];
2693         u8         cqn[0x18];
2694
2695         u8         counter_set_id[0x8];
2696         u8         atomic_mode[0x4];
2697         u8         rre[0x1];
2698         u8         rwe[0x1];
2699         u8         rae[0x1];
2700         u8         atomic_like_write_en[0x1];
2701         u8         latency_sensitive[0x1];
2702         u8         rlky[0x1];
2703         u8         reserved_4[0xe];
2704
2705         u8         reserved_5[0x8];
2706         u8         cs_res[0x8];
2707         u8         reserved_6[0x3];
2708         u8         min_rnr_nak[0x5];
2709         u8         reserved_7[0x8];
2710
2711         u8         reserved_8[0x8];
2712         u8         srqn[0x18];
2713
2714         u8         reserved_9[0x8];
2715         u8         pd[0x18];
2716
2717         u8         tclass[0x8];
2718         u8         reserved_10[0x4];
2719         u8         flow_label[0x14];
2720
2721         u8         dc_access_key[0x40];
2722
2723         u8         reserved_11[0x5];
2724         u8         mtu[0x3];
2725         u8         port[0x8];
2726         u8         pkey_index[0x10];
2727
2728         u8         reserved_12[0x8];
2729         u8         my_addr_index[0x8];
2730         u8         reserved_13[0x8];
2731         u8         hop_limit[0x8];
2732
2733         u8         dc_access_key_violation_count[0x20];
2734
2735         u8         reserved_14[0x14];
2736         u8         dei_cfi[0x1];
2737         u8         eth_prio[0x3];
2738         u8         ecn[0x2];
2739         u8         dscp[0x6];
2740
2741         u8         reserved_15[0x40];
2742 };
2743
2744 enum {
2745         MLX5_CQC_STATUS_OK             = 0x0,
2746         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2747         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2748 };
2749
2750 enum {
2751         CQE_SIZE_64                = 0x0,
2752         CQE_SIZE_128               = 0x1,
2753 };
2754
2755 enum {
2756         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2757         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2758 };
2759
2760 enum {
2761         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2762         MLX5_CQ_STATE_ARMED                               = 0x9,
2763         MLX5_CQ_STATE_FIRED                               = 0xa,
2764 };
2765
2766 struct mlx5_ifc_cqc_bits {
2767         u8         status[0x4];
2768         u8         reserved_0[0x4];
2769         u8         cqe_sz[0x3];
2770         u8         cc[0x1];
2771         u8         reserved_1[0x1];
2772         u8         scqe_break_moderation_en[0x1];
2773         u8         oi[0x1];
2774         u8         cq_period_mode[0x2];
2775         u8         cqe_compression_en[0x1];
2776         u8         mini_cqe_res_format[0x2];
2777         u8         st[0x4];
2778         u8         reserved_2[0x8];
2779
2780         u8         reserved_3[0x20];
2781
2782         u8         reserved_4[0x14];
2783         u8         page_offset[0x6];
2784         u8         reserved_5[0x6];
2785
2786         u8         reserved_6[0x3];
2787         u8         log_cq_size[0x5];
2788         u8         uar_page[0x18];
2789
2790         u8         reserved_7[0x4];
2791         u8         cq_period[0xc];
2792         u8         cq_max_count[0x10];
2793
2794         u8         reserved_8[0x18];
2795         u8         c_eqn[0x8];
2796
2797         u8         reserved_9[0x3];
2798         u8         log_page_size[0x5];
2799         u8         reserved_10[0x18];
2800
2801         u8         reserved_11[0x20];
2802
2803         u8         reserved_12[0x8];
2804         u8         last_notified_index[0x18];
2805
2806         u8         reserved_13[0x8];
2807         u8         last_solicit_index[0x18];
2808
2809         u8         reserved_14[0x8];
2810         u8         consumer_counter[0x18];
2811
2812         u8         reserved_15[0x8];
2813         u8         producer_counter[0x18];
2814
2815         u8         reserved_16[0x40];
2816
2817         u8         dbr_addr[0x40];
2818 };
2819
2820 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2821         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2822         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2823         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2824         u8         reserved_0[0x800];
2825 };
2826
2827 struct mlx5_ifc_query_adapter_param_block_bits {
2828         u8         reserved_0[0xc0];
2829
2830         u8         reserved_1[0x8];
2831         u8         ieee_vendor_id[0x18];
2832
2833         u8         reserved_2[0x10];
2834         u8         vsd_vendor_id[0x10];
2835
2836         u8         vsd[208][0x8];
2837
2838         u8         vsd_contd_psid[16][0x8];
2839 };
2840
2841 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2842         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2843         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2844         u8         reserved_0[0x20];
2845 };
2846
2847 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2848         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2849         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2850         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2851         u8         reserved_0[0x20];
2852 };
2853
2854 struct mlx5_ifc_bufferx_reg_bits {
2855         u8         reserved_0[0x6];
2856         u8         lossy[0x1];
2857         u8         epsb[0x1];
2858         u8         reserved_1[0xc];
2859         u8         size[0xc];
2860
2861         u8         xoff_threshold[0x10];
2862         u8         xon_threshold[0x10];
2863 };
2864
2865 struct mlx5_ifc_config_item_bits {
2866         u8         valid[0x2];
2867         u8         reserved_0[0x2];
2868         u8         header_type[0x2];
2869         u8         reserved_1[0x2];
2870         u8         default_location[0x1];
2871         u8         reserved_2[0x7];
2872         u8         version[0x4];
2873         u8         reserved_3[0x3];
2874         u8         length[0x9];
2875
2876         u8         type[0x20];
2877
2878         u8         reserved_4[0x10];
2879         u8         crc16[0x10];
2880 };
2881
2882 struct mlx5_ifc_nodnic_port_config_reg_bits {
2883         struct mlx5_ifc_nodnic_event_word_bits event;
2884
2885         u8         network_en[0x1];
2886         u8         dma_en[0x1];
2887         u8         promisc_en[0x1];
2888         u8         promisc_multicast_en[0x1];
2889         u8         reserved_0[0x17];
2890         u8         receive_filter_en[0x5];
2891
2892         u8         reserved_1[0x10];
2893         u8         mac_47_32[0x10];
2894
2895         u8         mac_31_0[0x20];
2896
2897         u8         receive_filters_mgid_mac[64][0x8];
2898
2899         u8         gid[16][0x8];
2900
2901         u8         reserved_2[0x10];
2902         u8         lid[0x10];
2903
2904         u8         reserved_3[0xc];
2905         u8         sm_sl[0x4];
2906         u8         sm_lid[0x10];
2907
2908         u8         completion_address_63_32[0x20];
2909
2910         u8         completion_address_31_12[0x14];
2911         u8         reserved_4[0x6];
2912         u8         log_cq_size[0x6];
2913
2914         u8         working_buffer_address_63_32[0x20];
2915
2916         u8         working_buffer_address_31_12[0x14];
2917         u8         reserved_5[0xc];
2918
2919         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2920
2921         u8         pkey_index[0x10];
2922         u8         pkey[0x10];
2923
2924         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2925
2926         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2927
2928         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2929
2930         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2931
2932         u8         reserved_6[0x400];
2933 };
2934
2935 union mlx5_ifc_event_auto_bits {
2936         struct mlx5_ifc_comp_event_bits comp_event;
2937         struct mlx5_ifc_dct_events_bits dct_events;
2938         struct mlx5_ifc_qp_events_bits qp_events;
2939         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2940         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2941         struct mlx5_ifc_cq_error_bits cq_error;
2942         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2943         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2944         struct mlx5_ifc_gpio_event_bits gpio_event;
2945         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2946         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2947         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2948         struct mlx5_ifc_pages_req_event_bits pages_req_event;
2949         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2950         u8         reserved_0[0xe0];
2951 };
2952
2953 struct mlx5_ifc_health_buffer_bits {
2954         u8         reserved_0[0x100];
2955
2956         u8         assert_existptr[0x20];
2957
2958         u8         assert_callra[0x20];
2959
2960         u8         reserved_1[0x40];
2961
2962         u8         fw_version[0x20];
2963
2964         u8         hw_id[0x20];
2965
2966         u8         reserved_2[0x20];
2967
2968         u8         irisc_index[0x8];
2969         u8         synd[0x8];
2970         u8         ext_synd[0x10];
2971 };
2972
2973 struct mlx5_ifc_register_loopback_control_bits {
2974         u8         no_lb[0x1];
2975         u8         reserved_0[0x7];
2976         u8         port[0x8];
2977         u8         reserved_1[0x10];
2978
2979         u8         reserved_2[0x60];
2980 };
2981
2982 struct mlx5_ifc_lrh_bits {
2983         u8      vl[4];
2984         u8      lver[4];
2985         u8      sl[4];
2986         u8      reserved2[2];
2987         u8      lnh[2];
2988         u8      dlid[16];
2989         u8      reserved5[5];
2990         u8      pkt_len[11];
2991         u8      slid[16];
2992 };
2993
2994 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
2995         u8         reserved_0[0x40];
2996
2997         u8         reserved_1[0x10];
2998         u8         rol_mode[0x8];
2999         u8         wol_mode[0x8];
3000 };
3001
3002 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3003         u8         reserved_0[0x40];
3004
3005         u8         rol_mode_valid[0x1];
3006         u8         wol_mode_valid[0x1];
3007         u8         reserved_1[0xe];
3008         u8         rol_mode[0x8];
3009         u8         wol_mode[0x8];
3010
3011         u8         reserved_2[0x7a0];
3012 };
3013
3014 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3015         u8         virtual_mac_en[0x1];
3016         u8         mac_aux_v[0x1];
3017         u8         reserved_0[0x1e];
3018
3019         u8         reserved_1[0x40];
3020
3021         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3022
3023         u8         reserved_2[0x760];
3024 };
3025
3026 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3027         u8         virtual_mac_en[0x1];
3028         u8         mac_aux_v[0x1];
3029         u8         reserved_0[0x1e];
3030
3031         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3032
3033         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3034
3035         u8         reserved_1[0x760];
3036 };
3037
3038 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3039         struct mlx5_ifc_fw_version_bits fw_version;
3040
3041         u8         reserved_0[0x10];
3042         u8         hash_signature[0x10];
3043
3044         u8         psid[16][0x8];
3045
3046         u8         reserved_1[0x6e0];
3047 };
3048
3049 struct mlx5_ifc_icmd_query_cap_in_bits {
3050         u8         reserved_0[0x10];
3051         u8         capability_group[0x10];
3052 };
3053
3054 struct mlx5_ifc_icmd_query_cap_general_bits {
3055         u8         nv_access[0x1];
3056         u8         fw_info_psid[0x1];
3057         u8         reserved_0[0x1e];
3058
3059         u8         reserved_1[0x16];
3060         u8         rol_s[0x1];
3061         u8         rol_g[0x1];
3062         u8         reserved_2[0x1];
3063         u8         wol_s[0x1];
3064         u8         wol_g[0x1];
3065         u8         wol_a[0x1];
3066         u8         wol_b[0x1];
3067         u8         wol_m[0x1];
3068         u8         wol_u[0x1];
3069         u8         wol_p[0x1];
3070 };
3071
3072 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3073         u8         status[0x8];
3074         u8         reserved_0[0x18];
3075
3076         u8         reserved_1[0x7e0];
3077 };
3078
3079 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3080         u8         status[0x8];
3081         u8         reserved_0[0x18];
3082
3083         u8         reserved_1[0x7e0];
3084 };
3085
3086 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3087         u8         address_hi[0x20];
3088
3089         u8         address_lo[0x20];
3090
3091         u8         reserved_0[0x7c0];
3092 };
3093
3094 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3095         u8         reserved_0[0x20];
3096
3097         u8         address_hi[0x20];
3098
3099         u8         address_lo[0x20];
3100
3101         u8         reserved_1[0x7a0];
3102 };
3103
3104 struct mlx5_ifc_icmd_access_reg_out_bits {
3105         u8         reserved_0[0x11];
3106         u8         status[0x7];
3107         u8         reserved_1[0x8];
3108
3109         u8         register_id[0x10];
3110         u8         reserved_2[0x10];
3111
3112         u8         reserved_3[0x40];
3113
3114         u8         reserved_4[0x5];
3115         u8         len[0xb];
3116         u8         reserved_5[0x10];
3117
3118         u8         register_data[0][0x20];
3119 };
3120
3121 enum {
3122         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3123         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3124 };
3125
3126 struct mlx5_ifc_icmd_access_reg_in_bits {
3127         u8         constant_1[0x5];
3128         u8         constant_2[0xb];
3129         u8         reserved_0[0x10];
3130
3131         u8         register_id[0x10];
3132         u8         reserved_1[0x1];
3133         u8         method[0x7];
3134         u8         constant_3[0x8];
3135
3136         u8         reserved_2[0x40];
3137
3138         u8         constant_4[0x5];
3139         u8         len[0xb];
3140         u8         reserved_3[0x10];
3141
3142         u8         register_data[0][0x20];
3143 };
3144
3145 struct mlx5_ifc_teardown_hca_out_bits {
3146         u8         status[0x8];
3147         u8         reserved_0[0x18];
3148
3149         u8         syndrome[0x20];
3150
3151         u8         reserved_1[0x40];
3152 };
3153
3154 enum {
3155         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3156         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3157 };
3158
3159 struct mlx5_ifc_teardown_hca_in_bits {
3160         u8         opcode[0x10];
3161         u8         reserved_0[0x10];
3162
3163         u8         reserved_1[0x10];
3164         u8         op_mod[0x10];
3165
3166         u8         reserved_2[0x10];
3167         u8         profile[0x10];
3168
3169         u8         reserved_3[0x20];
3170 };
3171
3172 struct mlx5_ifc_set_delay_drop_params_out_bits {
3173         u8         status[0x8];
3174         u8         reserved_at_8[0x18];
3175
3176         u8         syndrome[0x20];
3177
3178         u8         reserved_at_40[0x40];
3179 };
3180
3181 struct mlx5_ifc_set_delay_drop_params_in_bits {
3182         u8         opcode[0x10];
3183         u8         reserved_at_10[0x10];
3184
3185         u8         reserved_at_20[0x10];
3186         u8         op_mod[0x10];
3187
3188         u8         reserved_at_40[0x20];
3189
3190         u8         reserved_at_60[0x10];
3191         u8         delay_drop_timeout[0x10];
3192 };
3193
3194 struct mlx5_ifc_query_delay_drop_params_out_bits {
3195         u8         status[0x8];
3196         u8         reserved_at_8[0x18];
3197
3198         u8         syndrome[0x20];
3199
3200         u8         reserved_at_40[0x20];
3201
3202         u8         reserved_at_60[0x10];
3203         u8         delay_drop_timeout[0x10];
3204 };
3205
3206 struct mlx5_ifc_query_delay_drop_params_in_bits {
3207         u8         opcode[0x10];
3208         u8         reserved_at_10[0x10];
3209
3210         u8         reserved_at_20[0x10];
3211         u8         op_mod[0x10];
3212
3213         u8         reserved_at_40[0x40];
3214 };
3215
3216 struct mlx5_ifc_suspend_qp_out_bits {
3217         u8         status[0x8];
3218         u8         reserved_0[0x18];
3219
3220         u8         syndrome[0x20];
3221
3222         u8         reserved_1[0x40];
3223 };
3224
3225 struct mlx5_ifc_suspend_qp_in_bits {
3226         u8         opcode[0x10];
3227         u8         reserved_0[0x10];
3228
3229         u8         reserved_1[0x10];
3230         u8         op_mod[0x10];
3231
3232         u8         reserved_2[0x8];
3233         u8         qpn[0x18];
3234
3235         u8         reserved_3[0x20];
3236 };
3237
3238 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3239         u8         status[0x8];
3240         u8         reserved_0[0x18];
3241
3242         u8         syndrome[0x20];
3243
3244         u8         reserved_1[0x40];
3245 };
3246
3247 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3248         u8         opcode[0x10];
3249         u8         reserved_0[0x10];
3250
3251         u8         reserved_1[0x10];
3252         u8         op_mod[0x10];
3253
3254         u8         reserved_2[0x8];
3255         u8         qpn[0x18];
3256
3257         u8         reserved_3[0x20];
3258
3259         u8         opt_param_mask[0x20];
3260
3261         u8         reserved_4[0x20];
3262
3263         struct mlx5_ifc_qpc_bits qpc;
3264
3265         u8         reserved_5[0x80];
3266 };
3267
3268 struct mlx5_ifc_sqd2rts_qp_out_bits {
3269         u8         status[0x8];
3270         u8         reserved_0[0x18];
3271
3272         u8         syndrome[0x20];
3273
3274         u8         reserved_1[0x40];
3275 };
3276
3277 struct mlx5_ifc_sqd2rts_qp_in_bits {
3278         u8         opcode[0x10];
3279         u8         reserved_0[0x10];
3280
3281         u8         reserved_1[0x10];
3282         u8         op_mod[0x10];
3283
3284         u8         reserved_2[0x8];
3285         u8         qpn[0x18];
3286
3287         u8         reserved_3[0x20];
3288
3289         u8         opt_param_mask[0x20];
3290
3291         u8         reserved_4[0x20];
3292
3293         struct mlx5_ifc_qpc_bits qpc;
3294
3295         u8         reserved_5[0x80];
3296 };
3297
3298 struct mlx5_ifc_set_wol_rol_out_bits {
3299         u8         status[0x8];
3300         u8         reserved_0[0x18];
3301
3302         u8         syndrome[0x20];
3303
3304         u8         reserved_1[0x40];
3305 };
3306
3307 struct mlx5_ifc_set_wol_rol_in_bits {
3308         u8         opcode[0x10];
3309         u8         reserved_0[0x10];
3310
3311         u8         reserved_1[0x10];
3312         u8         op_mod[0x10];
3313
3314         u8         rol_mode_valid[0x1];
3315         u8         wol_mode_valid[0x1];
3316         u8         reserved_2[0xe];
3317         u8         rol_mode[0x8];
3318         u8         wol_mode[0x8];
3319
3320         u8         reserved_3[0x20];
3321 };
3322
3323 struct mlx5_ifc_set_roce_address_out_bits {
3324         u8         status[0x8];
3325         u8         reserved_0[0x18];
3326
3327         u8         syndrome[0x20];
3328
3329         u8         reserved_1[0x40];
3330 };
3331
3332 struct mlx5_ifc_set_roce_address_in_bits {
3333         u8         opcode[0x10];
3334         u8         reserved_0[0x10];
3335
3336         u8         reserved_1[0x10];
3337         u8         op_mod[0x10];
3338
3339         u8         roce_address_index[0x10];
3340         u8         reserved_2[0x10];
3341
3342         u8         reserved_3[0x20];
3343
3344         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3345 };
3346
3347 struct mlx5_ifc_set_rdb_out_bits {
3348         u8         status[0x8];
3349         u8         reserved_0[0x18];
3350
3351         u8         syndrome[0x20];
3352
3353         u8         reserved_1[0x40];
3354 };
3355
3356 struct mlx5_ifc_set_rdb_in_bits {
3357         u8         opcode[0x10];
3358         u8         reserved_0[0x10];
3359
3360         u8         reserved_1[0x10];
3361         u8         op_mod[0x10];
3362
3363         u8         reserved_2[0x8];
3364         u8         qpn[0x18];
3365
3366         u8         reserved_3[0x18];
3367         u8         rdb_list_size[0x8];
3368
3369         struct mlx5_ifc_rdbc_bits rdb_context[0];
3370 };
3371
3372 struct mlx5_ifc_set_mad_demux_out_bits {
3373         u8         status[0x8];
3374         u8         reserved_0[0x18];
3375
3376         u8         syndrome[0x20];
3377
3378         u8         reserved_1[0x40];
3379 };
3380
3381 enum {
3382         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3383         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3384 };
3385
3386 struct mlx5_ifc_set_mad_demux_in_bits {
3387         u8         opcode[0x10];
3388         u8         reserved_0[0x10];
3389
3390         u8         reserved_1[0x10];
3391         u8         op_mod[0x10];
3392
3393         u8         reserved_2[0x20];
3394
3395         u8         reserved_3[0x6];
3396         u8         demux_mode[0x2];
3397         u8         reserved_4[0x18];
3398 };
3399
3400 struct mlx5_ifc_set_l2_table_entry_out_bits {
3401         u8         status[0x8];
3402         u8         reserved_0[0x18];
3403
3404         u8         syndrome[0x20];
3405
3406         u8         reserved_1[0x40];
3407 };
3408
3409 struct mlx5_ifc_set_l2_table_entry_in_bits {
3410         u8         opcode[0x10];
3411         u8         reserved_0[0x10];
3412
3413         u8         reserved_1[0x10];
3414         u8         op_mod[0x10];
3415
3416         u8         reserved_2[0x60];
3417
3418         u8         reserved_3[0x8];
3419         u8         table_index[0x18];
3420
3421         u8         reserved_4[0x20];
3422
3423         u8         reserved_5[0x13];
3424         u8         vlan_valid[0x1];
3425         u8         vlan[0xc];
3426
3427         struct mlx5_ifc_mac_address_layout_bits mac_address;
3428
3429         u8         reserved_6[0xc0];
3430 };
3431
3432 struct mlx5_ifc_set_issi_out_bits {
3433         u8         status[0x8];
3434         u8         reserved_0[0x18];
3435
3436         u8         syndrome[0x20];
3437
3438         u8         reserved_1[0x40];
3439 };
3440
3441 struct mlx5_ifc_set_issi_in_bits {
3442         u8         opcode[0x10];
3443         u8         reserved_0[0x10];
3444
3445         u8         reserved_1[0x10];
3446         u8         op_mod[0x10];
3447
3448         u8         reserved_2[0x10];
3449         u8         current_issi[0x10];
3450
3451         u8         reserved_3[0x20];
3452 };
3453
3454 struct mlx5_ifc_set_hca_cap_out_bits {
3455         u8         status[0x8];
3456         u8         reserved_0[0x18];
3457
3458         u8         syndrome[0x20];
3459
3460         u8         reserved_1[0x40];
3461 };
3462
3463 struct mlx5_ifc_set_hca_cap_in_bits {
3464         u8         opcode[0x10];
3465         u8         reserved_0[0x10];
3466
3467         u8         reserved_1[0x10];
3468         u8         op_mod[0x10];
3469
3470         u8         reserved_2[0x40];
3471
3472         union mlx5_ifc_hca_cap_union_bits capability;
3473 };
3474
3475 enum {
3476         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3477         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3478         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3479         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3480 };
3481
3482 struct mlx5_ifc_set_flow_table_root_out_bits {
3483         u8         status[0x8];
3484         u8         reserved_0[0x18];
3485
3486         u8         syndrome[0x20];
3487
3488         u8         reserved_1[0x40];
3489 };
3490
3491 struct mlx5_ifc_set_flow_table_root_in_bits {
3492         u8         opcode[0x10];
3493         u8         reserved_0[0x10];
3494
3495         u8         reserved_1[0x10];
3496         u8         op_mod[0x10];
3497
3498         u8         other_vport[0x1];
3499         u8         reserved_2[0xf];
3500         u8         vport_number[0x10];
3501
3502         u8         reserved_3[0x20];
3503
3504         u8         table_type[0x8];
3505         u8         reserved_4[0x18];
3506
3507         u8         reserved_5[0x8];
3508         u8         table_id[0x18];
3509
3510         u8         reserved_6[0x8];
3511         u8         underlay_qpn[0x18];
3512
3513         u8         reserved_7[0x120];
3514 };
3515
3516 struct mlx5_ifc_set_fte_out_bits {
3517         u8         status[0x8];
3518         u8         reserved_0[0x18];
3519
3520         u8         syndrome[0x20];
3521
3522         u8         reserved_1[0x40];
3523 };
3524
3525 struct mlx5_ifc_set_fte_in_bits {
3526         u8         opcode[0x10];
3527         u8         reserved_0[0x10];
3528
3529         u8         reserved_1[0x10];
3530         u8         op_mod[0x10];
3531
3532         u8         other_vport[0x1];
3533         u8         reserved_2[0xf];
3534         u8         vport_number[0x10];
3535
3536         u8         reserved_3[0x20];
3537
3538         u8         table_type[0x8];
3539         u8         reserved_4[0x18];
3540
3541         u8         reserved_5[0x8];
3542         u8         table_id[0x18];
3543
3544         u8         reserved_6[0x18];
3545         u8         modify_enable_mask[0x8];
3546
3547         u8         reserved_7[0x20];
3548
3549         u8         flow_index[0x20];
3550
3551         u8         reserved_8[0xe0];
3552
3553         struct mlx5_ifc_flow_context_bits flow_context;
3554 };
3555
3556 struct mlx5_ifc_set_driver_version_out_bits {
3557         u8         status[0x8];
3558         u8         reserved_0[0x18];
3559
3560         u8         syndrome[0x20];
3561
3562         u8         reserved_1[0x40];
3563 };
3564
3565 struct mlx5_ifc_set_driver_version_in_bits {
3566         u8         opcode[0x10];
3567         u8         reserved_0[0x10];
3568
3569         u8         reserved_1[0x10];
3570         u8         op_mod[0x10];
3571
3572         u8         reserved_2[0x40];
3573
3574         u8         driver_version[64][0x8];
3575 };
3576
3577 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3578         u8         status[0x8];
3579         u8         reserved_0[0x18];
3580
3581         u8         syndrome[0x20];
3582
3583         u8         reserved_1[0x40];
3584 };
3585
3586 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3587         u8         opcode[0x10];
3588         u8         reserved_0[0x10];
3589
3590         u8         reserved_1[0x10];
3591         u8         op_mod[0x10];
3592
3593         u8         enable[0x1];
3594         u8         reserved_2[0x1f];
3595
3596         u8         reserved_3[0x160];
3597
3598         struct mlx5_ifc_cmd_pas_bits pas;
3599 };
3600
3601 struct mlx5_ifc_set_burst_size_out_bits {
3602         u8         status[0x8];
3603         u8         reserved_0[0x18];
3604
3605         u8         syndrome[0x20];
3606
3607         u8         reserved_1[0x40];
3608 };
3609
3610 struct mlx5_ifc_set_burst_size_in_bits {
3611         u8         opcode[0x10];
3612         u8         reserved_0[0x10];
3613
3614         u8         reserved_1[0x10];
3615         u8         op_mod[0x10];
3616
3617         u8         reserved_2[0x20];
3618
3619         u8         reserved_3[0x9];
3620         u8         device_burst_size[0x17];
3621 };
3622
3623 struct mlx5_ifc_rts2rts_qp_out_bits {
3624         u8         status[0x8];
3625         u8         reserved_0[0x18];
3626
3627         u8         syndrome[0x20];
3628
3629         u8         reserved_1[0x40];
3630 };
3631
3632 struct mlx5_ifc_rts2rts_qp_in_bits {
3633         u8         opcode[0x10];
3634         u8         reserved_0[0x10];
3635
3636         u8         reserved_1[0x10];
3637         u8         op_mod[0x10];
3638
3639         u8         reserved_2[0x8];
3640         u8         qpn[0x18];
3641
3642         u8         reserved_3[0x20];
3643
3644         u8         opt_param_mask[0x20];
3645
3646         u8         reserved_4[0x20];
3647
3648         struct mlx5_ifc_qpc_bits qpc;
3649
3650         u8         reserved_5[0x80];
3651 };
3652
3653 struct mlx5_ifc_rtr2rts_qp_out_bits {
3654         u8         status[0x8];
3655         u8         reserved_0[0x18];
3656
3657         u8         syndrome[0x20];
3658
3659         u8         reserved_1[0x40];
3660 };
3661
3662 struct mlx5_ifc_rtr2rts_qp_in_bits {
3663         u8         opcode[0x10];
3664         u8         reserved_0[0x10];
3665
3666         u8         reserved_1[0x10];
3667         u8         op_mod[0x10];
3668
3669         u8         reserved_2[0x8];
3670         u8         qpn[0x18];
3671
3672         u8         reserved_3[0x20];
3673
3674         u8         opt_param_mask[0x20];
3675
3676         u8         reserved_4[0x20];
3677
3678         struct mlx5_ifc_qpc_bits qpc;
3679
3680         u8         reserved_5[0x80];
3681 };
3682
3683 struct mlx5_ifc_rst2init_qp_out_bits {
3684         u8         status[0x8];
3685         u8         reserved_0[0x18];
3686
3687         u8         syndrome[0x20];
3688
3689         u8         reserved_1[0x40];
3690 };
3691
3692 struct mlx5_ifc_rst2init_qp_in_bits {
3693         u8         opcode[0x10];
3694         u8         reserved_0[0x10];
3695
3696         u8         reserved_1[0x10];
3697         u8         op_mod[0x10];
3698
3699         u8         reserved_2[0x8];
3700         u8         qpn[0x18];
3701
3702         u8         reserved_3[0x20];
3703
3704         u8         opt_param_mask[0x20];
3705
3706         u8         reserved_4[0x20];
3707
3708         struct mlx5_ifc_qpc_bits qpc;
3709
3710         u8         reserved_5[0x80];
3711 };
3712
3713 struct mlx5_ifc_resume_qp_out_bits {
3714         u8         status[0x8];
3715         u8         reserved_0[0x18];
3716
3717         u8         syndrome[0x20];
3718
3719         u8         reserved_1[0x40];
3720 };
3721
3722 struct mlx5_ifc_resume_qp_in_bits {
3723         u8         opcode[0x10];
3724         u8         reserved_0[0x10];
3725
3726         u8         reserved_1[0x10];
3727         u8         op_mod[0x10];
3728
3729         u8         reserved_2[0x8];
3730         u8         qpn[0x18];
3731
3732         u8         reserved_3[0x20];
3733 };
3734
3735 struct mlx5_ifc_query_xrc_srq_out_bits {
3736         u8         status[0x8];
3737         u8         reserved_0[0x18];
3738
3739         u8         syndrome[0x20];
3740
3741         u8         reserved_1[0x40];
3742
3743         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3744
3745         u8         reserved_2[0x600];
3746
3747         u8         pas[0][0x40];
3748 };
3749
3750 struct mlx5_ifc_query_xrc_srq_in_bits {
3751         u8         opcode[0x10];
3752         u8         reserved_0[0x10];
3753
3754         u8         reserved_1[0x10];
3755         u8         op_mod[0x10];
3756
3757         u8         reserved_2[0x8];
3758         u8         xrc_srqn[0x18];
3759
3760         u8         reserved_3[0x20];
3761 };
3762
3763 struct mlx5_ifc_query_wol_rol_out_bits {
3764         u8         status[0x8];
3765         u8         reserved_0[0x18];
3766
3767         u8         syndrome[0x20];
3768
3769         u8         reserved_1[0x10];
3770         u8         rol_mode[0x8];
3771         u8         wol_mode[0x8];
3772
3773         u8         reserved_2[0x20];
3774 };
3775
3776 struct mlx5_ifc_query_wol_rol_in_bits {
3777         u8         opcode[0x10];
3778         u8         reserved_0[0x10];
3779
3780         u8         reserved_1[0x10];
3781         u8         op_mod[0x10];
3782
3783         u8         reserved_2[0x40];
3784 };
3785
3786 enum {
3787         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3788         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3789 };
3790
3791 struct mlx5_ifc_query_vport_state_out_bits {
3792         u8         status[0x8];
3793         u8         reserved_0[0x18];
3794
3795         u8         syndrome[0x20];
3796
3797         u8         reserved_1[0x20];
3798
3799         u8         reserved_2[0x18];
3800         u8         admin_state[0x4];
3801         u8         state[0x4];
3802 };
3803
3804 enum {
3805         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3806         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3807         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3808 };
3809
3810 struct mlx5_ifc_query_vport_state_in_bits {
3811         u8         opcode[0x10];
3812         u8         reserved_0[0x10];
3813
3814         u8         reserved_1[0x10];
3815         u8         op_mod[0x10];
3816
3817         u8         other_vport[0x1];
3818         u8         reserved_2[0xf];
3819         u8         vport_number[0x10];
3820
3821         u8         reserved_3[0x20];
3822 };
3823
3824 struct mlx5_ifc_query_vport_counter_out_bits {
3825         u8         status[0x8];
3826         u8         reserved_0[0x18];
3827
3828         u8         syndrome[0x20];
3829
3830         u8         reserved_1[0x40];
3831
3832         struct mlx5_ifc_traffic_counter_bits received_errors;
3833
3834         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3835
3836         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3837
3838         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3839
3840         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3841
3842         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3843
3844         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3845
3846         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3847
3848         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3849
3850         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3851
3852         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3853
3854         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3855
3856         u8         reserved_2[0xa00];
3857 };
3858
3859 enum {
3860         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3861 };
3862
3863 struct mlx5_ifc_query_vport_counter_in_bits {
3864         u8         opcode[0x10];
3865         u8         reserved_0[0x10];
3866
3867         u8         reserved_1[0x10];
3868         u8         op_mod[0x10];
3869
3870         u8         other_vport[0x1];
3871         u8         reserved_2[0xb];
3872         u8         port_num[0x4];
3873         u8         vport_number[0x10];
3874
3875         u8         reserved_3[0x60];
3876
3877         u8         clear[0x1];
3878         u8         reserved_4[0x1f];
3879
3880         u8         reserved_5[0x20];
3881 };
3882
3883 struct mlx5_ifc_query_tis_out_bits {
3884         u8         status[0x8];
3885         u8         reserved_0[0x18];
3886
3887         u8         syndrome[0x20];
3888
3889         u8         reserved_1[0x40];
3890
3891         struct mlx5_ifc_tisc_bits tis_context;
3892 };
3893
3894 struct mlx5_ifc_query_tis_in_bits {
3895         u8         opcode[0x10];
3896         u8         reserved_0[0x10];
3897
3898         u8         reserved_1[0x10];
3899         u8         op_mod[0x10];
3900
3901         u8         reserved_2[0x8];
3902         u8         tisn[0x18];
3903
3904         u8         reserved_3[0x20];
3905 };
3906
3907 struct mlx5_ifc_query_tir_out_bits {
3908         u8         status[0x8];
3909         u8         reserved_0[0x18];
3910
3911         u8         syndrome[0x20];
3912
3913         u8         reserved_1[0xc0];
3914
3915         struct mlx5_ifc_tirc_bits tir_context;
3916 };
3917
3918 struct mlx5_ifc_query_tir_in_bits {
3919         u8         opcode[0x10];
3920         u8         reserved_0[0x10];
3921
3922         u8         reserved_1[0x10];
3923         u8         op_mod[0x10];
3924
3925         u8         reserved_2[0x8];
3926         u8         tirn[0x18];
3927
3928         u8         reserved_3[0x20];
3929 };
3930
3931 struct mlx5_ifc_query_srq_out_bits {
3932         u8         status[0x8];
3933         u8         reserved_0[0x18];
3934
3935         u8         syndrome[0x20];
3936
3937         u8         reserved_1[0x40];
3938
3939         struct mlx5_ifc_srqc_bits srq_context_entry;
3940
3941         u8         reserved_2[0x600];
3942
3943         u8         pas[0][0x40];
3944 };
3945
3946 struct mlx5_ifc_query_srq_in_bits {
3947         u8         opcode[0x10];
3948         u8         reserved_0[0x10];
3949
3950         u8         reserved_1[0x10];
3951         u8         op_mod[0x10];
3952
3953         u8         reserved_2[0x8];
3954         u8         srqn[0x18];
3955
3956         u8         reserved_3[0x20];
3957 };
3958
3959 struct mlx5_ifc_query_sq_out_bits {
3960         u8         status[0x8];
3961         u8         reserved_0[0x18];
3962
3963         u8         syndrome[0x20];
3964
3965         u8         reserved_1[0xc0];
3966
3967         struct mlx5_ifc_sqc_bits sq_context;
3968 };
3969
3970 struct mlx5_ifc_query_sq_in_bits {
3971         u8         opcode[0x10];
3972         u8         reserved_0[0x10];
3973
3974         u8         reserved_1[0x10];
3975         u8         op_mod[0x10];
3976
3977         u8         reserved_2[0x8];
3978         u8         sqn[0x18];
3979
3980         u8         reserved_3[0x20];
3981 };
3982
3983 struct mlx5_ifc_query_special_contexts_out_bits {
3984         u8         status[0x8];
3985         u8         reserved_0[0x18];
3986
3987         u8         syndrome[0x20];
3988
3989         u8         reserved_1[0x20];
3990
3991         u8         resd_lkey[0x20];
3992 };
3993
3994 struct mlx5_ifc_query_special_contexts_in_bits {
3995         u8         opcode[0x10];
3996         u8         reserved_0[0x10];
3997
3998         u8         reserved_1[0x10];
3999         u8         op_mod[0x10];
4000
4001         u8         reserved_2[0x40];
4002 };
4003
4004 struct mlx5_ifc_query_scheduling_element_out_bits {
4005         u8         status[0x8];
4006         u8         reserved_at_8[0x18];
4007
4008         u8         syndrome[0x20];
4009
4010         u8         reserved_at_40[0xc0];
4011
4012         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4013
4014         u8         reserved_at_300[0x100];
4015 };
4016
4017 enum {
4018         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4019 };
4020
4021 struct mlx5_ifc_query_scheduling_element_in_bits {
4022         u8         opcode[0x10];
4023         u8         reserved_at_10[0x10];
4024
4025         u8         reserved_at_20[0x10];
4026         u8         op_mod[0x10];
4027
4028         u8         scheduling_hierarchy[0x8];
4029         u8         reserved_at_48[0x18];
4030
4031         u8         scheduling_element_id[0x20];
4032
4033         u8         reserved_at_80[0x180];
4034 };
4035
4036 struct mlx5_ifc_query_rqt_out_bits {
4037         u8         status[0x8];
4038         u8         reserved_0[0x18];
4039
4040         u8         syndrome[0x20];
4041
4042         u8         reserved_1[0xc0];
4043
4044         struct mlx5_ifc_rqtc_bits rqt_context;
4045 };
4046
4047 struct mlx5_ifc_query_rqt_in_bits {
4048         u8         opcode[0x10];
4049         u8         reserved_0[0x10];
4050
4051         u8         reserved_1[0x10];
4052         u8         op_mod[0x10];
4053
4054         u8         reserved_2[0x8];
4055         u8         rqtn[0x18];
4056
4057         u8         reserved_3[0x20];
4058 };
4059
4060 struct mlx5_ifc_query_rq_out_bits {
4061         u8         status[0x8];
4062         u8         reserved_0[0x18];
4063
4064         u8         syndrome[0x20];
4065
4066         u8         reserved_1[0xc0];
4067
4068         struct mlx5_ifc_rqc_bits rq_context;
4069 };
4070
4071 struct mlx5_ifc_query_rq_in_bits {
4072         u8         opcode[0x10];
4073         u8         reserved_0[0x10];
4074
4075         u8         reserved_1[0x10];
4076         u8         op_mod[0x10];
4077
4078         u8         reserved_2[0x8];
4079         u8         rqn[0x18];
4080
4081         u8         reserved_3[0x20];
4082 };
4083
4084 struct mlx5_ifc_query_roce_address_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_0[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_1[0x40];
4091
4092         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4093 };
4094
4095 struct mlx5_ifc_query_roce_address_in_bits {
4096         u8         opcode[0x10];
4097         u8         reserved_0[0x10];
4098
4099         u8         reserved_1[0x10];
4100         u8         op_mod[0x10];
4101
4102         u8         roce_address_index[0x10];
4103         u8         reserved_2[0x10];
4104
4105         u8         reserved_3[0x20];
4106 };
4107
4108 struct mlx5_ifc_query_rmp_out_bits {
4109         u8         status[0x8];
4110         u8         reserved_0[0x18];
4111
4112         u8         syndrome[0x20];
4113
4114         u8         reserved_1[0xc0];
4115
4116         struct mlx5_ifc_rmpc_bits rmp_context;
4117 };
4118
4119 struct mlx5_ifc_query_rmp_in_bits {
4120         u8         opcode[0x10];
4121         u8         reserved_0[0x10];
4122
4123         u8         reserved_1[0x10];
4124         u8         op_mod[0x10];
4125
4126         u8         reserved_2[0x8];
4127         u8         rmpn[0x18];
4128
4129         u8         reserved_3[0x20];
4130 };
4131
4132 struct mlx5_ifc_query_rdb_out_bits {
4133         u8         status[0x8];
4134         u8         reserved_0[0x18];
4135
4136         u8         syndrome[0x20];
4137
4138         u8         reserved_1[0x20];
4139
4140         u8         reserved_2[0x18];
4141         u8         rdb_list_size[0x8];
4142
4143         struct mlx5_ifc_rdbc_bits rdb_context[0];
4144 };
4145
4146 struct mlx5_ifc_query_rdb_in_bits {
4147         u8         opcode[0x10];
4148         u8         reserved_0[0x10];
4149
4150         u8         reserved_1[0x10];
4151         u8         op_mod[0x10];
4152
4153         u8         reserved_2[0x8];
4154         u8         qpn[0x18];
4155
4156         u8         reserved_3[0x20];
4157 };
4158
4159 struct mlx5_ifc_query_qp_out_bits {
4160         u8         status[0x8];
4161         u8         reserved_0[0x18];
4162
4163         u8         syndrome[0x20];
4164
4165         u8         reserved_1[0x40];
4166
4167         u8         opt_param_mask[0x20];
4168
4169         u8         reserved_2[0x20];
4170
4171         struct mlx5_ifc_qpc_bits qpc;
4172
4173         u8         reserved_3[0x80];
4174
4175         u8         pas[0][0x40];
4176 };
4177
4178 struct mlx5_ifc_query_qp_in_bits {
4179         u8         opcode[0x10];
4180         u8         reserved_0[0x10];
4181
4182         u8         reserved_1[0x10];
4183         u8         op_mod[0x10];
4184
4185         u8         reserved_2[0x8];
4186         u8         qpn[0x18];
4187
4188         u8         reserved_3[0x20];
4189 };
4190
4191 struct mlx5_ifc_query_q_counter_out_bits {
4192         u8         status[0x8];
4193         u8         reserved_0[0x18];
4194
4195         u8         syndrome[0x20];
4196
4197         u8         reserved_1[0x40];
4198
4199         u8         rx_write_requests[0x20];
4200
4201         u8         reserved_2[0x20];
4202
4203         u8         rx_read_requests[0x20];
4204
4205         u8         reserved_3[0x20];
4206
4207         u8         rx_atomic_requests[0x20];
4208
4209         u8         reserved_4[0x20];
4210
4211         u8         rx_dct_connect[0x20];
4212
4213         u8         reserved_5[0x20];
4214
4215         u8         out_of_buffer[0x20];
4216
4217         u8         reserved_7[0x20];
4218
4219         u8         out_of_sequence[0x20];
4220
4221         u8         reserved_8[0x20];
4222
4223         u8         duplicate_request[0x20];
4224
4225         u8         reserved_9[0x20];
4226
4227         u8         rnr_nak_retry_err[0x20];
4228
4229         u8         reserved_10[0x20];
4230
4231         u8         packet_seq_err[0x20];
4232
4233         u8         reserved_11[0x20];
4234
4235         u8         implied_nak_seq_err[0x20];
4236
4237         u8         reserved_12[0x20];
4238
4239         u8         local_ack_timeout_err[0x20];
4240
4241         u8         reserved_13[0x20];
4242
4243         u8         resp_rnr_nak[0x20];
4244
4245         u8         reserved_14[0x20];
4246
4247         u8         req_rnr_retries_exceeded[0x20];
4248
4249         u8         reserved_15[0x460];
4250 };
4251
4252 struct mlx5_ifc_query_q_counter_in_bits {
4253         u8         opcode[0x10];
4254         u8         reserved_0[0x10];
4255
4256         u8         reserved_1[0x10];
4257         u8         op_mod[0x10];
4258
4259         u8         reserved_2[0x80];
4260
4261         u8         clear[0x1];
4262         u8         reserved_3[0x1f];
4263
4264         u8         reserved_4[0x18];
4265         u8         counter_set_id[0x8];
4266 };
4267
4268 struct mlx5_ifc_query_pages_out_bits {
4269         u8         status[0x8];
4270         u8         reserved_0[0x18];
4271
4272         u8         syndrome[0x20];
4273
4274         u8         reserved_1[0x10];
4275         u8         function_id[0x10];
4276
4277         u8         num_pages[0x20];
4278 };
4279
4280 enum {
4281         MLX5_BOOT_PAGES                           = 0x1,
4282         MLX5_INIT_PAGES                           = 0x2,
4283         MLX5_POST_INIT_PAGES                      = 0x3,
4284 };
4285
4286 struct mlx5_ifc_query_pages_in_bits {
4287         u8         opcode[0x10];
4288         u8         reserved_0[0x10];
4289
4290         u8         reserved_1[0x10];
4291         u8         op_mod[0x10];
4292
4293         u8         reserved_2[0x10];
4294         u8         function_id[0x10];
4295
4296         u8         reserved_3[0x20];
4297 };
4298
4299 struct mlx5_ifc_query_nic_vport_context_out_bits {
4300         u8         status[0x8];
4301         u8         reserved_0[0x18];
4302
4303         u8         syndrome[0x20];
4304
4305         u8         reserved_1[0x40];
4306
4307         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4308 };
4309
4310 struct mlx5_ifc_query_nic_vport_context_in_bits {
4311         u8         opcode[0x10];
4312         u8         reserved_0[0x10];
4313
4314         u8         reserved_1[0x10];
4315         u8         op_mod[0x10];
4316
4317         u8         other_vport[0x1];
4318         u8         reserved_2[0xf];
4319         u8         vport_number[0x10];
4320
4321         u8         reserved_3[0x5];
4322         u8         allowed_list_type[0x3];
4323         u8         reserved_4[0x18];
4324 };
4325
4326 struct mlx5_ifc_query_mkey_out_bits {
4327         u8         status[0x8];
4328         u8         reserved_0[0x18];
4329
4330         u8         syndrome[0x20];
4331
4332         u8         reserved_1[0x40];
4333
4334         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4335
4336         u8         reserved_2[0x600];
4337
4338         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4339
4340         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4341 };
4342
4343 struct mlx5_ifc_query_mkey_in_bits {
4344         u8         opcode[0x10];
4345         u8         reserved_0[0x10];
4346
4347         u8         reserved_1[0x10];
4348         u8         op_mod[0x10];
4349
4350         u8         reserved_2[0x8];
4351         u8         mkey_index[0x18];
4352
4353         u8         pg_access[0x1];
4354         u8         reserved_3[0x1f];
4355 };
4356
4357 struct mlx5_ifc_query_mad_demux_out_bits {
4358         u8         status[0x8];
4359         u8         reserved_0[0x18];
4360
4361         u8         syndrome[0x20];
4362
4363         u8         reserved_1[0x40];
4364
4365         u8         mad_dumux_parameters_block[0x20];
4366 };
4367
4368 struct mlx5_ifc_query_mad_demux_in_bits {
4369         u8         opcode[0x10];
4370         u8         reserved_0[0x10];
4371
4372         u8         reserved_1[0x10];
4373         u8         op_mod[0x10];
4374
4375         u8         reserved_2[0x40];
4376 };
4377
4378 struct mlx5_ifc_query_l2_table_entry_out_bits {
4379         u8         status[0x8];
4380         u8         reserved_0[0x18];
4381
4382         u8         syndrome[0x20];
4383
4384         u8         reserved_1[0xa0];
4385
4386         u8         reserved_2[0x13];
4387         u8         vlan_valid[0x1];
4388         u8         vlan[0xc];
4389
4390         struct mlx5_ifc_mac_address_layout_bits mac_address;
4391
4392         u8         reserved_3[0xc0];
4393 };
4394
4395 struct mlx5_ifc_query_l2_table_entry_in_bits {
4396         u8         opcode[0x10];
4397         u8         reserved_0[0x10];
4398
4399         u8         reserved_1[0x10];
4400         u8         op_mod[0x10];
4401
4402         u8         reserved_2[0x60];
4403
4404         u8         reserved_3[0x8];
4405         u8         table_index[0x18];
4406
4407         u8         reserved_4[0x140];
4408 };
4409
4410 struct mlx5_ifc_query_issi_out_bits {
4411         u8         status[0x8];
4412         u8         reserved_0[0x18];
4413
4414         u8         syndrome[0x20];
4415
4416         u8         reserved_1[0x10];
4417         u8         current_issi[0x10];
4418
4419         u8         reserved_2[0xa0];
4420
4421         u8         supported_issi_reserved[76][0x8];
4422         u8         supported_issi_dw0[0x20];
4423 };
4424
4425 struct mlx5_ifc_query_issi_in_bits {
4426         u8         opcode[0x10];
4427         u8         reserved_0[0x10];
4428
4429         u8         reserved_1[0x10];
4430         u8         op_mod[0x10];
4431
4432         u8         reserved_2[0x40];
4433 };
4434
4435 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4436         u8         status[0x8];
4437         u8         reserved_0[0x18];
4438
4439         u8         syndrome[0x20];
4440
4441         u8         reserved_1[0x40];
4442
4443         struct mlx5_ifc_pkey_bits pkey[0];
4444 };
4445
4446 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4447         u8         opcode[0x10];
4448         u8         reserved_0[0x10];
4449
4450         u8         reserved_1[0x10];
4451         u8         op_mod[0x10];
4452
4453         u8         other_vport[0x1];
4454         u8         reserved_2[0xb];
4455         u8         port_num[0x4];
4456         u8         vport_number[0x10];
4457
4458         u8         reserved_3[0x10];
4459         u8         pkey_index[0x10];
4460 };
4461
4462 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4463         u8         status[0x8];
4464         u8         reserved_0[0x18];
4465
4466         u8         syndrome[0x20];
4467
4468         u8         reserved_1[0x20];
4469
4470         u8         gids_num[0x10];
4471         u8         reserved_2[0x10];
4472
4473         struct mlx5_ifc_array128_auto_bits gid[0];
4474 };
4475
4476 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4477         u8         opcode[0x10];
4478         u8         reserved_0[0x10];
4479
4480         u8         reserved_1[0x10];
4481         u8         op_mod[0x10];
4482
4483         u8         other_vport[0x1];
4484         u8         reserved_2[0xb];
4485         u8         port_num[0x4];
4486         u8         vport_number[0x10];
4487
4488         u8         reserved_3[0x10];
4489         u8         gid_index[0x10];
4490 };
4491
4492 struct mlx5_ifc_query_hca_vport_context_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_0[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         reserved_1[0x40];
4499
4500         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4501 };
4502
4503 struct mlx5_ifc_query_hca_vport_context_in_bits {
4504         u8         opcode[0x10];
4505         u8         reserved_0[0x10];
4506
4507         u8         reserved_1[0x10];
4508         u8         op_mod[0x10];
4509
4510         u8         other_vport[0x1];
4511         u8         reserved_2[0xb];
4512         u8         port_num[0x4];
4513         u8         vport_number[0x10];
4514
4515         u8         reserved_3[0x20];
4516 };
4517
4518 struct mlx5_ifc_query_hca_cap_out_bits {
4519         u8         status[0x8];
4520         u8         reserved_0[0x18];
4521
4522         u8         syndrome[0x20];
4523
4524         u8         reserved_1[0x40];
4525
4526         union mlx5_ifc_hca_cap_union_bits capability;
4527 };
4528
4529 struct mlx5_ifc_query_hca_cap_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_0[0x10];
4532
4533         u8         reserved_1[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         reserved_2[0x40];
4537 };
4538
4539 struct mlx5_ifc_query_flow_table_out_bits {
4540         u8         status[0x8];
4541         u8         reserved_at_8[0x18];
4542
4543         u8         syndrome[0x20];
4544
4545         u8         reserved_at_40[0x80];
4546
4547         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4548 };
4549
4550 struct mlx5_ifc_query_flow_table_in_bits {
4551         u8         opcode[0x10];
4552         u8         reserved_0[0x10];
4553
4554         u8         reserved_1[0x10];
4555         u8         op_mod[0x10];
4556
4557         u8         other_vport[0x1];
4558         u8         reserved_2[0xf];
4559         u8         vport_number[0x10];
4560
4561         u8         reserved_3[0x20];
4562
4563         u8         table_type[0x8];
4564         u8         reserved_4[0x18];
4565
4566         u8         reserved_5[0x8];
4567         u8         table_id[0x18];
4568
4569         u8         reserved_6[0x140];
4570 };
4571
4572 struct mlx5_ifc_query_fte_out_bits {
4573         u8         status[0x8];
4574         u8         reserved_0[0x18];
4575
4576         u8         syndrome[0x20];
4577
4578         u8         reserved_1[0x1c0];
4579
4580         struct mlx5_ifc_flow_context_bits flow_context;
4581 };
4582
4583 struct mlx5_ifc_query_fte_in_bits {
4584         u8         opcode[0x10];
4585         u8         reserved_0[0x10];
4586
4587         u8         reserved_1[0x10];
4588         u8         op_mod[0x10];
4589
4590         u8         other_vport[0x1];
4591         u8         reserved_2[0xf];
4592         u8         vport_number[0x10];
4593
4594         u8         reserved_3[0x20];
4595
4596         u8         table_type[0x8];
4597         u8         reserved_4[0x18];
4598
4599         u8         reserved_5[0x8];
4600         u8         table_id[0x18];
4601
4602         u8         reserved_6[0x40];
4603
4604         u8         flow_index[0x20];
4605
4606         u8         reserved_7[0xe0];
4607 };
4608
4609 enum {
4610         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4611         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4612         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4613 };
4614
4615 struct mlx5_ifc_query_flow_group_out_bits {
4616         u8         status[0x8];
4617         u8         reserved_0[0x18];
4618
4619         u8         syndrome[0x20];
4620
4621         u8         reserved_1[0xa0];
4622
4623         u8         start_flow_index[0x20];
4624
4625         u8         reserved_2[0x20];
4626
4627         u8         end_flow_index[0x20];
4628
4629         u8         reserved_3[0xa0];
4630
4631         u8         reserved_4[0x18];
4632         u8         match_criteria_enable[0x8];
4633
4634         struct mlx5_ifc_fte_match_param_bits match_criteria;
4635
4636         u8         reserved_5[0xe00];
4637 };
4638
4639 struct mlx5_ifc_query_flow_group_in_bits {
4640         u8         opcode[0x10];
4641         u8         reserved_0[0x10];
4642
4643         u8         reserved_1[0x10];
4644         u8         op_mod[0x10];
4645
4646         u8         other_vport[0x1];
4647         u8         reserved_2[0xf];
4648         u8         vport_number[0x10];
4649
4650         u8         reserved_3[0x20];
4651
4652         u8         table_type[0x8];
4653         u8         reserved_4[0x18];
4654
4655         u8         reserved_5[0x8];
4656         u8         table_id[0x18];
4657
4658         u8         group_id[0x20];
4659
4660         u8         reserved_6[0x120];
4661 };
4662
4663 struct mlx5_ifc_query_flow_counter_out_bits {
4664         u8         status[0x8];
4665         u8         reserved_0[0x18];
4666
4667         u8         syndrome[0x20];
4668
4669         u8         reserved_1[0x40];
4670
4671         struct mlx5_ifc_traffic_counter_bits flow_statistics;
4672
4673         u8         reserved_2[0x700];
4674 };
4675
4676 struct mlx5_ifc_query_flow_counter_in_bits {
4677         u8         opcode[0x10];
4678         u8         reserved_0[0x10];
4679
4680         u8         reserved_1[0x10];
4681         u8         op_mod[0x10];
4682
4683         u8         reserved_2[0x80];
4684
4685         u8         clear[0x1];
4686         u8         reserved_3[0x1f];
4687
4688         u8         reserved_4[0x10];
4689         u8         flow_counter_id[0x10];
4690 };
4691
4692 struct mlx5_ifc_query_esw_vport_context_out_bits {
4693         u8         status[0x8];
4694         u8         reserved_0[0x18];
4695
4696         u8         syndrome[0x20];
4697
4698         u8         reserved_1[0x40];
4699
4700         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4701 };
4702
4703 struct mlx5_ifc_query_esw_vport_context_in_bits {
4704         u8         opcode[0x10];
4705         u8         reserved_0[0x10];
4706
4707         u8         reserved_1[0x10];
4708         u8         op_mod[0x10];
4709
4710         u8         other_vport[0x1];
4711         u8         reserved_2[0xf];
4712         u8         vport_number[0x10];
4713
4714         u8         reserved_3[0x20];
4715 };
4716
4717 struct mlx5_ifc_query_eq_out_bits {
4718         u8         status[0x8];
4719         u8         reserved_0[0x18];
4720
4721         u8         syndrome[0x20];
4722
4723         u8         reserved_1[0x40];
4724
4725         struct mlx5_ifc_eqc_bits eq_context_entry;
4726
4727         u8         reserved_2[0x40];
4728
4729         u8         event_bitmask[0x40];
4730
4731         u8         reserved_3[0x580];
4732
4733         u8         pas[0][0x40];
4734 };
4735
4736 struct mlx5_ifc_query_eq_in_bits {
4737         u8         opcode[0x10];
4738         u8         reserved_0[0x10];
4739
4740         u8         reserved_1[0x10];
4741         u8         op_mod[0x10];
4742
4743         u8         reserved_2[0x18];
4744         u8         eq_number[0x8];
4745
4746         u8         reserved_3[0x20];
4747 };
4748
4749 struct mlx5_ifc_query_dct_out_bits {
4750         u8         status[0x8];
4751         u8         reserved_0[0x18];
4752
4753         u8         syndrome[0x20];
4754
4755         u8         reserved_1[0x40];
4756
4757         struct mlx5_ifc_dctc_bits dct_context_entry;
4758
4759         u8         reserved_2[0x180];
4760 };
4761
4762 struct mlx5_ifc_query_dct_in_bits {
4763         u8         opcode[0x10];
4764         u8         reserved_0[0x10];
4765
4766         u8         reserved_1[0x10];
4767         u8         op_mod[0x10];
4768
4769         u8         reserved_2[0x8];
4770         u8         dctn[0x18];
4771
4772         u8         reserved_3[0x20];
4773 };
4774
4775 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4776         u8         status[0x8];
4777         u8         reserved_0[0x18];
4778
4779         u8         syndrome[0x20];
4780
4781         u8         enable[0x1];
4782         u8         reserved_1[0x1f];
4783
4784         u8         reserved_2[0x160];
4785
4786         struct mlx5_ifc_cmd_pas_bits pas;
4787 };
4788
4789 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4790         u8         opcode[0x10];
4791         u8         reserved_0[0x10];
4792
4793         u8         reserved_1[0x10];
4794         u8         op_mod[0x10];
4795
4796         u8         reserved_2[0x40];
4797 };
4798
4799 struct mlx5_ifc_query_cq_out_bits {
4800         u8         status[0x8];
4801         u8         reserved_0[0x18];
4802
4803         u8         syndrome[0x20];
4804
4805         u8         reserved_1[0x40];
4806
4807         struct mlx5_ifc_cqc_bits cq_context;
4808
4809         u8         reserved_2[0x600];
4810
4811         u8         pas[0][0x40];
4812 };
4813
4814 struct mlx5_ifc_query_cq_in_bits {
4815         u8         opcode[0x10];
4816         u8         reserved_0[0x10];
4817
4818         u8         reserved_1[0x10];
4819         u8         op_mod[0x10];
4820
4821         u8         reserved_2[0x8];
4822         u8         cqn[0x18];
4823
4824         u8         reserved_3[0x20];
4825 };
4826
4827 struct mlx5_ifc_query_cong_status_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_0[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_1[0x20];
4834
4835         u8         enable[0x1];
4836         u8         tag_enable[0x1];
4837         u8         reserved_2[0x1e];
4838 };
4839
4840 struct mlx5_ifc_query_cong_status_in_bits {
4841         u8         opcode[0x10];
4842         u8         reserved_0[0x10];
4843
4844         u8         reserved_1[0x10];
4845         u8         op_mod[0x10];
4846
4847         u8         reserved_2[0x18];
4848         u8         priority[0x4];
4849         u8         cong_protocol[0x4];
4850
4851         u8         reserved_3[0x20];
4852 };
4853
4854 struct mlx5_ifc_query_cong_statistics_out_bits {
4855         u8         status[0x8];
4856         u8         reserved_0[0x18];
4857
4858         u8         syndrome[0x20];
4859
4860         u8         reserved_1[0x40];
4861
4862         u8         cur_flows[0x20];
4863
4864         u8         sum_flows[0x20];
4865
4866         u8         cnp_ignored_high[0x20];
4867
4868         u8         cnp_ignored_low[0x20];
4869
4870         u8         cnp_handled_high[0x20];
4871
4872         u8         cnp_handled_low[0x20];
4873
4874         u8         reserved_2[0x100];
4875
4876         u8         time_stamp_high[0x20];
4877
4878         u8         time_stamp_low[0x20];
4879
4880         u8         accumulators_period[0x20];
4881
4882         u8         ecn_marked_roce_packets_high[0x20];
4883
4884         u8         ecn_marked_roce_packets_low[0x20];
4885
4886         u8         cnps_sent_high[0x20];
4887
4888         u8         cnps_sent_low[0x20];
4889
4890         u8         reserved_3[0x560];
4891 };
4892
4893 struct mlx5_ifc_query_cong_statistics_in_bits {
4894         u8         opcode[0x10];
4895         u8         reserved_0[0x10];
4896
4897         u8         reserved_1[0x10];
4898         u8         op_mod[0x10];
4899
4900         u8         clear[0x1];
4901         u8         reserved_2[0x1f];
4902
4903         u8         reserved_3[0x20];
4904 };
4905
4906 struct mlx5_ifc_query_cong_params_out_bits {
4907         u8         status[0x8];
4908         u8         reserved_0[0x18];
4909
4910         u8         syndrome[0x20];
4911
4912         u8         reserved_1[0x40];
4913
4914         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4915 };
4916
4917 struct mlx5_ifc_query_cong_params_in_bits {
4918         u8         opcode[0x10];
4919         u8         reserved_0[0x10];
4920
4921         u8         reserved_1[0x10];
4922         u8         op_mod[0x10];
4923
4924         u8         reserved_2[0x1c];
4925         u8         cong_protocol[0x4];
4926
4927         u8         reserved_3[0x20];
4928 };
4929
4930 struct mlx5_ifc_query_burst_size_out_bits {
4931         u8         status[0x8];
4932         u8         reserved_0[0x18];
4933
4934         u8         syndrome[0x20];
4935
4936         u8         reserved_1[0x20];
4937
4938         u8         reserved_2[0x9];
4939         u8         device_burst_size[0x17];
4940 };
4941
4942 struct mlx5_ifc_query_burst_size_in_bits {
4943         u8         opcode[0x10];
4944         u8         reserved_0[0x10];
4945
4946         u8         reserved_1[0x10];
4947         u8         op_mod[0x10];
4948
4949         u8         reserved_2[0x40];
4950 };
4951
4952 struct mlx5_ifc_query_adapter_out_bits {
4953         u8         status[0x8];
4954         u8         reserved_0[0x18];
4955
4956         u8         syndrome[0x20];
4957
4958         u8         reserved_1[0x40];
4959
4960         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4961 };
4962
4963 struct mlx5_ifc_query_adapter_in_bits {
4964         u8         opcode[0x10];
4965         u8         reserved_0[0x10];
4966
4967         u8         reserved_1[0x10];
4968         u8         op_mod[0x10];
4969
4970         u8         reserved_2[0x40];
4971 };
4972
4973 struct mlx5_ifc_qp_2rst_out_bits {
4974         u8         status[0x8];
4975         u8         reserved_0[0x18];
4976
4977         u8         syndrome[0x20];
4978
4979         u8         reserved_1[0x40];
4980 };
4981
4982 struct mlx5_ifc_qp_2rst_in_bits {
4983         u8         opcode[0x10];
4984         u8         reserved_0[0x10];
4985
4986         u8         reserved_1[0x10];
4987         u8         op_mod[0x10];
4988
4989         u8         reserved_2[0x8];
4990         u8         qpn[0x18];
4991
4992         u8         reserved_3[0x20];
4993 };
4994
4995 struct mlx5_ifc_qp_2err_out_bits {
4996         u8         status[0x8];
4997         u8         reserved_0[0x18];
4998
4999         u8         syndrome[0x20];
5000
5001         u8         reserved_1[0x40];
5002 };
5003
5004 struct mlx5_ifc_qp_2err_in_bits {
5005         u8         opcode[0x10];
5006         u8         reserved_0[0x10];
5007
5008         u8         reserved_1[0x10];
5009         u8         op_mod[0x10];
5010
5011         u8         reserved_2[0x8];
5012         u8         qpn[0x18];
5013
5014         u8         reserved_3[0x20];
5015 };
5016
5017 struct mlx5_ifc_para_vport_element_bits {
5018         u8         reserved_at_0[0xc];
5019         u8         traffic_class[0x4];
5020         u8         qos_para_vport_number[0x10];
5021 };
5022
5023 struct mlx5_ifc_page_fault_resume_out_bits {
5024         u8         status[0x8];
5025         u8         reserved_0[0x18];
5026
5027         u8         syndrome[0x20];
5028
5029         u8         reserved_1[0x40];
5030 };
5031
5032 struct mlx5_ifc_page_fault_resume_in_bits {
5033         u8         opcode[0x10];
5034         u8         reserved_0[0x10];
5035
5036         u8         reserved_1[0x10];
5037         u8         op_mod[0x10];
5038
5039         u8         error[0x1];
5040         u8         reserved_2[0x4];
5041         u8         rdma[0x1];
5042         u8         read_write[0x1];
5043         u8         req_res[0x1];
5044         u8         qpn[0x18];
5045
5046         u8         reserved_3[0x20];
5047 };
5048
5049 struct mlx5_ifc_nop_out_bits {
5050         u8         status[0x8];
5051         u8         reserved_0[0x18];
5052
5053         u8         syndrome[0x20];
5054
5055         u8         reserved_1[0x40];
5056 };
5057
5058 struct mlx5_ifc_nop_in_bits {
5059         u8         opcode[0x10];
5060         u8         reserved_0[0x10];
5061
5062         u8         reserved_1[0x10];
5063         u8         op_mod[0x10];
5064
5065         u8         reserved_2[0x40];
5066 };
5067
5068 struct mlx5_ifc_modify_vport_state_out_bits {
5069         u8         status[0x8];
5070         u8         reserved_0[0x18];
5071
5072         u8         syndrome[0x20];
5073
5074         u8         reserved_1[0x40];
5075 };
5076
5077 enum {
5078         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5079         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5080         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5081 };
5082
5083 enum {
5084         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5085         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5086         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5087 };
5088
5089 struct mlx5_ifc_modify_vport_state_in_bits {
5090         u8         opcode[0x10];
5091         u8         reserved_0[0x10];
5092
5093         u8         reserved_1[0x10];
5094         u8         op_mod[0x10];
5095
5096         u8         other_vport[0x1];
5097         u8         reserved_2[0xf];
5098         u8         vport_number[0x10];
5099
5100         u8         reserved_3[0x18];
5101         u8         admin_state[0x4];
5102         u8         reserved_4[0x4];
5103 };
5104
5105 struct mlx5_ifc_modify_tis_out_bits {
5106         u8         status[0x8];
5107         u8         reserved_0[0x18];
5108
5109         u8         syndrome[0x20];
5110
5111         u8         reserved_1[0x40];
5112 };
5113
5114 struct mlx5_ifc_modify_tis_in_bits {
5115         u8         opcode[0x10];
5116         u8         reserved_0[0x10];
5117
5118         u8         reserved_1[0x10];
5119         u8         op_mod[0x10];
5120
5121         u8         reserved_2[0x8];
5122         u8         tisn[0x18];
5123
5124         u8         reserved_3[0x20];
5125
5126         u8         modify_bitmask[0x40];
5127
5128         u8         reserved_4[0x40];
5129
5130         struct mlx5_ifc_tisc_bits ctx;
5131 };
5132
5133 struct mlx5_ifc_modify_tir_out_bits {
5134         u8         status[0x8];
5135         u8         reserved_0[0x18];
5136
5137         u8         syndrome[0x20];
5138
5139         u8         reserved_1[0x40];
5140 };
5141
5142 enum
5143 {
5144         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5145         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5146 };
5147
5148 struct mlx5_ifc_modify_tir_in_bits {
5149         u8         opcode[0x10];
5150         u8         reserved_0[0x10];
5151
5152         u8         reserved_1[0x10];
5153         u8         op_mod[0x10];
5154
5155         u8         reserved_2[0x8];
5156         u8         tirn[0x18];
5157
5158         u8         reserved_3[0x20];
5159
5160         u8         modify_bitmask[0x40];
5161
5162         u8         reserved_4[0x40];
5163
5164         struct mlx5_ifc_tirc_bits tir_context;
5165 };
5166
5167 struct mlx5_ifc_modify_sq_out_bits {
5168         u8         status[0x8];
5169         u8         reserved_0[0x18];
5170
5171         u8         syndrome[0x20];
5172
5173         u8         reserved_1[0x40];
5174 };
5175
5176 struct mlx5_ifc_modify_sq_in_bits {
5177         u8         opcode[0x10];
5178         u8         reserved_0[0x10];
5179
5180         u8         reserved_1[0x10];
5181         u8         op_mod[0x10];
5182
5183         u8         sq_state[0x4];
5184         u8         reserved_2[0x4];
5185         u8         sqn[0x18];
5186
5187         u8         reserved_3[0x20];
5188
5189         u8         modify_bitmask[0x40];
5190
5191         u8         reserved_4[0x40];
5192
5193         struct mlx5_ifc_sqc_bits ctx;
5194 };
5195
5196 struct mlx5_ifc_modify_scheduling_element_out_bits {
5197         u8         status[0x8];
5198         u8         reserved_at_8[0x18];
5199
5200         u8         syndrome[0x20];
5201
5202         u8         reserved_at_40[0x1c0];
5203 };
5204
5205 enum {
5206         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5207 };
5208
5209 enum {
5210         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5211         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5212 };
5213
5214 struct mlx5_ifc_modify_scheduling_element_in_bits {
5215         u8         opcode[0x10];
5216         u8         reserved_at_10[0x10];
5217
5218         u8         reserved_at_20[0x10];
5219         u8         op_mod[0x10];
5220
5221         u8         scheduling_hierarchy[0x8];
5222         u8         reserved_at_48[0x18];
5223
5224         u8         scheduling_element_id[0x20];
5225
5226         u8         reserved_at_80[0x20];
5227
5228         u8         modify_bitmask[0x20];
5229
5230         u8         reserved_at_c0[0x40];
5231
5232         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5233
5234         u8         reserved_at_300[0x100];
5235 };
5236
5237 struct mlx5_ifc_modify_rqt_out_bits {
5238         u8         status[0x8];
5239         u8         reserved_0[0x18];
5240
5241         u8         syndrome[0x20];
5242
5243         u8         reserved_1[0x40];
5244 };
5245
5246 struct mlx5_ifc_modify_rqt_in_bits {
5247         u8         opcode[0x10];
5248         u8         reserved_0[0x10];
5249
5250         u8         reserved_1[0x10];
5251         u8         op_mod[0x10];
5252
5253         u8         reserved_2[0x8];
5254         u8         rqtn[0x18];
5255
5256         u8         reserved_3[0x20];
5257
5258         u8         modify_bitmask[0x40];
5259
5260         u8         reserved_4[0x40];
5261
5262         struct mlx5_ifc_rqtc_bits ctx;
5263 };
5264
5265 struct mlx5_ifc_modify_rq_out_bits {
5266         u8         status[0x8];
5267         u8         reserved_0[0x18];
5268
5269         u8         syndrome[0x20];
5270
5271         u8         reserved_1[0x40];
5272 };
5273
5274 struct mlx5_ifc_rq_bitmask_bits {
5275         u8         reserved[0x20];
5276
5277         u8         reserved1[0x1e];
5278         u8         vlan_strip_disable[0x1];
5279         u8         reserved2[0x1];
5280 };
5281
5282 struct mlx5_ifc_modify_rq_in_bits {
5283         u8         opcode[0x10];
5284         u8         reserved_0[0x10];
5285
5286         u8         reserved_1[0x10];
5287         u8         op_mod[0x10];
5288
5289         u8         rq_state[0x4];
5290         u8         reserved_2[0x4];
5291         u8         rqn[0x18];
5292
5293         u8         reserved_3[0x20];
5294
5295         struct mlx5_ifc_rq_bitmask_bits bitmask;
5296
5297         u8         reserved_4[0x40];
5298
5299         struct mlx5_ifc_rqc_bits ctx;
5300 };
5301
5302 struct mlx5_ifc_modify_rmp_out_bits {
5303         u8         status[0x8];
5304         u8         reserved_0[0x18];
5305
5306         u8         syndrome[0x20];
5307
5308         u8         reserved_1[0x40];
5309 };
5310
5311 struct mlx5_ifc_rmp_bitmask_bits {
5312         u8         reserved[0x20];
5313
5314         u8         reserved1[0x1f];
5315         u8         lwm[0x1];
5316 };
5317
5318 struct mlx5_ifc_modify_rmp_in_bits {
5319         u8         opcode[0x10];
5320         u8         reserved_0[0x10];
5321
5322         u8         reserved_1[0x10];
5323         u8         op_mod[0x10];
5324
5325         u8         rmp_state[0x4];
5326         u8         reserved_2[0x4];
5327         u8         rmpn[0x18];
5328
5329         u8         reserved_3[0x20];
5330
5331         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5332
5333         u8         reserved_4[0x40];
5334
5335         struct mlx5_ifc_rmpc_bits ctx;
5336 };
5337
5338 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5339         u8         status[0x8];
5340         u8         reserved_0[0x18];
5341
5342         u8         syndrome[0x20];
5343
5344         u8         reserved_1[0x40];
5345 };
5346
5347 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5348         u8         reserved_0[0x14];
5349         u8         disable_uc_local_lb[0x1];
5350         u8         disable_mc_local_lb[0x1];
5351         u8         node_guid[0x1];
5352         u8         port_guid[0x1];
5353         u8         min_wqe_inline_mode[0x1];
5354         u8         mtu[0x1];
5355         u8         change_event[0x1];
5356         u8         promisc[0x1];
5357         u8         permanent_address[0x1];
5358         u8         addresses_list[0x1];
5359         u8         roce_en[0x1];
5360         u8         reserved_1[0x1];
5361 };
5362
5363 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5364         u8         opcode[0x10];
5365         u8         reserved_0[0x10];
5366
5367         u8         reserved_1[0x10];
5368         u8         op_mod[0x10];
5369
5370         u8         other_vport[0x1];
5371         u8         reserved_2[0xf];
5372         u8         vport_number[0x10];
5373
5374         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5375
5376         u8         reserved_3[0x780];
5377
5378         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5379 };
5380
5381 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5382         u8         status[0x8];
5383         u8         reserved_0[0x18];
5384
5385         u8         syndrome[0x20];
5386
5387         u8         reserved_1[0x40];
5388 };
5389
5390 struct mlx5_ifc_grh_bits {
5391         u8      ip_version[4];
5392         u8      traffic_class[8];
5393         u8      flow_label[20];
5394         u8      payload_length[16];
5395         u8      next_header[8];
5396         u8      hop_limit[8];
5397         u8      sgid[128];
5398         u8      dgid[128];
5399 };
5400
5401 struct mlx5_ifc_bth_bits {
5402         u8      opcode[8];
5403         u8      se[1];
5404         u8      migreq[1];
5405         u8      pad_count[2];
5406         u8      tver[4];
5407         u8      p_key[16];
5408         u8      reserved8[8];
5409         u8      dest_qp[24];
5410         u8      ack_req[1];
5411         u8      reserved7[7];
5412         u8      psn[24];
5413 };
5414
5415 struct mlx5_ifc_aeth_bits {
5416         u8      syndrome[8];
5417         u8      msn[24];
5418 };
5419
5420 struct mlx5_ifc_dceth_bits {
5421         u8      reserved0[8];
5422         u8      session_id[24];
5423         u8      reserved1[8];
5424         u8      dci_dct[24];
5425 };
5426
5427 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5428         u8         opcode[0x10];
5429         u8         reserved_0[0x10];
5430
5431         u8         reserved_1[0x10];
5432         u8         op_mod[0x10];
5433
5434         u8         other_vport[0x1];
5435         u8         reserved_2[0xb];
5436         u8         port_num[0x4];
5437         u8         vport_number[0x10];
5438
5439         u8         reserved_3[0x20];
5440
5441         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5442 };
5443
5444 struct mlx5_ifc_modify_flow_table_out_bits {
5445         u8         status[0x8];
5446         u8         reserved_at_8[0x18];
5447
5448         u8         syndrome[0x20];
5449
5450         u8         reserved_at_40[0x40];
5451 };
5452
5453 enum {
5454         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5455         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5456 };
5457
5458 struct mlx5_ifc_modify_flow_table_in_bits {
5459         u8         opcode[0x10];
5460         u8         reserved_at_10[0x10];
5461
5462         u8         reserved_at_20[0x10];
5463         u8         op_mod[0x10];
5464
5465         u8         other_vport[0x1];
5466         u8         reserved_at_41[0xf];
5467         u8         vport_number[0x10];
5468
5469         u8         reserved_at_60[0x10];
5470         u8         modify_field_select[0x10];
5471
5472         u8         table_type[0x8];
5473         u8         reserved_at_88[0x18];
5474
5475         u8         reserved_at_a0[0x8];
5476         u8         table_id[0x18];
5477
5478         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5479 };
5480
5481 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5482         u8         status[0x8];
5483         u8         reserved_0[0x18];
5484
5485         u8         syndrome[0x20];
5486
5487         u8         reserved_1[0x40];
5488 };
5489
5490 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5491         u8         reserved[0x1c];
5492         u8         vport_cvlan_insert[0x1];
5493         u8         vport_svlan_insert[0x1];
5494         u8         vport_cvlan_strip[0x1];
5495         u8         vport_svlan_strip[0x1];
5496 };
5497
5498 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5499         u8         opcode[0x10];
5500         u8         reserved_0[0x10];
5501
5502         u8         reserved_1[0x10];
5503         u8         op_mod[0x10];
5504
5505         u8         other_vport[0x1];
5506         u8         reserved_2[0xf];
5507         u8         vport_number[0x10];
5508
5509         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5510
5511         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5512 };
5513
5514 struct mlx5_ifc_modify_cq_out_bits {
5515         u8         status[0x8];
5516         u8         reserved_0[0x18];
5517
5518         u8         syndrome[0x20];
5519
5520         u8         reserved_1[0x40];
5521 };
5522
5523 enum {
5524         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5525         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5526 };
5527
5528 struct mlx5_ifc_modify_cq_in_bits {
5529         u8         opcode[0x10];
5530         u8         reserved_0[0x10];
5531
5532         u8         reserved_1[0x10];
5533         u8         op_mod[0x10];
5534
5535         u8         reserved_2[0x8];
5536         u8         cqn[0x18];
5537
5538         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5539
5540         struct mlx5_ifc_cqc_bits cq_context;
5541
5542         u8         reserved_3[0x600];
5543
5544         u8         pas[0][0x40];
5545 };
5546
5547 struct mlx5_ifc_modify_cong_status_out_bits {
5548         u8         status[0x8];
5549         u8         reserved_0[0x18];
5550
5551         u8         syndrome[0x20];
5552
5553         u8         reserved_1[0x40];
5554 };
5555
5556 struct mlx5_ifc_modify_cong_status_in_bits {
5557         u8         opcode[0x10];
5558         u8         reserved_0[0x10];
5559
5560         u8         reserved_1[0x10];
5561         u8         op_mod[0x10];
5562
5563         u8         reserved_2[0x18];
5564         u8         priority[0x4];
5565         u8         cong_protocol[0x4];
5566
5567         u8         enable[0x1];
5568         u8         tag_enable[0x1];
5569         u8         reserved_3[0x1e];
5570 };
5571
5572 struct mlx5_ifc_modify_cong_params_out_bits {
5573         u8         status[0x8];
5574         u8         reserved_0[0x18];
5575
5576         u8         syndrome[0x20];
5577
5578         u8         reserved_1[0x40];
5579 };
5580
5581 struct mlx5_ifc_modify_cong_params_in_bits {
5582         u8         opcode[0x10];
5583         u8         reserved_0[0x10];
5584
5585         u8         reserved_1[0x10];
5586         u8         op_mod[0x10];
5587
5588         u8         reserved_2[0x1c];
5589         u8         cong_protocol[0x4];
5590
5591         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5592
5593         u8         reserved_3[0x80];
5594
5595         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5596 };
5597
5598 struct mlx5_ifc_manage_pages_out_bits {
5599         u8         status[0x8];
5600         u8         reserved_0[0x18];
5601
5602         u8         syndrome[0x20];
5603
5604         u8         output_num_entries[0x20];
5605
5606         u8         reserved_1[0x20];
5607
5608         u8         pas[0][0x40];
5609 };
5610
5611 enum {
5612         MLX5_PAGES_CANT_GIVE                            = 0x0,
5613         MLX5_PAGES_GIVE                                 = 0x1,
5614         MLX5_PAGES_TAKE                                 = 0x2,
5615 };
5616
5617 struct mlx5_ifc_manage_pages_in_bits {
5618         u8         opcode[0x10];
5619         u8         reserved_0[0x10];
5620
5621         u8         reserved_1[0x10];
5622         u8         op_mod[0x10];
5623
5624         u8         reserved_2[0x10];
5625         u8         function_id[0x10];
5626
5627         u8         input_num_entries[0x20];
5628
5629         u8         pas[0][0x40];
5630 };
5631
5632 struct mlx5_ifc_mad_ifc_out_bits {
5633         u8         status[0x8];
5634         u8         reserved_0[0x18];
5635
5636         u8         syndrome[0x20];
5637
5638         u8         reserved_1[0x40];
5639
5640         u8         response_mad_packet[256][0x8];
5641 };
5642
5643 struct mlx5_ifc_mad_ifc_in_bits {
5644         u8         opcode[0x10];
5645         u8         reserved_0[0x10];
5646
5647         u8         reserved_1[0x10];
5648         u8         op_mod[0x10];
5649
5650         u8         remote_lid[0x10];
5651         u8         reserved_2[0x8];
5652         u8         port[0x8];
5653
5654         u8         reserved_3[0x20];
5655
5656         u8         mad[256][0x8];
5657 };
5658
5659 struct mlx5_ifc_init_hca_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_0[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_1[0x40];
5666 };
5667
5668 enum {
5669         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5670         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5671 };
5672
5673 struct mlx5_ifc_init_hca_in_bits {
5674         u8         opcode[0x10];
5675         u8         reserved_0[0x10];
5676
5677         u8         reserved_1[0x10];
5678         u8         op_mod[0x10];
5679
5680         u8         reserved_2[0x40];
5681 };
5682
5683 struct mlx5_ifc_init2rtr_qp_out_bits {
5684         u8         status[0x8];
5685         u8         reserved_0[0x18];
5686
5687         u8         syndrome[0x20];
5688
5689         u8         reserved_1[0x40];
5690 };
5691
5692 struct mlx5_ifc_init2rtr_qp_in_bits {
5693         u8         opcode[0x10];
5694         u8         reserved_0[0x10];
5695
5696         u8         reserved_1[0x10];
5697         u8         op_mod[0x10];
5698
5699         u8         reserved_2[0x8];
5700         u8         qpn[0x18];
5701
5702         u8         reserved_3[0x20];
5703
5704         u8         opt_param_mask[0x20];
5705
5706         u8         reserved_4[0x20];
5707
5708         struct mlx5_ifc_qpc_bits qpc;
5709
5710         u8         reserved_5[0x80];
5711 };
5712
5713 struct mlx5_ifc_init2init_qp_out_bits {
5714         u8         status[0x8];
5715         u8         reserved_0[0x18];
5716
5717         u8         syndrome[0x20];
5718
5719         u8         reserved_1[0x40];
5720 };
5721
5722 struct mlx5_ifc_init2init_qp_in_bits {
5723         u8         opcode[0x10];
5724         u8         reserved_0[0x10];
5725
5726         u8         reserved_1[0x10];
5727         u8         op_mod[0x10];
5728
5729         u8         reserved_2[0x8];
5730         u8         qpn[0x18];
5731
5732         u8         reserved_3[0x20];
5733
5734         u8         opt_param_mask[0x20];
5735
5736         u8         reserved_4[0x20];
5737
5738         struct mlx5_ifc_qpc_bits qpc;
5739
5740         u8         reserved_5[0x80];
5741 };
5742
5743 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5744         u8         status[0x8];
5745         u8         reserved_0[0x18];
5746
5747         u8         syndrome[0x20];
5748
5749         u8         reserved_1[0x40];
5750
5751         u8         packet_headers_log[128][0x8];
5752
5753         u8         packet_syndrome[64][0x8];
5754 };
5755
5756 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5757         u8         opcode[0x10];
5758         u8         reserved_0[0x10];
5759
5760         u8         reserved_1[0x10];
5761         u8         op_mod[0x10];
5762
5763         u8         reserved_2[0x40];
5764 };
5765
5766 struct mlx5_ifc_gen_eqe_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_0[0x10];
5769
5770         u8         reserved_1[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         reserved_2[0x18];
5774         u8         eq_number[0x8];
5775
5776         u8         reserved_3[0x20];
5777
5778         u8         eqe[64][0x8];
5779 };
5780
5781 struct mlx5_ifc_gen_eq_out_bits {
5782         u8         status[0x8];
5783         u8         reserved_0[0x18];
5784
5785         u8         syndrome[0x20];
5786
5787         u8         reserved_1[0x40];
5788 };
5789
5790 struct mlx5_ifc_enable_hca_out_bits {
5791         u8         status[0x8];
5792         u8         reserved_0[0x18];
5793
5794         u8         syndrome[0x20];
5795
5796         u8         reserved_1[0x20];
5797 };
5798
5799 struct mlx5_ifc_enable_hca_in_bits {
5800         u8         opcode[0x10];
5801         u8         reserved_0[0x10];
5802
5803         u8         reserved_1[0x10];
5804         u8         op_mod[0x10];
5805
5806         u8         reserved_2[0x10];
5807         u8         function_id[0x10];
5808
5809         u8         reserved_3[0x20];
5810 };
5811
5812 struct mlx5_ifc_drain_dct_out_bits {
5813         u8         status[0x8];
5814         u8         reserved_0[0x18];
5815
5816         u8         syndrome[0x20];
5817
5818         u8         reserved_1[0x40];
5819 };
5820
5821 struct mlx5_ifc_drain_dct_in_bits {
5822         u8         opcode[0x10];
5823         u8         reserved_0[0x10];
5824
5825         u8         reserved_1[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         reserved_2[0x8];
5829         u8         dctn[0x18];
5830
5831         u8         reserved_3[0x20];
5832 };
5833
5834 struct mlx5_ifc_disable_hca_out_bits {
5835         u8         status[0x8];
5836         u8         reserved_0[0x18];
5837
5838         u8         syndrome[0x20];
5839
5840         u8         reserved_1[0x20];
5841 };
5842
5843 struct mlx5_ifc_disable_hca_in_bits {
5844         u8         opcode[0x10];
5845         u8         reserved_0[0x10];
5846
5847         u8         reserved_1[0x10];
5848         u8         op_mod[0x10];
5849
5850         u8         reserved_2[0x10];
5851         u8         function_id[0x10];
5852
5853         u8         reserved_3[0x20];
5854 };
5855
5856 struct mlx5_ifc_detach_from_mcg_out_bits {
5857         u8         status[0x8];
5858         u8         reserved_0[0x18];
5859
5860         u8         syndrome[0x20];
5861
5862         u8         reserved_1[0x40];
5863 };
5864
5865 struct mlx5_ifc_detach_from_mcg_in_bits {
5866         u8         opcode[0x10];
5867         u8         reserved_0[0x10];
5868
5869         u8         reserved_1[0x10];
5870         u8         op_mod[0x10];
5871
5872         u8         reserved_2[0x8];
5873         u8         qpn[0x18];
5874
5875         u8         reserved_3[0x20];
5876
5877         u8         multicast_gid[16][0x8];
5878 };
5879
5880 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5881         u8         status[0x8];
5882         u8         reserved_0[0x18];
5883
5884         u8         syndrome[0x20];
5885
5886         u8         reserved_1[0x40];
5887 };
5888
5889 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5890         u8         opcode[0x10];
5891         u8         reserved_0[0x10];
5892
5893         u8         reserved_1[0x10];
5894         u8         op_mod[0x10];
5895
5896         u8         reserved_2[0x8];
5897         u8         xrc_srqn[0x18];
5898
5899         u8         reserved_3[0x20];
5900 };
5901
5902 struct mlx5_ifc_destroy_tis_out_bits {
5903         u8         status[0x8];
5904         u8         reserved_0[0x18];
5905
5906         u8         syndrome[0x20];
5907
5908         u8         reserved_1[0x40];
5909 };
5910
5911 struct mlx5_ifc_destroy_tis_in_bits {
5912         u8         opcode[0x10];
5913         u8         reserved_0[0x10];
5914
5915         u8         reserved_1[0x10];
5916         u8         op_mod[0x10];
5917
5918         u8         reserved_2[0x8];
5919         u8         tisn[0x18];
5920
5921         u8         reserved_3[0x20];
5922 };
5923
5924 struct mlx5_ifc_destroy_tir_out_bits {
5925         u8         status[0x8];
5926         u8         reserved_0[0x18];
5927
5928         u8         syndrome[0x20];
5929
5930         u8         reserved_1[0x40];
5931 };
5932
5933 struct mlx5_ifc_destroy_tir_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_0[0x10];
5936
5937         u8         reserved_1[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_2[0x8];
5941         u8         tirn[0x18];
5942
5943         u8         reserved_3[0x20];
5944 };
5945
5946 struct mlx5_ifc_destroy_srq_out_bits {
5947         u8         status[0x8];
5948         u8         reserved_0[0x18];
5949
5950         u8         syndrome[0x20];
5951
5952         u8         reserved_1[0x40];
5953 };
5954
5955 struct mlx5_ifc_destroy_srq_in_bits {
5956         u8         opcode[0x10];
5957         u8         reserved_0[0x10];
5958
5959         u8         reserved_1[0x10];
5960         u8         op_mod[0x10];
5961
5962         u8         reserved_2[0x8];
5963         u8         srqn[0x18];
5964
5965         u8         reserved_3[0x20];
5966 };
5967
5968 struct mlx5_ifc_destroy_sq_out_bits {
5969         u8         status[0x8];
5970         u8         reserved_0[0x18];
5971
5972         u8         syndrome[0x20];
5973
5974         u8         reserved_1[0x40];
5975 };
5976
5977 struct mlx5_ifc_destroy_sq_in_bits {
5978         u8         opcode[0x10];
5979         u8         reserved_0[0x10];
5980
5981         u8         reserved_1[0x10];
5982         u8         op_mod[0x10];
5983
5984         u8         reserved_2[0x8];
5985         u8         sqn[0x18];
5986
5987         u8         reserved_3[0x20];
5988 };
5989
5990 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5991         u8         status[0x8];
5992         u8         reserved_at_8[0x18];
5993
5994         u8         syndrome[0x20];
5995
5996         u8         reserved_at_40[0x1c0];
5997 };
5998
5999 enum {
6000         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6001 };
6002
6003 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6004         u8         opcode[0x10];
6005         u8         reserved_at_10[0x10];
6006
6007         u8         reserved_at_20[0x10];
6008         u8         op_mod[0x10];
6009
6010         u8         scheduling_hierarchy[0x8];
6011         u8         reserved_at_48[0x18];
6012
6013         u8         scheduling_element_id[0x20];
6014
6015         u8         reserved_at_80[0x180];
6016 };
6017
6018 struct mlx5_ifc_destroy_rqt_out_bits {
6019         u8         status[0x8];
6020         u8         reserved_0[0x18];
6021
6022         u8         syndrome[0x20];
6023
6024         u8         reserved_1[0x40];
6025 };
6026
6027 struct mlx5_ifc_destroy_rqt_in_bits {
6028         u8         opcode[0x10];
6029         u8         reserved_0[0x10];
6030
6031         u8         reserved_1[0x10];
6032         u8         op_mod[0x10];
6033
6034         u8         reserved_2[0x8];
6035         u8         rqtn[0x18];
6036
6037         u8         reserved_3[0x20];
6038 };
6039
6040 struct mlx5_ifc_destroy_rq_out_bits {
6041         u8         status[0x8];
6042         u8         reserved_0[0x18];
6043
6044         u8         syndrome[0x20];
6045
6046         u8         reserved_1[0x40];
6047 };
6048
6049 struct mlx5_ifc_destroy_rq_in_bits {
6050         u8         opcode[0x10];
6051         u8         reserved_0[0x10];
6052
6053         u8         reserved_1[0x10];
6054         u8         op_mod[0x10];
6055
6056         u8         reserved_2[0x8];
6057         u8         rqn[0x18];
6058
6059         u8         reserved_3[0x20];
6060 };
6061
6062 struct mlx5_ifc_destroy_rmp_out_bits {
6063         u8         status[0x8];
6064         u8         reserved_0[0x18];
6065
6066         u8         syndrome[0x20];
6067
6068         u8         reserved_1[0x40];
6069 };
6070
6071 struct mlx5_ifc_destroy_rmp_in_bits {
6072         u8         opcode[0x10];
6073         u8         reserved_0[0x10];
6074
6075         u8         reserved_1[0x10];
6076         u8         op_mod[0x10];
6077
6078         u8         reserved_2[0x8];
6079         u8         rmpn[0x18];
6080
6081         u8         reserved_3[0x20];
6082 };
6083
6084 struct mlx5_ifc_destroy_qp_out_bits {
6085         u8         status[0x8];
6086         u8         reserved_0[0x18];
6087
6088         u8         syndrome[0x20];
6089
6090         u8         reserved_1[0x40];
6091 };
6092
6093 struct mlx5_ifc_destroy_qp_in_bits {
6094         u8         opcode[0x10];
6095         u8         reserved_0[0x10];
6096
6097         u8         reserved_1[0x10];
6098         u8         op_mod[0x10];
6099
6100         u8         reserved_2[0x8];
6101         u8         qpn[0x18];
6102
6103         u8         reserved_3[0x20];
6104 };
6105
6106 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6107         u8         status[0x8];
6108         u8         reserved_at_8[0x18];
6109
6110         u8         syndrome[0x20];
6111
6112         u8         reserved_at_40[0x1c0];
6113 };
6114
6115 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6116         u8         opcode[0x10];
6117         u8         reserved_at_10[0x10];
6118
6119         u8         reserved_at_20[0x10];
6120         u8         op_mod[0x10];
6121
6122         u8         reserved_at_40[0x20];
6123
6124         u8         reserved_at_60[0x10];
6125         u8         qos_para_vport_number[0x10];
6126
6127         u8         reserved_at_80[0x180];
6128 };
6129
6130 struct mlx5_ifc_destroy_psv_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_0[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_1[0x40];
6137 };
6138
6139 struct mlx5_ifc_destroy_psv_in_bits {
6140         u8         opcode[0x10];
6141         u8         reserved_0[0x10];
6142
6143         u8         reserved_1[0x10];
6144         u8         op_mod[0x10];
6145
6146         u8         reserved_2[0x8];
6147         u8         psvn[0x18];
6148
6149         u8         reserved_3[0x20];
6150 };
6151
6152 struct mlx5_ifc_destroy_mkey_out_bits {
6153         u8         status[0x8];
6154         u8         reserved_0[0x18];
6155
6156         u8         syndrome[0x20];
6157
6158         u8         reserved_1[0x40];
6159 };
6160
6161 struct mlx5_ifc_destroy_mkey_in_bits {
6162         u8         opcode[0x10];
6163         u8         reserved_0[0x10];
6164
6165         u8         reserved_1[0x10];
6166         u8         op_mod[0x10];
6167
6168         u8         reserved_2[0x8];
6169         u8         mkey_index[0x18];
6170
6171         u8         reserved_3[0x20];
6172 };
6173
6174 struct mlx5_ifc_destroy_flow_table_out_bits {
6175         u8         status[0x8];
6176         u8         reserved_0[0x18];
6177
6178         u8         syndrome[0x20];
6179
6180         u8         reserved_1[0x40];
6181 };
6182
6183 struct mlx5_ifc_destroy_flow_table_in_bits {
6184         u8         opcode[0x10];
6185         u8         reserved_0[0x10];
6186
6187         u8         reserved_1[0x10];
6188         u8         op_mod[0x10];
6189
6190         u8         other_vport[0x1];
6191         u8         reserved_2[0xf];
6192         u8         vport_number[0x10];
6193
6194         u8         reserved_3[0x20];
6195
6196         u8         table_type[0x8];
6197         u8         reserved_4[0x18];
6198
6199         u8         reserved_5[0x8];
6200         u8         table_id[0x18];
6201
6202         u8         reserved_6[0x140];
6203 };
6204
6205 struct mlx5_ifc_destroy_flow_group_out_bits {
6206         u8         status[0x8];
6207         u8         reserved_0[0x18];
6208
6209         u8         syndrome[0x20];
6210
6211         u8         reserved_1[0x40];
6212 };
6213
6214 struct mlx5_ifc_destroy_flow_group_in_bits {
6215         u8         opcode[0x10];
6216         u8         reserved_0[0x10];
6217
6218         u8         reserved_1[0x10];
6219         u8         op_mod[0x10];
6220
6221         u8         other_vport[0x1];
6222         u8         reserved_2[0xf];
6223         u8         vport_number[0x10];
6224
6225         u8         reserved_3[0x20];
6226
6227         u8         table_type[0x8];
6228         u8         reserved_4[0x18];
6229
6230         u8         reserved_5[0x8];
6231         u8         table_id[0x18];
6232
6233         u8         group_id[0x20];
6234
6235         u8         reserved_6[0x120];
6236 };
6237
6238 struct mlx5_ifc_destroy_eq_out_bits {
6239         u8         status[0x8];
6240         u8         reserved_0[0x18];
6241
6242         u8         syndrome[0x20];
6243
6244         u8         reserved_1[0x40];
6245 };
6246
6247 struct mlx5_ifc_destroy_eq_in_bits {
6248         u8         opcode[0x10];
6249         u8         reserved_0[0x10];
6250
6251         u8         reserved_1[0x10];
6252         u8         op_mod[0x10];
6253
6254         u8         reserved_2[0x18];
6255         u8         eq_number[0x8];
6256
6257         u8         reserved_3[0x20];
6258 };
6259
6260 struct mlx5_ifc_destroy_dct_out_bits {
6261         u8         status[0x8];
6262         u8         reserved_0[0x18];
6263
6264         u8         syndrome[0x20];
6265
6266         u8         reserved_1[0x40];
6267 };
6268
6269 struct mlx5_ifc_destroy_dct_in_bits {
6270         u8         opcode[0x10];
6271         u8         reserved_0[0x10];
6272
6273         u8         reserved_1[0x10];
6274         u8         op_mod[0x10];
6275
6276         u8         reserved_2[0x8];
6277         u8         dctn[0x18];
6278
6279         u8         reserved_3[0x20];
6280 };
6281
6282 struct mlx5_ifc_destroy_cq_out_bits {
6283         u8         status[0x8];
6284         u8         reserved_0[0x18];
6285
6286         u8         syndrome[0x20];
6287
6288         u8         reserved_1[0x40];
6289 };
6290
6291 struct mlx5_ifc_destroy_cq_in_bits {
6292         u8         opcode[0x10];
6293         u8         reserved_0[0x10];
6294
6295         u8         reserved_1[0x10];
6296         u8         op_mod[0x10];
6297
6298         u8         reserved_2[0x8];
6299         u8         cqn[0x18];
6300
6301         u8         reserved_3[0x20];
6302 };
6303
6304 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6305         u8         status[0x8];
6306         u8         reserved_0[0x18];
6307
6308         u8         syndrome[0x20];
6309
6310         u8         reserved_1[0x40];
6311 };
6312
6313 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6314         u8         opcode[0x10];
6315         u8         reserved_0[0x10];
6316
6317         u8         reserved_1[0x10];
6318         u8         op_mod[0x10];
6319
6320         u8         reserved_2[0x20];
6321
6322         u8         reserved_3[0x10];
6323         u8         vxlan_udp_port[0x10];
6324 };
6325
6326 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6327         u8         status[0x8];
6328         u8         reserved_0[0x18];
6329
6330         u8         syndrome[0x20];
6331
6332         u8         reserved_1[0x40];
6333 };
6334
6335 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6336         u8         opcode[0x10];
6337         u8         reserved_0[0x10];
6338
6339         u8         reserved_1[0x10];
6340         u8         op_mod[0x10];
6341
6342         u8         reserved_2[0x60];
6343
6344         u8         reserved_3[0x8];
6345         u8         table_index[0x18];
6346
6347         u8         reserved_4[0x140];
6348 };
6349
6350 struct mlx5_ifc_delete_fte_out_bits {
6351         u8         status[0x8];
6352         u8         reserved_0[0x18];
6353
6354         u8         syndrome[0x20];
6355
6356         u8         reserved_1[0x40];
6357 };
6358
6359 struct mlx5_ifc_delete_fte_in_bits {
6360         u8         opcode[0x10];
6361         u8         reserved_0[0x10];
6362
6363         u8         reserved_1[0x10];
6364         u8         op_mod[0x10];
6365
6366         u8         other_vport[0x1];
6367         u8         reserved_2[0xf];
6368         u8         vport_number[0x10];
6369
6370         u8         reserved_3[0x20];
6371
6372         u8         table_type[0x8];
6373         u8         reserved_4[0x18];
6374
6375         u8         reserved_5[0x8];
6376         u8         table_id[0x18];
6377
6378         u8         reserved_6[0x40];
6379
6380         u8         flow_index[0x20];
6381
6382         u8         reserved_7[0xe0];
6383 };
6384
6385 struct mlx5_ifc_dealloc_xrcd_out_bits {
6386         u8         status[0x8];
6387         u8         reserved_0[0x18];
6388
6389         u8         syndrome[0x20];
6390
6391         u8         reserved_1[0x40];
6392 };
6393
6394 struct mlx5_ifc_dealloc_xrcd_in_bits {
6395         u8         opcode[0x10];
6396         u8         reserved_0[0x10];
6397
6398         u8         reserved_1[0x10];
6399         u8         op_mod[0x10];
6400
6401         u8         reserved_2[0x8];
6402         u8         xrcd[0x18];
6403
6404         u8         reserved_3[0x20];
6405 };
6406
6407 struct mlx5_ifc_dealloc_uar_out_bits {
6408         u8         status[0x8];
6409         u8         reserved_0[0x18];
6410
6411         u8         syndrome[0x20];
6412
6413         u8         reserved_1[0x40];
6414 };
6415
6416 struct mlx5_ifc_dealloc_uar_in_bits {
6417         u8         opcode[0x10];
6418         u8         reserved_0[0x10];
6419
6420         u8         reserved_1[0x10];
6421         u8         op_mod[0x10];
6422
6423         u8         reserved_2[0x8];
6424         u8         uar[0x18];
6425
6426         u8         reserved_3[0x20];
6427 };
6428
6429 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6430         u8         status[0x8];
6431         u8         reserved_0[0x18];
6432
6433         u8         syndrome[0x20];
6434
6435         u8         reserved_1[0x40];
6436 };
6437
6438 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6439         u8         opcode[0x10];
6440         u8         reserved_0[0x10];
6441
6442         u8         reserved_1[0x10];
6443         u8         op_mod[0x10];
6444
6445         u8         reserved_2[0x8];
6446         u8         transport_domain[0x18];
6447
6448         u8         reserved_3[0x20];
6449 };
6450
6451 struct mlx5_ifc_dealloc_q_counter_out_bits {
6452         u8         status[0x8];
6453         u8         reserved_0[0x18];
6454
6455         u8         syndrome[0x20];
6456
6457         u8         reserved_1[0x40];
6458 };
6459
6460 struct mlx5_ifc_counter_id_bits {
6461         u8         reserved[0x10];
6462         u8         counter_id[0x10];
6463 };
6464
6465 struct mlx5_ifc_diagnostic_params_context_bits {
6466         u8         num_of_counters[0x10];
6467         u8         reserved_2[0x8];
6468         u8         log_num_of_samples[0x8];
6469
6470         u8         single[0x1];
6471         u8         repetitive[0x1];
6472         u8         sync[0x1];
6473         u8         clear[0x1];
6474         u8         on_demand[0x1];
6475         u8         enable[0x1];
6476         u8         reserved_3[0x12];
6477         u8         log_sample_period[0x8];
6478
6479         u8         reserved_4[0x80];
6480
6481         struct mlx5_ifc_counter_id_bits counter_id[0];
6482 };
6483
6484 struct mlx5_ifc_set_diagnostic_params_in_bits {
6485         u8         opcode[0x10];
6486         u8         reserved_0[0x10];
6487
6488         u8         reserved_1[0x10];
6489         u8         op_mod[0x10];
6490
6491         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6492 };
6493
6494 struct mlx5_ifc_set_diagnostic_params_out_bits {
6495         u8         status[0x8];
6496         u8         reserved_0[0x18];
6497
6498         u8         syndrome[0x20];
6499
6500         u8         reserved_1[0x40];
6501 };
6502
6503 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6504         u8         opcode[0x10];
6505         u8         reserved_0[0x10];
6506
6507         u8         reserved_1[0x10];
6508         u8         op_mod[0x10];
6509
6510         u8         num_of_samples[0x10];
6511         u8         sample_index[0x10];
6512
6513         u8         reserved_2[0x20];
6514 };
6515
6516 struct mlx5_ifc_diagnostic_counter_bits {
6517         u8         counter_id[0x10];
6518         u8         sample_id[0x10];
6519
6520         u8         time_stamp_31_0[0x20];
6521
6522         u8         counter_value_h[0x20];
6523
6524         u8         counter_value_l[0x20];
6525 };
6526
6527 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6528         u8         status[0x8];
6529         u8         reserved_0[0x18];
6530
6531         u8         syndrome[0x20];
6532
6533         u8         reserved_1[0x40];
6534
6535         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6536 };
6537
6538 struct mlx5_ifc_dealloc_q_counter_in_bits {
6539         u8         opcode[0x10];
6540         u8         reserved_0[0x10];
6541
6542         u8         reserved_1[0x10];
6543         u8         op_mod[0x10];
6544
6545         u8         reserved_2[0x18];
6546         u8         counter_set_id[0x8];
6547
6548         u8         reserved_3[0x20];
6549 };
6550
6551 struct mlx5_ifc_dealloc_pd_out_bits {
6552         u8         status[0x8];
6553         u8         reserved_0[0x18];
6554
6555         u8         syndrome[0x20];
6556
6557         u8         reserved_1[0x40];
6558 };
6559
6560 struct mlx5_ifc_dealloc_pd_in_bits {
6561         u8         opcode[0x10];
6562         u8         reserved_0[0x10];
6563
6564         u8         reserved_1[0x10];
6565         u8         op_mod[0x10];
6566
6567         u8         reserved_2[0x8];
6568         u8         pd[0x18];
6569
6570         u8         reserved_3[0x20];
6571 };
6572
6573 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6574         u8         status[0x8];
6575         u8         reserved_0[0x18];
6576
6577         u8         syndrome[0x20];
6578
6579         u8         reserved_1[0x40];
6580 };
6581
6582 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6583         u8         opcode[0x10];
6584         u8         reserved_0[0x10];
6585
6586         u8         reserved_1[0x10];
6587         u8         op_mod[0x10];
6588
6589         u8         reserved_2[0x10];
6590         u8         flow_counter_id[0x10];
6591
6592         u8         reserved_3[0x20];
6593 };
6594
6595 struct mlx5_ifc_deactivate_tracer_out_bits {
6596         u8         status[0x8];
6597         u8         reserved_0[0x18];
6598
6599         u8         syndrome[0x20];
6600
6601         u8         reserved_1[0x40];
6602 };
6603
6604 struct mlx5_ifc_deactivate_tracer_in_bits {
6605         u8         opcode[0x10];
6606         u8         reserved_0[0x10];
6607
6608         u8         reserved_1[0x10];
6609         u8         op_mod[0x10];
6610
6611         u8         mkey[0x20];
6612
6613         u8         reserved_2[0x20];
6614 };
6615
6616 struct mlx5_ifc_create_xrc_srq_out_bits {
6617         u8         status[0x8];
6618         u8         reserved_0[0x18];
6619
6620         u8         syndrome[0x20];
6621
6622         u8         reserved_1[0x8];
6623         u8         xrc_srqn[0x18];
6624
6625         u8         reserved_2[0x20];
6626 };
6627
6628 struct mlx5_ifc_create_xrc_srq_in_bits {
6629         u8         opcode[0x10];
6630         u8         reserved_0[0x10];
6631
6632         u8         reserved_1[0x10];
6633         u8         op_mod[0x10];
6634
6635         u8         reserved_2[0x40];
6636
6637         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6638
6639         u8         reserved_3[0x600];
6640
6641         u8         pas[0][0x40];
6642 };
6643
6644 struct mlx5_ifc_create_tis_out_bits {
6645         u8         status[0x8];
6646         u8         reserved_0[0x18];
6647
6648         u8         syndrome[0x20];
6649
6650         u8         reserved_1[0x8];
6651         u8         tisn[0x18];
6652
6653         u8         reserved_2[0x20];
6654 };
6655
6656 struct mlx5_ifc_create_tis_in_bits {
6657         u8         opcode[0x10];
6658         u8         reserved_0[0x10];
6659
6660         u8         reserved_1[0x10];
6661         u8         op_mod[0x10];
6662
6663         u8         reserved_2[0xc0];
6664
6665         struct mlx5_ifc_tisc_bits ctx;
6666 };
6667
6668 struct mlx5_ifc_create_tir_out_bits {
6669         u8         status[0x8];
6670         u8         reserved_0[0x18];
6671
6672         u8         syndrome[0x20];
6673
6674         u8         reserved_1[0x8];
6675         u8         tirn[0x18];
6676
6677         u8         reserved_2[0x20];
6678 };
6679
6680 struct mlx5_ifc_create_tir_in_bits {
6681         u8         opcode[0x10];
6682         u8         reserved_0[0x10];
6683
6684         u8         reserved_1[0x10];
6685         u8         op_mod[0x10];
6686
6687         u8         reserved_2[0xc0];
6688
6689         struct mlx5_ifc_tirc_bits tir_context;
6690 };
6691
6692 struct mlx5_ifc_create_srq_out_bits {
6693         u8         status[0x8];
6694         u8         reserved_0[0x18];
6695
6696         u8         syndrome[0x20];
6697
6698         u8         reserved_1[0x8];
6699         u8         srqn[0x18];
6700
6701         u8         reserved_2[0x20];
6702 };
6703
6704 struct mlx5_ifc_create_srq_in_bits {
6705         u8         opcode[0x10];
6706         u8         reserved_0[0x10];
6707
6708         u8         reserved_1[0x10];
6709         u8         op_mod[0x10];
6710
6711         u8         reserved_2[0x40];
6712
6713         struct mlx5_ifc_srqc_bits srq_context_entry;
6714
6715         u8         reserved_3[0x600];
6716
6717         u8         pas[0][0x40];
6718 };
6719
6720 struct mlx5_ifc_create_sq_out_bits {
6721         u8         status[0x8];
6722         u8         reserved_0[0x18];
6723
6724         u8         syndrome[0x20];
6725
6726         u8         reserved_1[0x8];
6727         u8         sqn[0x18];
6728
6729         u8         reserved_2[0x20];
6730 };
6731
6732 struct mlx5_ifc_create_sq_in_bits {
6733         u8         opcode[0x10];
6734         u8         reserved_0[0x10];
6735
6736         u8         reserved_1[0x10];
6737         u8         op_mod[0x10];
6738
6739         u8         reserved_2[0xc0];
6740
6741         struct mlx5_ifc_sqc_bits ctx;
6742 };
6743
6744 struct mlx5_ifc_create_scheduling_element_out_bits {
6745         u8         status[0x8];
6746         u8         reserved_at_8[0x18];
6747
6748         u8         syndrome[0x20];
6749
6750         u8         reserved_at_40[0x40];
6751
6752         u8         scheduling_element_id[0x20];
6753
6754         u8         reserved_at_a0[0x160];
6755 };
6756
6757 enum {
6758         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6759 };
6760
6761 struct mlx5_ifc_create_scheduling_element_in_bits {
6762         u8         opcode[0x10];
6763         u8         reserved_at_10[0x10];
6764
6765         u8         reserved_at_20[0x10];
6766         u8         op_mod[0x10];
6767
6768         u8         scheduling_hierarchy[0x8];
6769         u8         reserved_at_48[0x18];
6770
6771         u8         reserved_at_60[0xa0];
6772
6773         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6774
6775         u8         reserved_at_300[0x100];
6776 };
6777
6778 struct mlx5_ifc_create_rqt_out_bits {
6779         u8         status[0x8];
6780         u8         reserved_0[0x18];
6781
6782         u8         syndrome[0x20];
6783
6784         u8         reserved_1[0x8];
6785         u8         rqtn[0x18];
6786
6787         u8         reserved_2[0x20];
6788 };
6789
6790 struct mlx5_ifc_create_rqt_in_bits {
6791         u8         opcode[0x10];
6792         u8         reserved_0[0x10];
6793
6794         u8         reserved_1[0x10];
6795         u8         op_mod[0x10];
6796
6797         u8         reserved_2[0xc0];
6798
6799         struct mlx5_ifc_rqtc_bits rqt_context;
6800 };
6801
6802 struct mlx5_ifc_create_rq_out_bits {
6803         u8         status[0x8];
6804         u8         reserved_0[0x18];
6805
6806         u8         syndrome[0x20];
6807
6808         u8         reserved_1[0x8];
6809         u8         rqn[0x18];
6810
6811         u8         reserved_2[0x20];
6812 };
6813
6814 struct mlx5_ifc_create_rq_in_bits {
6815         u8         opcode[0x10];
6816         u8         reserved_0[0x10];
6817
6818         u8         reserved_1[0x10];
6819         u8         op_mod[0x10];
6820
6821         u8         reserved_2[0xc0];
6822
6823         struct mlx5_ifc_rqc_bits ctx;
6824 };
6825
6826 struct mlx5_ifc_create_rmp_out_bits {
6827         u8         status[0x8];
6828         u8         reserved_0[0x18];
6829
6830         u8         syndrome[0x20];
6831
6832         u8         reserved_1[0x8];
6833         u8         rmpn[0x18];
6834
6835         u8         reserved_2[0x20];
6836 };
6837
6838 struct mlx5_ifc_create_rmp_in_bits {
6839         u8         opcode[0x10];
6840         u8         reserved_0[0x10];
6841
6842         u8         reserved_1[0x10];
6843         u8         op_mod[0x10];
6844
6845         u8         reserved_2[0xc0];
6846
6847         struct mlx5_ifc_rmpc_bits ctx;
6848 };
6849
6850 struct mlx5_ifc_create_qp_out_bits {
6851         u8         status[0x8];
6852         u8         reserved_0[0x18];
6853
6854         u8         syndrome[0x20];
6855
6856         u8         reserved_1[0x8];
6857         u8         qpn[0x18];
6858
6859         u8         reserved_2[0x20];
6860 };
6861
6862 struct mlx5_ifc_create_qp_in_bits {
6863         u8         opcode[0x10];
6864         u8         reserved_0[0x10];
6865
6866         u8         reserved_1[0x10];
6867         u8         op_mod[0x10];
6868
6869         u8         reserved_2[0x8];
6870         u8         input_qpn[0x18];
6871
6872         u8         reserved_3[0x20];
6873
6874         u8         opt_param_mask[0x20];
6875
6876         u8         reserved_4[0x20];
6877
6878         struct mlx5_ifc_qpc_bits qpc;
6879
6880         u8         reserved_5[0x80];
6881
6882         u8         pas[0][0x40];
6883 };
6884
6885 struct mlx5_ifc_create_qos_para_vport_out_bits {
6886         u8         status[0x8];
6887         u8         reserved_at_8[0x18];
6888
6889         u8         syndrome[0x20];
6890
6891         u8         reserved_at_40[0x20];
6892
6893         u8         reserved_at_60[0x10];
6894         u8         qos_para_vport_number[0x10];
6895
6896         u8         reserved_at_80[0x180];
6897 };
6898
6899 struct mlx5_ifc_create_qos_para_vport_in_bits {
6900         u8         opcode[0x10];
6901         u8         reserved_at_10[0x10];
6902
6903         u8         reserved_at_20[0x10];
6904         u8         op_mod[0x10];
6905
6906         u8         reserved_at_40[0x1c0];
6907 };
6908
6909 struct mlx5_ifc_create_psv_out_bits {
6910         u8         status[0x8];
6911         u8         reserved_0[0x18];
6912
6913         u8         syndrome[0x20];
6914
6915         u8         reserved_1[0x40];
6916
6917         u8         reserved_2[0x8];
6918         u8         psv0_index[0x18];
6919
6920         u8         reserved_3[0x8];
6921         u8         psv1_index[0x18];
6922
6923         u8         reserved_4[0x8];
6924         u8         psv2_index[0x18];
6925
6926         u8         reserved_5[0x8];
6927         u8         psv3_index[0x18];
6928 };
6929
6930 struct mlx5_ifc_create_psv_in_bits {
6931         u8         opcode[0x10];
6932         u8         reserved_0[0x10];
6933
6934         u8         reserved_1[0x10];
6935         u8         op_mod[0x10];
6936
6937         u8         num_psv[0x4];
6938         u8         reserved_2[0x4];
6939         u8         pd[0x18];
6940
6941         u8         reserved_3[0x20];
6942 };
6943
6944 struct mlx5_ifc_create_mkey_out_bits {
6945         u8         status[0x8];
6946         u8         reserved_0[0x18];
6947
6948         u8         syndrome[0x20];
6949
6950         u8         reserved_1[0x8];
6951         u8         mkey_index[0x18];
6952
6953         u8         reserved_2[0x20];
6954 };
6955
6956 struct mlx5_ifc_create_mkey_in_bits {
6957         u8         opcode[0x10];
6958         u8         reserved_0[0x10];
6959
6960         u8         reserved_1[0x10];
6961         u8         op_mod[0x10];
6962
6963         u8         reserved_2[0x20];
6964
6965         u8         pg_access[0x1];
6966         u8         reserved_3[0x1f];
6967
6968         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6969
6970         u8         reserved_4[0x80];
6971
6972         u8         translations_octword_actual_size[0x20];
6973
6974         u8         reserved_5[0x560];
6975
6976         u8         klm_pas_mtt[0][0x20];
6977 };
6978
6979 struct mlx5_ifc_create_flow_table_out_bits {
6980         u8         status[0x8];
6981         u8         reserved_0[0x18];
6982
6983         u8         syndrome[0x20];
6984
6985         u8         reserved_1[0x8];
6986         u8         table_id[0x18];
6987
6988         u8         reserved_2[0x20];
6989 };
6990
6991 struct mlx5_ifc_create_flow_table_in_bits {
6992         u8         opcode[0x10];
6993         u8         reserved_at_10[0x10];
6994
6995         u8         reserved_at_20[0x10];
6996         u8         op_mod[0x10];
6997
6998         u8         other_vport[0x1];
6999         u8         reserved_at_41[0xf];
7000         u8         vport_number[0x10];
7001
7002         u8         reserved_at_60[0x20];
7003
7004         u8         table_type[0x8];
7005         u8         reserved_at_88[0x18];
7006
7007         u8         reserved_at_a0[0x20];
7008
7009         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7010 };
7011
7012 struct mlx5_ifc_create_flow_group_out_bits {
7013         u8         status[0x8];
7014         u8         reserved_0[0x18];
7015
7016         u8         syndrome[0x20];
7017
7018         u8         reserved_1[0x8];
7019         u8         group_id[0x18];
7020
7021         u8         reserved_2[0x20];
7022 };
7023
7024 enum {
7025         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7026         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7027         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7028 };
7029
7030 struct mlx5_ifc_create_flow_group_in_bits {
7031         u8         opcode[0x10];
7032         u8         reserved_0[0x10];
7033
7034         u8         reserved_1[0x10];
7035         u8         op_mod[0x10];
7036
7037         u8         other_vport[0x1];
7038         u8         reserved_2[0xf];
7039         u8         vport_number[0x10];
7040
7041         u8         reserved_3[0x20];
7042
7043         u8         table_type[0x8];
7044         u8         reserved_4[0x18];
7045
7046         u8         reserved_5[0x8];
7047         u8         table_id[0x18];
7048
7049         u8         reserved_6[0x20];
7050
7051         u8         start_flow_index[0x20];
7052
7053         u8         reserved_7[0x20];
7054
7055         u8         end_flow_index[0x20];
7056
7057         u8         reserved_8[0xa0];
7058
7059         u8         reserved_9[0x18];
7060         u8         match_criteria_enable[0x8];
7061
7062         struct mlx5_ifc_fte_match_param_bits match_criteria;
7063
7064         u8         reserved_10[0xe00];
7065 };
7066
7067 struct mlx5_ifc_create_eq_out_bits {
7068         u8         status[0x8];
7069         u8         reserved_0[0x18];
7070
7071         u8         syndrome[0x20];
7072
7073         u8         reserved_1[0x18];
7074         u8         eq_number[0x8];
7075
7076         u8         reserved_2[0x20];
7077 };
7078
7079 struct mlx5_ifc_create_eq_in_bits {
7080         u8         opcode[0x10];
7081         u8         reserved_0[0x10];
7082
7083         u8         reserved_1[0x10];
7084         u8         op_mod[0x10];
7085
7086         u8         reserved_2[0x40];
7087
7088         struct mlx5_ifc_eqc_bits eq_context_entry;
7089
7090         u8         reserved_3[0x40];
7091
7092         u8         event_bitmask[0x40];
7093
7094         u8         reserved_4[0x580];
7095
7096         u8         pas[0][0x40];
7097 };
7098
7099 struct mlx5_ifc_create_dct_out_bits {
7100         u8         status[0x8];
7101         u8         reserved_0[0x18];
7102
7103         u8         syndrome[0x20];
7104
7105         u8         reserved_1[0x8];
7106         u8         dctn[0x18];
7107
7108         u8         reserved_2[0x20];
7109 };
7110
7111 struct mlx5_ifc_create_dct_in_bits {
7112         u8         opcode[0x10];
7113         u8         reserved_0[0x10];
7114
7115         u8         reserved_1[0x10];
7116         u8         op_mod[0x10];
7117
7118         u8         reserved_2[0x40];
7119
7120         struct mlx5_ifc_dctc_bits dct_context_entry;
7121
7122         u8         reserved_3[0x180];
7123 };
7124
7125 struct mlx5_ifc_create_cq_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_0[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_1[0x8];
7132         u8         cqn[0x18];
7133
7134         u8         reserved_2[0x20];
7135 };
7136
7137 struct mlx5_ifc_create_cq_in_bits {
7138         u8         opcode[0x10];
7139         u8         reserved_0[0x10];
7140
7141         u8         reserved_1[0x10];
7142         u8         op_mod[0x10];
7143
7144         u8         reserved_2[0x40];
7145
7146         struct mlx5_ifc_cqc_bits cq_context;
7147
7148         u8         reserved_3[0x600];
7149
7150         u8         pas[0][0x40];
7151 };
7152
7153 struct mlx5_ifc_config_int_moderation_out_bits {
7154         u8         status[0x8];
7155         u8         reserved_0[0x18];
7156
7157         u8         syndrome[0x20];
7158
7159         u8         reserved_1[0x4];
7160         u8         min_delay[0xc];
7161         u8         int_vector[0x10];
7162
7163         u8         reserved_2[0x20];
7164 };
7165
7166 enum {
7167         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7168         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7169 };
7170
7171 struct mlx5_ifc_config_int_moderation_in_bits {
7172         u8         opcode[0x10];
7173         u8         reserved_0[0x10];
7174
7175         u8         reserved_1[0x10];
7176         u8         op_mod[0x10];
7177
7178         u8         reserved_2[0x4];
7179         u8         min_delay[0xc];
7180         u8         int_vector[0x10];
7181
7182         u8         reserved_3[0x20];
7183 };
7184
7185 struct mlx5_ifc_attach_to_mcg_out_bits {
7186         u8         status[0x8];
7187         u8         reserved_0[0x18];
7188
7189         u8         syndrome[0x20];
7190
7191         u8         reserved_1[0x40];
7192 };
7193
7194 struct mlx5_ifc_attach_to_mcg_in_bits {
7195         u8         opcode[0x10];
7196         u8         reserved_0[0x10];
7197
7198         u8         reserved_1[0x10];
7199         u8         op_mod[0x10];
7200
7201         u8         reserved_2[0x8];
7202         u8         qpn[0x18];
7203
7204         u8         reserved_3[0x20];
7205
7206         u8         multicast_gid[16][0x8];
7207 };
7208
7209 struct mlx5_ifc_arm_xrc_srq_out_bits {
7210         u8         status[0x8];
7211         u8         reserved_0[0x18];
7212
7213         u8         syndrome[0x20];
7214
7215         u8         reserved_1[0x40];
7216 };
7217
7218 enum {
7219         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7220 };
7221
7222 struct mlx5_ifc_arm_xrc_srq_in_bits {
7223         u8         opcode[0x10];
7224         u8         reserved_0[0x10];
7225
7226         u8         reserved_1[0x10];
7227         u8         op_mod[0x10];
7228
7229         u8         reserved_2[0x8];
7230         u8         xrc_srqn[0x18];
7231
7232         u8         reserved_3[0x10];
7233         u8         lwm[0x10];
7234 };
7235
7236 struct mlx5_ifc_arm_rq_out_bits {
7237         u8         status[0x8];
7238         u8         reserved_0[0x18];
7239
7240         u8         syndrome[0x20];
7241
7242         u8         reserved_1[0x40];
7243 };
7244
7245 enum {
7246         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7247 };
7248
7249 struct mlx5_ifc_arm_rq_in_bits {
7250         u8         opcode[0x10];
7251         u8         reserved_0[0x10];
7252
7253         u8         reserved_1[0x10];
7254         u8         op_mod[0x10];
7255
7256         u8         reserved_2[0x8];
7257         u8         srq_number[0x18];
7258
7259         u8         reserved_3[0x10];
7260         u8         lwm[0x10];
7261 };
7262
7263 struct mlx5_ifc_arm_dct_out_bits {
7264         u8         status[0x8];
7265         u8         reserved_0[0x18];
7266
7267         u8         syndrome[0x20];
7268
7269         u8         reserved_1[0x40];
7270 };
7271
7272 struct mlx5_ifc_arm_dct_in_bits {
7273         u8         opcode[0x10];
7274         u8         reserved_0[0x10];
7275
7276         u8         reserved_1[0x10];
7277         u8         op_mod[0x10];
7278
7279         u8         reserved_2[0x8];
7280         u8         dctn[0x18];
7281
7282         u8         reserved_3[0x20];
7283 };
7284
7285 struct mlx5_ifc_alloc_xrcd_out_bits {
7286         u8         status[0x8];
7287         u8         reserved_0[0x18];
7288
7289         u8         syndrome[0x20];
7290
7291         u8         reserved_1[0x8];
7292         u8         xrcd[0x18];
7293
7294         u8         reserved_2[0x20];
7295 };
7296
7297 struct mlx5_ifc_alloc_xrcd_in_bits {
7298         u8         opcode[0x10];
7299         u8         reserved_0[0x10];
7300
7301         u8         reserved_1[0x10];
7302         u8         op_mod[0x10];
7303
7304         u8         reserved_2[0x40];
7305 };
7306
7307 struct mlx5_ifc_alloc_uar_out_bits {
7308         u8         status[0x8];
7309         u8         reserved_0[0x18];
7310
7311         u8         syndrome[0x20];
7312
7313         u8         reserved_1[0x8];
7314         u8         uar[0x18];
7315
7316         u8         reserved_2[0x20];
7317 };
7318
7319 struct mlx5_ifc_alloc_uar_in_bits {
7320         u8         opcode[0x10];
7321         u8         reserved_0[0x10];
7322
7323         u8         reserved_1[0x10];
7324         u8         op_mod[0x10];
7325
7326         u8         reserved_2[0x40];
7327 };
7328
7329 struct mlx5_ifc_alloc_transport_domain_out_bits {
7330         u8         status[0x8];
7331         u8         reserved_0[0x18];
7332
7333         u8         syndrome[0x20];
7334
7335         u8         reserved_1[0x8];
7336         u8         transport_domain[0x18];
7337
7338         u8         reserved_2[0x20];
7339 };
7340
7341 struct mlx5_ifc_alloc_transport_domain_in_bits {
7342         u8         opcode[0x10];
7343         u8         reserved_0[0x10];
7344
7345         u8         reserved_1[0x10];
7346         u8         op_mod[0x10];
7347
7348         u8         reserved_2[0x40];
7349 };
7350
7351 struct mlx5_ifc_alloc_q_counter_out_bits {
7352         u8         status[0x8];
7353         u8         reserved_0[0x18];
7354
7355         u8         syndrome[0x20];
7356
7357         u8         reserved_1[0x18];
7358         u8         counter_set_id[0x8];
7359
7360         u8         reserved_2[0x20];
7361 };
7362
7363 struct mlx5_ifc_alloc_q_counter_in_bits {
7364         u8         opcode[0x10];
7365         u8         reserved_0[0x10];
7366
7367         u8         reserved_1[0x10];
7368         u8         op_mod[0x10];
7369
7370         u8         reserved_2[0x40];
7371 };
7372
7373 struct mlx5_ifc_alloc_pd_out_bits {
7374         u8         status[0x8];
7375         u8         reserved_0[0x18];
7376
7377         u8         syndrome[0x20];
7378
7379         u8         reserved_1[0x8];
7380         u8         pd[0x18];
7381
7382         u8         reserved_2[0x20];
7383 };
7384
7385 struct mlx5_ifc_alloc_pd_in_bits {
7386         u8         opcode[0x10];
7387         u8         reserved_0[0x10];
7388
7389         u8         reserved_1[0x10];
7390         u8         op_mod[0x10];
7391
7392         u8         reserved_2[0x40];
7393 };
7394
7395 struct mlx5_ifc_alloc_flow_counter_out_bits {
7396         u8         status[0x8];
7397         u8         reserved_0[0x18];
7398
7399         u8         syndrome[0x20];
7400
7401         u8         reserved_1[0x10];
7402         u8         flow_counter_id[0x10];
7403
7404         u8         reserved_2[0x20];
7405 };
7406
7407 struct mlx5_ifc_alloc_flow_counter_in_bits {
7408         u8         opcode[0x10];
7409         u8         reserved_0[0x10];
7410
7411         u8         reserved_1[0x10];
7412         u8         op_mod[0x10];
7413
7414         u8         reserved_2[0x40];
7415 };
7416
7417 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7418         u8         status[0x8];
7419         u8         reserved_0[0x18];
7420
7421         u8         syndrome[0x20];
7422
7423         u8         reserved_1[0x40];
7424 };
7425
7426 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7427         u8         opcode[0x10];
7428         u8         reserved_0[0x10];
7429
7430         u8         reserved_1[0x10];
7431         u8         op_mod[0x10];
7432
7433         u8         reserved_2[0x20];
7434
7435         u8         reserved_3[0x10];
7436         u8         vxlan_udp_port[0x10];
7437 };
7438
7439 struct mlx5_ifc_activate_tracer_out_bits {
7440         u8         status[0x8];
7441         u8         reserved_0[0x18];
7442
7443         u8         syndrome[0x20];
7444
7445         u8         reserved_1[0x40];
7446 };
7447
7448 struct mlx5_ifc_activate_tracer_in_bits {
7449         u8         opcode[0x10];
7450         u8         reserved_0[0x10];
7451
7452         u8         reserved_1[0x10];
7453         u8         op_mod[0x10];
7454
7455         u8         mkey[0x20];
7456
7457         u8         reserved_2[0x20];
7458 };
7459
7460 struct mlx5_ifc_set_rate_limit_out_bits {
7461         u8         status[0x8];
7462         u8         reserved_at_8[0x18];
7463
7464         u8         syndrome[0x20];
7465
7466         u8         reserved_at_40[0x40];
7467 };
7468
7469 struct mlx5_ifc_set_rate_limit_in_bits {
7470         u8         opcode[0x10];
7471         u8         reserved_at_10[0x10];
7472
7473         u8         reserved_at_20[0x10];
7474         u8         op_mod[0x10];
7475
7476         u8         reserved_at_40[0x10];
7477         u8         rate_limit_index[0x10];
7478
7479         u8         reserved_at_60[0x20];
7480
7481         u8         rate_limit[0x20];
7482         u8         burst_upper_bound[0x20];
7483 };
7484
7485 struct mlx5_ifc_access_register_out_bits {
7486         u8         status[0x8];
7487         u8         reserved_0[0x18];
7488
7489         u8         syndrome[0x20];
7490
7491         u8         reserved_1[0x40];
7492
7493         u8         register_data[0][0x20];
7494 };
7495
7496 enum {
7497         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7498         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7499 };
7500
7501 struct mlx5_ifc_access_register_in_bits {
7502         u8         opcode[0x10];
7503         u8         reserved_0[0x10];
7504
7505         u8         reserved_1[0x10];
7506         u8         op_mod[0x10];
7507
7508         u8         reserved_2[0x10];
7509         u8         register_id[0x10];
7510
7511         u8         argument[0x20];
7512
7513         u8         register_data[0][0x20];
7514 };
7515
7516 struct mlx5_ifc_sltp_reg_bits {
7517         u8         status[0x4];
7518         u8         version[0x4];
7519         u8         local_port[0x8];
7520         u8         pnat[0x2];
7521         u8         reserved_0[0x2];
7522         u8         lane[0x4];
7523         u8         reserved_1[0x8];
7524
7525         u8         reserved_2[0x20];
7526
7527         u8         reserved_3[0x7];
7528         u8         polarity[0x1];
7529         u8         ob_tap0[0x8];
7530         u8         ob_tap1[0x8];
7531         u8         ob_tap2[0x8];
7532
7533         u8         reserved_4[0xc];
7534         u8         ob_preemp_mode[0x4];
7535         u8         ob_reg[0x8];
7536         u8         ob_bias[0x8];
7537
7538         u8         reserved_5[0x20];
7539 };
7540
7541 struct mlx5_ifc_slrp_reg_bits {
7542         u8         status[0x4];
7543         u8         version[0x4];
7544         u8         local_port[0x8];
7545         u8         pnat[0x2];
7546         u8         reserved_0[0x2];
7547         u8         lane[0x4];
7548         u8         reserved_1[0x8];
7549
7550         u8         ib_sel[0x2];
7551         u8         reserved_2[0x11];
7552         u8         dp_sel[0x1];
7553         u8         dp90sel[0x4];
7554         u8         mix90phase[0x8];
7555
7556         u8         ffe_tap0[0x8];
7557         u8         ffe_tap1[0x8];
7558         u8         ffe_tap2[0x8];
7559         u8         ffe_tap3[0x8];
7560
7561         u8         ffe_tap4[0x8];
7562         u8         ffe_tap5[0x8];
7563         u8         ffe_tap6[0x8];
7564         u8         ffe_tap7[0x8];
7565
7566         u8         ffe_tap8[0x8];
7567         u8         mixerbias_tap_amp[0x8];
7568         u8         reserved_3[0x7];
7569         u8         ffe_tap_en[0x9];
7570
7571         u8         ffe_tap_offset0[0x8];
7572         u8         ffe_tap_offset1[0x8];
7573         u8         slicer_offset0[0x10];
7574
7575         u8         mixer_offset0[0x10];
7576         u8         mixer_offset1[0x10];
7577
7578         u8         mixerbgn_inp[0x8];
7579         u8         mixerbgn_inn[0x8];
7580         u8         mixerbgn_refp[0x8];
7581         u8         mixerbgn_refn[0x8];
7582
7583         u8         sel_slicer_lctrl_h[0x1];
7584         u8         sel_slicer_lctrl_l[0x1];
7585         u8         reserved_4[0x1];
7586         u8         ref_mixer_vreg[0x5];
7587         u8         slicer_gctrl[0x8];
7588         u8         lctrl_input[0x8];
7589         u8         mixer_offset_cm1[0x8];
7590
7591         u8         common_mode[0x6];
7592         u8         reserved_5[0x1];
7593         u8         mixer_offset_cm0[0x9];
7594         u8         reserved_6[0x7];
7595         u8         slicer_offset_cm[0x9];
7596 };
7597
7598 struct mlx5_ifc_slrg_reg_bits {
7599         u8         status[0x4];
7600         u8         version[0x4];
7601         u8         local_port[0x8];
7602         u8         pnat[0x2];
7603         u8         reserved_0[0x2];
7604         u8         lane[0x4];
7605         u8         reserved_1[0x8];
7606
7607         u8         time_to_link_up[0x10];
7608         u8         reserved_2[0xc];
7609         u8         grade_lane_speed[0x4];
7610
7611         u8         grade_version[0x8];
7612         u8         grade[0x18];
7613
7614         u8         reserved_3[0x4];
7615         u8         height_grade_type[0x4];
7616         u8         height_grade[0x18];
7617
7618         u8         height_dz[0x10];
7619         u8         height_dv[0x10];
7620
7621         u8         reserved_4[0x10];
7622         u8         height_sigma[0x10];
7623
7624         u8         reserved_5[0x20];
7625
7626         u8         reserved_6[0x4];
7627         u8         phase_grade_type[0x4];
7628         u8         phase_grade[0x18];
7629
7630         u8         reserved_7[0x8];
7631         u8         phase_eo_pos[0x8];
7632         u8         reserved_8[0x8];
7633         u8         phase_eo_neg[0x8];
7634
7635         u8         ffe_set_tested[0x10];
7636         u8         test_errors_per_lane[0x10];
7637 };
7638
7639 struct mlx5_ifc_pvlc_reg_bits {
7640         u8         reserved_0[0x8];
7641         u8         local_port[0x8];
7642         u8         reserved_1[0x10];
7643
7644         u8         reserved_2[0x1c];
7645         u8         vl_hw_cap[0x4];
7646
7647         u8         reserved_3[0x1c];
7648         u8         vl_admin[0x4];
7649
7650         u8         reserved_4[0x1c];
7651         u8         vl_operational[0x4];
7652 };
7653
7654 struct mlx5_ifc_pude_reg_bits {
7655         u8         swid[0x8];
7656         u8         local_port[0x8];
7657         u8         reserved_0[0x4];
7658         u8         admin_status[0x4];
7659         u8         reserved_1[0x4];
7660         u8         oper_status[0x4];
7661
7662         u8         reserved_2[0x60];
7663 };
7664
7665 enum {
7666         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7667         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7668 };
7669
7670 struct mlx5_ifc_ptys_reg_bits {
7671         u8         reserved_0[0x1];
7672         u8         an_disable_admin[0x1];
7673         u8         an_disable_cap[0x1];
7674         u8         reserved_1[0x4];
7675         u8         force_tx_aba_param[0x1];
7676         u8         local_port[0x8];
7677         u8         reserved_2[0xd];
7678         u8         proto_mask[0x3];
7679
7680         u8         an_status[0x4];
7681         u8         reserved_3[0xc];
7682         u8         data_rate_oper[0x10];
7683
7684         u8         fc_proto_capability[0x20];
7685
7686         u8         eth_proto_capability[0x20];
7687
7688         u8         ib_link_width_capability[0x10];
7689         u8         ib_proto_capability[0x10];
7690
7691         u8         fc_proto_admin[0x20];
7692
7693         u8         eth_proto_admin[0x20];
7694
7695         u8         ib_link_width_admin[0x10];
7696         u8         ib_proto_admin[0x10];
7697
7698         u8         fc_proto_oper[0x20];
7699
7700         u8         eth_proto_oper[0x20];
7701
7702         u8         ib_link_width_oper[0x10];
7703         u8         ib_proto_oper[0x10];
7704
7705         u8         reserved_4[0x20];
7706
7707         u8         eth_proto_lp_advertise[0x20];
7708
7709         u8         reserved_5[0x60];
7710 };
7711
7712 struct mlx5_ifc_ptas_reg_bits {
7713         u8         reserved_0[0x20];
7714
7715         u8         algorithm_options[0x10];
7716         u8         reserved_1[0x4];
7717         u8         repetitions_mode[0x4];
7718         u8         num_of_repetitions[0x8];
7719
7720         u8         grade_version[0x8];
7721         u8         height_grade_type[0x4];
7722         u8         phase_grade_type[0x4];
7723         u8         height_grade_weight[0x8];
7724         u8         phase_grade_weight[0x8];
7725
7726         u8         gisim_measure_bits[0x10];
7727         u8         adaptive_tap_measure_bits[0x10];
7728
7729         u8         ber_bath_high_error_threshold[0x10];
7730         u8         ber_bath_mid_error_threshold[0x10];
7731
7732         u8         ber_bath_low_error_threshold[0x10];
7733         u8         one_ratio_high_threshold[0x10];
7734
7735         u8         one_ratio_high_mid_threshold[0x10];
7736         u8         one_ratio_low_mid_threshold[0x10];
7737
7738         u8         one_ratio_low_threshold[0x10];
7739         u8         ndeo_error_threshold[0x10];
7740
7741         u8         mixer_offset_step_size[0x10];
7742         u8         reserved_2[0x8];
7743         u8         mix90_phase_for_voltage_bath[0x8];
7744
7745         u8         mixer_offset_start[0x10];
7746         u8         mixer_offset_end[0x10];
7747
7748         u8         reserved_3[0x15];
7749         u8         ber_test_time[0xb];
7750 };
7751
7752 struct mlx5_ifc_pspa_reg_bits {
7753         u8         swid[0x8];
7754         u8         local_port[0x8];
7755         u8         sub_port[0x8];
7756         u8         reserved_0[0x8];
7757
7758         u8         reserved_1[0x20];
7759 };
7760
7761 struct mlx5_ifc_ppsc_reg_bits {
7762         u8         reserved_0[0x8];
7763         u8         local_port[0x8];
7764         u8         reserved_1[0x10];
7765
7766         u8         reserved_2[0x60];
7767
7768         u8         reserved_3[0x1c];
7769         u8         wrps_admin[0x4];
7770
7771         u8         reserved_4[0x1c];
7772         u8         wrps_status[0x4];
7773
7774         u8         up_th_vld[0x1];
7775         u8         down_th_vld[0x1];
7776         u8         reserved_5[0x6];
7777         u8         up_threshold[0x8];
7778         u8         reserved_6[0x8];
7779         u8         down_threshold[0x8];
7780
7781         u8         reserved_7[0x20];
7782
7783         u8         reserved_8[0x1c];
7784         u8         srps_admin[0x4];
7785
7786         u8         reserved_9[0x60];
7787 };
7788
7789 struct mlx5_ifc_pplr_reg_bits {
7790         u8         reserved_0[0x8];
7791         u8         local_port[0x8];
7792         u8         reserved_1[0x10];
7793
7794         u8         reserved_2[0x8];
7795         u8         lb_cap[0x8];
7796         u8         reserved_3[0x8];
7797         u8         lb_en[0x8];
7798 };
7799
7800 struct mlx5_ifc_pplm_reg_bits {
7801         u8         reserved_0[0x8];
7802         u8         local_port[0x8];
7803         u8         reserved_1[0x10];
7804
7805         u8         reserved_2[0x20];
7806
7807         u8         port_profile_mode[0x8];
7808         u8         static_port_profile[0x8];
7809         u8         active_port_profile[0x8];
7810         u8         reserved_3[0x8];
7811
7812         u8         retransmission_active[0x8];
7813         u8         fec_mode_active[0x18];
7814
7815         u8         reserved_4[0x10];
7816         u8         v_100g_fec_override_cap[0x4];
7817         u8         v_50g_fec_override_cap[0x4];
7818         u8         v_25g_fec_override_cap[0x4];
7819         u8         v_10g_40g_fec_override_cap[0x4];
7820
7821         u8         reserved_5[0x10];
7822         u8         v_100g_fec_override_admin[0x4];
7823         u8         v_50g_fec_override_admin[0x4];
7824         u8         v_25g_fec_override_admin[0x4];
7825         u8         v_10g_40g_fec_override_admin[0x4];
7826 };
7827
7828 struct mlx5_ifc_ppll_reg_bits {
7829         u8         num_pll_groups[0x8];
7830         u8         pll_group[0x8];
7831         u8         reserved_0[0x4];
7832         u8         num_plls[0x4];
7833         u8         reserved_1[0x8];
7834
7835         u8         reserved_2[0x1f];
7836         u8         ae[0x1];
7837
7838         u8         pll_status[4][0x40];
7839 };
7840
7841 struct mlx5_ifc_ppad_reg_bits {
7842         u8         reserved_0[0x3];
7843         u8         single_mac[0x1];
7844         u8         reserved_1[0x4];
7845         u8         local_port[0x8];
7846         u8         mac_47_32[0x10];
7847
7848         u8         mac_31_0[0x20];
7849
7850         u8         reserved_2[0x40];
7851 };
7852
7853 struct mlx5_ifc_pmtu_reg_bits {
7854         u8         reserved_0[0x8];
7855         u8         local_port[0x8];
7856         u8         reserved_1[0x10];
7857
7858         u8         max_mtu[0x10];
7859         u8         reserved_2[0x10];
7860
7861         u8         admin_mtu[0x10];
7862         u8         reserved_3[0x10];
7863
7864         u8         oper_mtu[0x10];
7865         u8         reserved_4[0x10];
7866 };
7867
7868 struct mlx5_ifc_pmpr_reg_bits {
7869         u8         reserved_0[0x8];
7870         u8         module[0x8];
7871         u8         reserved_1[0x10];
7872
7873         u8         reserved_2[0x18];
7874         u8         attenuation_5g[0x8];
7875
7876         u8         reserved_3[0x18];
7877         u8         attenuation_7g[0x8];
7878
7879         u8         reserved_4[0x18];
7880         u8         attenuation_12g[0x8];
7881 };
7882
7883 struct mlx5_ifc_pmpe_reg_bits {
7884         u8         reserved_0[0x8];
7885         u8         module[0x8];
7886         u8         reserved_1[0xc];
7887         u8         module_status[0x4];
7888
7889         u8         reserved_2[0x14];
7890         u8         error_type[0x4];
7891         u8         reserved_3[0x8];
7892
7893         u8         reserved_4[0x40];
7894 };
7895
7896 struct mlx5_ifc_pmpc_reg_bits {
7897         u8         module_state_updated[32][0x8];
7898 };
7899
7900 struct mlx5_ifc_pmlpn_reg_bits {
7901         u8         reserved_0[0x4];
7902         u8         mlpn_status[0x4];
7903         u8         local_port[0x8];
7904         u8         reserved_1[0x10];
7905
7906         u8         e[0x1];
7907         u8         reserved_2[0x1f];
7908 };
7909
7910 struct mlx5_ifc_pmlp_reg_bits {
7911         u8         rxtx[0x1];
7912         u8         reserved_0[0x7];
7913         u8         local_port[0x8];
7914         u8         reserved_1[0x8];
7915         u8         width[0x8];
7916
7917         u8         lane0_module_mapping[0x20];
7918
7919         u8         lane1_module_mapping[0x20];
7920
7921         u8         lane2_module_mapping[0x20];
7922
7923         u8         lane3_module_mapping[0x20];
7924
7925         u8         reserved_2[0x160];
7926 };
7927
7928 struct mlx5_ifc_pmaos_reg_bits {
7929         u8         reserved_0[0x8];
7930         u8         module[0x8];
7931         u8         reserved_1[0x4];
7932         u8         admin_status[0x4];
7933         u8         reserved_2[0x4];
7934         u8         oper_status[0x4];
7935
7936         u8         ase[0x1];
7937         u8         ee[0x1];
7938         u8         reserved_3[0x12];
7939         u8         error_type[0x4];
7940         u8         reserved_4[0x6];
7941         u8         e[0x2];
7942
7943         u8         reserved_5[0x40];
7944 };
7945
7946 struct mlx5_ifc_plpc_reg_bits {
7947         u8         reserved_0[0x4];
7948         u8         profile_id[0xc];
7949         u8         reserved_1[0x4];
7950         u8         proto_mask[0x4];
7951         u8         reserved_2[0x8];
7952
7953         u8         reserved_3[0x10];
7954         u8         lane_speed[0x10];
7955
7956         u8         reserved_4[0x17];
7957         u8         lpbf[0x1];
7958         u8         fec_mode_policy[0x8];
7959
7960         u8         retransmission_capability[0x8];
7961         u8         fec_mode_capability[0x18];
7962
7963         u8         retransmission_support_admin[0x8];
7964         u8         fec_mode_support_admin[0x18];
7965
7966         u8         retransmission_request_admin[0x8];
7967         u8         fec_mode_request_admin[0x18];
7968
7969         u8         reserved_5[0x80];
7970 };
7971
7972 struct mlx5_ifc_pll_status_data_bits {
7973         u8         reserved_0[0x1];
7974         u8         lock_cal[0x1];
7975         u8         lock_status[0x2];
7976         u8         reserved_1[0x2];
7977         u8         algo_f_ctrl[0xa];
7978         u8         analog_algo_num_var[0x6];
7979         u8         f_ctrl_measure[0xa];
7980
7981         u8         reserved_2[0x2];
7982         u8         analog_var[0x6];
7983         u8         reserved_3[0x2];
7984         u8         high_var[0x6];
7985         u8         reserved_4[0x2];
7986         u8         low_var[0x6];
7987         u8         reserved_5[0x2];
7988         u8         mid_val[0x6];
7989 };
7990
7991 struct mlx5_ifc_plib_reg_bits {
7992         u8         reserved_0[0x8];
7993         u8         local_port[0x8];
7994         u8         reserved_1[0x8];
7995         u8         ib_port[0x8];
7996
7997         u8         reserved_2[0x60];
7998 };
7999
8000 struct mlx5_ifc_plbf_reg_bits {
8001         u8         reserved_0[0x8];
8002         u8         local_port[0x8];
8003         u8         reserved_1[0xd];
8004         u8         lbf_mode[0x3];
8005
8006         u8         reserved_2[0x20];
8007 };
8008
8009 struct mlx5_ifc_pipg_reg_bits {
8010         u8         reserved_0[0x8];
8011         u8         local_port[0x8];
8012         u8         reserved_1[0x10];
8013
8014         u8         dic[0x1];
8015         u8         reserved_2[0x19];
8016         u8         ipg[0x4];
8017         u8         reserved_3[0x2];
8018 };
8019
8020 struct mlx5_ifc_pifr_reg_bits {
8021         u8         reserved_0[0x8];
8022         u8         local_port[0x8];
8023         u8         reserved_1[0x10];
8024
8025         u8         reserved_2[0xe0];
8026
8027         u8         port_filter[8][0x20];
8028
8029         u8         port_filter_update_en[8][0x20];
8030 };
8031
8032 struct mlx5_ifc_phys_layer_cntrs_bits {
8033         u8         time_since_last_clear_high[0x20];
8034
8035         u8         time_since_last_clear_low[0x20];
8036
8037         u8         symbol_errors_high[0x20];
8038
8039         u8         symbol_errors_low[0x20];
8040
8041         u8         sync_headers_errors_high[0x20];
8042
8043         u8         sync_headers_errors_low[0x20];
8044
8045         u8         edpl_bip_errors_lane0_high[0x20];
8046
8047         u8         edpl_bip_errors_lane0_low[0x20];
8048
8049         u8         edpl_bip_errors_lane1_high[0x20];
8050
8051         u8         edpl_bip_errors_lane1_low[0x20];
8052
8053         u8         edpl_bip_errors_lane2_high[0x20];
8054
8055         u8         edpl_bip_errors_lane2_low[0x20];
8056
8057         u8         edpl_bip_errors_lane3_high[0x20];
8058
8059         u8         edpl_bip_errors_lane3_low[0x20];
8060
8061         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8062
8063         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8064
8065         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8066
8067         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8068
8069         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8070
8071         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8072
8073         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8074
8075         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8076
8077         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8078
8079         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8080
8081         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8082
8083         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8084
8085         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8086
8087         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8088
8089         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8090
8091         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8092
8093         u8         rs_fec_corrected_blocks_high[0x20];
8094
8095         u8         rs_fec_corrected_blocks_low[0x20];
8096
8097         u8         rs_fec_uncorrectable_blocks_high[0x20];
8098
8099         u8         rs_fec_uncorrectable_blocks_low[0x20];
8100
8101         u8         rs_fec_no_errors_blocks_high[0x20];
8102
8103         u8         rs_fec_no_errors_blocks_low[0x20];
8104
8105         u8         rs_fec_single_error_blocks_high[0x20];
8106
8107         u8         rs_fec_single_error_blocks_low[0x20];
8108
8109         u8         rs_fec_corrected_symbols_total_high[0x20];
8110
8111         u8         rs_fec_corrected_symbols_total_low[0x20];
8112
8113         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8114
8115         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8116
8117         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8118
8119         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8120
8121         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8122
8123         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8124
8125         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8126
8127         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8128
8129         u8         link_down_events[0x20];
8130
8131         u8         successful_recovery_events[0x20];
8132
8133         u8         reserved_0[0x180];
8134 };
8135
8136 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8137         u8         time_since_last_clear_high[0x20];
8138
8139         u8         time_since_last_clear_low[0x20];
8140
8141         u8         phy_received_bits_high[0x20];
8142
8143         u8         phy_received_bits_low[0x20];
8144
8145         u8         phy_symbol_errors_high[0x20];
8146
8147         u8         phy_symbol_errors_low[0x20];
8148
8149         u8         phy_corrected_bits_high[0x20];
8150
8151         u8         phy_corrected_bits_low[0x20];
8152
8153         u8         phy_corrected_bits_lane0_high[0x20];
8154
8155         u8         phy_corrected_bits_lane0_low[0x20];
8156
8157         u8         phy_corrected_bits_lane1_high[0x20];
8158
8159         u8         phy_corrected_bits_lane1_low[0x20];
8160
8161         u8         phy_corrected_bits_lane2_high[0x20];
8162
8163         u8         phy_corrected_bits_lane2_low[0x20];
8164
8165         u8         phy_corrected_bits_lane3_high[0x20];
8166
8167         u8         phy_corrected_bits_lane3_low[0x20];
8168
8169         u8         reserved_at_200[0x5c0];
8170 };
8171
8172 struct mlx5_ifc_infiniband_port_cntrs_bits {
8173         u8         symbol_error_counter[0x10];
8174         u8         link_error_recovery_counter[0x8];
8175         u8         link_downed_counter[0x8];
8176
8177         u8         port_rcv_errors[0x10];
8178         u8         port_rcv_remote_physical_errors[0x10];
8179
8180         u8         port_rcv_switch_relay_errors[0x10];
8181         u8         port_xmit_discards[0x10];
8182
8183         u8         port_xmit_constraint_errors[0x8];
8184         u8         port_rcv_constraint_errors[0x8];
8185         u8         reserved_0[0x8];
8186         u8         local_link_integrity_errors[0x4];
8187         u8         excessive_buffer_overrun_errors[0x4];
8188
8189         u8         reserved_1[0x10];
8190         u8         vl_15_dropped[0x10];
8191
8192         u8         port_xmit_data[0x20];
8193
8194         u8         port_rcv_data[0x20];
8195
8196         u8         port_xmit_pkts[0x20];
8197
8198         u8         port_rcv_pkts[0x20];
8199
8200         u8         port_xmit_wait[0x20];
8201
8202         u8         reserved_2[0x680];
8203 };
8204
8205 struct mlx5_ifc_phrr_reg_bits {
8206         u8         clr[0x1];
8207         u8         reserved_0[0x7];
8208         u8         local_port[0x8];
8209         u8         reserved_1[0x10];
8210
8211         u8         hist_group[0x8];
8212         u8         reserved_2[0x10];
8213         u8         hist_id[0x8];
8214
8215         u8         reserved_3[0x40];
8216
8217         u8         time_since_last_clear_high[0x20];
8218
8219         u8         time_since_last_clear_low[0x20];
8220
8221         u8         bin[10][0x20];
8222 };
8223
8224 struct mlx5_ifc_phbr_for_prio_reg_bits {
8225         u8         reserved_0[0x18];
8226         u8         prio[0x8];
8227 };
8228
8229 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8230         u8         reserved_0[0x18];
8231         u8         tclass[0x8];
8232 };
8233
8234 struct mlx5_ifc_phbr_binding_reg_bits {
8235         u8         opcode[0x4];
8236         u8         reserved_0[0x4];
8237         u8         local_port[0x8];
8238         u8         pnat[0x2];
8239         u8         reserved_1[0xe];
8240
8241         u8         hist_group[0x8];
8242         u8         reserved_2[0x10];
8243         u8         hist_id[0x8];
8244
8245         u8         reserved_3[0x10];
8246         u8         hist_type[0x10];
8247
8248         u8         hist_parameters[0x20];
8249
8250         u8         hist_min_value[0x20];
8251
8252         u8         hist_max_value[0x20];
8253
8254         u8         sample_time[0x20];
8255 };
8256
8257 enum {
8258         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8259         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8260 };
8261
8262 struct mlx5_ifc_pfcc_reg_bits {
8263         u8         dcbx_operation_type[0x2];
8264         u8         cap_local_admin[0x1];
8265         u8         cap_remote_admin[0x1];
8266         u8         reserved_0[0x4];
8267         u8         local_port[0x8];
8268         u8         pnat[0x2];
8269         u8         reserved_1[0xc];
8270         u8         shl_cap[0x1];
8271         u8         shl_opr[0x1];
8272
8273         u8         ppan[0x4];
8274         u8         reserved_2[0x4];
8275         u8         prio_mask_tx[0x8];
8276         u8         reserved_3[0x8];
8277         u8         prio_mask_rx[0x8];
8278
8279         u8         pptx[0x1];
8280         u8         aptx[0x1];
8281         u8         reserved_4[0x6];
8282         u8         pfctx[0x8];
8283         u8         reserved_5[0x8];
8284         u8         cbftx[0x8];
8285
8286         u8         pprx[0x1];
8287         u8         aprx[0x1];
8288         u8         reserved_6[0x6];
8289         u8         pfcrx[0x8];
8290         u8         reserved_7[0x8];
8291         u8         cbfrx[0x8];
8292
8293         u8         device_stall_minor_watermark[0x10];
8294         u8         device_stall_critical_watermark[0x10];
8295
8296         u8         reserved_8[0x60];
8297 };
8298
8299 struct mlx5_ifc_pelc_reg_bits {
8300         u8         op[0x4];
8301         u8         reserved_0[0x4];
8302         u8         local_port[0x8];
8303         u8         reserved_1[0x10];
8304
8305         u8         op_admin[0x8];
8306         u8         op_capability[0x8];
8307         u8         op_request[0x8];
8308         u8         op_active[0x8];
8309
8310         u8         admin[0x40];
8311
8312         u8         capability[0x40];
8313
8314         u8         request[0x40];
8315
8316         u8         active[0x40];
8317
8318         u8         reserved_2[0x80];
8319 };
8320
8321 struct mlx5_ifc_peir_reg_bits {
8322         u8         reserved_0[0x8];
8323         u8         local_port[0x8];
8324         u8         reserved_1[0x10];
8325
8326         u8         reserved_2[0xc];
8327         u8         error_count[0x4];
8328         u8         reserved_3[0x10];
8329
8330         u8         reserved_4[0xc];
8331         u8         lane[0x4];
8332         u8         reserved_5[0x8];
8333         u8         error_type[0x8];
8334 };
8335
8336 struct mlx5_ifc_pcap_reg_bits {
8337         u8         reserved_0[0x8];
8338         u8         local_port[0x8];
8339         u8         reserved_1[0x10];
8340
8341         u8         port_capability_mask[4][0x20];
8342 };
8343
8344 struct mlx5_ifc_pbmc_reg_bits {
8345         u8         reserved_0[0x8];
8346         u8         local_port[0x8];
8347         u8         reserved_1[0x10];
8348
8349         u8         xoff_timer_value[0x10];
8350         u8         xoff_refresh[0x10];
8351
8352         u8         reserved_2[0x10];
8353         u8         port_buffer_size[0x10];
8354
8355         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8356
8357         u8         reserved_3[0x40];
8358
8359         u8         port_shared_buffer[0x40];
8360 };
8361
8362 struct mlx5_ifc_paos_reg_bits {
8363         u8         swid[0x8];
8364         u8         local_port[0x8];
8365         u8         reserved_0[0x4];
8366         u8         admin_status[0x4];
8367         u8         reserved_1[0x4];
8368         u8         oper_status[0x4];
8369
8370         u8         ase[0x1];
8371         u8         ee[0x1];
8372         u8         reserved_2[0x1c];
8373         u8         e[0x2];
8374
8375         u8         reserved_3[0x40];
8376 };
8377
8378 struct mlx5_ifc_pamp_reg_bits {
8379         u8         reserved_0[0x8];
8380         u8         opamp_group[0x8];
8381         u8         reserved_1[0xc];
8382         u8         opamp_group_type[0x4];
8383
8384         u8         start_index[0x10];
8385         u8         reserved_2[0x4];
8386         u8         num_of_indices[0xc];
8387
8388         u8         index_data[18][0x10];
8389 };
8390
8391 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8392         u8         llr_rx_cells_high[0x20];
8393
8394         u8         llr_rx_cells_low[0x20];
8395
8396         u8         llr_rx_error_high[0x20];
8397
8398         u8         llr_rx_error_low[0x20];
8399
8400         u8         llr_rx_crc_error_high[0x20];
8401
8402         u8         llr_rx_crc_error_low[0x20];
8403
8404         u8         llr_tx_cells_high[0x20];
8405
8406         u8         llr_tx_cells_low[0x20];
8407
8408         u8         llr_tx_ret_cells_high[0x20];
8409
8410         u8         llr_tx_ret_cells_low[0x20];
8411
8412         u8         llr_tx_ret_events_high[0x20];
8413
8414         u8         llr_tx_ret_events_low[0x20];
8415
8416         u8         reserved_0[0x640];
8417 };
8418
8419 struct mlx5_ifc_lane_2_module_mapping_bits {
8420         u8         reserved_0[0x6];
8421         u8         rx_lane[0x2];
8422         u8         reserved_1[0x6];
8423         u8         tx_lane[0x2];
8424         u8         reserved_2[0x8];
8425         u8         module[0x8];
8426 };
8427
8428 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8429         u8         transmit_queue_high[0x20];
8430
8431         u8         transmit_queue_low[0x20];
8432
8433         u8         reserved_0[0x780];
8434 };
8435
8436 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8437         u8         no_buffer_discard_uc_high[0x20];
8438
8439         u8         no_buffer_discard_uc_low[0x20];
8440
8441         u8         wred_discard_high[0x20];
8442
8443         u8         wred_discard_low[0x20];
8444
8445         u8         reserved_0[0x740];
8446 };
8447
8448 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8449         u8         rx_octets_high[0x20];
8450
8451         u8         rx_octets_low[0x20];
8452
8453         u8         reserved_0[0xc0];
8454
8455         u8         rx_frames_high[0x20];
8456
8457         u8         rx_frames_low[0x20];
8458
8459         u8         tx_octets_high[0x20];
8460
8461         u8         tx_octets_low[0x20];
8462
8463         u8         reserved_1[0xc0];
8464
8465         u8         tx_frames_high[0x20];
8466
8467         u8         tx_frames_low[0x20];
8468
8469         u8         rx_pause_high[0x20];
8470
8471         u8         rx_pause_low[0x20];
8472
8473         u8         rx_pause_duration_high[0x20];
8474
8475         u8         rx_pause_duration_low[0x20];
8476
8477         u8         tx_pause_high[0x20];
8478
8479         u8         tx_pause_low[0x20];
8480
8481         u8         tx_pause_duration_high[0x20];
8482
8483         u8         tx_pause_duration_low[0x20];
8484
8485         u8         rx_pause_transition_high[0x20];
8486
8487         u8         rx_pause_transition_low[0x20];
8488
8489         u8         rx_discards_high[0x20];
8490
8491         u8         rx_discards_low[0x20];
8492
8493         u8         device_stall_minor_watermark_cnt_high[0x20];
8494
8495         u8         device_stall_minor_watermark_cnt_low[0x20];
8496
8497         u8         device_stall_critical_watermark_cnt_high[0x20];
8498
8499         u8         device_stall_critical_watermark_cnt_low[0x20];
8500
8501         u8         reserved_2[0x340];
8502 };
8503
8504 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8505         u8         port_transmit_wait_high[0x20];
8506
8507         u8         port_transmit_wait_low[0x20];
8508
8509         u8         ecn_marked_high[0x20];
8510
8511         u8         ecn_marked_low[0x20];
8512
8513         u8         no_buffer_discard_mc_high[0x20];
8514
8515         u8         no_buffer_discard_mc_low[0x20];
8516
8517         u8         reserved_0[0x700];
8518 };
8519
8520 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8521         u8         a_frames_transmitted_ok_high[0x20];
8522
8523         u8         a_frames_transmitted_ok_low[0x20];
8524
8525         u8         a_frames_received_ok_high[0x20];
8526
8527         u8         a_frames_received_ok_low[0x20];
8528
8529         u8         a_frame_check_sequence_errors_high[0x20];
8530
8531         u8         a_frame_check_sequence_errors_low[0x20];
8532
8533         u8         a_alignment_errors_high[0x20];
8534
8535         u8         a_alignment_errors_low[0x20];
8536
8537         u8         a_octets_transmitted_ok_high[0x20];
8538
8539         u8         a_octets_transmitted_ok_low[0x20];
8540
8541         u8         a_octets_received_ok_high[0x20];
8542
8543         u8         a_octets_received_ok_low[0x20];
8544
8545         u8         a_multicast_frames_xmitted_ok_high[0x20];
8546
8547         u8         a_multicast_frames_xmitted_ok_low[0x20];
8548
8549         u8         a_broadcast_frames_xmitted_ok_high[0x20];
8550
8551         u8         a_broadcast_frames_xmitted_ok_low[0x20];
8552
8553         u8         a_multicast_frames_received_ok_high[0x20];
8554
8555         u8         a_multicast_frames_received_ok_low[0x20];
8556
8557         u8         a_broadcast_frames_recieved_ok_high[0x20];
8558
8559         u8         a_broadcast_frames_recieved_ok_low[0x20];
8560
8561         u8         a_in_range_length_errors_high[0x20];
8562
8563         u8         a_in_range_length_errors_low[0x20];
8564
8565         u8         a_out_of_range_length_field_high[0x20];
8566
8567         u8         a_out_of_range_length_field_low[0x20];
8568
8569         u8         a_frame_too_long_errors_high[0x20];
8570
8571         u8         a_frame_too_long_errors_low[0x20];
8572
8573         u8         a_symbol_error_during_carrier_high[0x20];
8574
8575         u8         a_symbol_error_during_carrier_low[0x20];
8576
8577         u8         a_mac_control_frames_transmitted_high[0x20];
8578
8579         u8         a_mac_control_frames_transmitted_low[0x20];
8580
8581         u8         a_mac_control_frames_received_high[0x20];
8582
8583         u8         a_mac_control_frames_received_low[0x20];
8584
8585         u8         a_unsupported_opcodes_received_high[0x20];
8586
8587         u8         a_unsupported_opcodes_received_low[0x20];
8588
8589         u8         a_pause_mac_ctrl_frames_received_high[0x20];
8590
8591         u8         a_pause_mac_ctrl_frames_received_low[0x20];
8592
8593         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8594
8595         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8596
8597         u8         reserved_0[0x300];
8598 };
8599
8600 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8601         u8         dot3stats_alignment_errors_high[0x20];
8602
8603         u8         dot3stats_alignment_errors_low[0x20];
8604
8605         u8         dot3stats_fcs_errors_high[0x20];
8606
8607         u8         dot3stats_fcs_errors_low[0x20];
8608
8609         u8         dot3stats_single_collision_frames_high[0x20];
8610
8611         u8         dot3stats_single_collision_frames_low[0x20];
8612
8613         u8         dot3stats_multiple_collision_frames_high[0x20];
8614
8615         u8         dot3stats_multiple_collision_frames_low[0x20];
8616
8617         u8         dot3stats_sqe_test_errors_high[0x20];
8618
8619         u8         dot3stats_sqe_test_errors_low[0x20];
8620
8621         u8         dot3stats_deferred_transmissions_high[0x20];
8622
8623         u8         dot3stats_deferred_transmissions_low[0x20];
8624
8625         u8         dot3stats_late_collisions_high[0x20];
8626
8627         u8         dot3stats_late_collisions_low[0x20];
8628
8629         u8         dot3stats_excessive_collisions_high[0x20];
8630
8631         u8         dot3stats_excessive_collisions_low[0x20];
8632
8633         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8634
8635         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8636
8637         u8         dot3stats_carrier_sense_errors_high[0x20];
8638
8639         u8         dot3stats_carrier_sense_errors_low[0x20];
8640
8641         u8         dot3stats_frame_too_longs_high[0x20];
8642
8643         u8         dot3stats_frame_too_longs_low[0x20];
8644
8645         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8646
8647         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8648
8649         u8         dot3stats_symbol_errors_high[0x20];
8650
8651         u8         dot3stats_symbol_errors_low[0x20];
8652
8653         u8         dot3control_in_unknown_opcodes_high[0x20];
8654
8655         u8         dot3control_in_unknown_opcodes_low[0x20];
8656
8657         u8         dot3in_pause_frames_high[0x20];
8658
8659         u8         dot3in_pause_frames_low[0x20];
8660
8661         u8         dot3out_pause_frames_high[0x20];
8662
8663         u8         dot3out_pause_frames_low[0x20];
8664
8665         u8         reserved_0[0x3c0];
8666 };
8667
8668 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8669         u8         if_in_octets_high[0x20];
8670
8671         u8         if_in_octets_low[0x20];
8672
8673         u8         if_in_ucast_pkts_high[0x20];
8674
8675         u8         if_in_ucast_pkts_low[0x20];
8676
8677         u8         if_in_discards_high[0x20];
8678
8679         u8         if_in_discards_low[0x20];
8680
8681         u8         if_in_errors_high[0x20];
8682
8683         u8         if_in_errors_low[0x20];
8684
8685         u8         if_in_unknown_protos_high[0x20];
8686
8687         u8         if_in_unknown_protos_low[0x20];
8688
8689         u8         if_out_octets_high[0x20];
8690
8691         u8         if_out_octets_low[0x20];
8692
8693         u8         if_out_ucast_pkts_high[0x20];
8694
8695         u8         if_out_ucast_pkts_low[0x20];
8696
8697         u8         if_out_discards_high[0x20];
8698
8699         u8         if_out_discards_low[0x20];
8700
8701         u8         if_out_errors_high[0x20];
8702
8703         u8         if_out_errors_low[0x20];
8704
8705         u8         if_in_multicast_pkts_high[0x20];
8706
8707         u8         if_in_multicast_pkts_low[0x20];
8708
8709         u8         if_in_broadcast_pkts_high[0x20];
8710
8711         u8         if_in_broadcast_pkts_low[0x20];
8712
8713         u8         if_out_multicast_pkts_high[0x20];
8714
8715         u8         if_out_multicast_pkts_low[0x20];
8716
8717         u8         if_out_broadcast_pkts_high[0x20];
8718
8719         u8         if_out_broadcast_pkts_low[0x20];
8720
8721         u8         reserved_0[0x480];
8722 };
8723
8724 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8725         u8         ether_stats_drop_events_high[0x20];
8726
8727         u8         ether_stats_drop_events_low[0x20];
8728
8729         u8         ether_stats_octets_high[0x20];
8730
8731         u8         ether_stats_octets_low[0x20];
8732
8733         u8         ether_stats_pkts_high[0x20];
8734
8735         u8         ether_stats_pkts_low[0x20];
8736
8737         u8         ether_stats_broadcast_pkts_high[0x20];
8738
8739         u8         ether_stats_broadcast_pkts_low[0x20];
8740
8741         u8         ether_stats_multicast_pkts_high[0x20];
8742
8743         u8         ether_stats_multicast_pkts_low[0x20];
8744
8745         u8         ether_stats_crc_align_errors_high[0x20];
8746
8747         u8         ether_stats_crc_align_errors_low[0x20];
8748
8749         u8         ether_stats_undersize_pkts_high[0x20];
8750
8751         u8         ether_stats_undersize_pkts_low[0x20];
8752
8753         u8         ether_stats_oversize_pkts_high[0x20];
8754
8755         u8         ether_stats_oversize_pkts_low[0x20];
8756
8757         u8         ether_stats_fragments_high[0x20];
8758
8759         u8         ether_stats_fragments_low[0x20];
8760
8761         u8         ether_stats_jabbers_high[0x20];
8762
8763         u8         ether_stats_jabbers_low[0x20];
8764
8765         u8         ether_stats_collisions_high[0x20];
8766
8767         u8         ether_stats_collisions_low[0x20];
8768
8769         u8         ether_stats_pkts64octets_high[0x20];
8770
8771         u8         ether_stats_pkts64octets_low[0x20];
8772
8773         u8         ether_stats_pkts65to127octets_high[0x20];
8774
8775         u8         ether_stats_pkts65to127octets_low[0x20];
8776
8777         u8         ether_stats_pkts128to255octets_high[0x20];
8778
8779         u8         ether_stats_pkts128to255octets_low[0x20];
8780
8781         u8         ether_stats_pkts256to511octets_high[0x20];
8782
8783         u8         ether_stats_pkts256to511octets_low[0x20];
8784
8785         u8         ether_stats_pkts512to1023octets_high[0x20];
8786
8787         u8         ether_stats_pkts512to1023octets_low[0x20];
8788
8789         u8         ether_stats_pkts1024to1518octets_high[0x20];
8790
8791         u8         ether_stats_pkts1024to1518octets_low[0x20];
8792
8793         u8         ether_stats_pkts1519to2047octets_high[0x20];
8794
8795         u8         ether_stats_pkts1519to2047octets_low[0x20];
8796
8797         u8         ether_stats_pkts2048to4095octets_high[0x20];
8798
8799         u8         ether_stats_pkts2048to4095octets_low[0x20];
8800
8801         u8         ether_stats_pkts4096to8191octets_high[0x20];
8802
8803         u8         ether_stats_pkts4096to8191octets_low[0x20];
8804
8805         u8         ether_stats_pkts8192to10239octets_high[0x20];
8806
8807         u8         ether_stats_pkts8192to10239octets_low[0x20];
8808
8809         u8         reserved_0[0x280];
8810 };
8811
8812 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8813         u8         symbol_error_counter[0x10];
8814         u8         link_error_recovery_counter[0x8];
8815         u8         link_downed_counter[0x8];
8816
8817         u8         port_rcv_errors[0x10];
8818         u8         port_rcv_remote_physical_errors[0x10];
8819
8820         u8         port_rcv_switch_relay_errors[0x10];
8821         u8         port_xmit_discards[0x10];
8822
8823         u8         port_xmit_constraint_errors[0x8];
8824         u8         port_rcv_constraint_errors[0x8];
8825         u8         reserved_0[0x8];
8826         u8         local_link_integrity_errors[0x4];
8827         u8         excessive_buffer_overrun_errors[0x4];
8828
8829         u8         reserved_1[0x10];
8830         u8         vl_15_dropped[0x10];
8831
8832         u8         port_xmit_data[0x20];
8833
8834         u8         port_rcv_data[0x20];
8835
8836         u8         port_xmit_pkts[0x20];
8837
8838         u8         port_rcv_pkts[0x20];
8839
8840         u8         port_xmit_wait[0x20];
8841
8842         u8         reserved_2[0x680];
8843 };
8844
8845 struct mlx5_ifc_trc_tlb_reg_bits {
8846         u8         reserved_0[0x80];
8847
8848         u8         tlb_addr[0][0x40];
8849 };
8850
8851 struct mlx5_ifc_trc_read_fifo_reg_bits {
8852         u8         reserved_0[0x10];
8853         u8         requested_event_num[0x10];
8854
8855         u8         reserved_1[0x20];
8856
8857         u8         reserved_2[0x10];
8858         u8         acual_event_num[0x10];
8859
8860         u8         reserved_3[0x20];
8861
8862         u8         event[0][0x40];
8863 };
8864
8865 struct mlx5_ifc_trc_lock_reg_bits {
8866         u8         reserved_0[0x1f];
8867         u8         lock[0x1];
8868
8869         u8         reserved_1[0x60];
8870 };
8871
8872 struct mlx5_ifc_trc_filter_reg_bits {
8873         u8         status[0x1];
8874         u8         reserved_0[0xf];
8875         u8         filter_index[0x10];
8876
8877         u8         reserved_1[0x20];
8878
8879         u8         filter_val[0x20];
8880
8881         u8         reserved_2[0x1a0];
8882 };
8883
8884 struct mlx5_ifc_trc_event_reg_bits {
8885         u8         status[0x1];
8886         u8         reserved_0[0xf];
8887         u8         event_index[0x10];
8888
8889         u8         reserved_1[0x20];
8890
8891         u8         event_id[0x20];
8892
8893         u8         event_selector_val[0x10];
8894         u8         event_selector_size[0x10];
8895
8896         u8         reserved_2[0x180];
8897 };
8898
8899 struct mlx5_ifc_trc_conf_reg_bits {
8900         u8         limit_en[0x1];
8901         u8         reserved_0[0x3];
8902         u8         dump_mode[0x4];
8903         u8         reserved_1[0x15];
8904         u8         state[0x3];
8905
8906         u8         reserved_2[0x20];
8907
8908         u8         limit_event_index[0x20];
8909
8910         u8         mkey[0x20];
8911
8912         u8         fifo_ready_ev_num[0x20];
8913
8914         u8         reserved_3[0x160];
8915 };
8916
8917 struct mlx5_ifc_trc_cap_reg_bits {
8918         u8         reserved_0[0x18];
8919         u8         dump_mode[0x8];
8920
8921         u8         reserved_1[0x20];
8922
8923         u8         num_of_events[0x10];
8924         u8         num_of_filters[0x10];
8925
8926         u8         fifo_size[0x20];
8927
8928         u8         tlb_size[0x10];
8929         u8         event_size[0x10];
8930
8931         u8         reserved_2[0x160];
8932 };
8933
8934 struct mlx5_ifc_set_node_in_bits {
8935         u8         node_description[64][0x8];
8936 };
8937
8938 struct mlx5_ifc_register_power_settings_bits {
8939         u8         reserved_0[0x18];
8940         u8         power_settings_level[0x8];
8941
8942         u8         reserved_1[0x60];
8943 };
8944
8945 struct mlx5_ifc_register_host_endianess_bits {
8946         u8         he[0x1];
8947         u8         reserved_0[0x1f];
8948
8949         u8         reserved_1[0x60];
8950 };
8951
8952 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
8953         u8         physical_address[0x40];
8954 };
8955
8956 struct mlx5_ifc_qtct_reg_bits {
8957         u8         operation_type[0x2];
8958         u8         cap_local_admin[0x1];
8959         u8         cap_remote_admin[0x1];
8960         u8         reserved_0[0x4];
8961         u8         port_number[0x8];
8962         u8         reserved_1[0xd];
8963         u8         prio[0x3];
8964
8965         u8         reserved_2[0x1d];
8966         u8         tclass[0x3];
8967 };
8968
8969 struct mlx5_ifc_qpdp_reg_bits {
8970         u8         reserved_0[0x8];
8971         u8         port_number[0x8];
8972         u8         reserved_1[0x10];
8973
8974         u8         reserved_2[0x1d];
8975         u8         pprio[0x3];
8976 };
8977
8978 struct mlx5_ifc_port_info_ro_fields_param_bits {
8979         u8         reserved_0[0x8];
8980         u8         port[0x8];
8981         u8         max_gid[0x10];
8982
8983         u8         reserved_1[0x20];
8984
8985         u8         port_guid[0x40];
8986 };
8987
8988 struct mlx5_ifc_nvqc_reg_bits {
8989         u8         type[0x20];
8990
8991         u8         reserved_0[0x18];
8992         u8         version[0x4];
8993         u8         reserved_1[0x2];
8994         u8         support_wr[0x1];
8995         u8         support_rd[0x1];
8996 };
8997
8998 struct mlx5_ifc_nvia_reg_bits {
8999         u8         reserved_0[0x1d];
9000         u8         target[0x3];
9001
9002         u8         reserved_1[0x20];
9003 };
9004
9005 struct mlx5_ifc_nvdi_reg_bits {
9006         struct mlx5_ifc_config_item_bits configuration_item_header;
9007 };
9008
9009 struct mlx5_ifc_nvda_reg_bits {
9010         struct mlx5_ifc_config_item_bits configuration_item_header;
9011
9012         u8         configuration_item_data[0x20];
9013 };
9014
9015 struct mlx5_ifc_node_info_ro_fields_param_bits {
9016         u8         system_image_guid[0x40];
9017
9018         u8         reserved_0[0x40];
9019
9020         u8         node_guid[0x40];
9021
9022         u8         reserved_1[0x10];
9023         u8         max_pkey[0x10];
9024
9025         u8         reserved_2[0x20];
9026 };
9027
9028 struct mlx5_ifc_ets_tcn_config_reg_bits {
9029         u8         g[0x1];
9030         u8         b[0x1];
9031         u8         r[0x1];
9032         u8         reserved_0[0x9];
9033         u8         group[0x4];
9034         u8         reserved_1[0x9];
9035         u8         bw_allocation[0x7];
9036
9037         u8         reserved_2[0xc];
9038         u8         max_bw_units[0x4];
9039         u8         reserved_3[0x8];
9040         u8         max_bw_value[0x8];
9041 };
9042
9043 struct mlx5_ifc_ets_global_config_reg_bits {
9044         u8         reserved_0[0x2];
9045         u8         r[0x1];
9046         u8         reserved_1[0x1d];
9047
9048         u8         reserved_2[0xc];
9049         u8         max_bw_units[0x4];
9050         u8         reserved_3[0x8];
9051         u8         max_bw_value[0x8];
9052 };
9053
9054 struct mlx5_ifc_nodnic_mac_filters_bits {
9055         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9056
9057         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9058
9059         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9060
9061         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9062
9063         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9064
9065         u8         reserved_0[0xc0];
9066 };
9067
9068 struct mlx5_ifc_nodnic_gid_filters_bits {
9069         u8         mgid_filter0[16][0x8];
9070
9071         u8         mgid_filter1[16][0x8];
9072
9073         u8         mgid_filter2[16][0x8];
9074
9075         u8         mgid_filter3[16][0x8];
9076 };
9077
9078 enum {
9079         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9080         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9081 };
9082
9083 enum {
9084         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9085         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9086 };
9087
9088 struct mlx5_ifc_nodnic_config_reg_bits {
9089         u8         no_dram_nic_revision[0x8];
9090         u8         hardware_format[0x8];
9091         u8         support_receive_filter[0x1];
9092         u8         support_promisc_filter[0x1];
9093         u8         support_promisc_multicast_filter[0x1];
9094         u8         reserved_0[0x2];
9095         u8         log_working_buffer_size[0x3];
9096         u8         log_pkey_table_size[0x4];
9097         u8         reserved_1[0x3];
9098         u8         num_ports[0x1];
9099
9100         u8         reserved_2[0x2];
9101         u8         log_max_ring_size[0x6];
9102         u8         reserved_3[0x18];
9103
9104         u8         lkey[0x20];
9105
9106         u8         cqe_format[0x4];
9107         u8         reserved_4[0x1c];
9108
9109         u8         node_guid[0x40];
9110
9111         u8         reserved_5[0x740];
9112
9113         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9114
9115         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9116 };
9117
9118 struct mlx5_ifc_vlan_layout_bits {
9119         u8         reserved_0[0x14];
9120         u8         vlan[0xc];
9121
9122         u8         reserved_1[0x20];
9123 };
9124
9125 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9126         u8         reserved_0[0x20];
9127
9128         u8         mkey[0x20];
9129
9130         u8         addressh_63_32[0x20];
9131
9132         u8         addressl_31_0[0x20];
9133 };
9134
9135 struct mlx5_ifc_ud_adrs_vector_bits {
9136         u8         dc_key[0x40];
9137
9138         u8         ext[0x1];
9139         u8         reserved_0[0x7];
9140         u8         destination_qp_dct[0x18];
9141
9142         u8         static_rate[0x4];
9143         u8         sl_eth_prio[0x4];
9144         u8         fl[0x1];
9145         u8         mlid[0x7];
9146         u8         rlid_udp_sport[0x10];
9147
9148         u8         reserved_1[0x20];
9149
9150         u8         rmac_47_16[0x20];
9151
9152         u8         rmac_15_0[0x10];
9153         u8         tclass[0x8];
9154         u8         hop_limit[0x8];
9155
9156         u8         reserved_2[0x1];
9157         u8         grh[0x1];
9158         u8         reserved_3[0x2];
9159         u8         src_addr_index[0x8];
9160         u8         flow_label[0x14];
9161
9162         u8         rgid_rip[16][0x8];
9163 };
9164
9165 struct mlx5_ifc_port_module_event_bits {
9166         u8         reserved_0[0x8];
9167         u8         module[0x8];
9168         u8         reserved_1[0xc];
9169         u8         module_status[0x4];
9170
9171         u8         reserved_2[0x14];
9172         u8         error_type[0x4];
9173         u8         reserved_3[0x8];
9174
9175         u8         reserved_4[0xa0];
9176 };
9177
9178 struct mlx5_ifc_icmd_control_bits {
9179         u8         opcode[0x10];
9180         u8         status[0x8];
9181         u8         reserved_0[0x7];
9182         u8         busy[0x1];
9183 };
9184
9185 struct mlx5_ifc_eqe_bits {
9186         u8         reserved_0[0x8];
9187         u8         event_type[0x8];
9188         u8         reserved_1[0x8];
9189         u8         event_sub_type[0x8];
9190
9191         u8         reserved_2[0xe0];
9192
9193         union mlx5_ifc_event_auto_bits event_data;
9194
9195         u8         reserved_3[0x10];
9196         u8         signature[0x8];
9197         u8         reserved_4[0x7];
9198         u8         owner[0x1];
9199 };
9200
9201 enum {
9202         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9203 };
9204
9205 struct mlx5_ifc_cmd_queue_entry_bits {
9206         u8         type[0x8];
9207         u8         reserved_0[0x18];
9208
9209         u8         input_length[0x20];
9210
9211         u8         input_mailbox_pointer_63_32[0x20];
9212
9213         u8         input_mailbox_pointer_31_9[0x17];
9214         u8         reserved_1[0x9];
9215
9216         u8         command_input_inline_data[16][0x8];
9217
9218         u8         command_output_inline_data[16][0x8];
9219
9220         u8         output_mailbox_pointer_63_32[0x20];
9221
9222         u8         output_mailbox_pointer_31_9[0x17];
9223         u8         reserved_2[0x9];
9224
9225         u8         output_length[0x20];
9226
9227         u8         token[0x8];
9228         u8         signature[0x8];
9229         u8         reserved_3[0x8];
9230         u8         status[0x7];
9231         u8         ownership[0x1];
9232 };
9233
9234 struct mlx5_ifc_cmd_out_bits {
9235         u8         status[0x8];
9236         u8         reserved_0[0x18];
9237
9238         u8         syndrome[0x20];
9239
9240         u8         command_output[0x20];
9241 };
9242
9243 struct mlx5_ifc_cmd_in_bits {
9244         u8         opcode[0x10];
9245         u8         reserved_0[0x10];
9246
9247         u8         reserved_1[0x10];
9248         u8         op_mod[0x10];
9249
9250         u8         command[0][0x20];
9251 };
9252
9253 struct mlx5_ifc_cmd_if_box_bits {
9254         u8         mailbox_data[512][0x8];
9255
9256         u8         reserved_0[0x180];
9257
9258         u8         next_pointer_63_32[0x20];
9259
9260         u8         next_pointer_31_10[0x16];
9261         u8         reserved_1[0xa];
9262
9263         u8         block_number[0x20];
9264
9265         u8         reserved_2[0x8];
9266         u8         token[0x8];
9267         u8         ctrl_signature[0x8];
9268         u8         signature[0x8];
9269 };
9270
9271 struct mlx5_ifc_mtt_bits {
9272         u8         ptag_63_32[0x20];
9273
9274         u8         ptag_31_8[0x18];
9275         u8         reserved_0[0x6];
9276         u8         wr_en[0x1];
9277         u8         rd_en[0x1];
9278 };
9279
9280 struct mlx5_ifc_vendor_specific_cap_bits {
9281         u8         type[0x8];
9282         u8         length[0x8];
9283         u8         next_pointer[0x8];
9284         u8         capability_id[0x8];
9285
9286         u8         status[0x3];
9287         u8         reserved_0[0xd];
9288         u8         space[0x10];
9289
9290         u8         counter[0x20];
9291
9292         u8         semaphore[0x20];
9293
9294         u8         flag[0x1];
9295         u8         reserved_1[0x1];
9296         u8         address[0x1e];
9297
9298         u8         data[0x20];
9299 };
9300
9301 enum {
9302         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9303         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9304         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9305 };
9306
9307 enum {
9308         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9309         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9310         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9311 };
9312
9313 enum {
9314         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9315         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9316         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9317         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9318         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9319         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9320         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9321         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9322         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9323         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9324         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9325 };
9326
9327 struct mlx5_ifc_initial_seg_bits {
9328         u8         fw_rev_minor[0x10];
9329         u8         fw_rev_major[0x10];
9330
9331         u8         cmd_interface_rev[0x10];
9332         u8         fw_rev_subminor[0x10];
9333
9334         u8         reserved_0[0x40];
9335
9336         u8         cmdq_phy_addr_63_32[0x20];
9337
9338         u8         cmdq_phy_addr_31_12[0x14];
9339         u8         reserved_1[0x2];
9340         u8         nic_interface[0x2];
9341         u8         log_cmdq_size[0x4];
9342         u8         log_cmdq_stride[0x4];
9343
9344         u8         command_doorbell_vector[0x20];
9345
9346         u8         reserved_2[0xf00];
9347
9348         u8         initializing[0x1];
9349         u8         reserved_3[0x4];
9350         u8         nic_interface_supported[0x3];
9351         u8         reserved_4[0x18];
9352
9353         struct mlx5_ifc_health_buffer_bits health_buffer;
9354
9355         u8         no_dram_nic_offset[0x20];
9356
9357         u8         reserved_5[0x6de0];
9358
9359         u8         internal_timer_h[0x20];
9360
9361         u8         internal_timer_l[0x20];
9362
9363         u8         reserved_6[0x20];
9364
9365         u8         reserved_7[0x1f];
9366         u8         clear_int[0x1];
9367
9368         u8         health_syndrome[0x8];
9369         u8         health_counter[0x18];
9370
9371         u8         reserved_8[0x17fc0];
9372 };
9373
9374 union mlx5_ifc_icmd_interface_document_bits {
9375         struct mlx5_ifc_fw_version_bits fw_version;
9376         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9377         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9378         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9379         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9380         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9381         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9382         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9383         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9384         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9385         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9386         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9387         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9388         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9389         u8         reserved_0[0x42c0];
9390 };
9391
9392 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9393         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9394         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9395         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9396         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9397         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9398         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9399         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9400         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9401         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9402         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9403         u8         reserved_0[0x7c0];
9404 };
9405
9406 struct mlx5_ifc_ppcnt_reg_bits {
9407         u8         swid[0x8];
9408         u8         local_port[0x8];
9409         u8         pnat[0x2];
9410         u8         reserved_0[0x8];
9411         u8         grp[0x6];
9412
9413         u8         clr[0x1];
9414         u8         reserved_1[0x1c];
9415         u8         prio_tc[0x3];
9416
9417         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9418 };
9419
9420 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9421         u8         life_time_counter_high[0x20];
9422
9423         u8         life_time_counter_low[0x20];
9424
9425         u8         rx_errors[0x20];
9426
9427         u8         tx_errors[0x20];
9428
9429         u8         l0_to_recovery_eieos[0x20];
9430
9431         u8         l0_to_recovery_ts[0x20];
9432
9433         u8         l0_to_recovery_framing[0x20];
9434
9435         u8         l0_to_recovery_retrain[0x20];
9436
9437         u8         crc_error_dllp[0x20];
9438
9439         u8         crc_error_tlp[0x20];
9440
9441         u8         reserved_0[0x680];
9442 };
9443
9444 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9445         u8         life_time_counter_high[0x20];
9446
9447         u8         life_time_counter_low[0x20];
9448
9449         u8         time_to_boot_image_start[0x20];
9450
9451         u8         time_to_link_image[0x20];
9452
9453         u8         calibration_time[0x20];
9454
9455         u8         time_to_first_perst[0x20];
9456
9457         u8         time_to_detect_state[0x20];
9458
9459         u8         time_to_l0[0x20];
9460
9461         u8         time_to_crs_en[0x20];
9462
9463         u8         time_to_plastic_image_start[0x20];
9464
9465         u8         time_to_iron_image_start[0x20];
9466
9467         u8         perst_handler[0x20];
9468
9469         u8         times_in_l1[0x20];
9470
9471         u8         times_in_l23[0x20];
9472
9473         u8         dl_down[0x20];
9474
9475         u8         config_cycle1usec[0x20];
9476
9477         u8         config_cycle2to7usec[0x20];
9478
9479         u8         config_cycle8to15usec[0x20];
9480
9481         u8         config_cycle16to63usec[0x20];
9482
9483         u8         config_cycle64usec[0x20];
9484
9485         u8         correctable_err_msg_sent[0x20];
9486
9487         u8         non_fatal_err_msg_sent[0x20];
9488
9489         u8         fatal_err_msg_sent[0x20];
9490
9491         u8         reserved_0[0x4e0];
9492 };
9493
9494 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9495         u8         life_time_counter_high[0x20];
9496
9497         u8         life_time_counter_low[0x20];
9498
9499         u8         error_counter_lane0[0x20];
9500
9501         u8         error_counter_lane1[0x20];
9502
9503         u8         error_counter_lane2[0x20];
9504
9505         u8         error_counter_lane3[0x20];
9506
9507         u8         error_counter_lane4[0x20];
9508
9509         u8         error_counter_lane5[0x20];
9510
9511         u8         error_counter_lane6[0x20];
9512
9513         u8         error_counter_lane7[0x20];
9514
9515         u8         error_counter_lane8[0x20];
9516
9517         u8         error_counter_lane9[0x20];
9518
9519         u8         error_counter_lane10[0x20];
9520
9521         u8         error_counter_lane11[0x20];
9522
9523         u8         error_counter_lane12[0x20];
9524
9525         u8         error_counter_lane13[0x20];
9526
9527         u8         error_counter_lane14[0x20];
9528
9529         u8         error_counter_lane15[0x20];
9530
9531         u8         reserved_0[0x580];
9532 };
9533
9534 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9535         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9536         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9537         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9538         u8         reserved_0[0xf8];
9539 };
9540
9541 struct mlx5_ifc_mpcnt_reg_bits {
9542         u8         reserved_0[0x8];
9543         u8         pcie_index[0x8];
9544         u8         reserved_1[0xa];
9545         u8         grp[0x6];
9546
9547         u8         clr[0x1];
9548         u8         reserved_2[0x1f];
9549
9550         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9551 };
9552
9553 union mlx5_ifc_ports_control_registers_document_bits {
9554         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9555         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9556         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9557         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9558         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9559         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9560         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9561         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9562         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9563         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9564         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9565         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9566         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9567         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9568         struct mlx5_ifc_paos_reg_bits paos_reg;
9569         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9570         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9571         struct mlx5_ifc_peir_reg_bits peir_reg;
9572         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9573         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9574         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9575         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9576         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9577         struct mlx5_ifc_phrr_reg_bits phrr_reg;
9578         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9579         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9580         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9581         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9582         struct mlx5_ifc_plib_reg_bits plib_reg;
9583         struct mlx5_ifc_pll_status_data_bits pll_status_data;
9584         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9585         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9586         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9587         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9588         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9589         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9590         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9591         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9592         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9593         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9594         struct mlx5_ifc_ppll_reg_bits ppll_reg;
9595         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9596         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9597         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9598         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9599         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9600         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9601         struct mlx5_ifc_pude_reg_bits pude_reg;
9602         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9603         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9604         struct mlx5_ifc_slrp_reg_bits slrp_reg;
9605         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9606         u8         reserved_0[0x7880];
9607 };
9608
9609 union mlx5_ifc_debug_enhancements_document_bits {
9610         struct mlx5_ifc_health_buffer_bits health_buffer;
9611         u8         reserved_0[0x200];
9612 };
9613
9614 union mlx5_ifc_no_dram_nic_document_bits {
9615         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9616         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9617         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9618         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9619         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9620         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9621         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9622         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9623         u8         reserved_0[0x3160];
9624 };
9625
9626 union mlx5_ifc_uplink_pci_interface_document_bits {
9627         struct mlx5_ifc_initial_seg_bits initial_seg;
9628         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9629         u8         reserved_0[0x20120];
9630 };
9631
9632
9633 #endif /* MLX5_IFC_H */