2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
34 MLX5_EVENT_TYPE_COMP = 0x0,
35 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
36 MLX5_EVENT_TYPE_COMM_EST = 0x2,
37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5,
44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8,
50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9,
51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16,
53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
61 MLX5_EVENT_TYPE_CMD = 0xa,
62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4
77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1,
81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
88 MLX5_CMD_OP_INIT_HCA = 0x102,
89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
90 MLX5_CMD_OP_ENABLE_HCA = 0x104,
91 MLX5_CMD_OP_DISABLE_HCA = 0x105,
92 MLX5_CMD_OP_QUERY_PAGES = 0x107,
93 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
94 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
95 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
96 MLX5_CMD_OP_SET_ISSI = 0x10b,
97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
100 MLX5_CMD_OP_CREATE_MKEY = 0x200,
101 MLX5_CMD_OP_QUERY_MKEY = 0x201,
102 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
105 MLX5_CMD_OP_CREATE_EQ = 0x301,
106 MLX5_CMD_OP_DESTROY_EQ = 0x302,
107 MLX5_CMD_OP_QUERY_EQ = 0x303,
108 MLX5_CMD_OP_GEN_EQE = 0x304,
109 MLX5_CMD_OP_CREATE_CQ = 0x400,
110 MLX5_CMD_OP_DESTROY_CQ = 0x401,
111 MLX5_CMD_OP_QUERY_CQ = 0x402,
112 MLX5_CMD_OP_MODIFY_CQ = 0x403,
113 MLX5_CMD_OP_CREATE_QP = 0x500,
114 MLX5_CMD_OP_DESTROY_QP = 0x501,
115 MLX5_CMD_OP_RST2INIT_QP = 0x502,
116 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
117 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
118 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
120 MLX5_CMD_OP_2ERR_QP = 0x507,
121 MLX5_CMD_OP_2RST_QP = 0x50a,
122 MLX5_CMD_OP_QUERY_QP = 0x50b,
123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
125 MLX5_CMD_OP_CREATE_PSV = 0x600,
126 MLX5_CMD_OP_DESTROY_PSV = 0x601,
127 MLX5_CMD_OP_CREATE_SRQ = 0x700,
128 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
129 MLX5_CMD_OP_QUERY_SRQ = 0x702,
130 MLX5_CMD_OP_ARM_RQ = 0x703,
131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
135 MLX5_CMD_OP_CREATE_DCT = 0x710,
136 MLX5_CMD_OP_DESTROY_DCT = 0x711,
137 MLX5_CMD_OP_DRAIN_DCT = 0x712,
138 MLX5_CMD_OP_QUERY_DCT = 0x713,
139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715,
141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
154 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
155 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
156 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
157 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
158 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
159 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
160 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
161 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
162 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
163 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
164 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
165 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
166 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
167 MLX5_CMD_OP_ALLOC_PD = 0x800,
168 MLX5_CMD_OP_DEALLOC_PD = 0x801,
169 MLX5_CMD_OP_ALLOC_UAR = 0x802,
170 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
171 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
172 MLX5_CMD_OP_ACCESS_REG = 0x805,
173 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
174 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
175 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
176 MLX5_CMD_OP_MAD_IFC = 0x50d,
177 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
178 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
179 MLX5_CMD_OP_NOP = 0x80d,
180 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
181 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
182 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
183 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
184 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
185 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
188 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820,
189 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821,
190 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
191 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
192 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
193 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
194 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
195 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
196 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
197 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
198 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
199 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
200 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
201 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
202 MLX5_CMD_OP_CREATE_LAG = 0x840,
203 MLX5_CMD_OP_MODIFY_LAG = 0x841,
204 MLX5_CMD_OP_QUERY_LAG = 0x842,
205 MLX5_CMD_OP_DESTROY_LAG = 0x843,
206 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
207 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
208 MLX5_CMD_OP_CREATE_TIR = 0x900,
209 MLX5_CMD_OP_MODIFY_TIR = 0x901,
210 MLX5_CMD_OP_DESTROY_TIR = 0x902,
211 MLX5_CMD_OP_QUERY_TIR = 0x903,
212 MLX5_CMD_OP_CREATE_SQ = 0x904,
213 MLX5_CMD_OP_MODIFY_SQ = 0x905,
214 MLX5_CMD_OP_DESTROY_SQ = 0x906,
215 MLX5_CMD_OP_QUERY_SQ = 0x907,
216 MLX5_CMD_OP_CREATE_RQ = 0x908,
217 MLX5_CMD_OP_MODIFY_RQ = 0x909,
218 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
219 MLX5_CMD_OP_QUERY_RQ = 0x90b,
220 MLX5_CMD_OP_CREATE_RMP = 0x90c,
221 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
222 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
223 MLX5_CMD_OP_QUERY_RMP = 0x90f,
224 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
225 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
226 MLX5_CMD_OP_CREATE_TIS = 0x912,
227 MLX5_CMD_OP_MODIFY_TIS = 0x913,
228 MLX5_CMD_OP_DESTROY_TIS = 0x914,
229 MLX5_CMD_OP_QUERY_TIS = 0x915,
230 MLX5_CMD_OP_CREATE_RQT = 0x916,
231 MLX5_CMD_OP_MODIFY_RQT = 0x917,
232 MLX5_CMD_OP_DESTROY_RQT = 0x918,
233 MLX5_CMD_OP_QUERY_RQT = 0x919,
234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
248 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
249 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
250 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
251 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
252 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
253 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
254 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
258 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007,
259 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400,
260 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001,
261 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003,
262 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004,
263 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005,
264 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006,
265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007,
266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009,
268 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a,
269 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004
272 struct mlx5_ifc_flow_table_fields_supported_bits {
275 u8 outer_ether_type[0x1];
277 u8 outer_first_prio[0x1];
278 u8 outer_first_cfi[0x1];
279 u8 outer_first_vid[0x1];
281 u8 outer_second_prio[0x1];
282 u8 outer_second_cfi[0x1];
283 u8 outer_second_vid[0x1];
284 u8 outer_ipv6_flow_label[0x1];
288 u8 outer_ip_protocol[0x1];
289 u8 outer_ip_ecn[0x1];
290 u8 outer_ip_dscp[0x1];
291 u8 outer_udp_sport[0x1];
292 u8 outer_udp_dport[0x1];
293 u8 outer_tcp_sport[0x1];
294 u8 outer_tcp_dport[0x1];
295 u8 outer_tcp_flags[0x1];
296 u8 outer_gre_protocol[0x1];
297 u8 outer_gre_key[0x1];
298 u8 outer_vxlan_vni[0x1];
299 u8 outer_geneve_vni[0x1];
300 u8 outer_geneve_oam[0x1];
301 u8 outer_geneve_protocol_type[0x1];
302 u8 outer_geneve_opt_len[0x1];
304 u8 source_eswitch_port[0x1];
308 u8 inner_ether_type[0x1];
310 u8 inner_first_prio[0x1];
311 u8 inner_first_cfi[0x1];
312 u8 inner_first_vid[0x1];
314 u8 inner_second_prio[0x1];
315 u8 inner_second_cfi[0x1];
316 u8 inner_second_vid[0x1];
317 u8 inner_ipv6_flow_label[0x1];
321 u8 inner_ip_protocol[0x1];
322 u8 inner_ip_ecn[0x1];
323 u8 inner_ip_dscp[0x1];
324 u8 inner_udp_sport[0x1];
325 u8 inner_udp_dport[0x1];
326 u8 inner_tcp_sport[0x1];
327 u8 inner_tcp_dport[0x1];
328 u8 inner_tcp_flags[0x1];
339 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
340 u8 ingress_general_high[0x20];
342 u8 ingress_general_low[0x20];
344 u8 ingress_policy_engine_high[0x20];
346 u8 ingress_policy_engine_low[0x20];
348 u8 ingress_vlan_membership_high[0x20];
350 u8 ingress_vlan_membership_low[0x20];
352 u8 ingress_tag_frame_type_high[0x20];
354 u8 ingress_tag_frame_type_low[0x20];
356 u8 egress_vlan_membership_high[0x20];
358 u8 egress_vlan_membership_low[0x20];
360 u8 loopback_filter_high[0x20];
362 u8 loopback_filter_low[0x20];
364 u8 egress_general_high[0x20];
366 u8 egress_general_low[0x20];
368 u8 reserved_at_1c0[0x40];
370 u8 egress_hoq_high[0x20];
372 u8 egress_hoq_low[0x20];
374 u8 port_isolation_high[0x20];
376 u8 port_isolation_low[0x20];
378 u8 egress_policy_engine_high[0x20];
380 u8 egress_policy_engine_low[0x20];
382 u8 ingress_tx_link_down_high[0x20];
384 u8 ingress_tx_link_down_low[0x20];
386 u8 egress_stp_filter_high[0x20];
388 u8 egress_stp_filter_low[0x20];
390 u8 egress_hoq_stall_high[0x20];
392 u8 egress_hoq_stall_low[0x20];
394 u8 reserved_at_340[0x440];
396 struct mlx5_ifc_flow_table_prop_layout_bits {
399 u8 flow_counter[0x1];
400 u8 flow_modify_en[0x1];
402 u8 identified_miss_table[0x1];
403 u8 flow_table_modify[0x1];
406 u8 reset_root_to_default[0x1];
407 u8 reserved_at_a[0x16];
409 u8 reserved_at_20[0x2];
410 u8 log_max_ft_size[0x6];
411 u8 reserved_at_28[0x10];
412 u8 max_ft_level[0x8];
414 u8 reserved_at_40[0x20];
416 u8 reserved_at_60[0x18];
417 u8 log_max_ft_num[0x8];
419 u8 reserved_at_80[0x10];
420 u8 log_max_flow_counter[0x8];
421 u8 log_max_destination[0x8];
423 u8 reserved_at_a0[0x18];
424 u8 log_max_flow[0x8];
426 u8 reserved_at_c0[0x40];
428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
430 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
433 struct mlx5_ifc_odp_per_transport_service_cap_bits {
443 struct mlx5_ifc_flow_counter_list_bits {
445 u8 flow_counter_id[0x10];
451 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,
452 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1,
453 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2,
454 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
457 struct mlx5_ifc_dest_format_struct_bits {
458 u8 destination_type[0x8];
459 u8 destination_id[0x18];
464 struct mlx5_ifc_ipv4_layout_bits {
465 u8 reserved_at_0[0x60];
470 struct mlx5_ifc_ipv6_layout_bits {
474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
475 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
476 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
477 u8 reserved_at_0[0x80];
480 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
515 struct mlx5_ifc_fte_match_set_misc_bits {
520 u8 source_port[0x10];
522 u8 outer_second_prio[0x3];
523 u8 outer_second_cfi[0x1];
524 u8 outer_second_vid[0xc];
525 u8 inner_second_prio[0x3];
526 u8 inner_second_cfi[0x1];
527 u8 inner_second_vid[0xc];
529 u8 outer_second_vlan_tag[0x1];
530 u8 inner_second_vlan_tag[0x1];
532 u8 gre_protocol[0x10];
545 u8 outer_ipv6_flow_label[0x14];
548 u8 inner_ipv6_flow_label[0x14];
551 u8 geneve_opt_len[0x6];
552 u8 geneve_protocol_type[0x10];
560 struct mlx5_ifc_cmd_pas_bits {
567 struct mlx5_ifc_uint64_bits {
573 struct mlx5_ifc_application_prio_entry_bits {
578 u8 protocol_id[0x10];
581 struct mlx5_ifc_nodnic_ring_doorbell_bits {
588 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
589 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
590 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
591 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
592 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
593 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
594 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
595 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
596 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
597 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
600 struct mlx5_ifc_ads_bits {
613 u8 src_addr_index[0x8];
622 u8 rgid_rip[16][0x8];
642 struct mlx5_ifc_diagnostic_counter_cap_bits {
648 struct mlx5_ifc_debug_cap_bits {
650 u8 log_max_samples[0x8];
654 u8 health_mon_rx_activity[0x1];
656 u8 log_min_sample_period[0x8];
658 u8 reserved_2[0x1c0];
660 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
663 struct mlx5_ifc_qos_cap_bits {
664 u8 packet_pacing[0x1];
665 u8 esw_scheduling[0x1];
666 u8 esw_bw_share[0x1];
667 u8 esw_rate_limit[0x1];
669 u8 packet_pacing_burst_bound[0x1];
670 u8 reserved_at_6[0x1a];
672 u8 reserved_at_20[0x20];
674 u8 packet_pacing_max_rate[0x20];
676 u8 packet_pacing_min_rate[0x20];
678 u8 reserved_at_80[0x10];
679 u8 packet_pacing_rate_table_size[0x10];
681 u8 esw_element_type[0x10];
682 u8 esw_tsar_type[0x10];
684 u8 reserved_at_c0[0x10];
685 u8 max_qos_para_vport[0x10];
687 u8 max_tsar_bw_share[0x20];
689 u8 reserved_at_100[0x700];
692 struct mlx5_ifc_snapshot_cap_bits {
694 u8 suspend_qp_uc[0x1];
695 u8 suspend_qp_ud[0x1];
696 u8 suspend_qp_rc[0x1];
701 u8 restore_mkey[0x1];
708 u8 reserved_3[0x7a0];
711 struct mlx5_ifc_e_switch_cap_bits {
712 u8 vport_svlan_strip[0x1];
713 u8 vport_cvlan_strip[0x1];
714 u8 vport_svlan_insert[0x1];
715 u8 vport_cvlan_insert_if_not_exist[0x1];
716 u8 vport_cvlan_insert_overwrite[0x1];
720 u8 nic_vport_node_guid_modify[0x1];
721 u8 nic_vport_port_guid_modify[0x1];
723 u8 reserved_1[0x7e0];
726 struct mlx5_ifc_flow_table_eswitch_cap_bits {
727 u8 reserved_0[0x200];
729 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
735 u8 reserved_1[0x7800];
738 struct mlx5_ifc_flow_table_nic_cap_bits {
739 u8 nic_rx_multi_path_tirs[0x1];
740 u8 nic_rx_multi_path_tirs_fts[0x1];
741 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
742 u8 reserved_at_3[0x1fd];
744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
746 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
756 u8 reserved_1[0x7200];
760 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR = 0x5031,
763 struct mlx5_ifc_pddr_module_info_bits {
764 u8 cable_technology[0x8];
765 u8 cable_breakout[0x8];
766 u8 ext_ethernet_compliance_code[0x8];
767 u8 ethernet_compliance_code[0x8];
770 u8 cable_vendor[0x4];
771 u8 cable_length[0x8];
772 u8 cable_identifier[0x8];
773 u8 cable_power_class[0x8];
775 u8 reserved_at_40[0x8];
776 u8 cable_rx_amp[0x8];
777 u8 cable_rx_emphasis[0x8];
778 u8 cable_tx_equalization[0x8];
780 u8 reserved_at_60[0x8];
781 u8 cable_attenuation_12g[0x8];
782 u8 cable_attenuation_7g[0x8];
783 u8 cable_attenuation_5g[0x8];
785 u8 reserved_at_80[0x8];
788 u8 reserved_at_90[0x4];
789 u8 rx_cdr_state[0x4];
790 u8 reserved_at_98[0x4];
791 u8 tx_cdr_state[0x4];
793 u8 vendor_name[16][0x8];
795 u8 vendor_pn[16][0x8];
801 u8 vendor_sn[16][0x8];
803 u8 temperature[0x10];
806 u8 rx_power_lane0[0x10];
807 u8 rx_power_lane1[0x10];
809 u8 rx_power_lane2[0x10];
810 u8 rx_power_lane3[0x10];
812 u8 reserved_at_2c0[0x40];
814 u8 tx_power_lane0[0x10];
815 u8 tx_power_lane1[0x10];
817 u8 tx_power_lane2[0x10];
818 u8 tx_power_lane3[0x10];
820 u8 reserved_at_340[0x40];
822 u8 tx_bias_lane0[0x10];
823 u8 tx_bias_lane1[0x10];
825 u8 tx_bias_lane2[0x10];
826 u8 tx_bias_lane3[0x10];
828 u8 reserved_at_3c0[0x40];
830 u8 temperature_high_th[0x10];
831 u8 temperature_low_th[0x10];
833 u8 voltage_high_th[0x10];
834 u8 voltage_low_th[0x10];
836 u8 rx_power_high_th[0x10];
837 u8 rx_power_low_th[0x10];
839 u8 tx_power_high_th[0x10];
840 u8 tx_power_low_th[0x10];
842 u8 tx_bias_high_th[0x10];
843 u8 tx_bias_low_th[0x10];
845 u8 reserved_at_4a0[0x10];
848 u8 reserved_at_4c0[0x300];
851 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
852 struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
853 u8 reserved_at_0[0x7c0];
856 struct mlx5_ifc_pddr_reg_bits {
857 u8 reserved_at_0[0x8];
860 u8 reserved_at_12[0xe];
862 u8 reserved_at_20[0x18];
865 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
868 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
872 u8 lro_psh_flag[0x1];
873 u8 lro_time_stamp[0x1];
874 u8 lro_max_msg_sz_mode[0x2];
875 u8 wqe_vlan_insert[0x1];
876 u8 self_lb_en_modifiable[0x1];
880 u8 multi_pkt_send_wqe[0x2];
881 u8 wqe_inline_mode[0x2];
882 u8 rss_ind_tbl_cap[0x4];
885 u8 tunnel_lso_const_out_ip_id[0x1];
886 u8 tunnel_lro_gre[0x1];
887 u8 tunnel_lro_vxlan[0x1];
888 u8 tunnel_statless_gre[0x1];
889 u8 tunnel_stateless_vxlan[0x1];
895 u8 max_geneve_opt_len[0x1];
896 u8 tunnel_stateless_geneve_rx[0x1];
899 u8 lro_min_mss_size[0x10];
901 u8 reserved_4[0x120];
903 u8 lro_timer_supported_periods[4][0x20];
905 u8 reserved_5[0x600];
909 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1,
910 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2,
911 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
914 struct mlx5_ifc_roce_cap_bits {
916 u8 rts2rts_primary_eth_prio[0x1];
917 u8 roce_rx_allow_untagged[0x1];
918 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
927 u8 roce_version[0x8];
930 u8 r_roce_dest_udp_port[0x10];
932 u8 r_roce_max_src_udp_port[0x10];
933 u8 r_roce_min_src_udp_port[0x10];
936 u8 roce_address_table_size[0x10];
938 u8 reserved_6[0x700];
942 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1,
943 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
944 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
945 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
946 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
947 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
948 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
949 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
950 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
954 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
955 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
956 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
965 struct mlx5_ifc_atomic_caps_bits {
968 u8 atomic_req_8B_endianess_mode[0x2];
970 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
977 u8 atomic_operations[0x10];
980 u8 atomic_size_qp[0x10];
983 u8 atomic_size_dc[0x10];
985 u8 reserved_7[0x720];
988 struct mlx5_ifc_odp_cap_bits {
996 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
998 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1000 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1002 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1004 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1006 u8 reserved_3[0x6e0];
1010 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1011 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1012 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1013 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1014 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1018 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1019 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1020 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1021 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1022 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1023 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1027 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1028 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1032 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1033 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1034 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1037 struct mlx5_ifc_cmd_hca_cap_bits {
1038 u8 reserved_0[0x80];
1040 u8 log_max_srq_sz[0x8];
1041 u8 log_max_qp_sz[0x8];
1046 u8 log_max_srq[0x5];
1047 u8 reserved_3[0x10];
1050 u8 log_max_cq_sz[0x8];
1054 u8 log_max_eq_sz[0x8];
1055 u8 relaxed_ordering_write[1];
1057 u8 log_max_mkey[0x6];
1059 u8 fast_teardown[0x1];
1062 u8 max_indirection[0x8];
1064 u8 log_max_mrw_sz[0x7];
1065 u8 force_teardown[0x1];
1067 u8 log_max_bsf_list_size[0x6];
1068 u8 reserved_10[0x2];
1069 u8 log_max_klm_list_size[0x6];
1071 u8 reserved_11[0xa];
1072 u8 log_max_ra_req_dc[0x6];
1073 u8 reserved_12[0xa];
1074 u8 log_max_ra_res_dc[0x6];
1076 u8 reserved_13[0xa];
1077 u8 log_max_ra_req_qp[0x6];
1078 u8 reserved_14[0xa];
1079 u8 log_max_ra_res_qp[0x6];
1082 u8 cc_query_allowed[0x1];
1083 u8 cc_modify_allowed[0x1];
1085 u8 cache_line_128byte[0x1];
1086 u8 reserved_at_165[0xa];
1088 u8 gid_table_size[0x10];
1090 u8 out_of_seq_cnt[0x1];
1091 u8 vport_counters[0x1];
1092 u8 retransmission_q_counters[0x1];
1094 u8 modify_rq_counters_set_id[0x1];
1095 u8 rq_delay_drop[0x1];
1097 u8 pkey_table_size[0x10];
1099 u8 vport_group_manager[0x1];
1100 u8 vhca_group_manager[0x1];
1103 u8 reserved_17[0x1];
1105 u8 nic_flow_table[0x1];
1106 u8 eswitch_flow_table[0x1];
1107 u8 reserved_18[0x1];
1110 u8 local_ca_ack_delay[0x5];
1111 u8 port_module_event[0x1];
1112 u8 reserved_19[0x5];
1117 u8 reserved_20[0x2];
1118 u8 log_max_msg[0x5];
1119 u8 reserved_21[0x4];
1121 u8 temp_warn_event[0x1];
1123 u8 general_notification_event[0x1];
1124 u8 reserved_at_1d3[0x2];
1128 u8 reserved_23[0x1];
1137 u8 stat_rate_support[0x10];
1138 u8 reserved_24[0xc];
1139 u8 cqe_version[0x4];
1141 u8 compact_address_vector[0x1];
1142 u8 striding_rq[0x1];
1143 u8 reserved_25[0x1];
1144 u8 ipoib_enhanced_offloads[0x1];
1145 u8 ipoib_ipoib_offloads[0x1];
1146 u8 reserved_26[0x8];
1147 u8 dc_connect_qp[0x1];
1148 u8 dc_cnak_trace[0x1];
1149 u8 drain_sigerr[0x1];
1150 u8 cmdif_checksum[0x2];
1152 u8 reserved_27[0x1];
1153 u8 wq_signature[0x1];
1154 u8 sctr_data_cqe[0x1];
1155 u8 reserved_28[0x1];
1161 u8 eth_net_offloads[0x1];
1164 u8 reserved_30[0x1];
1168 u8 cq_moderation[0x1];
1169 u8 cq_period_mode_modify[0x1];
1170 u8 cq_invalidate[0x1];
1171 u8 reserved_at_225[0x1];
1172 u8 cq_eq_remap[0x1];
1174 u8 block_lb_mc[0x1];
1175 u8 exponential_backoff[0x1];
1176 u8 scqe_break_moderation[0x1];
1177 u8 cq_period_start_from_cqe[0x1];
1182 u8 reserved_32[0x6];
1185 u8 set_deth_sqpn[0x1];
1186 u8 reserved_33[0x3];
1192 u8 reserved_34[0xa];
1194 u8 reserved_35[0x8];
1198 u8 driver_version[0x1];
1199 u8 pad_tx_eth_packet[0x1];
1200 u8 reserved_36[0x8];
1201 u8 log_bf_reg_size[0x5];
1202 u8 reserved_37[0x10];
1204 u8 num_of_diagnostic_counters[0x10];
1205 u8 max_wqe_sz_sq[0x10];
1207 u8 reserved_38[0x10];
1208 u8 max_wqe_sz_rq[0x10];
1210 u8 reserved_39[0x10];
1211 u8 max_wqe_sz_sq_dc[0x10];
1213 u8 reserved_40[0x7];
1214 u8 max_qp_mcg[0x19];
1216 u8 reserved_41[0x18];
1217 u8 log_max_mcg[0x8];
1219 u8 reserved_42[0x3];
1220 u8 log_max_transport_domain[0x5];
1221 u8 reserved_43[0x3];
1223 u8 reserved_44[0xb];
1224 u8 log_max_xrcd[0x5];
1226 u8 nic_receive_steering_discard[0x1];
1227 u8 reserved_45[0x7];
1228 u8 log_max_flow_counter_bulk[0x8];
1229 u8 max_flow_counter[0x10];
1231 u8 reserved_46[0x3];
1233 u8 reserved_47[0x3];
1235 u8 reserved_48[0x3];
1236 u8 log_max_tir[0x5];
1237 u8 reserved_49[0x3];
1238 u8 log_max_tis[0x5];
1240 u8 basic_cyclic_rcv_wqe[0x1];
1241 u8 reserved_50[0x2];
1242 u8 log_max_rmp[0x5];
1243 u8 reserved_51[0x3];
1244 u8 log_max_rqt[0x5];
1245 u8 reserved_52[0x3];
1246 u8 log_max_rqt_size[0x5];
1247 u8 reserved_53[0x3];
1248 u8 log_max_tis_per_sq[0x5];
1250 u8 reserved_54[0x3];
1251 u8 log_max_stride_sz_rq[0x5];
1252 u8 reserved_55[0x3];
1253 u8 log_min_stride_sz_rq[0x5];
1254 u8 reserved_56[0x3];
1255 u8 log_max_stride_sz_sq[0x5];
1256 u8 reserved_57[0x3];
1257 u8 log_min_stride_sz_sq[0x5];
1259 u8 reserved_58[0x1b];
1260 u8 log_max_wq_sz[0x5];
1262 u8 nic_vport_change_event[0x1];
1263 u8 disable_local_lb[0x1];
1264 u8 reserved_59[0x9];
1265 u8 log_max_vlan_list[0x5];
1266 u8 reserved_60[0x3];
1267 u8 log_max_current_mc_list[0x5];
1268 u8 reserved_61[0x3];
1269 u8 log_max_current_uc_list[0x5];
1271 u8 reserved_62[0x80];
1273 u8 reserved_63[0x3];
1274 u8 log_max_l2_table[0x5];
1275 u8 reserved_64[0x8];
1276 u8 log_uar_page_sz[0x10];
1278 u8 reserved_65[0x20];
1280 u8 device_frequency_mhz[0x20];
1282 u8 device_frequency_khz[0x20];
1284 u8 reserved_66[0x80];
1286 u8 log_max_atomic_size_qp[0x8];
1287 u8 reserved_67[0x10];
1288 u8 log_max_atomic_size_dc[0x8];
1290 u8 reserved_68[0x1f];
1291 u8 cqe_compression[0x1];
1293 u8 cqe_compression_timeout[0x10];
1294 u8 cqe_compression_max_num[0x10];
1296 u8 reserved_69[0x220];
1299 enum mlx5_flow_destination_type {
1300 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1301 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1302 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1305 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1306 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1307 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1308 u8 reserved_0[0x40];
1311 struct mlx5_ifc_fte_match_param_bits {
1312 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1314 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1316 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1318 u8 reserved_0[0xa00];
1322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1324 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1325 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1326 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1329 struct mlx5_ifc_rx_hash_field_select_bits {
1330 u8 l3_prot_type[0x1];
1331 u8 l4_prot_type[0x1];
1332 u8 selected_fields[0x1e];
1336 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1337 MLX5_WQ_TYPE_CYCLIC = 0x1,
1338 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2,
1339 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1348 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1349 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1352 struct mlx5_ifc_wq_bits {
1354 u8 wq_signature[0x1];
1355 u8 end_padding_mode[0x2];
1357 u8 reserved_0[0x18];
1359 u8 hds_skip_first_sge[0x1];
1360 u8 log2_hds_buf_size[0x3];
1362 u8 page_offset[0x5];
1373 u8 hw_counter[0x20];
1375 u8 sw_counter[0x20];
1378 u8 log_wq_stride[0x4];
1380 u8 log_wq_pg_sz[0x5];
1384 u8 reserved_7[0x15];
1385 u8 single_wqe_log_num_of_strides[0x3];
1386 u8 two_byte_shift_en[0x1];
1388 u8 single_stride_log_num_of_bytes[0x3];
1390 u8 reserved_9[0x4c0];
1392 struct mlx5_ifc_cmd_pas_bits pas[0];
1395 struct mlx5_ifc_rq_num_bits {
1400 struct mlx5_ifc_mac_address_layout_bits {
1401 u8 reserved_0[0x10];
1402 u8 mac_addr_47_32[0x10];
1404 u8 mac_addr_31_0[0x20];
1407 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1408 u8 reserved_0[0xa0];
1410 u8 min_time_between_cnps[0x20];
1412 u8 reserved_1[0x12];
1415 u8 cnp_prio_mode[0x1];
1416 u8 cnp_802p_prio[0x3];
1418 u8 reserved_3[0x720];
1421 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1422 u8 reserved_0[0x60];
1425 u8 clamp_tgt_rate[0x1];
1427 u8 clamp_tgt_rate_after_time_inc[0x1];
1428 u8 reserved_3[0x17];
1430 u8 reserved_4[0x20];
1432 u8 rpg_time_reset[0x20];
1434 u8 rpg_byte_reset[0x20];
1436 u8 rpg_threshold[0x20];
1438 u8 rpg_max_rate[0x20];
1440 u8 rpg_ai_rate[0x20];
1442 u8 rpg_hai_rate[0x20];
1446 u8 rpg_min_dec_fac[0x20];
1448 u8 rpg_min_rate[0x20];
1450 u8 reserved_5[0xe0];
1452 u8 rate_to_set_on_first_cnp[0x20];
1456 u8 dce_tcp_rtt[0x20];
1458 u8 rate_reduce_monitor_period[0x20];
1460 u8 reserved_6[0x20];
1462 u8 initial_alpha_value[0x20];
1464 u8 reserved_7[0x4a0];
1467 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1468 u8 reserved_0[0x80];
1470 u8 rppp_max_rps[0x20];
1472 u8 rpg_time_reset[0x20];
1474 u8 rpg_byte_reset[0x20];
1476 u8 rpg_threshold[0x20];
1478 u8 rpg_max_rate[0x20];
1480 u8 rpg_ai_rate[0x20];
1482 u8 rpg_hai_rate[0x20];
1486 u8 rpg_min_dec_fac[0x20];
1488 u8 rpg_min_rate[0x20];
1490 u8 reserved_1[0x640];
1494 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1495 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1496 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1499 struct mlx5_ifc_resize_field_select_bits {
1500 u8 resize_field_select[0x20];
1504 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1505 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1506 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1507 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1508 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
1509 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
1512 struct mlx5_ifc_modify_field_select_bits {
1513 u8 modify_field_select[0x20];
1516 struct mlx5_ifc_field_select_r_roce_np_bits {
1517 u8 field_select_r_roce_np[0x20];
1521 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2,
1522 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4,
1523 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8,
1524 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10,
1525 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20,
1526 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40,
1527 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80,
1528 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100,
1529 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200,
1530 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400,
1531 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800,
1532 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000,
1533 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000,
1534 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000,
1535 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000,
1538 struct mlx5_ifc_field_select_r_roce_rp_bits {
1539 u8 field_select_r_roce_rp[0x20];
1543 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1544 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1545 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1546 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1547 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1548 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1549 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1550 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1551 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1552 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1555 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1556 u8 field_select_8021qaurp[0x20];
1559 struct mlx5_ifc_pptb_reg_bits {
1579 u8 reserved_3[0x10];
1581 u8 untagged_buff[0x4];
1584 struct mlx5_ifc_dcbx_app_reg_bits {
1586 u8 port_number[0x8];
1587 u8 reserved_1[0x10];
1589 u8 reserved_2[0x1a];
1590 u8 num_app_prio[0x6];
1592 u8 reserved_3[0x40];
1594 struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1597 struct mlx5_ifc_dcbx_param_reg_bits {
1598 u8 dcbx_cee_cap[0x1];
1599 u8 dcbx_ieee_cap[0x1];
1600 u8 dcbx_standby_cap[0x1];
1602 u8 port_number[0x8];
1604 u8 max_application_table_size[0x6];
1606 u8 reserved_2[0x15];
1607 u8 version_oper[0x3];
1609 u8 version_admin[0x3];
1611 u8 willing_admin[0x1];
1613 u8 pfc_cap_oper[0x4];
1615 u8 pfc_cap_admin[0x4];
1617 u8 num_of_tc_oper[0x4];
1619 u8 num_of_tc_admin[0x4];
1621 u8 remote_willing[0x1];
1623 u8 remote_pfc_cap[0x4];
1624 u8 reserved_9[0x14];
1625 u8 remote_num_of_tc[0x4];
1627 u8 reserved_10[0x18];
1630 u8 reserved_11[0x160];
1633 struct mlx5_ifc_qhll_bits {
1634 u8 reserved_at_0[0x8];
1636 u8 reserved_at_10[0x10];
1638 u8 reserved_at_20[0x1b];
1642 u8 reserved_at_41[0x1c];
1646 struct mlx5_ifc_qetcr_reg_bits {
1647 u8 operation_type[0x2];
1648 u8 cap_local_admin[0x1];
1649 u8 cap_remote_admin[0x1];
1651 u8 port_number[0x8];
1652 u8 reserved_1[0x10];
1654 u8 reserved_2[0x20];
1658 u8 global_configuration[0x40];
1661 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1662 u8 queue_address_63_32[0x20];
1664 u8 queue_address_31_12[0x14];
1668 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1671 u8 queue_number[0x18];
1675 u8 reserved_2[0x10];
1676 u8 pkey_index[0x10];
1678 u8 reserved_3[0x40];
1681 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1688 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0,
1689 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1,
1693 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0,
1694 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1,
1695 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2,
1696 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
1699 struct mlx5_ifc_nodnic_event_word_bits {
1700 u8 driver_reset_needed[0x1];
1701 u8 port_management_change_event[0x1];
1702 u8 reserved_0[0x19];
1707 struct mlx5_ifc_nic_vport_change_event_bits {
1708 u8 reserved_0[0x10];
1711 u8 reserved_1[0xc0];
1714 struct mlx5_ifc_pages_req_event_bits {
1715 u8 reserved_0[0x10];
1716 u8 function_id[0x10];
1720 u8 reserved_1[0xa0];
1723 struct mlx5_ifc_cmd_inter_comp_event_bits {
1724 u8 command_completion_vector[0x20];
1726 u8 reserved_0[0xc0];
1729 struct mlx5_ifc_stall_vl_event_bits {
1730 u8 reserved_0[0x18];
1735 u8 reserved_2[0xa0];
1738 struct mlx5_ifc_db_bf_congestion_event_bits {
1739 u8 event_subtype[0x8];
1741 u8 congestion_level[0x8];
1744 u8 reserved_2[0xa0];
1747 struct mlx5_ifc_gpio_event_bits {
1748 u8 reserved_0[0x60];
1750 u8 gpio_event_hi[0x20];
1752 u8 gpio_event_lo[0x20];
1754 u8 reserved_1[0x40];
1757 struct mlx5_ifc_port_state_change_event_bits {
1758 u8 reserved_0[0x40];
1761 u8 reserved_1[0x1c];
1763 u8 reserved_2[0x80];
1766 struct mlx5_ifc_dropped_packet_logged_bits {
1767 u8 reserved_0[0xe0];
1771 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1772 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1775 struct mlx5_ifc_cq_error_bits {
1779 u8 reserved_1[0x20];
1781 u8 reserved_2[0x18];
1784 u8 reserved_3[0x80];
1787 struct mlx5_ifc_rdma_page_fault_event_bits {
1788 u8 bytes_commited[0x20];
1792 u8 reserved_0[0x10];
1793 u8 packet_len[0x10];
1795 u8 rdma_op_len[0x20];
1806 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1807 u8 bytes_committed[0x20];
1809 u8 reserved_0[0x10];
1812 u8 reserved_1[0x10];
1815 u8 reserved_2[0x60];
1825 MLX5_QP_EVENTS_TYPE_QP = 0x0,
1826 MLX5_QP_EVENTS_TYPE_RQ = 0x1,
1827 MLX5_QP_EVENTS_TYPE_SQ = 0x2,
1830 struct mlx5_ifc_qp_events_bits {
1831 u8 reserved_0[0xa0];
1834 u8 reserved_1[0x18];
1837 u8 qpn_rqn_sqn[0x18];
1840 struct mlx5_ifc_dct_events_bits {
1841 u8 reserved_0[0xc0];
1844 u8 dct_number[0x18];
1847 struct mlx5_ifc_comp_event_bits {
1848 u8 reserved_0[0xc0];
1854 struct mlx5_ifc_fw_version_bits {
1856 u8 reserved_0[0x10];
1872 MLX5_QPC_STATE_RST = 0x0,
1873 MLX5_QPC_STATE_INIT = 0x1,
1874 MLX5_QPC_STATE_RTR = 0x2,
1875 MLX5_QPC_STATE_RTS = 0x3,
1876 MLX5_QPC_STATE_SQER = 0x4,
1877 MLX5_QPC_STATE_SQD = 0x5,
1878 MLX5_QPC_STATE_ERR = 0x6,
1879 MLX5_QPC_STATE_SUSPENDED = 0x9,
1883 MLX5_QPC_ST_RC = 0x0,
1884 MLX5_QPC_ST_UC = 0x1,
1885 MLX5_QPC_ST_UD = 0x2,
1886 MLX5_QPC_ST_XRC = 0x3,
1887 MLX5_QPC_ST_DCI = 0x5,
1888 MLX5_QPC_ST_QP0 = 0x7,
1889 MLX5_QPC_ST_QP1 = 0x8,
1890 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1891 MLX5_QPC_ST_REG_UMR = 0xc,
1895 MLX5_QP_PM_ARMED = 0x0,
1896 MLX5_QP_PM_REARM = 0x1,
1897 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1898 MLX5_QP_PM_MIGRATED = 0x3,
1902 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1903 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1907 MLX5_QPC_MTU_256_BYTES = 0x1,
1908 MLX5_QPC_MTU_512_BYTES = 0x2,
1909 MLX5_QPC_MTU_1K_BYTES = 0x3,
1910 MLX5_QPC_MTU_2K_BYTES = 0x4,
1911 MLX5_QPC_MTU_4K_BYTES = 0x5,
1912 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1916 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1917 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1918 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1919 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1920 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1921 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1922 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1923 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1927 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1928 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1929 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1933 MLX5_QPC_CS_RES_DISABLE = 0x0,
1934 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1935 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1938 struct mlx5_ifc_qpc_bits {
1940 u8 lag_tx_port_affinity[0x4];
1945 u8 end_padding_mode[0x2];
1948 u8 wq_signature[0x1];
1949 u8 block_lb_mc[0x1];
1950 u8 atomic_like_write_en[0x1];
1951 u8 latency_sensitive[0x1];
1953 u8 drain_sigerr[0x1];
1958 u8 log_msg_max[0x5];
1960 u8 log_rq_size[0x4];
1961 u8 log_rq_stride[0x3];
1963 u8 log_sq_size[0x4];
1966 u8 ulp_stateless_offload_mode[0x4];
1968 u8 counter_set_id[0x8];
1972 u8 user_index[0x18];
1975 u8 log_page_size[0x5];
1976 u8 remote_qpn[0x18];
1978 struct mlx5_ifc_ads_bits primary_address_path;
1980 struct mlx5_ifc_ads_bits secondary_address_path;
1982 u8 log_ack_req_freq[0x4];
1983 u8 reserved_10[0x4];
1984 u8 log_sra_max[0x3];
1985 u8 reserved_11[0x2];
1986 u8 retry_count[0x3];
1988 u8 reserved_12[0x1];
1990 u8 cur_rnr_retry[0x3];
1991 u8 cur_retry_count[0x3];
1992 u8 reserved_13[0x5];
1994 u8 reserved_14[0x20];
1996 u8 reserved_15[0x8];
1997 u8 next_send_psn[0x18];
1999 u8 reserved_16[0x8];
2002 u8 reserved_at_400[0x8];
2005 u8 reserved_17[0x20];
2007 u8 reserved_18[0x8];
2008 u8 last_acked_psn[0x18];
2010 u8 reserved_19[0x8];
2013 u8 reserved_20[0x8];
2014 u8 log_rra_max[0x3];
2015 u8 reserved_21[0x1];
2016 u8 atomic_mode[0x4];
2020 u8 reserved_22[0x1];
2021 u8 page_offset[0x6];
2022 u8 reserved_23[0x3];
2023 u8 cd_slave_receive[0x1];
2024 u8 cd_slave_send[0x1];
2027 u8 reserved_24[0x3];
2028 u8 min_rnr_nak[0x5];
2029 u8 next_rcv_psn[0x18];
2031 u8 reserved_25[0x8];
2034 u8 reserved_26[0x8];
2041 u8 reserved_27[0x5];
2045 u8 reserved_28[0x8];
2048 u8 hw_sq_wqebb_counter[0x10];
2049 u8 sw_sq_wqebb_counter[0x10];
2051 u8 hw_rq_counter[0x20];
2053 u8 sw_rq_counter[0x20];
2055 u8 reserved_29[0x20];
2057 u8 reserved_30[0xf];
2062 u8 dc_access_key[0x40];
2064 u8 rdma_active[0x1];
2067 u8 reserved_31[0x5];
2068 u8 send_msg_psn[0x18];
2070 u8 reserved_32[0x8];
2071 u8 rcv_msg_psn[0x18];
2077 u8 reserved_33[0x20];
2080 struct mlx5_ifc_roce_addr_layout_bits {
2081 u8 source_l3_address[16][0x8];
2086 u8 source_mac_47_32[0x10];
2088 u8 source_mac_31_0[0x20];
2090 u8 reserved_1[0x14];
2091 u8 roce_l3_type[0x4];
2092 u8 roce_version[0x8];
2094 u8 reserved_2[0x20];
2097 struct mlx5_ifc_rdbc_bits {
2098 u8 reserved_0[0x1c];
2101 u8 reserved_1[0x20];
2110 u8 byte_count[0x20];
2112 u8 reserved_3[0x20];
2114 u8 atomic_resp[32][0x8];
2118 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2119 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2120 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2121 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2124 struct mlx5_ifc_flow_context_bits {
2125 u8 reserved_0[0x20];
2132 u8 reserved_2[0x10];
2136 u8 destination_list_size[0x18];
2139 u8 flow_counter_list_size[0x18];
2141 u8 reserved_5[0x140];
2143 struct mlx5_ifc_fte_match_param_bits match_value;
2145 u8 reserved_6[0x600];
2147 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2151 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2152 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2155 struct mlx5_ifc_xrc_srqc_bits {
2157 u8 log_xrc_srq_size[0x4];
2158 u8 reserved_0[0x18];
2160 u8 wq_signature[0x1];
2164 u8 basic_cyclic_rcv_wqe[0x1];
2165 u8 log_rq_stride[0x3];
2168 u8 page_offset[0x6];
2172 u8 reserved_3[0x20];
2175 u8 log_page_size[0x6];
2176 u8 user_index[0x18];
2178 u8 reserved_5[0x20];
2186 u8 reserved_7[0x40];
2188 u8 db_record_addr_h[0x20];
2190 u8 db_record_addr_l[0x1e];
2193 u8 reserved_9[0x80];
2196 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2197 u8 counter_error_queues[0x20];
2199 u8 total_error_queues[0x20];
2201 u8 send_queue_priority_update_flow[0x20];
2203 u8 reserved_at_60[0x20];
2205 u8 nic_receive_steering_discard[0x40];
2207 u8 receive_discard_vport_down[0x40];
2209 u8 transmit_discard_vport_down[0x40];
2211 u8 reserved_at_140[0xec0];
2214 struct mlx5_ifc_traffic_counter_bits {
2220 struct mlx5_ifc_tisc_bits {
2221 u8 strict_lag_tx_port_affinity[0x1];
2222 u8 reserved_at_1[0x3];
2223 u8 lag_tx_port_affinity[0x04];
2225 u8 reserved_at_8[0x4];
2227 u8 reserved_1[0x10];
2229 u8 reserved_2[0x100];
2232 u8 transport_domain[0x18];
2235 u8 underlay_qpn[0x18];
2237 u8 reserved_5[0x3a0];
2241 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2242 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2246 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2247 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2251 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
2252 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
2253 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
2257 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1,
2258 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2,
2261 struct mlx5_ifc_tirc_bits {
2262 u8 reserved_0[0x20];
2265 u8 reserved_1[0x1c];
2267 u8 reserved_2[0x40];
2270 u8 lro_timeout_period_usecs[0x10];
2271 u8 lro_enable_mask[0x4];
2272 u8 lro_max_msg_sz[0x8];
2274 u8 reserved_4[0x40];
2277 u8 inline_rqn[0x18];
2279 u8 rx_hash_symmetric[0x1];
2281 u8 tunneled_offload_en[0x1];
2283 u8 indirect_table[0x18];
2288 u8 transport_domain[0x18];
2290 u8 rx_hash_toeplitz_key[10][0x20];
2292 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2294 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2296 u8 reserved_9[0x4c0];
2300 MLX5_SRQC_STATE_GOOD = 0x0,
2301 MLX5_SRQC_STATE_ERROR = 0x1,
2304 struct mlx5_ifc_srqc_bits {
2306 u8 log_srq_size[0x4];
2307 u8 reserved_0[0x18];
2309 u8 wq_signature[0x1];
2314 u8 log_rq_stride[0x3];
2317 u8 page_offset[0x6];
2321 u8 reserved_4[0x20];
2324 u8 log_page_size[0x6];
2325 u8 reserved_6[0x18];
2327 u8 reserved_7[0x20];
2335 u8 reserved_9[0x40];
2339 u8 reserved_10[0x80];
2343 MLX5_SQC_STATE_RST = 0x0,
2344 MLX5_SQC_STATE_RDY = 0x1,
2345 MLX5_SQC_STATE_ERR = 0x3,
2348 struct mlx5_ifc_sqc_bits {
2352 u8 flush_in_error_en[0x1];
2353 u8 allow_multi_pkt_send_wqe[0x1];
2354 u8 min_wqe_inline_mode[0x3];
2358 u8 reserved_0[0x12];
2361 u8 user_index[0x18];
2366 u8 reserved_3[0x80];
2368 u8 qos_para_vport_number[0x10];
2369 u8 packet_pacing_rate_limit_index[0x10];
2371 u8 tis_lst_sz[0x10];
2372 u8 reserved_4[0x10];
2374 u8 reserved_5[0x40];
2379 struct mlx5_ifc_wq_bits wq;
2383 MLX5_TSAR_TYPE_DWRR = 0,
2384 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2385 MLX5_TSAR_TYPE_ETS = 2
2388 struct mlx5_ifc_tsar_element_attributes_bits {
2391 u8 reserved_1[0x10];
2394 struct mlx5_ifc_vport_element_attributes_bits {
2395 u8 reserved_0[0x10];
2396 u8 vport_number[0x10];
2399 struct mlx5_ifc_vport_tc_element_attributes_bits {
2400 u8 traffic_class[0x10];
2401 u8 vport_number[0x10];
2404 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2405 u8 reserved_0[0x0C];
2406 u8 traffic_class[0x04];
2407 u8 qos_para_vport_number[0x10];
2411 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2412 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2413 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2414 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2417 struct mlx5_ifc_scheduling_context_bits {
2418 u8 element_type[0x8];
2419 u8 reserved_at_8[0x18];
2421 u8 element_attributes[0x20];
2423 u8 parent_element_id[0x20];
2425 u8 reserved_at_60[0x40];
2429 u8 max_average_bw[0x20];
2431 u8 reserved_at_e0[0x120];
2434 struct mlx5_ifc_rqtc_bits {
2435 u8 reserved_0[0xa0];
2437 u8 reserved_1[0x10];
2438 u8 rqt_max_size[0x10];
2440 u8 reserved_2[0x10];
2441 u8 rqt_actual_size[0x10];
2443 u8 reserved_3[0x6a0];
2445 struct mlx5_ifc_rq_num_bits rq_num[0];
2449 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2450 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2454 MLX5_RQC_STATE_RST = 0x0,
2455 MLX5_RQC_STATE_RDY = 0x1,
2456 MLX5_RQC_STATE_ERR = 0x3,
2460 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
2461 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
2464 struct mlx5_ifc_rqc_bits {
2466 u8 delay_drop_en[0x1];
2467 u8 scatter_fcs[0x1];
2468 u8 vlan_strip_disable[0x1];
2469 u8 mem_rq_type[0x4];
2472 u8 flush_in_error_en[0x1];
2473 u8 reserved_2[0x12];
2476 u8 user_index[0x18];
2481 u8 counter_set_id[0x8];
2482 u8 reserved_5[0x18];
2487 u8 reserved_7[0xe0];
2489 struct mlx5_ifc_wq_bits wq;
2493 MLX5_RMPC_STATE_RDY = 0x1,
2494 MLX5_RMPC_STATE_ERR = 0x3,
2497 struct mlx5_ifc_rmpc_bits {
2500 u8 reserved_1[0x14];
2502 u8 basic_cyclic_rcv_wqe[0x1];
2503 u8 reserved_2[0x1f];
2505 u8 reserved_3[0x140];
2507 struct mlx5_ifc_wq_bits wq;
2511 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2512 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1,
2513 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2,
2516 struct mlx5_ifc_nic_vport_context_bits {
2518 u8 min_wqe_inline_mode[0x3];
2519 u8 reserved_1[0x15];
2520 u8 disable_mc_local_lb[0x1];
2521 u8 disable_uc_local_lb[0x1];
2524 u8 arm_change_event[0x1];
2525 u8 reserved_2[0x1a];
2526 u8 event_on_mtu[0x1];
2527 u8 event_on_promisc_change[0x1];
2528 u8 event_on_vlan_change[0x1];
2529 u8 event_on_mc_address_change[0x1];
2530 u8 event_on_uc_address_change[0x1];
2532 u8 reserved_3[0xe0];
2534 u8 reserved_4[0x10];
2537 u8 system_image_guid[0x40];
2543 u8 reserved_5[0x140];
2545 u8 qkey_violation_counter[0x10];
2546 u8 reserved_6[0x10];
2548 u8 reserved_7[0x420];
2552 u8 promisc_all[0x1];
2554 u8 allowed_list_type[0x3];
2556 u8 allowed_list_size[0xc];
2558 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2560 u8 reserved_10[0x20];
2562 u8 current_uc_mac_address[0][0x40];
2566 MLX5_ACCESS_MODE_PA = 0x0,
2567 MLX5_ACCESS_MODE_MTT = 0x1,
2568 MLX5_ACCESS_MODE_KLM = 0x2,
2571 struct mlx5_ifc_mkc_bits {
2572 u8 reserved_at_0[0x1];
2574 u8 reserved_at_2[0x1];
2575 u8 access_mode_4_2[0x3];
2576 u8 reserved_at_6[0x7];
2577 u8 relaxed_ordering_write[0x1];
2578 u8 reserved_at_e[0x1];
2579 u8 small_fence_on_rdma_read_response[0x1];
2586 u8 access_mode[0x2];
2592 u8 reserved_3[0x20];
2598 u8 expected_sigerr_count[0x1];
2603 u8 start_addr[0x40];
2607 u8 bsf_octword_size[0x20];
2609 u8 reserved_6[0x80];
2611 u8 translations_octword_size[0x20];
2613 u8 reserved_7[0x1b];
2614 u8 log_page_size[0x5];
2616 u8 reserved_8[0x20];
2619 struct mlx5_ifc_pkey_bits {
2620 u8 reserved_0[0x10];
2624 struct mlx5_ifc_array128_auto_bits {
2625 u8 array128_auto[16][0x8];
2629 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0,
2630 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1,
2631 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2,
2635 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1,
2636 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2,
2637 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
2638 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4,
2639 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5,
2640 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6,
2641 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
2645 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0,
2646 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1,
2647 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2,
2651 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1,
2652 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2,
2653 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
2654 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4,
2658 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1,
2659 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2,
2660 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
2661 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4,
2664 struct mlx5_ifc_hca_vport_context_bits {
2665 u8 field_select[0x20];
2667 u8 reserved_0[0xe0];
2669 u8 sm_virt_aware[0x1];
2672 u8 grh_required[0x1];
2674 u8 min_wqe_inline_mode[0x3];
2676 u8 port_physical_state[0x4];
2677 u8 vport_state_policy[0x4];
2679 u8 vport_state[0x4];
2681 u8 reserved_3[0x20];
2683 u8 system_image_guid[0x40];
2691 u8 cap_mask1_field_select[0x20];
2695 u8 cap_mask2_field_select[0x20];
2697 u8 reserved_4[0x80];
2701 u8 init_type_reply[0x4];
2703 u8 subnet_timeout[0x5];
2709 u8 qkey_violation_counter[0x10];
2710 u8 pkey_violation_counter[0x10];
2712 u8 reserved_7[0xca0];
2715 union mlx5_ifc_hca_cap_union_bits {
2716 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2717 struct mlx5_ifc_odp_cap_bits odp_cap;
2718 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2719 struct mlx5_ifc_roce_cap_bits roce_cap;
2720 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2721 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2722 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2723 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2724 struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2725 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2726 struct mlx5_ifc_qos_cap_bits qos_cap;
2727 u8 reserved_0[0x8000];
2731 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2732 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2735 struct mlx5_ifc_flow_table_context_bits {
2738 u8 reserved_at_2[0x2];
2739 u8 table_miss_action[0x4];
2741 u8 reserved_at_10[0x8];
2744 u8 reserved_at_20[0x8];
2745 u8 table_miss_id[0x18];
2747 u8 reserved_at_40[0x8];
2748 u8 lag_master_next_table_id[0x18];
2750 u8 reserved_at_60[0xe0];
2753 struct mlx5_ifc_esw_vport_context_bits {
2755 u8 vport_svlan_strip[0x1];
2756 u8 vport_cvlan_strip[0x1];
2757 u8 vport_svlan_insert[0x1];
2758 u8 vport_cvlan_insert[0x2];
2759 u8 reserved_1[0x18];
2761 u8 reserved_2[0x20];
2770 u8 reserved_3[0x7a0];
2774 MLX5_EQC_STATUS_OK = 0x0,
2775 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2779 MLX5_EQ_STATE_ARMED = 0x9,
2780 MLX5_EQ_STATE_FIRED = 0xa,
2783 struct mlx5_ifc_eqc_bits {
2792 u8 reserved_3[0x20];
2794 u8 reserved_4[0x14];
2795 u8 page_offset[0x6];
2799 u8 log_eq_size[0x5];
2802 u8 reserved_7[0x20];
2804 u8 reserved_8[0x18];
2808 u8 log_page_size[0x5];
2809 u8 reserved_10[0x18];
2811 u8 reserved_11[0x60];
2813 u8 reserved_12[0x8];
2814 u8 consumer_counter[0x18];
2816 u8 reserved_13[0x8];
2817 u8 producer_counter[0x18];
2819 u8 reserved_14[0x80];
2823 MLX5_DCTC_STATE_ACTIVE = 0x0,
2824 MLX5_DCTC_STATE_DRAINING = 0x1,
2825 MLX5_DCTC_STATE_DRAINED = 0x2,
2829 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2830 MLX5_DCTC_CS_RES_NA = 0x1,
2831 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2835 MLX5_DCTC_MTU_256_BYTES = 0x1,
2836 MLX5_DCTC_MTU_512_BYTES = 0x2,
2837 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2838 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2839 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2842 struct mlx5_ifc_dctc_bits {
2845 u8 reserved_1[0x18];
2848 u8 user_index[0x18];
2853 u8 counter_set_id[0x8];
2854 u8 atomic_mode[0x4];
2858 u8 atomic_like_write_en[0x1];
2859 u8 latency_sensitive[0x1];
2866 u8 min_rnr_nak[0x5];
2876 u8 reserved_10[0x4];
2877 u8 flow_label[0x14];
2879 u8 dc_access_key[0x40];
2881 u8 reserved_11[0x5];
2884 u8 pkey_index[0x10];
2886 u8 reserved_12[0x8];
2887 u8 my_addr_index[0x8];
2888 u8 reserved_13[0x8];
2891 u8 dc_access_key_violation_count[0x20];
2893 u8 reserved_14[0x14];
2899 u8 reserved_15[0x40];
2903 MLX5_CQC_STATUS_OK = 0x0,
2904 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2905 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2914 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2915 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2919 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6,
2920 MLX5_CQ_STATE_ARMED = 0x9,
2921 MLX5_CQ_STATE_FIRED = 0xa,
2924 struct mlx5_ifc_cqc_bits {
2930 u8 scqe_break_moderation_en[0x1];
2932 u8 cq_period_mode[0x2];
2933 u8 cqe_compression_en[0x1];
2934 u8 mini_cqe_res_format[0x2];
2938 u8 reserved_3[0x20];
2940 u8 reserved_4[0x14];
2941 u8 page_offset[0x6];
2945 u8 log_cq_size[0x5];
2950 u8 cq_max_count[0x10];
2952 u8 reserved_8[0x18];
2956 u8 log_page_size[0x5];
2957 u8 reserved_10[0x18];
2959 u8 reserved_11[0x20];
2961 u8 reserved_12[0x8];
2962 u8 last_notified_index[0x18];
2964 u8 reserved_13[0x8];
2965 u8 last_solicit_index[0x18];
2967 u8 reserved_14[0x8];
2968 u8 consumer_counter[0x18];
2970 u8 reserved_15[0x8];
2971 u8 producer_counter[0x18];
2973 u8 reserved_16[0x40];
2978 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2979 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2980 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2981 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2982 u8 reserved_0[0x800];
2985 struct mlx5_ifc_query_adapter_param_block_bits {
2986 u8 reserved_0[0xc0];
2989 u8 ieee_vendor_id[0x18];
2991 u8 reserved_2[0x10];
2992 u8 vsd_vendor_id[0x10];
2996 u8 vsd_contd_psid[16][0x8];
2999 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3000 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3001 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3002 u8 reserved_0[0x20];
3005 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3006 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3007 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3008 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3009 u8 reserved_0[0x20];
3012 struct mlx5_ifc_bufferx_reg_bits {
3019 u8 xoff_threshold[0x10];
3020 u8 xon_threshold[0x10];
3023 struct mlx5_ifc_config_item_bits {
3026 u8 header_type[0x2];
3028 u8 default_location[0x1];
3036 u8 reserved_4[0x10];
3040 struct mlx5_ifc_nodnic_port_config_reg_bits {
3041 struct mlx5_ifc_nodnic_event_word_bits event;
3046 u8 promisc_multicast_en[0x1];
3047 u8 reserved_0[0x17];
3048 u8 receive_filter_en[0x5];
3050 u8 reserved_1[0x10];
3055 u8 receive_filters_mgid_mac[64][0x8];
3059 u8 reserved_2[0x10];
3066 u8 completion_address_63_32[0x20];
3068 u8 completion_address_31_12[0x14];
3070 u8 log_cq_size[0x6];
3072 u8 working_buffer_address_63_32[0x20];
3074 u8 working_buffer_address_31_12[0x14];
3077 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3079 u8 pkey_index[0x10];
3082 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3084 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3086 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3088 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3090 u8 reserved_6[0x400];
3093 union mlx5_ifc_event_auto_bits {
3094 struct mlx5_ifc_comp_event_bits comp_event;
3095 struct mlx5_ifc_dct_events_bits dct_events;
3096 struct mlx5_ifc_qp_events_bits qp_events;
3097 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3098 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3099 struct mlx5_ifc_cq_error_bits cq_error;
3100 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3101 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3102 struct mlx5_ifc_gpio_event_bits gpio_event;
3103 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3104 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3105 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3106 struct mlx5_ifc_pages_req_event_bits pages_req_event;
3107 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3108 u8 reserved_0[0xe0];
3111 struct mlx5_ifc_health_buffer_bits {
3112 u8 reserved_0[0x100];
3114 u8 assert_existptr[0x20];
3116 u8 assert_callra[0x20];
3118 u8 reserved_1[0x40];
3120 u8 fw_version[0x20];
3124 u8 reserved_2[0x20];
3126 u8 irisc_index[0x8];
3131 struct mlx5_ifc_register_loopback_control_bits {
3135 u8 reserved_1[0x10];
3137 u8 reserved_2[0x60];
3140 struct mlx5_ifc_lrh_bits {
3152 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3153 u8 reserved_0[0x40];
3155 u8 reserved_1[0x10];
3160 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3161 u8 reserved_0[0x40];
3163 u8 rol_mode_valid[0x1];
3164 u8 wol_mode_valid[0x1];
3169 u8 reserved_2[0x7a0];
3172 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3173 u8 virtual_mac_en[0x1];
3175 u8 reserved_0[0x1e];
3177 u8 reserved_1[0x40];
3179 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3181 u8 reserved_2[0x760];
3184 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3185 u8 virtual_mac_en[0x1];
3187 u8 reserved_0[0x1e];
3189 struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3191 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3193 u8 reserved_1[0x760];
3196 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3197 struct mlx5_ifc_fw_version_bits fw_version;
3199 u8 reserved_0[0x10];
3200 u8 hash_signature[0x10];
3204 u8 reserved_1[0x6e0];
3207 struct mlx5_ifc_icmd_query_cap_in_bits {
3208 u8 reserved_0[0x10];
3209 u8 capability_group[0x10];
3212 struct mlx5_ifc_icmd_query_cap_general_bits {
3214 u8 fw_info_psid[0x1];
3215 u8 reserved_0[0x1e];
3217 u8 reserved_1[0x16];
3230 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3232 u8 reserved_0[0x18];
3234 u8 reserved_1[0x7e0];
3237 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3239 u8 reserved_0[0x18];
3241 u8 reserved_1[0x7e0];
3244 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3245 u8 address_hi[0x20];
3247 u8 address_lo[0x20];
3249 u8 reserved_0[0x7c0];
3252 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3253 u8 reserved_0[0x20];
3255 u8 address_hi[0x20];
3257 u8 address_lo[0x20];
3259 u8 reserved_1[0x7a0];
3262 struct mlx5_ifc_icmd_access_reg_out_bits {
3263 u8 reserved_0[0x11];
3267 u8 register_id[0x10];
3268 u8 reserved_2[0x10];
3270 u8 reserved_3[0x40];
3274 u8 reserved_5[0x10];
3276 u8 register_data[0][0x20];
3280 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1,
3281 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2,
3284 struct mlx5_ifc_icmd_access_reg_in_bits {
3287 u8 reserved_0[0x10];
3289 u8 register_id[0x10];
3294 u8 reserved_2[0x40];
3298 u8 reserved_3[0x10];
3300 u8 register_data[0][0x20];
3304 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3305 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3308 struct mlx5_ifc_teardown_hca_out_bits {
3310 u8 reserved_0[0x18];
3314 u8 reserved_1[0x3f];
3320 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3321 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3322 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3325 struct mlx5_ifc_teardown_hca_in_bits {
3327 u8 reserved_0[0x10];
3329 u8 reserved_1[0x10];
3332 u8 reserved_2[0x10];
3335 u8 reserved_3[0x20];
3338 struct mlx5_ifc_set_delay_drop_params_out_bits {
3340 u8 reserved_at_8[0x18];
3344 u8 reserved_at_40[0x40];
3347 struct mlx5_ifc_set_delay_drop_params_in_bits {
3349 u8 reserved_at_10[0x10];
3351 u8 reserved_at_20[0x10];
3354 u8 reserved_at_40[0x20];
3356 u8 reserved_at_60[0x10];
3357 u8 delay_drop_timeout[0x10];
3360 struct mlx5_ifc_query_delay_drop_params_out_bits {
3362 u8 reserved_at_8[0x18];
3366 u8 reserved_at_40[0x20];
3368 u8 reserved_at_60[0x10];
3369 u8 delay_drop_timeout[0x10];
3372 struct mlx5_ifc_query_delay_drop_params_in_bits {
3374 u8 reserved_at_10[0x10];
3376 u8 reserved_at_20[0x10];
3379 u8 reserved_at_40[0x40];
3382 struct mlx5_ifc_suspend_qp_out_bits {
3384 u8 reserved_0[0x18];
3388 u8 reserved_1[0x40];
3391 struct mlx5_ifc_suspend_qp_in_bits {
3393 u8 reserved_0[0x10];
3395 u8 reserved_1[0x10];
3401 u8 reserved_3[0x20];
3404 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3406 u8 reserved_0[0x18];
3410 u8 reserved_1[0x40];
3413 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3415 u8 reserved_0[0x10];
3417 u8 reserved_1[0x10];
3423 u8 reserved_3[0x20];
3425 u8 opt_param_mask[0x20];
3427 u8 reserved_4[0x20];
3429 struct mlx5_ifc_qpc_bits qpc;
3431 u8 reserved_5[0x80];
3434 struct mlx5_ifc_sqd2rts_qp_out_bits {
3436 u8 reserved_0[0x18];
3440 u8 reserved_1[0x40];
3443 struct mlx5_ifc_sqd2rts_qp_in_bits {
3445 u8 reserved_0[0x10];
3447 u8 reserved_1[0x10];
3453 u8 reserved_3[0x20];
3455 u8 opt_param_mask[0x20];
3457 u8 reserved_4[0x20];
3459 struct mlx5_ifc_qpc_bits qpc;
3461 u8 reserved_5[0x80];
3464 struct mlx5_ifc_set_wol_rol_out_bits {
3466 u8 reserved_0[0x18];
3470 u8 reserved_1[0x40];
3473 struct mlx5_ifc_set_wol_rol_in_bits {
3475 u8 reserved_0[0x10];
3477 u8 reserved_1[0x10];
3480 u8 rol_mode_valid[0x1];
3481 u8 wol_mode_valid[0x1];
3486 u8 reserved_3[0x20];
3489 struct mlx5_ifc_set_roce_address_out_bits {
3491 u8 reserved_0[0x18];
3495 u8 reserved_1[0x40];
3498 struct mlx5_ifc_set_roce_address_in_bits {
3500 u8 reserved_0[0x10];
3502 u8 reserved_1[0x10];
3505 u8 roce_address_index[0x10];
3506 u8 reserved_2[0x10];
3508 u8 reserved_3[0x20];
3510 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3513 struct mlx5_ifc_set_rdb_out_bits {
3515 u8 reserved_0[0x18];
3519 u8 reserved_1[0x40];
3522 struct mlx5_ifc_set_rdb_in_bits {
3524 u8 reserved_0[0x10];
3526 u8 reserved_1[0x10];
3532 u8 reserved_3[0x18];
3533 u8 rdb_list_size[0x8];
3535 struct mlx5_ifc_rdbc_bits rdb_context[0];
3538 struct mlx5_ifc_set_mad_demux_out_bits {
3540 u8 reserved_0[0x18];
3544 u8 reserved_1[0x40];
3548 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3549 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3552 struct mlx5_ifc_set_mad_demux_in_bits {
3554 u8 reserved_0[0x10];
3556 u8 reserved_1[0x10];
3559 u8 reserved_2[0x20];
3563 u8 reserved_4[0x18];
3566 struct mlx5_ifc_set_l2_table_entry_out_bits {
3568 u8 reserved_0[0x18];
3572 u8 reserved_1[0x40];
3575 struct mlx5_ifc_set_l2_table_entry_in_bits {
3577 u8 reserved_0[0x10];
3579 u8 reserved_1[0x10];
3582 u8 reserved_2[0x60];
3585 u8 table_index[0x18];
3587 u8 reserved_4[0x20];
3589 u8 reserved_5[0x13];
3593 struct mlx5_ifc_mac_address_layout_bits mac_address;
3595 u8 reserved_6[0xc0];
3598 struct mlx5_ifc_set_issi_out_bits {
3600 u8 reserved_0[0x18];
3604 u8 reserved_1[0x40];
3607 struct mlx5_ifc_set_issi_in_bits {
3609 u8 reserved_0[0x10];
3611 u8 reserved_1[0x10];
3614 u8 reserved_2[0x10];
3615 u8 current_issi[0x10];
3617 u8 reserved_3[0x20];
3620 struct mlx5_ifc_set_hca_cap_out_bits {
3622 u8 reserved_0[0x18];
3626 u8 reserved_1[0x40];
3629 struct mlx5_ifc_set_hca_cap_in_bits {
3631 u8 reserved_0[0x10];
3633 u8 reserved_1[0x10];
3636 u8 reserved_2[0x40];
3638 union mlx5_ifc_hca_cap_union_bits capability;
3642 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3643 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3644 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3645 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3648 struct mlx5_ifc_set_flow_table_root_out_bits {
3650 u8 reserved_0[0x18];
3654 u8 reserved_1[0x40];
3657 struct mlx5_ifc_set_flow_table_root_in_bits {
3659 u8 reserved_0[0x10];
3661 u8 reserved_1[0x10];
3664 u8 other_vport[0x1];
3666 u8 vport_number[0x10];
3668 u8 reserved_3[0x20];
3671 u8 reserved_4[0x18];
3677 u8 underlay_qpn[0x18];
3679 u8 reserved_7[0x120];
3682 struct mlx5_ifc_set_fte_out_bits {
3684 u8 reserved_0[0x18];
3688 u8 reserved_1[0x40];
3691 struct mlx5_ifc_set_fte_in_bits {
3693 u8 reserved_0[0x10];
3695 u8 reserved_1[0x10];
3698 u8 other_vport[0x1];
3700 u8 vport_number[0x10];
3702 u8 reserved_3[0x20];
3705 u8 reserved_4[0x18];
3710 u8 reserved_6[0x18];
3711 u8 modify_enable_mask[0x8];
3713 u8 reserved_7[0x20];
3715 u8 flow_index[0x20];
3717 u8 reserved_8[0xe0];
3719 struct mlx5_ifc_flow_context_bits flow_context;
3722 struct mlx5_ifc_set_driver_version_out_bits {
3724 u8 reserved_0[0x18];
3728 u8 reserved_1[0x40];
3731 struct mlx5_ifc_set_driver_version_in_bits {
3733 u8 reserved_0[0x10];
3735 u8 reserved_1[0x10];
3738 u8 reserved_2[0x40];
3740 u8 driver_version[64][0x8];
3743 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3745 u8 reserved_0[0x18];
3749 u8 reserved_1[0x40];
3752 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3754 u8 reserved_0[0x10];
3756 u8 reserved_1[0x10];
3760 u8 reserved_2[0x1f];
3762 u8 reserved_3[0x160];
3764 struct mlx5_ifc_cmd_pas_bits pas;
3767 struct mlx5_ifc_set_burst_size_out_bits {
3769 u8 reserved_0[0x18];
3773 u8 reserved_1[0x40];
3776 struct mlx5_ifc_set_burst_size_in_bits {
3778 u8 reserved_0[0x10];
3780 u8 reserved_1[0x10];
3783 u8 reserved_2[0x20];
3786 u8 device_burst_size[0x17];
3789 struct mlx5_ifc_rts2rts_qp_out_bits {
3791 u8 reserved_0[0x18];
3795 u8 reserved_1[0x40];
3798 struct mlx5_ifc_rts2rts_qp_in_bits {
3800 u8 reserved_0[0x10];
3802 u8 reserved_1[0x10];
3808 u8 reserved_3[0x20];
3810 u8 opt_param_mask[0x20];
3812 u8 reserved_4[0x20];
3814 struct mlx5_ifc_qpc_bits qpc;
3816 u8 reserved_5[0x80];
3819 struct mlx5_ifc_rtr2rts_qp_out_bits {
3821 u8 reserved_0[0x18];
3825 u8 reserved_1[0x40];
3828 struct mlx5_ifc_rtr2rts_qp_in_bits {
3830 u8 reserved_0[0x10];
3832 u8 reserved_1[0x10];
3838 u8 reserved_3[0x20];
3840 u8 opt_param_mask[0x20];
3842 u8 reserved_4[0x20];
3844 struct mlx5_ifc_qpc_bits qpc;
3846 u8 reserved_5[0x80];
3849 struct mlx5_ifc_rst2init_qp_out_bits {
3851 u8 reserved_0[0x18];
3855 u8 reserved_1[0x40];
3858 struct mlx5_ifc_rst2init_qp_in_bits {
3860 u8 reserved_0[0x10];
3862 u8 reserved_1[0x10];
3868 u8 reserved_3[0x20];
3870 u8 opt_param_mask[0x20];
3872 u8 reserved_4[0x20];
3874 struct mlx5_ifc_qpc_bits qpc;
3876 u8 reserved_5[0x80];
3879 struct mlx5_ifc_resume_qp_out_bits {
3881 u8 reserved_0[0x18];
3885 u8 reserved_1[0x40];
3888 struct mlx5_ifc_resume_qp_in_bits {
3890 u8 reserved_0[0x10];
3892 u8 reserved_1[0x10];
3898 u8 reserved_3[0x20];
3901 struct mlx5_ifc_query_xrc_srq_out_bits {
3903 u8 reserved_0[0x18];
3907 u8 reserved_1[0x40];
3909 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3911 u8 reserved_2[0x600];
3916 struct mlx5_ifc_query_xrc_srq_in_bits {
3918 u8 reserved_0[0x10];
3920 u8 reserved_1[0x10];
3926 u8 reserved_3[0x20];
3929 struct mlx5_ifc_query_wol_rol_out_bits {
3931 u8 reserved_0[0x18];
3935 u8 reserved_1[0x10];
3939 u8 reserved_2[0x20];
3942 struct mlx5_ifc_query_wol_rol_in_bits {
3944 u8 reserved_0[0x10];
3946 u8 reserved_1[0x10];
3949 u8 reserved_2[0x40];
3953 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3954 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3957 struct mlx5_ifc_query_vport_state_out_bits {
3959 u8 reserved_0[0x18];
3963 u8 reserved_1[0x20];
3965 u8 reserved_2[0x18];
3966 u8 admin_state[0x4];
3971 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3972 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3973 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
3976 struct mlx5_ifc_query_vport_state_in_bits {
3978 u8 reserved_0[0x10];
3980 u8 reserved_1[0x10];
3983 u8 other_vport[0x1];
3985 u8 vport_number[0x10];
3987 u8 reserved_3[0x20];
3990 struct mlx5_ifc_query_vnic_env_out_bits {
3992 u8 reserved_at_8[0x18];
3996 u8 reserved_at_40[0x40];
3998 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4002 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4005 struct mlx5_ifc_query_vnic_env_in_bits {
4007 u8 reserved_at_10[0x10];
4009 u8 reserved_at_20[0x10];
4012 u8 other_vport[0x1];
4013 u8 reserved_at_41[0xf];
4014 u8 vport_number[0x10];
4016 u8 reserved_at_60[0x20];
4019 struct mlx5_ifc_query_vport_counter_out_bits {
4021 u8 reserved_0[0x18];
4025 u8 reserved_1[0x40];
4027 struct mlx5_ifc_traffic_counter_bits received_errors;
4029 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4031 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4033 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4035 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4037 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4039 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4041 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4043 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4045 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4047 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4049 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4051 u8 reserved_2[0xa00];
4055 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4058 struct mlx5_ifc_query_vport_counter_in_bits {
4060 u8 reserved_0[0x10];
4062 u8 reserved_1[0x10];
4065 u8 other_vport[0x1];
4068 u8 vport_number[0x10];
4070 u8 reserved_3[0x60];
4073 u8 reserved_4[0x1f];
4075 u8 reserved_5[0x20];
4078 struct mlx5_ifc_query_tis_out_bits {
4080 u8 reserved_0[0x18];
4084 u8 reserved_1[0x40];
4086 struct mlx5_ifc_tisc_bits tis_context;
4089 struct mlx5_ifc_query_tis_in_bits {
4091 u8 reserved_0[0x10];
4093 u8 reserved_1[0x10];
4099 u8 reserved_3[0x20];
4102 struct mlx5_ifc_query_tir_out_bits {
4104 u8 reserved_0[0x18];
4108 u8 reserved_1[0xc0];
4110 struct mlx5_ifc_tirc_bits tir_context;
4113 struct mlx5_ifc_query_tir_in_bits {
4115 u8 reserved_0[0x10];
4117 u8 reserved_1[0x10];
4123 u8 reserved_3[0x20];
4126 struct mlx5_ifc_query_srq_out_bits {
4128 u8 reserved_0[0x18];
4132 u8 reserved_1[0x40];
4134 struct mlx5_ifc_srqc_bits srq_context_entry;
4136 u8 reserved_2[0x600];
4141 struct mlx5_ifc_query_srq_in_bits {
4143 u8 reserved_0[0x10];
4145 u8 reserved_1[0x10];
4151 u8 reserved_3[0x20];
4154 struct mlx5_ifc_query_sq_out_bits {
4156 u8 reserved_0[0x18];
4160 u8 reserved_1[0xc0];
4162 struct mlx5_ifc_sqc_bits sq_context;
4165 struct mlx5_ifc_query_sq_in_bits {
4167 u8 reserved_0[0x10];
4169 u8 reserved_1[0x10];
4175 u8 reserved_3[0x20];
4178 struct mlx5_ifc_query_special_contexts_out_bits {
4180 u8 reserved_0[0x18];
4184 u8 dump_fill_mkey[0x20];
4189 struct mlx5_ifc_query_special_contexts_in_bits {
4191 u8 reserved_0[0x10];
4193 u8 reserved_1[0x10];
4196 u8 reserved_2[0x40];
4199 struct mlx5_ifc_query_scheduling_element_out_bits {
4201 u8 reserved_at_8[0x18];
4205 u8 reserved_at_40[0xc0];
4207 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4209 u8 reserved_at_300[0x100];
4213 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4216 struct mlx5_ifc_query_scheduling_element_in_bits {
4218 u8 reserved_at_10[0x10];
4220 u8 reserved_at_20[0x10];
4223 u8 scheduling_hierarchy[0x8];
4224 u8 reserved_at_48[0x18];
4226 u8 scheduling_element_id[0x20];
4228 u8 reserved_at_80[0x180];
4231 struct mlx5_ifc_query_rqt_out_bits {
4233 u8 reserved_0[0x18];
4237 u8 reserved_1[0xc0];
4239 struct mlx5_ifc_rqtc_bits rqt_context;
4242 struct mlx5_ifc_query_rqt_in_bits {
4244 u8 reserved_0[0x10];
4246 u8 reserved_1[0x10];
4252 u8 reserved_3[0x20];
4255 struct mlx5_ifc_query_rq_out_bits {
4257 u8 reserved_0[0x18];
4261 u8 reserved_1[0xc0];
4263 struct mlx5_ifc_rqc_bits rq_context;
4266 struct mlx5_ifc_query_rq_in_bits {
4268 u8 reserved_0[0x10];
4270 u8 reserved_1[0x10];
4276 u8 reserved_3[0x20];
4279 struct mlx5_ifc_query_roce_address_out_bits {
4281 u8 reserved_0[0x18];
4285 u8 reserved_1[0x40];
4287 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4290 struct mlx5_ifc_query_roce_address_in_bits {
4292 u8 reserved_0[0x10];
4294 u8 reserved_1[0x10];
4297 u8 roce_address_index[0x10];
4298 u8 reserved_2[0x10];
4300 u8 reserved_3[0x20];
4303 struct mlx5_ifc_query_rmp_out_bits {
4305 u8 reserved_0[0x18];
4309 u8 reserved_1[0xc0];
4311 struct mlx5_ifc_rmpc_bits rmp_context;
4314 struct mlx5_ifc_query_rmp_in_bits {
4316 u8 reserved_0[0x10];
4318 u8 reserved_1[0x10];
4324 u8 reserved_3[0x20];
4327 struct mlx5_ifc_query_rdb_out_bits {
4329 u8 reserved_0[0x18];
4333 u8 reserved_1[0x20];
4335 u8 reserved_2[0x18];
4336 u8 rdb_list_size[0x8];
4338 struct mlx5_ifc_rdbc_bits rdb_context[0];
4341 struct mlx5_ifc_query_rdb_in_bits {
4343 u8 reserved_0[0x10];
4345 u8 reserved_1[0x10];
4351 u8 reserved_3[0x20];
4354 struct mlx5_ifc_query_qp_out_bits {
4356 u8 reserved_0[0x18];
4360 u8 reserved_1[0x40];
4362 u8 opt_param_mask[0x20];
4364 u8 reserved_2[0x20];
4366 struct mlx5_ifc_qpc_bits qpc;
4368 u8 reserved_3[0x80];
4373 struct mlx5_ifc_query_qp_in_bits {
4375 u8 reserved_0[0x10];
4377 u8 reserved_1[0x10];
4383 u8 reserved_3[0x20];
4386 struct mlx5_ifc_query_q_counter_out_bits {
4388 u8 reserved_0[0x18];
4392 u8 reserved_1[0x40];
4394 u8 rx_write_requests[0x20];
4396 u8 reserved_2[0x20];
4398 u8 rx_read_requests[0x20];
4400 u8 reserved_3[0x20];
4402 u8 rx_atomic_requests[0x20];
4404 u8 reserved_4[0x20];
4406 u8 rx_dct_connect[0x20];
4408 u8 reserved_5[0x20];
4410 u8 out_of_buffer[0x20];
4412 u8 reserved_7[0x20];
4414 u8 out_of_sequence[0x20];
4416 u8 reserved_8[0x20];
4418 u8 duplicate_request[0x20];
4420 u8 reserved_9[0x20];
4422 u8 rnr_nak_retry_err[0x20];
4424 u8 reserved_10[0x20];
4426 u8 packet_seq_err[0x20];
4428 u8 reserved_11[0x20];
4430 u8 implied_nak_seq_err[0x20];
4432 u8 reserved_12[0x20];
4434 u8 local_ack_timeout_err[0x20];
4436 u8 reserved_13[0x20];
4438 u8 resp_rnr_nak[0x20];
4440 u8 reserved_14[0x20];
4442 u8 req_rnr_retries_exceeded[0x20];
4444 u8 reserved_15[0x460];
4447 struct mlx5_ifc_query_q_counter_in_bits {
4449 u8 reserved_0[0x10];
4451 u8 reserved_1[0x10];
4454 u8 reserved_2[0x80];
4457 u8 reserved_3[0x1f];
4459 u8 reserved_4[0x18];
4460 u8 counter_set_id[0x8];
4463 struct mlx5_ifc_query_pages_out_bits {
4465 u8 reserved_0[0x18];
4469 u8 reserved_1[0x10];
4470 u8 function_id[0x10];
4476 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4477 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4478 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4481 struct mlx5_ifc_query_pages_in_bits {
4483 u8 reserved_0[0x10];
4485 u8 reserved_1[0x10];
4488 u8 reserved_2[0x10];
4489 u8 function_id[0x10];
4491 u8 reserved_3[0x20];
4494 struct mlx5_ifc_query_nic_vport_context_out_bits {
4496 u8 reserved_0[0x18];
4500 u8 reserved_1[0x40];
4502 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4505 struct mlx5_ifc_query_nic_vport_context_in_bits {
4507 u8 reserved_0[0x10];
4509 u8 reserved_1[0x10];
4512 u8 other_vport[0x1];
4514 u8 vport_number[0x10];
4517 u8 allowed_list_type[0x3];
4518 u8 reserved_4[0x18];
4521 struct mlx5_ifc_query_mkey_out_bits {
4523 u8 reserved_0[0x18];
4527 u8 reserved_1[0x40];
4529 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4531 u8 reserved_2[0x600];
4533 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4535 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4538 struct mlx5_ifc_query_mkey_in_bits {
4540 u8 reserved_0[0x10];
4542 u8 reserved_1[0x10];
4546 u8 mkey_index[0x18];
4549 u8 reserved_3[0x1f];
4552 struct mlx5_ifc_query_mad_demux_out_bits {
4554 u8 reserved_0[0x18];
4558 u8 reserved_1[0x40];
4560 u8 mad_dumux_parameters_block[0x20];
4563 struct mlx5_ifc_query_mad_demux_in_bits {
4565 u8 reserved_0[0x10];
4567 u8 reserved_1[0x10];
4570 u8 reserved_2[0x40];
4573 struct mlx5_ifc_query_l2_table_entry_out_bits {
4575 u8 reserved_0[0x18];
4579 u8 reserved_1[0xa0];
4581 u8 reserved_2[0x13];
4585 struct mlx5_ifc_mac_address_layout_bits mac_address;
4587 u8 reserved_3[0xc0];
4590 struct mlx5_ifc_query_l2_table_entry_in_bits {
4592 u8 reserved_0[0x10];
4594 u8 reserved_1[0x10];
4597 u8 reserved_2[0x60];
4600 u8 table_index[0x18];
4602 u8 reserved_4[0x140];
4605 struct mlx5_ifc_query_issi_out_bits {
4607 u8 reserved_0[0x18];
4611 u8 reserved_1[0x10];
4612 u8 current_issi[0x10];
4614 u8 reserved_2[0xa0];
4616 u8 supported_issi_reserved[76][0x8];
4617 u8 supported_issi_dw0[0x20];
4620 struct mlx5_ifc_query_issi_in_bits {
4622 u8 reserved_0[0x10];
4624 u8 reserved_1[0x10];
4627 u8 reserved_2[0x40];
4630 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4632 u8 reserved_0[0x18];
4636 u8 reserved_1[0x40];
4638 struct mlx5_ifc_pkey_bits pkey[0];
4641 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4643 u8 reserved_0[0x10];
4645 u8 reserved_1[0x10];
4648 u8 other_vport[0x1];
4651 u8 vport_number[0x10];
4653 u8 reserved_3[0x10];
4654 u8 pkey_index[0x10];
4657 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4659 u8 reserved_0[0x18];
4663 u8 reserved_1[0x20];
4666 u8 reserved_2[0x10];
4668 struct mlx5_ifc_array128_auto_bits gid[0];
4671 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4673 u8 reserved_0[0x10];
4675 u8 reserved_1[0x10];
4678 u8 other_vport[0x1];
4681 u8 vport_number[0x10];
4683 u8 reserved_3[0x10];
4687 struct mlx5_ifc_query_hca_vport_context_out_bits {
4689 u8 reserved_0[0x18];
4693 u8 reserved_1[0x40];
4695 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4698 struct mlx5_ifc_query_hca_vport_context_in_bits {
4700 u8 reserved_0[0x10];
4702 u8 reserved_1[0x10];
4705 u8 other_vport[0x1];
4708 u8 vport_number[0x10];
4710 u8 reserved_3[0x20];
4713 struct mlx5_ifc_query_hca_cap_out_bits {
4715 u8 reserved_0[0x18];
4719 u8 reserved_1[0x40];
4721 union mlx5_ifc_hca_cap_union_bits capability;
4724 struct mlx5_ifc_query_hca_cap_in_bits {
4726 u8 reserved_0[0x10];
4728 u8 reserved_1[0x10];
4731 u8 reserved_2[0x40];
4734 struct mlx5_ifc_query_flow_table_out_bits {
4736 u8 reserved_at_8[0x18];
4740 u8 reserved_at_40[0x80];
4742 struct mlx5_ifc_flow_table_context_bits flow_table_context;
4745 struct mlx5_ifc_query_flow_table_in_bits {
4747 u8 reserved_0[0x10];
4749 u8 reserved_1[0x10];
4752 u8 other_vport[0x1];
4754 u8 vport_number[0x10];
4756 u8 reserved_3[0x20];
4759 u8 reserved_4[0x18];
4764 u8 reserved_6[0x140];
4767 struct mlx5_ifc_query_fte_out_bits {
4769 u8 reserved_0[0x18];
4773 u8 reserved_1[0x1c0];
4775 struct mlx5_ifc_flow_context_bits flow_context;
4778 struct mlx5_ifc_query_fte_in_bits {
4780 u8 reserved_0[0x10];
4782 u8 reserved_1[0x10];
4785 u8 other_vport[0x1];
4787 u8 vport_number[0x10];
4789 u8 reserved_3[0x20];
4792 u8 reserved_4[0x18];
4797 u8 reserved_6[0x40];
4799 u8 flow_index[0x20];
4801 u8 reserved_7[0xe0];
4805 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4806 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4807 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4810 struct mlx5_ifc_query_flow_group_out_bits {
4812 u8 reserved_0[0x18];
4816 u8 reserved_1[0xa0];
4818 u8 start_flow_index[0x20];
4820 u8 reserved_2[0x20];
4822 u8 end_flow_index[0x20];
4824 u8 reserved_3[0xa0];
4826 u8 reserved_4[0x18];
4827 u8 match_criteria_enable[0x8];
4829 struct mlx5_ifc_fte_match_param_bits match_criteria;
4831 u8 reserved_5[0xe00];
4834 struct mlx5_ifc_query_flow_group_in_bits {
4836 u8 reserved_0[0x10];
4838 u8 reserved_1[0x10];
4841 u8 other_vport[0x1];
4843 u8 vport_number[0x10];
4845 u8 reserved_3[0x20];
4848 u8 reserved_4[0x18];
4855 u8 reserved_6[0x120];
4858 struct mlx5_ifc_query_flow_counter_out_bits {
4860 u8 reserved_at_8[0x18];
4864 u8 reserved_at_40[0x40];
4866 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4869 struct mlx5_ifc_query_flow_counter_in_bits {
4871 u8 reserved_at_10[0x10];
4873 u8 reserved_at_20[0x10];
4876 u8 reserved_at_40[0x80];
4879 u8 reserved_at_c1[0xf];
4880 u8 num_of_counters[0x10];
4882 u8 reserved_at_e0[0x10];
4883 u8 flow_counter_id[0x10];
4886 struct mlx5_ifc_query_esw_vport_context_out_bits {
4888 u8 reserved_0[0x18];
4892 u8 reserved_1[0x40];
4894 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4897 struct mlx5_ifc_query_esw_vport_context_in_bits {
4899 u8 reserved_0[0x10];
4901 u8 reserved_1[0x10];
4904 u8 other_vport[0x1];
4906 u8 vport_number[0x10];
4908 u8 reserved_3[0x20];
4911 struct mlx5_ifc_query_eq_out_bits {
4913 u8 reserved_0[0x18];
4917 u8 reserved_1[0x40];
4919 struct mlx5_ifc_eqc_bits eq_context_entry;
4921 u8 reserved_2[0x40];
4923 u8 event_bitmask[0x40];
4925 u8 reserved_3[0x580];
4930 struct mlx5_ifc_query_eq_in_bits {
4932 u8 reserved_0[0x10];
4934 u8 reserved_1[0x10];
4937 u8 reserved_2[0x18];
4940 u8 reserved_3[0x20];
4943 struct mlx5_ifc_query_dct_out_bits {
4945 u8 reserved_0[0x18];
4949 u8 reserved_1[0x40];
4951 struct mlx5_ifc_dctc_bits dct_context_entry;
4953 u8 reserved_2[0x180];
4956 struct mlx5_ifc_query_dct_in_bits {
4958 u8 reserved_0[0x10];
4960 u8 reserved_1[0x10];
4966 u8 reserved_3[0x20];
4969 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4971 u8 reserved_0[0x18];
4976 u8 reserved_1[0x1f];
4978 u8 reserved_2[0x160];
4980 struct mlx5_ifc_cmd_pas_bits pas;
4983 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4985 u8 reserved_0[0x10];
4987 u8 reserved_1[0x10];
4990 u8 reserved_2[0x40];
4993 struct mlx5_ifc_query_cq_out_bits {
4995 u8 reserved_0[0x18];
4999 u8 reserved_1[0x40];
5001 struct mlx5_ifc_cqc_bits cq_context;
5003 u8 reserved_2[0x600];
5008 struct mlx5_ifc_query_cq_in_bits {
5010 u8 reserved_0[0x10];
5012 u8 reserved_1[0x10];
5018 u8 reserved_3[0x20];
5021 struct mlx5_ifc_query_cong_status_out_bits {
5023 u8 reserved_0[0x18];
5027 u8 reserved_1[0x20];
5031 u8 reserved_2[0x1e];
5034 struct mlx5_ifc_query_cong_status_in_bits {
5036 u8 reserved_0[0x10];
5038 u8 reserved_1[0x10];
5041 u8 reserved_2[0x18];
5043 u8 cong_protocol[0x4];
5045 u8 reserved_3[0x20];
5048 struct mlx5_ifc_query_cong_statistics_out_bits {
5050 u8 reserved_0[0x18];
5054 u8 reserved_1[0x40];
5056 u8 rp_cur_flows[0x20];
5060 u8 rp_cnp_ignored_high[0x20];
5062 u8 rp_cnp_ignored_low[0x20];
5064 u8 rp_cnp_handled_high[0x20];
5066 u8 rp_cnp_handled_low[0x20];
5068 u8 reserved_2[0x100];
5070 u8 time_stamp_high[0x20];
5072 u8 time_stamp_low[0x20];
5074 u8 accumulators_period[0x20];
5076 u8 np_ecn_marked_roce_packets_high[0x20];
5078 u8 np_ecn_marked_roce_packets_low[0x20];
5080 u8 np_cnp_sent_high[0x20];
5082 u8 np_cnp_sent_low[0x20];
5084 u8 reserved_3[0x560];
5087 struct mlx5_ifc_query_cong_statistics_in_bits {
5089 u8 reserved_0[0x10];
5091 u8 reserved_1[0x10];
5095 u8 reserved_2[0x1f];
5097 u8 reserved_3[0x20];
5100 struct mlx5_ifc_query_cong_params_out_bits {
5102 u8 reserved_0[0x18];
5106 u8 reserved_1[0x40];
5108 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5111 struct mlx5_ifc_query_cong_params_in_bits {
5113 u8 reserved_0[0x10];
5115 u8 reserved_1[0x10];
5118 u8 reserved_2[0x1c];
5119 u8 cong_protocol[0x4];
5121 u8 reserved_3[0x20];
5124 struct mlx5_ifc_query_burst_size_out_bits {
5126 u8 reserved_0[0x18];
5130 u8 reserved_1[0x20];
5133 u8 device_burst_size[0x17];
5136 struct mlx5_ifc_query_burst_size_in_bits {
5138 u8 reserved_0[0x10];
5140 u8 reserved_1[0x10];
5143 u8 reserved_2[0x40];
5146 struct mlx5_ifc_query_adapter_out_bits {
5148 u8 reserved_0[0x18];
5152 u8 reserved_1[0x40];
5154 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5157 struct mlx5_ifc_query_adapter_in_bits {
5159 u8 reserved_0[0x10];
5161 u8 reserved_1[0x10];
5164 u8 reserved_2[0x40];
5167 struct mlx5_ifc_qp_2rst_out_bits {
5169 u8 reserved_0[0x18];
5173 u8 reserved_1[0x40];
5176 struct mlx5_ifc_qp_2rst_in_bits {
5178 u8 reserved_0[0x10];
5180 u8 reserved_1[0x10];
5186 u8 reserved_3[0x20];
5189 struct mlx5_ifc_qp_2err_out_bits {
5191 u8 reserved_0[0x18];
5195 u8 reserved_1[0x40];
5198 struct mlx5_ifc_qp_2err_in_bits {
5200 u8 reserved_0[0x10];
5202 u8 reserved_1[0x10];
5208 u8 reserved_3[0x20];
5211 struct mlx5_ifc_para_vport_element_bits {
5212 u8 reserved_at_0[0xc];
5213 u8 traffic_class[0x4];
5214 u8 qos_para_vport_number[0x10];
5217 struct mlx5_ifc_page_fault_resume_out_bits {
5219 u8 reserved_0[0x18];
5223 u8 reserved_1[0x40];
5226 struct mlx5_ifc_page_fault_resume_in_bits {
5228 u8 reserved_0[0x10];
5230 u8 reserved_1[0x10];
5240 u8 reserved_3[0x20];
5243 struct mlx5_ifc_nop_out_bits {
5245 u8 reserved_0[0x18];
5249 u8 reserved_1[0x40];
5252 struct mlx5_ifc_nop_in_bits {
5254 u8 reserved_0[0x10];
5256 u8 reserved_1[0x10];
5259 u8 reserved_2[0x40];
5262 struct mlx5_ifc_modify_vport_state_out_bits {
5264 u8 reserved_0[0x18];
5268 u8 reserved_1[0x40];
5272 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0,
5273 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
5274 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
5278 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0,
5279 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1,
5280 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2,
5283 struct mlx5_ifc_modify_vport_state_in_bits {
5285 u8 reserved_0[0x10];
5287 u8 reserved_1[0x10];
5290 u8 other_vport[0x1];
5292 u8 vport_number[0x10];
5294 u8 reserved_3[0x18];
5295 u8 admin_state[0x4];
5299 struct mlx5_ifc_modify_tis_out_bits {
5301 u8 reserved_0[0x18];
5305 u8 reserved_1[0x40];
5308 struct mlx5_ifc_modify_tis_bitmask_bits {
5309 u8 reserved_at_0[0x20];
5311 u8 reserved_at_20[0x1d];
5312 u8 lag_tx_port_affinity[0x1];
5313 u8 strict_lag_tx_port_affinity[0x1];
5317 struct mlx5_ifc_modify_tis_in_bits {
5319 u8 reserved_0[0x10];
5321 u8 reserved_1[0x10];
5327 u8 reserved_3[0x20];
5329 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5331 u8 reserved_4[0x40];
5333 struct mlx5_ifc_tisc_bits ctx;
5336 struct mlx5_ifc_modify_tir_out_bits {
5338 u8 reserved_0[0x18];
5342 u8 reserved_1[0x40];
5347 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5348 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1
5351 struct mlx5_ifc_modify_tir_in_bits {
5353 u8 reserved_0[0x10];
5355 u8 reserved_1[0x10];
5361 u8 reserved_3[0x20];
5363 u8 modify_bitmask[0x40];
5365 u8 reserved_4[0x40];
5367 struct mlx5_ifc_tirc_bits tir_context;
5370 struct mlx5_ifc_modify_sq_out_bits {
5372 u8 reserved_0[0x18];
5376 u8 reserved_1[0x40];
5379 struct mlx5_ifc_modify_sq_in_bits {
5381 u8 reserved_0[0x10];
5383 u8 reserved_1[0x10];
5390 u8 reserved_3[0x20];
5392 u8 modify_bitmask[0x40];
5394 u8 reserved_4[0x40];
5396 struct mlx5_ifc_sqc_bits ctx;
5399 struct mlx5_ifc_modify_scheduling_element_out_bits {
5401 u8 reserved_at_8[0x18];
5405 u8 reserved_at_40[0x1c0];
5409 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5413 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1,
5414 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2,
5417 struct mlx5_ifc_modify_scheduling_element_in_bits {
5419 u8 reserved_at_10[0x10];
5421 u8 reserved_at_20[0x10];
5424 u8 scheduling_hierarchy[0x8];
5425 u8 reserved_at_48[0x18];
5427 u8 scheduling_element_id[0x20];
5429 u8 reserved_at_80[0x20];
5431 u8 modify_bitmask[0x20];
5433 u8 reserved_at_c0[0x40];
5435 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5437 u8 reserved_at_300[0x100];
5440 struct mlx5_ifc_modify_rqt_out_bits {
5442 u8 reserved_0[0x18];
5446 u8 reserved_1[0x40];
5449 struct mlx5_ifc_modify_rqt_in_bits {
5451 u8 reserved_0[0x10];
5453 u8 reserved_1[0x10];
5459 u8 reserved_3[0x20];
5461 u8 modify_bitmask[0x40];
5463 u8 reserved_4[0x40];
5465 struct mlx5_ifc_rqtc_bits ctx;
5468 struct mlx5_ifc_modify_rq_out_bits {
5470 u8 reserved_0[0x18];
5474 u8 reserved_1[0x40];
5478 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5479 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5482 struct mlx5_ifc_modify_rq_in_bits {
5484 u8 reserved_0[0x10];
5486 u8 reserved_1[0x10];
5493 u8 reserved_3[0x20];
5495 u8 modify_bitmask[0x40];
5497 u8 reserved_4[0x40];
5499 struct mlx5_ifc_rqc_bits ctx;
5502 struct mlx5_ifc_modify_rmp_out_bits {
5504 u8 reserved_0[0x18];
5508 u8 reserved_1[0x40];
5511 struct mlx5_ifc_rmp_bitmask_bits {
5518 struct mlx5_ifc_modify_rmp_in_bits {
5520 u8 reserved_0[0x10];
5522 u8 reserved_1[0x10];
5529 u8 reserved_3[0x20];
5531 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5533 u8 reserved_4[0x40];
5535 struct mlx5_ifc_rmpc_bits ctx;
5538 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5540 u8 reserved_0[0x18];
5544 u8 reserved_1[0x40];
5547 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5548 u8 reserved_0[0x14];
5549 u8 disable_uc_local_lb[0x1];
5550 u8 disable_mc_local_lb[0x1];
5553 u8 min_wqe_inline_mode[0x1];
5555 u8 change_event[0x1];
5557 u8 permanent_address[0x1];
5558 u8 addresses_list[0x1];
5563 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5565 u8 reserved_0[0x10];
5567 u8 reserved_1[0x10];
5570 u8 other_vport[0x1];
5572 u8 vport_number[0x10];
5574 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5576 u8 reserved_3[0x780];
5578 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5581 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5583 u8 reserved_0[0x18];
5587 u8 reserved_1[0x40];
5590 struct mlx5_ifc_grh_bits {
5592 u8 traffic_class[8];
5594 u8 payload_length[16];
5601 struct mlx5_ifc_bth_bits {
5615 struct mlx5_ifc_aeth_bits {
5620 struct mlx5_ifc_dceth_bits {
5627 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5629 u8 reserved_0[0x10];
5631 u8 reserved_1[0x10];
5634 u8 other_vport[0x1];
5637 u8 vport_number[0x10];
5639 u8 reserved_3[0x20];
5641 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5644 struct mlx5_ifc_modify_flow_table_out_bits {
5646 u8 reserved_at_8[0x18];
5650 u8 reserved_at_40[0x40];
5654 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5655 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5658 struct mlx5_ifc_modify_flow_table_in_bits {
5660 u8 reserved_at_10[0x10];
5662 u8 reserved_at_20[0x10];
5665 u8 other_vport[0x1];
5666 u8 reserved_at_41[0xf];
5667 u8 vport_number[0x10];
5669 u8 reserved_at_60[0x10];
5670 u8 modify_field_select[0x10];
5673 u8 reserved_at_88[0x18];
5675 u8 reserved_at_a0[0x8];
5678 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5681 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5683 u8 reserved_0[0x18];
5687 u8 reserved_1[0x40];
5690 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5692 u8 vport_cvlan_insert[0x1];
5693 u8 vport_svlan_insert[0x1];
5694 u8 vport_cvlan_strip[0x1];
5695 u8 vport_svlan_strip[0x1];
5698 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5700 u8 reserved_0[0x10];
5702 u8 reserved_1[0x10];
5705 u8 other_vport[0x1];
5707 u8 vport_number[0x10];
5709 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5711 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5714 struct mlx5_ifc_modify_cq_out_bits {
5716 u8 reserved_0[0x18];
5720 u8 reserved_1[0x40];
5724 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5725 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5728 struct mlx5_ifc_modify_cq_in_bits {
5730 u8 reserved_0[0x10];
5732 u8 reserved_1[0x10];
5738 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5740 struct mlx5_ifc_cqc_bits cq_context;
5742 u8 reserved_3[0x600];
5747 struct mlx5_ifc_modify_cong_status_out_bits {
5749 u8 reserved_0[0x18];
5753 u8 reserved_1[0x40];
5756 struct mlx5_ifc_modify_cong_status_in_bits {
5758 u8 reserved_0[0x10];
5760 u8 reserved_1[0x10];
5763 u8 reserved_2[0x18];
5765 u8 cong_protocol[0x4];
5769 u8 reserved_3[0x1e];
5772 struct mlx5_ifc_modify_cong_params_out_bits {
5774 u8 reserved_0[0x18];
5778 u8 reserved_1[0x40];
5781 struct mlx5_ifc_modify_cong_params_in_bits {
5783 u8 reserved_0[0x10];
5785 u8 reserved_1[0x10];
5788 u8 reserved_2[0x1c];
5789 u8 cong_protocol[0x4];
5791 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5793 u8 reserved_3[0x80];
5795 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5798 struct mlx5_ifc_manage_pages_out_bits {
5800 u8 reserved_0[0x18];
5804 u8 output_num_entries[0x20];
5806 u8 reserved_1[0x20];
5812 MLX5_PAGES_CANT_GIVE = 0x0,
5813 MLX5_PAGES_GIVE = 0x1,
5814 MLX5_PAGES_TAKE = 0x2,
5817 struct mlx5_ifc_manage_pages_in_bits {
5819 u8 reserved_0[0x10];
5821 u8 reserved_1[0x10];
5824 u8 reserved_2[0x10];
5825 u8 function_id[0x10];
5827 u8 input_num_entries[0x20];
5832 struct mlx5_ifc_mad_ifc_out_bits {
5834 u8 reserved_0[0x18];
5838 u8 reserved_1[0x40];
5840 u8 response_mad_packet[256][0x8];
5843 struct mlx5_ifc_mad_ifc_in_bits {
5845 u8 reserved_0[0x10];
5847 u8 reserved_1[0x10];
5850 u8 remote_lid[0x10];
5854 u8 reserved_3[0x20];
5859 struct mlx5_ifc_init_hca_out_bits {
5861 u8 reserved_0[0x18];
5865 u8 reserved_1[0x40];
5869 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0,
5870 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1,
5873 struct mlx5_ifc_init_hca_in_bits {
5875 u8 reserved_0[0x10];
5877 u8 reserved_1[0x10];
5880 u8 reserved_2[0x40];
5883 struct mlx5_ifc_init2rtr_qp_out_bits {
5885 u8 reserved_0[0x18];
5889 u8 reserved_1[0x40];
5892 struct mlx5_ifc_init2rtr_qp_in_bits {
5894 u8 reserved_0[0x10];
5896 u8 reserved_1[0x10];
5902 u8 reserved_3[0x20];
5904 u8 opt_param_mask[0x20];
5906 u8 reserved_4[0x20];
5908 struct mlx5_ifc_qpc_bits qpc;
5910 u8 reserved_5[0x80];
5913 struct mlx5_ifc_init2init_qp_out_bits {
5915 u8 reserved_0[0x18];
5919 u8 reserved_1[0x40];
5922 struct mlx5_ifc_init2init_qp_in_bits {
5924 u8 reserved_0[0x10];
5926 u8 reserved_1[0x10];
5932 u8 reserved_3[0x20];
5934 u8 opt_param_mask[0x20];
5936 u8 reserved_4[0x20];
5938 struct mlx5_ifc_qpc_bits qpc;
5940 u8 reserved_5[0x80];
5943 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5945 u8 reserved_0[0x18];
5949 u8 reserved_1[0x40];
5951 u8 packet_headers_log[128][0x8];
5953 u8 packet_syndrome[64][0x8];
5956 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5958 u8 reserved_0[0x10];
5960 u8 reserved_1[0x10];
5963 u8 reserved_2[0x40];
5966 struct mlx5_ifc_gen_eqe_in_bits {
5968 u8 reserved_0[0x10];
5970 u8 reserved_1[0x10];
5973 u8 reserved_2[0x18];
5976 u8 reserved_3[0x20];
5981 struct mlx5_ifc_gen_eq_out_bits {
5983 u8 reserved_0[0x18];
5987 u8 reserved_1[0x40];
5990 struct mlx5_ifc_enable_hca_out_bits {
5992 u8 reserved_0[0x18];
5996 u8 reserved_1[0x20];
5999 struct mlx5_ifc_enable_hca_in_bits {
6001 u8 reserved_0[0x10];
6003 u8 reserved_1[0x10];
6006 u8 reserved_2[0x10];
6007 u8 function_id[0x10];
6009 u8 reserved_3[0x20];
6012 struct mlx5_ifc_drain_dct_out_bits {
6014 u8 reserved_0[0x18];
6018 u8 reserved_1[0x40];
6021 struct mlx5_ifc_drain_dct_in_bits {
6023 u8 reserved_0[0x10];
6025 u8 reserved_1[0x10];
6031 u8 reserved_3[0x20];
6034 struct mlx5_ifc_disable_hca_out_bits {
6036 u8 reserved_0[0x18];
6040 u8 reserved_1[0x20];
6043 struct mlx5_ifc_disable_hca_in_bits {
6045 u8 reserved_0[0x10];
6047 u8 reserved_1[0x10];
6050 u8 reserved_2[0x10];
6051 u8 function_id[0x10];
6053 u8 reserved_3[0x20];
6056 struct mlx5_ifc_detach_from_mcg_out_bits {
6058 u8 reserved_0[0x18];
6062 u8 reserved_1[0x40];
6065 struct mlx5_ifc_detach_from_mcg_in_bits {
6067 u8 reserved_0[0x10];
6069 u8 reserved_1[0x10];
6075 u8 reserved_3[0x20];
6077 u8 multicast_gid[16][0x8];
6080 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6082 u8 reserved_0[0x18];
6086 u8 reserved_1[0x40];
6089 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6091 u8 reserved_0[0x10];
6093 u8 reserved_1[0x10];
6099 u8 reserved_3[0x20];
6102 struct mlx5_ifc_destroy_tis_out_bits {
6104 u8 reserved_0[0x18];
6108 u8 reserved_1[0x40];
6111 struct mlx5_ifc_destroy_tis_in_bits {
6113 u8 reserved_0[0x10];
6115 u8 reserved_1[0x10];
6121 u8 reserved_3[0x20];
6124 struct mlx5_ifc_destroy_tir_out_bits {
6126 u8 reserved_0[0x18];
6130 u8 reserved_1[0x40];
6133 struct mlx5_ifc_destroy_tir_in_bits {
6135 u8 reserved_0[0x10];
6137 u8 reserved_1[0x10];
6143 u8 reserved_3[0x20];
6146 struct mlx5_ifc_destroy_srq_out_bits {
6148 u8 reserved_0[0x18];
6152 u8 reserved_1[0x40];
6155 struct mlx5_ifc_destroy_srq_in_bits {
6157 u8 reserved_0[0x10];
6159 u8 reserved_1[0x10];
6165 u8 reserved_3[0x20];
6168 struct mlx5_ifc_destroy_sq_out_bits {
6170 u8 reserved_0[0x18];
6174 u8 reserved_1[0x40];
6177 struct mlx5_ifc_destroy_sq_in_bits {
6179 u8 reserved_0[0x10];
6181 u8 reserved_1[0x10];
6187 u8 reserved_3[0x20];
6190 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6192 u8 reserved_at_8[0x18];
6196 u8 reserved_at_40[0x1c0];
6200 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6203 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6205 u8 reserved_at_10[0x10];
6207 u8 reserved_at_20[0x10];
6210 u8 scheduling_hierarchy[0x8];
6211 u8 reserved_at_48[0x18];
6213 u8 scheduling_element_id[0x20];
6215 u8 reserved_at_80[0x180];
6218 struct mlx5_ifc_destroy_rqt_out_bits {
6220 u8 reserved_0[0x18];
6224 u8 reserved_1[0x40];
6227 struct mlx5_ifc_destroy_rqt_in_bits {
6229 u8 reserved_0[0x10];
6231 u8 reserved_1[0x10];
6237 u8 reserved_3[0x20];
6240 struct mlx5_ifc_destroy_rq_out_bits {
6242 u8 reserved_0[0x18];
6246 u8 reserved_1[0x40];
6249 struct mlx5_ifc_destroy_rq_in_bits {
6251 u8 reserved_0[0x10];
6253 u8 reserved_1[0x10];
6259 u8 reserved_3[0x20];
6262 struct mlx5_ifc_destroy_rmp_out_bits {
6264 u8 reserved_0[0x18];
6268 u8 reserved_1[0x40];
6271 struct mlx5_ifc_destroy_rmp_in_bits {
6273 u8 reserved_0[0x10];
6275 u8 reserved_1[0x10];
6281 u8 reserved_3[0x20];
6284 struct mlx5_ifc_destroy_qp_out_bits {
6286 u8 reserved_0[0x18];
6290 u8 reserved_1[0x40];
6293 struct mlx5_ifc_destroy_qp_in_bits {
6295 u8 reserved_0[0x10];
6297 u8 reserved_1[0x10];
6303 u8 reserved_3[0x20];
6306 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6308 u8 reserved_at_8[0x18];
6312 u8 reserved_at_40[0x1c0];
6315 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6317 u8 reserved_at_10[0x10];
6319 u8 reserved_at_20[0x10];
6322 u8 reserved_at_40[0x20];
6324 u8 reserved_at_60[0x10];
6325 u8 qos_para_vport_number[0x10];
6327 u8 reserved_at_80[0x180];
6330 struct mlx5_ifc_destroy_psv_out_bits {
6332 u8 reserved_0[0x18];
6336 u8 reserved_1[0x40];
6339 struct mlx5_ifc_destroy_psv_in_bits {
6341 u8 reserved_0[0x10];
6343 u8 reserved_1[0x10];
6349 u8 reserved_3[0x20];
6352 struct mlx5_ifc_destroy_mkey_out_bits {
6354 u8 reserved_0[0x18];
6358 u8 reserved_1[0x40];
6361 struct mlx5_ifc_destroy_mkey_in_bits {
6363 u8 reserved_0[0x10];
6365 u8 reserved_1[0x10];
6369 u8 mkey_index[0x18];
6371 u8 reserved_3[0x20];
6374 struct mlx5_ifc_destroy_flow_table_out_bits {
6376 u8 reserved_0[0x18];
6380 u8 reserved_1[0x40];
6383 struct mlx5_ifc_destroy_flow_table_in_bits {
6385 u8 reserved_0[0x10];
6387 u8 reserved_1[0x10];
6390 u8 other_vport[0x1];
6392 u8 vport_number[0x10];
6394 u8 reserved_3[0x20];
6397 u8 reserved_4[0x18];
6402 u8 reserved_6[0x140];
6405 struct mlx5_ifc_destroy_flow_group_out_bits {
6407 u8 reserved_0[0x18];
6411 u8 reserved_1[0x40];
6414 struct mlx5_ifc_destroy_flow_group_in_bits {
6416 u8 reserved_0[0x10];
6418 u8 reserved_1[0x10];
6421 u8 other_vport[0x1];
6423 u8 vport_number[0x10];
6425 u8 reserved_3[0x20];
6428 u8 reserved_4[0x18];
6435 u8 reserved_6[0x120];
6438 struct mlx5_ifc_destroy_eq_out_bits {
6440 u8 reserved_0[0x18];
6444 u8 reserved_1[0x40];
6447 struct mlx5_ifc_destroy_eq_in_bits {
6449 u8 reserved_0[0x10];
6451 u8 reserved_1[0x10];
6454 u8 reserved_2[0x18];
6457 u8 reserved_3[0x20];
6460 struct mlx5_ifc_destroy_dct_out_bits {
6462 u8 reserved_0[0x18];
6466 u8 reserved_1[0x40];
6469 struct mlx5_ifc_destroy_dct_in_bits {
6471 u8 reserved_0[0x10];
6473 u8 reserved_1[0x10];
6479 u8 reserved_3[0x20];
6482 struct mlx5_ifc_destroy_cq_out_bits {
6484 u8 reserved_0[0x18];
6488 u8 reserved_1[0x40];
6491 struct mlx5_ifc_destroy_cq_in_bits {
6493 u8 reserved_0[0x10];
6495 u8 reserved_1[0x10];
6501 u8 reserved_3[0x20];
6504 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6506 u8 reserved_0[0x18];
6510 u8 reserved_1[0x40];
6513 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6515 u8 reserved_0[0x10];
6517 u8 reserved_1[0x10];
6520 u8 reserved_2[0x20];
6522 u8 reserved_3[0x10];
6523 u8 vxlan_udp_port[0x10];
6526 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6528 u8 reserved_0[0x18];
6532 u8 reserved_1[0x40];
6535 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6537 u8 reserved_0[0x10];
6539 u8 reserved_1[0x10];
6542 u8 reserved_2[0x60];
6545 u8 table_index[0x18];
6547 u8 reserved_4[0x140];
6550 struct mlx5_ifc_delete_fte_out_bits {
6552 u8 reserved_0[0x18];
6556 u8 reserved_1[0x40];
6559 struct mlx5_ifc_delete_fte_in_bits {
6561 u8 reserved_0[0x10];
6563 u8 reserved_1[0x10];
6566 u8 other_vport[0x1];
6568 u8 vport_number[0x10];
6570 u8 reserved_3[0x20];
6573 u8 reserved_4[0x18];
6578 u8 reserved_6[0x40];
6580 u8 flow_index[0x20];
6582 u8 reserved_7[0xe0];
6585 struct mlx5_ifc_dealloc_xrcd_out_bits {
6587 u8 reserved_0[0x18];
6591 u8 reserved_1[0x40];
6594 struct mlx5_ifc_dealloc_xrcd_in_bits {
6596 u8 reserved_0[0x10];
6598 u8 reserved_1[0x10];
6604 u8 reserved_3[0x20];
6607 struct mlx5_ifc_dealloc_uar_out_bits {
6609 u8 reserved_0[0x18];
6613 u8 reserved_1[0x40];
6616 struct mlx5_ifc_dealloc_uar_in_bits {
6618 u8 reserved_0[0x10];
6620 u8 reserved_1[0x10];
6626 u8 reserved_3[0x20];
6629 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6631 u8 reserved_0[0x18];
6635 u8 reserved_1[0x40];
6638 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6640 u8 reserved_0[0x10];
6642 u8 reserved_1[0x10];
6646 u8 transport_domain[0x18];
6648 u8 reserved_3[0x20];
6651 struct mlx5_ifc_dealloc_q_counter_out_bits {
6653 u8 reserved_0[0x18];
6657 u8 reserved_1[0x40];
6660 struct mlx5_ifc_counter_id_bits {
6662 u8 counter_id[0x10];
6665 struct mlx5_ifc_diagnostic_params_context_bits {
6666 u8 num_of_counters[0x10];
6668 u8 log_num_of_samples[0x8];
6676 u8 reserved_3[0x12];
6677 u8 log_sample_period[0x8];
6679 u8 reserved_4[0x80];
6681 struct mlx5_ifc_counter_id_bits counter_id[0];
6684 struct mlx5_ifc_set_diagnostic_params_in_bits {
6686 u8 reserved_0[0x10];
6688 u8 reserved_1[0x10];
6691 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6694 struct mlx5_ifc_set_diagnostic_params_out_bits {
6696 u8 reserved_0[0x18];
6700 u8 reserved_1[0x40];
6703 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6705 u8 reserved_0[0x10];
6707 u8 reserved_1[0x10];
6710 u8 num_of_samples[0x10];
6711 u8 sample_index[0x10];
6713 u8 reserved_2[0x20];
6716 struct mlx5_ifc_diagnostic_counter_bits {
6717 u8 counter_id[0x10];
6720 u8 time_stamp_31_0[0x20];
6722 u8 counter_value_h[0x20];
6724 u8 counter_value_l[0x20];
6727 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6729 u8 reserved_0[0x18];
6733 u8 reserved_1[0x40];
6735 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6738 struct mlx5_ifc_dealloc_q_counter_in_bits {
6740 u8 reserved_0[0x10];
6742 u8 reserved_1[0x10];
6745 u8 reserved_2[0x18];
6746 u8 counter_set_id[0x8];
6748 u8 reserved_3[0x20];
6751 struct mlx5_ifc_dealloc_pd_out_bits {
6753 u8 reserved_0[0x18];
6757 u8 reserved_1[0x40];
6760 struct mlx5_ifc_dealloc_pd_in_bits {
6762 u8 reserved_0[0x10];
6764 u8 reserved_1[0x10];
6770 u8 reserved_3[0x20];
6773 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6775 u8 reserved_0[0x18];
6779 u8 reserved_1[0x40];
6782 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6784 u8 reserved_0[0x10];
6786 u8 reserved_1[0x10];
6789 u8 reserved_2[0x10];
6790 u8 flow_counter_id[0x10];
6792 u8 reserved_3[0x20];
6795 struct mlx5_ifc_deactivate_tracer_out_bits {
6797 u8 reserved_0[0x18];
6801 u8 reserved_1[0x40];
6804 struct mlx5_ifc_deactivate_tracer_in_bits {
6806 u8 reserved_0[0x10];
6808 u8 reserved_1[0x10];
6813 u8 reserved_2[0x20];
6816 struct mlx5_ifc_create_xrc_srq_out_bits {
6818 u8 reserved_0[0x18];
6825 u8 reserved_2[0x20];
6828 struct mlx5_ifc_create_xrc_srq_in_bits {
6830 u8 reserved_0[0x10];
6832 u8 reserved_1[0x10];
6835 u8 reserved_2[0x40];
6837 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6839 u8 reserved_3[0x600];
6844 struct mlx5_ifc_create_tis_out_bits {
6846 u8 reserved_0[0x18];
6853 u8 reserved_2[0x20];
6856 struct mlx5_ifc_create_tis_in_bits {
6858 u8 reserved_0[0x10];
6860 u8 reserved_1[0x10];
6863 u8 reserved_2[0xc0];
6865 struct mlx5_ifc_tisc_bits ctx;
6868 struct mlx5_ifc_create_tir_out_bits {
6870 u8 reserved_0[0x18];
6877 u8 reserved_2[0x20];
6880 struct mlx5_ifc_create_tir_in_bits {
6882 u8 reserved_0[0x10];
6884 u8 reserved_1[0x10];
6887 u8 reserved_2[0xc0];
6889 struct mlx5_ifc_tirc_bits tir_context;
6892 struct mlx5_ifc_create_srq_out_bits {
6894 u8 reserved_0[0x18];
6901 u8 reserved_2[0x20];
6904 struct mlx5_ifc_create_srq_in_bits {
6906 u8 reserved_0[0x10];
6908 u8 reserved_1[0x10];
6911 u8 reserved_2[0x40];
6913 struct mlx5_ifc_srqc_bits srq_context_entry;
6915 u8 reserved_3[0x600];
6920 struct mlx5_ifc_create_sq_out_bits {
6922 u8 reserved_0[0x18];
6929 u8 reserved_2[0x20];
6932 struct mlx5_ifc_create_sq_in_bits {
6934 u8 reserved_0[0x10];
6936 u8 reserved_1[0x10];
6939 u8 reserved_2[0xc0];
6941 struct mlx5_ifc_sqc_bits ctx;
6944 struct mlx5_ifc_create_scheduling_element_out_bits {
6946 u8 reserved_at_8[0x18];
6950 u8 reserved_at_40[0x40];
6952 u8 scheduling_element_id[0x20];
6954 u8 reserved_at_a0[0x160];
6958 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6961 struct mlx5_ifc_create_scheduling_element_in_bits {
6963 u8 reserved_at_10[0x10];
6965 u8 reserved_at_20[0x10];
6968 u8 scheduling_hierarchy[0x8];
6969 u8 reserved_at_48[0x18];
6971 u8 reserved_at_60[0xa0];
6973 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6975 u8 reserved_at_300[0x100];
6978 struct mlx5_ifc_create_rqt_out_bits {
6980 u8 reserved_0[0x18];
6987 u8 reserved_2[0x20];
6990 struct mlx5_ifc_create_rqt_in_bits {
6992 u8 reserved_0[0x10];
6994 u8 reserved_1[0x10];
6997 u8 reserved_2[0xc0];
6999 struct mlx5_ifc_rqtc_bits rqt_context;
7002 struct mlx5_ifc_create_rq_out_bits {
7004 u8 reserved_0[0x18];
7011 u8 reserved_2[0x20];
7014 struct mlx5_ifc_create_rq_in_bits {
7016 u8 reserved_0[0x10];
7018 u8 reserved_1[0x10];
7021 u8 reserved_2[0xc0];
7023 struct mlx5_ifc_rqc_bits ctx;
7026 struct mlx5_ifc_create_rmp_out_bits {
7028 u8 reserved_0[0x18];
7035 u8 reserved_2[0x20];
7038 struct mlx5_ifc_create_rmp_in_bits {
7040 u8 reserved_0[0x10];
7042 u8 reserved_1[0x10];
7045 u8 reserved_2[0xc0];
7047 struct mlx5_ifc_rmpc_bits ctx;
7050 struct mlx5_ifc_create_qp_out_bits {
7052 u8 reserved_0[0x18];
7059 u8 reserved_2[0x20];
7062 struct mlx5_ifc_create_qp_in_bits {
7064 u8 reserved_0[0x10];
7066 u8 reserved_1[0x10];
7072 u8 reserved_3[0x20];
7074 u8 opt_param_mask[0x20];
7076 u8 reserved_4[0x20];
7078 struct mlx5_ifc_qpc_bits qpc;
7080 u8 reserved_5[0x80];
7085 struct mlx5_ifc_create_qos_para_vport_out_bits {
7087 u8 reserved_at_8[0x18];
7091 u8 reserved_at_40[0x20];
7093 u8 reserved_at_60[0x10];
7094 u8 qos_para_vport_number[0x10];
7096 u8 reserved_at_80[0x180];
7099 struct mlx5_ifc_create_qos_para_vport_in_bits {
7101 u8 reserved_at_10[0x10];
7103 u8 reserved_at_20[0x10];
7106 u8 reserved_at_40[0x1c0];
7109 struct mlx5_ifc_create_psv_out_bits {
7111 u8 reserved_0[0x18];
7115 u8 reserved_1[0x40];
7118 u8 psv0_index[0x18];
7121 u8 psv1_index[0x18];
7124 u8 psv2_index[0x18];
7127 u8 psv3_index[0x18];
7130 struct mlx5_ifc_create_psv_in_bits {
7132 u8 reserved_0[0x10];
7134 u8 reserved_1[0x10];
7141 u8 reserved_3[0x20];
7144 struct mlx5_ifc_create_mkey_out_bits {
7146 u8 reserved_0[0x18];
7151 u8 mkey_index[0x18];
7153 u8 reserved_2[0x20];
7156 struct mlx5_ifc_create_mkey_in_bits {
7158 u8 reserved_0[0x10];
7160 u8 reserved_1[0x10];
7163 u8 reserved_2[0x20];
7166 u8 reserved_3[0x1f];
7168 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7170 u8 reserved_4[0x80];
7172 u8 translations_octword_actual_size[0x20];
7174 u8 reserved_5[0x560];
7176 u8 klm_pas_mtt[0][0x20];
7179 struct mlx5_ifc_create_flow_table_out_bits {
7181 u8 reserved_0[0x18];
7188 u8 reserved_2[0x20];
7191 struct mlx5_ifc_create_flow_table_in_bits {
7193 u8 reserved_at_10[0x10];
7195 u8 reserved_at_20[0x10];
7198 u8 other_vport[0x1];
7199 u8 reserved_at_41[0xf];
7200 u8 vport_number[0x10];
7202 u8 reserved_at_60[0x20];
7205 u8 reserved_at_88[0x18];
7207 u8 reserved_at_a0[0x20];
7209 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7212 struct mlx5_ifc_create_flow_group_out_bits {
7214 u8 reserved_0[0x18];
7221 u8 reserved_2[0x20];
7225 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7226 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7227 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7230 struct mlx5_ifc_create_flow_group_in_bits {
7232 u8 reserved_0[0x10];
7234 u8 reserved_1[0x10];
7237 u8 other_vport[0x1];
7239 u8 vport_number[0x10];
7241 u8 reserved_3[0x20];
7244 u8 reserved_4[0x18];
7249 u8 reserved_6[0x20];
7251 u8 start_flow_index[0x20];
7253 u8 reserved_7[0x20];
7255 u8 end_flow_index[0x20];
7257 u8 reserved_8[0xa0];
7259 u8 reserved_9[0x18];
7260 u8 match_criteria_enable[0x8];
7262 struct mlx5_ifc_fte_match_param_bits match_criteria;
7264 u8 reserved_10[0xe00];
7267 struct mlx5_ifc_create_eq_out_bits {
7269 u8 reserved_0[0x18];
7273 u8 reserved_1[0x18];
7276 u8 reserved_2[0x20];
7279 struct mlx5_ifc_create_eq_in_bits {
7281 u8 reserved_0[0x10];
7283 u8 reserved_1[0x10];
7286 u8 reserved_2[0x40];
7288 struct mlx5_ifc_eqc_bits eq_context_entry;
7290 u8 reserved_3[0x40];
7292 u8 event_bitmask[0x40];
7294 u8 reserved_4[0x580];
7299 struct mlx5_ifc_create_dct_out_bits {
7301 u8 reserved_0[0x18];
7308 u8 reserved_2[0x20];
7311 struct mlx5_ifc_create_dct_in_bits {
7313 u8 reserved_0[0x10];
7315 u8 reserved_1[0x10];
7318 u8 reserved_2[0x40];
7320 struct mlx5_ifc_dctc_bits dct_context_entry;
7322 u8 reserved_3[0x180];
7325 struct mlx5_ifc_create_cq_out_bits {
7327 u8 reserved_0[0x18];
7334 u8 reserved_2[0x20];
7337 struct mlx5_ifc_create_cq_in_bits {
7339 u8 reserved_0[0x10];
7341 u8 reserved_1[0x10];
7344 u8 reserved_2[0x40];
7346 struct mlx5_ifc_cqc_bits cq_context;
7348 u8 reserved_3[0x600];
7353 struct mlx5_ifc_config_int_moderation_out_bits {
7355 u8 reserved_0[0x18];
7361 u8 int_vector[0x10];
7363 u8 reserved_2[0x20];
7367 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7368 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7371 struct mlx5_ifc_config_int_moderation_in_bits {
7373 u8 reserved_0[0x10];
7375 u8 reserved_1[0x10];
7380 u8 int_vector[0x10];
7382 u8 reserved_3[0x20];
7385 struct mlx5_ifc_attach_to_mcg_out_bits {
7387 u8 reserved_0[0x18];
7391 u8 reserved_1[0x40];
7394 struct mlx5_ifc_attach_to_mcg_in_bits {
7396 u8 reserved_0[0x10];
7398 u8 reserved_1[0x10];
7404 u8 reserved_3[0x20];
7406 u8 multicast_gid[16][0x8];
7409 struct mlx5_ifc_arm_xrc_srq_out_bits {
7411 u8 reserved_0[0x18];
7415 u8 reserved_1[0x40];
7419 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7422 struct mlx5_ifc_arm_xrc_srq_in_bits {
7424 u8 reserved_0[0x10];
7426 u8 reserved_1[0x10];
7432 u8 reserved_3[0x10];
7436 struct mlx5_ifc_arm_rq_out_bits {
7438 u8 reserved_0[0x18];
7442 u8 reserved_1[0x40];
7446 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7449 struct mlx5_ifc_arm_rq_in_bits {
7451 u8 reserved_0[0x10];
7453 u8 reserved_1[0x10];
7457 u8 srq_number[0x18];
7459 u8 reserved_3[0x10];
7463 struct mlx5_ifc_arm_dct_out_bits {
7465 u8 reserved_0[0x18];
7469 u8 reserved_1[0x40];
7472 struct mlx5_ifc_arm_dct_in_bits {
7474 u8 reserved_0[0x10];
7476 u8 reserved_1[0x10];
7482 u8 reserved_3[0x20];
7485 struct mlx5_ifc_alloc_xrcd_out_bits {
7487 u8 reserved_0[0x18];
7494 u8 reserved_2[0x20];
7497 struct mlx5_ifc_alloc_xrcd_in_bits {
7499 u8 reserved_0[0x10];
7501 u8 reserved_1[0x10];
7504 u8 reserved_2[0x40];
7507 struct mlx5_ifc_alloc_uar_out_bits {
7509 u8 reserved_0[0x18];
7516 u8 reserved_2[0x20];
7519 struct mlx5_ifc_alloc_uar_in_bits {
7521 u8 reserved_0[0x10];
7523 u8 reserved_1[0x10];
7526 u8 reserved_2[0x40];
7529 struct mlx5_ifc_alloc_transport_domain_out_bits {
7531 u8 reserved_0[0x18];
7536 u8 transport_domain[0x18];
7538 u8 reserved_2[0x20];
7541 struct mlx5_ifc_alloc_transport_domain_in_bits {
7543 u8 reserved_0[0x10];
7545 u8 reserved_1[0x10];
7548 u8 reserved_2[0x40];
7551 struct mlx5_ifc_alloc_q_counter_out_bits {
7553 u8 reserved_0[0x18];
7557 u8 reserved_1[0x18];
7558 u8 counter_set_id[0x8];
7560 u8 reserved_2[0x20];
7563 struct mlx5_ifc_alloc_q_counter_in_bits {
7565 u8 reserved_0[0x10];
7567 u8 reserved_1[0x10];
7570 u8 reserved_2[0x40];
7573 struct mlx5_ifc_alloc_pd_out_bits {
7575 u8 reserved_0[0x18];
7582 u8 reserved_2[0x20];
7585 struct mlx5_ifc_alloc_pd_in_bits {
7587 u8 reserved_0[0x10];
7589 u8 reserved_1[0x10];
7592 u8 reserved_2[0x40];
7595 struct mlx5_ifc_alloc_flow_counter_out_bits {
7597 u8 reserved_0[0x18];
7601 u8 reserved_1[0x10];
7602 u8 flow_counter_id[0x10];
7604 u8 reserved_2[0x20];
7607 struct mlx5_ifc_alloc_flow_counter_in_bits {
7609 u8 reserved_0[0x10];
7611 u8 reserved_1[0x10];
7614 u8 reserved_2[0x40];
7617 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7619 u8 reserved_0[0x18];
7623 u8 reserved_1[0x40];
7626 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7628 u8 reserved_0[0x10];
7630 u8 reserved_1[0x10];
7633 u8 reserved_2[0x20];
7635 u8 reserved_3[0x10];
7636 u8 vxlan_udp_port[0x10];
7639 struct mlx5_ifc_activate_tracer_out_bits {
7641 u8 reserved_0[0x18];
7645 u8 reserved_1[0x40];
7648 struct mlx5_ifc_activate_tracer_in_bits {
7650 u8 reserved_0[0x10];
7652 u8 reserved_1[0x10];
7657 u8 reserved_2[0x20];
7660 struct mlx5_ifc_set_rate_limit_out_bits {
7662 u8 reserved_at_8[0x18];
7666 u8 reserved_at_40[0x40];
7669 struct mlx5_ifc_set_rate_limit_in_bits {
7671 u8 reserved_at_10[0x10];
7673 u8 reserved_at_20[0x10];
7676 u8 reserved_at_40[0x10];
7677 u8 rate_limit_index[0x10];
7679 u8 reserved_at_60[0x20];
7681 u8 rate_limit[0x20];
7682 u8 burst_upper_bound[0x20];
7685 struct mlx5_ifc_access_register_out_bits {
7687 u8 reserved_0[0x18];
7691 u8 reserved_1[0x40];
7693 u8 register_data[0][0x20];
7697 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7698 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7701 struct mlx5_ifc_access_register_in_bits {
7703 u8 reserved_0[0x10];
7705 u8 reserved_1[0x10];
7708 u8 reserved_2[0x10];
7709 u8 register_id[0x10];
7713 u8 register_data[0][0x20];
7716 struct mlx5_ifc_sltp_reg_bits {
7725 u8 reserved_2[0x20];
7734 u8 ob_preemp_mode[0x4];
7738 u8 reserved_5[0x20];
7741 struct mlx5_ifc_slrp_reg_bits {
7751 u8 reserved_2[0x11];
7767 u8 mixerbias_tap_amp[0x8];
7771 u8 ffe_tap_offset0[0x8];
7772 u8 ffe_tap_offset1[0x8];
7773 u8 slicer_offset0[0x10];
7775 u8 mixer_offset0[0x10];
7776 u8 mixer_offset1[0x10];
7778 u8 mixerbgn_inp[0x8];
7779 u8 mixerbgn_inn[0x8];
7780 u8 mixerbgn_refp[0x8];
7781 u8 mixerbgn_refn[0x8];
7783 u8 sel_slicer_lctrl_h[0x1];
7784 u8 sel_slicer_lctrl_l[0x1];
7786 u8 ref_mixer_vreg[0x5];
7787 u8 slicer_gctrl[0x8];
7788 u8 lctrl_input[0x8];
7789 u8 mixer_offset_cm1[0x8];
7791 u8 common_mode[0x6];
7793 u8 mixer_offset_cm0[0x9];
7795 u8 slicer_offset_cm[0x9];
7798 struct mlx5_ifc_slrg_reg_bits {
7807 u8 time_to_link_up[0x10];
7809 u8 grade_lane_speed[0x4];
7811 u8 grade_version[0x8];
7815 u8 height_grade_type[0x4];
7816 u8 height_grade[0x18];
7821 u8 reserved_4[0x10];
7822 u8 height_sigma[0x10];
7824 u8 reserved_5[0x20];
7827 u8 phase_grade_type[0x4];
7828 u8 phase_grade[0x18];
7831 u8 phase_eo_pos[0x8];
7833 u8 phase_eo_neg[0x8];
7835 u8 ffe_set_tested[0x10];
7836 u8 test_errors_per_lane[0x10];
7839 struct mlx5_ifc_pvlc_reg_bits {
7842 u8 reserved_1[0x10];
7844 u8 reserved_2[0x1c];
7847 u8 reserved_3[0x1c];
7850 u8 reserved_4[0x1c];
7851 u8 vl_operational[0x4];
7854 struct mlx5_ifc_pude_reg_bits {
7858 u8 admin_status[0x4];
7860 u8 oper_status[0x4];
7862 u8 reserved_2[0x60];
7866 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1,
7867 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4,
7870 struct mlx5_ifc_ptys_reg_bits {
7872 u8 an_disable_admin[0x1];
7873 u8 an_disable_cap[0x1];
7875 u8 force_tx_aba_param[0x1];
7882 u8 data_rate_oper[0x10];
7884 u8 ext_eth_proto_capability[0x20];
7886 u8 eth_proto_capability[0x20];
7888 u8 ib_link_width_capability[0x10];
7889 u8 ib_proto_capability[0x10];
7891 u8 ext_eth_proto_admin[0x20];
7893 u8 eth_proto_admin[0x20];
7895 u8 ib_link_width_admin[0x10];
7896 u8 ib_proto_admin[0x10];
7898 u8 ext_eth_proto_oper[0x20];
7900 u8 eth_proto_oper[0x20];
7902 u8 ib_link_width_oper[0x10];
7903 u8 ib_proto_oper[0x10];
7905 u8 reserved_4[0x1c];
7906 u8 connector_type[0x4];
7908 u8 eth_proto_lp_advertise[0x20];
7910 u8 reserved_5[0x60];
7913 struct mlx5_ifc_ptas_reg_bits {
7914 u8 reserved_0[0x20];
7916 u8 algorithm_options[0x10];
7918 u8 repetitions_mode[0x4];
7919 u8 num_of_repetitions[0x8];
7921 u8 grade_version[0x8];
7922 u8 height_grade_type[0x4];
7923 u8 phase_grade_type[0x4];
7924 u8 height_grade_weight[0x8];
7925 u8 phase_grade_weight[0x8];
7927 u8 gisim_measure_bits[0x10];
7928 u8 adaptive_tap_measure_bits[0x10];
7930 u8 ber_bath_high_error_threshold[0x10];
7931 u8 ber_bath_mid_error_threshold[0x10];
7933 u8 ber_bath_low_error_threshold[0x10];
7934 u8 one_ratio_high_threshold[0x10];
7936 u8 one_ratio_high_mid_threshold[0x10];
7937 u8 one_ratio_low_mid_threshold[0x10];
7939 u8 one_ratio_low_threshold[0x10];
7940 u8 ndeo_error_threshold[0x10];
7942 u8 mixer_offset_step_size[0x10];
7944 u8 mix90_phase_for_voltage_bath[0x8];
7946 u8 mixer_offset_start[0x10];
7947 u8 mixer_offset_end[0x10];
7949 u8 reserved_3[0x15];
7950 u8 ber_test_time[0xb];
7953 struct mlx5_ifc_pspa_reg_bits {
7959 u8 reserved_1[0x20];
7962 struct mlx5_ifc_ppsc_reg_bits {
7965 u8 reserved_1[0x10];
7967 u8 reserved_2[0x60];
7969 u8 reserved_3[0x1c];
7972 u8 reserved_4[0x1c];
7973 u8 wrps_status[0x4];
7976 u8 down_th_vld[0x1];
7978 u8 up_threshold[0x8];
7980 u8 down_threshold[0x8];
7982 u8 reserved_7[0x20];
7984 u8 reserved_8[0x1c];
7987 u8 reserved_9[0x60];
7990 struct mlx5_ifc_pplr_reg_bits {
7993 u8 reserved_1[0x10];
8001 struct mlx5_ifc_pplm_reg_bits {
8004 u8 reserved_1[0x10];
8006 u8 reserved_2[0x20];
8008 u8 port_profile_mode[0x8];
8009 u8 static_port_profile[0x8];
8010 u8 active_port_profile[0x8];
8013 u8 retransmission_active[0x8];
8014 u8 fec_mode_active[0x18];
8016 u8 reserved_4[0x10];
8017 u8 v_100g_fec_override_cap[0x4];
8018 u8 v_50g_fec_override_cap[0x4];
8019 u8 v_25g_fec_override_cap[0x4];
8020 u8 v_10g_40g_fec_override_cap[0x4];
8022 u8 reserved_5[0x10];
8023 u8 v_100g_fec_override_admin[0x4];
8024 u8 v_50g_fec_override_admin[0x4];
8025 u8 v_25g_fec_override_admin[0x4];
8026 u8 v_10g_40g_fec_override_admin[0x4];
8029 struct mlx5_ifc_ppll_reg_bits {
8030 u8 num_pll_groups[0x8];
8036 u8 reserved_2[0x1f];
8039 u8 pll_status[4][0x40];
8042 struct mlx5_ifc_ppad_reg_bits {
8051 u8 reserved_2[0x40];
8054 struct mlx5_ifc_pmtu_reg_bits {
8057 u8 reserved_1[0x10];
8060 u8 reserved_2[0x10];
8063 u8 reserved_3[0x10];
8066 u8 reserved_4[0x10];
8069 struct mlx5_ifc_pmpr_reg_bits {
8072 u8 reserved_1[0x10];
8074 u8 reserved_2[0x18];
8075 u8 attenuation_5g[0x8];
8077 u8 reserved_3[0x18];
8078 u8 attenuation_7g[0x8];
8080 u8 reserved_4[0x18];
8081 u8 attenuation_12g[0x8];
8084 struct mlx5_ifc_pmpe_reg_bits {
8088 u8 module_status[0x4];
8090 u8 reserved_2[0x14];
8094 u8 reserved_4[0x40];
8097 struct mlx5_ifc_pmpc_reg_bits {
8098 u8 module_state_updated[32][0x8];
8101 struct mlx5_ifc_pmlpn_reg_bits {
8103 u8 mlpn_status[0x4];
8105 u8 reserved_1[0x10];
8108 u8 reserved_2[0x1f];
8111 struct mlx5_ifc_pmlp_reg_bits {
8118 u8 lane0_module_mapping[0x20];
8120 u8 lane1_module_mapping[0x20];
8122 u8 lane2_module_mapping[0x20];
8124 u8 lane3_module_mapping[0x20];
8126 u8 reserved_2[0x160];
8129 struct mlx5_ifc_pmaos_reg_bits {
8133 u8 admin_status[0x4];
8135 u8 oper_status[0x4];
8139 u8 reserved_3[0x12];
8144 u8 reserved_5[0x40];
8147 struct mlx5_ifc_plpc_reg_bits {
8154 u8 reserved_3[0x10];
8155 u8 lane_speed[0x10];
8157 u8 reserved_4[0x17];
8159 u8 fec_mode_policy[0x8];
8161 u8 retransmission_capability[0x8];
8162 u8 fec_mode_capability[0x18];
8164 u8 retransmission_support_admin[0x8];
8165 u8 fec_mode_support_admin[0x18];
8167 u8 retransmission_request_admin[0x8];
8168 u8 fec_mode_request_admin[0x18];
8170 u8 reserved_5[0x80];
8173 struct mlx5_ifc_pll_status_data_bits {
8176 u8 lock_status[0x2];
8178 u8 algo_f_ctrl[0xa];
8179 u8 analog_algo_num_var[0x6];
8180 u8 f_ctrl_measure[0xa];
8192 struct mlx5_ifc_plib_reg_bits {
8198 u8 reserved_2[0x60];
8201 struct mlx5_ifc_plbf_reg_bits {
8207 u8 reserved_2[0x20];
8210 struct mlx5_ifc_pipg_reg_bits {
8213 u8 reserved_1[0x10];
8216 u8 reserved_2[0x19];
8221 struct mlx5_ifc_pifr_reg_bits {
8224 u8 reserved_1[0x10];
8226 u8 reserved_2[0xe0];
8228 u8 port_filter[8][0x20];
8230 u8 port_filter_update_en[8][0x20];
8233 struct mlx5_ifc_phys_layer_cntrs_bits {
8234 u8 time_since_last_clear_high[0x20];
8236 u8 time_since_last_clear_low[0x20];
8238 u8 symbol_errors_high[0x20];
8240 u8 symbol_errors_low[0x20];
8242 u8 sync_headers_errors_high[0x20];
8244 u8 sync_headers_errors_low[0x20];
8246 u8 edpl_bip_errors_lane0_high[0x20];
8248 u8 edpl_bip_errors_lane0_low[0x20];
8250 u8 edpl_bip_errors_lane1_high[0x20];
8252 u8 edpl_bip_errors_lane1_low[0x20];
8254 u8 edpl_bip_errors_lane2_high[0x20];
8256 u8 edpl_bip_errors_lane2_low[0x20];
8258 u8 edpl_bip_errors_lane3_high[0x20];
8260 u8 edpl_bip_errors_lane3_low[0x20];
8262 u8 fc_fec_corrected_blocks_lane0_high[0x20];
8264 u8 fc_fec_corrected_blocks_lane0_low[0x20];
8266 u8 fc_fec_corrected_blocks_lane1_high[0x20];
8268 u8 fc_fec_corrected_blocks_lane1_low[0x20];
8270 u8 fc_fec_corrected_blocks_lane2_high[0x20];
8272 u8 fc_fec_corrected_blocks_lane2_low[0x20];
8274 u8 fc_fec_corrected_blocks_lane3_high[0x20];
8276 u8 fc_fec_corrected_blocks_lane3_low[0x20];
8278 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
8280 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
8282 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
8284 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
8286 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
8288 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
8290 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
8292 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
8294 u8 rs_fec_corrected_blocks_high[0x20];
8296 u8 rs_fec_corrected_blocks_low[0x20];
8298 u8 rs_fec_uncorrectable_blocks_high[0x20];
8300 u8 rs_fec_uncorrectable_blocks_low[0x20];
8302 u8 rs_fec_no_errors_blocks_high[0x20];
8304 u8 rs_fec_no_errors_blocks_low[0x20];
8306 u8 rs_fec_single_error_blocks_high[0x20];
8308 u8 rs_fec_single_error_blocks_low[0x20];
8310 u8 rs_fec_corrected_symbols_total_high[0x20];
8312 u8 rs_fec_corrected_symbols_total_low[0x20];
8314 u8 rs_fec_corrected_symbols_lane0_high[0x20];
8316 u8 rs_fec_corrected_symbols_lane0_low[0x20];
8318 u8 rs_fec_corrected_symbols_lane1_high[0x20];
8320 u8 rs_fec_corrected_symbols_lane1_low[0x20];
8322 u8 rs_fec_corrected_symbols_lane2_high[0x20];
8324 u8 rs_fec_corrected_symbols_lane2_low[0x20];
8326 u8 rs_fec_corrected_symbols_lane3_high[0x20];
8328 u8 rs_fec_corrected_symbols_lane3_low[0x20];
8330 u8 link_down_events[0x20];
8332 u8 successful_recovery_events[0x20];
8334 u8 reserved_0[0x180];
8337 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8338 u8 symbol_error_counter[0x10];
8340 u8 link_error_recovery_counter[0x8];
8342 u8 link_downed_counter[0x8];
8344 u8 port_rcv_errors[0x10];
8346 u8 port_rcv_remote_physical_errors[0x10];
8348 u8 port_rcv_switch_relay_errors[0x10];
8350 u8 port_xmit_discards[0x10];
8352 u8 port_xmit_constraint_errors[0x8];
8354 u8 port_rcv_constraint_errors[0x8];
8356 u8 reserved_at_70[0x8];
8358 u8 link_overrun_errors[0x8];
8360 u8 reserved_at_80[0x10];
8362 u8 vl_15_dropped[0x10];
8364 u8 reserved_at_a0[0xa0];
8367 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8368 u8 time_since_last_clear_high[0x20];
8370 u8 time_since_last_clear_low[0x20];
8372 u8 phy_received_bits_high[0x20];
8374 u8 phy_received_bits_low[0x20];
8376 u8 phy_symbol_errors_high[0x20];
8378 u8 phy_symbol_errors_low[0x20];
8380 u8 phy_corrected_bits_high[0x20];
8382 u8 phy_corrected_bits_low[0x20];
8384 u8 phy_corrected_bits_lane0_high[0x20];
8386 u8 phy_corrected_bits_lane0_low[0x20];
8388 u8 phy_corrected_bits_lane1_high[0x20];
8390 u8 phy_corrected_bits_lane1_low[0x20];
8392 u8 phy_corrected_bits_lane2_high[0x20];
8394 u8 phy_corrected_bits_lane2_low[0x20];
8396 u8 phy_corrected_bits_lane3_high[0x20];
8398 u8 phy_corrected_bits_lane3_low[0x20];
8400 u8 reserved_at_200[0x5c0];
8403 struct mlx5_ifc_infiniband_port_cntrs_bits {
8404 u8 symbol_error_counter[0x10];
8405 u8 link_error_recovery_counter[0x8];
8406 u8 link_downed_counter[0x8];
8408 u8 port_rcv_errors[0x10];
8409 u8 port_rcv_remote_physical_errors[0x10];
8411 u8 port_rcv_switch_relay_errors[0x10];
8412 u8 port_xmit_discards[0x10];
8414 u8 port_xmit_constraint_errors[0x8];
8415 u8 port_rcv_constraint_errors[0x8];
8417 u8 local_link_integrity_errors[0x4];
8418 u8 excessive_buffer_overrun_errors[0x4];
8420 u8 reserved_1[0x10];
8421 u8 vl_15_dropped[0x10];
8423 u8 port_xmit_data[0x20];
8425 u8 port_rcv_data[0x20];
8427 u8 port_xmit_pkts[0x20];
8429 u8 port_rcv_pkts[0x20];
8431 u8 port_xmit_wait[0x20];
8433 u8 reserved_2[0x680];
8436 struct mlx5_ifc_phrr_reg_bits {
8440 u8 reserved_1[0x10];
8443 u8 reserved_2[0x10];
8446 u8 reserved_3[0x40];
8448 u8 time_since_last_clear_high[0x20];
8450 u8 time_since_last_clear_low[0x20];
8455 struct mlx5_ifc_phbr_for_prio_reg_bits {
8456 u8 reserved_0[0x18];
8460 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8461 u8 reserved_0[0x18];
8465 struct mlx5_ifc_phbr_binding_reg_bits {
8473 u8 reserved_2[0x10];
8476 u8 reserved_3[0x10];
8479 u8 hist_parameters[0x20];
8481 u8 hist_min_value[0x20];
8483 u8 hist_max_value[0x20];
8485 u8 sample_time[0x20];
8489 MLX5_PFCC_REG_PPAN_DISABLED = 0x0,
8490 MLX5_PFCC_REG_PPAN_ENABLED = 0x1,
8493 struct mlx5_ifc_pfcc_reg_bits {
8494 u8 dcbx_operation_type[0x2];
8495 u8 cap_local_admin[0x1];
8496 u8 cap_remote_admin[0x1];
8506 u8 prio_mask_tx[0x8];
8508 u8 prio_mask_rx[0x8];
8524 u8 device_stall_minor_watermark[0x10];
8525 u8 device_stall_critical_watermark[0x10];
8527 u8 reserved_8[0x60];
8530 struct mlx5_ifc_pelc_reg_bits {
8534 u8 reserved_1[0x10];
8537 u8 op_capability[0x8];
8543 u8 capability[0x40];
8549 u8 reserved_2[0x80];
8552 struct mlx5_ifc_peir_reg_bits {
8555 u8 reserved_1[0x10];
8558 u8 error_count[0x4];
8559 u8 reserved_3[0x10];
8567 struct mlx5_ifc_qcam_access_reg_cap_mask {
8568 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8570 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8574 u8 qcam_access_reg_cap_mask_0[0x1];
8577 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8578 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8579 u8 qpts_trust_both[0x1];
8582 struct mlx5_ifc_qcam_reg_bits {
8583 u8 reserved_at_0[0x8];
8584 u8 feature_group[0x8];
8585 u8 reserved_at_10[0x8];
8586 u8 access_reg_group[0x8];
8587 u8 reserved_at_20[0x20];
8590 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8591 u8 reserved_at_0[0x80];
8592 } qos_access_reg_cap_mask;
8594 u8 reserved_at_c0[0x80];
8597 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8598 u8 reserved_at_0[0x80];
8599 } qos_feature_cap_mask;
8601 u8 reserved_at_1c0[0x80];
8604 struct mlx5_ifc_pcam_enhanced_features_bits {
8605 u8 reserved_at_0[0x6d];
8606 u8 rx_icrc_encapsulated_counter[0x1];
8607 u8 reserved_at_6e[0x4];
8608 u8 ptys_extended_ethernet[0x1];
8609 u8 reserved_at_73[0x3];
8611 u8 reserved_at_77[0x3];
8612 u8 per_lane_error_counters[0x1];
8613 u8 rx_buffer_fullness_counters[0x1];
8614 u8 ptys_connector_type[0x1];
8615 u8 reserved_at_7d[0x1];
8616 u8 ppcnt_discard_group[0x1];
8617 u8 ppcnt_statistical_group[0x1];
8620 struct mlx5_ifc_pcam_reg_bits {
8621 u8 reserved_at_0[0x8];
8622 u8 feature_group[0x8];
8623 u8 reserved_at_10[0x8];
8624 u8 access_reg_group[0x8];
8626 u8 reserved_at_20[0x20];
8629 u8 reserved_at_0[0x80];
8630 } port_access_reg_cap_mask;
8632 u8 reserved_at_c0[0x80];
8635 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8636 u8 reserved_at_0[0x80];
8639 u8 reserved_at_1c0[0xc0];
8642 struct mlx5_ifc_mcam_enhanced_features_bits {
8643 u8 reserved_at_0[0x6e];
8644 u8 pcie_status_and_power[0x1];
8645 u8 reserved_at_111[0x10];
8646 u8 pcie_performance_group[0x1];
8649 struct mlx5_ifc_mcam_access_reg_bits {
8650 u8 reserved_at_0[0x1c];
8654 u8 reserved_at_1f[0x1];
8656 u8 regs_95_to_64[0x20];
8657 u8 regs_63_to_32[0x20];
8658 u8 regs_31_to_0[0x20];
8661 struct mlx5_ifc_mcam_reg_bits {
8662 u8 reserved_at_0[0x8];
8663 u8 feature_group[0x8];
8664 u8 reserved_at_10[0x8];
8665 u8 access_reg_group[0x8];
8667 u8 reserved_at_20[0x20];
8670 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8671 u8 reserved_at_0[0x80];
8672 } mng_access_reg_cap_mask;
8674 u8 reserved_at_c0[0x80];
8677 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8678 u8 reserved_at_0[0x80];
8679 } mng_feature_cap_mask;
8681 u8 reserved_at_1c0[0x80];
8684 struct mlx5_ifc_pcap_reg_bits {
8687 u8 reserved_1[0x10];
8689 u8 port_capability_mask[4][0x20];
8692 struct mlx5_ifc_pbmc_reg_bits {
8695 u8 reserved_1[0x10];
8697 u8 xoff_timer_value[0x10];
8698 u8 xoff_refresh[0x10];
8700 u8 reserved_2[0x10];
8701 u8 port_buffer_size[0x10];
8703 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8705 u8 reserved_3[0x40];
8707 u8 port_shared_buffer[0x40];
8710 struct mlx5_ifc_paos_reg_bits {
8714 u8 admin_status[0x4];
8716 u8 oper_status[0x4];
8720 u8 reserved_2[0x1c];
8723 u8 reserved_3[0x40];
8726 struct mlx5_ifc_pamp_reg_bits {
8728 u8 opamp_group[0x8];
8730 u8 opamp_group_type[0x4];
8732 u8 start_index[0x10];
8734 u8 num_of_indices[0xc];
8736 u8 index_data[18][0x10];
8739 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8740 u8 llr_rx_cells_high[0x20];
8742 u8 llr_rx_cells_low[0x20];
8744 u8 llr_rx_error_high[0x20];
8746 u8 llr_rx_error_low[0x20];
8748 u8 llr_rx_crc_error_high[0x20];
8750 u8 llr_rx_crc_error_low[0x20];
8752 u8 llr_tx_cells_high[0x20];
8754 u8 llr_tx_cells_low[0x20];
8756 u8 llr_tx_ret_cells_high[0x20];
8758 u8 llr_tx_ret_cells_low[0x20];
8760 u8 llr_tx_ret_events_high[0x20];
8762 u8 llr_tx_ret_events_low[0x20];
8764 u8 reserved_0[0x640];
8767 struct mlx5_ifc_mtmp_reg_bits {
8769 u8 reserved_at_1[0x18];
8770 u8 sensor_index[0x7];
8772 u8 reserved_at_20[0x10];
8773 u8 temperature[0x10];
8777 u8 reserved_at_42[0x0e];
8778 u8 max_temperature[0x10];
8781 u8 reserved_at_62[0x0e];
8782 u8 temperature_threshold_hi[0x10];
8784 u8 reserved_at_80[0x10];
8785 u8 temperature_threshold_lo[0x10];
8787 u8 reserved_at_100[0x20];
8789 u8 sensor_name[0x40];
8792 struct mlx5_ifc_lane_2_module_mapping_bits {
8801 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8802 u8 transmit_queue_high[0x20];
8804 u8 transmit_queue_low[0x20];
8806 u8 reserved_0[0x780];
8809 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8810 u8 no_buffer_discard_uc_high[0x20];
8812 u8 no_buffer_discard_uc_low[0x20];
8814 u8 wred_discard_high[0x20];
8816 u8 wred_discard_low[0x20];
8818 u8 reserved_0[0x740];
8821 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8822 u8 rx_octets_high[0x20];
8824 u8 rx_octets_low[0x20];
8826 u8 reserved_0[0xc0];
8828 u8 rx_frames_high[0x20];
8830 u8 rx_frames_low[0x20];
8832 u8 tx_octets_high[0x20];
8834 u8 tx_octets_low[0x20];
8836 u8 reserved_1[0xc0];
8838 u8 tx_frames_high[0x20];
8840 u8 tx_frames_low[0x20];
8842 u8 rx_pause_high[0x20];
8844 u8 rx_pause_low[0x20];
8846 u8 rx_pause_duration_high[0x20];
8848 u8 rx_pause_duration_low[0x20];
8850 u8 tx_pause_high[0x20];
8852 u8 tx_pause_low[0x20];
8854 u8 tx_pause_duration_high[0x20];
8856 u8 tx_pause_duration_low[0x20];
8858 u8 rx_pause_transition_high[0x20];
8860 u8 rx_pause_transition_low[0x20];
8862 u8 rx_discards_high[0x20];
8864 u8 rx_discards_low[0x20];
8866 u8 device_stall_minor_watermark_cnt_high[0x20];
8868 u8 device_stall_minor_watermark_cnt_low[0x20];
8870 u8 device_stall_critical_watermark_cnt_high[0x20];
8872 u8 device_stall_critical_watermark_cnt_low[0x20];
8874 u8 reserved_2[0x340];
8877 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8878 u8 port_transmit_wait_high[0x20];
8880 u8 port_transmit_wait_low[0x20];
8882 u8 ecn_marked_high[0x20];
8884 u8 ecn_marked_low[0x20];
8886 u8 no_buffer_discard_mc_high[0x20];
8888 u8 no_buffer_discard_mc_low[0x20];
8890 u8 rx_ebp_high[0x20];
8892 u8 rx_ebp_low[0x20];
8894 u8 tx_ebp_high[0x20];
8896 u8 tx_ebp_low[0x20];
8898 u8 rx_buffer_almost_full_high[0x20];
8900 u8 rx_buffer_almost_full_low[0x20];
8902 u8 rx_buffer_full_high[0x20];
8904 u8 rx_buffer_full_low[0x20];
8906 u8 rx_icrc_encapsulated_high[0x20];
8908 u8 rx_icrc_encapsulated_low[0x20];
8910 u8 reserved_0[0x80];
8912 u8 tx_stats_pkts64octets_high[0x20];
8914 u8 tx_stats_pkts64octets_low[0x20];
8916 u8 tx_stats_pkts65to127octets_high[0x20];
8918 u8 tx_stats_pkts65to127octets_low[0x20];
8920 u8 tx_stats_pkts128to255octets_high[0x20];
8922 u8 tx_stats_pkts128to255octets_low[0x20];
8924 u8 tx_stats_pkts256to511octets_high[0x20];
8926 u8 tx_stats_pkts256to511octets_low[0x20];
8928 u8 tx_stats_pkts512to1023octets_high[0x20];
8930 u8 tx_stats_pkts512to1023octets_low[0x20];
8932 u8 tx_stats_pkts1024to1518octets_high[0x20];
8934 u8 tx_stats_pkts1024to1518octets_low[0x20];
8936 u8 tx_stats_pkts1519to2047octets_high[0x20];
8938 u8 tx_stats_pkts1519to2047octets_low[0x20];
8940 u8 tx_stats_pkts2048to4095octets_high[0x20];
8942 u8 tx_stats_pkts2048to4095octets_low[0x20];
8944 u8 tx_stats_pkts4096to8191octets_high[0x20];
8946 u8 tx_stats_pkts4096to8191octets_low[0x20];
8948 u8 tx_stats_pkts8192to10239octets_high[0x20];
8950 u8 tx_stats_pkts8192to10239octets_low[0x20];
8952 u8 reserved_1[0x2C0];
8955 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8956 u8 a_frames_transmitted_ok_high[0x20];
8958 u8 a_frames_transmitted_ok_low[0x20];
8960 u8 a_frames_received_ok_high[0x20];
8962 u8 a_frames_received_ok_low[0x20];
8964 u8 a_frame_check_sequence_errors_high[0x20];
8966 u8 a_frame_check_sequence_errors_low[0x20];
8968 u8 a_alignment_errors_high[0x20];
8970 u8 a_alignment_errors_low[0x20];
8972 u8 a_octets_transmitted_ok_high[0x20];
8974 u8 a_octets_transmitted_ok_low[0x20];
8976 u8 a_octets_received_ok_high[0x20];
8978 u8 a_octets_received_ok_low[0x20];
8980 u8 a_multicast_frames_xmitted_ok_high[0x20];
8982 u8 a_multicast_frames_xmitted_ok_low[0x20];
8984 u8 a_broadcast_frames_xmitted_ok_high[0x20];
8986 u8 a_broadcast_frames_xmitted_ok_low[0x20];
8988 u8 a_multicast_frames_received_ok_high[0x20];
8990 u8 a_multicast_frames_received_ok_low[0x20];
8992 u8 a_broadcast_frames_recieved_ok_high[0x20];
8994 u8 a_broadcast_frames_recieved_ok_low[0x20];
8996 u8 a_in_range_length_errors_high[0x20];
8998 u8 a_in_range_length_errors_low[0x20];
9000 u8 a_out_of_range_length_field_high[0x20];
9002 u8 a_out_of_range_length_field_low[0x20];
9004 u8 a_frame_too_long_errors_high[0x20];
9006 u8 a_frame_too_long_errors_low[0x20];
9008 u8 a_symbol_error_during_carrier_high[0x20];
9010 u8 a_symbol_error_during_carrier_low[0x20];
9012 u8 a_mac_control_frames_transmitted_high[0x20];
9014 u8 a_mac_control_frames_transmitted_low[0x20];
9016 u8 a_mac_control_frames_received_high[0x20];
9018 u8 a_mac_control_frames_received_low[0x20];
9020 u8 a_unsupported_opcodes_received_high[0x20];
9022 u8 a_unsupported_opcodes_received_low[0x20];
9024 u8 a_pause_mac_ctrl_frames_received_high[0x20];
9026 u8 a_pause_mac_ctrl_frames_received_low[0x20];
9028 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
9030 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
9032 u8 reserved_0[0x300];
9035 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9036 u8 dot3stats_alignment_errors_high[0x20];
9038 u8 dot3stats_alignment_errors_low[0x20];
9040 u8 dot3stats_fcs_errors_high[0x20];
9042 u8 dot3stats_fcs_errors_low[0x20];
9044 u8 dot3stats_single_collision_frames_high[0x20];
9046 u8 dot3stats_single_collision_frames_low[0x20];
9048 u8 dot3stats_multiple_collision_frames_high[0x20];
9050 u8 dot3stats_multiple_collision_frames_low[0x20];
9052 u8 dot3stats_sqe_test_errors_high[0x20];
9054 u8 dot3stats_sqe_test_errors_low[0x20];
9056 u8 dot3stats_deferred_transmissions_high[0x20];
9058 u8 dot3stats_deferred_transmissions_low[0x20];
9060 u8 dot3stats_late_collisions_high[0x20];
9062 u8 dot3stats_late_collisions_low[0x20];
9064 u8 dot3stats_excessive_collisions_high[0x20];
9066 u8 dot3stats_excessive_collisions_low[0x20];
9068 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
9070 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
9072 u8 dot3stats_carrier_sense_errors_high[0x20];
9074 u8 dot3stats_carrier_sense_errors_low[0x20];
9076 u8 dot3stats_frame_too_longs_high[0x20];
9078 u8 dot3stats_frame_too_longs_low[0x20];
9080 u8 dot3stats_internal_mac_receive_errors_high[0x20];
9082 u8 dot3stats_internal_mac_receive_errors_low[0x20];
9084 u8 dot3stats_symbol_errors_high[0x20];
9086 u8 dot3stats_symbol_errors_low[0x20];
9088 u8 dot3control_in_unknown_opcodes_high[0x20];
9090 u8 dot3control_in_unknown_opcodes_low[0x20];
9092 u8 dot3in_pause_frames_high[0x20];
9094 u8 dot3in_pause_frames_low[0x20];
9096 u8 dot3out_pause_frames_high[0x20];
9098 u8 dot3out_pause_frames_low[0x20];
9100 u8 reserved_0[0x3c0];
9103 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9104 u8 if_in_octets_high[0x20];
9106 u8 if_in_octets_low[0x20];
9108 u8 if_in_ucast_pkts_high[0x20];
9110 u8 if_in_ucast_pkts_low[0x20];
9112 u8 if_in_discards_high[0x20];
9114 u8 if_in_discards_low[0x20];
9116 u8 if_in_errors_high[0x20];
9118 u8 if_in_errors_low[0x20];
9120 u8 if_in_unknown_protos_high[0x20];
9122 u8 if_in_unknown_protos_low[0x20];
9124 u8 if_out_octets_high[0x20];
9126 u8 if_out_octets_low[0x20];
9128 u8 if_out_ucast_pkts_high[0x20];
9130 u8 if_out_ucast_pkts_low[0x20];
9132 u8 if_out_discards_high[0x20];
9134 u8 if_out_discards_low[0x20];
9136 u8 if_out_errors_high[0x20];
9138 u8 if_out_errors_low[0x20];
9140 u8 if_in_multicast_pkts_high[0x20];
9142 u8 if_in_multicast_pkts_low[0x20];
9144 u8 if_in_broadcast_pkts_high[0x20];
9146 u8 if_in_broadcast_pkts_low[0x20];
9148 u8 if_out_multicast_pkts_high[0x20];
9150 u8 if_out_multicast_pkts_low[0x20];
9152 u8 if_out_broadcast_pkts_high[0x20];
9154 u8 if_out_broadcast_pkts_low[0x20];
9156 u8 reserved_0[0x480];
9159 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9160 u8 ether_stats_drop_events_high[0x20];
9162 u8 ether_stats_drop_events_low[0x20];
9164 u8 ether_stats_octets_high[0x20];
9166 u8 ether_stats_octets_low[0x20];
9168 u8 ether_stats_pkts_high[0x20];
9170 u8 ether_stats_pkts_low[0x20];
9172 u8 ether_stats_broadcast_pkts_high[0x20];
9174 u8 ether_stats_broadcast_pkts_low[0x20];
9176 u8 ether_stats_multicast_pkts_high[0x20];
9178 u8 ether_stats_multicast_pkts_low[0x20];
9180 u8 ether_stats_crc_align_errors_high[0x20];
9182 u8 ether_stats_crc_align_errors_low[0x20];
9184 u8 ether_stats_undersize_pkts_high[0x20];
9186 u8 ether_stats_undersize_pkts_low[0x20];
9188 u8 ether_stats_oversize_pkts_high[0x20];
9190 u8 ether_stats_oversize_pkts_low[0x20];
9192 u8 ether_stats_fragments_high[0x20];
9194 u8 ether_stats_fragments_low[0x20];
9196 u8 ether_stats_jabbers_high[0x20];
9198 u8 ether_stats_jabbers_low[0x20];
9200 u8 ether_stats_collisions_high[0x20];
9202 u8 ether_stats_collisions_low[0x20];
9204 u8 ether_stats_pkts64octets_high[0x20];
9206 u8 ether_stats_pkts64octets_low[0x20];
9208 u8 ether_stats_pkts65to127octets_high[0x20];
9210 u8 ether_stats_pkts65to127octets_low[0x20];
9212 u8 ether_stats_pkts128to255octets_high[0x20];
9214 u8 ether_stats_pkts128to255octets_low[0x20];
9216 u8 ether_stats_pkts256to511octets_high[0x20];
9218 u8 ether_stats_pkts256to511octets_low[0x20];
9220 u8 ether_stats_pkts512to1023octets_high[0x20];
9222 u8 ether_stats_pkts512to1023octets_low[0x20];
9224 u8 ether_stats_pkts1024to1518octets_high[0x20];
9226 u8 ether_stats_pkts1024to1518octets_low[0x20];
9228 u8 ether_stats_pkts1519to2047octets_high[0x20];
9230 u8 ether_stats_pkts1519to2047octets_low[0x20];
9232 u8 ether_stats_pkts2048to4095octets_high[0x20];
9234 u8 ether_stats_pkts2048to4095octets_low[0x20];
9236 u8 ether_stats_pkts4096to8191octets_high[0x20];
9238 u8 ether_stats_pkts4096to8191octets_low[0x20];
9240 u8 ether_stats_pkts8192to10239octets_high[0x20];
9242 u8 ether_stats_pkts8192to10239octets_low[0x20];
9244 u8 reserved_0[0x280];
9247 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9248 u8 symbol_error_counter[0x10];
9249 u8 link_error_recovery_counter[0x8];
9250 u8 link_downed_counter[0x8];
9252 u8 port_rcv_errors[0x10];
9253 u8 port_rcv_remote_physical_errors[0x10];
9255 u8 port_rcv_switch_relay_errors[0x10];
9256 u8 port_xmit_discards[0x10];
9258 u8 port_xmit_constraint_errors[0x8];
9259 u8 port_rcv_constraint_errors[0x8];
9261 u8 local_link_integrity_errors[0x4];
9262 u8 excessive_buffer_overrun_errors[0x4];
9264 u8 reserved_1[0x10];
9265 u8 vl_15_dropped[0x10];
9267 u8 port_xmit_data[0x20];
9269 u8 port_rcv_data[0x20];
9271 u8 port_xmit_pkts[0x20];
9273 u8 port_rcv_pkts[0x20];
9275 u8 port_xmit_wait[0x20];
9277 u8 reserved_2[0x680];
9280 struct mlx5_ifc_trc_tlb_reg_bits {
9281 u8 reserved_0[0x80];
9283 u8 tlb_addr[0][0x40];
9286 struct mlx5_ifc_trc_read_fifo_reg_bits {
9287 u8 reserved_0[0x10];
9288 u8 requested_event_num[0x10];
9290 u8 reserved_1[0x20];
9292 u8 reserved_2[0x10];
9293 u8 acual_event_num[0x10];
9295 u8 reserved_3[0x20];
9300 struct mlx5_ifc_trc_lock_reg_bits {
9301 u8 reserved_0[0x1f];
9304 u8 reserved_1[0x60];
9307 struct mlx5_ifc_trc_filter_reg_bits {
9310 u8 filter_index[0x10];
9312 u8 reserved_1[0x20];
9314 u8 filter_val[0x20];
9316 u8 reserved_2[0x1a0];
9319 struct mlx5_ifc_trc_event_reg_bits {
9322 u8 event_index[0x10];
9324 u8 reserved_1[0x20];
9328 u8 event_selector_val[0x10];
9329 u8 event_selector_size[0x10];
9331 u8 reserved_2[0x180];
9334 struct mlx5_ifc_trc_conf_reg_bits {
9338 u8 reserved_1[0x15];
9341 u8 reserved_2[0x20];
9343 u8 limit_event_index[0x20];
9347 u8 fifo_ready_ev_num[0x20];
9349 u8 reserved_3[0x160];
9352 struct mlx5_ifc_trc_cap_reg_bits {
9353 u8 reserved_0[0x18];
9356 u8 reserved_1[0x20];
9358 u8 num_of_events[0x10];
9359 u8 num_of_filters[0x10];
9364 u8 event_size[0x10];
9366 u8 reserved_2[0x160];
9369 struct mlx5_ifc_set_node_in_bits {
9370 u8 node_description[64][0x8];
9373 struct mlx5_ifc_register_power_settings_bits {
9374 u8 reserved_0[0x18];
9375 u8 power_settings_level[0x8];
9377 u8 reserved_1[0x60];
9380 struct mlx5_ifc_register_host_endianess_bits {
9382 u8 reserved_0[0x1f];
9384 u8 reserved_1[0x60];
9387 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9388 u8 physical_address[0x40];
9391 struct mlx5_ifc_qtct_reg_bits {
9392 u8 operation_type[0x2];
9393 u8 cap_local_admin[0x1];
9394 u8 cap_remote_admin[0x1];
9396 u8 port_number[0x8];
9400 u8 reserved_2[0x1d];
9404 struct mlx5_ifc_qpdp_reg_bits {
9406 u8 port_number[0x8];
9407 u8 reserved_1[0x10];
9409 u8 reserved_2[0x1d];
9413 struct mlx5_ifc_port_info_ro_fields_param_bits {
9418 u8 reserved_1[0x20];
9423 struct mlx5_ifc_nvqc_reg_bits {
9426 u8 reserved_0[0x18];
9433 struct mlx5_ifc_nvia_reg_bits {
9434 u8 reserved_0[0x1d];
9437 u8 reserved_1[0x20];
9440 struct mlx5_ifc_nvdi_reg_bits {
9441 struct mlx5_ifc_config_item_bits configuration_item_header;
9444 struct mlx5_ifc_nvda_reg_bits {
9445 struct mlx5_ifc_config_item_bits configuration_item_header;
9447 u8 configuration_item_data[0x20];
9450 struct mlx5_ifc_node_info_ro_fields_param_bits {
9451 u8 system_image_guid[0x40];
9453 u8 reserved_0[0x40];
9457 u8 reserved_1[0x10];
9460 u8 reserved_2[0x20];
9463 struct mlx5_ifc_ets_tcn_config_reg_bits {
9470 u8 bw_allocation[0x7];
9473 u8 max_bw_units[0x4];
9475 u8 max_bw_value[0x8];
9478 struct mlx5_ifc_ets_global_config_reg_bits {
9481 u8 reserved_1[0x1d];
9484 u8 max_bw_units[0x4];
9486 u8 max_bw_value[0x8];
9489 struct mlx5_ifc_qetc_reg_bits {
9490 u8 reserved_at_0[0x8];
9491 u8 port_number[0x8];
9492 u8 reserved_at_10[0x30];
9494 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9495 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9498 struct mlx5_ifc_nodnic_mac_filters_bits {
9499 struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9501 struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9503 struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9505 struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9507 struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9509 u8 reserved_0[0xc0];
9512 struct mlx5_ifc_nodnic_gid_filters_bits {
9513 u8 mgid_filter0[16][0x8];
9515 u8 mgid_filter1[16][0x8];
9517 u8 mgid_filter2[16][0x8];
9519 u8 mgid_filter3[16][0x8];
9523 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0,
9524 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1,
9528 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0,
9529 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1,
9532 struct mlx5_ifc_nodnic_config_reg_bits {
9533 u8 no_dram_nic_revision[0x8];
9534 u8 hardware_format[0x8];
9535 u8 support_receive_filter[0x1];
9536 u8 support_promisc_filter[0x1];
9537 u8 support_promisc_multicast_filter[0x1];
9539 u8 log_working_buffer_size[0x3];
9540 u8 log_pkey_table_size[0x4];
9545 u8 log_max_ring_size[0x6];
9546 u8 reserved_3[0x18];
9551 u8 reserved_4[0x1c];
9555 u8 reserved_5[0x740];
9557 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9559 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9562 struct mlx5_ifc_vlan_layout_bits {
9563 u8 reserved_0[0x14];
9566 u8 reserved_1[0x20];
9569 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9570 u8 reserved_0[0x20];
9574 u8 addressh_63_32[0x20];
9576 u8 addressl_31_0[0x20];
9579 struct mlx5_ifc_ud_adrs_vector_bits {
9584 u8 destination_qp_dct[0x18];
9586 u8 static_rate[0x4];
9587 u8 sl_eth_prio[0x4];
9590 u8 rlid_udp_sport[0x10];
9592 u8 reserved_1[0x20];
9594 u8 rmac_47_16[0x20];
9603 u8 src_addr_index[0x8];
9604 u8 flow_label[0x14];
9606 u8 rgid_rip[16][0x8];
9609 struct mlx5_ifc_port_module_event_bits {
9613 u8 module_status[0x4];
9615 u8 reserved_2[0x14];
9619 u8 reserved_4[0xa0];
9622 struct mlx5_ifc_icmd_control_bits {
9629 struct mlx5_ifc_eqe_bits {
9633 u8 event_sub_type[0x8];
9635 u8 reserved_2[0xe0];
9637 union mlx5_ifc_event_auto_bits event_data;
9639 u8 reserved_3[0x10];
9646 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9649 struct mlx5_ifc_cmd_queue_entry_bits {
9651 u8 reserved_0[0x18];
9653 u8 input_length[0x20];
9655 u8 input_mailbox_pointer_63_32[0x20];
9657 u8 input_mailbox_pointer_31_9[0x17];
9660 u8 command_input_inline_data[16][0x8];
9662 u8 command_output_inline_data[16][0x8];
9664 u8 output_mailbox_pointer_63_32[0x20];
9666 u8 output_mailbox_pointer_31_9[0x17];
9669 u8 output_length[0x20];
9678 struct mlx5_ifc_cmd_out_bits {
9680 u8 reserved_0[0x18];
9684 u8 command_output[0x20];
9687 struct mlx5_ifc_cmd_in_bits {
9689 u8 reserved_0[0x10];
9691 u8 reserved_1[0x10];
9694 u8 command[0][0x20];
9697 struct mlx5_ifc_cmd_if_box_bits {
9698 u8 mailbox_data[512][0x8];
9700 u8 reserved_0[0x180];
9702 u8 next_pointer_63_32[0x20];
9704 u8 next_pointer_31_10[0x16];
9707 u8 block_number[0x20];
9711 u8 ctrl_signature[0x8];
9715 struct mlx5_ifc_mtt_bits {
9716 u8 ptag_63_32[0x20];
9724 /* Vendor Specific Capabilities, VSC */
9726 MLX5_VSC_DOMAIN_ICMD = 0x1,
9727 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6,
9728 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA,
9731 struct mlx5_ifc_vendor_specific_cap_bits {
9734 u8 next_pointer[0x8];
9735 u8 capability_id[0x8];
9753 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9754 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9755 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9759 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9760 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9761 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9765 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
9766 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
9767 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
9768 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
9769 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
9770 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
9771 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
9772 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
9773 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
9774 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
9775 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10,
9778 struct mlx5_ifc_initial_seg_bits {
9779 u8 fw_rev_minor[0x10];
9780 u8 fw_rev_major[0x10];
9782 u8 cmd_interface_rev[0x10];
9783 u8 fw_rev_subminor[0x10];
9785 u8 reserved_0[0x40];
9787 u8 cmdq_phy_addr_63_32[0x20];
9789 u8 cmdq_phy_addr_31_12[0x14];
9791 u8 nic_interface[0x2];
9792 u8 log_cmdq_size[0x4];
9793 u8 log_cmdq_stride[0x4];
9795 u8 command_doorbell_vector[0x20];
9797 u8 reserved_2[0xf00];
9799 u8 initializing[0x1];
9801 u8 nic_interface_supported[0x3];
9802 u8 reserved_4[0x18];
9804 struct mlx5_ifc_health_buffer_bits health_buffer;
9806 u8 no_dram_nic_offset[0x20];
9808 u8 reserved_5[0x6de0];
9810 u8 internal_timer_h[0x20];
9812 u8 internal_timer_l[0x20];
9814 u8 reserved_6[0x20];
9816 u8 reserved_7[0x1f];
9819 u8 health_syndrome[0x8];
9820 u8 health_counter[0x18];
9822 u8 reserved_8[0x17fc0];
9825 union mlx5_ifc_icmd_interface_document_bits {
9826 struct mlx5_ifc_fw_version_bits fw_version;
9827 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9828 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9829 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9830 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9831 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9832 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9833 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9834 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9835 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9836 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9837 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9838 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9839 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9840 u8 reserved_0[0x42c0];
9843 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9844 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9845 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9846 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9847 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9848 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9849 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9850 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9851 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9852 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9853 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9854 u8 reserved_0[0x7c0];
9857 struct mlx5_ifc_ppcnt_reg_bits {
9865 u8 reserved_1[0x1c];
9868 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9871 struct mlx5_ifc_pcie_lanes_counters_bits {
9872 u8 life_time_counter_high[0x20];
9874 u8 life_time_counter_low[0x20];
9876 u8 error_counter_lane0[0x20];
9878 u8 error_counter_lane1[0x20];
9880 u8 error_counter_lane2[0x20];
9882 u8 error_counter_lane3[0x20];
9884 u8 error_counter_lane4[0x20];
9886 u8 error_counter_lane5[0x20];
9888 u8 error_counter_lane6[0x20];
9890 u8 error_counter_lane7[0x20];
9892 u8 error_counter_lane8[0x20];
9894 u8 error_counter_lane9[0x20];
9896 u8 error_counter_lane10[0x20];
9898 u8 error_counter_lane11[0x20];
9900 u8 error_counter_lane12[0x20];
9902 u8 error_counter_lane13[0x20];
9904 u8 error_counter_lane14[0x20];
9906 u8 error_counter_lane15[0x20];
9908 u8 reserved_at_240[0x580];
9911 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
9912 u8 reserved_at_0[0x40];
9914 u8 error_counter_lane0[0x20];
9916 u8 error_counter_lane1[0x20];
9918 u8 error_counter_lane2[0x20];
9920 u8 error_counter_lane3[0x20];
9922 u8 error_counter_lane4[0x20];
9924 u8 error_counter_lane5[0x20];
9926 u8 error_counter_lane6[0x20];
9928 u8 error_counter_lane7[0x20];
9930 u8 error_counter_lane8[0x20];
9932 u8 error_counter_lane9[0x20];
9934 u8 error_counter_lane10[0x20];
9936 u8 error_counter_lane11[0x20];
9938 u8 error_counter_lane12[0x20];
9940 u8 error_counter_lane13[0x20];
9942 u8 error_counter_lane14[0x20];
9944 u8 error_counter_lane15[0x20];
9946 u8 reserved_at_240[0x580];
9949 struct mlx5_ifc_pcie_perf_counters_bits {
9950 u8 life_time_counter_high[0x20];
9952 u8 life_time_counter_low[0x20];
9958 u8 l0_to_recovery_eieos[0x20];
9960 u8 l0_to_recovery_ts[0x20];
9962 u8 l0_to_recovery_framing[0x20];
9964 u8 l0_to_recovery_retrain[0x20];
9966 u8 crc_error_dllp[0x20];
9968 u8 crc_error_tlp[0x20];
9970 u8 tx_overflow_buffer_pkt[0x40];
9972 u8 outbound_stalled_reads[0x20];
9974 u8 outbound_stalled_writes[0x20];
9976 u8 outbound_stalled_reads_events[0x20];
9978 u8 outbound_stalled_writes_events[0x20];
9980 u8 tx_overflow_buffer_marked_pkt[0x40];
9982 u8 reserved_at_240[0x580];
9985 struct mlx5_ifc_pcie_perf_counters_ext_bits {
9986 u8 reserved_at_0[0x40];
9992 u8 reserved_at_80[0xc0];
9994 u8 tx_overflow_buffer_pkt[0x40];
9996 u8 outbound_stalled_reads[0x20];
9998 u8 outbound_stalled_writes[0x20];
10000 u8 outbound_stalled_reads_events[0x20];
10002 u8 outbound_stalled_writes_events[0x20];
10004 u8 tx_overflow_buffer_marked_pkt[0x40];
10006 u8 reserved_at_240[0x580];
10009 struct mlx5_ifc_pcie_timers_states_bits {
10010 u8 life_time_counter_high[0x20];
10012 u8 life_time_counter_low[0x20];
10014 u8 time_to_boot_image_start[0x20];
10016 u8 time_to_link_image[0x20];
10018 u8 calibration_time[0x20];
10020 u8 time_to_first_perst[0x20];
10022 u8 time_to_detect_state[0x20];
10024 u8 time_to_l0[0x20];
10026 u8 time_to_crs_en[0x20];
10028 u8 time_to_plastic_image_start[0x20];
10030 u8 time_to_iron_image_start[0x20];
10032 u8 perst_handler[0x20];
10034 u8 times_in_l1[0x20];
10036 u8 times_in_l23[0x20];
10040 u8 config_cycle1usec[0x20];
10042 u8 config_cycle2to7usec[0x20];
10044 u8 config_cycle8to15usec[0x20];
10046 u8 config_cycle16to63usec[0x20];
10048 u8 config_cycle64usec[0x20];
10050 u8 correctable_err_msg_sent[0x20];
10052 u8 non_fatal_err_msg_sent[0x20];
10054 u8 fatal_err_msg_sent[0x20];
10056 u8 reserved_at_2e0[0x4e0];
10059 struct mlx5_ifc_pcie_timers_states_ext_bits {
10060 u8 reserved_at_0[0x40];
10062 u8 time_to_boot_image_start[0x20];
10064 u8 time_to_link_image[0x20];
10066 u8 calibration_time[0x20];
10068 u8 time_to_first_perst[0x20];
10070 u8 time_to_detect_state[0x20];
10072 u8 time_to_l0[0x20];
10074 u8 time_to_crs_en[0x20];
10076 u8 time_to_plastic_image_start[0x20];
10078 u8 time_to_iron_image_start[0x20];
10080 u8 perst_handler[0x20];
10082 u8 times_in_l1[0x20];
10084 u8 times_in_l23[0x20];
10088 u8 config_cycle1usec[0x20];
10090 u8 config_cycle2to7usec[0x20];
10092 u8 config_cycle8to15usec[0x20];
10094 u8 config_cycle16to63usec[0x20];
10096 u8 config_cycle64usec[0x20];
10098 u8 correctable_err_msg_sent[0x20];
10100 u8 non_fatal_err_msg_sent[0x20];
10102 u8 fatal_err_msg_sent[0x20];
10104 u8 reserved_at_2e0[0x4e0];
10107 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10108 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10109 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10110 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10111 u8 reserved_at_0[0x7c0];
10114 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10115 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10116 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10117 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10118 u8 reserved_at_0[0x7c0];
10121 struct mlx5_ifc_mpcnt_reg_bits {
10122 u8 reserved_at_0[0x2];
10124 u8 pcie_index[0x8];
10126 u8 reserved_at_18[0x2];
10130 u8 reserved_at_21[0x1f];
10132 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10135 struct mlx5_ifc_mpcnt_reg_ext_bits {
10136 u8 reserved_at_0[0x2];
10138 u8 pcie_index[0x8];
10140 u8 reserved_at_18[0x2];
10144 u8 reserved_at_21[0x1f];
10146 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10150 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10151 MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10152 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10153 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10156 struct mlx5_ifc_mpein_reg_bits {
10157 u8 reserved_at_0[0x2];
10159 u8 pcie_index[0x8];
10161 u8 reserved_at_18[0x8];
10163 u8 capability_mask[0x20];
10165 u8 reserved_at_40[0x8];
10166 u8 link_width_enabled[0x8];
10167 u8 link_speed_enabled[0x10];
10169 u8 lane0_physical_position[0x8];
10170 u8 link_width_active[0x8];
10171 u8 link_speed_active[0x10];
10173 u8 num_of_pfs[0x10];
10174 u8 num_of_vfs[0x10];
10177 u8 reserved_at_b0[0x10];
10179 u8 max_read_request_size[0x4];
10180 u8 max_payload_size[0x4];
10181 u8 reserved_at_c8[0x5];
10182 u8 pwr_status[0x3];
10184 u8 reserved_at_d4[0xb];
10185 u8 lane_reversal[0x1];
10187 u8 reserved_at_e0[0x14];
10190 u8 reserved_at_100[0x20];
10192 u8 device_status[0x10];
10193 u8 port_state[0x8];
10194 u8 reserved_at_138[0x8];
10196 u8 reserved_at_140[0x10];
10197 u8 receiver_detect_result[0x10];
10199 u8 reserved_at_160[0x20];
10202 struct mlx5_ifc_mpein_reg_ext_bits {
10203 u8 reserved_at_0[0x2];
10205 u8 pcie_index[0x8];
10207 u8 reserved_at_18[0x8];
10209 u8 reserved_at_20[0x20];
10211 u8 reserved_at_40[0x8];
10212 u8 link_width_enabled[0x8];
10213 u8 link_speed_enabled[0x10];
10215 u8 lane0_physical_position[0x8];
10216 u8 link_width_active[0x8];
10217 u8 link_speed_active[0x10];
10219 u8 num_of_pfs[0x10];
10220 u8 num_of_vfs[0x10];
10223 u8 reserved_at_b0[0x10];
10225 u8 max_read_request_size[0x4];
10226 u8 max_payload_size[0x4];
10227 u8 reserved_at_c8[0x5];
10228 u8 pwr_status[0x3];
10230 u8 reserved_at_d4[0xb];
10231 u8 lane_reversal[0x1];
10234 struct mlx5_ifc_mcqi_cap_bits {
10235 u8 supported_info_bitmask[0x20];
10237 u8 component_size[0x20];
10239 u8 max_component_size[0x20];
10241 u8 log_mcda_word_size[0x4];
10242 u8 reserved_at_64[0xc];
10243 u8 mcda_max_write_size[0x10];
10246 u8 reserved_at_81[0x1];
10247 u8 match_chip_id[0x1];
10248 u8 match_psid[0x1];
10249 u8 check_user_timestamp[0x1];
10250 u8 match_base_guid_mac[0x1];
10251 u8 reserved_at_86[0x1a];
10254 struct mlx5_ifc_mcqi_reg_bits {
10255 u8 read_pending_component[0x1];
10256 u8 reserved_at_1[0xf];
10257 u8 component_index[0x10];
10259 u8 reserved_at_20[0x20];
10261 u8 reserved_at_40[0x1b];
10264 u8 info_size[0x20];
10268 u8 reserved_at_a0[0x10];
10269 u8 data_size[0x10];
10274 struct mlx5_ifc_mcc_reg_bits {
10275 u8 reserved_at_0[0x4];
10276 u8 time_elapsed_since_last_cmd[0xc];
10277 u8 reserved_at_10[0x8];
10278 u8 instruction[0x8];
10280 u8 reserved_at_20[0x10];
10281 u8 component_index[0x10];
10283 u8 reserved_at_40[0x8];
10284 u8 update_handle[0x18];
10286 u8 handle_owner_type[0x4];
10287 u8 handle_owner_host_id[0x4];
10288 u8 reserved_at_68[0x1];
10289 u8 control_progress[0x7];
10290 u8 error_code[0x8];
10291 u8 reserved_at_78[0x4];
10292 u8 control_state[0x4];
10294 u8 component_size[0x20];
10296 u8 reserved_at_a0[0x60];
10299 struct mlx5_ifc_mcda_reg_bits {
10300 u8 reserved_at_0[0x8];
10301 u8 update_handle[0x18];
10305 u8 reserved_at_40[0x10];
10308 u8 reserved_at_60[0x20];
10313 union mlx5_ifc_ports_control_registers_document_bits {
10314 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10315 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10316 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10317 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10318 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10319 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10320 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10321 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10322 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10323 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10324 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10325 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10326 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10327 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10328 struct mlx5_ifc_paos_reg_bits paos_reg;
10329 struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10330 struct mlx5_ifc_pcap_reg_bits pcap_reg;
10331 struct mlx5_ifc_peir_reg_bits peir_reg;
10332 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10333 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10334 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10335 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10336 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10337 struct mlx5_ifc_phrr_reg_bits phrr_reg;
10338 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10339 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10340 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10341 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10342 struct mlx5_ifc_plib_reg_bits plib_reg;
10343 struct mlx5_ifc_pll_status_data_bits pll_status_data;
10344 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10345 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10346 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10347 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10348 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10349 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10350 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10351 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10352 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10353 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10354 struct mlx5_ifc_ppll_reg_bits ppll_reg;
10355 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10356 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10357 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10358 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10359 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10360 struct mlx5_ifc_ptys_reg_bits ptys_reg;
10361 struct mlx5_ifc_pude_reg_bits pude_reg;
10362 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10363 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10364 struct mlx5_ifc_slrp_reg_bits slrp_reg;
10365 struct mlx5_ifc_sltp_reg_bits sltp_reg;
10366 u8 reserved_0[0x7880];
10369 union mlx5_ifc_debug_enhancements_document_bits {
10370 struct mlx5_ifc_health_buffer_bits health_buffer;
10371 u8 reserved_0[0x200];
10374 union mlx5_ifc_no_dram_nic_document_bits {
10375 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10376 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10377 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10378 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10379 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10380 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10381 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10382 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10383 u8 reserved_0[0x3160];
10386 union mlx5_ifc_uplink_pci_interface_document_bits {
10387 struct mlx5_ifc_initial_seg_bits initial_seg;
10388 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10389 u8 reserved_0[0x20120];
10392 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10394 u8 reserved_at_01[0x0b];
10398 struct mlx5_ifc_qpdpm_reg_bits {
10399 u8 reserved_at_0[0x8];
10400 u8 local_port[0x8];
10401 u8 reserved_at_10[0x10];
10402 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10405 struct mlx5_ifc_qpts_reg_bits {
10406 u8 reserved_at_0[0x8];
10407 u8 local_port[0x8];
10408 u8 reserved_at_10[0x2d];
10409 u8 trust_state[0x3];
10412 struct mlx5_ifc_mfrl_reg_bits {
10413 u8 reserved_at_0[0x38];
10414 u8 reset_level[0x8];
10417 #endif /* MLX5_IFC_H */