sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
  32
  33 enum {
  34         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  35         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  36         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  37         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  38         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  39         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  40         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  41         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  42         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  43         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  44         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  45         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  46         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  47         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  48         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  49         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  50         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  51         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  52         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  53         MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
  54         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  56         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  57         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  58         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  59         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  60         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  61         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  62         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  63         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
  64         MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
  65         MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
  66 };
  67
  68 enum {
  69         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  70         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  71         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  72         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  73         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  74 };
  75
  76 enum {
  77         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  78 };
  79
  80 enum {
  81         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  82         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  83 };
  84
  85 enum {
  86         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  87         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  88         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  89         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  90         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  91         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  92         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  93         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  94         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  95         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  96         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  97         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  98         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
  99         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 100         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 101         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 102         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 103         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 104         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 105         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 106         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 107         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 108         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 109         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 110         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 111         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 112         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 113         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 114         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 115         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 116         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 117         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 118         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 119         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 120         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 121         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 122         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 123         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 124         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 125         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 126         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 127         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 128         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 129         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 130         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 131         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 132         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 133         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 134         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 135         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 136         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 137         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 138         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 139         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 140         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 141         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 142         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 143         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 144         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 145         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 146         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 147         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 148         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 149         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 150         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 151         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 152         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 153         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 154         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 155         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 156         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 157         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 158         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 159         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 160         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 161         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 162         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 163         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 164         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 165         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 166         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 167         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 168         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 169         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 170         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 171         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 172         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 173         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 174         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 175         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 176         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 177         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 178         MLX5_CMD_OP_NOP                           = 0x80d,
 179         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 180         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 181         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 182         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 183         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 184         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 185         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 186         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 187         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 188         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 218         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 219         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 220         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 221         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 222         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 223         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 224         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 225         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 226         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 227         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 228         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 229         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 230         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 231         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 232         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 233         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 234         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 235         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 236         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 237         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 238         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 239         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 240         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 241         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 242         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 243         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 244         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 245         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 246         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 247         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 248         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 249         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 250         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 251         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 252         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 253         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 254 };
 255
 256 enum {
 257         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 258         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 259         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 260         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 261         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 262         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 263         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 264         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 265         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 266         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 267         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 268         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 269 };
 270
 271 struct mlx5_ifc_flow_table_fields_supported_bits {
 272         u8         outer_dmac[0x1];
 273         u8         outer_smac[0x1];
 274         u8         outer_ether_type[0x1];
 275         u8         reserved_0[0x1];
 276         u8         outer_first_prio[0x1];
 277         u8         outer_first_cfi[0x1];
 278         u8         outer_first_vid[0x1];
 279         u8         reserved_1[0x1];
 280         u8         outer_second_prio[0x1];
 281         u8         outer_second_cfi[0x1];
 282         u8         outer_second_vid[0x1];
 283         u8         outer_ipv6_flow_label[0x1];
 284         u8         outer_sip[0x1];
 285         u8         outer_dip[0x1];
 286         u8         outer_frag[0x1];
 287         u8         outer_ip_protocol[0x1];
 288         u8         outer_ip_ecn[0x1];
 289         u8         outer_ip_dscp[0x1];
 290         u8         outer_udp_sport[0x1];
 291         u8         outer_udp_dport[0x1];
 292         u8         outer_tcp_sport[0x1];
 293         u8         outer_tcp_dport[0x1];
 294         u8         outer_tcp_flags[0x1];
 295         u8         outer_gre_protocol[0x1];
 296         u8         outer_gre_key[0x1];
 297         u8         outer_vxlan_vni[0x1];
 298         u8         outer_geneve_vni[0x1];
 299         u8         outer_geneve_oam[0x1];
 300         u8         outer_geneve_protocol_type[0x1];
 301         u8         outer_geneve_opt_len[0x1];
 302         u8         reserved_2[0x1];
 303         u8         source_eswitch_port[0x1];
 304
 305         u8         inner_dmac[0x1];
 306         u8         inner_smac[0x1];
 307         u8         inner_ether_type[0x1];
 308         u8         reserved_3[0x1];
 309         u8         inner_first_prio[0x1];
 310         u8         inner_first_cfi[0x1];
 311         u8         inner_first_vid[0x1];
 312         u8         reserved_4[0x1];
 313         u8         inner_second_prio[0x1];
 314         u8         inner_second_cfi[0x1];
 315         u8         inner_second_vid[0x1];
 316         u8         inner_ipv6_flow_label[0x1];
 317         u8         inner_sip[0x1];
 318         u8         inner_dip[0x1];
 319         u8         inner_frag[0x1];
 320         u8         inner_ip_protocol[0x1];
 321         u8         inner_ip_ecn[0x1];
 322         u8         inner_ip_dscp[0x1];
 323         u8         inner_udp_sport[0x1];
 324         u8         inner_udp_dport[0x1];
 325         u8         inner_tcp_sport[0x1];
 326         u8         inner_tcp_dport[0x1];
 327         u8         inner_tcp_flags[0x1];
 328         u8         reserved_5[0x9];
 329
 330         u8         reserved_6[0x1a];
 331         u8         bth_dst_qp[0x1];
 332         u8         reserved_7[0x4];
 333         u8         source_sqn[0x1];
 334
 335         u8         reserved_8[0x20];
 336 };
 337
 338 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 339         u8         ingress_general_high[0x20];
 340
 341         u8         ingress_general_low[0x20];
 342
 343         u8         ingress_policy_engine_high[0x20];
 344
 345         u8         ingress_policy_engine_low[0x20];
 346
 347         u8         ingress_vlan_membership_high[0x20];
 348
 349         u8         ingress_vlan_membership_low[0x20];
 350
 351         u8         ingress_tag_frame_type_high[0x20];
 352
 353         u8         ingress_tag_frame_type_low[0x20];
 354
 355         u8         egress_vlan_membership_high[0x20];
 356
 357         u8         egress_vlan_membership_low[0x20];
 358
 359         u8         loopback_filter_high[0x20];
 360
 361         u8         loopback_filter_low[0x20];
 362
 363         u8         egress_general_high[0x20];
 364
 365         u8         egress_general_low[0x20];
 366
 367         u8         reserved_at_1c0[0x40];
 368
 369         u8         egress_hoq_high[0x20];
 370
 371         u8         egress_hoq_low[0x20];
 372
 373         u8         port_isolation_high[0x20];
 374
 375         u8         port_isolation_low[0x20];
 376
 377         u8         egress_policy_engine_high[0x20];
 378
 379         u8         egress_policy_engine_low[0x20];
 380
 381         u8         ingress_tx_link_down_high[0x20];
 382
 383         u8         ingress_tx_link_down_low[0x20];
 384
 385         u8         egress_stp_filter_high[0x20];
 386
 387         u8         egress_stp_filter_low[0x20];
 388
 389         u8         egress_hoq_stall_high[0x20];
 390
 391         u8         egress_hoq_stall_low[0x20];
 392
 393         u8         reserved_at_340[0x440];
 394 };
 395 struct mlx5_ifc_flow_table_prop_layout_bits {
 396         u8         ft_support[0x1];
 397         u8         flow_tag[0x1];
 398         u8         flow_counter[0x1];
 399         u8         flow_modify_en[0x1];
 400         u8         modify_root[0x1];
 401         u8         identified_miss_table[0x1];
 402         u8         flow_table_modify[0x1];
 403         u8         encap[0x1];
 404         u8         decap[0x1];
 405         u8         reset_root_to_default[0x1];
 406         u8         reserved_at_a[0x16];
 407
 408         u8         reserved_at_20[0x2];
 409         u8         log_max_ft_size[0x6];
 410         u8         reserved_at_28[0x10];
 411         u8         max_ft_level[0x8];
 412
 413         u8         reserved_at_40[0x20];
 414
 415         u8         reserved_at_60[0x18];
 416         u8         log_max_ft_num[0x8];
 417
 418         u8         reserved_at_80[0x10];
 419         u8         log_max_flow_counter[0x8];
 420         u8         log_max_destination[0x8];
 421
 422         u8         reserved_at_a0[0x18];
 423         u8         log_max_flow[0x8];
 424
 425         u8         reserved_at_c0[0x40];
 426
 427         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 428
 429         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 430 };
 431
 432 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 433         u8         send[0x1];
 434         u8         receive[0x1];
 435         u8         write[0x1];
 436         u8         read[0x1];
 437         u8         atomic[0x1];
 438         u8         srq_receive[0x1];
 439         u8         reserved_0[0x1a];
 440 };
 441
 442 struct mlx5_ifc_flow_counter_list_bits {
 443         u8         reserved_0[0x10];
 444         u8         flow_counter_id[0x10];
 445
 446         u8         reserved_1[0x20];
 447 };
 448
 449 enum {
 450         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 451         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 452         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 453         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 454 };
 455
 456 struct mlx5_ifc_dest_format_struct_bits {
 457         u8         destination_type[0x8];
 458         u8         destination_id[0x18];
 459
 460         u8         reserved_0[0x20];
 461 };
 462
 463 struct mlx5_ifc_ipv4_layout_bits {
 464         u8         reserved_at_0[0x60];
 465
 466         u8         ipv4[0x20];
 467 };
 468
 469 struct mlx5_ifc_ipv6_layout_bits {
 470         u8         ipv6[16][0x8];
 471 };
 472
 473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 474         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 475         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 476         u8         reserved_at_0[0x80];
 477 };
 478
 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 480         u8         smac_47_16[0x20];
 481
 482         u8         smac_15_0[0x10];
 483         u8         ethertype[0x10];
 484
 485         u8         dmac_47_16[0x20];
 486
 487         u8         dmac_15_0[0x10];
 488         u8         first_prio[0x3];
 489         u8         first_cfi[0x1];
 490         u8         first_vid[0xc];
 491
 492         u8         ip_protocol[0x8];
 493         u8         ip_dscp[0x6];
 494         u8         ip_ecn[0x2];
 495         u8         cvlan_tag[0x1];
 496         u8         svlan_tag[0x1];
 497         u8         frag[0x1];
 498         u8         reserved_1[0x4];
 499         u8         tcp_flags[0x9];
 500
 501         u8         tcp_sport[0x10];
 502         u8         tcp_dport[0x10];
 503
 504         u8         reserved_2[0x20];
 505
 506         u8         udp_sport[0x10];
 507         u8         udp_dport[0x10];
 508
 509         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 510
 511         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 512 };
 513
 514 struct mlx5_ifc_fte_match_set_misc_bits {
 515         u8         reserved_0[0x8];
 516         u8         source_sqn[0x18];
 517
 518         u8         reserved_1[0x10];
 519         u8         source_port[0x10];
 520
 521         u8         outer_second_prio[0x3];
 522         u8         outer_second_cfi[0x1];
 523         u8         outer_second_vid[0xc];
 524         u8         inner_second_prio[0x3];
 525         u8         inner_second_cfi[0x1];
 526         u8         inner_second_vid[0xc];
 527
 528         u8         outer_second_vlan_tag[0x1];
 529         u8         inner_second_vlan_tag[0x1];
 530         u8         reserved_2[0xe];
 531         u8         gre_protocol[0x10];
 532
 533         u8         gre_key_h[0x18];
 534         u8         gre_key_l[0x8];
 535
 536         u8         vxlan_vni[0x18];
 537         u8         reserved_3[0x8];
 538
 539         u8         geneve_vni[0x18];
 540         u8         reserved4[0x7];
 541         u8         geneve_oam[0x1];
 542
 543         u8         reserved_5[0xc];
 544         u8         outer_ipv6_flow_label[0x14];
 545
 546         u8         reserved_6[0xc];
 547         u8         inner_ipv6_flow_label[0x14];
 548
 549         u8         reserved_7[0xa];
 550         u8         geneve_opt_len[0x6];
 551         u8         geneve_protocol_type[0x10];
 552
 553         u8         reserved_8[0x8];
 554         u8         bth_dst_qp[0x18];
 555
 556         u8         reserved_9[0xa0];
 557 };
 558
 559 struct mlx5_ifc_cmd_pas_bits {
 560         u8         pa_h[0x20];
 561
 562         u8         pa_l[0x14];
 563         u8         reserved_0[0xc];
 564 };
 565
 566 struct mlx5_ifc_uint64_bits {
 567         u8         hi[0x20];
 568
 569         u8         lo[0x20];
 570 };
 571
 572 struct mlx5_ifc_application_prio_entry_bits {
 573         u8         reserved_0[0x8];
 574         u8         priority[0x3];
 575         u8         reserved_1[0x2];
 576         u8         sel[0x3];
 577         u8         protocol_id[0x10];
 578 };
 579
 580 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 581         u8         reserved_0[0x8];
 582         u8         ring_pi[0x10];
 583         u8         reserved_1[0x8];
 584 };
 585
 586 enum {
 587         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 588         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 589         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 590         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 591         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 592         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 593         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 594         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 595         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 596         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 597 };
 598
 599 struct mlx5_ifc_ads_bits {
 600         u8         fl[0x1];
 601         u8         free_ar[0x1];
 602         u8         reserved_0[0xe];
 603         u8         pkey_index[0x10];
 604
 605         u8         reserved_1[0x8];
 606         u8         grh[0x1];
 607         u8         mlid[0x7];
 608         u8         rlid[0x10];
 609
 610         u8         ack_timeout[0x5];
 611         u8         reserved_2[0x3];
 612         u8         src_addr_index[0x8];
 613         u8         log_rtm[0x4];
 614         u8         stat_rate[0x4];
 615         u8         hop_limit[0x8];
 616
 617         u8         reserved_3[0x4];
 618         u8         tclass[0x8];
 619         u8         flow_label[0x14];
 620
 621         u8         rgid_rip[16][0x8];
 622
 623         u8         reserved_4[0x4];
 624         u8         f_dscp[0x1];
 625         u8         f_ecn[0x1];
 626         u8         reserved_5[0x1];
 627         u8         f_eth_prio[0x1];
 628         u8         ecn[0x2];
 629         u8         dscp[0x6];
 630         u8         udp_sport[0x10];
 631
 632         u8         dei_cfi[0x1];
 633         u8         eth_prio[0x3];
 634         u8         sl[0x4];
 635         u8         port[0x8];
 636         u8         rmac_47_32[0x10];
 637
 638         u8         rmac_31_0[0x20];
 639 };
 640
 641 struct mlx5_ifc_diagnostic_counter_cap_bits {
 642         u8         sync[0x1];
 643         u8         reserved_0[0xf];
 644         u8         counter_id[0x10];
 645 };
 646
 647 struct mlx5_ifc_debug_cap_bits {
 648         u8         reserved_0[0x18];
 649         u8         log_max_samples[0x8];
 650
 651         u8         single[0x1];
 652         u8         repetitive[0x1];
 653         u8         health_mon_rx_activity[0x1];
 654         u8         reserved_1[0x15];
 655         u8         log_min_sample_period[0x8];
 656
 657         u8         reserved_2[0x1c0];
 658
 659         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 660 };
 661
 662 struct mlx5_ifc_qos_cap_bits {
 663         u8         packet_pacing[0x1];
 664         u8         esw_scheduling[0x1];
 665         u8         esw_bw_share[0x1];
 666         u8         esw_rate_limit[0x1];
 667         u8         hll[0x1];
 668         u8         packet_pacing_burst_bound[0x1];
 669         u8         reserved_at_6[0x1a];
 670
 671         u8         reserved_at_20[0x20];
 672
 673         u8         packet_pacing_max_rate[0x20];
 674
 675         u8         packet_pacing_min_rate[0x20];
 676
 677         u8         reserved_at_80[0x10];
 678         u8         packet_pacing_rate_table_size[0x10];
 679
 680         u8         esw_element_type[0x10];
 681         u8         esw_tsar_type[0x10];
 682
 683         u8         reserved_at_c0[0x10];
 684         u8         max_qos_para_vport[0x10];
 685
 686         u8         max_tsar_bw_share[0x20];
 687
 688         u8         reserved_at_100[0x700];
 689 };
 690
 691 struct mlx5_ifc_snapshot_cap_bits {
 692         u8         reserved_0[0x1d];
 693         u8         suspend_qp_uc[0x1];
 694         u8         suspend_qp_ud[0x1];
 695         u8         suspend_qp_rc[0x1];
 696
 697         u8         reserved_1[0x1c];
 698         u8         restore_pd[0x1];
 699         u8         restore_uar[0x1];
 700         u8         restore_mkey[0x1];
 701         u8         restore_qp[0x1];
 702
 703         u8         reserved_2[0x1e];
 704         u8         named_mkey[0x1];
 705         u8         named_qp[0x1];
 706
 707         u8         reserved_3[0x7a0];
 708 };
 709
 710 struct mlx5_ifc_e_switch_cap_bits {
 711         u8         vport_svlan_strip[0x1];
 712         u8         vport_cvlan_strip[0x1];
 713         u8         vport_svlan_insert[0x1];
 714         u8         vport_cvlan_insert_if_not_exist[0x1];
 715         u8         vport_cvlan_insert_overwrite[0x1];
 716
 717         u8         reserved_0[0x19];
 718
 719         u8         nic_vport_node_guid_modify[0x1];
 720         u8         nic_vport_port_guid_modify[0x1];
 721
 722         u8         reserved_1[0x7e0];
 723 };
 724
 725 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 726         u8         reserved_0[0x200];
 727
 728         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 729
 730         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 731
 732         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 733
 734         u8         reserved_1[0x7800];
 735 };
 736
 737 struct mlx5_ifc_flow_table_nic_cap_bits {
 738         u8         nic_rx_multi_path_tirs[0x1];
 739         u8         nic_rx_multi_path_tirs_fts[0x1];
 740         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 741         u8         reserved_at_3[0x1fd];
 742
 743         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 744
 745         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 746
 747         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 748
 749         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 754
 755         u8         reserved_1[0x7200];
 756 };
 757
 758 enum {
 759         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR                   = 0x5031,
 760 };
 761
 762 struct mlx5_ifc_pddr_module_info_bits {
 763         u8         cable_technology[0x8];
 764         u8         cable_breakout[0x8];
 765         u8         ext_ethernet_compliance_code[0x8];
 766         u8         ethernet_compliance_code[0x8];
 767
 768         u8         cable_type[0x4];
 769         u8         cable_vendor[0x4];
 770         u8         cable_length[0x8];
 771         u8         cable_identifier[0x8];
 772         u8         cable_power_class[0x8];
 773
 774         u8         reserved_at_40[0x8];
 775         u8         cable_rx_amp[0x8];
 776         u8         cable_rx_emphasis[0x8];
 777         u8         cable_tx_equalization[0x8];
 778
 779         u8         reserved_at_60[0x8];
 780         u8         cable_attenuation_12g[0x8];
 781         u8         cable_attenuation_7g[0x8];
 782         u8         cable_attenuation_5g[0x8];
 783
 784         u8         reserved_at_80[0x8];
 785         u8         rx_cdr_cap[0x4];
 786         u8         tx_cdr_cap[0x4];
 787         u8         reserved_at_90[0x4];
 788         u8         rx_cdr_state[0x4];
 789         u8         reserved_at_98[0x4];
 790         u8         tx_cdr_state[0x4];
 791
 792         u8         vendor_name[16][0x8];
 793
 794         u8         vendor_pn[16][0x8];
 795
 796         u8         vendor_rev[0x20];
 797
 798         u8         fw_version[0x20];
 799
 800         u8         vendor_sn[16][0x8];
 801
 802         u8         temperature[0x10];
 803         u8         voltage[0x10];
 804
 805         u8         rx_power_lane0[0x10];
 806         u8         rx_power_lane1[0x10];
 807
 808         u8         rx_power_lane2[0x10];
 809         u8         rx_power_lane3[0x10];
 810
 811         u8         reserved_at_2c0[0x40];
 812
 813         u8         tx_power_lane0[0x10];
 814         u8         tx_power_lane1[0x10];
 815
 816         u8         tx_power_lane2[0x10];
 817         u8         tx_power_lane3[0x10];
 818
 819         u8         reserved_at_340[0x40];
 820
 821         u8         tx_bias_lane0[0x10];
 822         u8         tx_bias_lane1[0x10];
 823
 824         u8         tx_bias_lane2[0x10];
 825         u8         tx_bias_lane3[0x10];
 826
 827         u8         reserved_at_3c0[0x40];
 828
 829         u8         temperature_high_th[0x10];
 830         u8         temperature_low_th[0x10];
 831
 832         u8         voltage_high_th[0x10];
 833         u8         voltage_low_th[0x10];
 834
 835         u8         rx_power_high_th[0x10];
 836         u8         rx_power_low_th[0x10];
 837
 838         u8         tx_power_high_th[0x10];
 839         u8         tx_power_low_th[0x10];
 840
 841         u8         tx_bias_high_th[0x10];
 842         u8         tx_bias_low_th[0x10];
 843
 844         u8         reserved_at_4a0[0x10];
 845         u8         wavelength[0x10];
 846
 847         u8         reserved_at_4c0[0x300];
 848 };
 849
 850 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
 851         struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
 852         u8         reserved_at_0[0x7c0];
 853 };
 854
 855 struct mlx5_ifc_pddr_reg_bits {
 856         u8         reserved_at_0[0x8];
 857         u8         local_port[0x8];
 858         u8         pnat[0x2];
 859         u8         reserved_at_12[0xe];
 860
 861         u8         reserved_at_20[0x18];
 862         u8         page_select[0x8];
 863
 864         union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
 865 };
 866
 867 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 868         u8         csum_cap[0x1];
 869         u8         vlan_cap[0x1];
 870         u8         lro_cap[0x1];
 871         u8         lro_psh_flag[0x1];
 872         u8         lro_time_stamp[0x1];
 873         u8         lro_max_msg_sz_mode[0x2];
 874         u8         wqe_vlan_insert[0x1];
 875         u8         self_lb_en_modifiable[0x1];
 876         u8         self_lb_mc[0x1];
 877         u8         self_lb_uc[0x1];
 878         u8         max_lso_cap[0x5];
 879         u8         multi_pkt_send_wqe[0x2];
 880         u8         wqe_inline_mode[0x2];
 881         u8         rss_ind_tbl_cap[0x4];
 882         u8         scatter_fcs[0x1];
 883         u8         reserved_1[0x2];
 884         u8         tunnel_lso_const_out_ip_id[0x1];
 885         u8         tunnel_lro_gre[0x1];
 886         u8         tunnel_lro_vxlan[0x1];
 887         u8         tunnel_statless_gre[0x1];
 888         u8         tunnel_stateless_vxlan[0x1];
 889
 890         u8         swp[0x1];
 891         u8         swp_csum[0x1];
 892         u8         swp_lso[0x1];
 893         u8         reserved_2[0x1b];
 894         u8         max_geneve_opt_len[0x1];
 895         u8         tunnel_stateless_geneve_rx[0x1];
 896
 897         u8         reserved_3[0x10];
 898         u8         lro_min_mss_size[0x10];
 899
 900         u8         reserved_4[0x120];
 901
 902         u8         lro_timer_supported_periods[4][0x20];
 903
 904         u8         reserved_5[0x600];
 905 };
 906
 907 enum {
 908         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 909         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 910         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 911 };
 912
 913 struct mlx5_ifc_roce_cap_bits {
 914         u8         roce_apm[0x1];
 915         u8         rts2rts_primary_eth_prio[0x1];
 916         u8         roce_rx_allow_untagged[0x1];
 917         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 918
 919         u8         reserved_0[0x1c];
 920
 921         u8         reserved_1[0x60];
 922
 923         u8         reserved_2[0xc];
 924         u8         l3_type[0x4];
 925         u8         reserved_3[0x8];
 926         u8         roce_version[0x8];
 927
 928         u8         reserved_4[0x10];
 929         u8         r_roce_dest_udp_port[0x10];
 930
 931         u8         r_roce_max_src_udp_port[0x10];
 932         u8         r_roce_min_src_udp_port[0x10];
 933
 934         u8         reserved_5[0x10];
 935         u8         roce_address_table_size[0x10];
 936
 937         u8         reserved_6[0x700];
 938 };
 939
 940 enum {
 941         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 942         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 943         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 944         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 945         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 946         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 947         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 948         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 949         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 950 };
 951
 952 enum {
 953         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 954         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 955         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 956         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 957         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 958         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 959         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 960         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 961         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 962 };
 963
 964 struct mlx5_ifc_atomic_caps_bits {
 965         u8         reserved_0[0x40];
 966
 967         u8         atomic_req_8B_endianess_mode[0x2];
 968         u8         reserved_1[0x4];
 969         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 970
 971         u8         reserved_2[0x19];
 972
 973         u8         reserved_3[0x20];
 974
 975         u8         reserved_4[0x10];
 976         u8         atomic_operations[0x10];
 977
 978         u8         reserved_5[0x10];
 979         u8         atomic_size_qp[0x10];
 980
 981         u8         reserved_6[0x10];
 982         u8         atomic_size_dc[0x10];
 983
 984         u8         reserved_7[0x720];
 985 };
 986
 987 struct mlx5_ifc_odp_cap_bits {
 988         u8         reserved_0[0x40];
 989
 990         u8         sig[0x1];
 991         u8         reserved_1[0x1f];
 992
 993         u8         reserved_2[0x20];
 994
 995         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 996
 997         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 998
 999         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1000
1001         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1002
1003         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1004
1005         u8         reserved_3[0x6e0];
1006 };
1007
1008 enum {
1009         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1010         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1011         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1012         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1013         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1014 };
1015
1016 enum {
1017         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1018         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1019         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1020         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1021         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1022         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1023 };
1024
1025 enum {
1026         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1027         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1028 };
1029
1030 enum {
1031         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1032         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1033         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1034 };
1035
1036 struct mlx5_ifc_cmd_hca_cap_bits {
1037         u8         reserved_0[0x80];
1038
1039         u8         log_max_srq_sz[0x8];
1040         u8         log_max_qp_sz[0x8];
1041         u8         reserved_1[0xb];
1042         u8         log_max_qp[0x5];
1043
1044         u8         reserved_2[0xb];
1045         u8         log_max_srq[0x5];
1046         u8         reserved_3[0x10];
1047
1048         u8         reserved_4[0x8];
1049         u8         log_max_cq_sz[0x8];
1050         u8         reserved_5[0xb];
1051         u8         log_max_cq[0x5];
1052
1053         u8         log_max_eq_sz[0x8];
1054         u8         relaxed_ordering_write[1];
1055         u8         reserved_6[0x1];
1056         u8         log_max_mkey[0x6];
1057         u8         reserved_7[0xb];
1058         u8         fast_teardown[0x1];
1059         u8         log_max_eq[0x4];
1060
1061         u8         max_indirection[0x8];
1062         u8         reserved_8[0x1];
1063         u8         log_max_mrw_sz[0x7];
1064         u8         force_teardown[0x1];
1065         u8         reserved_9[0x1];
1066         u8         log_max_bsf_list_size[0x6];
1067         u8         reserved_10[0x2];
1068         u8         log_max_klm_list_size[0x6];
1069
1070         u8         reserved_11[0xa];
1071         u8         log_max_ra_req_dc[0x6];
1072         u8         reserved_12[0xa];
1073         u8         log_max_ra_res_dc[0x6];
1074
1075         u8         reserved_13[0xa];
1076         u8         log_max_ra_req_qp[0x6];
1077         u8         reserved_14[0xa];
1078         u8         log_max_ra_res_qp[0x6];
1079
1080         u8         pad_cap[0x1];
1081         u8         cc_query_allowed[0x1];
1082         u8         cc_modify_allowed[0x1];
1083         u8         start_pad[0x1];
1084         u8         cache_line_128byte[0x1];
1085         u8         reserved_at_165[0xa];
1086         u8         qcam_reg[0x1];
1087         u8         gid_table_size[0x10];
1088
1089         u8         out_of_seq_cnt[0x1];
1090         u8         vport_counters[0x1];
1091         u8         retransmission_q_counters[0x1];
1092         u8         debug[0x1];
1093         u8         modify_rq_counters_set_id[0x1];
1094         u8         rq_delay_drop[0x1];
1095         u8         max_qp_cnt[0xa];
1096         u8         pkey_table_size[0x10];
1097
1098         u8         vport_group_manager[0x1];
1099         u8         vhca_group_manager[0x1];
1100         u8         ib_virt[0x1];
1101         u8         eth_virt[0x1];
1102         u8         reserved_17[0x1];
1103         u8         ets[0x1];
1104         u8         nic_flow_table[0x1];
1105         u8         eswitch_flow_table[0x1];
1106         u8         reserved_18[0x3];
1107         u8         local_ca_ack_delay[0x5];
1108         u8         port_module_event[0x1];
1109         u8         reserved_19[0x5];
1110         u8         port_type[0x2];
1111         u8         num_ports[0x8];
1112
1113         u8         snapshot[0x1];
1114         u8         reserved_20[0x2];
1115         u8         log_max_msg[0x5];
1116         u8         reserved_21[0x4];
1117         u8         max_tc[0x4];
1118         u8         temp_warn_event[0x1];
1119         u8         dcbx[0x1];
1120         u8         general_notification_event[0x1];
1121         u8         reserved_at_1d3[0x2];
1122         u8         fpga[0x1];
1123         u8         rol_s[0x1];
1124         u8         rol_g[0x1];
1125         u8         reserved_23[0x1];
1126         u8         wol_s[0x1];
1127         u8         wol_g[0x1];
1128         u8         wol_a[0x1];
1129         u8         wol_b[0x1];
1130         u8         wol_m[0x1];
1131         u8         wol_u[0x1];
1132         u8         wol_p[0x1];
1133
1134         u8         stat_rate_support[0x10];
1135         u8         reserved_24[0xc];
1136         u8         cqe_version[0x4];
1137
1138         u8         compact_address_vector[0x1];
1139         u8         striding_rq[0x1];
1140         u8         reserved_25[0x1];
1141         u8         ipoib_enhanced_offloads[0x1];
1142         u8         ipoib_ipoib_offloads[0x1];
1143         u8         reserved_26[0x8];
1144         u8         dc_connect_qp[0x1];
1145         u8         dc_cnak_trace[0x1];
1146         u8         drain_sigerr[0x1];
1147         u8         cmdif_checksum[0x2];
1148         u8         sigerr_cqe[0x1];
1149         u8         reserved_27[0x1];
1150         u8         wq_signature[0x1];
1151         u8         sctr_data_cqe[0x1];
1152         u8         reserved_28[0x1];
1153         u8         sho[0x1];
1154         u8         tph[0x1];
1155         u8         rf[0x1];
1156         u8         dct[0x1];
1157         u8         qos[0x1];
1158         u8         eth_net_offloads[0x1];
1159         u8         roce[0x1];
1160         u8         atomic[0x1];
1161         u8         reserved_30[0x1];
1162
1163         u8         cq_oi[0x1];
1164         u8         cq_resize[0x1];
1165         u8         cq_moderation[0x1];
1166         u8         cq_period_mode_modify[0x1];
1167         u8         cq_invalidate[0x1];
1168         u8         reserved_at_225[0x1];
1169         u8         cq_eq_remap[0x1];
1170         u8         pg[0x1];
1171         u8         block_lb_mc[0x1];
1172         u8         exponential_backoff[0x1];
1173         u8         scqe_break_moderation[0x1];
1174         u8         cq_period_start_from_cqe[0x1];
1175         u8         cd[0x1];
1176         u8         atm[0x1];
1177         u8         apm[0x1];
1178         u8         imaicl[0x1];
1179         u8         reserved_32[0x6];
1180         u8         qkv[0x1];
1181         u8         pkv[0x1];
1182         u8         set_deth_sqpn[0x1];
1183         u8         reserved_33[0x3];
1184         u8         xrc[0x1];
1185         u8         ud[0x1];
1186         u8         uc[0x1];
1187         u8         rc[0x1];
1188
1189         u8         reserved_34[0xa];
1190         u8         uar_sz[0x6];
1191         u8         reserved_35[0x8];
1192         u8         log_pg_sz[0x8];
1193
1194         u8         bf[0x1];
1195         u8         driver_version[0x1];
1196         u8         pad_tx_eth_packet[0x1];
1197         u8         reserved_36[0x8];
1198         u8         log_bf_reg_size[0x5];
1199         u8         reserved_37[0x10];
1200
1201         u8         num_of_diagnostic_counters[0x10];
1202         u8         max_wqe_sz_sq[0x10];
1203
1204         u8         reserved_38[0x10];
1205         u8         max_wqe_sz_rq[0x10];
1206
1207         u8         reserved_39[0x10];
1208         u8         max_wqe_sz_sq_dc[0x10];
1209
1210         u8         reserved_40[0x7];
1211         u8         max_qp_mcg[0x19];
1212
1213         u8         reserved_41[0x18];
1214         u8         log_max_mcg[0x8];
1215
1216         u8         reserved_42[0x3];
1217         u8         log_max_transport_domain[0x5];
1218         u8         reserved_43[0x3];
1219         u8         log_max_pd[0x5];
1220         u8         reserved_44[0xb];
1221         u8         log_max_xrcd[0x5];
1222
1223         u8         reserved_45[0x10];
1224         u8         max_flow_counter[0x10];
1225
1226         u8         reserved_46[0x3];
1227         u8         log_max_rq[0x5];
1228         u8         reserved_47[0x3];
1229         u8         log_max_sq[0x5];
1230         u8         reserved_48[0x3];
1231         u8         log_max_tir[0x5];
1232         u8         reserved_49[0x3];
1233         u8         log_max_tis[0x5];
1234
1235         u8         basic_cyclic_rcv_wqe[0x1];
1236         u8         reserved_50[0x2];
1237         u8         log_max_rmp[0x5];
1238         u8         reserved_51[0x3];
1239         u8         log_max_rqt[0x5];
1240         u8         reserved_52[0x3];
1241         u8         log_max_rqt_size[0x5];
1242         u8         reserved_53[0x3];
1243         u8         log_max_tis_per_sq[0x5];
1244
1245         u8         reserved_54[0x3];
1246         u8         log_max_stride_sz_rq[0x5];
1247         u8         reserved_55[0x3];
1248         u8         log_min_stride_sz_rq[0x5];
1249         u8         reserved_56[0x3];
1250         u8         log_max_stride_sz_sq[0x5];
1251         u8         reserved_57[0x3];
1252         u8         log_min_stride_sz_sq[0x5];
1253
1254         u8         reserved_58[0x1b];
1255         u8         log_max_wq_sz[0x5];
1256
1257         u8         nic_vport_change_event[0x1];
1258         u8         disable_local_lb[0x1];
1259         u8         reserved_59[0x9];
1260         u8         log_max_vlan_list[0x5];
1261         u8         reserved_60[0x3];
1262         u8         log_max_current_mc_list[0x5];
1263         u8         reserved_61[0x3];
1264         u8         log_max_current_uc_list[0x5];
1265
1266         u8         reserved_62[0x80];
1267
1268         u8         reserved_63[0x3];
1269         u8         log_max_l2_table[0x5];
1270         u8         reserved_64[0x8];
1271         u8         log_uar_page_sz[0x10];
1272
1273         u8         reserved_65[0x20];
1274
1275         u8         device_frequency_mhz[0x20];
1276
1277         u8         device_frequency_khz[0x20];
1278
1279         u8         reserved_66[0x80];
1280
1281         u8         log_max_atomic_size_qp[0x8];
1282         u8         reserved_67[0x10];
1283         u8         log_max_atomic_size_dc[0x8];
1284
1285         u8         reserved_68[0x1f];
1286         u8         cqe_compression[0x1];
1287
1288         u8         cqe_compression_timeout[0x10];
1289         u8         cqe_compression_max_num[0x10];
1290
1291         u8         reserved_69[0x220];
1292 };
1293
1294 enum mlx5_flow_destination_type {
1295         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1296         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1297         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1298 };
1299
1300 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1301         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1302         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1303         u8         reserved_0[0x40];
1304 };
1305
1306 struct mlx5_ifc_fte_match_param_bits {
1307         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1308
1309         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1310
1311         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1312
1313         u8         reserved_0[0xa00];
1314 };
1315
1316 enum {
1317         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1318         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1319         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1320         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1321         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1322 };
1323
1324 struct mlx5_ifc_rx_hash_field_select_bits {
1325         u8         l3_prot_type[0x1];
1326         u8         l4_prot_type[0x1];
1327         u8         selected_fields[0x1e];
1328 };
1329
1330 enum {
1331         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1332         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1333         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1334         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1335 };
1336
1337 enum rq_type {
1338         RQ_TYPE_NONE,
1339         RQ_TYPE_STRIDE,
1340 };
1341
1342 enum {
1343         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1344         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1345 };
1346
1347 struct mlx5_ifc_wq_bits {
1348         u8         wq_type[0x4];
1349         u8         wq_signature[0x1];
1350         u8         end_padding_mode[0x2];
1351         u8         cd_slave[0x1];
1352         u8         reserved_0[0x18];
1353
1354         u8         hds_skip_first_sge[0x1];
1355         u8         log2_hds_buf_size[0x3];
1356         u8         reserved_1[0x7];
1357         u8         page_offset[0x5];
1358         u8         lwm[0x10];
1359
1360         u8         reserved_2[0x8];
1361         u8         pd[0x18];
1362
1363         u8         reserved_3[0x8];
1364         u8         uar_page[0x18];
1365
1366         u8         dbr_addr[0x40];
1367
1368         u8         hw_counter[0x20];
1369
1370         u8         sw_counter[0x20];
1371
1372         u8         reserved_4[0xc];
1373         u8         log_wq_stride[0x4];
1374         u8         reserved_5[0x3];
1375         u8         log_wq_pg_sz[0x5];
1376         u8         reserved_6[0x3];
1377         u8         log_wq_sz[0x5];
1378
1379         u8         reserved_7[0x15];
1380         u8         single_wqe_log_num_of_strides[0x3];
1381         u8         two_byte_shift_en[0x1];
1382         u8         reserved_8[0x4];
1383         u8         single_stride_log_num_of_bytes[0x3];
1384
1385         u8         reserved_9[0x4c0];
1386
1387         struct mlx5_ifc_cmd_pas_bits pas[0];
1388 };
1389
1390 struct mlx5_ifc_rq_num_bits {
1391         u8         reserved_0[0x8];
1392         u8         rq_num[0x18];
1393 };
1394
1395 struct mlx5_ifc_mac_address_layout_bits {
1396         u8         reserved_0[0x10];
1397         u8         mac_addr_47_32[0x10];
1398
1399         u8         mac_addr_31_0[0x20];
1400 };
1401
1402 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1403         u8         reserved_0[0xa0];
1404
1405         u8         min_time_between_cnps[0x20];
1406
1407         u8         reserved_1[0x12];
1408         u8         cnp_dscp[0x6];
1409         u8         reserved_2[0x4];
1410         u8         cnp_prio_mode[0x1];
1411         u8         cnp_802p_prio[0x3];
1412
1413         u8         reserved_3[0x720];
1414 };
1415
1416 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1417         u8         reserved_0[0x60];
1418
1419         u8         reserved_1[0x4];
1420         u8         clamp_tgt_rate[0x1];
1421         u8         reserved_2[0x3];
1422         u8         clamp_tgt_rate_after_time_inc[0x1];
1423         u8         reserved_3[0x17];
1424
1425         u8         reserved_4[0x20];
1426
1427         u8         rpg_time_reset[0x20];
1428
1429         u8         rpg_byte_reset[0x20];
1430
1431         u8         rpg_threshold[0x20];
1432
1433         u8         rpg_max_rate[0x20];
1434
1435         u8         rpg_ai_rate[0x20];
1436
1437         u8         rpg_hai_rate[0x20];
1438
1439         u8         rpg_gd[0x20];
1440
1441         u8         rpg_min_dec_fac[0x20];
1442
1443         u8         rpg_min_rate[0x20];
1444
1445         u8         reserved_5[0xe0];
1446
1447         u8         rate_to_set_on_first_cnp[0x20];
1448
1449         u8         dce_tcp_g[0x20];
1450
1451         u8         dce_tcp_rtt[0x20];
1452
1453         u8         rate_reduce_monitor_period[0x20];
1454
1455         u8         reserved_6[0x20];
1456
1457         u8         initial_alpha_value[0x20];
1458
1459         u8         reserved_7[0x4a0];
1460 };
1461
1462 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1463         u8         reserved_0[0x80];
1464
1465         u8         rppp_max_rps[0x20];
1466
1467         u8         rpg_time_reset[0x20];
1468
1469         u8         rpg_byte_reset[0x20];
1470
1471         u8         rpg_threshold[0x20];
1472
1473         u8         rpg_max_rate[0x20];
1474
1475         u8         rpg_ai_rate[0x20];
1476
1477         u8         rpg_hai_rate[0x20];
1478
1479         u8         rpg_gd[0x20];
1480
1481         u8         rpg_min_dec_fac[0x20];
1482
1483         u8         rpg_min_rate[0x20];
1484
1485         u8         reserved_1[0x640];
1486 };
1487
1488 enum {
1489         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1490         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1491         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1492 };
1493
1494 struct mlx5_ifc_resize_field_select_bits {
1495         u8         resize_field_select[0x20];
1496 };
1497
1498 enum {
1499         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1500         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1501         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1502         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1503         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1504         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1505 };
1506
1507 struct mlx5_ifc_modify_field_select_bits {
1508         u8         modify_field_select[0x20];
1509 };
1510
1511 struct mlx5_ifc_field_select_r_roce_np_bits {
1512         u8         field_select_r_roce_np[0x20];
1513 };
1514
1515 enum {
1516         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1517         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1518         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1519         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1520         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1521         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1522         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1523         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1524         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1525         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1526         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1527         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1528         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1529         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1530         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1531 };
1532
1533 struct mlx5_ifc_field_select_r_roce_rp_bits {
1534         u8         field_select_r_roce_rp[0x20];
1535 };
1536
1537 enum {
1538         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1539         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1540         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1541         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1542         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1543         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1544         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1545         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1546         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1547         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1548 };
1549
1550 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1551         u8         field_select_8021qaurp[0x20];
1552 };
1553
1554 struct mlx5_ifc_pptb_reg_bits {
1555         u8         reserved_0[0x2];
1556         u8         mm[0x2];
1557         u8         reserved_1[0x4];
1558         u8         local_port[0x8];
1559         u8         reserved_2[0x6];
1560         u8         cm[0x1];
1561         u8         um[0x1];
1562         u8         pm[0x8];
1563
1564         u8         prio7buff[0x4];
1565         u8         prio6buff[0x4];
1566         u8         prio5buff[0x4];
1567         u8         prio4buff[0x4];
1568         u8         prio3buff[0x4];
1569         u8         prio2buff[0x4];
1570         u8         prio1buff[0x4];
1571         u8         prio0buff[0x4];
1572
1573         u8         pm_msb[0x8];
1574         u8         reserved_3[0x10];
1575         u8         ctrl_buff[0x4];
1576         u8         untagged_buff[0x4];
1577 };
1578
1579 struct mlx5_ifc_dcbx_app_reg_bits {
1580         u8         reserved_0[0x8];
1581         u8         port_number[0x8];
1582         u8         reserved_1[0x10];
1583
1584         u8         reserved_2[0x1a];
1585         u8         num_app_prio[0x6];
1586
1587         u8         reserved_3[0x40];
1588
1589         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1590 };
1591
1592 struct mlx5_ifc_dcbx_param_reg_bits {
1593         u8         dcbx_cee_cap[0x1];
1594         u8         dcbx_ieee_cap[0x1];
1595         u8         dcbx_standby_cap[0x1];
1596         u8         reserved_0[0x5];
1597         u8         port_number[0x8];
1598         u8         reserved_1[0xa];
1599         u8         max_application_table_size[0x6];
1600
1601         u8         reserved_2[0x15];
1602         u8         version_oper[0x3];
1603         u8         reserved_3[0x5];
1604         u8         version_admin[0x3];
1605
1606         u8         willing_admin[0x1];
1607         u8         reserved_4[0x3];
1608         u8         pfc_cap_oper[0x4];
1609         u8         reserved_5[0x4];
1610         u8         pfc_cap_admin[0x4];
1611         u8         reserved_6[0x4];
1612         u8         num_of_tc_oper[0x4];
1613         u8         reserved_7[0x4];
1614         u8         num_of_tc_admin[0x4];
1615
1616         u8         remote_willing[0x1];
1617         u8         reserved_8[0x3];
1618         u8         remote_pfc_cap[0x4];
1619         u8         reserved_9[0x14];
1620         u8         remote_num_of_tc[0x4];
1621
1622         u8         reserved_10[0x18];
1623         u8         error[0x8];
1624
1625         u8         reserved_11[0x160];
1626 };
1627
1628 struct mlx5_ifc_qhll_bits {
1629         u8         reserved_at_0[0x8];
1630         u8         local_port[0x8];
1631         u8         reserved_at_10[0x10];
1632
1633         u8         reserved_at_20[0x1b];
1634         u8         hll_time[0x5];
1635
1636         u8         stall_en[0x1];
1637         u8         reserved_at_41[0x1c];
1638         u8         stall_cnt[0x3];
1639 };
1640
1641 struct mlx5_ifc_qetcr_reg_bits {
1642         u8         operation_type[0x2];
1643         u8         cap_local_admin[0x1];
1644         u8         cap_remote_admin[0x1];
1645         u8         reserved_0[0x4];
1646         u8         port_number[0x8];
1647         u8         reserved_1[0x10];
1648
1649         u8         reserved_2[0x20];
1650
1651         u8         tc[8][0x40];
1652
1653         u8         global_configuration[0x40];
1654 };
1655
1656 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1657         u8         queue_address_63_32[0x20];
1658
1659         u8         queue_address_31_12[0x14];
1660         u8         reserved_0[0x6];
1661         u8         log_size[0x6];
1662
1663         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1664
1665         u8         reserved_1[0x8];
1666         u8         queue_number[0x18];
1667
1668         u8         q_key[0x20];
1669
1670         u8         reserved_2[0x10];
1671         u8         pkey_index[0x10];
1672
1673         u8         reserved_3[0x40];
1674 };
1675
1676 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1677         u8         reserved_0[0x8];
1678         u8         cq_ci[0x10];
1679         u8         reserved_1[0x8];
1680 };
1681
1682 enum {
1683         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1684         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1685 };
1686
1687 enum {
1688         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1689         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1690         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1691         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1692 };
1693
1694 struct mlx5_ifc_nodnic_event_word_bits {
1695         u8         driver_reset_needed[0x1];
1696         u8         port_management_change_event[0x1];
1697         u8         reserved_0[0x19];
1698         u8         link_type[0x1];
1699         u8         port_state[0x4];
1700 };
1701
1702 struct mlx5_ifc_nic_vport_change_event_bits {
1703         u8         reserved_0[0x10];
1704         u8         vport_num[0x10];
1705
1706         u8         reserved_1[0xc0];
1707 };
1708
1709 struct mlx5_ifc_pages_req_event_bits {
1710         u8         reserved_0[0x10];
1711         u8         function_id[0x10];
1712
1713         u8         num_pages[0x20];
1714
1715         u8         reserved_1[0xa0];
1716 };
1717
1718 struct mlx5_ifc_cmd_inter_comp_event_bits {
1719         u8         command_completion_vector[0x20];
1720
1721         u8         reserved_0[0xc0];
1722 };
1723
1724 struct mlx5_ifc_stall_vl_event_bits {
1725         u8         reserved_0[0x18];
1726         u8         port_num[0x1];
1727         u8         reserved_1[0x3];
1728         u8         vl[0x4];
1729
1730         u8         reserved_2[0xa0];
1731 };
1732
1733 struct mlx5_ifc_db_bf_congestion_event_bits {
1734         u8         event_subtype[0x8];
1735         u8         reserved_0[0x8];
1736         u8         congestion_level[0x8];
1737         u8         reserved_1[0x8];
1738
1739         u8         reserved_2[0xa0];
1740 };
1741
1742 struct mlx5_ifc_gpio_event_bits {
1743         u8         reserved_0[0x60];
1744
1745         u8         gpio_event_hi[0x20];
1746
1747         u8         gpio_event_lo[0x20];
1748
1749         u8         reserved_1[0x40];
1750 };
1751
1752 struct mlx5_ifc_port_state_change_event_bits {
1753         u8         reserved_0[0x40];
1754
1755         u8         port_num[0x4];
1756         u8         reserved_1[0x1c];
1757
1758         u8         reserved_2[0x80];
1759 };
1760
1761 struct mlx5_ifc_dropped_packet_logged_bits {
1762         u8         reserved_0[0xe0];
1763 };
1764
1765 enum {
1766         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1767         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1768 };
1769
1770 struct mlx5_ifc_cq_error_bits {
1771         u8         reserved_0[0x8];
1772         u8         cqn[0x18];
1773
1774         u8         reserved_1[0x20];
1775
1776         u8         reserved_2[0x18];
1777         u8         syndrome[0x8];
1778
1779         u8         reserved_3[0x80];
1780 };
1781
1782 struct mlx5_ifc_rdma_page_fault_event_bits {
1783         u8         bytes_commited[0x20];
1784
1785         u8         r_key[0x20];
1786
1787         u8         reserved_0[0x10];
1788         u8         packet_len[0x10];
1789
1790         u8         rdma_op_len[0x20];
1791
1792         u8         rdma_va[0x40];
1793
1794         u8         reserved_1[0x5];
1795         u8         rdma[0x1];
1796         u8         write[0x1];
1797         u8         requestor[0x1];
1798         u8         qp_number[0x18];
1799 };
1800
1801 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1802         u8         bytes_committed[0x20];
1803
1804         u8         reserved_0[0x10];
1805         u8         wqe_index[0x10];
1806
1807         u8         reserved_1[0x10];
1808         u8         len[0x10];
1809
1810         u8         reserved_2[0x60];
1811
1812         u8         reserved_3[0x5];
1813         u8         rdma[0x1];
1814         u8         write_read[0x1];
1815         u8         requestor[0x1];
1816         u8         qpn[0x18];
1817 };
1818
1819 enum {
1820         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1821         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1822         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1823 };
1824
1825 struct mlx5_ifc_qp_events_bits {
1826         u8         reserved_0[0xa0];
1827
1828         u8         type[0x8];
1829         u8         reserved_1[0x18];
1830
1831         u8         reserved_2[0x8];
1832         u8         qpn_rqn_sqn[0x18];
1833 };
1834
1835 struct mlx5_ifc_dct_events_bits {
1836         u8         reserved_0[0xc0];
1837
1838         u8         reserved_1[0x8];
1839         u8         dct_number[0x18];
1840 };
1841
1842 struct mlx5_ifc_comp_event_bits {
1843         u8         reserved_0[0xc0];
1844
1845         u8         reserved_1[0x8];
1846         u8         cq_number[0x18];
1847 };
1848
1849 struct mlx5_ifc_fw_version_bits {
1850         u8         major[0x10];
1851         u8         reserved_0[0x10];
1852
1853         u8         minor[0x10];
1854         u8         subminor[0x10];
1855
1856         u8         second[0x8];
1857         u8         minute[0x8];
1858         u8         hour[0x8];
1859         u8         reserved_1[0x8];
1860
1861         u8         year[0x10];
1862         u8         month[0x8];
1863         u8         day[0x8];
1864 };
1865
1866 enum {
1867         MLX5_QPC_STATE_RST        = 0x0,
1868         MLX5_QPC_STATE_INIT       = 0x1,
1869         MLX5_QPC_STATE_RTR        = 0x2,
1870         MLX5_QPC_STATE_RTS        = 0x3,
1871         MLX5_QPC_STATE_SQER       = 0x4,
1872         MLX5_QPC_STATE_SQD        = 0x5,
1873         MLX5_QPC_STATE_ERR        = 0x6,
1874         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1875 };
1876
1877 enum {
1878         MLX5_QPC_ST_RC            = 0x0,
1879         MLX5_QPC_ST_UC            = 0x1,
1880         MLX5_QPC_ST_UD            = 0x2,
1881         MLX5_QPC_ST_XRC           = 0x3,
1882         MLX5_QPC_ST_DCI           = 0x5,
1883         MLX5_QPC_ST_QP0           = 0x7,
1884         MLX5_QPC_ST_QP1           = 0x8,
1885         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1886         MLX5_QPC_ST_REG_UMR       = 0xc,
1887 };
1888
1889 enum {
1890         MLX5_QP_PM_ARMED            = 0x0,
1891         MLX5_QP_PM_REARM            = 0x1,
1892         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1893         MLX5_QP_PM_MIGRATED         = 0x3,
1894 };
1895
1896 enum {
1897         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1898         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1899 };
1900
1901 enum {
1902         MLX5_QPC_MTU_256_BYTES        = 0x1,
1903         MLX5_QPC_MTU_512_BYTES        = 0x2,
1904         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1905         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1906         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1907         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1908 };
1909
1910 enum {
1911         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1912         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1913         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1914         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1915         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1916         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1917         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1918         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1919 };
1920
1921 enum {
1922         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1923         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1924         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1925 };
1926
1927 enum {
1928         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1929         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1930         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1931 };
1932
1933 struct mlx5_ifc_qpc_bits {
1934         u8         state[0x4];
1935         u8         lag_tx_port_affinity[0x4];
1936         u8         st[0x8];
1937         u8         reserved_1[0x3];
1938         u8         pm_state[0x2];
1939         u8         reserved_2[0x7];
1940         u8         end_padding_mode[0x2];
1941         u8         reserved_3[0x2];
1942
1943         u8         wq_signature[0x1];
1944         u8         block_lb_mc[0x1];
1945         u8         atomic_like_write_en[0x1];
1946         u8         latency_sensitive[0x1];
1947         u8         reserved_4[0x1];
1948         u8         drain_sigerr[0x1];
1949         u8         reserved_5[0x2];
1950         u8         pd[0x18];
1951
1952         u8         mtu[0x3];
1953         u8         log_msg_max[0x5];
1954         u8         reserved_6[0x1];
1955         u8         log_rq_size[0x4];
1956         u8         log_rq_stride[0x3];
1957         u8         no_sq[0x1];
1958         u8         log_sq_size[0x4];
1959         u8         reserved_7[0x6];
1960         u8         rlky[0x1];
1961         u8         ulp_stateless_offload_mode[0x4];
1962
1963         u8         counter_set_id[0x8];
1964         u8         uar_page[0x18];
1965
1966         u8         reserved_8[0x8];
1967         u8         user_index[0x18];
1968
1969         u8         reserved_9[0x3];
1970         u8         log_page_size[0x5];
1971         u8         remote_qpn[0x18];
1972
1973         struct mlx5_ifc_ads_bits primary_address_path;
1974
1975         struct mlx5_ifc_ads_bits secondary_address_path;
1976
1977         u8         log_ack_req_freq[0x4];
1978         u8         reserved_10[0x4];
1979         u8         log_sra_max[0x3];
1980         u8         reserved_11[0x2];
1981         u8         retry_count[0x3];
1982         u8         rnr_retry[0x3];
1983         u8         reserved_12[0x1];
1984         u8         fre[0x1];
1985         u8         cur_rnr_retry[0x3];
1986         u8         cur_retry_count[0x3];
1987         u8         reserved_13[0x5];
1988
1989         u8         reserved_14[0x20];
1990
1991         u8         reserved_15[0x8];
1992         u8         next_send_psn[0x18];
1993
1994         u8         reserved_16[0x8];
1995         u8         cqn_snd[0x18];
1996
1997         u8         reserved_at_400[0x8];
1998
1999         u8         deth_sqpn[0x18];
2000         u8         reserved_17[0x20];
2001
2002         u8         reserved_18[0x8];
2003         u8         last_acked_psn[0x18];
2004
2005         u8         reserved_19[0x8];
2006         u8         ssn[0x18];
2007
2008         u8         reserved_20[0x8];
2009         u8         log_rra_max[0x3];
2010         u8         reserved_21[0x1];
2011         u8         atomic_mode[0x4];
2012         u8         rre[0x1];
2013         u8         rwe[0x1];
2014         u8         rae[0x1];
2015         u8         reserved_22[0x1];
2016         u8         page_offset[0x6];
2017         u8         reserved_23[0x3];
2018         u8         cd_slave_receive[0x1];
2019         u8         cd_slave_send[0x1];
2020         u8         cd_master[0x1];
2021
2022         u8         reserved_24[0x3];
2023         u8         min_rnr_nak[0x5];
2024         u8         next_rcv_psn[0x18];
2025
2026         u8         reserved_25[0x8];
2027         u8         xrcd[0x18];
2028
2029         u8         reserved_26[0x8];
2030         u8         cqn_rcv[0x18];
2031
2032         u8         dbr_addr[0x40];
2033
2034         u8         q_key[0x20];
2035
2036         u8         reserved_27[0x5];
2037         u8         rq_type[0x3];
2038         u8         srqn_rmpn[0x18];
2039
2040         u8         reserved_28[0x8];
2041         u8         rmsn[0x18];
2042
2043         u8         hw_sq_wqebb_counter[0x10];
2044         u8         sw_sq_wqebb_counter[0x10];
2045
2046         u8         hw_rq_counter[0x20];
2047
2048         u8         sw_rq_counter[0x20];
2049
2050         u8         reserved_29[0x20];
2051
2052         u8         reserved_30[0xf];
2053         u8         cgs[0x1];
2054         u8         cs_req[0x8];
2055         u8         cs_res[0x8];
2056
2057         u8         dc_access_key[0x40];
2058
2059         u8         rdma_active[0x1];
2060         u8         comm_est[0x1];
2061         u8         suspended[0x1];
2062         u8         reserved_31[0x5];
2063         u8         send_msg_psn[0x18];
2064
2065         u8         reserved_32[0x8];
2066         u8         rcv_msg_psn[0x18];
2067
2068         u8         rdma_va[0x40];
2069
2070         u8         rdma_key[0x20];
2071
2072         u8         reserved_33[0x20];
2073 };
2074
2075 struct mlx5_ifc_roce_addr_layout_bits {
2076         u8         source_l3_address[16][0x8];
2077
2078         u8         reserved_0[0x3];
2079         u8         vlan_valid[0x1];
2080         u8         vlan_id[0xc];
2081         u8         source_mac_47_32[0x10];
2082
2083         u8         source_mac_31_0[0x20];
2084
2085         u8         reserved_1[0x14];
2086         u8         roce_l3_type[0x4];
2087         u8         roce_version[0x8];
2088
2089         u8         reserved_2[0x20];
2090 };
2091
2092 struct mlx5_ifc_rdbc_bits {
2093         u8         reserved_0[0x1c];
2094         u8         type[0x4];
2095
2096         u8         reserved_1[0x20];
2097
2098         u8         reserved_2[0x8];
2099         u8         psn[0x18];
2100
2101         u8         rkey[0x20];
2102
2103         u8         address[0x40];
2104
2105         u8         byte_count[0x20];
2106
2107         u8         reserved_3[0x20];
2108
2109         u8         atomic_resp[32][0x8];
2110 };
2111
2112 enum {
2113         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2114         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2115         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2116         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2117 };
2118
2119 struct mlx5_ifc_flow_context_bits {
2120         u8         reserved_0[0x20];
2121
2122         u8         group_id[0x20];
2123
2124         u8         reserved_1[0x8];
2125         u8         flow_tag[0x18];
2126
2127         u8         reserved_2[0x10];
2128         u8         action[0x10];
2129
2130         u8         reserved_3[0x8];
2131         u8         destination_list_size[0x18];
2132
2133         u8         reserved_4[0x8];
2134         u8         flow_counter_list_size[0x18];
2135
2136         u8         reserved_5[0x140];
2137
2138         struct mlx5_ifc_fte_match_param_bits match_value;
2139
2140         u8         reserved_6[0x600];
2141
2142         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2143 };
2144
2145 enum {
2146         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2147         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2148 };
2149
2150 struct mlx5_ifc_xrc_srqc_bits {
2151         u8         state[0x4];
2152         u8         log_xrc_srq_size[0x4];
2153         u8         reserved_0[0x18];
2154
2155         u8         wq_signature[0x1];
2156         u8         cont_srq[0x1];
2157         u8         reserved_1[0x1];
2158         u8         rlky[0x1];
2159         u8         basic_cyclic_rcv_wqe[0x1];
2160         u8         log_rq_stride[0x3];
2161         u8         xrcd[0x18];
2162
2163         u8         page_offset[0x6];
2164         u8         reserved_2[0x2];
2165         u8         cqn[0x18];
2166
2167         u8         reserved_3[0x20];
2168
2169         u8         reserved_4[0x2];
2170         u8         log_page_size[0x6];
2171         u8         user_index[0x18];
2172
2173         u8         reserved_5[0x20];
2174
2175         u8         reserved_6[0x8];
2176         u8         pd[0x18];
2177
2178         u8         lwm[0x10];
2179         u8         wqe_cnt[0x10];
2180
2181         u8         reserved_7[0x40];
2182
2183         u8         db_record_addr_h[0x20];
2184
2185         u8         db_record_addr_l[0x1e];
2186         u8         reserved_8[0x2];
2187
2188         u8         reserved_9[0x80];
2189 };
2190
2191 struct mlx5_ifc_traffic_counter_bits {
2192         u8         packets[0x40];
2193
2194         u8         octets[0x40];
2195 };
2196
2197 struct mlx5_ifc_tisc_bits {
2198         u8         strict_lag_tx_port_affinity[0x1];
2199         u8         reserved_at_1[0x3];
2200         u8         lag_tx_port_affinity[0x04];
2201
2202         u8         reserved_at_8[0x4];
2203         u8         prio[0x4];
2204         u8         reserved_1[0x10];
2205
2206         u8         reserved_2[0x100];
2207
2208         u8         reserved_3[0x8];
2209         u8         transport_domain[0x18];
2210
2211         u8         reserved_4[0x8];
2212         u8         underlay_qpn[0x18];
2213
2214         u8         reserved_5[0x3a0];
2215 };
2216
2217 enum {
2218         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2219         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2220 };
2221
2222 enum {
2223         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2224         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2225 };
2226
2227 enum {
2228         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2229         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2230         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2231 };
2232
2233 enum {
2234         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2235         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2236 };
2237
2238 struct mlx5_ifc_tirc_bits {
2239         u8         reserved_0[0x20];
2240
2241         u8         disp_type[0x4];
2242         u8         reserved_1[0x1c];
2243
2244         u8         reserved_2[0x40];
2245
2246         u8         reserved_3[0x4];
2247         u8         lro_timeout_period_usecs[0x10];
2248         u8         lro_enable_mask[0x4];
2249         u8         lro_max_msg_sz[0x8];
2250
2251         u8         reserved_4[0x40];
2252
2253         u8         reserved_5[0x8];
2254         u8         inline_rqn[0x18];
2255
2256         u8         rx_hash_symmetric[0x1];
2257         u8         reserved_6[0x1];
2258         u8         tunneled_offload_en[0x1];
2259         u8         reserved_7[0x5];
2260         u8         indirect_table[0x18];
2261
2262         u8         rx_hash_fn[0x4];
2263         u8         reserved_8[0x2];
2264         u8         self_lb_en[0x2];
2265         u8         transport_domain[0x18];
2266
2267         u8         rx_hash_toeplitz_key[10][0x20];
2268
2269         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2270
2271         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2272
2273         u8         reserved_9[0x4c0];
2274 };
2275
2276 enum {
2277         MLX5_SRQC_STATE_GOOD   = 0x0,
2278         MLX5_SRQC_STATE_ERROR  = 0x1,
2279 };
2280
2281 struct mlx5_ifc_srqc_bits {
2282         u8         state[0x4];
2283         u8         log_srq_size[0x4];
2284         u8         reserved_0[0x18];
2285
2286         u8         wq_signature[0x1];
2287         u8         cont_srq[0x1];
2288         u8         reserved_1[0x1];
2289         u8         rlky[0x1];
2290         u8         reserved_2[0x1];
2291         u8         log_rq_stride[0x3];
2292         u8         xrcd[0x18];
2293
2294         u8         page_offset[0x6];
2295         u8         reserved_3[0x2];
2296         u8         cqn[0x18];
2297
2298         u8         reserved_4[0x20];
2299
2300         u8         reserved_5[0x2];
2301         u8         log_page_size[0x6];
2302         u8         reserved_6[0x18];
2303
2304         u8         reserved_7[0x20];
2305
2306         u8         reserved_8[0x8];
2307         u8         pd[0x18];
2308
2309         u8         lwm[0x10];
2310         u8         wqe_cnt[0x10];
2311
2312         u8         reserved_9[0x40];
2313
2314         u8         dbr_addr[0x40];
2315
2316         u8         reserved_10[0x80];
2317 };
2318
2319 enum {
2320         MLX5_SQC_STATE_RST  = 0x0,
2321         MLX5_SQC_STATE_RDY  = 0x1,
2322         MLX5_SQC_STATE_ERR  = 0x3,
2323 };
2324
2325 struct mlx5_ifc_sqc_bits {
2326         u8         rlkey[0x1];
2327         u8         cd_master[0x1];
2328         u8         fre[0x1];
2329         u8         flush_in_error_en[0x1];
2330         u8         allow_multi_pkt_send_wqe[0x1];
2331         u8         min_wqe_inline_mode[0x3];
2332         u8         state[0x4];
2333         u8         reg_umr[0x1];
2334         u8         allow_swp[0x1];
2335         u8         reserved_0[0x12];
2336
2337         u8         reserved_1[0x8];
2338         u8         user_index[0x18];
2339
2340         u8         reserved_2[0x8];
2341         u8         cqn[0x18];
2342
2343         u8         reserved_3[0x80];
2344
2345         u8         qos_para_vport_number[0x10];
2346         u8         packet_pacing_rate_limit_index[0x10];
2347
2348         u8         tis_lst_sz[0x10];
2349         u8         reserved_4[0x10];
2350
2351         u8         reserved_5[0x40];
2352
2353         u8         reserved_6[0x8];
2354         u8         tis_num_0[0x18];
2355
2356         struct mlx5_ifc_wq_bits wq;
2357 };
2358
2359 enum {
2360         MLX5_TSAR_TYPE_DWRR = 0,
2361         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2362         MLX5_TSAR_TYPE_ETS = 2
2363 };
2364
2365 struct mlx5_ifc_tsar_element_attributes_bits {
2366         u8         reserved_0[0x8];
2367         u8         tsar_type[0x8];
2368         u8         reserved_1[0x10];
2369 };
2370
2371 struct mlx5_ifc_vport_element_attributes_bits {
2372         u8         reserved_0[0x10];
2373         u8         vport_number[0x10];
2374 };
2375
2376 struct mlx5_ifc_vport_tc_element_attributes_bits {
2377         u8         traffic_class[0x10];
2378         u8         vport_number[0x10];
2379 };
2380
2381 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2382         u8         reserved_0[0x0C];
2383         u8         traffic_class[0x04];
2384         u8         qos_para_vport_number[0x10];
2385 };
2386
2387 enum {
2388         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2389         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2390         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2391         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2392 };
2393
2394 struct mlx5_ifc_scheduling_context_bits {
2395         u8         element_type[0x8];
2396         u8         reserved_at_8[0x18];
2397
2398         u8         element_attributes[0x20];
2399
2400         u8         parent_element_id[0x20];
2401
2402         u8         reserved_at_60[0x40];
2403
2404         u8         bw_share[0x20];
2405
2406         u8         max_average_bw[0x20];
2407
2408         u8         reserved_at_e0[0x120];
2409 };
2410
2411 struct mlx5_ifc_rqtc_bits {
2412         u8         reserved_0[0xa0];
2413
2414         u8         reserved_1[0x10];
2415         u8         rqt_max_size[0x10];
2416
2417         u8         reserved_2[0x10];
2418         u8         rqt_actual_size[0x10];
2419
2420         u8         reserved_3[0x6a0];
2421
2422         struct mlx5_ifc_rq_num_bits rq_num[0];
2423 };
2424
2425 enum {
2426         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2427         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2428 };
2429
2430 enum {
2431         MLX5_RQC_STATE_RST  = 0x0,
2432         MLX5_RQC_STATE_RDY  = 0x1,
2433         MLX5_RQC_STATE_ERR  = 0x3,
2434 };
2435
2436 enum {
2437         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2438         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2439 };
2440
2441 struct mlx5_ifc_rqc_bits {
2442         u8         rlkey[0x1];
2443         u8         delay_drop_en[0x1];
2444         u8         scatter_fcs[0x1];
2445         u8         vlan_strip_disable[0x1];
2446         u8         mem_rq_type[0x4];
2447         u8         state[0x4];
2448         u8         reserved_1[0x1];
2449         u8         flush_in_error_en[0x1];
2450         u8         reserved_2[0x12];
2451
2452         u8         reserved_3[0x8];
2453         u8         user_index[0x18];
2454
2455         u8         reserved_4[0x8];
2456         u8         cqn[0x18];
2457
2458         u8         counter_set_id[0x8];
2459         u8         reserved_5[0x18];
2460
2461         u8         reserved_6[0x8];
2462         u8         rmpn[0x18];
2463
2464         u8         reserved_7[0xe0];
2465
2466         struct mlx5_ifc_wq_bits wq;
2467 };
2468
2469 enum {
2470         MLX5_RMPC_STATE_RDY  = 0x1,
2471         MLX5_RMPC_STATE_ERR  = 0x3,
2472 };
2473
2474 struct mlx5_ifc_rmpc_bits {
2475         u8         reserved_0[0x8];
2476         u8         state[0x4];
2477         u8         reserved_1[0x14];
2478
2479         u8         basic_cyclic_rcv_wqe[0x1];
2480         u8         reserved_2[0x1f];
2481
2482         u8         reserved_3[0x140];
2483
2484         struct mlx5_ifc_wq_bits wq;
2485 };
2486
2487 enum {
2488         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2489         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2490         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2491 };
2492
2493 struct mlx5_ifc_nic_vport_context_bits {
2494         u8         reserved_0[0x5];
2495         u8         min_wqe_inline_mode[0x3];
2496         u8         reserved_1[0x15];
2497         u8         disable_mc_local_lb[0x1];
2498         u8         disable_uc_local_lb[0x1];
2499         u8         roce_en[0x1];
2500
2501         u8         arm_change_event[0x1];
2502         u8         reserved_2[0x1a];
2503         u8         event_on_mtu[0x1];
2504         u8         event_on_promisc_change[0x1];
2505         u8         event_on_vlan_change[0x1];
2506         u8         event_on_mc_address_change[0x1];
2507         u8         event_on_uc_address_change[0x1];
2508
2509         u8         reserved_3[0xe0];
2510
2511         u8         reserved_4[0x10];
2512         u8         mtu[0x10];
2513
2514         u8         system_image_guid[0x40];
2515
2516         u8         port_guid[0x40];
2517
2518         u8         node_guid[0x40];
2519
2520         u8         reserved_5[0x140];
2521
2522         u8         qkey_violation_counter[0x10];
2523         u8         reserved_6[0x10];
2524
2525         u8         reserved_7[0x420];
2526
2527         u8         promisc_uc[0x1];
2528         u8         promisc_mc[0x1];
2529         u8         promisc_all[0x1];
2530         u8         reserved_8[0x2];
2531         u8         allowed_list_type[0x3];
2532         u8         reserved_9[0xc];
2533         u8         allowed_list_size[0xc];
2534
2535         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2536
2537         u8         reserved_10[0x20];
2538
2539         u8         current_uc_mac_address[0][0x40];
2540 };
2541
2542 enum {
2543         MLX5_ACCESS_MODE_PA        = 0x0,
2544         MLX5_ACCESS_MODE_MTT       = 0x1,
2545         MLX5_ACCESS_MODE_KLM       = 0x2,
2546 };
2547
2548 struct mlx5_ifc_mkc_bits {
2549         u8         reserved_at_0[0x1];
2550         u8         free[0x1];
2551         u8         reserved_at_2[0x1];
2552         u8         access_mode_4_2[0x3];
2553         u8         reserved_at_6[0x7];
2554         u8         relaxed_ordering_write[0x1];
2555         u8         reserved_at_e[0x1];
2556         u8         small_fence_on_rdma_read_response[0x1];
2557         u8         umr_en[0x1];
2558         u8         a[0x1];
2559         u8         rw[0x1];
2560         u8         rr[0x1];
2561         u8         lw[0x1];
2562         u8         lr[0x1];
2563         u8         access_mode[0x2];
2564         u8         reserved_2[0x8];
2565
2566         u8         qpn[0x18];
2567         u8         mkey_7_0[0x8];
2568
2569         u8         reserved_3[0x20];
2570
2571         u8         length64[0x1];
2572         u8         bsf_en[0x1];
2573         u8         sync_umr[0x1];
2574         u8         reserved_4[0x2];
2575         u8         expected_sigerr_count[0x1];
2576         u8         reserved_5[0x1];
2577         u8         en_rinval[0x1];
2578         u8         pd[0x18];
2579
2580         u8         start_addr[0x40];
2581
2582         u8         len[0x40];
2583
2584         u8         bsf_octword_size[0x20];
2585
2586         u8         reserved_6[0x80];
2587
2588         u8         translations_octword_size[0x20];
2589
2590         u8         reserved_7[0x1b];
2591         u8         log_page_size[0x5];
2592
2593         u8         reserved_8[0x20];
2594 };
2595
2596 struct mlx5_ifc_pkey_bits {
2597         u8         reserved_0[0x10];
2598         u8         pkey[0x10];
2599 };
2600
2601 struct mlx5_ifc_array128_auto_bits {
2602         u8         array128_auto[16][0x8];
2603 };
2604
2605 enum {
2606         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2607         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2608         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2609 };
2610
2611 enum {
2612         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2613         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2614         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2615         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2616         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2617         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2618         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2619 };
2620
2621 enum {
2622         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2623         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2624         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2625 };
2626
2627 enum {
2628         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2629         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2630         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2631         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2632 };
2633
2634 enum {
2635         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2636         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2637         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2638         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2639 };
2640
2641 struct mlx5_ifc_hca_vport_context_bits {
2642         u8         field_select[0x20];
2643
2644         u8         reserved_0[0xe0];
2645
2646         u8         sm_virt_aware[0x1];
2647         u8         has_smi[0x1];
2648         u8         has_raw[0x1];
2649         u8         grh_required[0x1];
2650         u8         reserved_1[0x1];
2651         u8         min_wqe_inline_mode[0x3];
2652         u8         reserved_2[0x8];
2653         u8         port_physical_state[0x4];
2654         u8         vport_state_policy[0x4];
2655         u8         port_state[0x4];
2656         u8         vport_state[0x4];
2657
2658         u8         reserved_3[0x20];
2659
2660         u8         system_image_guid[0x40];
2661
2662         u8         port_guid[0x40];
2663
2664         u8         node_guid[0x40];
2665
2666         u8         cap_mask1[0x20];
2667
2668         u8         cap_mask1_field_select[0x20];
2669
2670         u8         cap_mask2[0x20];
2671
2672         u8         cap_mask2_field_select[0x20];
2673
2674         u8         reserved_4[0x80];
2675
2676         u8         lid[0x10];
2677         u8         reserved_5[0x4];
2678         u8         init_type_reply[0x4];
2679         u8         lmc[0x3];
2680         u8         subnet_timeout[0x5];
2681
2682         u8         sm_lid[0x10];
2683         u8         sm_sl[0x4];
2684         u8         reserved_6[0xc];
2685
2686         u8         qkey_violation_counter[0x10];
2687         u8         pkey_violation_counter[0x10];
2688
2689         u8         reserved_7[0xca0];
2690 };
2691
2692 union mlx5_ifc_hca_cap_union_bits {
2693         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2694         struct mlx5_ifc_odp_cap_bits odp_cap;
2695         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2696         struct mlx5_ifc_roce_cap_bits roce_cap;
2697         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2698         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2699         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2700         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2701         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2702         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2703         struct mlx5_ifc_qos_cap_bits qos_cap;
2704         u8         reserved_0[0x8000];
2705 };
2706
2707 enum {
2708         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2709         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2710 };
2711
2712 struct mlx5_ifc_flow_table_context_bits {
2713         u8         encap_en[0x1];
2714         u8         decap_en[0x1];
2715         u8         reserved_at_2[0x2];
2716         u8         table_miss_action[0x4];
2717         u8         level[0x8];
2718         u8         reserved_at_10[0x8];
2719         u8         log_size[0x8];
2720
2721         u8         reserved_at_20[0x8];
2722         u8         table_miss_id[0x18];
2723
2724         u8         reserved_at_40[0x8];
2725         u8         lag_master_next_table_id[0x18];
2726
2727         u8         reserved_at_60[0xe0];
2728 };
2729
2730 struct mlx5_ifc_esw_vport_context_bits {
2731         u8         reserved_0[0x3];
2732         u8         vport_svlan_strip[0x1];
2733         u8         vport_cvlan_strip[0x1];
2734         u8         vport_svlan_insert[0x1];
2735         u8         vport_cvlan_insert[0x2];
2736         u8         reserved_1[0x18];
2737
2738         u8         reserved_2[0x20];
2739
2740         u8         svlan_cfi[0x1];
2741         u8         svlan_pcp[0x3];
2742         u8         svlan_id[0xc];
2743         u8         cvlan_cfi[0x1];
2744         u8         cvlan_pcp[0x3];
2745         u8         cvlan_id[0xc];
2746
2747         u8         reserved_3[0x7a0];
2748 };
2749
2750 enum {
2751         MLX5_EQC_STATUS_OK                = 0x0,
2752         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2753 };
2754
2755 enum {
2756         MLX5_EQ_STATE_ARMED = 0x9,
2757         MLX5_EQ_STATE_FIRED = 0xa,
2758 };
2759
2760 struct mlx5_ifc_eqc_bits {
2761         u8         status[0x4];
2762         u8         reserved_0[0x9];
2763         u8         ec[0x1];
2764         u8         oi[0x1];
2765         u8         reserved_1[0x5];
2766         u8         st[0x4];
2767         u8         reserved_2[0x8];
2768
2769         u8         reserved_3[0x20];
2770
2771         u8         reserved_4[0x14];
2772         u8         page_offset[0x6];
2773         u8         reserved_5[0x6];
2774
2775         u8         reserved_6[0x3];
2776         u8         log_eq_size[0x5];
2777         u8         uar_page[0x18];
2778
2779         u8         reserved_7[0x20];
2780
2781         u8         reserved_8[0x18];
2782         u8         intr[0x8];
2783
2784         u8         reserved_9[0x3];
2785         u8         log_page_size[0x5];
2786         u8         reserved_10[0x18];
2787
2788         u8         reserved_11[0x60];
2789
2790         u8         reserved_12[0x8];
2791         u8         consumer_counter[0x18];
2792
2793         u8         reserved_13[0x8];
2794         u8         producer_counter[0x18];
2795
2796         u8         reserved_14[0x80];
2797 };
2798
2799 enum {
2800         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2801         MLX5_DCTC_STATE_DRAINING  = 0x1,
2802         MLX5_DCTC_STATE_DRAINED   = 0x2,
2803 };
2804
2805 enum {
2806         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2807         MLX5_DCTC_CS_RES_NA         = 0x1,
2808         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2809 };
2810
2811 enum {
2812         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2813         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2814         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2815         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2816         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2817 };
2818
2819 struct mlx5_ifc_dctc_bits {
2820         u8         reserved_0[0x4];
2821         u8         state[0x4];
2822         u8         reserved_1[0x18];
2823
2824         u8         reserved_2[0x8];
2825         u8         user_index[0x18];
2826
2827         u8         reserved_3[0x8];
2828         u8         cqn[0x18];
2829
2830         u8         counter_set_id[0x8];
2831         u8         atomic_mode[0x4];
2832         u8         rre[0x1];
2833         u8         rwe[0x1];
2834         u8         rae[0x1];
2835         u8         atomic_like_write_en[0x1];
2836         u8         latency_sensitive[0x1];
2837         u8         rlky[0x1];
2838         u8         reserved_4[0xe];
2839
2840         u8         reserved_5[0x8];
2841         u8         cs_res[0x8];
2842         u8         reserved_6[0x3];
2843         u8         min_rnr_nak[0x5];
2844         u8         reserved_7[0x8];
2845
2846         u8         reserved_8[0x8];
2847         u8         srqn[0x18];
2848
2849         u8         reserved_9[0x8];
2850         u8         pd[0x18];
2851
2852         u8         tclass[0x8];
2853         u8         reserved_10[0x4];
2854         u8         flow_label[0x14];
2855
2856         u8         dc_access_key[0x40];
2857
2858         u8         reserved_11[0x5];
2859         u8         mtu[0x3];
2860         u8         port[0x8];
2861         u8         pkey_index[0x10];
2862
2863         u8         reserved_12[0x8];
2864         u8         my_addr_index[0x8];
2865         u8         reserved_13[0x8];
2866         u8         hop_limit[0x8];
2867
2868         u8         dc_access_key_violation_count[0x20];
2869
2870         u8         reserved_14[0x14];
2871         u8         dei_cfi[0x1];
2872         u8         eth_prio[0x3];
2873         u8         ecn[0x2];
2874         u8         dscp[0x6];
2875
2876         u8         reserved_15[0x40];
2877 };
2878
2879 enum {
2880         MLX5_CQC_STATUS_OK             = 0x0,
2881         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2882         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2883 };
2884
2885 enum {
2886         CQE_SIZE_64                = 0x0,
2887         CQE_SIZE_128               = 0x1,
2888 };
2889
2890 enum {
2891         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2892         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2893 };
2894
2895 enum {
2896         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2897         MLX5_CQ_STATE_ARMED                               = 0x9,
2898         MLX5_CQ_STATE_FIRED                               = 0xa,
2899 };
2900
2901 struct mlx5_ifc_cqc_bits {
2902         u8         status[0x4];
2903         u8         reserved_0[0x4];
2904         u8         cqe_sz[0x3];
2905         u8         cc[0x1];
2906         u8         reserved_1[0x1];
2907         u8         scqe_break_moderation_en[0x1];
2908         u8         oi[0x1];
2909         u8         cq_period_mode[0x2];
2910         u8         cqe_compression_en[0x1];
2911         u8         mini_cqe_res_format[0x2];
2912         u8         st[0x4];
2913         u8         reserved_2[0x8];
2914
2915         u8         reserved_3[0x20];
2916
2917         u8         reserved_4[0x14];
2918         u8         page_offset[0x6];
2919         u8         reserved_5[0x6];
2920
2921         u8         reserved_6[0x3];
2922         u8         log_cq_size[0x5];
2923         u8         uar_page[0x18];
2924
2925         u8         reserved_7[0x4];
2926         u8         cq_period[0xc];
2927         u8         cq_max_count[0x10];
2928
2929         u8         reserved_8[0x18];
2930         u8         c_eqn[0x8];
2931
2932         u8         reserved_9[0x3];
2933         u8         log_page_size[0x5];
2934         u8         reserved_10[0x18];
2935
2936         u8         reserved_11[0x20];
2937
2938         u8         reserved_12[0x8];
2939         u8         last_notified_index[0x18];
2940
2941         u8         reserved_13[0x8];
2942         u8         last_solicit_index[0x18];
2943
2944         u8         reserved_14[0x8];
2945         u8         consumer_counter[0x18];
2946
2947         u8         reserved_15[0x8];
2948         u8         producer_counter[0x18];
2949
2950         u8         reserved_16[0x40];
2951
2952         u8         dbr_addr[0x40];
2953 };
2954
2955 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2956         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2957         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2958         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2959         u8         reserved_0[0x800];
2960 };
2961
2962 struct mlx5_ifc_query_adapter_param_block_bits {
2963         u8         reserved_0[0xc0];
2964
2965         u8         reserved_1[0x8];
2966         u8         ieee_vendor_id[0x18];
2967
2968         u8         reserved_2[0x10];
2969         u8         vsd_vendor_id[0x10];
2970
2971         u8         vsd[208][0x8];
2972
2973         u8         vsd_contd_psid[16][0x8];
2974 };
2975
2976 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2977         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2978         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2979         u8         reserved_0[0x20];
2980 };
2981
2982 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2983         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2984         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2985         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2986         u8         reserved_0[0x20];
2987 };
2988
2989 struct mlx5_ifc_bufferx_reg_bits {
2990         u8         reserved_0[0x6];
2991         u8         lossy[0x1];
2992         u8         epsb[0x1];
2993         u8         reserved_1[0xc];
2994         u8         size[0xc];
2995
2996         u8         xoff_threshold[0x10];
2997         u8         xon_threshold[0x10];
2998 };
2999
3000 struct mlx5_ifc_config_item_bits {
3001         u8         valid[0x2];
3002         u8         reserved_0[0x2];
3003         u8         header_type[0x2];
3004         u8         reserved_1[0x2];
3005         u8         default_location[0x1];
3006         u8         reserved_2[0x7];
3007         u8         version[0x4];
3008         u8         reserved_3[0x3];
3009         u8         length[0x9];
3010
3011         u8         type[0x20];
3012
3013         u8         reserved_4[0x10];
3014         u8         crc16[0x10];
3015 };
3016
3017 struct mlx5_ifc_nodnic_port_config_reg_bits {
3018         struct mlx5_ifc_nodnic_event_word_bits event;
3019
3020         u8         network_en[0x1];
3021         u8         dma_en[0x1];
3022         u8         promisc_en[0x1];
3023         u8         promisc_multicast_en[0x1];
3024         u8         reserved_0[0x17];
3025         u8         receive_filter_en[0x5];
3026
3027         u8         reserved_1[0x10];
3028         u8         mac_47_32[0x10];
3029
3030         u8         mac_31_0[0x20];
3031
3032         u8         receive_filters_mgid_mac[64][0x8];
3033
3034         u8         gid[16][0x8];
3035
3036         u8         reserved_2[0x10];
3037         u8         lid[0x10];
3038
3039         u8         reserved_3[0xc];
3040         u8         sm_sl[0x4];
3041         u8         sm_lid[0x10];
3042
3043         u8         completion_address_63_32[0x20];
3044
3045         u8         completion_address_31_12[0x14];
3046         u8         reserved_4[0x6];
3047         u8         log_cq_size[0x6];
3048
3049         u8         working_buffer_address_63_32[0x20];
3050
3051         u8         working_buffer_address_31_12[0x14];
3052         u8         reserved_5[0xc];
3053
3054         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3055
3056         u8         pkey_index[0x10];
3057         u8         pkey[0x10];
3058
3059         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3060
3061         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3062
3063         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3064
3065         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3066
3067         u8         reserved_6[0x400];
3068 };
3069
3070 union mlx5_ifc_event_auto_bits {
3071         struct mlx5_ifc_comp_event_bits comp_event;
3072         struct mlx5_ifc_dct_events_bits dct_events;
3073         struct mlx5_ifc_qp_events_bits qp_events;
3074         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3075         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3076         struct mlx5_ifc_cq_error_bits cq_error;
3077         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3078         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3079         struct mlx5_ifc_gpio_event_bits gpio_event;
3080         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3081         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3082         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3083         struct mlx5_ifc_pages_req_event_bits pages_req_event;
3084         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3085         u8         reserved_0[0xe0];
3086 };
3087
3088 struct mlx5_ifc_health_buffer_bits {
3089         u8         reserved_0[0x100];
3090
3091         u8         assert_existptr[0x20];
3092
3093         u8         assert_callra[0x20];
3094
3095         u8         reserved_1[0x40];
3096
3097         u8         fw_version[0x20];
3098
3099         u8         hw_id[0x20];
3100
3101         u8         reserved_2[0x20];
3102
3103         u8         irisc_index[0x8];
3104         u8         synd[0x8];
3105         u8         ext_synd[0x10];
3106 };
3107
3108 struct mlx5_ifc_register_loopback_control_bits {
3109         u8         no_lb[0x1];
3110         u8         reserved_0[0x7];
3111         u8         port[0x8];
3112         u8         reserved_1[0x10];
3113
3114         u8         reserved_2[0x60];
3115 };
3116
3117 struct mlx5_ifc_lrh_bits {
3118         u8      vl[4];
3119         u8      lver[4];
3120         u8      sl[4];
3121         u8      reserved2[2];
3122         u8      lnh[2];
3123         u8      dlid[16];
3124         u8      reserved5[5];
3125         u8      pkt_len[11];
3126         u8      slid[16];
3127 };
3128
3129 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3130         u8         reserved_0[0x40];
3131
3132         u8         reserved_1[0x10];
3133         u8         rol_mode[0x8];
3134         u8         wol_mode[0x8];
3135 };
3136
3137 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3138         u8         reserved_0[0x40];
3139
3140         u8         rol_mode_valid[0x1];
3141         u8         wol_mode_valid[0x1];
3142         u8         reserved_1[0xe];
3143         u8         rol_mode[0x8];
3144         u8         wol_mode[0x8];
3145
3146         u8         reserved_2[0x7a0];
3147 };
3148
3149 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3150         u8         virtual_mac_en[0x1];
3151         u8         mac_aux_v[0x1];
3152         u8         reserved_0[0x1e];
3153
3154         u8         reserved_1[0x40];
3155
3156         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3157
3158         u8         reserved_2[0x760];
3159 };
3160
3161 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3162         u8         virtual_mac_en[0x1];
3163         u8         mac_aux_v[0x1];
3164         u8         reserved_0[0x1e];
3165
3166         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3167
3168         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3169
3170         u8         reserved_1[0x760];
3171 };
3172
3173 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3174         struct mlx5_ifc_fw_version_bits fw_version;
3175
3176         u8         reserved_0[0x10];
3177         u8         hash_signature[0x10];
3178
3179         u8         psid[16][0x8];
3180
3181         u8         reserved_1[0x6e0];
3182 };
3183
3184 struct mlx5_ifc_icmd_query_cap_in_bits {
3185         u8         reserved_0[0x10];
3186         u8         capability_group[0x10];
3187 };
3188
3189 struct mlx5_ifc_icmd_query_cap_general_bits {
3190         u8         nv_access[0x1];
3191         u8         fw_info_psid[0x1];
3192         u8         reserved_0[0x1e];
3193
3194         u8         reserved_1[0x16];
3195         u8         rol_s[0x1];
3196         u8         rol_g[0x1];
3197         u8         reserved_2[0x1];
3198         u8         wol_s[0x1];
3199         u8         wol_g[0x1];
3200         u8         wol_a[0x1];
3201         u8         wol_b[0x1];
3202         u8         wol_m[0x1];
3203         u8         wol_u[0x1];
3204         u8         wol_p[0x1];
3205 };
3206
3207 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3208         u8         status[0x8];
3209         u8         reserved_0[0x18];
3210
3211         u8         reserved_1[0x7e0];
3212 };
3213
3214 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3215         u8         status[0x8];
3216         u8         reserved_0[0x18];
3217
3218         u8         reserved_1[0x7e0];
3219 };
3220
3221 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3222         u8         address_hi[0x20];
3223
3224         u8         address_lo[0x20];
3225
3226         u8         reserved_0[0x7c0];
3227 };
3228
3229 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3230         u8         reserved_0[0x20];
3231
3232         u8         address_hi[0x20];
3233
3234         u8         address_lo[0x20];
3235
3236         u8         reserved_1[0x7a0];
3237 };
3238
3239 struct mlx5_ifc_icmd_access_reg_out_bits {
3240         u8         reserved_0[0x11];
3241         u8         status[0x7];
3242         u8         reserved_1[0x8];
3243
3244         u8         register_id[0x10];
3245         u8         reserved_2[0x10];
3246
3247         u8         reserved_3[0x40];
3248
3249         u8         reserved_4[0x5];
3250         u8         len[0xb];
3251         u8         reserved_5[0x10];
3252
3253         u8         register_data[0][0x20];
3254 };
3255
3256 enum {
3257         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3258         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3259 };
3260
3261 struct mlx5_ifc_icmd_access_reg_in_bits {
3262         u8         constant_1[0x5];
3263         u8         constant_2[0xb];
3264         u8         reserved_0[0x10];
3265
3266         u8         register_id[0x10];
3267         u8         reserved_1[0x1];
3268         u8         method[0x7];
3269         u8         constant_3[0x8];
3270
3271         u8         reserved_2[0x40];
3272
3273         u8         constant_4[0x5];
3274         u8         len[0xb];
3275         u8         reserved_3[0x10];
3276
3277         u8         register_data[0][0x20];
3278 };
3279
3280 enum {
3281         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3282         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3283 };
3284
3285 struct mlx5_ifc_teardown_hca_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_0[0x18];
3288
3289         u8         syndrome[0x20];
3290
3291         u8         reserved_1[0x3f];
3292
3293         u8         state[0x1];
3294 };
3295
3296 enum {
3297         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3298         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3299         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3300 };
3301
3302 struct mlx5_ifc_teardown_hca_in_bits {
3303         u8         opcode[0x10];
3304         u8         reserved_0[0x10];
3305
3306         u8         reserved_1[0x10];
3307         u8         op_mod[0x10];
3308
3309         u8         reserved_2[0x10];
3310         u8         profile[0x10];
3311
3312         u8         reserved_3[0x20];
3313 };
3314
3315 struct mlx5_ifc_set_delay_drop_params_out_bits {
3316         u8         status[0x8];
3317         u8         reserved_at_8[0x18];
3318
3319         u8         syndrome[0x20];
3320
3321         u8         reserved_at_40[0x40];
3322 };
3323
3324 struct mlx5_ifc_set_delay_drop_params_in_bits {
3325         u8         opcode[0x10];
3326         u8         reserved_at_10[0x10];
3327
3328         u8         reserved_at_20[0x10];
3329         u8         op_mod[0x10];
3330
3331         u8         reserved_at_40[0x20];
3332
3333         u8         reserved_at_60[0x10];
3334         u8         delay_drop_timeout[0x10];
3335 };
3336
3337 struct mlx5_ifc_query_delay_drop_params_out_bits {
3338         u8         status[0x8];
3339         u8         reserved_at_8[0x18];
3340
3341         u8         syndrome[0x20];
3342
3343         u8         reserved_at_40[0x20];
3344
3345         u8         reserved_at_60[0x10];
3346         u8         delay_drop_timeout[0x10];
3347 };
3348
3349 struct mlx5_ifc_query_delay_drop_params_in_bits {
3350         u8         opcode[0x10];
3351         u8         reserved_at_10[0x10];
3352
3353         u8         reserved_at_20[0x10];
3354         u8         op_mod[0x10];
3355
3356         u8         reserved_at_40[0x40];
3357 };
3358
3359 struct mlx5_ifc_suspend_qp_out_bits {
3360         u8         status[0x8];
3361         u8         reserved_0[0x18];
3362
3363         u8         syndrome[0x20];
3364
3365         u8         reserved_1[0x40];
3366 };
3367
3368 struct mlx5_ifc_suspend_qp_in_bits {
3369         u8         opcode[0x10];
3370         u8         reserved_0[0x10];
3371
3372         u8         reserved_1[0x10];
3373         u8         op_mod[0x10];
3374
3375         u8         reserved_2[0x8];
3376         u8         qpn[0x18];
3377
3378         u8         reserved_3[0x20];
3379 };
3380
3381 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3382         u8         status[0x8];
3383         u8         reserved_0[0x18];
3384
3385         u8         syndrome[0x20];
3386
3387         u8         reserved_1[0x40];
3388 };
3389
3390 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3391         u8         opcode[0x10];
3392         u8         reserved_0[0x10];
3393
3394         u8         reserved_1[0x10];
3395         u8         op_mod[0x10];
3396
3397         u8         reserved_2[0x8];
3398         u8         qpn[0x18];
3399
3400         u8         reserved_3[0x20];
3401
3402         u8         opt_param_mask[0x20];
3403
3404         u8         reserved_4[0x20];
3405
3406         struct mlx5_ifc_qpc_bits qpc;
3407
3408         u8         reserved_5[0x80];
3409 };
3410
3411 struct mlx5_ifc_sqd2rts_qp_out_bits {
3412         u8         status[0x8];
3413         u8         reserved_0[0x18];
3414
3415         u8         syndrome[0x20];
3416
3417         u8         reserved_1[0x40];
3418 };
3419
3420 struct mlx5_ifc_sqd2rts_qp_in_bits {
3421         u8         opcode[0x10];
3422         u8         reserved_0[0x10];
3423
3424         u8         reserved_1[0x10];
3425         u8         op_mod[0x10];
3426
3427         u8         reserved_2[0x8];
3428         u8         qpn[0x18];
3429
3430         u8         reserved_3[0x20];
3431
3432         u8         opt_param_mask[0x20];
3433
3434         u8         reserved_4[0x20];
3435
3436         struct mlx5_ifc_qpc_bits qpc;
3437
3438         u8         reserved_5[0x80];
3439 };
3440
3441 struct mlx5_ifc_set_wol_rol_out_bits {
3442         u8         status[0x8];
3443         u8         reserved_0[0x18];
3444
3445         u8         syndrome[0x20];
3446
3447         u8         reserved_1[0x40];
3448 };
3449
3450 struct mlx5_ifc_set_wol_rol_in_bits {
3451         u8         opcode[0x10];
3452         u8         reserved_0[0x10];
3453
3454         u8         reserved_1[0x10];
3455         u8         op_mod[0x10];
3456
3457         u8         rol_mode_valid[0x1];
3458         u8         wol_mode_valid[0x1];
3459         u8         reserved_2[0xe];
3460         u8         rol_mode[0x8];
3461         u8         wol_mode[0x8];
3462
3463         u8         reserved_3[0x20];
3464 };
3465
3466 struct mlx5_ifc_set_roce_address_out_bits {
3467         u8         status[0x8];
3468         u8         reserved_0[0x18];
3469
3470         u8         syndrome[0x20];
3471
3472         u8         reserved_1[0x40];
3473 };
3474
3475 struct mlx5_ifc_set_roce_address_in_bits {
3476         u8         opcode[0x10];
3477         u8         reserved_0[0x10];
3478
3479         u8         reserved_1[0x10];
3480         u8         op_mod[0x10];
3481
3482         u8         roce_address_index[0x10];
3483         u8         reserved_2[0x10];
3484
3485         u8         reserved_3[0x20];
3486
3487         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3488 };
3489
3490 struct mlx5_ifc_set_rdb_out_bits {
3491         u8         status[0x8];
3492         u8         reserved_0[0x18];
3493
3494         u8         syndrome[0x20];
3495
3496         u8         reserved_1[0x40];
3497 };
3498
3499 struct mlx5_ifc_set_rdb_in_bits {
3500         u8         opcode[0x10];
3501         u8         reserved_0[0x10];
3502
3503         u8         reserved_1[0x10];
3504         u8         op_mod[0x10];
3505
3506         u8         reserved_2[0x8];
3507         u8         qpn[0x18];
3508
3509         u8         reserved_3[0x18];
3510         u8         rdb_list_size[0x8];
3511
3512         struct mlx5_ifc_rdbc_bits rdb_context[0];
3513 };
3514
3515 struct mlx5_ifc_set_mad_demux_out_bits {
3516         u8         status[0x8];
3517         u8         reserved_0[0x18];
3518
3519         u8         syndrome[0x20];
3520
3521         u8         reserved_1[0x40];
3522 };
3523
3524 enum {
3525         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3526         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3527 };
3528
3529 struct mlx5_ifc_set_mad_demux_in_bits {
3530         u8         opcode[0x10];
3531         u8         reserved_0[0x10];
3532
3533         u8         reserved_1[0x10];
3534         u8         op_mod[0x10];
3535
3536         u8         reserved_2[0x20];
3537
3538         u8         reserved_3[0x6];
3539         u8         demux_mode[0x2];
3540         u8         reserved_4[0x18];
3541 };
3542
3543 struct mlx5_ifc_set_l2_table_entry_out_bits {
3544         u8         status[0x8];
3545         u8         reserved_0[0x18];
3546
3547         u8         syndrome[0x20];
3548
3549         u8         reserved_1[0x40];
3550 };
3551
3552 struct mlx5_ifc_set_l2_table_entry_in_bits {
3553         u8         opcode[0x10];
3554         u8         reserved_0[0x10];
3555
3556         u8         reserved_1[0x10];
3557         u8         op_mod[0x10];
3558
3559         u8         reserved_2[0x60];
3560
3561         u8         reserved_3[0x8];
3562         u8         table_index[0x18];
3563
3564         u8         reserved_4[0x20];
3565
3566         u8         reserved_5[0x13];
3567         u8         vlan_valid[0x1];
3568         u8         vlan[0xc];
3569
3570         struct mlx5_ifc_mac_address_layout_bits mac_address;
3571
3572         u8         reserved_6[0xc0];
3573 };
3574
3575 struct mlx5_ifc_set_issi_out_bits {
3576         u8         status[0x8];
3577         u8         reserved_0[0x18];
3578
3579         u8         syndrome[0x20];
3580
3581         u8         reserved_1[0x40];
3582 };
3583
3584 struct mlx5_ifc_set_issi_in_bits {
3585         u8         opcode[0x10];
3586         u8         reserved_0[0x10];
3587
3588         u8         reserved_1[0x10];
3589         u8         op_mod[0x10];
3590
3591         u8         reserved_2[0x10];
3592         u8         current_issi[0x10];
3593
3594         u8         reserved_3[0x20];
3595 };
3596
3597 struct mlx5_ifc_set_hca_cap_out_bits {
3598         u8         status[0x8];
3599         u8         reserved_0[0x18];
3600
3601         u8         syndrome[0x20];
3602
3603         u8         reserved_1[0x40];
3604 };
3605
3606 struct mlx5_ifc_set_hca_cap_in_bits {
3607         u8         opcode[0x10];
3608         u8         reserved_0[0x10];
3609
3610         u8         reserved_1[0x10];
3611         u8         op_mod[0x10];
3612
3613         u8         reserved_2[0x40];
3614
3615         union mlx5_ifc_hca_cap_union_bits capability;
3616 };
3617
3618 enum {
3619         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3620         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3621         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3622         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3623 };
3624
3625 struct mlx5_ifc_set_flow_table_root_out_bits {
3626         u8         status[0x8];
3627         u8         reserved_0[0x18];
3628
3629         u8         syndrome[0x20];
3630
3631         u8         reserved_1[0x40];
3632 };
3633
3634 struct mlx5_ifc_set_flow_table_root_in_bits {
3635         u8         opcode[0x10];
3636         u8         reserved_0[0x10];
3637
3638         u8         reserved_1[0x10];
3639         u8         op_mod[0x10];
3640
3641         u8         other_vport[0x1];
3642         u8         reserved_2[0xf];
3643         u8         vport_number[0x10];
3644
3645         u8         reserved_3[0x20];
3646
3647         u8         table_type[0x8];
3648         u8         reserved_4[0x18];
3649
3650         u8         reserved_5[0x8];
3651         u8         table_id[0x18];
3652
3653         u8         reserved_6[0x8];
3654         u8         underlay_qpn[0x18];
3655
3656         u8         reserved_7[0x120];
3657 };
3658
3659 struct mlx5_ifc_set_fte_out_bits {
3660         u8         status[0x8];
3661         u8         reserved_0[0x18];
3662
3663         u8         syndrome[0x20];
3664
3665         u8         reserved_1[0x40];
3666 };
3667
3668 struct mlx5_ifc_set_fte_in_bits {
3669         u8         opcode[0x10];
3670         u8         reserved_0[0x10];
3671
3672         u8         reserved_1[0x10];
3673         u8         op_mod[0x10];
3674
3675         u8         other_vport[0x1];
3676         u8         reserved_2[0xf];
3677         u8         vport_number[0x10];
3678
3679         u8         reserved_3[0x20];
3680
3681         u8         table_type[0x8];
3682         u8         reserved_4[0x18];
3683
3684         u8         reserved_5[0x8];
3685         u8         table_id[0x18];
3686
3687         u8         reserved_6[0x18];
3688         u8         modify_enable_mask[0x8];
3689
3690         u8         reserved_7[0x20];
3691
3692         u8         flow_index[0x20];
3693
3694         u8         reserved_8[0xe0];
3695
3696         struct mlx5_ifc_flow_context_bits flow_context;
3697 };
3698
3699 struct mlx5_ifc_set_driver_version_out_bits {
3700         u8         status[0x8];
3701         u8         reserved_0[0x18];
3702
3703         u8         syndrome[0x20];
3704
3705         u8         reserved_1[0x40];
3706 };
3707
3708 struct mlx5_ifc_set_driver_version_in_bits {
3709         u8         opcode[0x10];
3710         u8         reserved_0[0x10];
3711
3712         u8         reserved_1[0x10];
3713         u8         op_mod[0x10];
3714
3715         u8         reserved_2[0x40];
3716
3717         u8         driver_version[64][0x8];
3718 };
3719
3720 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_0[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         reserved_1[0x40];
3727 };
3728
3729 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3730         u8         opcode[0x10];
3731         u8         reserved_0[0x10];
3732
3733         u8         reserved_1[0x10];
3734         u8         op_mod[0x10];
3735
3736         u8         enable[0x1];
3737         u8         reserved_2[0x1f];
3738
3739         u8         reserved_3[0x160];
3740
3741         struct mlx5_ifc_cmd_pas_bits pas;
3742 };
3743
3744 struct mlx5_ifc_set_burst_size_out_bits {
3745         u8         status[0x8];
3746         u8         reserved_0[0x18];
3747
3748         u8         syndrome[0x20];
3749
3750         u8         reserved_1[0x40];
3751 };
3752
3753 struct mlx5_ifc_set_burst_size_in_bits {
3754         u8         opcode[0x10];
3755         u8         reserved_0[0x10];
3756
3757         u8         reserved_1[0x10];
3758         u8         op_mod[0x10];
3759
3760         u8         reserved_2[0x20];
3761
3762         u8         reserved_3[0x9];
3763         u8         device_burst_size[0x17];
3764 };
3765
3766 struct mlx5_ifc_rts2rts_qp_out_bits {
3767         u8         status[0x8];
3768         u8         reserved_0[0x18];
3769
3770         u8         syndrome[0x20];
3771
3772         u8         reserved_1[0x40];
3773 };
3774
3775 struct mlx5_ifc_rts2rts_qp_in_bits {
3776         u8         opcode[0x10];
3777         u8         reserved_0[0x10];
3778
3779         u8         reserved_1[0x10];
3780         u8         op_mod[0x10];
3781
3782         u8         reserved_2[0x8];
3783         u8         qpn[0x18];
3784
3785         u8         reserved_3[0x20];
3786
3787         u8         opt_param_mask[0x20];
3788
3789         u8         reserved_4[0x20];
3790
3791         struct mlx5_ifc_qpc_bits qpc;
3792
3793         u8         reserved_5[0x80];
3794 };
3795
3796 struct mlx5_ifc_rtr2rts_qp_out_bits {
3797         u8         status[0x8];
3798         u8         reserved_0[0x18];
3799
3800         u8         syndrome[0x20];
3801
3802         u8         reserved_1[0x40];
3803 };
3804
3805 struct mlx5_ifc_rtr2rts_qp_in_bits {
3806         u8         opcode[0x10];
3807         u8         reserved_0[0x10];
3808
3809         u8         reserved_1[0x10];
3810         u8         op_mod[0x10];
3811
3812         u8         reserved_2[0x8];
3813         u8         qpn[0x18];
3814
3815         u8         reserved_3[0x20];
3816
3817         u8         opt_param_mask[0x20];
3818
3819         u8         reserved_4[0x20];
3820
3821         struct mlx5_ifc_qpc_bits qpc;
3822
3823         u8         reserved_5[0x80];
3824 };
3825
3826 struct mlx5_ifc_rst2init_qp_out_bits {
3827         u8         status[0x8];
3828         u8         reserved_0[0x18];
3829
3830         u8         syndrome[0x20];
3831
3832         u8         reserved_1[0x40];
3833 };
3834
3835 struct mlx5_ifc_rst2init_qp_in_bits {
3836         u8         opcode[0x10];
3837         u8         reserved_0[0x10];
3838
3839         u8         reserved_1[0x10];
3840         u8         op_mod[0x10];
3841
3842         u8         reserved_2[0x8];
3843         u8         qpn[0x18];
3844
3845         u8         reserved_3[0x20];
3846
3847         u8         opt_param_mask[0x20];
3848
3849         u8         reserved_4[0x20];
3850
3851         struct mlx5_ifc_qpc_bits qpc;
3852
3853         u8         reserved_5[0x80];
3854 };
3855
3856 struct mlx5_ifc_resume_qp_out_bits {
3857         u8         status[0x8];
3858         u8         reserved_0[0x18];
3859
3860         u8         syndrome[0x20];
3861
3862         u8         reserved_1[0x40];
3863 };
3864
3865 struct mlx5_ifc_resume_qp_in_bits {
3866         u8         opcode[0x10];
3867         u8         reserved_0[0x10];
3868
3869         u8         reserved_1[0x10];
3870         u8         op_mod[0x10];
3871
3872         u8         reserved_2[0x8];
3873         u8         qpn[0x18];
3874
3875         u8         reserved_3[0x20];
3876 };
3877
3878 struct mlx5_ifc_query_xrc_srq_out_bits {
3879         u8         status[0x8];
3880         u8         reserved_0[0x18];
3881
3882         u8         syndrome[0x20];
3883
3884         u8         reserved_1[0x40];
3885
3886         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3887
3888         u8         reserved_2[0x600];
3889
3890         u8         pas[0][0x40];
3891 };
3892
3893 struct mlx5_ifc_query_xrc_srq_in_bits {
3894         u8         opcode[0x10];
3895         u8         reserved_0[0x10];
3896
3897         u8         reserved_1[0x10];
3898         u8         op_mod[0x10];
3899
3900         u8         reserved_2[0x8];
3901         u8         xrc_srqn[0x18];
3902
3903         u8         reserved_3[0x20];
3904 };
3905
3906 struct mlx5_ifc_query_wol_rol_out_bits {
3907         u8         status[0x8];
3908         u8         reserved_0[0x18];
3909
3910         u8         syndrome[0x20];
3911
3912         u8         reserved_1[0x10];
3913         u8         rol_mode[0x8];
3914         u8         wol_mode[0x8];
3915
3916         u8         reserved_2[0x20];
3917 };
3918
3919 struct mlx5_ifc_query_wol_rol_in_bits {
3920         u8         opcode[0x10];
3921         u8         reserved_0[0x10];
3922
3923         u8         reserved_1[0x10];
3924         u8         op_mod[0x10];
3925
3926         u8         reserved_2[0x40];
3927 };
3928
3929 enum {
3930         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3931         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3932 };
3933
3934 struct mlx5_ifc_query_vport_state_out_bits {
3935         u8         status[0x8];
3936         u8         reserved_0[0x18];
3937
3938         u8         syndrome[0x20];
3939
3940         u8         reserved_1[0x20];
3941
3942         u8         reserved_2[0x18];
3943         u8         admin_state[0x4];
3944         u8         state[0x4];
3945 };
3946
3947 enum {
3948         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3949         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3950         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3951 };
3952
3953 struct mlx5_ifc_query_vport_state_in_bits {
3954         u8         opcode[0x10];
3955         u8         reserved_0[0x10];
3956
3957         u8         reserved_1[0x10];
3958         u8         op_mod[0x10];
3959
3960         u8         other_vport[0x1];
3961         u8         reserved_2[0xf];
3962         u8         vport_number[0x10];
3963
3964         u8         reserved_3[0x20];
3965 };
3966
3967 struct mlx5_ifc_query_vport_counter_out_bits {
3968         u8         status[0x8];
3969         u8         reserved_0[0x18];
3970
3971         u8         syndrome[0x20];
3972
3973         u8         reserved_1[0x40];
3974
3975         struct mlx5_ifc_traffic_counter_bits received_errors;
3976
3977         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3978
3979         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3980
3981         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3982
3983         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3984
3985         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3986
3987         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3988
3989         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3990
3991         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3992
3993         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3994
3995         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3996
3997         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3998
3999         u8         reserved_2[0xa00];
4000 };
4001
4002 enum {
4003         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4004 };
4005
4006 struct mlx5_ifc_query_vport_counter_in_bits {
4007         u8         opcode[0x10];
4008         u8         reserved_0[0x10];
4009
4010         u8         reserved_1[0x10];
4011         u8         op_mod[0x10];
4012
4013         u8         other_vport[0x1];
4014         u8         reserved_2[0xb];
4015         u8         port_num[0x4];
4016         u8         vport_number[0x10];
4017
4018         u8         reserved_3[0x60];
4019
4020         u8         clear[0x1];
4021         u8         reserved_4[0x1f];
4022
4023         u8         reserved_5[0x20];
4024 };
4025
4026 struct mlx5_ifc_query_tis_out_bits {
4027         u8         status[0x8];
4028         u8         reserved_0[0x18];
4029
4030         u8         syndrome[0x20];
4031
4032         u8         reserved_1[0x40];
4033
4034         struct mlx5_ifc_tisc_bits tis_context;
4035 };
4036
4037 struct mlx5_ifc_query_tis_in_bits {
4038         u8         opcode[0x10];
4039         u8         reserved_0[0x10];
4040
4041         u8         reserved_1[0x10];
4042         u8         op_mod[0x10];
4043
4044         u8         reserved_2[0x8];
4045         u8         tisn[0x18];
4046
4047         u8         reserved_3[0x20];
4048 };
4049
4050 struct mlx5_ifc_query_tir_out_bits {
4051         u8         status[0x8];
4052         u8         reserved_0[0x18];
4053
4054         u8         syndrome[0x20];
4055
4056         u8         reserved_1[0xc0];
4057
4058         struct mlx5_ifc_tirc_bits tir_context;
4059 };
4060
4061 struct mlx5_ifc_query_tir_in_bits {
4062         u8         opcode[0x10];
4063         u8         reserved_0[0x10];
4064
4065         u8         reserved_1[0x10];
4066         u8         op_mod[0x10];
4067
4068         u8         reserved_2[0x8];
4069         u8         tirn[0x18];
4070
4071         u8         reserved_3[0x20];
4072 };
4073
4074 struct mlx5_ifc_query_srq_out_bits {
4075         u8         status[0x8];
4076         u8         reserved_0[0x18];
4077
4078         u8         syndrome[0x20];
4079
4080         u8         reserved_1[0x40];
4081
4082         struct mlx5_ifc_srqc_bits srq_context_entry;
4083
4084         u8         reserved_2[0x600];
4085
4086         u8         pas[0][0x40];
4087 };
4088
4089 struct mlx5_ifc_query_srq_in_bits {
4090         u8         opcode[0x10];
4091         u8         reserved_0[0x10];
4092
4093         u8         reserved_1[0x10];
4094         u8         op_mod[0x10];
4095
4096         u8         reserved_2[0x8];
4097         u8         srqn[0x18];
4098
4099         u8         reserved_3[0x20];
4100 };
4101
4102 struct mlx5_ifc_query_sq_out_bits {
4103         u8         status[0x8];
4104         u8         reserved_0[0x18];
4105
4106         u8         syndrome[0x20];
4107
4108         u8         reserved_1[0xc0];
4109
4110         struct mlx5_ifc_sqc_bits sq_context;
4111 };
4112
4113 struct mlx5_ifc_query_sq_in_bits {
4114         u8         opcode[0x10];
4115         u8         reserved_0[0x10];
4116
4117         u8         reserved_1[0x10];
4118         u8         op_mod[0x10];
4119
4120         u8         reserved_2[0x8];
4121         u8         sqn[0x18];
4122
4123         u8         reserved_3[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_special_contexts_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_0[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         dump_fill_mkey[0x20];
4133
4134         u8         resd_lkey[0x20];
4135 };
4136
4137 struct mlx5_ifc_query_special_contexts_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_0[0x10];
4140
4141         u8         reserved_1[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         reserved_2[0x40];
4145 };
4146
4147 struct mlx5_ifc_query_scheduling_element_out_bits {
4148         u8         status[0x8];
4149         u8         reserved_at_8[0x18];
4150
4151         u8         syndrome[0x20];
4152
4153         u8         reserved_at_40[0xc0];
4154
4155         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4156
4157         u8         reserved_at_300[0x100];
4158 };
4159
4160 enum {
4161         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4162 };
4163
4164 struct mlx5_ifc_query_scheduling_element_in_bits {
4165         u8         opcode[0x10];
4166         u8         reserved_at_10[0x10];
4167
4168         u8         reserved_at_20[0x10];
4169         u8         op_mod[0x10];
4170
4171         u8         scheduling_hierarchy[0x8];
4172         u8         reserved_at_48[0x18];
4173
4174         u8         scheduling_element_id[0x20];
4175
4176         u8         reserved_at_80[0x180];
4177 };
4178
4179 struct mlx5_ifc_query_rqt_out_bits {
4180         u8         status[0x8];
4181         u8         reserved_0[0x18];
4182
4183         u8         syndrome[0x20];
4184
4185         u8         reserved_1[0xc0];
4186
4187         struct mlx5_ifc_rqtc_bits rqt_context;
4188 };
4189
4190 struct mlx5_ifc_query_rqt_in_bits {
4191         u8         opcode[0x10];
4192         u8         reserved_0[0x10];
4193
4194         u8         reserved_1[0x10];
4195         u8         op_mod[0x10];
4196
4197         u8         reserved_2[0x8];
4198         u8         rqtn[0x18];
4199
4200         u8         reserved_3[0x20];
4201 };
4202
4203 struct mlx5_ifc_query_rq_out_bits {
4204         u8         status[0x8];
4205         u8         reserved_0[0x18];
4206
4207         u8         syndrome[0x20];
4208
4209         u8         reserved_1[0xc0];
4210
4211         struct mlx5_ifc_rqc_bits rq_context;
4212 };
4213
4214 struct mlx5_ifc_query_rq_in_bits {
4215         u8         opcode[0x10];
4216         u8         reserved_0[0x10];
4217
4218         u8         reserved_1[0x10];
4219         u8         op_mod[0x10];
4220
4221         u8         reserved_2[0x8];
4222         u8         rqn[0x18];
4223
4224         u8         reserved_3[0x20];
4225 };
4226
4227 struct mlx5_ifc_query_roce_address_out_bits {
4228         u8         status[0x8];
4229         u8         reserved_0[0x18];
4230
4231         u8         syndrome[0x20];
4232
4233         u8         reserved_1[0x40];
4234
4235         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4236 };
4237
4238 struct mlx5_ifc_query_roce_address_in_bits {
4239         u8         opcode[0x10];
4240         u8         reserved_0[0x10];
4241
4242         u8         reserved_1[0x10];
4243         u8         op_mod[0x10];
4244
4245         u8         roce_address_index[0x10];
4246         u8         reserved_2[0x10];
4247
4248         u8         reserved_3[0x20];
4249 };
4250
4251 struct mlx5_ifc_query_rmp_out_bits {
4252         u8         status[0x8];
4253         u8         reserved_0[0x18];
4254
4255         u8         syndrome[0x20];
4256
4257         u8         reserved_1[0xc0];
4258
4259         struct mlx5_ifc_rmpc_bits rmp_context;
4260 };
4261
4262 struct mlx5_ifc_query_rmp_in_bits {
4263         u8         opcode[0x10];
4264         u8         reserved_0[0x10];
4265
4266         u8         reserved_1[0x10];
4267         u8         op_mod[0x10];
4268
4269         u8         reserved_2[0x8];
4270         u8         rmpn[0x18];
4271
4272         u8         reserved_3[0x20];
4273 };
4274
4275 struct mlx5_ifc_query_rdb_out_bits {
4276         u8         status[0x8];
4277         u8         reserved_0[0x18];
4278
4279         u8         syndrome[0x20];
4280
4281         u8         reserved_1[0x20];
4282
4283         u8         reserved_2[0x18];
4284         u8         rdb_list_size[0x8];
4285
4286         struct mlx5_ifc_rdbc_bits rdb_context[0];
4287 };
4288
4289 struct mlx5_ifc_query_rdb_in_bits {
4290         u8         opcode[0x10];
4291         u8         reserved_0[0x10];
4292
4293         u8         reserved_1[0x10];
4294         u8         op_mod[0x10];
4295
4296         u8         reserved_2[0x8];
4297         u8         qpn[0x18];
4298
4299         u8         reserved_3[0x20];
4300 };
4301
4302 struct mlx5_ifc_query_qp_out_bits {
4303         u8         status[0x8];
4304         u8         reserved_0[0x18];
4305
4306         u8         syndrome[0x20];
4307
4308         u8         reserved_1[0x40];
4309
4310         u8         opt_param_mask[0x20];
4311
4312         u8         reserved_2[0x20];
4313
4314         struct mlx5_ifc_qpc_bits qpc;
4315
4316         u8         reserved_3[0x80];
4317
4318         u8         pas[0][0x40];
4319 };
4320
4321 struct mlx5_ifc_query_qp_in_bits {
4322         u8         opcode[0x10];
4323         u8         reserved_0[0x10];
4324
4325         u8         reserved_1[0x10];
4326         u8         op_mod[0x10];
4327
4328         u8         reserved_2[0x8];
4329         u8         qpn[0x18];
4330
4331         u8         reserved_3[0x20];
4332 };
4333
4334 struct mlx5_ifc_query_q_counter_out_bits {
4335         u8         status[0x8];
4336         u8         reserved_0[0x18];
4337
4338         u8         syndrome[0x20];
4339
4340         u8         reserved_1[0x40];
4341
4342         u8         rx_write_requests[0x20];
4343
4344         u8         reserved_2[0x20];
4345
4346         u8         rx_read_requests[0x20];
4347
4348         u8         reserved_3[0x20];
4349
4350         u8         rx_atomic_requests[0x20];
4351
4352         u8         reserved_4[0x20];
4353
4354         u8         rx_dct_connect[0x20];
4355
4356         u8         reserved_5[0x20];
4357
4358         u8         out_of_buffer[0x20];
4359
4360         u8         reserved_7[0x20];
4361
4362         u8         out_of_sequence[0x20];
4363
4364         u8         reserved_8[0x20];
4365
4366         u8         duplicate_request[0x20];
4367
4368         u8         reserved_9[0x20];
4369
4370         u8         rnr_nak_retry_err[0x20];
4371
4372         u8         reserved_10[0x20];
4373
4374         u8         packet_seq_err[0x20];
4375
4376         u8         reserved_11[0x20];
4377
4378         u8         implied_nak_seq_err[0x20];
4379
4380         u8         reserved_12[0x20];
4381
4382         u8         local_ack_timeout_err[0x20];
4383
4384         u8         reserved_13[0x20];
4385
4386         u8         resp_rnr_nak[0x20];
4387
4388         u8         reserved_14[0x20];
4389
4390         u8         req_rnr_retries_exceeded[0x20];
4391
4392         u8         reserved_15[0x460];
4393 };
4394
4395 struct mlx5_ifc_query_q_counter_in_bits {
4396         u8         opcode[0x10];
4397         u8         reserved_0[0x10];
4398
4399         u8         reserved_1[0x10];
4400         u8         op_mod[0x10];
4401
4402         u8         reserved_2[0x80];
4403
4404         u8         clear[0x1];
4405         u8         reserved_3[0x1f];
4406
4407         u8         reserved_4[0x18];
4408         u8         counter_set_id[0x8];
4409 };
4410
4411 struct mlx5_ifc_query_pages_out_bits {
4412         u8         status[0x8];
4413         u8         reserved_0[0x18];
4414
4415         u8         syndrome[0x20];
4416
4417         u8         reserved_1[0x10];
4418         u8         function_id[0x10];
4419
4420         u8         num_pages[0x20];
4421 };
4422
4423 enum {
4424         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4425         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4426         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4427 };
4428
4429 struct mlx5_ifc_query_pages_in_bits {
4430         u8         opcode[0x10];
4431         u8         reserved_0[0x10];
4432
4433         u8         reserved_1[0x10];
4434         u8         op_mod[0x10];
4435
4436         u8         reserved_2[0x10];
4437         u8         function_id[0x10];
4438
4439         u8         reserved_3[0x20];
4440 };
4441
4442 struct mlx5_ifc_query_nic_vport_context_out_bits {
4443         u8         status[0x8];
4444         u8         reserved_0[0x18];
4445
4446         u8         syndrome[0x20];
4447
4448         u8         reserved_1[0x40];
4449
4450         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4451 };
4452
4453 struct mlx5_ifc_query_nic_vport_context_in_bits {
4454         u8         opcode[0x10];
4455         u8         reserved_0[0x10];
4456
4457         u8         reserved_1[0x10];
4458         u8         op_mod[0x10];
4459
4460         u8         other_vport[0x1];
4461         u8         reserved_2[0xf];
4462         u8         vport_number[0x10];
4463
4464         u8         reserved_3[0x5];
4465         u8         allowed_list_type[0x3];
4466         u8         reserved_4[0x18];
4467 };
4468
4469 struct mlx5_ifc_query_mkey_out_bits {
4470         u8         status[0x8];
4471         u8         reserved_0[0x18];
4472
4473         u8         syndrome[0x20];
4474
4475         u8         reserved_1[0x40];
4476
4477         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4478
4479         u8         reserved_2[0x600];
4480
4481         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4482
4483         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4484 };
4485
4486 struct mlx5_ifc_query_mkey_in_bits {
4487         u8         opcode[0x10];
4488         u8         reserved_0[0x10];
4489
4490         u8         reserved_1[0x10];
4491         u8         op_mod[0x10];
4492
4493         u8         reserved_2[0x8];
4494         u8         mkey_index[0x18];
4495
4496         u8         pg_access[0x1];
4497         u8         reserved_3[0x1f];
4498 };
4499
4500 struct mlx5_ifc_query_mad_demux_out_bits {
4501         u8         status[0x8];
4502         u8         reserved_0[0x18];
4503
4504         u8         syndrome[0x20];
4505
4506         u8         reserved_1[0x40];
4507
4508         u8         mad_dumux_parameters_block[0x20];
4509 };
4510
4511 struct mlx5_ifc_query_mad_demux_in_bits {
4512         u8         opcode[0x10];
4513         u8         reserved_0[0x10];
4514
4515         u8         reserved_1[0x10];
4516         u8         op_mod[0x10];
4517
4518         u8         reserved_2[0x40];
4519 };
4520
4521 struct mlx5_ifc_query_l2_table_entry_out_bits {
4522         u8         status[0x8];
4523         u8         reserved_0[0x18];
4524
4525         u8         syndrome[0x20];
4526
4527         u8         reserved_1[0xa0];
4528
4529         u8         reserved_2[0x13];
4530         u8         vlan_valid[0x1];
4531         u8         vlan[0xc];
4532
4533         struct mlx5_ifc_mac_address_layout_bits mac_address;
4534
4535         u8         reserved_3[0xc0];
4536 };
4537
4538 struct mlx5_ifc_query_l2_table_entry_in_bits {
4539         u8         opcode[0x10];
4540         u8         reserved_0[0x10];
4541
4542         u8         reserved_1[0x10];
4543         u8         op_mod[0x10];
4544
4545         u8         reserved_2[0x60];
4546
4547         u8         reserved_3[0x8];
4548         u8         table_index[0x18];
4549
4550         u8         reserved_4[0x140];
4551 };
4552
4553 struct mlx5_ifc_query_issi_out_bits {
4554         u8         status[0x8];
4555         u8         reserved_0[0x18];
4556
4557         u8         syndrome[0x20];
4558
4559         u8         reserved_1[0x10];
4560         u8         current_issi[0x10];
4561
4562         u8         reserved_2[0xa0];
4563
4564         u8         supported_issi_reserved[76][0x8];
4565         u8         supported_issi_dw0[0x20];
4566 };
4567
4568 struct mlx5_ifc_query_issi_in_bits {
4569         u8         opcode[0x10];
4570         u8         reserved_0[0x10];
4571
4572         u8         reserved_1[0x10];
4573         u8         op_mod[0x10];
4574
4575         u8         reserved_2[0x40];
4576 };
4577
4578 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4579         u8         status[0x8];
4580         u8         reserved_0[0x18];
4581
4582         u8         syndrome[0x20];
4583
4584         u8         reserved_1[0x40];
4585
4586         struct mlx5_ifc_pkey_bits pkey[0];
4587 };
4588
4589 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4590         u8         opcode[0x10];
4591         u8         reserved_0[0x10];
4592
4593         u8         reserved_1[0x10];
4594         u8         op_mod[0x10];
4595
4596         u8         other_vport[0x1];
4597         u8         reserved_2[0xb];
4598         u8         port_num[0x4];
4599         u8         vport_number[0x10];
4600
4601         u8         reserved_3[0x10];
4602         u8         pkey_index[0x10];
4603 };
4604
4605 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4606         u8         status[0x8];
4607         u8         reserved_0[0x18];
4608
4609         u8         syndrome[0x20];
4610
4611         u8         reserved_1[0x20];
4612
4613         u8         gids_num[0x10];
4614         u8         reserved_2[0x10];
4615
4616         struct mlx5_ifc_array128_auto_bits gid[0];
4617 };
4618
4619 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_0[0x10];
4622
4623         u8         reserved_1[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         other_vport[0x1];
4627         u8         reserved_2[0xb];
4628         u8         port_num[0x4];
4629         u8         vport_number[0x10];
4630
4631         u8         reserved_3[0x10];
4632         u8         gid_index[0x10];
4633 };
4634
4635 struct mlx5_ifc_query_hca_vport_context_out_bits {
4636         u8         status[0x8];
4637         u8         reserved_0[0x18];
4638
4639         u8         syndrome[0x20];
4640
4641         u8         reserved_1[0x40];
4642
4643         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4644 };
4645
4646 struct mlx5_ifc_query_hca_vport_context_in_bits {
4647         u8         opcode[0x10];
4648         u8         reserved_0[0x10];
4649
4650         u8         reserved_1[0x10];
4651         u8         op_mod[0x10];
4652
4653         u8         other_vport[0x1];
4654         u8         reserved_2[0xb];
4655         u8         port_num[0x4];
4656         u8         vport_number[0x10];
4657
4658         u8         reserved_3[0x20];
4659 };
4660
4661 struct mlx5_ifc_query_hca_cap_out_bits {
4662         u8         status[0x8];
4663         u8         reserved_0[0x18];
4664
4665         u8         syndrome[0x20];
4666
4667         u8         reserved_1[0x40];
4668
4669         union mlx5_ifc_hca_cap_union_bits capability;
4670 };
4671
4672 struct mlx5_ifc_query_hca_cap_in_bits {
4673         u8         opcode[0x10];
4674         u8         reserved_0[0x10];
4675
4676         u8         reserved_1[0x10];
4677         u8         op_mod[0x10];
4678
4679         u8         reserved_2[0x40];
4680 };
4681
4682 struct mlx5_ifc_query_flow_table_out_bits {
4683         u8         status[0x8];
4684         u8         reserved_at_8[0x18];
4685
4686         u8         syndrome[0x20];
4687
4688         u8         reserved_at_40[0x80];
4689
4690         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4691 };
4692
4693 struct mlx5_ifc_query_flow_table_in_bits {
4694         u8         opcode[0x10];
4695         u8         reserved_0[0x10];
4696
4697         u8         reserved_1[0x10];
4698         u8         op_mod[0x10];
4699
4700         u8         other_vport[0x1];
4701         u8         reserved_2[0xf];
4702         u8         vport_number[0x10];
4703
4704         u8         reserved_3[0x20];
4705
4706         u8         table_type[0x8];
4707         u8         reserved_4[0x18];
4708
4709         u8         reserved_5[0x8];
4710         u8         table_id[0x18];
4711
4712         u8         reserved_6[0x140];
4713 };
4714
4715 struct mlx5_ifc_query_fte_out_bits {
4716         u8         status[0x8];
4717         u8         reserved_0[0x18];
4718
4719         u8         syndrome[0x20];
4720
4721         u8         reserved_1[0x1c0];
4722
4723         struct mlx5_ifc_flow_context_bits flow_context;
4724 };
4725
4726 struct mlx5_ifc_query_fte_in_bits {
4727         u8         opcode[0x10];
4728         u8         reserved_0[0x10];
4729
4730         u8         reserved_1[0x10];
4731         u8         op_mod[0x10];
4732
4733         u8         other_vport[0x1];
4734         u8         reserved_2[0xf];
4735         u8         vport_number[0x10];
4736
4737         u8         reserved_3[0x20];
4738
4739         u8         table_type[0x8];
4740         u8         reserved_4[0x18];
4741
4742         u8         reserved_5[0x8];
4743         u8         table_id[0x18];
4744
4745         u8         reserved_6[0x40];
4746
4747         u8         flow_index[0x20];
4748
4749         u8         reserved_7[0xe0];
4750 };
4751
4752 enum {
4753         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4754         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4755         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4756 };
4757
4758 struct mlx5_ifc_query_flow_group_out_bits {
4759         u8         status[0x8];
4760         u8         reserved_0[0x18];
4761
4762         u8         syndrome[0x20];
4763
4764         u8         reserved_1[0xa0];
4765
4766         u8         start_flow_index[0x20];
4767
4768         u8         reserved_2[0x20];
4769
4770         u8         end_flow_index[0x20];
4771
4772         u8         reserved_3[0xa0];
4773
4774         u8         reserved_4[0x18];
4775         u8         match_criteria_enable[0x8];
4776
4777         struct mlx5_ifc_fte_match_param_bits match_criteria;
4778
4779         u8         reserved_5[0xe00];
4780 };
4781
4782 struct mlx5_ifc_query_flow_group_in_bits {
4783         u8         opcode[0x10];
4784         u8         reserved_0[0x10];
4785
4786         u8         reserved_1[0x10];
4787         u8         op_mod[0x10];
4788
4789         u8         other_vport[0x1];
4790         u8         reserved_2[0xf];
4791         u8         vport_number[0x10];
4792
4793         u8         reserved_3[0x20];
4794
4795         u8         table_type[0x8];
4796         u8         reserved_4[0x18];
4797
4798         u8         reserved_5[0x8];
4799         u8         table_id[0x18];
4800
4801         u8         group_id[0x20];
4802
4803         u8         reserved_6[0x120];
4804 };
4805
4806 struct mlx5_ifc_query_flow_counter_out_bits {
4807         u8         status[0x8];
4808         u8         reserved_at_8[0x18];
4809
4810         u8         syndrome[0x20];
4811
4812         u8         reserved_at_40[0x40];
4813
4814         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4815 };
4816
4817 struct mlx5_ifc_query_flow_counter_in_bits {
4818         u8         opcode[0x10];
4819         u8         reserved_at_10[0x10];
4820
4821         u8         reserved_at_20[0x10];
4822         u8         op_mod[0x10];
4823
4824         u8         reserved_at_40[0x80];
4825
4826         u8         clear[0x1];
4827         u8         reserved_at_c1[0xf];
4828         u8         num_of_counters[0x10];
4829
4830         u8         reserved_at_e0[0x10];
4831         u8         flow_counter_id[0x10];
4832 };
4833
4834 struct mlx5_ifc_query_esw_vport_context_out_bits {
4835         u8         status[0x8];
4836         u8         reserved_0[0x18];
4837
4838         u8         syndrome[0x20];
4839
4840         u8         reserved_1[0x40];
4841
4842         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4843 };
4844
4845 struct mlx5_ifc_query_esw_vport_context_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_0[0x10];
4848
4849         u8         reserved_1[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         other_vport[0x1];
4853         u8         reserved_2[0xf];
4854         u8         vport_number[0x10];
4855
4856         u8         reserved_3[0x20];
4857 };
4858
4859 struct mlx5_ifc_query_eq_out_bits {
4860         u8         status[0x8];
4861         u8         reserved_0[0x18];
4862
4863         u8         syndrome[0x20];
4864
4865         u8         reserved_1[0x40];
4866
4867         struct mlx5_ifc_eqc_bits eq_context_entry;
4868
4869         u8         reserved_2[0x40];
4870
4871         u8         event_bitmask[0x40];
4872
4873         u8         reserved_3[0x580];
4874
4875         u8         pas[0][0x40];
4876 };
4877
4878 struct mlx5_ifc_query_eq_in_bits {
4879         u8         opcode[0x10];
4880         u8         reserved_0[0x10];
4881
4882         u8         reserved_1[0x10];
4883         u8         op_mod[0x10];
4884
4885         u8         reserved_2[0x18];
4886         u8         eq_number[0x8];
4887
4888         u8         reserved_3[0x20];
4889 };
4890
4891 struct mlx5_ifc_query_dct_out_bits {
4892         u8         status[0x8];
4893         u8         reserved_0[0x18];
4894
4895         u8         syndrome[0x20];
4896
4897         u8         reserved_1[0x40];
4898
4899         struct mlx5_ifc_dctc_bits dct_context_entry;
4900
4901         u8         reserved_2[0x180];
4902 };
4903
4904 struct mlx5_ifc_query_dct_in_bits {
4905         u8         opcode[0x10];
4906         u8         reserved_0[0x10];
4907
4908         u8         reserved_1[0x10];
4909         u8         op_mod[0x10];
4910
4911         u8         reserved_2[0x8];
4912         u8         dctn[0x18];
4913
4914         u8         reserved_3[0x20];
4915 };
4916
4917 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4918         u8         status[0x8];
4919         u8         reserved_0[0x18];
4920
4921         u8         syndrome[0x20];
4922
4923         u8         enable[0x1];
4924         u8         reserved_1[0x1f];
4925
4926         u8         reserved_2[0x160];
4927
4928         struct mlx5_ifc_cmd_pas_bits pas;
4929 };
4930
4931 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4932         u8         opcode[0x10];
4933         u8         reserved_0[0x10];
4934
4935         u8         reserved_1[0x10];
4936         u8         op_mod[0x10];
4937
4938         u8         reserved_2[0x40];
4939 };
4940
4941 struct mlx5_ifc_query_cq_out_bits {
4942         u8         status[0x8];
4943         u8         reserved_0[0x18];
4944
4945         u8         syndrome[0x20];
4946
4947         u8         reserved_1[0x40];
4948
4949         struct mlx5_ifc_cqc_bits cq_context;
4950
4951         u8         reserved_2[0x600];
4952
4953         u8         pas[0][0x40];
4954 };
4955
4956 struct mlx5_ifc_query_cq_in_bits {
4957         u8         opcode[0x10];
4958         u8         reserved_0[0x10];
4959
4960         u8         reserved_1[0x10];
4961         u8         op_mod[0x10];
4962
4963         u8         reserved_2[0x8];
4964         u8         cqn[0x18];
4965
4966         u8         reserved_3[0x20];
4967 };
4968
4969 struct mlx5_ifc_query_cong_status_out_bits {
4970         u8         status[0x8];
4971         u8         reserved_0[0x18];
4972
4973         u8         syndrome[0x20];
4974
4975         u8         reserved_1[0x20];
4976
4977         u8         enable[0x1];
4978         u8         tag_enable[0x1];
4979         u8         reserved_2[0x1e];
4980 };
4981
4982 struct mlx5_ifc_query_cong_status_in_bits {
4983         u8         opcode[0x10];
4984         u8         reserved_0[0x10];
4985
4986         u8         reserved_1[0x10];
4987         u8         op_mod[0x10];
4988
4989         u8         reserved_2[0x18];
4990         u8         priority[0x4];
4991         u8         cong_protocol[0x4];
4992
4993         u8         reserved_3[0x20];
4994 };
4995
4996 struct mlx5_ifc_query_cong_statistics_out_bits {
4997         u8         status[0x8];
4998         u8         reserved_0[0x18];
4999
5000         u8         syndrome[0x20];
5001
5002         u8         reserved_1[0x40];
5003
5004         u8         rp_cur_flows[0x20];
5005
5006         u8         sum_flows[0x20];
5007
5008         u8         rp_cnp_ignored_high[0x20];
5009
5010         u8         rp_cnp_ignored_low[0x20];
5011
5012         u8         rp_cnp_handled_high[0x20];
5013
5014         u8         rp_cnp_handled_low[0x20];
5015
5016         u8         reserved_2[0x100];
5017
5018         u8         time_stamp_high[0x20];
5019
5020         u8         time_stamp_low[0x20];
5021
5022         u8         accumulators_period[0x20];
5023
5024         u8         np_ecn_marked_roce_packets_high[0x20];
5025
5026         u8         np_ecn_marked_roce_packets_low[0x20];
5027
5028         u8         np_cnp_sent_high[0x20];
5029
5030         u8         np_cnp_sent_low[0x20];
5031
5032         u8         reserved_3[0x560];
5033 };
5034
5035 struct mlx5_ifc_query_cong_statistics_in_bits {
5036         u8         opcode[0x10];
5037         u8         reserved_0[0x10];
5038
5039         u8         reserved_1[0x10];
5040         u8         op_mod[0x10];
5041
5042         u8         clear[0x1];
5043         u8         reserved_2[0x1f];
5044
5045         u8         reserved_3[0x20];
5046 };
5047
5048 struct mlx5_ifc_query_cong_params_out_bits {
5049         u8         status[0x8];
5050         u8         reserved_0[0x18];
5051
5052         u8         syndrome[0x20];
5053
5054         u8         reserved_1[0x40];
5055
5056         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5057 };
5058
5059 struct mlx5_ifc_query_cong_params_in_bits {
5060         u8         opcode[0x10];
5061         u8         reserved_0[0x10];
5062
5063         u8         reserved_1[0x10];
5064         u8         op_mod[0x10];
5065
5066         u8         reserved_2[0x1c];
5067         u8         cong_protocol[0x4];
5068
5069         u8         reserved_3[0x20];
5070 };
5071
5072 struct mlx5_ifc_query_burst_size_out_bits {
5073         u8         status[0x8];
5074         u8         reserved_0[0x18];
5075
5076         u8         syndrome[0x20];
5077
5078         u8         reserved_1[0x20];
5079
5080         u8         reserved_2[0x9];
5081         u8         device_burst_size[0x17];
5082 };
5083
5084 struct mlx5_ifc_query_burst_size_in_bits {
5085         u8         opcode[0x10];
5086         u8         reserved_0[0x10];
5087
5088         u8         reserved_1[0x10];
5089         u8         op_mod[0x10];
5090
5091         u8         reserved_2[0x40];
5092 };
5093
5094 struct mlx5_ifc_query_adapter_out_bits {
5095         u8         status[0x8];
5096         u8         reserved_0[0x18];
5097
5098         u8         syndrome[0x20];
5099
5100         u8         reserved_1[0x40];
5101
5102         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5103 };
5104
5105 struct mlx5_ifc_query_adapter_in_bits {
5106         u8         opcode[0x10];
5107         u8         reserved_0[0x10];
5108
5109         u8         reserved_1[0x10];
5110         u8         op_mod[0x10];
5111
5112         u8         reserved_2[0x40];
5113 };
5114
5115 struct mlx5_ifc_qp_2rst_out_bits {
5116         u8         status[0x8];
5117         u8         reserved_0[0x18];
5118
5119         u8         syndrome[0x20];
5120
5121         u8         reserved_1[0x40];
5122 };
5123
5124 struct mlx5_ifc_qp_2rst_in_bits {
5125         u8         opcode[0x10];
5126         u8         reserved_0[0x10];
5127
5128         u8         reserved_1[0x10];
5129         u8         op_mod[0x10];
5130
5131         u8         reserved_2[0x8];
5132         u8         qpn[0x18];
5133
5134         u8         reserved_3[0x20];
5135 };
5136
5137 struct mlx5_ifc_qp_2err_out_bits {
5138         u8         status[0x8];
5139         u8         reserved_0[0x18];
5140
5141         u8         syndrome[0x20];
5142
5143         u8         reserved_1[0x40];
5144 };
5145
5146 struct mlx5_ifc_qp_2err_in_bits {
5147         u8         opcode[0x10];
5148         u8         reserved_0[0x10];
5149
5150         u8         reserved_1[0x10];
5151         u8         op_mod[0x10];
5152
5153         u8         reserved_2[0x8];
5154         u8         qpn[0x18];
5155
5156         u8         reserved_3[0x20];
5157 };
5158
5159 struct mlx5_ifc_para_vport_element_bits {
5160         u8         reserved_at_0[0xc];
5161         u8         traffic_class[0x4];
5162         u8         qos_para_vport_number[0x10];
5163 };
5164
5165 struct mlx5_ifc_page_fault_resume_out_bits {
5166         u8         status[0x8];
5167         u8         reserved_0[0x18];
5168
5169         u8         syndrome[0x20];
5170
5171         u8         reserved_1[0x40];
5172 };
5173
5174 struct mlx5_ifc_page_fault_resume_in_bits {
5175         u8         opcode[0x10];
5176         u8         reserved_0[0x10];
5177
5178         u8         reserved_1[0x10];
5179         u8         op_mod[0x10];
5180
5181         u8         error[0x1];
5182         u8         reserved_2[0x4];
5183         u8         rdma[0x1];
5184         u8         read_write[0x1];
5185         u8         req_res[0x1];
5186         u8         qpn[0x18];
5187
5188         u8         reserved_3[0x20];
5189 };
5190
5191 struct mlx5_ifc_nop_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_0[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_1[0x40];
5198 };
5199
5200 struct mlx5_ifc_nop_in_bits {
5201         u8         opcode[0x10];
5202         u8         reserved_0[0x10];
5203
5204         u8         reserved_1[0x10];
5205         u8         op_mod[0x10];
5206
5207         u8         reserved_2[0x40];
5208 };
5209
5210 struct mlx5_ifc_modify_vport_state_out_bits {
5211         u8         status[0x8];
5212         u8         reserved_0[0x18];
5213
5214         u8         syndrome[0x20];
5215
5216         u8         reserved_1[0x40];
5217 };
5218
5219 enum {
5220         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5221         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5222         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5223 };
5224
5225 enum {
5226         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5227         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5228         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5229 };
5230
5231 struct mlx5_ifc_modify_vport_state_in_bits {
5232         u8         opcode[0x10];
5233         u8         reserved_0[0x10];
5234
5235         u8         reserved_1[0x10];
5236         u8         op_mod[0x10];
5237
5238         u8         other_vport[0x1];
5239         u8         reserved_2[0xf];
5240         u8         vport_number[0x10];
5241
5242         u8         reserved_3[0x18];
5243         u8         admin_state[0x4];
5244         u8         reserved_4[0x4];
5245 };
5246
5247 struct mlx5_ifc_modify_tis_out_bits {
5248         u8         status[0x8];
5249         u8         reserved_0[0x18];
5250
5251         u8         syndrome[0x20];
5252
5253         u8         reserved_1[0x40];
5254 };
5255
5256 struct mlx5_ifc_modify_tis_bitmask_bits {
5257         u8         reserved_at_0[0x20];
5258
5259         u8         reserved_at_20[0x1d];
5260         u8         lag_tx_port_affinity[0x1];
5261         u8         strict_lag_tx_port_affinity[0x1];
5262         u8         prio[0x1];
5263 };
5264
5265 struct mlx5_ifc_modify_tis_in_bits {
5266         u8         opcode[0x10];
5267         u8         reserved_0[0x10];
5268
5269         u8         reserved_1[0x10];
5270         u8         op_mod[0x10];
5271
5272         u8         reserved_2[0x8];
5273         u8         tisn[0x18];
5274
5275         u8         reserved_3[0x20];
5276
5277         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5278
5279         u8         reserved_4[0x40];
5280
5281         struct mlx5_ifc_tisc_bits ctx;
5282 };
5283
5284 struct mlx5_ifc_modify_tir_out_bits {
5285         u8         status[0x8];
5286         u8         reserved_0[0x18];
5287
5288         u8         syndrome[0x20];
5289
5290         u8         reserved_1[0x40];
5291 };
5292
5293 enum
5294 {
5295         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5296         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5297 };
5298
5299 struct mlx5_ifc_modify_tir_in_bits {
5300         u8         opcode[0x10];
5301         u8         reserved_0[0x10];
5302
5303         u8         reserved_1[0x10];
5304         u8         op_mod[0x10];
5305
5306         u8         reserved_2[0x8];
5307         u8         tirn[0x18];
5308
5309         u8         reserved_3[0x20];
5310
5311         u8         modify_bitmask[0x40];
5312
5313         u8         reserved_4[0x40];
5314
5315         struct mlx5_ifc_tirc_bits tir_context;
5316 };
5317
5318 struct mlx5_ifc_modify_sq_out_bits {
5319         u8         status[0x8];
5320         u8         reserved_0[0x18];
5321
5322         u8         syndrome[0x20];
5323
5324         u8         reserved_1[0x40];
5325 };
5326
5327 struct mlx5_ifc_modify_sq_in_bits {
5328         u8         opcode[0x10];
5329         u8         reserved_0[0x10];
5330
5331         u8         reserved_1[0x10];
5332         u8         op_mod[0x10];
5333
5334         u8         sq_state[0x4];
5335         u8         reserved_2[0x4];
5336         u8         sqn[0x18];
5337
5338         u8         reserved_3[0x20];
5339
5340         u8         modify_bitmask[0x40];
5341
5342         u8         reserved_4[0x40];
5343
5344         struct mlx5_ifc_sqc_bits ctx;
5345 };
5346
5347 struct mlx5_ifc_modify_scheduling_element_out_bits {
5348         u8         status[0x8];
5349         u8         reserved_at_8[0x18];
5350
5351         u8         syndrome[0x20];
5352
5353         u8         reserved_at_40[0x1c0];
5354 };
5355
5356 enum {
5357         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5358 };
5359
5360 enum {
5361         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5362         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5363 };
5364
5365 struct mlx5_ifc_modify_scheduling_element_in_bits {
5366         u8         opcode[0x10];
5367         u8         reserved_at_10[0x10];
5368
5369         u8         reserved_at_20[0x10];
5370         u8         op_mod[0x10];
5371
5372         u8         scheduling_hierarchy[0x8];
5373         u8         reserved_at_48[0x18];
5374
5375         u8         scheduling_element_id[0x20];
5376
5377         u8         reserved_at_80[0x20];
5378
5379         u8         modify_bitmask[0x20];
5380
5381         u8         reserved_at_c0[0x40];
5382
5383         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5384
5385         u8         reserved_at_300[0x100];
5386 };
5387
5388 struct mlx5_ifc_modify_rqt_out_bits {
5389         u8         status[0x8];
5390         u8         reserved_0[0x18];
5391
5392         u8         syndrome[0x20];
5393
5394         u8         reserved_1[0x40];
5395 };
5396
5397 struct mlx5_ifc_modify_rqt_in_bits {
5398         u8         opcode[0x10];
5399         u8         reserved_0[0x10];
5400
5401         u8         reserved_1[0x10];
5402         u8         op_mod[0x10];
5403
5404         u8         reserved_2[0x8];
5405         u8         rqtn[0x18];
5406
5407         u8         reserved_3[0x20];
5408
5409         u8         modify_bitmask[0x40];
5410
5411         u8         reserved_4[0x40];
5412
5413         struct mlx5_ifc_rqtc_bits ctx;
5414 };
5415
5416 struct mlx5_ifc_modify_rq_out_bits {
5417         u8         status[0x8];
5418         u8         reserved_0[0x18];
5419
5420         u8         syndrome[0x20];
5421
5422         u8         reserved_1[0x40];
5423 };
5424
5425 enum {
5426         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5427         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5428 };
5429
5430 struct mlx5_ifc_modify_rq_in_bits {
5431         u8         opcode[0x10];
5432         u8         reserved_0[0x10];
5433
5434         u8         reserved_1[0x10];
5435         u8         op_mod[0x10];
5436
5437         u8         rq_state[0x4];
5438         u8         reserved_2[0x4];
5439         u8         rqn[0x18];
5440
5441         u8         reserved_3[0x20];
5442
5443         u8         modify_bitmask[0x40];
5444
5445         u8         reserved_4[0x40];
5446
5447         struct mlx5_ifc_rqc_bits ctx;
5448 };
5449
5450 struct mlx5_ifc_modify_rmp_out_bits {
5451         u8         status[0x8];
5452         u8         reserved_0[0x18];
5453
5454         u8         syndrome[0x20];
5455
5456         u8         reserved_1[0x40];
5457 };
5458
5459 struct mlx5_ifc_rmp_bitmask_bits {
5460         u8         reserved[0x20];
5461
5462         u8         reserved1[0x1f];
5463         u8         lwm[0x1];
5464 };
5465
5466 struct mlx5_ifc_modify_rmp_in_bits {
5467         u8         opcode[0x10];
5468         u8         reserved_0[0x10];
5469
5470         u8         reserved_1[0x10];
5471         u8         op_mod[0x10];
5472
5473         u8         rmp_state[0x4];
5474         u8         reserved_2[0x4];
5475         u8         rmpn[0x18];
5476
5477         u8         reserved_3[0x20];
5478
5479         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5480
5481         u8         reserved_4[0x40];
5482
5483         struct mlx5_ifc_rmpc_bits ctx;
5484 };
5485
5486 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5487         u8         status[0x8];
5488         u8         reserved_0[0x18];
5489
5490         u8         syndrome[0x20];
5491
5492         u8         reserved_1[0x40];
5493 };
5494
5495 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5496         u8         reserved_0[0x14];
5497         u8         disable_uc_local_lb[0x1];
5498         u8         disable_mc_local_lb[0x1];
5499         u8         node_guid[0x1];
5500         u8         port_guid[0x1];
5501         u8         min_wqe_inline_mode[0x1];
5502         u8         mtu[0x1];
5503         u8         change_event[0x1];
5504         u8         promisc[0x1];
5505         u8         permanent_address[0x1];
5506         u8         addresses_list[0x1];
5507         u8         roce_en[0x1];
5508         u8         reserved_1[0x1];
5509 };
5510
5511 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5512         u8         opcode[0x10];
5513         u8         reserved_0[0x10];
5514
5515         u8         reserved_1[0x10];
5516         u8         op_mod[0x10];
5517
5518         u8         other_vport[0x1];
5519         u8         reserved_2[0xf];
5520         u8         vport_number[0x10];
5521
5522         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5523
5524         u8         reserved_3[0x780];
5525
5526         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5527 };
5528
5529 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5530         u8         status[0x8];
5531         u8         reserved_0[0x18];
5532
5533         u8         syndrome[0x20];
5534
5535         u8         reserved_1[0x40];
5536 };
5537
5538 struct mlx5_ifc_grh_bits {
5539         u8      ip_version[4];
5540         u8      traffic_class[8];
5541         u8      flow_label[20];
5542         u8      payload_length[16];
5543         u8      next_header[8];
5544         u8      hop_limit[8];
5545         u8      sgid[128];
5546         u8      dgid[128];
5547 };
5548
5549 struct mlx5_ifc_bth_bits {
5550         u8      opcode[8];
5551         u8      se[1];
5552         u8      migreq[1];
5553         u8      pad_count[2];
5554         u8      tver[4];
5555         u8      p_key[16];
5556         u8      reserved8[8];
5557         u8      dest_qp[24];
5558         u8      ack_req[1];
5559         u8      reserved7[7];
5560         u8      psn[24];
5561 };
5562
5563 struct mlx5_ifc_aeth_bits {
5564         u8      syndrome[8];
5565         u8      msn[24];
5566 };
5567
5568 struct mlx5_ifc_dceth_bits {
5569         u8      reserved0[8];
5570         u8      session_id[24];
5571         u8      reserved1[8];
5572         u8      dci_dct[24];
5573 };
5574
5575 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5576         u8         opcode[0x10];
5577         u8         reserved_0[0x10];
5578
5579         u8         reserved_1[0x10];
5580         u8         op_mod[0x10];
5581
5582         u8         other_vport[0x1];
5583         u8         reserved_2[0xb];
5584         u8         port_num[0x4];
5585         u8         vport_number[0x10];
5586
5587         u8         reserved_3[0x20];
5588
5589         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5590 };
5591
5592 struct mlx5_ifc_modify_flow_table_out_bits {
5593         u8         status[0x8];
5594         u8         reserved_at_8[0x18];
5595
5596         u8         syndrome[0x20];
5597
5598         u8         reserved_at_40[0x40];
5599 };
5600
5601 enum {
5602         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5603         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5604 };
5605
5606 struct mlx5_ifc_modify_flow_table_in_bits {
5607         u8         opcode[0x10];
5608         u8         reserved_at_10[0x10];
5609
5610         u8         reserved_at_20[0x10];
5611         u8         op_mod[0x10];
5612
5613         u8         other_vport[0x1];
5614         u8         reserved_at_41[0xf];
5615         u8         vport_number[0x10];
5616
5617         u8         reserved_at_60[0x10];
5618         u8         modify_field_select[0x10];
5619
5620         u8         table_type[0x8];
5621         u8         reserved_at_88[0x18];
5622
5623         u8         reserved_at_a0[0x8];
5624         u8         table_id[0x18];
5625
5626         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5627 };
5628
5629 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_0[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_1[0x40];
5636 };
5637
5638 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5639         u8         reserved[0x1c];
5640         u8         vport_cvlan_insert[0x1];
5641         u8         vport_svlan_insert[0x1];
5642         u8         vport_cvlan_strip[0x1];
5643         u8         vport_svlan_strip[0x1];
5644 };
5645
5646 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5647         u8         opcode[0x10];
5648         u8         reserved_0[0x10];
5649
5650         u8         reserved_1[0x10];
5651         u8         op_mod[0x10];
5652
5653         u8         other_vport[0x1];
5654         u8         reserved_2[0xf];
5655         u8         vport_number[0x10];
5656
5657         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5658
5659         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5660 };
5661
5662 struct mlx5_ifc_modify_cq_out_bits {
5663         u8         status[0x8];
5664         u8         reserved_0[0x18];
5665
5666         u8         syndrome[0x20];
5667
5668         u8         reserved_1[0x40];
5669 };
5670
5671 enum {
5672         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5673         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5674 };
5675
5676 struct mlx5_ifc_modify_cq_in_bits {
5677         u8         opcode[0x10];
5678         u8         reserved_0[0x10];
5679
5680         u8         reserved_1[0x10];
5681         u8         op_mod[0x10];
5682
5683         u8         reserved_2[0x8];
5684         u8         cqn[0x18];
5685
5686         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5687
5688         struct mlx5_ifc_cqc_bits cq_context;
5689
5690         u8         reserved_3[0x600];
5691
5692         u8         pas[0][0x40];
5693 };
5694
5695 struct mlx5_ifc_modify_cong_status_out_bits {
5696         u8         status[0x8];
5697         u8         reserved_0[0x18];
5698
5699         u8         syndrome[0x20];
5700
5701         u8         reserved_1[0x40];
5702 };
5703
5704 struct mlx5_ifc_modify_cong_status_in_bits {
5705         u8         opcode[0x10];
5706         u8         reserved_0[0x10];
5707
5708         u8         reserved_1[0x10];
5709         u8         op_mod[0x10];
5710
5711         u8         reserved_2[0x18];
5712         u8         priority[0x4];
5713         u8         cong_protocol[0x4];
5714
5715         u8         enable[0x1];
5716         u8         tag_enable[0x1];
5717         u8         reserved_3[0x1e];
5718 };
5719
5720 struct mlx5_ifc_modify_cong_params_out_bits {
5721         u8         status[0x8];
5722         u8         reserved_0[0x18];
5723
5724         u8         syndrome[0x20];
5725
5726         u8         reserved_1[0x40];
5727 };
5728
5729 struct mlx5_ifc_modify_cong_params_in_bits {
5730         u8         opcode[0x10];
5731         u8         reserved_0[0x10];
5732
5733         u8         reserved_1[0x10];
5734         u8         op_mod[0x10];
5735
5736         u8         reserved_2[0x1c];
5737         u8         cong_protocol[0x4];
5738
5739         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5740
5741         u8         reserved_3[0x80];
5742
5743         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5744 };
5745
5746 struct mlx5_ifc_manage_pages_out_bits {
5747         u8         status[0x8];
5748         u8         reserved_0[0x18];
5749
5750         u8         syndrome[0x20];
5751
5752         u8         output_num_entries[0x20];
5753
5754         u8         reserved_1[0x20];
5755
5756         u8         pas[0][0x40];
5757 };
5758
5759 enum {
5760         MLX5_PAGES_CANT_GIVE                            = 0x0,
5761         MLX5_PAGES_GIVE                                 = 0x1,
5762         MLX5_PAGES_TAKE                                 = 0x2,
5763 };
5764
5765 struct mlx5_ifc_manage_pages_in_bits {
5766         u8         opcode[0x10];
5767         u8         reserved_0[0x10];
5768
5769         u8         reserved_1[0x10];
5770         u8         op_mod[0x10];
5771
5772         u8         reserved_2[0x10];
5773         u8         function_id[0x10];
5774
5775         u8         input_num_entries[0x20];
5776
5777         u8         pas[0][0x40];
5778 };
5779
5780 struct mlx5_ifc_mad_ifc_out_bits {
5781         u8         status[0x8];
5782         u8         reserved_0[0x18];
5783
5784         u8         syndrome[0x20];
5785
5786         u8         reserved_1[0x40];
5787
5788         u8         response_mad_packet[256][0x8];
5789 };
5790
5791 struct mlx5_ifc_mad_ifc_in_bits {
5792         u8         opcode[0x10];
5793         u8         reserved_0[0x10];
5794
5795         u8         reserved_1[0x10];
5796         u8         op_mod[0x10];
5797
5798         u8         remote_lid[0x10];
5799         u8         reserved_2[0x8];
5800         u8         port[0x8];
5801
5802         u8         reserved_3[0x20];
5803
5804         u8         mad[256][0x8];
5805 };
5806
5807 struct mlx5_ifc_init_hca_out_bits {
5808         u8         status[0x8];
5809         u8         reserved_0[0x18];
5810
5811         u8         syndrome[0x20];
5812
5813         u8         reserved_1[0x40];
5814 };
5815
5816 enum {
5817         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5818         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5819 };
5820
5821 struct mlx5_ifc_init_hca_in_bits {
5822         u8         opcode[0x10];
5823         u8         reserved_0[0x10];
5824
5825         u8         reserved_1[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         reserved_2[0x40];
5829 };
5830
5831 struct mlx5_ifc_init2rtr_qp_out_bits {
5832         u8         status[0x8];
5833         u8         reserved_0[0x18];
5834
5835         u8         syndrome[0x20];
5836
5837         u8         reserved_1[0x40];
5838 };
5839
5840 struct mlx5_ifc_init2rtr_qp_in_bits {
5841         u8         opcode[0x10];
5842         u8         reserved_0[0x10];
5843
5844         u8         reserved_1[0x10];
5845         u8         op_mod[0x10];
5846
5847         u8         reserved_2[0x8];
5848         u8         qpn[0x18];
5849
5850         u8         reserved_3[0x20];
5851
5852         u8         opt_param_mask[0x20];
5853
5854         u8         reserved_4[0x20];
5855
5856         struct mlx5_ifc_qpc_bits qpc;
5857
5858         u8         reserved_5[0x80];
5859 };
5860
5861 struct mlx5_ifc_init2init_qp_out_bits {
5862         u8         status[0x8];
5863         u8         reserved_0[0x18];
5864
5865         u8         syndrome[0x20];
5866
5867         u8         reserved_1[0x40];
5868 };
5869
5870 struct mlx5_ifc_init2init_qp_in_bits {
5871         u8         opcode[0x10];
5872         u8         reserved_0[0x10];
5873
5874         u8         reserved_1[0x10];
5875         u8         op_mod[0x10];
5876
5877         u8         reserved_2[0x8];
5878         u8         qpn[0x18];
5879
5880         u8         reserved_3[0x20];
5881
5882         u8         opt_param_mask[0x20];
5883
5884         u8         reserved_4[0x20];
5885
5886         struct mlx5_ifc_qpc_bits qpc;
5887
5888         u8         reserved_5[0x80];
5889 };
5890
5891 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5892         u8         status[0x8];
5893         u8         reserved_0[0x18];
5894
5895         u8         syndrome[0x20];
5896
5897         u8         reserved_1[0x40];
5898
5899         u8         packet_headers_log[128][0x8];
5900
5901         u8         packet_syndrome[64][0x8];
5902 };
5903
5904 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5905         u8         opcode[0x10];
5906         u8         reserved_0[0x10];
5907
5908         u8         reserved_1[0x10];
5909         u8         op_mod[0x10];
5910
5911         u8         reserved_2[0x40];
5912 };
5913
5914 struct mlx5_ifc_gen_eqe_in_bits {
5915         u8         opcode[0x10];
5916         u8         reserved_0[0x10];
5917
5918         u8         reserved_1[0x10];
5919         u8         op_mod[0x10];
5920
5921         u8         reserved_2[0x18];
5922         u8         eq_number[0x8];
5923
5924         u8         reserved_3[0x20];
5925
5926         u8         eqe[64][0x8];
5927 };
5928
5929 struct mlx5_ifc_gen_eq_out_bits {
5930         u8         status[0x8];
5931         u8         reserved_0[0x18];
5932
5933         u8         syndrome[0x20];
5934
5935         u8         reserved_1[0x40];
5936 };
5937
5938 struct mlx5_ifc_enable_hca_out_bits {
5939         u8         status[0x8];
5940         u8         reserved_0[0x18];
5941
5942         u8         syndrome[0x20];
5943
5944         u8         reserved_1[0x20];
5945 };
5946
5947 struct mlx5_ifc_enable_hca_in_bits {
5948         u8         opcode[0x10];
5949         u8         reserved_0[0x10];
5950
5951         u8         reserved_1[0x10];
5952         u8         op_mod[0x10];
5953
5954         u8         reserved_2[0x10];
5955         u8         function_id[0x10];
5956
5957         u8         reserved_3[0x20];
5958 };
5959
5960 struct mlx5_ifc_drain_dct_out_bits {
5961         u8         status[0x8];
5962         u8         reserved_0[0x18];
5963
5964         u8         syndrome[0x20];
5965
5966         u8         reserved_1[0x40];
5967 };
5968
5969 struct mlx5_ifc_drain_dct_in_bits {
5970         u8         opcode[0x10];
5971         u8         reserved_0[0x10];
5972
5973         u8         reserved_1[0x10];
5974         u8         op_mod[0x10];
5975
5976         u8         reserved_2[0x8];
5977         u8         dctn[0x18];
5978
5979         u8         reserved_3[0x20];
5980 };
5981
5982 struct mlx5_ifc_disable_hca_out_bits {
5983         u8         status[0x8];
5984         u8         reserved_0[0x18];
5985
5986         u8         syndrome[0x20];
5987
5988         u8         reserved_1[0x20];
5989 };
5990
5991 struct mlx5_ifc_disable_hca_in_bits {
5992         u8         opcode[0x10];
5993         u8         reserved_0[0x10];
5994
5995         u8         reserved_1[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         reserved_2[0x10];
5999         u8         function_id[0x10];
6000
6001         u8         reserved_3[0x20];
6002 };
6003
6004 struct mlx5_ifc_detach_from_mcg_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_0[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_1[0x40];
6011 };
6012
6013 struct mlx5_ifc_detach_from_mcg_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_0[0x10];
6016
6017         u8         reserved_1[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_2[0x8];
6021         u8         qpn[0x18];
6022
6023         u8         reserved_3[0x20];
6024
6025         u8         multicast_gid[16][0x8];
6026 };
6027
6028 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_0[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_1[0x40];
6035 };
6036
6037 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6038         u8         opcode[0x10];
6039         u8         reserved_0[0x10];
6040
6041         u8         reserved_1[0x10];
6042         u8         op_mod[0x10];
6043
6044         u8         reserved_2[0x8];
6045         u8         xrc_srqn[0x18];
6046
6047         u8         reserved_3[0x20];
6048 };
6049
6050 struct mlx5_ifc_destroy_tis_out_bits {
6051         u8         status[0x8];
6052         u8         reserved_0[0x18];
6053
6054         u8         syndrome[0x20];
6055
6056         u8         reserved_1[0x40];
6057 };
6058
6059 struct mlx5_ifc_destroy_tis_in_bits {
6060         u8         opcode[0x10];
6061         u8         reserved_0[0x10];
6062
6063         u8         reserved_1[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         reserved_2[0x8];
6067         u8         tisn[0x18];
6068
6069         u8         reserved_3[0x20];
6070 };
6071
6072 struct mlx5_ifc_destroy_tir_out_bits {
6073         u8         status[0x8];
6074         u8         reserved_0[0x18];
6075
6076         u8         syndrome[0x20];
6077
6078         u8         reserved_1[0x40];
6079 };
6080
6081 struct mlx5_ifc_destroy_tir_in_bits {
6082         u8         opcode[0x10];
6083         u8         reserved_0[0x10];
6084
6085         u8         reserved_1[0x10];
6086         u8         op_mod[0x10];
6087
6088         u8         reserved_2[0x8];
6089         u8         tirn[0x18];
6090
6091         u8         reserved_3[0x20];
6092 };
6093
6094 struct mlx5_ifc_destroy_srq_out_bits {
6095         u8         status[0x8];
6096         u8         reserved_0[0x18];
6097
6098         u8         syndrome[0x20];
6099
6100         u8         reserved_1[0x40];
6101 };
6102
6103 struct mlx5_ifc_destroy_srq_in_bits {
6104         u8         opcode[0x10];
6105         u8         reserved_0[0x10];
6106
6107         u8         reserved_1[0x10];
6108         u8         op_mod[0x10];
6109
6110         u8         reserved_2[0x8];
6111         u8         srqn[0x18];
6112
6113         u8         reserved_3[0x20];
6114 };
6115
6116 struct mlx5_ifc_destroy_sq_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_0[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_1[0x40];
6123 };
6124
6125 struct mlx5_ifc_destroy_sq_in_bits {
6126         u8         opcode[0x10];
6127         u8         reserved_0[0x10];
6128
6129         u8         reserved_1[0x10];
6130         u8         op_mod[0x10];
6131
6132         u8         reserved_2[0x8];
6133         u8         sqn[0x18];
6134
6135         u8         reserved_3[0x20];
6136 };
6137
6138 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6139         u8         status[0x8];
6140         u8         reserved_at_8[0x18];
6141
6142         u8         syndrome[0x20];
6143
6144         u8         reserved_at_40[0x1c0];
6145 };
6146
6147 enum {
6148         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6149 };
6150
6151 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6152         u8         opcode[0x10];
6153         u8         reserved_at_10[0x10];
6154
6155         u8         reserved_at_20[0x10];
6156         u8         op_mod[0x10];
6157
6158         u8         scheduling_hierarchy[0x8];
6159         u8         reserved_at_48[0x18];
6160
6161         u8         scheduling_element_id[0x20];
6162
6163         u8         reserved_at_80[0x180];
6164 };
6165
6166 struct mlx5_ifc_destroy_rqt_out_bits {
6167         u8         status[0x8];
6168         u8         reserved_0[0x18];
6169
6170         u8         syndrome[0x20];
6171
6172         u8         reserved_1[0x40];
6173 };
6174
6175 struct mlx5_ifc_destroy_rqt_in_bits {
6176         u8         opcode[0x10];
6177         u8         reserved_0[0x10];
6178
6179         u8         reserved_1[0x10];
6180         u8         op_mod[0x10];
6181
6182         u8         reserved_2[0x8];
6183         u8         rqtn[0x18];
6184
6185         u8         reserved_3[0x20];
6186 };
6187
6188 struct mlx5_ifc_destroy_rq_out_bits {
6189         u8         status[0x8];
6190         u8         reserved_0[0x18];
6191
6192         u8         syndrome[0x20];
6193
6194         u8         reserved_1[0x40];
6195 };
6196
6197 struct mlx5_ifc_destroy_rq_in_bits {
6198         u8         opcode[0x10];
6199         u8         reserved_0[0x10];
6200
6201         u8         reserved_1[0x10];
6202         u8         op_mod[0x10];
6203
6204         u8         reserved_2[0x8];
6205         u8         rqn[0x18];
6206
6207         u8         reserved_3[0x20];
6208 };
6209
6210 struct mlx5_ifc_destroy_rmp_out_bits {
6211         u8         status[0x8];
6212         u8         reserved_0[0x18];
6213
6214         u8         syndrome[0x20];
6215
6216         u8         reserved_1[0x40];
6217 };
6218
6219 struct mlx5_ifc_destroy_rmp_in_bits {
6220         u8         opcode[0x10];
6221         u8         reserved_0[0x10];
6222
6223         u8         reserved_1[0x10];
6224         u8         op_mod[0x10];
6225
6226         u8         reserved_2[0x8];
6227         u8         rmpn[0x18];
6228
6229         u8         reserved_3[0x20];
6230 };
6231
6232 struct mlx5_ifc_destroy_qp_out_bits {
6233         u8         status[0x8];
6234         u8         reserved_0[0x18];
6235
6236         u8         syndrome[0x20];
6237
6238         u8         reserved_1[0x40];
6239 };
6240
6241 struct mlx5_ifc_destroy_qp_in_bits {
6242         u8         opcode[0x10];
6243         u8         reserved_0[0x10];
6244
6245         u8         reserved_1[0x10];
6246         u8         op_mod[0x10];
6247
6248         u8         reserved_2[0x8];
6249         u8         qpn[0x18];
6250
6251         u8         reserved_3[0x20];
6252 };
6253
6254 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6255         u8         status[0x8];
6256         u8         reserved_at_8[0x18];
6257
6258         u8         syndrome[0x20];
6259
6260         u8         reserved_at_40[0x1c0];
6261 };
6262
6263 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6264         u8         opcode[0x10];
6265         u8         reserved_at_10[0x10];
6266
6267         u8         reserved_at_20[0x10];
6268         u8         op_mod[0x10];
6269
6270         u8         reserved_at_40[0x20];
6271
6272         u8         reserved_at_60[0x10];
6273         u8         qos_para_vport_number[0x10];
6274
6275         u8         reserved_at_80[0x180];
6276 };
6277
6278 struct mlx5_ifc_destroy_psv_out_bits {
6279         u8         status[0x8];
6280         u8         reserved_0[0x18];
6281
6282         u8         syndrome[0x20];
6283
6284         u8         reserved_1[0x40];
6285 };
6286
6287 struct mlx5_ifc_destroy_psv_in_bits {
6288         u8         opcode[0x10];
6289         u8         reserved_0[0x10];
6290
6291         u8         reserved_1[0x10];
6292         u8         op_mod[0x10];
6293
6294         u8         reserved_2[0x8];
6295         u8         psvn[0x18];
6296
6297         u8         reserved_3[0x20];
6298 };
6299
6300 struct mlx5_ifc_destroy_mkey_out_bits {
6301         u8         status[0x8];
6302         u8         reserved_0[0x18];
6303
6304         u8         syndrome[0x20];
6305
6306         u8         reserved_1[0x40];
6307 };
6308
6309 struct mlx5_ifc_destroy_mkey_in_bits {
6310         u8         opcode[0x10];
6311         u8         reserved_0[0x10];
6312
6313         u8         reserved_1[0x10];
6314         u8         op_mod[0x10];
6315
6316         u8         reserved_2[0x8];
6317         u8         mkey_index[0x18];
6318
6319         u8         reserved_3[0x20];
6320 };
6321
6322 struct mlx5_ifc_destroy_flow_table_out_bits {
6323         u8         status[0x8];
6324         u8         reserved_0[0x18];
6325
6326         u8         syndrome[0x20];
6327
6328         u8         reserved_1[0x40];
6329 };
6330
6331 struct mlx5_ifc_destroy_flow_table_in_bits {
6332         u8         opcode[0x10];
6333         u8         reserved_0[0x10];
6334
6335         u8         reserved_1[0x10];
6336         u8         op_mod[0x10];
6337
6338         u8         other_vport[0x1];
6339         u8         reserved_2[0xf];
6340         u8         vport_number[0x10];
6341
6342         u8         reserved_3[0x20];
6343
6344         u8         table_type[0x8];
6345         u8         reserved_4[0x18];
6346
6347         u8         reserved_5[0x8];
6348         u8         table_id[0x18];
6349
6350         u8         reserved_6[0x140];
6351 };
6352
6353 struct mlx5_ifc_destroy_flow_group_out_bits {
6354         u8         status[0x8];
6355         u8         reserved_0[0x18];
6356
6357         u8         syndrome[0x20];
6358
6359         u8         reserved_1[0x40];
6360 };
6361
6362 struct mlx5_ifc_destroy_flow_group_in_bits {
6363         u8         opcode[0x10];
6364         u8         reserved_0[0x10];
6365
6366         u8         reserved_1[0x10];
6367         u8         op_mod[0x10];
6368
6369         u8         other_vport[0x1];
6370         u8         reserved_2[0xf];
6371         u8         vport_number[0x10];
6372
6373         u8         reserved_3[0x20];
6374
6375         u8         table_type[0x8];
6376         u8         reserved_4[0x18];
6377
6378         u8         reserved_5[0x8];
6379         u8         table_id[0x18];
6380
6381         u8         group_id[0x20];
6382
6383         u8         reserved_6[0x120];
6384 };
6385
6386 struct mlx5_ifc_destroy_eq_out_bits {
6387         u8         status[0x8];
6388         u8         reserved_0[0x18];
6389
6390         u8         syndrome[0x20];
6391
6392         u8         reserved_1[0x40];
6393 };
6394
6395 struct mlx5_ifc_destroy_eq_in_bits {
6396         u8         opcode[0x10];
6397         u8         reserved_0[0x10];
6398
6399         u8         reserved_1[0x10];
6400         u8         op_mod[0x10];
6401
6402         u8         reserved_2[0x18];
6403         u8         eq_number[0x8];
6404
6405         u8         reserved_3[0x20];
6406 };
6407
6408 struct mlx5_ifc_destroy_dct_out_bits {
6409         u8         status[0x8];
6410         u8         reserved_0[0x18];
6411
6412         u8         syndrome[0x20];
6413
6414         u8         reserved_1[0x40];
6415 };
6416
6417 struct mlx5_ifc_destroy_dct_in_bits {
6418         u8         opcode[0x10];
6419         u8         reserved_0[0x10];
6420
6421         u8         reserved_1[0x10];
6422         u8         op_mod[0x10];
6423
6424         u8         reserved_2[0x8];
6425         u8         dctn[0x18];
6426
6427         u8         reserved_3[0x20];
6428 };
6429
6430 struct mlx5_ifc_destroy_cq_out_bits {
6431         u8         status[0x8];
6432         u8         reserved_0[0x18];
6433
6434         u8         syndrome[0x20];
6435
6436         u8         reserved_1[0x40];
6437 };
6438
6439 struct mlx5_ifc_destroy_cq_in_bits {
6440         u8         opcode[0x10];
6441         u8         reserved_0[0x10];
6442
6443         u8         reserved_1[0x10];
6444         u8         op_mod[0x10];
6445
6446         u8         reserved_2[0x8];
6447         u8         cqn[0x18];
6448
6449         u8         reserved_3[0x20];
6450 };
6451
6452 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6453         u8         status[0x8];
6454         u8         reserved_0[0x18];
6455
6456         u8         syndrome[0x20];
6457
6458         u8         reserved_1[0x40];
6459 };
6460
6461 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6462         u8         opcode[0x10];
6463         u8         reserved_0[0x10];
6464
6465         u8         reserved_1[0x10];
6466         u8         op_mod[0x10];
6467
6468         u8         reserved_2[0x20];
6469
6470         u8         reserved_3[0x10];
6471         u8         vxlan_udp_port[0x10];
6472 };
6473
6474 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6475         u8         status[0x8];
6476         u8         reserved_0[0x18];
6477
6478         u8         syndrome[0x20];
6479
6480         u8         reserved_1[0x40];
6481 };
6482
6483 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6484         u8         opcode[0x10];
6485         u8         reserved_0[0x10];
6486
6487         u8         reserved_1[0x10];
6488         u8         op_mod[0x10];
6489
6490         u8         reserved_2[0x60];
6491
6492         u8         reserved_3[0x8];
6493         u8         table_index[0x18];
6494
6495         u8         reserved_4[0x140];
6496 };
6497
6498 struct mlx5_ifc_delete_fte_out_bits {
6499         u8         status[0x8];
6500         u8         reserved_0[0x18];
6501
6502         u8         syndrome[0x20];
6503
6504         u8         reserved_1[0x40];
6505 };
6506
6507 struct mlx5_ifc_delete_fte_in_bits {
6508         u8         opcode[0x10];
6509         u8         reserved_0[0x10];
6510
6511         u8         reserved_1[0x10];
6512         u8         op_mod[0x10];
6513
6514         u8         other_vport[0x1];
6515         u8         reserved_2[0xf];
6516         u8         vport_number[0x10];
6517
6518         u8         reserved_3[0x20];
6519
6520         u8         table_type[0x8];
6521         u8         reserved_4[0x18];
6522
6523         u8         reserved_5[0x8];
6524         u8         table_id[0x18];
6525
6526         u8         reserved_6[0x40];
6527
6528         u8         flow_index[0x20];
6529
6530         u8         reserved_7[0xe0];
6531 };
6532
6533 struct mlx5_ifc_dealloc_xrcd_out_bits {
6534         u8         status[0x8];
6535         u8         reserved_0[0x18];
6536
6537         u8         syndrome[0x20];
6538
6539         u8         reserved_1[0x40];
6540 };
6541
6542 struct mlx5_ifc_dealloc_xrcd_in_bits {
6543         u8         opcode[0x10];
6544         u8         reserved_0[0x10];
6545
6546         u8         reserved_1[0x10];
6547         u8         op_mod[0x10];
6548
6549         u8         reserved_2[0x8];
6550         u8         xrcd[0x18];
6551
6552         u8         reserved_3[0x20];
6553 };
6554
6555 struct mlx5_ifc_dealloc_uar_out_bits {
6556         u8         status[0x8];
6557         u8         reserved_0[0x18];
6558
6559         u8         syndrome[0x20];
6560
6561         u8         reserved_1[0x40];
6562 };
6563
6564 struct mlx5_ifc_dealloc_uar_in_bits {
6565         u8         opcode[0x10];
6566         u8         reserved_0[0x10];
6567
6568         u8         reserved_1[0x10];
6569         u8         op_mod[0x10];
6570
6571         u8         reserved_2[0x8];
6572         u8         uar[0x18];
6573
6574         u8         reserved_3[0x20];
6575 };
6576
6577 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6578         u8         status[0x8];
6579         u8         reserved_0[0x18];
6580
6581         u8         syndrome[0x20];
6582
6583         u8         reserved_1[0x40];
6584 };
6585
6586 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6587         u8         opcode[0x10];
6588         u8         reserved_0[0x10];
6589
6590         u8         reserved_1[0x10];
6591         u8         op_mod[0x10];
6592
6593         u8         reserved_2[0x8];
6594         u8         transport_domain[0x18];
6595
6596         u8         reserved_3[0x20];
6597 };
6598
6599 struct mlx5_ifc_dealloc_q_counter_out_bits {
6600         u8         status[0x8];
6601         u8         reserved_0[0x18];
6602
6603         u8         syndrome[0x20];
6604
6605         u8         reserved_1[0x40];
6606 };
6607
6608 struct mlx5_ifc_counter_id_bits {
6609         u8         reserved[0x10];
6610         u8         counter_id[0x10];
6611 };
6612
6613 struct mlx5_ifc_diagnostic_params_context_bits {
6614         u8         num_of_counters[0x10];
6615         u8         reserved_2[0x8];
6616         u8         log_num_of_samples[0x8];
6617
6618         u8         single[0x1];
6619         u8         repetitive[0x1];
6620         u8         sync[0x1];
6621         u8         clear[0x1];
6622         u8         on_demand[0x1];
6623         u8         enable[0x1];
6624         u8         reserved_3[0x12];
6625         u8         log_sample_period[0x8];
6626
6627         u8         reserved_4[0x80];
6628
6629         struct mlx5_ifc_counter_id_bits counter_id[0];
6630 };
6631
6632 struct mlx5_ifc_set_diagnostic_params_in_bits {
6633         u8         opcode[0x10];
6634         u8         reserved_0[0x10];
6635
6636         u8         reserved_1[0x10];
6637         u8         op_mod[0x10];
6638
6639         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6640 };
6641
6642 struct mlx5_ifc_set_diagnostic_params_out_bits {
6643         u8         status[0x8];
6644         u8         reserved_0[0x18];
6645
6646         u8         syndrome[0x20];
6647
6648         u8         reserved_1[0x40];
6649 };
6650
6651 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6652         u8         opcode[0x10];
6653         u8         reserved_0[0x10];
6654
6655         u8         reserved_1[0x10];
6656         u8         op_mod[0x10];
6657
6658         u8         num_of_samples[0x10];
6659         u8         sample_index[0x10];
6660
6661         u8         reserved_2[0x20];
6662 };
6663
6664 struct mlx5_ifc_diagnostic_counter_bits {
6665         u8         counter_id[0x10];
6666         u8         sample_id[0x10];
6667
6668         u8         time_stamp_31_0[0x20];
6669
6670         u8         counter_value_h[0x20];
6671
6672         u8         counter_value_l[0x20];
6673 };
6674
6675 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6676         u8         status[0x8];
6677         u8         reserved_0[0x18];
6678
6679         u8         syndrome[0x20];
6680
6681         u8         reserved_1[0x40];
6682
6683         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6684 };
6685
6686 struct mlx5_ifc_dealloc_q_counter_in_bits {
6687         u8         opcode[0x10];
6688         u8         reserved_0[0x10];
6689
6690         u8         reserved_1[0x10];
6691         u8         op_mod[0x10];
6692
6693         u8         reserved_2[0x18];
6694         u8         counter_set_id[0x8];
6695
6696         u8         reserved_3[0x20];
6697 };
6698
6699 struct mlx5_ifc_dealloc_pd_out_bits {
6700         u8         status[0x8];
6701         u8         reserved_0[0x18];
6702
6703         u8         syndrome[0x20];
6704
6705         u8         reserved_1[0x40];
6706 };
6707
6708 struct mlx5_ifc_dealloc_pd_in_bits {
6709         u8         opcode[0x10];
6710         u8         reserved_0[0x10];
6711
6712         u8         reserved_1[0x10];
6713         u8         op_mod[0x10];
6714
6715         u8         reserved_2[0x8];
6716         u8         pd[0x18];
6717
6718         u8         reserved_3[0x20];
6719 };
6720
6721 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6722         u8         status[0x8];
6723         u8         reserved_0[0x18];
6724
6725         u8         syndrome[0x20];
6726
6727         u8         reserved_1[0x40];
6728 };
6729
6730 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6731         u8         opcode[0x10];
6732         u8         reserved_0[0x10];
6733
6734         u8         reserved_1[0x10];
6735         u8         op_mod[0x10];
6736
6737         u8         reserved_2[0x10];
6738         u8         flow_counter_id[0x10];
6739
6740         u8         reserved_3[0x20];
6741 };
6742
6743 struct mlx5_ifc_deactivate_tracer_out_bits {
6744         u8         status[0x8];
6745         u8         reserved_0[0x18];
6746
6747         u8         syndrome[0x20];
6748
6749         u8         reserved_1[0x40];
6750 };
6751
6752 struct mlx5_ifc_deactivate_tracer_in_bits {
6753         u8         opcode[0x10];
6754         u8         reserved_0[0x10];
6755
6756         u8         reserved_1[0x10];
6757         u8         op_mod[0x10];
6758
6759         u8         mkey[0x20];
6760
6761         u8         reserved_2[0x20];
6762 };
6763
6764 struct mlx5_ifc_create_xrc_srq_out_bits {
6765         u8         status[0x8];
6766         u8         reserved_0[0x18];
6767
6768         u8         syndrome[0x20];
6769
6770         u8         reserved_1[0x8];
6771         u8         xrc_srqn[0x18];
6772
6773         u8         reserved_2[0x20];
6774 };
6775
6776 struct mlx5_ifc_create_xrc_srq_in_bits {
6777         u8         opcode[0x10];
6778         u8         reserved_0[0x10];
6779
6780         u8         reserved_1[0x10];
6781         u8         op_mod[0x10];
6782
6783         u8         reserved_2[0x40];
6784
6785         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6786
6787         u8         reserved_3[0x600];
6788
6789         u8         pas[0][0x40];
6790 };
6791
6792 struct mlx5_ifc_create_tis_out_bits {
6793         u8         status[0x8];
6794         u8         reserved_0[0x18];
6795
6796         u8         syndrome[0x20];
6797
6798         u8         reserved_1[0x8];
6799         u8         tisn[0x18];
6800
6801         u8         reserved_2[0x20];
6802 };
6803
6804 struct mlx5_ifc_create_tis_in_bits {
6805         u8         opcode[0x10];
6806         u8         reserved_0[0x10];
6807
6808         u8         reserved_1[0x10];
6809         u8         op_mod[0x10];
6810
6811         u8         reserved_2[0xc0];
6812
6813         struct mlx5_ifc_tisc_bits ctx;
6814 };
6815
6816 struct mlx5_ifc_create_tir_out_bits {
6817         u8         status[0x8];
6818         u8         reserved_0[0x18];
6819
6820         u8         syndrome[0x20];
6821
6822         u8         reserved_1[0x8];
6823         u8         tirn[0x18];
6824
6825         u8         reserved_2[0x20];
6826 };
6827
6828 struct mlx5_ifc_create_tir_in_bits {
6829         u8         opcode[0x10];
6830         u8         reserved_0[0x10];
6831
6832         u8         reserved_1[0x10];
6833         u8         op_mod[0x10];
6834
6835         u8         reserved_2[0xc0];
6836
6837         struct mlx5_ifc_tirc_bits tir_context;
6838 };
6839
6840 struct mlx5_ifc_create_srq_out_bits {
6841         u8         status[0x8];
6842         u8         reserved_0[0x18];
6843
6844         u8         syndrome[0x20];
6845
6846         u8         reserved_1[0x8];
6847         u8         srqn[0x18];
6848
6849         u8         reserved_2[0x20];
6850 };
6851
6852 struct mlx5_ifc_create_srq_in_bits {
6853         u8         opcode[0x10];
6854         u8         reserved_0[0x10];
6855
6856         u8         reserved_1[0x10];
6857         u8         op_mod[0x10];
6858
6859         u8         reserved_2[0x40];
6860
6861         struct mlx5_ifc_srqc_bits srq_context_entry;
6862
6863         u8         reserved_3[0x600];
6864
6865         u8         pas[0][0x40];
6866 };
6867
6868 struct mlx5_ifc_create_sq_out_bits {
6869         u8         status[0x8];
6870         u8         reserved_0[0x18];
6871
6872         u8         syndrome[0x20];
6873
6874         u8         reserved_1[0x8];
6875         u8         sqn[0x18];
6876
6877         u8         reserved_2[0x20];
6878 };
6879
6880 struct mlx5_ifc_create_sq_in_bits {
6881         u8         opcode[0x10];
6882         u8         reserved_0[0x10];
6883
6884         u8         reserved_1[0x10];
6885         u8         op_mod[0x10];
6886
6887         u8         reserved_2[0xc0];
6888
6889         struct mlx5_ifc_sqc_bits ctx;
6890 };
6891
6892 struct mlx5_ifc_create_scheduling_element_out_bits {
6893         u8         status[0x8];
6894         u8         reserved_at_8[0x18];
6895
6896         u8         syndrome[0x20];
6897
6898         u8         reserved_at_40[0x40];
6899
6900         u8         scheduling_element_id[0x20];
6901
6902         u8         reserved_at_a0[0x160];
6903 };
6904
6905 enum {
6906         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6907 };
6908
6909 struct mlx5_ifc_create_scheduling_element_in_bits {
6910         u8         opcode[0x10];
6911         u8         reserved_at_10[0x10];
6912
6913         u8         reserved_at_20[0x10];
6914         u8         op_mod[0x10];
6915
6916         u8         scheduling_hierarchy[0x8];
6917         u8         reserved_at_48[0x18];
6918
6919         u8         reserved_at_60[0xa0];
6920
6921         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6922
6923         u8         reserved_at_300[0x100];
6924 };
6925
6926 struct mlx5_ifc_create_rqt_out_bits {
6927         u8         status[0x8];
6928         u8         reserved_0[0x18];
6929
6930         u8         syndrome[0x20];
6931
6932         u8         reserved_1[0x8];
6933         u8         rqtn[0x18];
6934
6935         u8         reserved_2[0x20];
6936 };
6937
6938 struct mlx5_ifc_create_rqt_in_bits {
6939         u8         opcode[0x10];
6940         u8         reserved_0[0x10];
6941
6942         u8         reserved_1[0x10];
6943         u8         op_mod[0x10];
6944
6945         u8         reserved_2[0xc0];
6946
6947         struct mlx5_ifc_rqtc_bits rqt_context;
6948 };
6949
6950 struct mlx5_ifc_create_rq_out_bits {
6951         u8         status[0x8];
6952         u8         reserved_0[0x18];
6953
6954         u8         syndrome[0x20];
6955
6956         u8         reserved_1[0x8];
6957         u8         rqn[0x18];
6958
6959         u8         reserved_2[0x20];
6960 };
6961
6962 struct mlx5_ifc_create_rq_in_bits {
6963         u8         opcode[0x10];
6964         u8         reserved_0[0x10];
6965
6966         u8         reserved_1[0x10];
6967         u8         op_mod[0x10];
6968
6969         u8         reserved_2[0xc0];
6970
6971         struct mlx5_ifc_rqc_bits ctx;
6972 };
6973
6974 struct mlx5_ifc_create_rmp_out_bits {
6975         u8         status[0x8];
6976         u8         reserved_0[0x18];
6977
6978         u8         syndrome[0x20];
6979
6980         u8         reserved_1[0x8];
6981         u8         rmpn[0x18];
6982
6983         u8         reserved_2[0x20];
6984 };
6985
6986 struct mlx5_ifc_create_rmp_in_bits {
6987         u8         opcode[0x10];
6988         u8         reserved_0[0x10];
6989
6990         u8         reserved_1[0x10];
6991         u8         op_mod[0x10];
6992
6993         u8         reserved_2[0xc0];
6994
6995         struct mlx5_ifc_rmpc_bits ctx;
6996 };
6997
6998 struct mlx5_ifc_create_qp_out_bits {
6999         u8         status[0x8];
7000         u8         reserved_0[0x18];
7001
7002         u8         syndrome[0x20];
7003
7004         u8         reserved_1[0x8];
7005         u8         qpn[0x18];
7006
7007         u8         reserved_2[0x20];
7008 };
7009
7010 struct mlx5_ifc_create_qp_in_bits {
7011         u8         opcode[0x10];
7012         u8         reserved_0[0x10];
7013
7014         u8         reserved_1[0x10];
7015         u8         op_mod[0x10];
7016
7017         u8         reserved_2[0x8];
7018         u8         input_qpn[0x18];
7019
7020         u8         reserved_3[0x20];
7021
7022         u8         opt_param_mask[0x20];
7023
7024         u8         reserved_4[0x20];
7025
7026         struct mlx5_ifc_qpc_bits qpc;
7027
7028         u8         reserved_5[0x80];
7029
7030         u8         pas[0][0x40];
7031 };
7032
7033 struct mlx5_ifc_create_qos_para_vport_out_bits {
7034         u8         status[0x8];
7035         u8         reserved_at_8[0x18];
7036
7037         u8         syndrome[0x20];
7038
7039         u8         reserved_at_40[0x20];
7040
7041         u8         reserved_at_60[0x10];
7042         u8         qos_para_vport_number[0x10];
7043
7044         u8         reserved_at_80[0x180];
7045 };
7046
7047 struct mlx5_ifc_create_qos_para_vport_in_bits {
7048         u8         opcode[0x10];
7049         u8         reserved_at_10[0x10];
7050
7051         u8         reserved_at_20[0x10];
7052         u8         op_mod[0x10];
7053
7054         u8         reserved_at_40[0x1c0];
7055 };
7056
7057 struct mlx5_ifc_create_psv_out_bits {
7058         u8         status[0x8];
7059         u8         reserved_0[0x18];
7060
7061         u8         syndrome[0x20];
7062
7063         u8         reserved_1[0x40];
7064
7065         u8         reserved_2[0x8];
7066         u8         psv0_index[0x18];
7067
7068         u8         reserved_3[0x8];
7069         u8         psv1_index[0x18];
7070
7071         u8         reserved_4[0x8];
7072         u8         psv2_index[0x18];
7073
7074         u8         reserved_5[0x8];
7075         u8         psv3_index[0x18];
7076 };
7077
7078 struct mlx5_ifc_create_psv_in_bits {
7079         u8         opcode[0x10];
7080         u8         reserved_0[0x10];
7081
7082         u8         reserved_1[0x10];
7083         u8         op_mod[0x10];
7084
7085         u8         num_psv[0x4];
7086         u8         reserved_2[0x4];
7087         u8         pd[0x18];
7088
7089         u8         reserved_3[0x20];
7090 };
7091
7092 struct mlx5_ifc_create_mkey_out_bits {
7093         u8         status[0x8];
7094         u8         reserved_0[0x18];
7095
7096         u8         syndrome[0x20];
7097
7098         u8         reserved_1[0x8];
7099         u8         mkey_index[0x18];
7100
7101         u8         reserved_2[0x20];
7102 };
7103
7104 struct mlx5_ifc_create_mkey_in_bits {
7105         u8         opcode[0x10];
7106         u8         reserved_0[0x10];
7107
7108         u8         reserved_1[0x10];
7109         u8         op_mod[0x10];
7110
7111         u8         reserved_2[0x20];
7112
7113         u8         pg_access[0x1];
7114         u8         reserved_3[0x1f];
7115
7116         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7117
7118         u8         reserved_4[0x80];
7119
7120         u8         translations_octword_actual_size[0x20];
7121
7122         u8         reserved_5[0x560];
7123
7124         u8         klm_pas_mtt[0][0x20];
7125 };
7126
7127 struct mlx5_ifc_create_flow_table_out_bits {
7128         u8         status[0x8];
7129         u8         reserved_0[0x18];
7130
7131         u8         syndrome[0x20];
7132
7133         u8         reserved_1[0x8];
7134         u8         table_id[0x18];
7135
7136         u8         reserved_2[0x20];
7137 };
7138
7139 struct mlx5_ifc_create_flow_table_in_bits {
7140         u8         opcode[0x10];
7141         u8         reserved_at_10[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         other_vport[0x1];
7147         u8         reserved_at_41[0xf];
7148         u8         vport_number[0x10];
7149
7150         u8         reserved_at_60[0x20];
7151
7152         u8         table_type[0x8];
7153         u8         reserved_at_88[0x18];
7154
7155         u8         reserved_at_a0[0x20];
7156
7157         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7158 };
7159
7160 struct mlx5_ifc_create_flow_group_out_bits {
7161         u8         status[0x8];
7162         u8         reserved_0[0x18];
7163
7164         u8         syndrome[0x20];
7165
7166         u8         reserved_1[0x8];
7167         u8         group_id[0x18];
7168
7169         u8         reserved_2[0x20];
7170 };
7171
7172 enum {
7173         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7174         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7175         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7176 };
7177
7178 struct mlx5_ifc_create_flow_group_in_bits {
7179         u8         opcode[0x10];
7180         u8         reserved_0[0x10];
7181
7182         u8         reserved_1[0x10];
7183         u8         op_mod[0x10];
7184
7185         u8         other_vport[0x1];
7186         u8         reserved_2[0xf];
7187         u8         vport_number[0x10];
7188
7189         u8         reserved_3[0x20];
7190
7191         u8         table_type[0x8];
7192         u8         reserved_4[0x18];
7193
7194         u8         reserved_5[0x8];
7195         u8         table_id[0x18];
7196
7197         u8         reserved_6[0x20];
7198
7199         u8         start_flow_index[0x20];
7200
7201         u8         reserved_7[0x20];
7202
7203         u8         end_flow_index[0x20];
7204
7205         u8         reserved_8[0xa0];
7206
7207         u8         reserved_9[0x18];
7208         u8         match_criteria_enable[0x8];
7209
7210         struct mlx5_ifc_fte_match_param_bits match_criteria;
7211
7212         u8         reserved_10[0xe00];
7213 };
7214
7215 struct mlx5_ifc_create_eq_out_bits {
7216         u8         status[0x8];
7217         u8         reserved_0[0x18];
7218
7219         u8         syndrome[0x20];
7220
7221         u8         reserved_1[0x18];
7222         u8         eq_number[0x8];
7223
7224         u8         reserved_2[0x20];
7225 };
7226
7227 struct mlx5_ifc_create_eq_in_bits {
7228         u8         opcode[0x10];
7229         u8         reserved_0[0x10];
7230
7231         u8         reserved_1[0x10];
7232         u8         op_mod[0x10];
7233
7234         u8         reserved_2[0x40];
7235
7236         struct mlx5_ifc_eqc_bits eq_context_entry;
7237
7238         u8         reserved_3[0x40];
7239
7240         u8         event_bitmask[0x40];
7241
7242         u8         reserved_4[0x580];
7243
7244         u8         pas[0][0x40];
7245 };
7246
7247 struct mlx5_ifc_create_dct_out_bits {
7248         u8         status[0x8];
7249         u8         reserved_0[0x18];
7250
7251         u8         syndrome[0x20];
7252
7253         u8         reserved_1[0x8];
7254         u8         dctn[0x18];
7255
7256         u8         reserved_2[0x20];
7257 };
7258
7259 struct mlx5_ifc_create_dct_in_bits {
7260         u8         opcode[0x10];
7261         u8         reserved_0[0x10];
7262
7263         u8         reserved_1[0x10];
7264         u8         op_mod[0x10];
7265
7266         u8         reserved_2[0x40];
7267
7268         struct mlx5_ifc_dctc_bits dct_context_entry;
7269
7270         u8         reserved_3[0x180];
7271 };
7272
7273 struct mlx5_ifc_create_cq_out_bits {
7274         u8         status[0x8];
7275         u8         reserved_0[0x18];
7276
7277         u8         syndrome[0x20];
7278
7279         u8         reserved_1[0x8];
7280         u8         cqn[0x18];
7281
7282         u8         reserved_2[0x20];
7283 };
7284
7285 struct mlx5_ifc_create_cq_in_bits {
7286         u8         opcode[0x10];
7287         u8         reserved_0[0x10];
7288
7289         u8         reserved_1[0x10];
7290         u8         op_mod[0x10];
7291
7292         u8         reserved_2[0x40];
7293
7294         struct mlx5_ifc_cqc_bits cq_context;
7295
7296         u8         reserved_3[0x600];
7297
7298         u8         pas[0][0x40];
7299 };
7300
7301 struct mlx5_ifc_config_int_moderation_out_bits {
7302         u8         status[0x8];
7303         u8         reserved_0[0x18];
7304
7305         u8         syndrome[0x20];
7306
7307         u8         reserved_1[0x4];
7308         u8         min_delay[0xc];
7309         u8         int_vector[0x10];
7310
7311         u8         reserved_2[0x20];
7312 };
7313
7314 enum {
7315         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7316         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7317 };
7318
7319 struct mlx5_ifc_config_int_moderation_in_bits {
7320         u8         opcode[0x10];
7321         u8         reserved_0[0x10];
7322
7323         u8         reserved_1[0x10];
7324         u8         op_mod[0x10];
7325
7326         u8         reserved_2[0x4];
7327         u8         min_delay[0xc];
7328         u8         int_vector[0x10];
7329
7330         u8         reserved_3[0x20];
7331 };
7332
7333 struct mlx5_ifc_attach_to_mcg_out_bits {
7334         u8         status[0x8];
7335         u8         reserved_0[0x18];
7336
7337         u8         syndrome[0x20];
7338
7339         u8         reserved_1[0x40];
7340 };
7341
7342 struct mlx5_ifc_attach_to_mcg_in_bits {
7343         u8         opcode[0x10];
7344         u8         reserved_0[0x10];
7345
7346         u8         reserved_1[0x10];
7347         u8         op_mod[0x10];
7348
7349         u8         reserved_2[0x8];
7350         u8         qpn[0x18];
7351
7352         u8         reserved_3[0x20];
7353
7354         u8         multicast_gid[16][0x8];
7355 };
7356
7357 struct mlx5_ifc_arm_xrc_srq_out_bits {
7358         u8         status[0x8];
7359         u8         reserved_0[0x18];
7360
7361         u8         syndrome[0x20];
7362
7363         u8         reserved_1[0x40];
7364 };
7365
7366 enum {
7367         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7368 };
7369
7370 struct mlx5_ifc_arm_xrc_srq_in_bits {
7371         u8         opcode[0x10];
7372         u8         reserved_0[0x10];
7373
7374         u8         reserved_1[0x10];
7375         u8         op_mod[0x10];
7376
7377         u8         reserved_2[0x8];
7378         u8         xrc_srqn[0x18];
7379
7380         u8         reserved_3[0x10];
7381         u8         lwm[0x10];
7382 };
7383
7384 struct mlx5_ifc_arm_rq_out_bits {
7385         u8         status[0x8];
7386         u8         reserved_0[0x18];
7387
7388         u8         syndrome[0x20];
7389
7390         u8         reserved_1[0x40];
7391 };
7392
7393 enum {
7394         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7395 };
7396
7397 struct mlx5_ifc_arm_rq_in_bits {
7398         u8         opcode[0x10];
7399         u8         reserved_0[0x10];
7400
7401         u8         reserved_1[0x10];
7402         u8         op_mod[0x10];
7403
7404         u8         reserved_2[0x8];
7405         u8         srq_number[0x18];
7406
7407         u8         reserved_3[0x10];
7408         u8         lwm[0x10];
7409 };
7410
7411 struct mlx5_ifc_arm_dct_out_bits {
7412         u8         status[0x8];
7413         u8         reserved_0[0x18];
7414
7415         u8         syndrome[0x20];
7416
7417         u8         reserved_1[0x40];
7418 };
7419
7420 struct mlx5_ifc_arm_dct_in_bits {
7421         u8         opcode[0x10];
7422         u8         reserved_0[0x10];
7423
7424         u8         reserved_1[0x10];
7425         u8         op_mod[0x10];
7426
7427         u8         reserved_2[0x8];
7428         u8         dctn[0x18];
7429
7430         u8         reserved_3[0x20];
7431 };
7432
7433 struct mlx5_ifc_alloc_xrcd_out_bits {
7434         u8         status[0x8];
7435         u8         reserved_0[0x18];
7436
7437         u8         syndrome[0x20];
7438
7439         u8         reserved_1[0x8];
7440         u8         xrcd[0x18];
7441
7442         u8         reserved_2[0x20];
7443 };
7444
7445 struct mlx5_ifc_alloc_xrcd_in_bits {
7446         u8         opcode[0x10];
7447         u8         reserved_0[0x10];
7448
7449         u8         reserved_1[0x10];
7450         u8         op_mod[0x10];
7451
7452         u8         reserved_2[0x40];
7453 };
7454
7455 struct mlx5_ifc_alloc_uar_out_bits {
7456         u8         status[0x8];
7457         u8         reserved_0[0x18];
7458
7459         u8         syndrome[0x20];
7460
7461         u8         reserved_1[0x8];
7462         u8         uar[0x18];
7463
7464         u8         reserved_2[0x20];
7465 };
7466
7467 struct mlx5_ifc_alloc_uar_in_bits {
7468         u8         opcode[0x10];
7469         u8         reserved_0[0x10];
7470
7471         u8         reserved_1[0x10];
7472         u8         op_mod[0x10];
7473
7474         u8         reserved_2[0x40];
7475 };
7476
7477 struct mlx5_ifc_alloc_transport_domain_out_bits {
7478         u8         status[0x8];
7479         u8         reserved_0[0x18];
7480
7481         u8         syndrome[0x20];
7482
7483         u8         reserved_1[0x8];
7484         u8         transport_domain[0x18];
7485
7486         u8         reserved_2[0x20];
7487 };
7488
7489 struct mlx5_ifc_alloc_transport_domain_in_bits {
7490         u8         opcode[0x10];
7491         u8         reserved_0[0x10];
7492
7493         u8         reserved_1[0x10];
7494         u8         op_mod[0x10];
7495
7496         u8         reserved_2[0x40];
7497 };
7498
7499 struct mlx5_ifc_alloc_q_counter_out_bits {
7500         u8         status[0x8];
7501         u8         reserved_0[0x18];
7502
7503         u8         syndrome[0x20];
7504
7505         u8         reserved_1[0x18];
7506         u8         counter_set_id[0x8];
7507
7508         u8         reserved_2[0x20];
7509 };
7510
7511 struct mlx5_ifc_alloc_q_counter_in_bits {
7512         u8         opcode[0x10];
7513         u8         reserved_0[0x10];
7514
7515         u8         reserved_1[0x10];
7516         u8         op_mod[0x10];
7517
7518         u8         reserved_2[0x40];
7519 };
7520
7521 struct mlx5_ifc_alloc_pd_out_bits {
7522         u8         status[0x8];
7523         u8         reserved_0[0x18];
7524
7525         u8         syndrome[0x20];
7526
7527         u8         reserved_1[0x8];
7528         u8         pd[0x18];
7529
7530         u8         reserved_2[0x20];
7531 };
7532
7533 struct mlx5_ifc_alloc_pd_in_bits {
7534         u8         opcode[0x10];
7535         u8         reserved_0[0x10];
7536
7537         u8         reserved_1[0x10];
7538         u8         op_mod[0x10];
7539
7540         u8         reserved_2[0x40];
7541 };
7542
7543 struct mlx5_ifc_alloc_flow_counter_out_bits {
7544         u8         status[0x8];
7545         u8         reserved_0[0x18];
7546
7547         u8         syndrome[0x20];
7548
7549         u8         reserved_1[0x10];
7550         u8         flow_counter_id[0x10];
7551
7552         u8         reserved_2[0x20];
7553 };
7554
7555 struct mlx5_ifc_alloc_flow_counter_in_bits {
7556         u8         opcode[0x10];
7557         u8         reserved_0[0x10];
7558
7559         u8         reserved_1[0x10];
7560         u8         op_mod[0x10];
7561
7562         u8         reserved_2[0x40];
7563 };
7564
7565 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7566         u8         status[0x8];
7567         u8         reserved_0[0x18];
7568
7569         u8         syndrome[0x20];
7570
7571         u8         reserved_1[0x40];
7572 };
7573
7574 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7575         u8         opcode[0x10];
7576         u8         reserved_0[0x10];
7577
7578         u8         reserved_1[0x10];
7579         u8         op_mod[0x10];
7580
7581         u8         reserved_2[0x20];
7582
7583         u8         reserved_3[0x10];
7584         u8         vxlan_udp_port[0x10];
7585 };
7586
7587 struct mlx5_ifc_activate_tracer_out_bits {
7588         u8         status[0x8];
7589         u8         reserved_0[0x18];
7590
7591         u8         syndrome[0x20];
7592
7593         u8         reserved_1[0x40];
7594 };
7595
7596 struct mlx5_ifc_activate_tracer_in_bits {
7597         u8         opcode[0x10];
7598         u8         reserved_0[0x10];
7599
7600         u8         reserved_1[0x10];
7601         u8         op_mod[0x10];
7602
7603         u8         mkey[0x20];
7604
7605         u8         reserved_2[0x20];
7606 };
7607
7608 struct mlx5_ifc_set_rate_limit_out_bits {
7609         u8         status[0x8];
7610         u8         reserved_at_8[0x18];
7611
7612         u8         syndrome[0x20];
7613
7614         u8         reserved_at_40[0x40];
7615 };
7616
7617 struct mlx5_ifc_set_rate_limit_in_bits {
7618         u8         opcode[0x10];
7619         u8         reserved_at_10[0x10];
7620
7621         u8         reserved_at_20[0x10];
7622         u8         op_mod[0x10];
7623
7624         u8         reserved_at_40[0x10];
7625         u8         rate_limit_index[0x10];
7626
7627         u8         reserved_at_60[0x20];
7628
7629         u8         rate_limit[0x20];
7630         u8         burst_upper_bound[0x20];
7631 };
7632
7633 struct mlx5_ifc_access_register_out_bits {
7634         u8         status[0x8];
7635         u8         reserved_0[0x18];
7636
7637         u8         syndrome[0x20];
7638
7639         u8         reserved_1[0x40];
7640
7641         u8         register_data[0][0x20];
7642 };
7643
7644 enum {
7645         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7646         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7647 };
7648
7649 struct mlx5_ifc_access_register_in_bits {
7650         u8         opcode[0x10];
7651         u8         reserved_0[0x10];
7652
7653         u8         reserved_1[0x10];
7654         u8         op_mod[0x10];
7655
7656         u8         reserved_2[0x10];
7657         u8         register_id[0x10];
7658
7659         u8         argument[0x20];
7660
7661         u8         register_data[0][0x20];
7662 };
7663
7664 struct mlx5_ifc_sltp_reg_bits {
7665         u8         status[0x4];
7666         u8         version[0x4];
7667         u8         local_port[0x8];
7668         u8         pnat[0x2];
7669         u8         reserved_0[0x2];
7670         u8         lane[0x4];
7671         u8         reserved_1[0x8];
7672
7673         u8         reserved_2[0x20];
7674
7675         u8         reserved_3[0x7];
7676         u8         polarity[0x1];
7677         u8         ob_tap0[0x8];
7678         u8         ob_tap1[0x8];
7679         u8         ob_tap2[0x8];
7680
7681         u8         reserved_4[0xc];
7682         u8         ob_preemp_mode[0x4];
7683         u8         ob_reg[0x8];
7684         u8         ob_bias[0x8];
7685
7686         u8         reserved_5[0x20];
7687 };
7688
7689 struct mlx5_ifc_slrp_reg_bits {
7690         u8         status[0x4];
7691         u8         version[0x4];
7692         u8         local_port[0x8];
7693         u8         pnat[0x2];
7694         u8         reserved_0[0x2];
7695         u8         lane[0x4];
7696         u8         reserved_1[0x8];
7697
7698         u8         ib_sel[0x2];
7699         u8         reserved_2[0x11];
7700         u8         dp_sel[0x1];
7701         u8         dp90sel[0x4];
7702         u8         mix90phase[0x8];
7703
7704         u8         ffe_tap0[0x8];
7705         u8         ffe_tap1[0x8];
7706         u8         ffe_tap2[0x8];
7707         u8         ffe_tap3[0x8];
7708
7709         u8         ffe_tap4[0x8];
7710         u8         ffe_tap5[0x8];
7711         u8         ffe_tap6[0x8];
7712         u8         ffe_tap7[0x8];
7713
7714         u8         ffe_tap8[0x8];
7715         u8         mixerbias_tap_amp[0x8];
7716         u8         reserved_3[0x7];
7717         u8         ffe_tap_en[0x9];
7718
7719         u8         ffe_tap_offset0[0x8];
7720         u8         ffe_tap_offset1[0x8];
7721         u8         slicer_offset0[0x10];
7722
7723         u8         mixer_offset0[0x10];
7724         u8         mixer_offset1[0x10];
7725
7726         u8         mixerbgn_inp[0x8];
7727         u8         mixerbgn_inn[0x8];
7728         u8         mixerbgn_refp[0x8];
7729         u8         mixerbgn_refn[0x8];
7730
7731         u8         sel_slicer_lctrl_h[0x1];
7732         u8         sel_slicer_lctrl_l[0x1];
7733         u8         reserved_4[0x1];
7734         u8         ref_mixer_vreg[0x5];
7735         u8         slicer_gctrl[0x8];
7736         u8         lctrl_input[0x8];
7737         u8         mixer_offset_cm1[0x8];
7738
7739         u8         common_mode[0x6];
7740         u8         reserved_5[0x1];
7741         u8         mixer_offset_cm0[0x9];
7742         u8         reserved_6[0x7];
7743         u8         slicer_offset_cm[0x9];
7744 };
7745
7746 struct mlx5_ifc_slrg_reg_bits {
7747         u8         status[0x4];
7748         u8         version[0x4];
7749         u8         local_port[0x8];
7750         u8         pnat[0x2];
7751         u8         reserved_0[0x2];
7752         u8         lane[0x4];
7753         u8         reserved_1[0x8];
7754
7755         u8         time_to_link_up[0x10];
7756         u8         reserved_2[0xc];
7757         u8         grade_lane_speed[0x4];
7758
7759         u8         grade_version[0x8];
7760         u8         grade[0x18];
7761
7762         u8         reserved_3[0x4];
7763         u8         height_grade_type[0x4];
7764         u8         height_grade[0x18];
7765
7766         u8         height_dz[0x10];
7767         u8         height_dv[0x10];
7768
7769         u8         reserved_4[0x10];
7770         u8         height_sigma[0x10];
7771
7772         u8         reserved_5[0x20];
7773
7774         u8         reserved_6[0x4];
7775         u8         phase_grade_type[0x4];
7776         u8         phase_grade[0x18];
7777
7778         u8         reserved_7[0x8];
7779         u8         phase_eo_pos[0x8];
7780         u8         reserved_8[0x8];
7781         u8         phase_eo_neg[0x8];
7782
7783         u8         ffe_set_tested[0x10];
7784         u8         test_errors_per_lane[0x10];
7785 };
7786
7787 struct mlx5_ifc_pvlc_reg_bits {
7788         u8         reserved_0[0x8];
7789         u8         local_port[0x8];
7790         u8         reserved_1[0x10];
7791
7792         u8         reserved_2[0x1c];
7793         u8         vl_hw_cap[0x4];
7794
7795         u8         reserved_3[0x1c];
7796         u8         vl_admin[0x4];
7797
7798         u8         reserved_4[0x1c];
7799         u8         vl_operational[0x4];
7800 };
7801
7802 struct mlx5_ifc_pude_reg_bits {
7803         u8         swid[0x8];
7804         u8         local_port[0x8];
7805         u8         reserved_0[0x4];
7806         u8         admin_status[0x4];
7807         u8         reserved_1[0x4];
7808         u8         oper_status[0x4];
7809
7810         u8         reserved_2[0x60];
7811 };
7812
7813 enum {
7814         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7815         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7816 };
7817
7818 struct mlx5_ifc_ptys_reg_bits {
7819         u8         reserved_0[0x1];
7820         u8         an_disable_admin[0x1];
7821         u8         an_disable_cap[0x1];
7822         u8         reserved_1[0x4];
7823         u8         force_tx_aba_param[0x1];
7824         u8         local_port[0x8];
7825         u8         reserved_2[0xd];
7826         u8         proto_mask[0x3];
7827
7828         u8         an_status[0x4];
7829         u8         reserved_3[0xc];
7830         u8         data_rate_oper[0x10];
7831
7832         u8         fc_proto_capability[0x20];
7833
7834         u8         eth_proto_capability[0x20];
7835
7836         u8         ib_link_width_capability[0x10];
7837         u8         ib_proto_capability[0x10];
7838
7839         u8         fc_proto_admin[0x20];
7840
7841         u8         eth_proto_admin[0x20];
7842
7843         u8         ib_link_width_admin[0x10];
7844         u8         ib_proto_admin[0x10];
7845
7846         u8         fc_proto_oper[0x20];
7847
7848         u8         eth_proto_oper[0x20];
7849
7850         u8         ib_link_width_oper[0x10];
7851         u8         ib_proto_oper[0x10];
7852
7853         u8         reserved_4[0x20];
7854
7855         u8         eth_proto_lp_advertise[0x20];
7856
7857         u8         reserved_5[0x60];
7858 };
7859
7860 struct mlx5_ifc_ptas_reg_bits {
7861         u8         reserved_0[0x20];
7862
7863         u8         algorithm_options[0x10];
7864         u8         reserved_1[0x4];
7865         u8         repetitions_mode[0x4];
7866         u8         num_of_repetitions[0x8];
7867
7868         u8         grade_version[0x8];
7869         u8         height_grade_type[0x4];
7870         u8         phase_grade_type[0x4];
7871         u8         height_grade_weight[0x8];
7872         u8         phase_grade_weight[0x8];
7873
7874         u8         gisim_measure_bits[0x10];
7875         u8         adaptive_tap_measure_bits[0x10];
7876
7877         u8         ber_bath_high_error_threshold[0x10];
7878         u8         ber_bath_mid_error_threshold[0x10];
7879
7880         u8         ber_bath_low_error_threshold[0x10];
7881         u8         one_ratio_high_threshold[0x10];
7882
7883         u8         one_ratio_high_mid_threshold[0x10];
7884         u8         one_ratio_low_mid_threshold[0x10];
7885
7886         u8         one_ratio_low_threshold[0x10];
7887         u8         ndeo_error_threshold[0x10];
7888
7889         u8         mixer_offset_step_size[0x10];
7890         u8         reserved_2[0x8];
7891         u8         mix90_phase_for_voltage_bath[0x8];
7892
7893         u8         mixer_offset_start[0x10];
7894         u8         mixer_offset_end[0x10];
7895
7896         u8         reserved_3[0x15];
7897         u8         ber_test_time[0xb];
7898 };
7899
7900 struct mlx5_ifc_pspa_reg_bits {
7901         u8         swid[0x8];
7902         u8         local_port[0x8];
7903         u8         sub_port[0x8];
7904         u8         reserved_0[0x8];
7905
7906         u8         reserved_1[0x20];
7907 };
7908
7909 struct mlx5_ifc_ppsc_reg_bits {
7910         u8         reserved_0[0x8];
7911         u8         local_port[0x8];
7912         u8         reserved_1[0x10];
7913
7914         u8         reserved_2[0x60];
7915
7916         u8         reserved_3[0x1c];
7917         u8         wrps_admin[0x4];
7918
7919         u8         reserved_4[0x1c];
7920         u8         wrps_status[0x4];
7921
7922         u8         up_th_vld[0x1];
7923         u8         down_th_vld[0x1];
7924         u8         reserved_5[0x6];
7925         u8         up_threshold[0x8];
7926         u8         reserved_6[0x8];
7927         u8         down_threshold[0x8];
7928
7929         u8         reserved_7[0x20];
7930
7931         u8         reserved_8[0x1c];
7932         u8         srps_admin[0x4];
7933
7934         u8         reserved_9[0x60];
7935 };
7936
7937 struct mlx5_ifc_pplr_reg_bits {
7938         u8         reserved_0[0x8];
7939         u8         local_port[0x8];
7940         u8         reserved_1[0x10];
7941
7942         u8         reserved_2[0x8];
7943         u8         lb_cap[0x8];
7944         u8         reserved_3[0x8];
7945         u8         lb_en[0x8];
7946 };
7947
7948 struct mlx5_ifc_pplm_reg_bits {
7949         u8         reserved_0[0x8];
7950         u8         local_port[0x8];
7951         u8         reserved_1[0x10];
7952
7953         u8         reserved_2[0x20];
7954
7955         u8         port_profile_mode[0x8];
7956         u8         static_port_profile[0x8];
7957         u8         active_port_profile[0x8];
7958         u8         reserved_3[0x8];
7959
7960         u8         retransmission_active[0x8];
7961         u8         fec_mode_active[0x18];
7962
7963         u8         reserved_4[0x10];
7964         u8         v_100g_fec_override_cap[0x4];
7965         u8         v_50g_fec_override_cap[0x4];
7966         u8         v_25g_fec_override_cap[0x4];
7967         u8         v_10g_40g_fec_override_cap[0x4];
7968
7969         u8         reserved_5[0x10];
7970         u8         v_100g_fec_override_admin[0x4];
7971         u8         v_50g_fec_override_admin[0x4];
7972         u8         v_25g_fec_override_admin[0x4];
7973         u8         v_10g_40g_fec_override_admin[0x4];
7974 };
7975
7976 struct mlx5_ifc_ppll_reg_bits {
7977         u8         num_pll_groups[0x8];
7978         u8         pll_group[0x8];
7979         u8         reserved_0[0x4];
7980         u8         num_plls[0x4];
7981         u8         reserved_1[0x8];
7982
7983         u8         reserved_2[0x1f];
7984         u8         ae[0x1];
7985
7986         u8         pll_status[4][0x40];
7987 };
7988
7989 struct mlx5_ifc_ppad_reg_bits {
7990         u8         reserved_0[0x3];
7991         u8         single_mac[0x1];
7992         u8         reserved_1[0x4];
7993         u8         local_port[0x8];
7994         u8         mac_47_32[0x10];
7995
7996         u8         mac_31_0[0x20];
7997
7998         u8         reserved_2[0x40];
7999 };
8000
8001 struct mlx5_ifc_pmtu_reg_bits {
8002         u8         reserved_0[0x8];
8003         u8         local_port[0x8];
8004         u8         reserved_1[0x10];
8005
8006         u8         max_mtu[0x10];
8007         u8         reserved_2[0x10];
8008
8009         u8         admin_mtu[0x10];
8010         u8         reserved_3[0x10];
8011
8012         u8         oper_mtu[0x10];
8013         u8         reserved_4[0x10];
8014 };
8015
8016 struct mlx5_ifc_pmpr_reg_bits {
8017         u8         reserved_0[0x8];
8018         u8         module[0x8];
8019         u8         reserved_1[0x10];
8020
8021         u8         reserved_2[0x18];
8022         u8         attenuation_5g[0x8];
8023
8024         u8         reserved_3[0x18];
8025         u8         attenuation_7g[0x8];
8026
8027         u8         reserved_4[0x18];
8028         u8         attenuation_12g[0x8];
8029 };
8030
8031 struct mlx5_ifc_pmpe_reg_bits {
8032         u8         reserved_0[0x8];
8033         u8         module[0x8];
8034         u8         reserved_1[0xc];
8035         u8         module_status[0x4];
8036
8037         u8         reserved_2[0x14];
8038         u8         error_type[0x4];
8039         u8         reserved_3[0x8];
8040
8041         u8         reserved_4[0x40];
8042 };
8043
8044 struct mlx5_ifc_pmpc_reg_bits {
8045         u8         module_state_updated[32][0x8];
8046 };
8047
8048 struct mlx5_ifc_pmlpn_reg_bits {
8049         u8         reserved_0[0x4];
8050         u8         mlpn_status[0x4];
8051         u8         local_port[0x8];
8052         u8         reserved_1[0x10];
8053
8054         u8         e[0x1];
8055         u8         reserved_2[0x1f];
8056 };
8057
8058 struct mlx5_ifc_pmlp_reg_bits {
8059         u8         rxtx[0x1];
8060         u8         reserved_0[0x7];
8061         u8         local_port[0x8];
8062         u8         reserved_1[0x8];
8063         u8         width[0x8];
8064
8065         u8         lane0_module_mapping[0x20];
8066
8067         u8         lane1_module_mapping[0x20];
8068
8069         u8         lane2_module_mapping[0x20];
8070
8071         u8         lane3_module_mapping[0x20];
8072
8073         u8         reserved_2[0x160];
8074 };
8075
8076 struct mlx5_ifc_pmaos_reg_bits {
8077         u8         reserved_0[0x8];
8078         u8         module[0x8];
8079         u8         reserved_1[0x4];
8080         u8         admin_status[0x4];
8081         u8         reserved_2[0x4];
8082         u8         oper_status[0x4];
8083
8084         u8         ase[0x1];
8085         u8         ee[0x1];
8086         u8         reserved_3[0x12];
8087         u8         error_type[0x4];
8088         u8         reserved_4[0x6];
8089         u8         e[0x2];
8090
8091         u8         reserved_5[0x40];
8092 };
8093
8094 struct mlx5_ifc_plpc_reg_bits {
8095         u8         reserved_0[0x4];
8096         u8         profile_id[0xc];
8097         u8         reserved_1[0x4];
8098         u8         proto_mask[0x4];
8099         u8         reserved_2[0x8];
8100
8101         u8         reserved_3[0x10];
8102         u8         lane_speed[0x10];
8103
8104         u8         reserved_4[0x17];
8105         u8         lpbf[0x1];
8106         u8         fec_mode_policy[0x8];
8107
8108         u8         retransmission_capability[0x8];
8109         u8         fec_mode_capability[0x18];
8110
8111         u8         retransmission_support_admin[0x8];
8112         u8         fec_mode_support_admin[0x18];
8113
8114         u8         retransmission_request_admin[0x8];
8115         u8         fec_mode_request_admin[0x18];
8116
8117         u8         reserved_5[0x80];
8118 };
8119
8120 struct mlx5_ifc_pll_status_data_bits {
8121         u8         reserved_0[0x1];
8122         u8         lock_cal[0x1];
8123         u8         lock_status[0x2];
8124         u8         reserved_1[0x2];
8125         u8         algo_f_ctrl[0xa];
8126         u8         analog_algo_num_var[0x6];
8127         u8         f_ctrl_measure[0xa];
8128
8129         u8         reserved_2[0x2];
8130         u8         analog_var[0x6];
8131         u8         reserved_3[0x2];
8132         u8         high_var[0x6];
8133         u8         reserved_4[0x2];
8134         u8         low_var[0x6];
8135         u8         reserved_5[0x2];
8136         u8         mid_val[0x6];
8137 };
8138
8139 struct mlx5_ifc_plib_reg_bits {
8140         u8         reserved_0[0x8];
8141         u8         local_port[0x8];
8142         u8         reserved_1[0x8];
8143         u8         ib_port[0x8];
8144
8145         u8         reserved_2[0x60];
8146 };
8147
8148 struct mlx5_ifc_plbf_reg_bits {
8149         u8         reserved_0[0x8];
8150         u8         local_port[0x8];
8151         u8         reserved_1[0xd];
8152         u8         lbf_mode[0x3];
8153
8154         u8         reserved_2[0x20];
8155 };
8156
8157 struct mlx5_ifc_pipg_reg_bits {
8158         u8         reserved_0[0x8];
8159         u8         local_port[0x8];
8160         u8         reserved_1[0x10];
8161
8162         u8         dic[0x1];
8163         u8         reserved_2[0x19];
8164         u8         ipg[0x4];
8165         u8         reserved_3[0x2];
8166 };
8167
8168 struct mlx5_ifc_pifr_reg_bits {
8169         u8         reserved_0[0x8];
8170         u8         local_port[0x8];
8171         u8         reserved_1[0x10];
8172
8173         u8         reserved_2[0xe0];
8174
8175         u8         port_filter[8][0x20];
8176
8177         u8         port_filter_update_en[8][0x20];
8178 };
8179
8180 struct mlx5_ifc_phys_layer_cntrs_bits {
8181         u8         time_since_last_clear_high[0x20];
8182
8183         u8         time_since_last_clear_low[0x20];
8184
8185         u8         symbol_errors_high[0x20];
8186
8187         u8         symbol_errors_low[0x20];
8188
8189         u8         sync_headers_errors_high[0x20];
8190
8191         u8         sync_headers_errors_low[0x20];
8192
8193         u8         edpl_bip_errors_lane0_high[0x20];
8194
8195         u8         edpl_bip_errors_lane0_low[0x20];
8196
8197         u8         edpl_bip_errors_lane1_high[0x20];
8198
8199         u8         edpl_bip_errors_lane1_low[0x20];
8200
8201         u8         edpl_bip_errors_lane2_high[0x20];
8202
8203         u8         edpl_bip_errors_lane2_low[0x20];
8204
8205         u8         edpl_bip_errors_lane3_high[0x20];
8206
8207         u8         edpl_bip_errors_lane3_low[0x20];
8208
8209         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8210
8211         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8212
8213         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8214
8215         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8216
8217         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8218
8219         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8220
8221         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8222
8223         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8224
8225         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8226
8227         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8228
8229         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8230
8231         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8232
8233         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8234
8235         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8236
8237         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8238
8239         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8240
8241         u8         rs_fec_corrected_blocks_high[0x20];
8242
8243         u8         rs_fec_corrected_blocks_low[0x20];
8244
8245         u8         rs_fec_uncorrectable_blocks_high[0x20];
8246
8247         u8         rs_fec_uncorrectable_blocks_low[0x20];
8248
8249         u8         rs_fec_no_errors_blocks_high[0x20];
8250
8251         u8         rs_fec_no_errors_blocks_low[0x20];
8252
8253         u8         rs_fec_single_error_blocks_high[0x20];
8254
8255         u8         rs_fec_single_error_blocks_low[0x20];
8256
8257         u8         rs_fec_corrected_symbols_total_high[0x20];
8258
8259         u8         rs_fec_corrected_symbols_total_low[0x20];
8260
8261         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8262
8263         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8264
8265         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8266
8267         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8268
8269         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8270
8271         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8272
8273         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8274
8275         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8276
8277         u8         link_down_events[0x20];
8278
8279         u8         successful_recovery_events[0x20];
8280
8281         u8         reserved_0[0x180];
8282 };
8283
8284 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8285         u8         symbol_error_counter[0x10];
8286
8287         u8         link_error_recovery_counter[0x8];
8288
8289         u8         link_downed_counter[0x8];
8290
8291         u8         port_rcv_errors[0x10];
8292
8293         u8         port_rcv_remote_physical_errors[0x10];
8294
8295         u8         port_rcv_switch_relay_errors[0x10];
8296
8297         u8         port_xmit_discards[0x10];
8298
8299         u8         port_xmit_constraint_errors[0x8];
8300
8301         u8         port_rcv_constraint_errors[0x8];
8302
8303         u8         reserved_at_70[0x8];
8304
8305         u8         link_overrun_errors[0x8];
8306
8307         u8         reserved_at_80[0x10];
8308
8309         u8         vl_15_dropped[0x10];
8310
8311         u8         reserved_at_a0[0xa0];
8312 };
8313
8314 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8315         u8         time_since_last_clear_high[0x20];
8316
8317         u8         time_since_last_clear_low[0x20];
8318
8319         u8         phy_received_bits_high[0x20];
8320
8321         u8         phy_received_bits_low[0x20];
8322
8323         u8         phy_symbol_errors_high[0x20];
8324
8325         u8         phy_symbol_errors_low[0x20];
8326
8327         u8         phy_corrected_bits_high[0x20];
8328
8329         u8         phy_corrected_bits_low[0x20];
8330
8331         u8         phy_corrected_bits_lane0_high[0x20];
8332
8333         u8         phy_corrected_bits_lane0_low[0x20];
8334
8335         u8         phy_corrected_bits_lane1_high[0x20];
8336
8337         u8         phy_corrected_bits_lane1_low[0x20];
8338
8339         u8         phy_corrected_bits_lane2_high[0x20];
8340
8341         u8         phy_corrected_bits_lane2_low[0x20];
8342
8343         u8         phy_corrected_bits_lane3_high[0x20];
8344
8345         u8         phy_corrected_bits_lane3_low[0x20];
8346
8347         u8         reserved_at_200[0x5c0];
8348 };
8349
8350 struct mlx5_ifc_infiniband_port_cntrs_bits {
8351         u8         symbol_error_counter[0x10];
8352         u8         link_error_recovery_counter[0x8];
8353         u8         link_downed_counter[0x8];
8354
8355         u8         port_rcv_errors[0x10];
8356         u8         port_rcv_remote_physical_errors[0x10];
8357
8358         u8         port_rcv_switch_relay_errors[0x10];
8359         u8         port_xmit_discards[0x10];
8360
8361         u8         port_xmit_constraint_errors[0x8];
8362         u8         port_rcv_constraint_errors[0x8];
8363         u8         reserved_0[0x8];
8364         u8         local_link_integrity_errors[0x4];
8365         u8         excessive_buffer_overrun_errors[0x4];
8366
8367         u8         reserved_1[0x10];
8368         u8         vl_15_dropped[0x10];
8369
8370         u8         port_xmit_data[0x20];
8371
8372         u8         port_rcv_data[0x20];
8373
8374         u8         port_xmit_pkts[0x20];
8375
8376         u8         port_rcv_pkts[0x20];
8377
8378         u8         port_xmit_wait[0x20];
8379
8380         u8         reserved_2[0x680];
8381 };
8382
8383 struct mlx5_ifc_phrr_reg_bits {
8384         u8         clr[0x1];
8385         u8         reserved_0[0x7];
8386         u8         local_port[0x8];
8387         u8         reserved_1[0x10];
8388
8389         u8         hist_group[0x8];
8390         u8         reserved_2[0x10];
8391         u8         hist_id[0x8];
8392
8393         u8         reserved_3[0x40];
8394
8395         u8         time_since_last_clear_high[0x20];
8396
8397         u8         time_since_last_clear_low[0x20];
8398
8399         u8         bin[10][0x20];
8400 };
8401
8402 struct mlx5_ifc_phbr_for_prio_reg_bits {
8403         u8         reserved_0[0x18];
8404         u8         prio[0x8];
8405 };
8406
8407 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8408         u8         reserved_0[0x18];
8409         u8         tclass[0x8];
8410 };
8411
8412 struct mlx5_ifc_phbr_binding_reg_bits {
8413         u8         opcode[0x4];
8414         u8         reserved_0[0x4];
8415         u8         local_port[0x8];
8416         u8         pnat[0x2];
8417         u8         reserved_1[0xe];
8418
8419         u8         hist_group[0x8];
8420         u8         reserved_2[0x10];
8421         u8         hist_id[0x8];
8422
8423         u8         reserved_3[0x10];
8424         u8         hist_type[0x10];
8425
8426         u8         hist_parameters[0x20];
8427
8428         u8         hist_min_value[0x20];
8429
8430         u8         hist_max_value[0x20];
8431
8432         u8         sample_time[0x20];
8433 };
8434
8435 enum {
8436         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8437         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8438 };
8439
8440 struct mlx5_ifc_pfcc_reg_bits {
8441         u8         dcbx_operation_type[0x2];
8442         u8         cap_local_admin[0x1];
8443         u8         cap_remote_admin[0x1];
8444         u8         reserved_0[0x4];
8445         u8         local_port[0x8];
8446         u8         pnat[0x2];
8447         u8         reserved_1[0xc];
8448         u8         shl_cap[0x1];
8449         u8         shl_opr[0x1];
8450
8451         u8         ppan[0x4];
8452         u8         reserved_2[0x4];
8453         u8         prio_mask_tx[0x8];
8454         u8         reserved_3[0x8];
8455         u8         prio_mask_rx[0x8];
8456
8457         u8         pptx[0x1];
8458         u8         aptx[0x1];
8459         u8         reserved_4[0x6];
8460         u8         pfctx[0x8];
8461         u8         reserved_5[0x8];
8462         u8         cbftx[0x8];
8463
8464         u8         pprx[0x1];
8465         u8         aprx[0x1];
8466         u8         reserved_6[0x6];
8467         u8         pfcrx[0x8];
8468         u8         reserved_7[0x8];
8469         u8         cbfrx[0x8];
8470
8471         u8         device_stall_minor_watermark[0x10];
8472         u8         device_stall_critical_watermark[0x10];
8473
8474         u8         reserved_8[0x60];
8475 };
8476
8477 struct mlx5_ifc_pelc_reg_bits {
8478         u8         op[0x4];
8479         u8         reserved_0[0x4];
8480         u8         local_port[0x8];
8481         u8         reserved_1[0x10];
8482
8483         u8         op_admin[0x8];
8484         u8         op_capability[0x8];
8485         u8         op_request[0x8];
8486         u8         op_active[0x8];
8487
8488         u8         admin[0x40];
8489
8490         u8         capability[0x40];
8491
8492         u8         request[0x40];
8493
8494         u8         active[0x40];
8495
8496         u8         reserved_2[0x80];
8497 };
8498
8499 struct mlx5_ifc_peir_reg_bits {
8500         u8         reserved_0[0x8];
8501         u8         local_port[0x8];
8502         u8         reserved_1[0x10];
8503
8504         u8         reserved_2[0xc];
8505         u8         error_count[0x4];
8506         u8         reserved_3[0x10];
8507
8508         u8         reserved_4[0xc];
8509         u8         lane[0x4];
8510         u8         reserved_5[0x8];
8511         u8         error_type[0x8];
8512 };
8513
8514 struct mlx5_ifc_qcam_access_reg_cap_mask {
8515         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8516         u8         qpdpm[0x1];
8517         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8518         u8         qdpm[0x1];
8519         u8         qpts[0x1];
8520         u8         qcap[0x1];
8521         u8         qcam_access_reg_cap_mask_0[0x1];
8522 };
8523
8524 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8525         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8526         u8         qpts_trust_both[0x1];
8527 };
8528
8529 struct mlx5_ifc_qcam_reg_bits {
8530         u8         reserved_at_0[0x8];
8531         u8         feature_group[0x8];
8532         u8         reserved_at_10[0x8];
8533         u8         access_reg_group[0x8];
8534         u8         reserved_at_20[0x20];
8535
8536         union {
8537                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8538                 u8  reserved_at_0[0x80];
8539         } qos_access_reg_cap_mask;
8540
8541         u8         reserved_at_c0[0x80];
8542
8543         union {
8544                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8545                 u8  reserved_at_0[0x80];
8546         } qos_feature_cap_mask;
8547
8548         u8         reserved_at_1c0[0x80];
8549 };
8550
8551 struct mlx5_ifc_pcap_reg_bits {
8552         u8         reserved_0[0x8];
8553         u8         local_port[0x8];
8554         u8         reserved_1[0x10];
8555
8556         u8         port_capability_mask[4][0x20];
8557 };
8558
8559 struct mlx5_ifc_pbmc_reg_bits {
8560         u8         reserved_0[0x8];
8561         u8         local_port[0x8];
8562         u8         reserved_1[0x10];
8563
8564         u8         xoff_timer_value[0x10];
8565         u8         xoff_refresh[0x10];
8566
8567         u8         reserved_2[0x10];
8568         u8         port_buffer_size[0x10];
8569
8570         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8571
8572         u8         reserved_3[0x40];
8573
8574         u8         port_shared_buffer[0x40];
8575 };
8576
8577 struct mlx5_ifc_paos_reg_bits {
8578         u8         swid[0x8];
8579         u8         local_port[0x8];
8580         u8         reserved_0[0x4];
8581         u8         admin_status[0x4];
8582         u8         reserved_1[0x4];
8583         u8         oper_status[0x4];
8584
8585         u8         ase[0x1];
8586         u8         ee[0x1];
8587         u8         reserved_2[0x1c];
8588         u8         e[0x2];
8589
8590         u8         reserved_3[0x40];
8591 };
8592
8593 struct mlx5_ifc_pamp_reg_bits {
8594         u8         reserved_0[0x8];
8595         u8         opamp_group[0x8];
8596         u8         reserved_1[0xc];
8597         u8         opamp_group_type[0x4];
8598
8599         u8         start_index[0x10];
8600         u8         reserved_2[0x4];
8601         u8         num_of_indices[0xc];
8602
8603         u8         index_data[18][0x10];
8604 };
8605
8606 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8607         u8         llr_rx_cells_high[0x20];
8608
8609         u8         llr_rx_cells_low[0x20];
8610
8611         u8         llr_rx_error_high[0x20];
8612
8613         u8         llr_rx_error_low[0x20];
8614
8615         u8         llr_rx_crc_error_high[0x20];
8616
8617         u8         llr_rx_crc_error_low[0x20];
8618
8619         u8         llr_tx_cells_high[0x20];
8620
8621         u8         llr_tx_cells_low[0x20];
8622
8623         u8         llr_tx_ret_cells_high[0x20];
8624
8625         u8         llr_tx_ret_cells_low[0x20];
8626
8627         u8         llr_tx_ret_events_high[0x20];
8628
8629         u8         llr_tx_ret_events_low[0x20];
8630
8631         u8         reserved_0[0x640];
8632 };
8633
8634 struct mlx5_ifc_mtmp_reg_bits {
8635         u8         i[0x1];
8636         u8         reserved_at_1[0x18];
8637         u8         sensor_index[0x7];
8638
8639         u8         reserved_at_20[0x10];
8640         u8         temperature[0x10];
8641
8642         u8         mte[0x1];
8643         u8         mtr[0x1];
8644         u8         reserved_at_42[0x0e];
8645         u8         max_temperature[0x10];
8646
8647         u8         tee[0x2];
8648         u8         reserved_at_62[0x0e];
8649         u8         temperature_threshold_hi[0x10];
8650
8651         u8         reserved_at_80[0x10];
8652         u8         temperature_threshold_lo[0x10];
8653
8654         u8         reserved_at_100[0x20];
8655
8656         u8         sensor_name[0x40];
8657 };
8658
8659 struct mlx5_ifc_lane_2_module_mapping_bits {
8660         u8         reserved_0[0x6];
8661         u8         rx_lane[0x2];
8662         u8         reserved_1[0x6];
8663         u8         tx_lane[0x2];
8664         u8         reserved_2[0x8];
8665         u8         module[0x8];
8666 };
8667
8668 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8669         u8         transmit_queue_high[0x20];
8670
8671         u8         transmit_queue_low[0x20];
8672
8673         u8         reserved_0[0x780];
8674 };
8675
8676 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8677         u8         no_buffer_discard_uc_high[0x20];
8678
8679         u8         no_buffer_discard_uc_low[0x20];
8680
8681         u8         wred_discard_high[0x20];
8682
8683         u8         wred_discard_low[0x20];
8684
8685         u8         reserved_0[0x740];
8686 };
8687
8688 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8689         u8         rx_octets_high[0x20];
8690
8691         u8         rx_octets_low[0x20];
8692
8693         u8         reserved_0[0xc0];
8694
8695         u8         rx_frames_high[0x20];
8696
8697         u8         rx_frames_low[0x20];
8698
8699         u8         tx_octets_high[0x20];
8700
8701         u8         tx_octets_low[0x20];
8702
8703         u8         reserved_1[0xc0];
8704
8705         u8         tx_frames_high[0x20];
8706
8707         u8         tx_frames_low[0x20];
8708
8709         u8         rx_pause_high[0x20];
8710
8711         u8         rx_pause_low[0x20];
8712
8713         u8         rx_pause_duration_high[0x20];
8714
8715         u8         rx_pause_duration_low[0x20];
8716
8717         u8         tx_pause_high[0x20];
8718
8719         u8         tx_pause_low[0x20];
8720
8721         u8         tx_pause_duration_high[0x20];
8722
8723         u8         tx_pause_duration_low[0x20];
8724
8725         u8         rx_pause_transition_high[0x20];
8726
8727         u8         rx_pause_transition_low[0x20];
8728
8729         u8         rx_discards_high[0x20];
8730
8731         u8         rx_discards_low[0x20];
8732
8733         u8         device_stall_minor_watermark_cnt_high[0x20];
8734
8735         u8         device_stall_minor_watermark_cnt_low[0x20];
8736
8737         u8         device_stall_critical_watermark_cnt_high[0x20];
8738
8739         u8         device_stall_critical_watermark_cnt_low[0x20];
8740
8741         u8         reserved_2[0x340];
8742 };
8743
8744 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8745         u8         port_transmit_wait_high[0x20];
8746
8747         u8         port_transmit_wait_low[0x20];
8748
8749         u8         ecn_marked_high[0x20];
8750
8751         u8         ecn_marked_low[0x20];
8752
8753         u8         no_buffer_discard_mc_high[0x20];
8754
8755         u8         no_buffer_discard_mc_low[0x20];
8756
8757         u8         rx_ebp_high[0x20];
8758
8759         u8         rx_ebp_low[0x20];
8760
8761         u8         tx_ebp_high[0x20];
8762
8763         u8         tx_ebp_low[0x20];
8764
8765         u8         rx_buffer_almost_full_high[0x20];
8766
8767         u8         rx_buffer_almost_full_low[0x20];
8768
8769         u8         rx_buffer_full_high[0x20];
8770
8771         u8         rx_buffer_full_low[0x20];
8772
8773         u8         rx_icrc_encapsulated_high[0x20];
8774
8775         u8         rx_icrc_encapsulated_low[0x20];
8776
8777         u8         reserved_0[0x80];
8778
8779         u8         tx_stats_pkts64octets_high[0x20];
8780
8781         u8         tx_stats_pkts64octets_low[0x20];
8782
8783         u8         tx_stats_pkts65to127octets_high[0x20];
8784
8785         u8         tx_stats_pkts65to127octets_low[0x20];
8786
8787         u8         tx_stats_pkts128to255octets_high[0x20];
8788
8789         u8         tx_stats_pkts128to255octets_low[0x20];
8790
8791         u8         tx_stats_pkts256to511octets_high[0x20];
8792
8793         u8         tx_stats_pkts256to511octets_low[0x20];
8794
8795         u8         tx_stats_pkts512to1023octets_high[0x20];
8796
8797         u8         tx_stats_pkts512to1023octets_low[0x20];
8798
8799         u8         tx_stats_pkts1024to1518octets_high[0x20];
8800
8801         u8         tx_stats_pkts1024to1518octets_low[0x20];
8802
8803         u8         tx_stats_pkts1519to2047octets_high[0x20];
8804
8805         u8         tx_stats_pkts1519to2047octets_low[0x20];
8806
8807         u8         tx_stats_pkts2048to4095octets_high[0x20];
8808
8809         u8         tx_stats_pkts2048to4095octets_low[0x20];
8810
8811         u8         tx_stats_pkts4096to8191octets_high[0x20];
8812
8813         u8         tx_stats_pkts4096to8191octets_low[0x20];
8814
8815         u8         tx_stats_pkts8192to10239octets_high[0x20];
8816
8817         u8         tx_stats_pkts8192to10239octets_low[0x20];
8818
8819         u8         reserved_1[0x2C0];
8820 };
8821
8822 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8823         u8         a_frames_transmitted_ok_high[0x20];
8824
8825         u8         a_frames_transmitted_ok_low[0x20];
8826
8827         u8         a_frames_received_ok_high[0x20];
8828
8829         u8         a_frames_received_ok_low[0x20];
8830
8831         u8         a_frame_check_sequence_errors_high[0x20];
8832
8833         u8         a_frame_check_sequence_errors_low[0x20];
8834
8835         u8         a_alignment_errors_high[0x20];
8836
8837         u8         a_alignment_errors_low[0x20];
8838
8839         u8         a_octets_transmitted_ok_high[0x20];
8840
8841         u8         a_octets_transmitted_ok_low[0x20];
8842
8843         u8         a_octets_received_ok_high[0x20];
8844
8845         u8         a_octets_received_ok_low[0x20];
8846
8847         u8         a_multicast_frames_xmitted_ok_high[0x20];
8848
8849         u8         a_multicast_frames_xmitted_ok_low[0x20];
8850
8851         u8         a_broadcast_frames_xmitted_ok_high[0x20];
8852
8853         u8         a_broadcast_frames_xmitted_ok_low[0x20];
8854
8855         u8         a_multicast_frames_received_ok_high[0x20];
8856
8857         u8         a_multicast_frames_received_ok_low[0x20];
8858
8859         u8         a_broadcast_frames_recieved_ok_high[0x20];
8860
8861         u8         a_broadcast_frames_recieved_ok_low[0x20];
8862
8863         u8         a_in_range_length_errors_high[0x20];
8864
8865         u8         a_in_range_length_errors_low[0x20];
8866
8867         u8         a_out_of_range_length_field_high[0x20];
8868
8869         u8         a_out_of_range_length_field_low[0x20];
8870
8871         u8         a_frame_too_long_errors_high[0x20];
8872
8873         u8         a_frame_too_long_errors_low[0x20];
8874
8875         u8         a_symbol_error_during_carrier_high[0x20];
8876
8877         u8         a_symbol_error_during_carrier_low[0x20];
8878
8879         u8         a_mac_control_frames_transmitted_high[0x20];
8880
8881         u8         a_mac_control_frames_transmitted_low[0x20];
8882
8883         u8         a_mac_control_frames_received_high[0x20];
8884
8885         u8         a_mac_control_frames_received_low[0x20];
8886
8887         u8         a_unsupported_opcodes_received_high[0x20];
8888
8889         u8         a_unsupported_opcodes_received_low[0x20];
8890
8891         u8         a_pause_mac_ctrl_frames_received_high[0x20];
8892
8893         u8         a_pause_mac_ctrl_frames_received_low[0x20];
8894
8895         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8896
8897         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8898
8899         u8         reserved_0[0x300];
8900 };
8901
8902 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8903         u8         dot3stats_alignment_errors_high[0x20];
8904
8905         u8         dot3stats_alignment_errors_low[0x20];
8906
8907         u8         dot3stats_fcs_errors_high[0x20];
8908
8909         u8         dot3stats_fcs_errors_low[0x20];
8910
8911         u8         dot3stats_single_collision_frames_high[0x20];
8912
8913         u8         dot3stats_single_collision_frames_low[0x20];
8914
8915         u8         dot3stats_multiple_collision_frames_high[0x20];
8916
8917         u8         dot3stats_multiple_collision_frames_low[0x20];
8918
8919         u8         dot3stats_sqe_test_errors_high[0x20];
8920
8921         u8         dot3stats_sqe_test_errors_low[0x20];
8922
8923         u8         dot3stats_deferred_transmissions_high[0x20];
8924
8925         u8         dot3stats_deferred_transmissions_low[0x20];
8926
8927         u8         dot3stats_late_collisions_high[0x20];
8928
8929         u8         dot3stats_late_collisions_low[0x20];
8930
8931         u8         dot3stats_excessive_collisions_high[0x20];
8932
8933         u8         dot3stats_excessive_collisions_low[0x20];
8934
8935         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8936
8937         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8938
8939         u8         dot3stats_carrier_sense_errors_high[0x20];
8940
8941         u8         dot3stats_carrier_sense_errors_low[0x20];
8942
8943         u8         dot3stats_frame_too_longs_high[0x20];
8944
8945         u8         dot3stats_frame_too_longs_low[0x20];
8946
8947         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8948
8949         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8950
8951         u8         dot3stats_symbol_errors_high[0x20];
8952
8953         u8         dot3stats_symbol_errors_low[0x20];
8954
8955         u8         dot3control_in_unknown_opcodes_high[0x20];
8956
8957         u8         dot3control_in_unknown_opcodes_low[0x20];
8958
8959         u8         dot3in_pause_frames_high[0x20];
8960
8961         u8         dot3in_pause_frames_low[0x20];
8962
8963         u8         dot3out_pause_frames_high[0x20];
8964
8965         u8         dot3out_pause_frames_low[0x20];
8966
8967         u8         reserved_0[0x3c0];
8968 };
8969
8970 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8971         u8         if_in_octets_high[0x20];
8972
8973         u8         if_in_octets_low[0x20];
8974
8975         u8         if_in_ucast_pkts_high[0x20];
8976
8977         u8         if_in_ucast_pkts_low[0x20];
8978
8979         u8         if_in_discards_high[0x20];
8980
8981         u8         if_in_discards_low[0x20];
8982
8983         u8         if_in_errors_high[0x20];
8984
8985         u8         if_in_errors_low[0x20];
8986
8987         u8         if_in_unknown_protos_high[0x20];
8988
8989         u8         if_in_unknown_protos_low[0x20];
8990
8991         u8         if_out_octets_high[0x20];
8992
8993         u8         if_out_octets_low[0x20];
8994
8995         u8         if_out_ucast_pkts_high[0x20];
8996
8997         u8         if_out_ucast_pkts_low[0x20];
8998
8999         u8         if_out_discards_high[0x20];
9000
9001         u8         if_out_discards_low[0x20];
9002
9003         u8         if_out_errors_high[0x20];
9004
9005         u8         if_out_errors_low[0x20];
9006
9007         u8         if_in_multicast_pkts_high[0x20];
9008
9009         u8         if_in_multicast_pkts_low[0x20];
9010
9011         u8         if_in_broadcast_pkts_high[0x20];
9012
9013         u8         if_in_broadcast_pkts_low[0x20];
9014
9015         u8         if_out_multicast_pkts_high[0x20];
9016
9017         u8         if_out_multicast_pkts_low[0x20];
9018
9019         u8         if_out_broadcast_pkts_high[0x20];
9020
9021         u8         if_out_broadcast_pkts_low[0x20];
9022
9023         u8         reserved_0[0x480];
9024 };
9025
9026 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9027         u8         ether_stats_drop_events_high[0x20];
9028
9029         u8         ether_stats_drop_events_low[0x20];
9030
9031         u8         ether_stats_octets_high[0x20];
9032
9033         u8         ether_stats_octets_low[0x20];
9034
9035         u8         ether_stats_pkts_high[0x20];
9036
9037         u8         ether_stats_pkts_low[0x20];
9038
9039         u8         ether_stats_broadcast_pkts_high[0x20];
9040
9041         u8         ether_stats_broadcast_pkts_low[0x20];
9042
9043         u8         ether_stats_multicast_pkts_high[0x20];
9044
9045         u8         ether_stats_multicast_pkts_low[0x20];
9046
9047         u8         ether_stats_crc_align_errors_high[0x20];
9048
9049         u8         ether_stats_crc_align_errors_low[0x20];
9050
9051         u8         ether_stats_undersize_pkts_high[0x20];
9052
9053         u8         ether_stats_undersize_pkts_low[0x20];
9054
9055         u8         ether_stats_oversize_pkts_high[0x20];
9056
9057         u8         ether_stats_oversize_pkts_low[0x20];
9058
9059         u8         ether_stats_fragments_high[0x20];
9060
9061         u8         ether_stats_fragments_low[0x20];
9062
9063         u8         ether_stats_jabbers_high[0x20];
9064
9065         u8         ether_stats_jabbers_low[0x20];
9066
9067         u8         ether_stats_collisions_high[0x20];
9068
9069         u8         ether_stats_collisions_low[0x20];
9070
9071         u8         ether_stats_pkts64octets_high[0x20];
9072
9073         u8         ether_stats_pkts64octets_low[0x20];
9074
9075         u8         ether_stats_pkts65to127octets_high[0x20];
9076
9077         u8         ether_stats_pkts65to127octets_low[0x20];
9078
9079         u8         ether_stats_pkts128to255octets_high[0x20];
9080
9081         u8         ether_stats_pkts128to255octets_low[0x20];
9082
9083         u8         ether_stats_pkts256to511octets_high[0x20];
9084
9085         u8         ether_stats_pkts256to511octets_low[0x20];
9086
9087         u8         ether_stats_pkts512to1023octets_high[0x20];
9088
9089         u8         ether_stats_pkts512to1023octets_low[0x20];
9090
9091         u8         ether_stats_pkts1024to1518octets_high[0x20];
9092
9093         u8         ether_stats_pkts1024to1518octets_low[0x20];
9094
9095         u8         ether_stats_pkts1519to2047octets_high[0x20];
9096
9097         u8         ether_stats_pkts1519to2047octets_low[0x20];
9098
9099         u8         ether_stats_pkts2048to4095octets_high[0x20];
9100
9101         u8         ether_stats_pkts2048to4095octets_low[0x20];
9102
9103         u8         ether_stats_pkts4096to8191octets_high[0x20];
9104
9105         u8         ether_stats_pkts4096to8191octets_low[0x20];
9106
9107         u8         ether_stats_pkts8192to10239octets_high[0x20];
9108
9109         u8         ether_stats_pkts8192to10239octets_low[0x20];
9110
9111         u8         reserved_0[0x280];
9112 };
9113
9114 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9115         u8         symbol_error_counter[0x10];
9116         u8         link_error_recovery_counter[0x8];
9117         u8         link_downed_counter[0x8];
9118
9119         u8         port_rcv_errors[0x10];
9120         u8         port_rcv_remote_physical_errors[0x10];
9121
9122         u8         port_rcv_switch_relay_errors[0x10];
9123         u8         port_xmit_discards[0x10];
9124
9125         u8         port_xmit_constraint_errors[0x8];
9126         u8         port_rcv_constraint_errors[0x8];
9127         u8         reserved_0[0x8];
9128         u8         local_link_integrity_errors[0x4];
9129         u8         excessive_buffer_overrun_errors[0x4];
9130
9131         u8         reserved_1[0x10];
9132         u8         vl_15_dropped[0x10];
9133
9134         u8         port_xmit_data[0x20];
9135
9136         u8         port_rcv_data[0x20];
9137
9138         u8         port_xmit_pkts[0x20];
9139
9140         u8         port_rcv_pkts[0x20];
9141
9142         u8         port_xmit_wait[0x20];
9143
9144         u8         reserved_2[0x680];
9145 };
9146
9147 struct mlx5_ifc_trc_tlb_reg_bits {
9148         u8         reserved_0[0x80];
9149
9150         u8         tlb_addr[0][0x40];
9151 };
9152
9153 struct mlx5_ifc_trc_read_fifo_reg_bits {
9154         u8         reserved_0[0x10];
9155         u8         requested_event_num[0x10];
9156
9157         u8         reserved_1[0x20];
9158
9159         u8         reserved_2[0x10];
9160         u8         acual_event_num[0x10];
9161
9162         u8         reserved_3[0x20];
9163
9164         u8         event[0][0x40];
9165 };
9166
9167 struct mlx5_ifc_trc_lock_reg_bits {
9168         u8         reserved_0[0x1f];
9169         u8         lock[0x1];
9170
9171         u8         reserved_1[0x60];
9172 };
9173
9174 struct mlx5_ifc_trc_filter_reg_bits {
9175         u8         status[0x1];
9176         u8         reserved_0[0xf];
9177         u8         filter_index[0x10];
9178
9179         u8         reserved_1[0x20];
9180
9181         u8         filter_val[0x20];
9182
9183         u8         reserved_2[0x1a0];
9184 };
9185
9186 struct mlx5_ifc_trc_event_reg_bits {
9187         u8         status[0x1];
9188         u8         reserved_0[0xf];
9189         u8         event_index[0x10];
9190
9191         u8         reserved_1[0x20];
9192
9193         u8         event_id[0x20];
9194
9195         u8         event_selector_val[0x10];
9196         u8         event_selector_size[0x10];
9197
9198         u8         reserved_2[0x180];
9199 };
9200
9201 struct mlx5_ifc_trc_conf_reg_bits {
9202         u8         limit_en[0x1];
9203         u8         reserved_0[0x3];
9204         u8         dump_mode[0x4];
9205         u8         reserved_1[0x15];
9206         u8         state[0x3];
9207
9208         u8         reserved_2[0x20];
9209
9210         u8         limit_event_index[0x20];
9211
9212         u8         mkey[0x20];
9213
9214         u8         fifo_ready_ev_num[0x20];
9215
9216         u8         reserved_3[0x160];
9217 };
9218
9219 struct mlx5_ifc_trc_cap_reg_bits {
9220         u8         reserved_0[0x18];
9221         u8         dump_mode[0x8];
9222
9223         u8         reserved_1[0x20];
9224
9225         u8         num_of_events[0x10];
9226         u8         num_of_filters[0x10];
9227
9228         u8         fifo_size[0x20];
9229
9230         u8         tlb_size[0x10];
9231         u8         event_size[0x10];
9232
9233         u8         reserved_2[0x160];
9234 };
9235
9236 struct mlx5_ifc_set_node_in_bits {
9237         u8         node_description[64][0x8];
9238 };
9239
9240 struct mlx5_ifc_register_power_settings_bits {
9241         u8         reserved_0[0x18];
9242         u8         power_settings_level[0x8];
9243
9244         u8         reserved_1[0x60];
9245 };
9246
9247 struct mlx5_ifc_register_host_endianess_bits {
9248         u8         he[0x1];
9249         u8         reserved_0[0x1f];
9250
9251         u8         reserved_1[0x60];
9252 };
9253
9254 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9255         u8         physical_address[0x40];
9256 };
9257
9258 struct mlx5_ifc_qtct_reg_bits {
9259         u8         operation_type[0x2];
9260         u8         cap_local_admin[0x1];
9261         u8         cap_remote_admin[0x1];
9262         u8         reserved_0[0x4];
9263         u8         port_number[0x8];
9264         u8         reserved_1[0xd];
9265         u8         prio[0x3];
9266
9267         u8         reserved_2[0x1d];
9268         u8         tclass[0x3];
9269 };
9270
9271 struct mlx5_ifc_qpdp_reg_bits {
9272         u8         reserved_0[0x8];
9273         u8         port_number[0x8];
9274         u8         reserved_1[0x10];
9275
9276         u8         reserved_2[0x1d];
9277         u8         pprio[0x3];
9278 };
9279
9280 struct mlx5_ifc_port_info_ro_fields_param_bits {
9281         u8         reserved_0[0x8];
9282         u8         port[0x8];
9283         u8         max_gid[0x10];
9284
9285         u8         reserved_1[0x20];
9286
9287         u8         port_guid[0x40];
9288 };
9289
9290 struct mlx5_ifc_nvqc_reg_bits {
9291         u8         type[0x20];
9292
9293         u8         reserved_0[0x18];
9294         u8         version[0x4];
9295         u8         reserved_1[0x2];
9296         u8         support_wr[0x1];
9297         u8         support_rd[0x1];
9298 };
9299
9300 struct mlx5_ifc_nvia_reg_bits {
9301         u8         reserved_0[0x1d];
9302         u8         target[0x3];
9303
9304         u8         reserved_1[0x20];
9305 };
9306
9307 struct mlx5_ifc_nvdi_reg_bits {
9308         struct mlx5_ifc_config_item_bits configuration_item_header;
9309 };
9310
9311 struct mlx5_ifc_nvda_reg_bits {
9312         struct mlx5_ifc_config_item_bits configuration_item_header;
9313
9314         u8         configuration_item_data[0x20];
9315 };
9316
9317 struct mlx5_ifc_node_info_ro_fields_param_bits {
9318         u8         system_image_guid[0x40];
9319
9320         u8         reserved_0[0x40];
9321
9322         u8         node_guid[0x40];
9323
9324         u8         reserved_1[0x10];
9325         u8         max_pkey[0x10];
9326
9327         u8         reserved_2[0x20];
9328 };
9329
9330 struct mlx5_ifc_ets_tcn_config_reg_bits {
9331         u8         g[0x1];
9332         u8         b[0x1];
9333         u8         r[0x1];
9334         u8         reserved_0[0x9];
9335         u8         group[0x4];
9336         u8         reserved_1[0x9];
9337         u8         bw_allocation[0x7];
9338
9339         u8         reserved_2[0xc];
9340         u8         max_bw_units[0x4];
9341         u8         reserved_3[0x8];
9342         u8         max_bw_value[0x8];
9343 };
9344
9345 struct mlx5_ifc_ets_global_config_reg_bits {
9346         u8         reserved_0[0x2];
9347         u8         r[0x1];
9348         u8         reserved_1[0x1d];
9349
9350         u8         reserved_2[0xc];
9351         u8         max_bw_units[0x4];
9352         u8         reserved_3[0x8];
9353         u8         max_bw_value[0x8];
9354 };
9355
9356 struct mlx5_ifc_qetc_reg_bits {
9357         u8                                         reserved_at_0[0x8];
9358         u8                                         port_number[0x8];
9359         u8                                         reserved_at_10[0x30];
9360
9361         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9362         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9363 };
9364
9365 struct mlx5_ifc_nodnic_mac_filters_bits {
9366         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9367
9368         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9369
9370         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9371
9372         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9373
9374         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9375
9376         u8         reserved_0[0xc0];
9377 };
9378
9379 struct mlx5_ifc_nodnic_gid_filters_bits {
9380         u8         mgid_filter0[16][0x8];
9381
9382         u8         mgid_filter1[16][0x8];
9383
9384         u8         mgid_filter2[16][0x8];
9385
9386         u8         mgid_filter3[16][0x8];
9387 };
9388
9389 enum {
9390         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9391         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9392 };
9393
9394 enum {
9395         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9396         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9397 };
9398
9399 struct mlx5_ifc_nodnic_config_reg_bits {
9400         u8         no_dram_nic_revision[0x8];
9401         u8         hardware_format[0x8];
9402         u8         support_receive_filter[0x1];
9403         u8         support_promisc_filter[0x1];
9404         u8         support_promisc_multicast_filter[0x1];
9405         u8         reserved_0[0x2];
9406         u8         log_working_buffer_size[0x3];
9407         u8         log_pkey_table_size[0x4];
9408         u8         reserved_1[0x3];
9409         u8         num_ports[0x1];
9410
9411         u8         reserved_2[0x2];
9412         u8         log_max_ring_size[0x6];
9413         u8         reserved_3[0x18];
9414
9415         u8         lkey[0x20];
9416
9417         u8         cqe_format[0x4];
9418         u8         reserved_4[0x1c];
9419
9420         u8         node_guid[0x40];
9421
9422         u8         reserved_5[0x740];
9423
9424         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9425
9426         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9427 };
9428
9429 struct mlx5_ifc_vlan_layout_bits {
9430         u8         reserved_0[0x14];
9431         u8         vlan[0xc];
9432
9433         u8         reserved_1[0x20];
9434 };
9435
9436 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9437         u8         reserved_0[0x20];
9438
9439         u8         mkey[0x20];
9440
9441         u8         addressh_63_32[0x20];
9442
9443         u8         addressl_31_0[0x20];
9444 };
9445
9446 struct mlx5_ifc_ud_adrs_vector_bits {
9447         u8         dc_key[0x40];
9448
9449         u8         ext[0x1];
9450         u8         reserved_0[0x7];
9451         u8         destination_qp_dct[0x18];
9452
9453         u8         static_rate[0x4];
9454         u8         sl_eth_prio[0x4];
9455         u8         fl[0x1];
9456         u8         mlid[0x7];
9457         u8         rlid_udp_sport[0x10];
9458
9459         u8         reserved_1[0x20];
9460
9461         u8         rmac_47_16[0x20];
9462
9463         u8         rmac_15_0[0x10];
9464         u8         tclass[0x8];
9465         u8         hop_limit[0x8];
9466
9467         u8         reserved_2[0x1];
9468         u8         grh[0x1];
9469         u8         reserved_3[0x2];
9470         u8         src_addr_index[0x8];
9471         u8         flow_label[0x14];
9472
9473         u8         rgid_rip[16][0x8];
9474 };
9475
9476 struct mlx5_ifc_port_module_event_bits {
9477         u8         reserved_0[0x8];
9478         u8         module[0x8];
9479         u8         reserved_1[0xc];
9480         u8         module_status[0x4];
9481
9482         u8         reserved_2[0x14];
9483         u8         error_type[0x4];
9484         u8         reserved_3[0x8];
9485
9486         u8         reserved_4[0xa0];
9487 };
9488
9489 struct mlx5_ifc_icmd_control_bits {
9490         u8         opcode[0x10];
9491         u8         status[0x8];
9492         u8         reserved_0[0x7];
9493         u8         busy[0x1];
9494 };
9495
9496 struct mlx5_ifc_eqe_bits {
9497         u8         reserved_0[0x8];
9498         u8         event_type[0x8];
9499         u8         reserved_1[0x8];
9500         u8         event_sub_type[0x8];
9501
9502         u8         reserved_2[0xe0];
9503
9504         union mlx5_ifc_event_auto_bits event_data;
9505
9506         u8         reserved_3[0x10];
9507         u8         signature[0x8];
9508         u8         reserved_4[0x7];
9509         u8         owner[0x1];
9510 };
9511
9512 enum {
9513         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9514 };
9515
9516 struct mlx5_ifc_cmd_queue_entry_bits {
9517         u8         type[0x8];
9518         u8         reserved_0[0x18];
9519
9520         u8         input_length[0x20];
9521
9522         u8         input_mailbox_pointer_63_32[0x20];
9523
9524         u8         input_mailbox_pointer_31_9[0x17];
9525         u8         reserved_1[0x9];
9526
9527         u8         command_input_inline_data[16][0x8];
9528
9529         u8         command_output_inline_data[16][0x8];
9530
9531         u8         output_mailbox_pointer_63_32[0x20];
9532
9533         u8         output_mailbox_pointer_31_9[0x17];
9534         u8         reserved_2[0x9];
9535
9536         u8         output_length[0x20];
9537
9538         u8         token[0x8];
9539         u8         signature[0x8];
9540         u8         reserved_3[0x8];
9541         u8         status[0x7];
9542         u8         ownership[0x1];
9543 };
9544
9545 struct mlx5_ifc_cmd_out_bits {
9546         u8         status[0x8];
9547         u8         reserved_0[0x18];
9548
9549         u8         syndrome[0x20];
9550
9551         u8         command_output[0x20];
9552 };
9553
9554 struct mlx5_ifc_cmd_in_bits {
9555         u8         opcode[0x10];
9556         u8         reserved_0[0x10];
9557
9558         u8         reserved_1[0x10];
9559         u8         op_mod[0x10];
9560
9561         u8         command[0][0x20];
9562 };
9563
9564 struct mlx5_ifc_cmd_if_box_bits {
9565         u8         mailbox_data[512][0x8];
9566
9567         u8         reserved_0[0x180];
9568
9569         u8         next_pointer_63_32[0x20];
9570
9571         u8         next_pointer_31_10[0x16];
9572         u8         reserved_1[0xa];
9573
9574         u8         block_number[0x20];
9575
9576         u8         reserved_2[0x8];
9577         u8         token[0x8];
9578         u8         ctrl_signature[0x8];
9579         u8         signature[0x8];
9580 };
9581
9582 struct mlx5_ifc_mtt_bits {
9583         u8         ptag_63_32[0x20];
9584
9585         u8         ptag_31_8[0x18];
9586         u8         reserved_0[0x6];
9587         u8         wr_en[0x1];
9588         u8         rd_en[0x1];
9589 };
9590
9591 /* Vendor Specific Capabilities, VSC */
9592 enum {
9593         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9594         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9595         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9596 };
9597
9598 struct mlx5_ifc_vendor_specific_cap_bits {
9599         u8         type[0x8];
9600         u8         length[0x8];
9601         u8         next_pointer[0x8];
9602         u8         capability_id[0x8];
9603
9604         u8         status[0x3];
9605         u8         reserved_0[0xd];
9606         u8         space[0x10];
9607
9608         u8         counter[0x20];
9609
9610         u8         semaphore[0x20];
9611
9612         u8         flag[0x1];
9613         u8         reserved_1[0x1];
9614         u8         address[0x1e];
9615
9616         u8         data[0x20];
9617 };
9618
9619 enum {
9620         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9621         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9622         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9623 };
9624
9625 enum {
9626         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9627         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9628         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9629 };
9630
9631 enum {
9632         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9633         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9634         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9635         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9636         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9637         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9638         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9639         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9640         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9641         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9642         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9643 };
9644
9645 struct mlx5_ifc_initial_seg_bits {
9646         u8         fw_rev_minor[0x10];
9647         u8         fw_rev_major[0x10];
9648
9649         u8         cmd_interface_rev[0x10];
9650         u8         fw_rev_subminor[0x10];
9651
9652         u8         reserved_0[0x40];
9653
9654         u8         cmdq_phy_addr_63_32[0x20];
9655
9656         u8         cmdq_phy_addr_31_12[0x14];
9657         u8         reserved_1[0x2];
9658         u8         nic_interface[0x2];
9659         u8         log_cmdq_size[0x4];
9660         u8         log_cmdq_stride[0x4];
9661
9662         u8         command_doorbell_vector[0x20];
9663
9664         u8         reserved_2[0xf00];
9665
9666         u8         initializing[0x1];
9667         u8         reserved_3[0x4];
9668         u8         nic_interface_supported[0x3];
9669         u8         reserved_4[0x18];
9670
9671         struct mlx5_ifc_health_buffer_bits health_buffer;
9672
9673         u8         no_dram_nic_offset[0x20];
9674
9675         u8         reserved_5[0x6de0];
9676
9677         u8         internal_timer_h[0x20];
9678
9679         u8         internal_timer_l[0x20];
9680
9681         u8         reserved_6[0x20];
9682
9683         u8         reserved_7[0x1f];
9684         u8         clear_int[0x1];
9685
9686         u8         health_syndrome[0x8];
9687         u8         health_counter[0x18];
9688
9689         u8         reserved_8[0x17fc0];
9690 };
9691
9692 union mlx5_ifc_icmd_interface_document_bits {
9693         struct mlx5_ifc_fw_version_bits fw_version;
9694         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9695         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9696         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9697         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9698         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9699         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9700         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9701         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9702         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9703         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9704         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9705         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9706         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9707         u8         reserved_0[0x42c0];
9708 };
9709
9710 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9711         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9712         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9713         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9714         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9715         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9716         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9717         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9718         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9719         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9720         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9721         u8         reserved_0[0x7c0];
9722 };
9723
9724 struct mlx5_ifc_ppcnt_reg_bits {
9725         u8         swid[0x8];
9726         u8         local_port[0x8];
9727         u8         pnat[0x2];
9728         u8         reserved_0[0x8];
9729         u8         grp[0x6];
9730
9731         u8         clr[0x1];
9732         u8         reserved_1[0x1c];
9733         u8         prio_tc[0x3];
9734
9735         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9736 };
9737
9738 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9739         u8         life_time_counter_high[0x20];
9740
9741         u8         life_time_counter_low[0x20];
9742
9743         u8         rx_errors[0x20];
9744
9745         u8         tx_errors[0x20];
9746
9747         u8         l0_to_recovery_eieos[0x20];
9748
9749         u8         l0_to_recovery_ts[0x20];
9750
9751         u8         l0_to_recovery_framing[0x20];
9752
9753         u8         l0_to_recovery_retrain[0x20];
9754
9755         u8         crc_error_dllp[0x20];
9756
9757         u8         crc_error_tlp[0x20];
9758
9759         u8         reserved_0[0x680];
9760 };
9761
9762 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9763         u8         life_time_counter_high[0x20];
9764
9765         u8         life_time_counter_low[0x20];
9766
9767         u8         time_to_boot_image_start[0x20];
9768
9769         u8         time_to_link_image[0x20];
9770
9771         u8         calibration_time[0x20];
9772
9773         u8         time_to_first_perst[0x20];
9774
9775         u8         time_to_detect_state[0x20];
9776
9777         u8         time_to_l0[0x20];
9778
9779         u8         time_to_crs_en[0x20];
9780
9781         u8         time_to_plastic_image_start[0x20];
9782
9783         u8         time_to_iron_image_start[0x20];
9784
9785         u8         perst_handler[0x20];
9786
9787         u8         times_in_l1[0x20];
9788
9789         u8         times_in_l23[0x20];
9790
9791         u8         dl_down[0x20];
9792
9793         u8         config_cycle1usec[0x20];
9794
9795         u8         config_cycle2to7usec[0x20];
9796
9797         u8         config_cycle8to15usec[0x20];
9798
9799         u8         config_cycle16to63usec[0x20];
9800
9801         u8         config_cycle64usec[0x20];
9802
9803         u8         correctable_err_msg_sent[0x20];
9804
9805         u8         non_fatal_err_msg_sent[0x20];
9806
9807         u8         fatal_err_msg_sent[0x20];
9808
9809         u8         reserved_0[0x4e0];
9810 };
9811
9812 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9813         u8         life_time_counter_high[0x20];
9814
9815         u8         life_time_counter_low[0x20];
9816
9817         u8         error_counter_lane0[0x20];
9818
9819         u8         error_counter_lane1[0x20];
9820
9821         u8         error_counter_lane2[0x20];
9822
9823         u8         error_counter_lane3[0x20];
9824
9825         u8         error_counter_lane4[0x20];
9826
9827         u8         error_counter_lane5[0x20];
9828
9829         u8         error_counter_lane6[0x20];
9830
9831         u8         error_counter_lane7[0x20];
9832
9833         u8         error_counter_lane8[0x20];
9834
9835         u8         error_counter_lane9[0x20];
9836
9837         u8         error_counter_lane10[0x20];
9838
9839         u8         error_counter_lane11[0x20];
9840
9841         u8         error_counter_lane12[0x20];
9842
9843         u8         error_counter_lane13[0x20];
9844
9845         u8         error_counter_lane14[0x20];
9846
9847         u8         error_counter_lane15[0x20];
9848
9849         u8         reserved_0[0x580];
9850 };
9851
9852 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9853         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9854         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9855         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9856         u8         reserved_0[0xf8];
9857 };
9858
9859 struct mlx5_ifc_mpcnt_reg_bits {
9860         u8         reserved_0[0x8];
9861         u8         pcie_index[0x8];
9862         u8         reserved_1[0xa];
9863         u8         grp[0x6];
9864
9865         u8         clr[0x1];
9866         u8         reserved_2[0x1f];
9867
9868         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9869 };
9870
9871 union mlx5_ifc_ports_control_registers_document_bits {
9872         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9873         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9874         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9875         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9876         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9877         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9878         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9879         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9880         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9881         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9882         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9883         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9884         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9885         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9886         struct mlx5_ifc_paos_reg_bits paos_reg;
9887         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9888         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9889         struct mlx5_ifc_peir_reg_bits peir_reg;
9890         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9891         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9892         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9893         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9894         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9895         struct mlx5_ifc_phrr_reg_bits phrr_reg;
9896         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9897         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9898         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9899         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9900         struct mlx5_ifc_plib_reg_bits plib_reg;
9901         struct mlx5_ifc_pll_status_data_bits pll_status_data;
9902         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9903         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9904         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9905         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9906         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9907         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9908         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9909         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9910         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9911         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9912         struct mlx5_ifc_ppll_reg_bits ppll_reg;
9913         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9914         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9915         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9916         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9917         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9918         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9919         struct mlx5_ifc_pude_reg_bits pude_reg;
9920         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9921         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9922         struct mlx5_ifc_slrp_reg_bits slrp_reg;
9923         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9924         u8         reserved_0[0x7880];
9925 };
9926
9927 union mlx5_ifc_debug_enhancements_document_bits {
9928         struct mlx5_ifc_health_buffer_bits health_buffer;
9929         u8         reserved_0[0x200];
9930 };
9931
9932 union mlx5_ifc_no_dram_nic_document_bits {
9933         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9934         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9935         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9936         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9937         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9938         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9939         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9940         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9941         u8         reserved_0[0x3160];
9942 };
9943
9944 union mlx5_ifc_uplink_pci_interface_document_bits {
9945         struct mlx5_ifc_initial_seg_bits initial_seg;
9946         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9947         u8         reserved_0[0x20120];
9948 };
9949
9950 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9951         u8         e[0x1];
9952         u8         reserved_at_01[0x0b];
9953         u8         prio[0x04];
9954 };
9955
9956 struct mlx5_ifc_qpdpm_reg_bits {
9957         u8                                     reserved_at_0[0x8];
9958         u8                                     local_port[0x8];
9959         u8                                     reserved_at_10[0x10];
9960         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9961 };
9962
9963 struct mlx5_ifc_qpts_reg_bits {
9964         u8         reserved_at_0[0x8];
9965         u8         local_port[0x8];
9966         u8         reserved_at_10[0x2d];
9967         u8         trust_state[0x3];
9968 };
9969
9970 #endif /* MLX5_IFC_H */