2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 MLX5_EVENT_TYPE_COMP = 0x0,
33 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
34 MLX5_EVENT_TYPE_COMM_EST = 0x2,
35 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
36 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
37 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
38 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
39 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
40 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
41 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5,
42 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
43 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
44 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
45 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
46 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
47 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8,
48 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9,
49 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
50 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16,
51 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17,
52 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
53 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
54 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
55 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
56 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
57 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
58 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
59 MLX5_EVENT_TYPE_CMD = 0xa,
60 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
61 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd
65 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
66 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
67 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
68 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
69 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4
73 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1,
77 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
78 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
79 MLX5_CMD_OP_INIT_HCA = 0x102,
80 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
81 MLX5_CMD_OP_ENABLE_HCA = 0x104,
82 MLX5_CMD_OP_DISABLE_HCA = 0x105,
83 MLX5_CMD_OP_QUERY_PAGES = 0x107,
84 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
85 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
86 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
87 MLX5_CMD_OP_SET_ISSI = 0x10b,
88 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
89 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
90 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
91 MLX5_CMD_OP_CREATE_MKEY = 0x200,
92 MLX5_CMD_OP_QUERY_MKEY = 0x201,
93 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
94 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
95 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
96 MLX5_CMD_OP_CREATE_EQ = 0x301,
97 MLX5_CMD_OP_DESTROY_EQ = 0x302,
98 MLX5_CMD_OP_QUERY_EQ = 0x303,
99 MLX5_CMD_OP_GEN_EQE = 0x304,
100 MLX5_CMD_OP_CREATE_CQ = 0x400,
101 MLX5_CMD_OP_DESTROY_CQ = 0x401,
102 MLX5_CMD_OP_QUERY_CQ = 0x402,
103 MLX5_CMD_OP_MODIFY_CQ = 0x403,
104 MLX5_CMD_OP_CREATE_QP = 0x500,
105 MLX5_CMD_OP_DESTROY_QP = 0x501,
106 MLX5_CMD_OP_RST2INIT_QP = 0x502,
107 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
108 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
109 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
110 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
111 MLX5_CMD_OP_2ERR_QP = 0x507,
112 MLX5_CMD_OP_2RST_QP = 0x50a,
113 MLX5_CMD_OP_QUERY_QP = 0x50b,
114 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
115 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
116 MLX5_CMD_OP_CREATE_PSV = 0x600,
117 MLX5_CMD_OP_DESTROY_PSV = 0x601,
118 MLX5_CMD_OP_CREATE_SRQ = 0x700,
119 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
120 MLX5_CMD_OP_QUERY_SRQ = 0x702,
121 MLX5_CMD_OP_ARM_RQ = 0x703,
122 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
123 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
124 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
125 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
126 MLX5_CMD_OP_CREATE_DCT = 0x710,
127 MLX5_CMD_OP_DESTROY_DCT = 0x711,
128 MLX5_CMD_OP_DRAIN_DCT = 0x712,
129 MLX5_CMD_OP_QUERY_DCT = 0x713,
130 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
131 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715,
132 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
133 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
134 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
135 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
136 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
137 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
138 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
139 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
140 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
142 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
143 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
145 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
146 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
147 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
148 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
149 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
150 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
151 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
152 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
153 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
154 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
155 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
156 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
157 MLX5_CMD_OP_ALLOC_PD = 0x800,
158 MLX5_CMD_OP_DEALLOC_PD = 0x801,
159 MLX5_CMD_OP_ALLOC_UAR = 0x802,
160 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
161 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
162 MLX5_CMD_OP_ACCESS_REG = 0x805,
163 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
164 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
165 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
166 MLX5_CMD_OP_MAD_IFC = 0x50d,
167 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
168 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
169 MLX5_CMD_OP_NOP = 0x80d,
170 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
171 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
172 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
173 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
174 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
175 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820,
179 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821,
180 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
181 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
182 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
183 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
184 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
185 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
186 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
187 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
188 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
189 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
190 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
191 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
192 MLX5_CMD_OP_CREATE_LAG = 0x840,
193 MLX5_CMD_OP_MODIFY_LAG = 0x841,
194 MLX5_CMD_OP_QUERY_LAG = 0x842,
195 MLX5_CMD_OP_DESTROY_LAG = 0x843,
196 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
197 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
198 MLX5_CMD_OP_CREATE_TIR = 0x900,
199 MLX5_CMD_OP_MODIFY_TIR = 0x901,
200 MLX5_CMD_OP_DESTROY_TIR = 0x902,
201 MLX5_CMD_OP_QUERY_TIR = 0x903,
202 MLX5_CMD_OP_CREATE_SQ = 0x904,
203 MLX5_CMD_OP_MODIFY_SQ = 0x905,
204 MLX5_CMD_OP_DESTROY_SQ = 0x906,
205 MLX5_CMD_OP_QUERY_SQ = 0x907,
206 MLX5_CMD_OP_CREATE_RQ = 0x908,
207 MLX5_CMD_OP_MODIFY_RQ = 0x909,
208 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
209 MLX5_CMD_OP_QUERY_RQ = 0x90b,
210 MLX5_CMD_OP_CREATE_RMP = 0x90c,
211 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
212 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
213 MLX5_CMD_OP_QUERY_RMP = 0x90f,
214 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
215 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
216 MLX5_CMD_OP_CREATE_TIS = 0x912,
217 MLX5_CMD_OP_MODIFY_TIS = 0x913,
218 MLX5_CMD_OP_DESTROY_TIS = 0x914,
219 MLX5_CMD_OP_QUERY_TIS = 0x915,
220 MLX5_CMD_OP_CREATE_RQT = 0x916,
221 MLX5_CMD_OP_MODIFY_RQT = 0x917,
222 MLX5_CMD_OP_DESTROY_RQT = 0x918,
223 MLX5_CMD_OP_QUERY_RQT = 0x919,
224 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
225 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
226 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
227 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
228 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
229 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
230 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
231 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
232 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
233 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
234 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
235 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
236 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
237 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
238 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
239 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
243 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007,
244 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400,
245 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001,
246 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003,
247 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004,
248 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005,
249 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006,
250 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007,
251 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
252 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009,
253 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a,
254 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004
257 struct mlx5_ifc_flow_table_fields_supported_bits {
260 u8 outer_ether_type[0x1];
262 u8 outer_first_prio[0x1];
263 u8 outer_first_cfi[0x1];
264 u8 outer_first_vid[0x1];
266 u8 outer_second_prio[0x1];
267 u8 outer_second_cfi[0x1];
268 u8 outer_second_vid[0x1];
269 u8 outer_ipv6_flow_label[0x1];
273 u8 outer_ip_protocol[0x1];
274 u8 outer_ip_ecn[0x1];
275 u8 outer_ip_dscp[0x1];
276 u8 outer_udp_sport[0x1];
277 u8 outer_udp_dport[0x1];
278 u8 outer_tcp_sport[0x1];
279 u8 outer_tcp_dport[0x1];
280 u8 outer_tcp_flags[0x1];
281 u8 outer_gre_protocol[0x1];
282 u8 outer_gre_key[0x1];
283 u8 outer_vxlan_vni[0x1];
284 u8 outer_geneve_vni[0x1];
285 u8 outer_geneve_oam[0x1];
286 u8 outer_geneve_protocol_type[0x1];
287 u8 outer_geneve_opt_len[0x1];
289 u8 source_eswitch_port[0x1];
293 u8 inner_ether_type[0x1];
295 u8 inner_first_prio[0x1];
296 u8 inner_first_cfi[0x1];
297 u8 inner_first_vid[0x1];
299 u8 inner_second_prio[0x1];
300 u8 inner_second_cfi[0x1];
301 u8 inner_second_vid[0x1];
302 u8 inner_ipv6_flow_label[0x1];
306 u8 inner_ip_protocol[0x1];
307 u8 inner_ip_ecn[0x1];
308 u8 inner_ip_dscp[0x1];
309 u8 inner_udp_sport[0x1];
310 u8 inner_udp_dport[0x1];
311 u8 inner_tcp_sport[0x1];
312 u8 inner_tcp_dport[0x1];
313 u8 inner_tcp_flags[0x1];
324 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
325 u8 ingress_general_high[0x20];
327 u8 ingress_general_low[0x20];
329 u8 ingress_policy_engine_high[0x20];
331 u8 ingress_policy_engine_low[0x20];
333 u8 ingress_vlan_membership_high[0x20];
335 u8 ingress_vlan_membership_low[0x20];
337 u8 ingress_tag_frame_type_high[0x20];
339 u8 ingress_tag_frame_type_low[0x20];
341 u8 egress_vlan_membership_high[0x20];
343 u8 egress_vlan_membership_low[0x20];
345 u8 loopback_filter_high[0x20];
347 u8 loopback_filter_low[0x20];
349 u8 egress_general_high[0x20];
351 u8 egress_general_low[0x20];
353 u8 reserved_at_1c0[0x40];
355 u8 egress_hoq_high[0x20];
357 u8 egress_hoq_low[0x20];
359 u8 port_isolation_high[0x20];
361 u8 port_isolation_low[0x20];
363 u8 egress_policy_engine_high[0x20];
365 u8 egress_policy_engine_low[0x20];
367 u8 ingress_tx_link_down_high[0x20];
369 u8 ingress_tx_link_down_low[0x20];
371 u8 egress_stp_filter_high[0x20];
373 u8 egress_stp_filter_low[0x20];
375 u8 egress_hoq_stall_high[0x20];
377 u8 egress_hoq_stall_low[0x20];
379 u8 reserved_at_340[0x440];
381 struct mlx5_ifc_flow_table_prop_layout_bits {
384 u8 flow_counter[0x1];
385 u8 flow_modify_en[0x1];
390 u8 log_max_ft_size[0x6];
392 u8 max_ft_level[0x8];
397 u8 log_max_ft_num[0x8];
400 u8 log_max_flow_counter[0x8];
401 u8 log_max_destination[0x8];
404 u8 log_max_flow[0x8];
408 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
410 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
413 struct mlx5_ifc_odp_per_transport_service_cap_bits {
423 struct mlx5_ifc_flow_counter_list_bits {
425 u8 flow_counter_id[0x10];
431 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,
432 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1,
433 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2,
434 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
437 struct mlx5_ifc_dest_format_struct_bits {
438 u8 destination_type[0x8];
439 u8 destination_id[0x18];
444 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
479 struct mlx5_ifc_fte_match_set_misc_bits {
484 u8 source_port[0x10];
486 u8 outer_second_prio[0x3];
487 u8 outer_second_cfi[0x1];
488 u8 outer_second_vid[0xc];
489 u8 inner_second_prio[0x3];
490 u8 inner_second_cfi[0x1];
491 u8 inner_second_vid[0xc];
493 u8 outer_second_vlan_tag[0x1];
494 u8 inner_second_vlan_tag[0x1];
496 u8 gre_protocol[0x10];
509 u8 outer_ipv6_flow_label[0x14];
512 u8 inner_ipv6_flow_label[0x14];
515 u8 geneve_opt_len[0x6];
516 u8 geneve_protocol_type[0x10];
524 struct mlx5_ifc_cmd_pas_bits {
531 struct mlx5_ifc_uint64_bits {
537 struct mlx5_ifc_application_prio_entry_bits {
542 u8 protocol_id[0x10];
545 struct mlx5_ifc_nodnic_ring_doorbell_bits {
552 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
553 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
554 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
555 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
556 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
557 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
558 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
559 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
560 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
561 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
564 struct mlx5_ifc_ads_bits {
577 u8 src_addr_index[0x8];
586 u8 rgid_rip[16][0x8];
606 struct mlx5_ifc_diagnostic_counter_cap_bits {
612 struct mlx5_ifc_debug_cap_bits {
614 u8 log_max_samples[0x8];
618 u8 health_mon_rx_activity[0x1];
620 u8 log_min_sample_period[0x8];
622 u8 reserved_2[0x1c0];
624 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
627 struct mlx5_ifc_qos_cap_bits {
628 u8 packet_pacing[0x1];
629 u8 esw_scheduling[0x1];
630 u8 esw_bw_share[0x1];
631 u8 esw_rate_limit[0x1];
633 u8 packet_pacing_burst_bound[0x1];
634 u8 reserved_at_6[0x1a];
636 u8 reserved_at_20[0x20];
638 u8 packet_pacing_max_rate[0x20];
640 u8 packet_pacing_min_rate[0x20];
642 u8 reserved_at_80[0x10];
643 u8 packet_pacing_rate_table_size[0x10];
645 u8 esw_element_type[0x10];
646 u8 esw_tsar_type[0x10];
648 u8 reserved_at_c0[0x10];
649 u8 max_qos_para_vport[0x10];
651 u8 max_tsar_bw_share[0x20];
653 u8 reserved_at_100[0x700];
656 struct mlx5_ifc_snapshot_cap_bits {
658 u8 suspend_qp_uc[0x1];
659 u8 suspend_qp_ud[0x1];
660 u8 suspend_qp_rc[0x1];
665 u8 restore_mkey[0x1];
672 u8 reserved_3[0x7a0];
675 struct mlx5_ifc_e_switch_cap_bits {
676 u8 vport_svlan_strip[0x1];
677 u8 vport_cvlan_strip[0x1];
678 u8 vport_svlan_insert[0x1];
679 u8 vport_cvlan_insert_if_not_exist[0x1];
680 u8 vport_cvlan_insert_overwrite[0x1];
684 u8 nic_vport_node_guid_modify[0x1];
685 u8 nic_vport_port_guid_modify[0x1];
687 u8 reserved_1[0x7e0];
690 struct mlx5_ifc_flow_table_eswitch_cap_bits {
691 u8 reserved_0[0x200];
693 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
697 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
699 u8 reserved_1[0x7800];
702 struct mlx5_ifc_flow_table_nic_cap_bits {
703 u8 reserved_0[0x200];
705 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
717 u8 reserved_1[0x7200];
720 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
724 u8 lro_psh_flag[0x1];
725 u8 lro_time_stamp[0x1];
726 u8 lro_max_msg_sz_mode[0x2];
727 u8 wqe_vlan_insert[0x1];
728 u8 self_lb_en_modifiable[0x1];
732 u8 multi_pkt_send_wqe[0x2];
733 u8 wqe_inline_mode[0x2];
734 u8 rss_ind_tbl_cap[0x4];
736 u8 tunnel_lso_const_out_ip_id[0x1];
737 u8 tunnel_lro_gre[0x1];
738 u8 tunnel_lro_vxlan[0x1];
739 u8 tunnel_statless_gre[0x1];
740 u8 tunnel_stateless_vxlan[0x1];
746 u8 max_geneve_opt_len[0x1];
747 u8 tunnel_stateless_geneve_rx[0x1];
750 u8 lro_min_mss_size[0x10];
752 u8 reserved_4[0x120];
754 u8 lro_timer_supported_periods[4][0x20];
756 u8 reserved_5[0x600];
760 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1,
761 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2,
762 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
765 struct mlx5_ifc_roce_cap_bits {
767 u8 rts2rts_primary_eth_prio[0x1];
768 u8 roce_rx_allow_untagged[0x1];
769 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
778 u8 roce_version[0x8];
781 u8 r_roce_dest_udp_port[0x10];
783 u8 r_roce_max_src_udp_port[0x10];
784 u8 r_roce_min_src_udp_port[0x10];
787 u8 roce_address_table_size[0x10];
789 u8 reserved_6[0x700];
793 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1,
794 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
795 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
796 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
797 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
798 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
799 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
800 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
801 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
805 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
806 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
807 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
808 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
809 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
810 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
811 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
812 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
813 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
816 struct mlx5_ifc_atomic_caps_bits {
819 u8 atomic_req_8B_endianess_mode[0x2];
821 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
828 u8 atomic_operations[0x10];
831 u8 atomic_size_qp[0x10];
834 u8 atomic_size_dc[0x10];
836 u8 reserved_7[0x720];
839 struct mlx5_ifc_odp_cap_bits {
847 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
849 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
851 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
853 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
855 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
857 u8 reserved_3[0x6e0];
861 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
862 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
863 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
864 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
865 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
869 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
870 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
871 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
872 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
873 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
874 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
878 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
879 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
883 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
884 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
885 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
888 struct mlx5_ifc_cmd_hca_cap_bits {
891 u8 log_max_srq_sz[0x8];
892 u8 log_max_qp_sz[0x8];
901 u8 log_max_cq_sz[0x8];
905 u8 log_max_eq_sz[0x8];
907 u8 log_max_mkey[0x6];
911 u8 max_indirection[0x8];
913 u8 log_max_mrw_sz[0x7];
915 u8 log_max_bsf_list_size[0x6];
917 u8 log_max_klm_list_size[0x6];
920 u8 log_max_ra_req_dc[0x6];
922 u8 log_max_ra_res_dc[0x6];
925 u8 log_max_ra_req_qp[0x6];
927 u8 log_max_ra_res_qp[0x6];
930 u8 cc_query_allowed[0x1];
931 u8 cc_modify_allowed[0x1];
933 u8 cache_line_128byte[0x1];
935 u8 gid_table_size[0x10];
937 u8 out_of_seq_cnt[0x1];
938 u8 vport_counters[0x1];
939 u8 retransmission_q_counters[0x1];
941 u8 modify_rq_counters_set_id[0x1];
942 u8 rq_delay_drop[0x1];
944 u8 pkey_table_size[0x10];
946 u8 vport_group_manager[0x1];
947 u8 vhca_group_manager[0x1];
952 u8 nic_flow_table[0x1];
953 u8 eswitch_flow_table[0x1];
955 u8 local_ca_ack_delay[0x5];
956 u8 port_module_event[0x1];
966 u8 temp_warn_event[0x1];
980 u8 stat_rate_support[0x10];
984 u8 compact_address_vector[0x1];
987 u8 ipoib_enhanced_offloads[0x1];
988 u8 ipoib_ipoib_offloads[0x1];
990 u8 dc_connect_qp[0x1];
991 u8 dc_cnak_trace[0x1];
992 u8 drain_sigerr[0x1];
993 u8 cmdif_checksum[0x2];
996 u8 wq_signature[0x1];
997 u8 sctr_data_cqe[0x1];
1004 u8 eth_net_offloads[0x1];
1007 u8 reserved_30[0x1];
1011 u8 cq_moderation[0x1];
1012 u8 cq_period_mode_modify[0x1];
1013 u8 cq_invalidate[0x1];
1014 u8 reserved_at_225[0x1];
1015 u8 cq_eq_remap[0x1];
1017 u8 block_lb_mc[0x1];
1018 u8 exponential_backoff[0x1];
1019 u8 scqe_break_moderation[0x1];
1020 u8 cq_period_start_from_cqe[0x1];
1024 u8 reserved_32[0x7];
1027 u8 reserved_33[0x4];
1033 u8 reserved_34[0xa];
1035 u8 reserved_35[0x8];
1039 u8 driver_version[0x1];
1040 u8 pad_tx_eth_packet[0x1];
1041 u8 reserved_36[0x8];
1042 u8 log_bf_reg_size[0x5];
1043 u8 reserved_37[0x10];
1045 u8 num_of_diagnostic_counters[0x10];
1046 u8 max_wqe_sz_sq[0x10];
1048 u8 reserved_38[0x10];
1049 u8 max_wqe_sz_rq[0x10];
1051 u8 reserved_39[0x10];
1052 u8 max_wqe_sz_sq_dc[0x10];
1054 u8 reserved_40[0x7];
1055 u8 max_qp_mcg[0x19];
1057 u8 reserved_41[0x18];
1058 u8 log_max_mcg[0x8];
1060 u8 reserved_42[0x3];
1061 u8 log_max_transport_domain[0x5];
1062 u8 reserved_43[0x3];
1064 u8 reserved_44[0xb];
1065 u8 log_max_xrcd[0x5];
1067 u8 reserved_45[0x10];
1068 u8 max_flow_counter[0x10];
1070 u8 reserved_46[0x3];
1072 u8 reserved_47[0x3];
1074 u8 reserved_48[0x3];
1075 u8 log_max_tir[0x5];
1076 u8 reserved_49[0x3];
1077 u8 log_max_tis[0x5];
1079 u8 basic_cyclic_rcv_wqe[0x1];
1080 u8 reserved_50[0x2];
1081 u8 log_max_rmp[0x5];
1082 u8 reserved_51[0x3];
1083 u8 log_max_rqt[0x5];
1084 u8 reserved_52[0x3];
1085 u8 log_max_rqt_size[0x5];
1086 u8 reserved_53[0x3];
1087 u8 log_max_tis_per_sq[0x5];
1089 u8 reserved_54[0x3];
1090 u8 log_max_stride_sz_rq[0x5];
1091 u8 reserved_55[0x3];
1092 u8 log_min_stride_sz_rq[0x5];
1093 u8 reserved_56[0x3];
1094 u8 log_max_stride_sz_sq[0x5];
1095 u8 reserved_57[0x3];
1096 u8 log_min_stride_sz_sq[0x5];
1098 u8 reserved_58[0x1b];
1099 u8 log_max_wq_sz[0x5];
1101 u8 nic_vport_change_event[0x1];
1102 u8 disable_local_lb[0x1];
1103 u8 reserved_59[0x9];
1104 u8 log_max_vlan_list[0x5];
1105 u8 reserved_60[0x3];
1106 u8 log_max_current_mc_list[0x5];
1107 u8 reserved_61[0x3];
1108 u8 log_max_current_uc_list[0x5];
1110 u8 reserved_62[0x80];
1112 u8 reserved_63[0x3];
1113 u8 log_max_l2_table[0x5];
1114 u8 reserved_64[0x8];
1115 u8 log_uar_page_sz[0x10];
1117 u8 reserved_65[0x20];
1119 u8 device_frequency_mhz[0x20];
1121 u8 device_frequency_khz[0x20];
1123 u8 reserved_66[0x80];
1125 u8 log_max_atomic_size_qp[0x8];
1126 u8 reserved_67[0x10];
1127 u8 log_max_atomic_size_dc[0x8];
1129 u8 reserved_68[0x1f];
1130 u8 cqe_compression[0x1];
1132 u8 cqe_compression_timeout[0x10];
1133 u8 cqe_compression_max_num[0x10];
1135 u8 reserved_69[0x220];
1138 enum mlx5_flow_destination_type {
1139 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1140 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1141 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1144 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1145 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1146 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1147 u8 reserved_0[0x40];
1150 struct mlx5_ifc_fte_match_param_bits {
1151 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1153 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1155 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1157 u8 reserved_0[0xa00];
1161 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1162 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1164 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1165 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1168 struct mlx5_ifc_rx_hash_field_select_bits {
1169 u8 l3_prot_type[0x1];
1170 u8 l4_prot_type[0x1];
1171 u8 selected_fields[0x1e];
1175 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1176 MLX5_WQ_TYPE_CYCLIC = 0x1,
1177 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2,
1178 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1187 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1188 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1191 struct mlx5_ifc_wq_bits {
1193 u8 wq_signature[0x1];
1194 u8 end_padding_mode[0x2];
1196 u8 reserved_0[0x18];
1198 u8 hds_skip_first_sge[0x1];
1199 u8 log2_hds_buf_size[0x3];
1201 u8 page_offset[0x5];
1212 u8 hw_counter[0x20];
1214 u8 sw_counter[0x20];
1217 u8 log_wq_stride[0x4];
1219 u8 log_wq_pg_sz[0x5];
1223 u8 reserved_7[0x15];
1224 u8 single_wqe_log_num_of_strides[0x3];
1225 u8 two_byte_shift_en[0x1];
1227 u8 single_stride_log_num_of_bytes[0x3];
1229 u8 reserved_9[0x4c0];
1231 struct mlx5_ifc_cmd_pas_bits pas[0];
1234 struct mlx5_ifc_rq_num_bits {
1239 struct mlx5_ifc_mac_address_layout_bits {
1240 u8 reserved_0[0x10];
1241 u8 mac_addr_47_32[0x10];
1243 u8 mac_addr_31_0[0x20];
1246 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1247 u8 reserved_0[0xa0];
1249 u8 min_time_between_cnps[0x20];
1251 u8 reserved_1[0x12];
1254 u8 cnp_prio_mode[0x1];
1255 u8 cnp_802p_prio[0x3];
1257 u8 reserved_3[0x720];
1260 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1261 u8 reserved_0[0x60];
1264 u8 clamp_tgt_rate[0x1];
1266 u8 clamp_tgt_rate_after_time_inc[0x1];
1267 u8 reserved_3[0x17];
1269 u8 reserved_4[0x20];
1271 u8 rpg_time_reset[0x20];
1273 u8 rpg_byte_reset[0x20];
1275 u8 rpg_threshold[0x20];
1277 u8 rpg_max_rate[0x20];
1279 u8 rpg_ai_rate[0x20];
1281 u8 rpg_hai_rate[0x20];
1285 u8 rpg_min_dec_fac[0x20];
1287 u8 rpg_min_rate[0x20];
1289 u8 reserved_5[0xe0];
1291 u8 rate_to_set_on_first_cnp[0x20];
1295 u8 dce_tcp_rtt[0x20];
1297 u8 rate_reduce_monitor_period[0x20];
1299 u8 reserved_6[0x20];
1301 u8 initial_alpha_value[0x20];
1303 u8 reserved_7[0x4a0];
1306 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1307 u8 reserved_0[0x80];
1309 u8 rppp_max_rps[0x20];
1311 u8 rpg_time_reset[0x20];
1313 u8 rpg_byte_reset[0x20];
1315 u8 rpg_threshold[0x20];
1317 u8 rpg_max_rate[0x20];
1319 u8 rpg_ai_rate[0x20];
1321 u8 rpg_hai_rate[0x20];
1325 u8 rpg_min_dec_fac[0x20];
1327 u8 rpg_min_rate[0x20];
1329 u8 reserved_1[0x640];
1333 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1334 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1335 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1338 struct mlx5_ifc_resize_field_select_bits {
1339 u8 resize_field_select[0x20];
1343 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1344 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1345 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1346 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1347 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
1348 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
1351 struct mlx5_ifc_modify_field_select_bits {
1352 u8 modify_field_select[0x20];
1355 struct mlx5_ifc_field_select_r_roce_np_bits {
1356 u8 field_select_r_roce_np[0x20];
1360 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2,
1361 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4,
1362 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8,
1363 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10,
1364 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20,
1365 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40,
1366 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80,
1367 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100,
1368 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200,
1369 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400,
1370 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800,
1371 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000,
1372 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000,
1373 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000,
1374 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000,
1377 struct mlx5_ifc_field_select_r_roce_rp_bits {
1378 u8 field_select_r_roce_rp[0x20];
1382 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1383 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1384 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1385 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1386 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1387 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1388 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1389 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1391 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1394 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1395 u8 field_select_8021qaurp[0x20];
1398 struct mlx5_ifc_pptb_reg_bits {
1418 u8 reserved_3[0x10];
1420 u8 untagged_buff[0x4];
1423 struct mlx5_ifc_dcbx_app_reg_bits {
1425 u8 port_number[0x8];
1426 u8 reserved_1[0x10];
1428 u8 reserved_2[0x1a];
1429 u8 num_app_prio[0x6];
1431 u8 reserved_3[0x40];
1433 struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1436 struct mlx5_ifc_dcbx_param_reg_bits {
1437 u8 dcbx_cee_cap[0x1];
1438 u8 dcbx_ieee_cap[0x1];
1439 u8 dcbx_standby_cap[0x1];
1441 u8 port_number[0x8];
1443 u8 max_application_table_size[0x6];
1445 u8 reserved_2[0x15];
1446 u8 version_oper[0x3];
1448 u8 version_admin[0x3];
1450 u8 willing_admin[0x1];
1452 u8 pfc_cap_oper[0x4];
1454 u8 pfc_cap_admin[0x4];
1456 u8 num_of_tc_oper[0x4];
1458 u8 num_of_tc_admin[0x4];
1460 u8 remote_willing[0x1];
1462 u8 remote_pfc_cap[0x4];
1463 u8 reserved_9[0x14];
1464 u8 remote_num_of_tc[0x4];
1466 u8 reserved_10[0x18];
1469 u8 reserved_11[0x160];
1472 struct mlx5_ifc_qhll_bits {
1473 u8 reserved_at_0[0x8];
1475 u8 reserved_at_10[0x10];
1477 u8 reserved_at_20[0x1b];
1481 u8 reserved_at_41[0x1c];
1485 struct mlx5_ifc_qetcr_reg_bits {
1486 u8 operation_type[0x2];
1487 u8 cap_local_admin[0x1];
1488 u8 cap_remote_admin[0x1];
1490 u8 port_number[0x8];
1491 u8 reserved_1[0x10];
1493 u8 reserved_2[0x20];
1497 u8 global_configuration[0x40];
1500 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1501 u8 queue_address_63_32[0x20];
1503 u8 queue_address_31_12[0x14];
1507 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1510 u8 queue_number[0x18];
1514 u8 reserved_2[0x10];
1515 u8 pkey_index[0x10];
1517 u8 reserved_3[0x40];
1520 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1527 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0,
1528 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1,
1532 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0,
1533 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1,
1534 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2,
1535 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
1538 struct mlx5_ifc_nodnic_event_word_bits {
1539 u8 driver_reset_needed[0x1];
1540 u8 port_management_change_event[0x1];
1541 u8 reserved_0[0x19];
1546 struct mlx5_ifc_nic_vport_change_event_bits {
1547 u8 reserved_0[0x10];
1550 u8 reserved_1[0xc0];
1553 struct mlx5_ifc_pages_req_event_bits {
1554 u8 reserved_0[0x10];
1555 u8 function_id[0x10];
1559 u8 reserved_1[0xa0];
1562 struct mlx5_ifc_cmd_inter_comp_event_bits {
1563 u8 command_completion_vector[0x20];
1565 u8 reserved_0[0xc0];
1568 struct mlx5_ifc_stall_vl_event_bits {
1569 u8 reserved_0[0x18];
1574 u8 reserved_2[0xa0];
1577 struct mlx5_ifc_db_bf_congestion_event_bits {
1578 u8 event_subtype[0x8];
1580 u8 congestion_level[0x8];
1583 u8 reserved_2[0xa0];
1586 struct mlx5_ifc_gpio_event_bits {
1587 u8 reserved_0[0x60];
1589 u8 gpio_event_hi[0x20];
1591 u8 gpio_event_lo[0x20];
1593 u8 reserved_1[0x40];
1596 struct mlx5_ifc_port_state_change_event_bits {
1597 u8 reserved_0[0x40];
1600 u8 reserved_1[0x1c];
1602 u8 reserved_2[0x80];
1605 struct mlx5_ifc_dropped_packet_logged_bits {
1606 u8 reserved_0[0xe0];
1610 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1611 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1614 struct mlx5_ifc_cq_error_bits {
1618 u8 reserved_1[0x20];
1620 u8 reserved_2[0x18];
1623 u8 reserved_3[0x80];
1626 struct mlx5_ifc_rdma_page_fault_event_bits {
1627 u8 bytes_commited[0x20];
1631 u8 reserved_0[0x10];
1632 u8 packet_len[0x10];
1634 u8 rdma_op_len[0x20];
1645 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1646 u8 bytes_committed[0x20];
1648 u8 reserved_0[0x10];
1651 u8 reserved_1[0x10];
1654 u8 reserved_2[0x60];
1664 MLX5_QP_EVENTS_TYPE_QP = 0x0,
1665 MLX5_QP_EVENTS_TYPE_RQ = 0x1,
1666 MLX5_QP_EVENTS_TYPE_SQ = 0x2,
1669 struct mlx5_ifc_qp_events_bits {
1670 u8 reserved_0[0xa0];
1673 u8 reserved_1[0x18];
1676 u8 qpn_rqn_sqn[0x18];
1679 struct mlx5_ifc_dct_events_bits {
1680 u8 reserved_0[0xc0];
1683 u8 dct_number[0x18];
1686 struct mlx5_ifc_comp_event_bits {
1687 u8 reserved_0[0xc0];
1693 struct mlx5_ifc_fw_version_bits {
1695 u8 reserved_0[0x10];
1711 MLX5_QPC_STATE_RST = 0x0,
1712 MLX5_QPC_STATE_INIT = 0x1,
1713 MLX5_QPC_STATE_RTR = 0x2,
1714 MLX5_QPC_STATE_RTS = 0x3,
1715 MLX5_QPC_STATE_SQER = 0x4,
1716 MLX5_QPC_STATE_SQD = 0x5,
1717 MLX5_QPC_STATE_ERR = 0x6,
1718 MLX5_QPC_STATE_SUSPENDED = 0x9,
1722 MLX5_QPC_ST_RC = 0x0,
1723 MLX5_QPC_ST_UC = 0x1,
1724 MLX5_QPC_ST_UD = 0x2,
1725 MLX5_QPC_ST_XRC = 0x3,
1726 MLX5_QPC_ST_DCI = 0x5,
1727 MLX5_QPC_ST_QP0 = 0x7,
1728 MLX5_QPC_ST_QP1 = 0x8,
1729 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1730 MLX5_QPC_ST_REG_UMR = 0xc,
1734 MLX5_QP_PM_ARMED = 0x0,
1735 MLX5_QP_PM_REARM = 0x1,
1736 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1737 MLX5_QP_PM_MIGRATED = 0x3,
1741 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1742 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1746 MLX5_QPC_MTU_256_BYTES = 0x1,
1747 MLX5_QPC_MTU_512_BYTES = 0x2,
1748 MLX5_QPC_MTU_1K_BYTES = 0x3,
1749 MLX5_QPC_MTU_2K_BYTES = 0x4,
1750 MLX5_QPC_MTU_4K_BYTES = 0x5,
1751 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1755 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1756 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1757 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1758 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1759 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1760 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1761 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1762 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1766 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1767 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1768 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1772 MLX5_QPC_CS_RES_DISABLE = 0x0,
1773 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1774 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1777 struct mlx5_ifc_qpc_bits {
1784 u8 end_padding_mode[0x2];
1787 u8 wq_signature[0x1];
1788 u8 block_lb_mc[0x1];
1789 u8 atomic_like_write_en[0x1];
1790 u8 latency_sensitive[0x1];
1792 u8 drain_sigerr[0x1];
1797 u8 log_msg_max[0x5];
1799 u8 log_rq_size[0x4];
1800 u8 log_rq_stride[0x3];
1802 u8 log_sq_size[0x4];
1805 u8 ulp_stateless_offload_mode[0x4];
1807 u8 counter_set_id[0x8];
1811 u8 user_index[0x18];
1814 u8 log_page_size[0x5];
1815 u8 remote_qpn[0x18];
1817 struct mlx5_ifc_ads_bits primary_address_path;
1819 struct mlx5_ifc_ads_bits secondary_address_path;
1821 u8 log_ack_req_freq[0x4];
1822 u8 reserved_10[0x4];
1823 u8 log_sra_max[0x3];
1824 u8 reserved_11[0x2];
1825 u8 retry_count[0x3];
1827 u8 reserved_12[0x1];
1829 u8 cur_rnr_retry[0x3];
1830 u8 cur_retry_count[0x3];
1831 u8 reserved_13[0x5];
1833 u8 reserved_14[0x20];
1835 u8 reserved_15[0x8];
1836 u8 next_send_psn[0x18];
1838 u8 reserved_16[0x8];
1841 u8 reserved_17[0x40];
1843 u8 reserved_18[0x8];
1844 u8 last_acked_psn[0x18];
1846 u8 reserved_19[0x8];
1849 u8 reserved_20[0x8];
1850 u8 log_rra_max[0x3];
1851 u8 reserved_21[0x1];
1852 u8 atomic_mode[0x4];
1856 u8 reserved_22[0x1];
1857 u8 page_offset[0x6];
1858 u8 reserved_23[0x3];
1859 u8 cd_slave_receive[0x1];
1860 u8 cd_slave_send[0x1];
1863 u8 reserved_24[0x3];
1864 u8 min_rnr_nak[0x5];
1865 u8 next_rcv_psn[0x18];
1867 u8 reserved_25[0x8];
1870 u8 reserved_26[0x8];
1877 u8 reserved_27[0x5];
1881 u8 reserved_28[0x8];
1884 u8 hw_sq_wqebb_counter[0x10];
1885 u8 sw_sq_wqebb_counter[0x10];
1887 u8 hw_rq_counter[0x20];
1889 u8 sw_rq_counter[0x20];
1891 u8 reserved_29[0x20];
1893 u8 reserved_30[0xf];
1898 u8 dc_access_key[0x40];
1900 u8 rdma_active[0x1];
1903 u8 reserved_31[0x5];
1904 u8 send_msg_psn[0x18];
1906 u8 reserved_32[0x8];
1907 u8 rcv_msg_psn[0x18];
1913 u8 reserved_33[0x20];
1916 struct mlx5_ifc_roce_addr_layout_bits {
1917 u8 source_l3_address[16][0x8];
1922 u8 source_mac_47_32[0x10];
1924 u8 source_mac_31_0[0x20];
1926 u8 reserved_1[0x14];
1927 u8 roce_l3_type[0x4];
1928 u8 roce_version[0x8];
1930 u8 reserved_2[0x20];
1933 struct mlx5_ifc_rdbc_bits {
1934 u8 reserved_0[0x1c];
1937 u8 reserved_1[0x20];
1946 u8 byte_count[0x20];
1948 u8 reserved_3[0x20];
1950 u8 atomic_resp[32][0x8];
1954 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1955 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1956 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1957 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
1960 struct mlx5_ifc_flow_context_bits {
1961 u8 reserved_0[0x20];
1968 u8 reserved_2[0x10];
1972 u8 destination_list_size[0x18];
1975 u8 flow_counter_list_size[0x18];
1977 u8 reserved_5[0x140];
1979 struct mlx5_ifc_fte_match_param_bits match_value;
1981 u8 reserved_6[0x600];
1983 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
1987 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1988 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1991 struct mlx5_ifc_xrc_srqc_bits {
1993 u8 log_xrc_srq_size[0x4];
1994 u8 reserved_0[0x18];
1996 u8 wq_signature[0x1];
2000 u8 basic_cyclic_rcv_wqe[0x1];
2001 u8 log_rq_stride[0x3];
2004 u8 page_offset[0x6];
2008 u8 reserved_3[0x20];
2011 u8 log_page_size[0x6];
2012 u8 user_index[0x18];
2014 u8 reserved_5[0x20];
2022 u8 reserved_7[0x40];
2024 u8 db_record_addr_h[0x20];
2026 u8 db_record_addr_l[0x1e];
2029 u8 reserved_9[0x80];
2032 struct mlx5_ifc_traffic_counter_bits {
2038 struct mlx5_ifc_tisc_bits {
2041 u8 reserved_1[0x10];
2043 u8 reserved_2[0x100];
2046 u8 transport_domain[0x18];
2049 u8 underlay_qpn[0x18];
2051 u8 reserved_5[0x3a0];
2055 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2056 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2060 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2061 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2065 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
2066 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
2067 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
2071 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1,
2072 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2,
2075 struct mlx5_ifc_tirc_bits {
2076 u8 reserved_0[0x20];
2079 u8 reserved_1[0x1c];
2081 u8 reserved_2[0x40];
2084 u8 lro_timeout_period_usecs[0x10];
2085 u8 lro_enable_mask[0x4];
2086 u8 lro_max_msg_sz[0x8];
2088 u8 reserved_4[0x40];
2091 u8 inline_rqn[0x18];
2093 u8 rx_hash_symmetric[0x1];
2095 u8 tunneled_offload_en[0x1];
2097 u8 indirect_table[0x18];
2102 u8 transport_domain[0x18];
2104 u8 rx_hash_toeplitz_key[10][0x20];
2106 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2108 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2110 u8 reserved_9[0x4c0];
2114 MLX5_SRQC_STATE_GOOD = 0x0,
2115 MLX5_SRQC_STATE_ERROR = 0x1,
2118 struct mlx5_ifc_srqc_bits {
2120 u8 log_srq_size[0x4];
2121 u8 reserved_0[0x18];
2123 u8 wq_signature[0x1];
2128 u8 log_rq_stride[0x3];
2131 u8 page_offset[0x6];
2135 u8 reserved_4[0x20];
2138 u8 log_page_size[0x6];
2139 u8 reserved_6[0x18];
2141 u8 reserved_7[0x20];
2149 u8 reserved_9[0x40];
2151 u8 db_record_addr_h[0x20];
2153 u8 db_record_addr_l[0x1e];
2154 u8 reserved_10[0x2];
2156 u8 reserved_11[0x80];
2160 MLX5_SQC_STATE_RST = 0x0,
2161 MLX5_SQC_STATE_RDY = 0x1,
2162 MLX5_SQC_STATE_ERR = 0x3,
2165 struct mlx5_ifc_sqc_bits {
2169 u8 flush_in_error_en[0x1];
2170 u8 allow_multi_pkt_send_wqe[0x1];
2171 u8 min_wqe_inline_mode[0x3];
2175 u8 reserved_0[0x12];
2178 u8 user_index[0x18];
2183 u8 reserved_3[0x80];
2185 u8 qos_para_vport_number[0x10];
2186 u8 packet_pacing_rate_limit_index[0x10];
2188 u8 tis_lst_sz[0x10];
2189 u8 reserved_4[0x10];
2191 u8 reserved_5[0x40];
2196 struct mlx5_ifc_wq_bits wq;
2200 MLX5_TSAR_TYPE_DWRR = 0,
2201 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2202 MLX5_TSAR_TYPE_ETS = 2
2205 struct mlx5_ifc_tsar_element_attributes_bits {
2208 u8 reserved_1[0x10];
2211 struct mlx5_ifc_vport_element_attributes_bits {
2212 u8 reserved_0[0x10];
2213 u8 vport_number[0x10];
2216 struct mlx5_ifc_vport_tc_element_attributes_bits {
2217 u8 traffic_class[0x10];
2218 u8 vport_number[0x10];
2221 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2222 u8 reserved_0[0x0C];
2223 u8 traffic_class[0x04];
2224 u8 qos_para_vport_number[0x10];
2228 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2229 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2230 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2231 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2234 struct mlx5_ifc_scheduling_context_bits {
2235 u8 element_type[0x8];
2236 u8 reserved_at_8[0x18];
2238 u8 element_attributes[0x20];
2240 u8 parent_element_id[0x20];
2242 u8 reserved_at_60[0x40];
2246 u8 max_average_bw[0x20];
2248 u8 reserved_at_e0[0x120];
2251 struct mlx5_ifc_rqtc_bits {
2252 u8 reserved_0[0xa0];
2254 u8 reserved_1[0x10];
2255 u8 rqt_max_size[0x10];
2257 u8 reserved_2[0x10];
2258 u8 rqt_actual_size[0x10];
2260 u8 reserved_3[0x6a0];
2262 struct mlx5_ifc_rq_num_bits rq_num[0];
2266 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2267 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2271 MLX5_RQC_STATE_RST = 0x0,
2272 MLX5_RQC_STATE_RDY = 0x1,
2273 MLX5_RQC_STATE_ERR = 0x3,
2277 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
2278 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
2281 struct mlx5_ifc_rqc_bits {
2283 u8 delay_drop_en[0x1];
2284 u8 scatter_fcs[0x1];
2285 u8 vlan_strip_disable[0x1];
2286 u8 mem_rq_type[0x4];
2289 u8 flush_in_error_en[0x1];
2290 u8 reserved_2[0x12];
2293 u8 user_index[0x18];
2298 u8 counter_set_id[0x8];
2299 u8 reserved_5[0x18];
2304 u8 reserved_7[0xe0];
2306 struct mlx5_ifc_wq_bits wq;
2310 MLX5_RMPC_STATE_RDY = 0x1,
2311 MLX5_RMPC_STATE_ERR = 0x3,
2314 struct mlx5_ifc_rmpc_bits {
2317 u8 reserved_1[0x14];
2319 u8 basic_cyclic_rcv_wqe[0x1];
2320 u8 reserved_2[0x1f];
2322 u8 reserved_3[0x140];
2324 struct mlx5_ifc_wq_bits wq;
2328 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2329 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1,
2330 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2,
2333 struct mlx5_ifc_nic_vport_context_bits {
2335 u8 min_wqe_inline_mode[0x3];
2336 u8 reserved_1[0x15];
2337 u8 disable_mc_local_lb[0x1];
2338 u8 disable_uc_local_lb[0x1];
2341 u8 arm_change_event[0x1];
2342 u8 reserved_2[0x1a];
2343 u8 event_on_mtu[0x1];
2344 u8 event_on_promisc_change[0x1];
2345 u8 event_on_vlan_change[0x1];
2346 u8 event_on_mc_address_change[0x1];
2347 u8 event_on_uc_address_change[0x1];
2349 u8 reserved_3[0xe0];
2351 u8 reserved_4[0x10];
2354 u8 system_image_guid[0x40];
2360 u8 reserved_5[0x140];
2362 u8 qkey_violation_counter[0x10];
2363 u8 reserved_6[0x10];
2365 u8 reserved_7[0x420];
2369 u8 promisc_all[0x1];
2371 u8 allowed_list_type[0x3];
2373 u8 allowed_list_size[0xc];
2375 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2377 u8 reserved_10[0x20];
2379 u8 current_uc_mac_address[0][0x40];
2383 MLX5_ACCESS_MODE_PA = 0x0,
2384 MLX5_ACCESS_MODE_MTT = 0x1,
2385 MLX5_ACCESS_MODE_KLM = 0x2,
2388 struct mlx5_ifc_mkc_bits {
2392 u8 small_fence_on_rdma_read_response[0x1];
2399 u8 access_mode[0x2];
2405 u8 reserved_3[0x20];
2411 u8 expected_sigerr_count[0x1];
2416 u8 start_addr[0x40];
2420 u8 bsf_octword_size[0x20];
2422 u8 reserved_6[0x80];
2424 u8 translations_octword_size[0x20];
2426 u8 reserved_7[0x1b];
2427 u8 log_page_size[0x5];
2429 u8 reserved_8[0x20];
2432 struct mlx5_ifc_pkey_bits {
2433 u8 reserved_0[0x10];
2437 struct mlx5_ifc_array128_auto_bits {
2438 u8 array128_auto[16][0x8];
2442 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0,
2443 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1,
2444 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2,
2448 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1,
2449 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2,
2450 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
2451 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4,
2452 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5,
2453 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6,
2454 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
2458 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0,
2459 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1,
2460 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2,
2464 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1,
2465 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2,
2466 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
2467 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4,
2471 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1,
2472 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2,
2473 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
2474 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4,
2477 struct mlx5_ifc_hca_vport_context_bits {
2478 u8 field_select[0x20];
2480 u8 reserved_0[0xe0];
2482 u8 sm_virt_aware[0x1];
2485 u8 grh_required[0x1];
2487 u8 min_wqe_inline_mode[0x3];
2489 u8 port_physical_state[0x4];
2490 u8 vport_state_policy[0x4];
2492 u8 vport_state[0x4];
2494 u8 reserved_3[0x20];
2496 u8 system_image_guid[0x40];
2504 u8 cap_mask1_field_select[0x20];
2508 u8 cap_mask2_field_select[0x20];
2510 u8 reserved_4[0x80];
2514 u8 init_type_reply[0x4];
2516 u8 subnet_timeout[0x5];
2522 u8 qkey_violation_counter[0x10];
2523 u8 pkey_violation_counter[0x10];
2525 u8 reserved_7[0xca0];
2528 union mlx5_ifc_hca_cap_union_bits {
2529 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2530 struct mlx5_ifc_odp_cap_bits odp_cap;
2531 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2532 struct mlx5_ifc_roce_cap_bits roce_cap;
2533 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2534 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2535 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2536 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2537 struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2538 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2539 struct mlx5_ifc_qos_cap_bits qos_cap;
2540 u8 reserved_0[0x8000];
2543 struct mlx5_ifc_esw_vport_context_bits {
2545 u8 vport_svlan_strip[0x1];
2546 u8 vport_cvlan_strip[0x1];
2547 u8 vport_svlan_insert[0x1];
2548 u8 vport_cvlan_insert[0x2];
2549 u8 reserved_1[0x18];
2551 u8 reserved_2[0x20];
2560 u8 reserved_3[0x7a0];
2564 MLX5_EQC_STATUS_OK = 0x0,
2565 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2569 MLX5_EQ_STATE_ARMED = 0x9,
2570 MLX5_EQ_STATE_FIRED = 0xa,
2573 struct mlx5_ifc_eqc_bits {
2582 u8 reserved_3[0x20];
2584 u8 reserved_4[0x14];
2585 u8 page_offset[0x6];
2589 u8 log_eq_size[0x5];
2592 u8 reserved_7[0x20];
2594 u8 reserved_8[0x18];
2598 u8 log_page_size[0x5];
2599 u8 reserved_10[0x18];
2601 u8 reserved_11[0x60];
2603 u8 reserved_12[0x8];
2604 u8 consumer_counter[0x18];
2606 u8 reserved_13[0x8];
2607 u8 producer_counter[0x18];
2609 u8 reserved_14[0x80];
2613 MLX5_DCTC_STATE_ACTIVE = 0x0,
2614 MLX5_DCTC_STATE_DRAINING = 0x1,
2615 MLX5_DCTC_STATE_DRAINED = 0x2,
2619 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2620 MLX5_DCTC_CS_RES_NA = 0x1,
2621 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2625 MLX5_DCTC_MTU_256_BYTES = 0x1,
2626 MLX5_DCTC_MTU_512_BYTES = 0x2,
2627 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2628 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2629 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2632 struct mlx5_ifc_dctc_bits {
2635 u8 reserved_1[0x18];
2638 u8 user_index[0x18];
2643 u8 counter_set_id[0x8];
2644 u8 atomic_mode[0x4];
2648 u8 atomic_like_write_en[0x1];
2649 u8 latency_sensitive[0x1];
2656 u8 min_rnr_nak[0x5];
2666 u8 reserved_10[0x4];
2667 u8 flow_label[0x14];
2669 u8 dc_access_key[0x40];
2671 u8 reserved_11[0x5];
2674 u8 pkey_index[0x10];
2676 u8 reserved_12[0x8];
2677 u8 my_addr_index[0x8];
2678 u8 reserved_13[0x8];
2681 u8 dc_access_key_violation_count[0x20];
2683 u8 reserved_14[0x14];
2689 u8 reserved_15[0x40];
2693 MLX5_CQC_STATUS_OK = 0x0,
2694 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2695 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2704 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2705 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2709 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6,
2710 MLX5_CQ_STATE_ARMED = 0x9,
2711 MLX5_CQ_STATE_FIRED = 0xa,
2714 struct mlx5_ifc_cqc_bits {
2720 u8 scqe_break_moderation_en[0x1];
2722 u8 cq_period_mode[0x2];
2723 u8 cqe_compression_en[0x1];
2724 u8 mini_cqe_res_format[0x2];
2728 u8 reserved_3[0x20];
2730 u8 reserved_4[0x14];
2731 u8 page_offset[0x6];
2735 u8 log_cq_size[0x5];
2740 u8 cq_max_count[0x10];
2742 u8 reserved_8[0x18];
2746 u8 log_page_size[0x5];
2747 u8 reserved_10[0x18];
2749 u8 reserved_11[0x20];
2751 u8 reserved_12[0x8];
2752 u8 last_notified_index[0x18];
2754 u8 reserved_13[0x8];
2755 u8 last_solicit_index[0x18];
2757 u8 reserved_14[0x8];
2758 u8 consumer_counter[0x18];
2760 u8 reserved_15[0x8];
2761 u8 producer_counter[0x18];
2763 u8 reserved_16[0x40];
2768 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2769 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2770 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2771 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2772 u8 reserved_0[0x800];
2775 struct mlx5_ifc_query_adapter_param_block_bits {
2776 u8 reserved_0[0xc0];
2779 u8 ieee_vendor_id[0x18];
2781 u8 reserved_2[0x10];
2782 u8 vsd_vendor_id[0x10];
2786 u8 vsd_contd_psid[16][0x8];
2789 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2790 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2791 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2792 u8 reserved_0[0x20];
2795 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2796 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2797 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2798 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2799 u8 reserved_0[0x20];
2802 struct mlx5_ifc_bufferx_reg_bits {
2809 u8 xoff_threshold[0x10];
2810 u8 xon_threshold[0x10];
2813 struct mlx5_ifc_config_item_bits {
2816 u8 header_type[0x2];
2818 u8 default_location[0x1];
2826 u8 reserved_4[0x10];
2830 struct mlx5_ifc_nodnic_port_config_reg_bits {
2831 struct mlx5_ifc_nodnic_event_word_bits event;
2836 u8 promisc_multicast_en[0x1];
2837 u8 reserved_0[0x17];
2838 u8 receive_filter_en[0x5];
2840 u8 reserved_1[0x10];
2845 u8 receive_filters_mgid_mac[64][0x8];
2849 u8 reserved_2[0x10];
2856 u8 completion_address_63_32[0x20];
2858 u8 completion_address_31_12[0x14];
2860 u8 log_cq_size[0x6];
2862 u8 working_buffer_address_63_32[0x20];
2864 u8 working_buffer_address_31_12[0x14];
2867 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2869 u8 pkey_index[0x10];
2872 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2874 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2876 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2878 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2880 u8 reserved_6[0x400];
2883 union mlx5_ifc_event_auto_bits {
2884 struct mlx5_ifc_comp_event_bits comp_event;
2885 struct mlx5_ifc_dct_events_bits dct_events;
2886 struct mlx5_ifc_qp_events_bits qp_events;
2887 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2888 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2889 struct mlx5_ifc_cq_error_bits cq_error;
2890 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2891 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2892 struct mlx5_ifc_gpio_event_bits gpio_event;
2893 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2894 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2895 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2896 struct mlx5_ifc_pages_req_event_bits pages_req_event;
2897 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2898 u8 reserved_0[0xe0];
2901 struct mlx5_ifc_health_buffer_bits {
2902 u8 reserved_0[0x100];
2904 u8 assert_existptr[0x20];
2906 u8 assert_callra[0x20];
2908 u8 reserved_1[0x40];
2910 u8 fw_version[0x20];
2914 u8 reserved_2[0x20];
2916 u8 irisc_index[0x8];
2921 struct mlx5_ifc_register_loopback_control_bits {
2925 u8 reserved_1[0x10];
2927 u8 reserved_2[0x60];
2930 struct mlx5_ifc_lrh_bits {
2942 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
2943 u8 reserved_0[0x40];
2945 u8 reserved_1[0x10];
2950 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
2951 u8 reserved_0[0x40];
2953 u8 rol_mode_valid[0x1];
2954 u8 wol_mode_valid[0x1];
2959 u8 reserved_2[0x7a0];
2962 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
2963 u8 virtual_mac_en[0x1];
2965 u8 reserved_0[0x1e];
2967 u8 reserved_1[0x40];
2969 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2971 u8 reserved_2[0x760];
2974 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
2975 u8 virtual_mac_en[0x1];
2977 u8 reserved_0[0x1e];
2979 struct mlx5_ifc_mac_address_layout_bits permanent_mac;
2981 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2983 u8 reserved_1[0x760];
2986 struct mlx5_ifc_icmd_query_fw_info_out_bits {
2987 struct mlx5_ifc_fw_version_bits fw_version;
2989 u8 reserved_0[0x10];
2990 u8 hash_signature[0x10];
2994 u8 reserved_1[0x6e0];
2997 struct mlx5_ifc_icmd_query_cap_in_bits {
2998 u8 reserved_0[0x10];
2999 u8 capability_group[0x10];
3002 struct mlx5_ifc_icmd_query_cap_general_bits {
3004 u8 fw_info_psid[0x1];
3005 u8 reserved_0[0x1e];
3007 u8 reserved_1[0x16];
3020 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3022 u8 reserved_0[0x18];
3024 u8 reserved_1[0x7e0];
3027 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3029 u8 reserved_0[0x18];
3031 u8 reserved_1[0x7e0];
3034 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3035 u8 address_hi[0x20];
3037 u8 address_lo[0x20];
3039 u8 reserved_0[0x7c0];
3042 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3043 u8 reserved_0[0x20];
3045 u8 address_hi[0x20];
3047 u8 address_lo[0x20];
3049 u8 reserved_1[0x7a0];
3052 struct mlx5_ifc_icmd_access_reg_out_bits {
3053 u8 reserved_0[0x11];
3057 u8 register_id[0x10];
3058 u8 reserved_2[0x10];
3060 u8 reserved_3[0x40];
3064 u8 reserved_5[0x10];
3066 u8 register_data[0][0x20];
3070 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1,
3071 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2,
3074 struct mlx5_ifc_icmd_access_reg_in_bits {
3077 u8 reserved_0[0x10];
3079 u8 register_id[0x10];
3084 u8 reserved_2[0x40];
3088 u8 reserved_3[0x10];
3090 u8 register_data[0][0x20];
3093 struct mlx5_ifc_teardown_hca_out_bits {
3095 u8 reserved_0[0x18];
3099 u8 reserved_1[0x40];
3103 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3104 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3107 struct mlx5_ifc_teardown_hca_in_bits {
3109 u8 reserved_0[0x10];
3111 u8 reserved_1[0x10];
3114 u8 reserved_2[0x10];
3117 u8 reserved_3[0x20];
3120 struct mlx5_ifc_set_delay_drop_params_out_bits {
3122 u8 reserved_at_8[0x18];
3126 u8 reserved_at_40[0x40];
3129 struct mlx5_ifc_set_delay_drop_params_in_bits {
3131 u8 reserved_at_10[0x10];
3133 u8 reserved_at_20[0x10];
3136 u8 reserved_at_40[0x20];
3138 u8 reserved_at_60[0x10];
3139 u8 delay_drop_timeout[0x10];
3142 struct mlx5_ifc_query_delay_drop_params_out_bits {
3144 u8 reserved_at_8[0x18];
3148 u8 reserved_at_40[0x20];
3150 u8 reserved_at_60[0x10];
3151 u8 delay_drop_timeout[0x10];
3154 struct mlx5_ifc_query_delay_drop_params_in_bits {
3156 u8 reserved_at_10[0x10];
3158 u8 reserved_at_20[0x10];
3161 u8 reserved_at_40[0x40];
3164 struct mlx5_ifc_suspend_qp_out_bits {
3166 u8 reserved_0[0x18];
3170 u8 reserved_1[0x40];
3173 struct mlx5_ifc_suspend_qp_in_bits {
3175 u8 reserved_0[0x10];
3177 u8 reserved_1[0x10];
3183 u8 reserved_3[0x20];
3186 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3188 u8 reserved_0[0x18];
3192 u8 reserved_1[0x40];
3195 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3197 u8 reserved_0[0x10];
3199 u8 reserved_1[0x10];
3205 u8 reserved_3[0x20];
3207 u8 opt_param_mask[0x20];
3209 u8 reserved_4[0x20];
3211 struct mlx5_ifc_qpc_bits qpc;
3213 u8 reserved_5[0x80];
3216 struct mlx5_ifc_sqd2rts_qp_out_bits {
3218 u8 reserved_0[0x18];
3222 u8 reserved_1[0x40];
3225 struct mlx5_ifc_sqd2rts_qp_in_bits {
3227 u8 reserved_0[0x10];
3229 u8 reserved_1[0x10];
3235 u8 reserved_3[0x20];
3237 u8 opt_param_mask[0x20];
3239 u8 reserved_4[0x20];
3241 struct mlx5_ifc_qpc_bits qpc;
3243 u8 reserved_5[0x80];
3246 struct mlx5_ifc_set_wol_rol_out_bits {
3248 u8 reserved_0[0x18];
3252 u8 reserved_1[0x40];
3255 struct mlx5_ifc_set_wol_rol_in_bits {
3257 u8 reserved_0[0x10];
3259 u8 reserved_1[0x10];
3262 u8 rol_mode_valid[0x1];
3263 u8 wol_mode_valid[0x1];
3268 u8 reserved_3[0x20];
3271 struct mlx5_ifc_set_roce_address_out_bits {
3273 u8 reserved_0[0x18];
3277 u8 reserved_1[0x40];
3280 struct mlx5_ifc_set_roce_address_in_bits {
3282 u8 reserved_0[0x10];
3284 u8 reserved_1[0x10];
3287 u8 roce_address_index[0x10];
3288 u8 reserved_2[0x10];
3290 u8 reserved_3[0x20];
3292 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3295 struct mlx5_ifc_set_rdb_out_bits {
3297 u8 reserved_0[0x18];
3301 u8 reserved_1[0x40];
3304 struct mlx5_ifc_set_rdb_in_bits {
3306 u8 reserved_0[0x10];
3308 u8 reserved_1[0x10];
3314 u8 reserved_3[0x18];
3315 u8 rdb_list_size[0x8];
3317 struct mlx5_ifc_rdbc_bits rdb_context[0];
3320 struct mlx5_ifc_set_mad_demux_out_bits {
3322 u8 reserved_0[0x18];
3326 u8 reserved_1[0x40];
3330 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3331 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3334 struct mlx5_ifc_set_mad_demux_in_bits {
3336 u8 reserved_0[0x10];
3338 u8 reserved_1[0x10];
3341 u8 reserved_2[0x20];
3345 u8 reserved_4[0x18];
3348 struct mlx5_ifc_set_l2_table_entry_out_bits {
3350 u8 reserved_0[0x18];
3354 u8 reserved_1[0x40];
3357 struct mlx5_ifc_set_l2_table_entry_in_bits {
3359 u8 reserved_0[0x10];
3361 u8 reserved_1[0x10];
3364 u8 reserved_2[0x60];
3367 u8 table_index[0x18];
3369 u8 reserved_4[0x20];
3371 u8 reserved_5[0x13];
3375 struct mlx5_ifc_mac_address_layout_bits mac_address;
3377 u8 reserved_6[0xc0];
3380 struct mlx5_ifc_set_issi_out_bits {
3382 u8 reserved_0[0x18];
3386 u8 reserved_1[0x40];
3389 struct mlx5_ifc_set_issi_in_bits {
3391 u8 reserved_0[0x10];
3393 u8 reserved_1[0x10];
3396 u8 reserved_2[0x10];
3397 u8 current_issi[0x10];
3399 u8 reserved_3[0x20];
3402 struct mlx5_ifc_set_hca_cap_out_bits {
3404 u8 reserved_0[0x18];
3408 u8 reserved_1[0x40];
3411 struct mlx5_ifc_set_hca_cap_in_bits {
3413 u8 reserved_0[0x10];
3415 u8 reserved_1[0x10];
3418 u8 reserved_2[0x40];
3420 union mlx5_ifc_hca_cap_union_bits capability;
3424 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3425 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3426 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3427 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3430 struct mlx5_ifc_set_flow_table_root_out_bits {
3432 u8 reserved_0[0x18];
3436 u8 reserved_1[0x40];
3439 struct mlx5_ifc_set_flow_table_root_in_bits {
3441 u8 reserved_0[0x10];
3443 u8 reserved_1[0x10];
3446 u8 other_vport[0x1];
3448 u8 vport_number[0x10];
3450 u8 reserved_3[0x20];
3453 u8 reserved_4[0x18];
3459 u8 underlay_qpn[0x18];
3461 u8 reserved_7[0x120];
3464 struct mlx5_ifc_set_fte_out_bits {
3466 u8 reserved_0[0x18];
3470 u8 reserved_1[0x40];
3473 struct mlx5_ifc_set_fte_in_bits {
3475 u8 reserved_0[0x10];
3477 u8 reserved_1[0x10];
3480 u8 other_vport[0x1];
3482 u8 vport_number[0x10];
3484 u8 reserved_3[0x20];
3487 u8 reserved_4[0x18];
3492 u8 reserved_6[0x18];
3493 u8 modify_enable_mask[0x8];
3495 u8 reserved_7[0x20];
3497 u8 flow_index[0x20];
3499 u8 reserved_8[0xe0];
3501 struct mlx5_ifc_flow_context_bits flow_context;
3504 struct mlx5_ifc_set_driver_version_out_bits {
3506 u8 reserved_0[0x18];
3510 u8 reserved_1[0x40];
3513 struct mlx5_ifc_set_driver_version_in_bits {
3515 u8 reserved_0[0x10];
3517 u8 reserved_1[0x10];
3520 u8 reserved_2[0x40];
3522 u8 driver_version[64][0x8];
3525 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3527 u8 reserved_0[0x18];
3531 u8 reserved_1[0x40];
3534 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3536 u8 reserved_0[0x10];
3538 u8 reserved_1[0x10];
3542 u8 reserved_2[0x1f];
3544 u8 reserved_3[0x160];
3546 struct mlx5_ifc_cmd_pas_bits pas;
3549 struct mlx5_ifc_set_burst_size_out_bits {
3551 u8 reserved_0[0x18];
3555 u8 reserved_1[0x40];
3558 struct mlx5_ifc_set_burst_size_in_bits {
3560 u8 reserved_0[0x10];
3562 u8 reserved_1[0x10];
3565 u8 reserved_2[0x20];
3568 u8 device_burst_size[0x17];
3571 struct mlx5_ifc_rts2rts_qp_out_bits {
3573 u8 reserved_0[0x18];
3577 u8 reserved_1[0x40];
3580 struct mlx5_ifc_rts2rts_qp_in_bits {
3582 u8 reserved_0[0x10];
3584 u8 reserved_1[0x10];
3590 u8 reserved_3[0x20];
3592 u8 opt_param_mask[0x20];
3594 u8 reserved_4[0x20];
3596 struct mlx5_ifc_qpc_bits qpc;
3598 u8 reserved_5[0x80];
3601 struct mlx5_ifc_rtr2rts_qp_out_bits {
3603 u8 reserved_0[0x18];
3607 u8 reserved_1[0x40];
3610 struct mlx5_ifc_rtr2rts_qp_in_bits {
3612 u8 reserved_0[0x10];
3614 u8 reserved_1[0x10];
3620 u8 reserved_3[0x20];
3622 u8 opt_param_mask[0x20];
3624 u8 reserved_4[0x20];
3626 struct mlx5_ifc_qpc_bits qpc;
3628 u8 reserved_5[0x80];
3631 struct mlx5_ifc_rst2init_qp_out_bits {
3633 u8 reserved_0[0x18];
3637 u8 reserved_1[0x40];
3640 struct mlx5_ifc_rst2init_qp_in_bits {
3642 u8 reserved_0[0x10];
3644 u8 reserved_1[0x10];
3650 u8 reserved_3[0x20];
3652 u8 opt_param_mask[0x20];
3654 u8 reserved_4[0x20];
3656 struct mlx5_ifc_qpc_bits qpc;
3658 u8 reserved_5[0x80];
3661 struct mlx5_ifc_resume_qp_out_bits {
3663 u8 reserved_0[0x18];
3667 u8 reserved_1[0x40];
3670 struct mlx5_ifc_resume_qp_in_bits {
3672 u8 reserved_0[0x10];
3674 u8 reserved_1[0x10];
3680 u8 reserved_3[0x20];
3683 struct mlx5_ifc_query_xrc_srq_out_bits {
3685 u8 reserved_0[0x18];
3689 u8 reserved_1[0x40];
3691 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3693 u8 reserved_2[0x600];
3698 struct mlx5_ifc_query_xrc_srq_in_bits {
3700 u8 reserved_0[0x10];
3702 u8 reserved_1[0x10];
3708 u8 reserved_3[0x20];
3711 struct mlx5_ifc_query_wol_rol_out_bits {
3713 u8 reserved_0[0x18];
3717 u8 reserved_1[0x10];
3721 u8 reserved_2[0x20];
3724 struct mlx5_ifc_query_wol_rol_in_bits {
3726 u8 reserved_0[0x10];
3728 u8 reserved_1[0x10];
3731 u8 reserved_2[0x40];
3735 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3736 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3739 struct mlx5_ifc_query_vport_state_out_bits {
3741 u8 reserved_0[0x18];
3745 u8 reserved_1[0x20];
3747 u8 reserved_2[0x18];
3748 u8 admin_state[0x4];
3753 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3754 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3755 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
3758 struct mlx5_ifc_query_vport_state_in_bits {
3760 u8 reserved_0[0x10];
3762 u8 reserved_1[0x10];
3765 u8 other_vport[0x1];
3767 u8 vport_number[0x10];
3769 u8 reserved_3[0x20];
3772 struct mlx5_ifc_query_vport_counter_out_bits {
3774 u8 reserved_0[0x18];
3778 u8 reserved_1[0x40];
3780 struct mlx5_ifc_traffic_counter_bits received_errors;
3782 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3784 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3786 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3788 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3790 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3792 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3794 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3796 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3798 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3800 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3802 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3804 u8 reserved_2[0xa00];
3808 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3811 struct mlx5_ifc_query_vport_counter_in_bits {
3813 u8 reserved_0[0x10];
3815 u8 reserved_1[0x10];
3818 u8 other_vport[0x1];
3821 u8 vport_number[0x10];
3823 u8 reserved_3[0x60];
3826 u8 reserved_4[0x1f];
3828 u8 reserved_5[0x20];
3831 struct mlx5_ifc_query_tis_out_bits {
3833 u8 reserved_0[0x18];
3837 u8 reserved_1[0x40];
3839 struct mlx5_ifc_tisc_bits tis_context;
3842 struct mlx5_ifc_query_tis_in_bits {
3844 u8 reserved_0[0x10];
3846 u8 reserved_1[0x10];
3852 u8 reserved_3[0x20];
3855 struct mlx5_ifc_query_tir_out_bits {
3857 u8 reserved_0[0x18];
3861 u8 reserved_1[0xc0];
3863 struct mlx5_ifc_tirc_bits tir_context;
3866 struct mlx5_ifc_query_tir_in_bits {
3868 u8 reserved_0[0x10];
3870 u8 reserved_1[0x10];
3876 u8 reserved_3[0x20];
3879 struct mlx5_ifc_query_srq_out_bits {
3881 u8 reserved_0[0x18];
3885 u8 reserved_1[0x40];
3887 struct mlx5_ifc_srqc_bits srq_context_entry;
3889 u8 reserved_2[0x600];
3894 struct mlx5_ifc_query_srq_in_bits {
3896 u8 reserved_0[0x10];
3898 u8 reserved_1[0x10];
3904 u8 reserved_3[0x20];
3907 struct mlx5_ifc_query_sq_out_bits {
3909 u8 reserved_0[0x18];
3913 u8 reserved_1[0xc0];
3915 struct mlx5_ifc_sqc_bits sq_context;
3918 struct mlx5_ifc_query_sq_in_bits {
3920 u8 reserved_0[0x10];
3922 u8 reserved_1[0x10];
3928 u8 reserved_3[0x20];
3931 struct mlx5_ifc_query_special_contexts_out_bits {
3933 u8 reserved_0[0x18];
3937 u8 reserved_1[0x20];
3942 struct mlx5_ifc_query_special_contexts_in_bits {
3944 u8 reserved_0[0x10];
3946 u8 reserved_1[0x10];
3949 u8 reserved_2[0x40];
3952 struct mlx5_ifc_query_scheduling_element_out_bits {
3954 u8 reserved_at_8[0x18];
3958 u8 reserved_at_40[0xc0];
3960 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3962 u8 reserved_at_300[0x100];
3966 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
3969 struct mlx5_ifc_query_scheduling_element_in_bits {
3971 u8 reserved_at_10[0x10];
3973 u8 reserved_at_20[0x10];
3976 u8 scheduling_hierarchy[0x8];
3977 u8 reserved_at_48[0x18];
3979 u8 scheduling_element_id[0x20];
3981 u8 reserved_at_80[0x180];
3984 struct mlx5_ifc_query_rqt_out_bits {
3986 u8 reserved_0[0x18];
3990 u8 reserved_1[0xc0];
3992 struct mlx5_ifc_rqtc_bits rqt_context;
3995 struct mlx5_ifc_query_rqt_in_bits {
3997 u8 reserved_0[0x10];
3999 u8 reserved_1[0x10];
4005 u8 reserved_3[0x20];
4008 struct mlx5_ifc_query_rq_out_bits {
4010 u8 reserved_0[0x18];
4014 u8 reserved_1[0xc0];
4016 struct mlx5_ifc_rqc_bits rq_context;
4019 struct mlx5_ifc_query_rq_in_bits {
4021 u8 reserved_0[0x10];
4023 u8 reserved_1[0x10];
4029 u8 reserved_3[0x20];
4032 struct mlx5_ifc_query_roce_address_out_bits {
4034 u8 reserved_0[0x18];
4038 u8 reserved_1[0x40];
4040 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4043 struct mlx5_ifc_query_roce_address_in_bits {
4045 u8 reserved_0[0x10];
4047 u8 reserved_1[0x10];
4050 u8 roce_address_index[0x10];
4051 u8 reserved_2[0x10];
4053 u8 reserved_3[0x20];
4056 struct mlx5_ifc_query_rmp_out_bits {
4058 u8 reserved_0[0x18];
4062 u8 reserved_1[0xc0];
4064 struct mlx5_ifc_rmpc_bits rmp_context;
4067 struct mlx5_ifc_query_rmp_in_bits {
4069 u8 reserved_0[0x10];
4071 u8 reserved_1[0x10];
4077 u8 reserved_3[0x20];
4080 struct mlx5_ifc_query_rdb_out_bits {
4082 u8 reserved_0[0x18];
4086 u8 reserved_1[0x20];
4088 u8 reserved_2[0x18];
4089 u8 rdb_list_size[0x8];
4091 struct mlx5_ifc_rdbc_bits rdb_context[0];
4094 struct mlx5_ifc_query_rdb_in_bits {
4096 u8 reserved_0[0x10];
4098 u8 reserved_1[0x10];
4104 u8 reserved_3[0x20];
4107 struct mlx5_ifc_query_qp_out_bits {
4109 u8 reserved_0[0x18];
4113 u8 reserved_1[0x40];
4115 u8 opt_param_mask[0x20];
4117 u8 reserved_2[0x20];
4119 struct mlx5_ifc_qpc_bits qpc;
4121 u8 reserved_3[0x80];
4126 struct mlx5_ifc_query_qp_in_bits {
4128 u8 reserved_0[0x10];
4130 u8 reserved_1[0x10];
4136 u8 reserved_3[0x20];
4139 struct mlx5_ifc_query_q_counter_out_bits {
4141 u8 reserved_0[0x18];
4145 u8 reserved_1[0x40];
4147 u8 rx_write_requests[0x20];
4149 u8 reserved_2[0x20];
4151 u8 rx_read_requests[0x20];
4153 u8 reserved_3[0x20];
4155 u8 rx_atomic_requests[0x20];
4157 u8 reserved_4[0x20];
4159 u8 rx_dct_connect[0x20];
4161 u8 reserved_5[0x20];
4163 u8 out_of_buffer[0x20];
4165 u8 reserved_7[0x20];
4167 u8 out_of_sequence[0x20];
4169 u8 reserved_8[0x20];
4171 u8 duplicate_request[0x20];
4173 u8 reserved_9[0x20];
4175 u8 rnr_nak_retry_err[0x20];
4177 u8 reserved_10[0x20];
4179 u8 packet_seq_err[0x20];
4181 u8 reserved_11[0x20];
4183 u8 implied_nak_seq_err[0x20];
4185 u8 reserved_12[0x20];
4187 u8 local_ack_timeout_err[0x20];
4189 u8 reserved_13[0x20];
4191 u8 resp_rnr_nak[0x20];
4193 u8 reserved_14[0x20];
4195 u8 req_rnr_retries_exceeded[0x20];
4197 u8 reserved_15[0x460];
4200 struct mlx5_ifc_query_q_counter_in_bits {
4202 u8 reserved_0[0x10];
4204 u8 reserved_1[0x10];
4207 u8 reserved_2[0x80];
4210 u8 reserved_3[0x1f];
4212 u8 reserved_4[0x18];
4213 u8 counter_set_id[0x8];
4216 struct mlx5_ifc_query_pages_out_bits {
4218 u8 reserved_0[0x18];
4222 u8 reserved_1[0x10];
4223 u8 function_id[0x10];
4229 MLX5_BOOT_PAGES = 0x1,
4230 MLX5_INIT_PAGES = 0x2,
4231 MLX5_POST_INIT_PAGES = 0x3,
4234 struct mlx5_ifc_query_pages_in_bits {
4236 u8 reserved_0[0x10];
4238 u8 reserved_1[0x10];
4241 u8 reserved_2[0x10];
4242 u8 function_id[0x10];
4244 u8 reserved_3[0x20];
4247 struct mlx5_ifc_query_nic_vport_context_out_bits {
4249 u8 reserved_0[0x18];
4253 u8 reserved_1[0x40];
4255 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4258 struct mlx5_ifc_query_nic_vport_context_in_bits {
4260 u8 reserved_0[0x10];
4262 u8 reserved_1[0x10];
4265 u8 other_vport[0x1];
4267 u8 vport_number[0x10];
4270 u8 allowed_list_type[0x3];
4271 u8 reserved_4[0x18];
4274 struct mlx5_ifc_query_mkey_out_bits {
4276 u8 reserved_0[0x18];
4280 u8 reserved_1[0x40];
4282 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4284 u8 reserved_2[0x600];
4286 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4288 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4291 struct mlx5_ifc_query_mkey_in_bits {
4293 u8 reserved_0[0x10];
4295 u8 reserved_1[0x10];
4299 u8 mkey_index[0x18];
4302 u8 reserved_3[0x1f];
4305 struct mlx5_ifc_query_mad_demux_out_bits {
4307 u8 reserved_0[0x18];
4311 u8 reserved_1[0x40];
4313 u8 mad_dumux_parameters_block[0x20];
4316 struct mlx5_ifc_query_mad_demux_in_bits {
4318 u8 reserved_0[0x10];
4320 u8 reserved_1[0x10];
4323 u8 reserved_2[0x40];
4326 struct mlx5_ifc_query_l2_table_entry_out_bits {
4328 u8 reserved_0[0x18];
4332 u8 reserved_1[0xa0];
4334 u8 reserved_2[0x13];
4338 struct mlx5_ifc_mac_address_layout_bits mac_address;
4340 u8 reserved_3[0xc0];
4343 struct mlx5_ifc_query_l2_table_entry_in_bits {
4345 u8 reserved_0[0x10];
4347 u8 reserved_1[0x10];
4350 u8 reserved_2[0x60];
4353 u8 table_index[0x18];
4355 u8 reserved_4[0x140];
4358 struct mlx5_ifc_query_issi_out_bits {
4360 u8 reserved_0[0x18];
4364 u8 reserved_1[0x10];
4365 u8 current_issi[0x10];
4367 u8 reserved_2[0xa0];
4369 u8 supported_issi_reserved[76][0x8];
4370 u8 supported_issi_dw0[0x20];
4373 struct mlx5_ifc_query_issi_in_bits {
4375 u8 reserved_0[0x10];
4377 u8 reserved_1[0x10];
4380 u8 reserved_2[0x40];
4383 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4385 u8 reserved_0[0x18];
4389 u8 reserved_1[0x40];
4391 struct mlx5_ifc_pkey_bits pkey[0];
4394 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4396 u8 reserved_0[0x10];
4398 u8 reserved_1[0x10];
4401 u8 other_vport[0x1];
4404 u8 vport_number[0x10];
4406 u8 reserved_3[0x10];
4407 u8 pkey_index[0x10];
4410 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4412 u8 reserved_0[0x18];
4416 u8 reserved_1[0x20];
4419 u8 reserved_2[0x10];
4421 struct mlx5_ifc_array128_auto_bits gid[0];
4424 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4426 u8 reserved_0[0x10];
4428 u8 reserved_1[0x10];
4431 u8 other_vport[0x1];
4434 u8 vport_number[0x10];
4436 u8 reserved_3[0x10];
4440 struct mlx5_ifc_query_hca_vport_context_out_bits {
4442 u8 reserved_0[0x18];
4446 u8 reserved_1[0x40];
4448 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4451 struct mlx5_ifc_query_hca_vport_context_in_bits {
4453 u8 reserved_0[0x10];
4455 u8 reserved_1[0x10];
4458 u8 other_vport[0x1];
4461 u8 vport_number[0x10];
4463 u8 reserved_3[0x20];
4466 struct mlx5_ifc_query_hca_cap_out_bits {
4468 u8 reserved_0[0x18];
4472 u8 reserved_1[0x40];
4474 union mlx5_ifc_hca_cap_union_bits capability;
4477 struct mlx5_ifc_query_hca_cap_in_bits {
4479 u8 reserved_0[0x10];
4481 u8 reserved_1[0x10];
4484 u8 reserved_2[0x40];
4487 struct mlx5_ifc_query_flow_table_out_bits {
4489 u8 reserved_0[0x18];
4493 u8 reserved_1[0x80];
4500 u8 reserved_4[0x120];
4503 struct mlx5_ifc_query_flow_table_in_bits {
4505 u8 reserved_0[0x10];
4507 u8 reserved_1[0x10];
4510 u8 other_vport[0x1];
4512 u8 vport_number[0x10];
4514 u8 reserved_3[0x20];
4517 u8 reserved_4[0x18];
4522 u8 reserved_6[0x140];
4525 struct mlx5_ifc_query_fte_out_bits {
4527 u8 reserved_0[0x18];
4531 u8 reserved_1[0x1c0];
4533 struct mlx5_ifc_flow_context_bits flow_context;
4536 struct mlx5_ifc_query_fte_in_bits {
4538 u8 reserved_0[0x10];
4540 u8 reserved_1[0x10];
4543 u8 other_vport[0x1];
4545 u8 vport_number[0x10];
4547 u8 reserved_3[0x20];
4550 u8 reserved_4[0x18];
4555 u8 reserved_6[0x40];
4557 u8 flow_index[0x20];
4559 u8 reserved_7[0xe0];
4563 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4564 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4565 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4568 struct mlx5_ifc_query_flow_group_out_bits {
4570 u8 reserved_0[0x18];
4574 u8 reserved_1[0xa0];
4576 u8 start_flow_index[0x20];
4578 u8 reserved_2[0x20];
4580 u8 end_flow_index[0x20];
4582 u8 reserved_3[0xa0];
4584 u8 reserved_4[0x18];
4585 u8 match_criteria_enable[0x8];
4587 struct mlx5_ifc_fte_match_param_bits match_criteria;
4589 u8 reserved_5[0xe00];
4592 struct mlx5_ifc_query_flow_group_in_bits {
4594 u8 reserved_0[0x10];
4596 u8 reserved_1[0x10];
4599 u8 other_vport[0x1];
4601 u8 vport_number[0x10];
4603 u8 reserved_3[0x20];
4606 u8 reserved_4[0x18];
4613 u8 reserved_6[0x120];
4616 struct mlx5_ifc_query_flow_counter_out_bits {
4618 u8 reserved_0[0x18];
4622 u8 reserved_1[0x40];
4624 struct mlx5_ifc_traffic_counter_bits flow_statistics;
4626 u8 reserved_2[0x700];
4629 struct mlx5_ifc_query_flow_counter_in_bits {
4631 u8 reserved_0[0x10];
4633 u8 reserved_1[0x10];
4636 u8 reserved_2[0x80];
4639 u8 reserved_3[0x1f];
4641 u8 reserved_4[0x10];
4642 u8 flow_counter_id[0x10];
4645 struct mlx5_ifc_query_esw_vport_context_out_bits {
4647 u8 reserved_0[0x18];
4651 u8 reserved_1[0x40];
4653 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4656 struct mlx5_ifc_query_esw_vport_context_in_bits {
4658 u8 reserved_0[0x10];
4660 u8 reserved_1[0x10];
4663 u8 other_vport[0x1];
4665 u8 vport_number[0x10];
4667 u8 reserved_3[0x20];
4670 struct mlx5_ifc_query_eq_out_bits {
4672 u8 reserved_0[0x18];
4676 u8 reserved_1[0x40];
4678 struct mlx5_ifc_eqc_bits eq_context_entry;
4680 u8 reserved_2[0x40];
4682 u8 event_bitmask[0x40];
4684 u8 reserved_3[0x580];
4689 struct mlx5_ifc_query_eq_in_bits {
4691 u8 reserved_0[0x10];
4693 u8 reserved_1[0x10];
4696 u8 reserved_2[0x18];
4699 u8 reserved_3[0x20];
4702 struct mlx5_ifc_query_dct_out_bits {
4704 u8 reserved_0[0x18];
4708 u8 reserved_1[0x40];
4710 struct mlx5_ifc_dctc_bits dct_context_entry;
4712 u8 reserved_2[0x180];
4715 struct mlx5_ifc_query_dct_in_bits {
4717 u8 reserved_0[0x10];
4719 u8 reserved_1[0x10];
4725 u8 reserved_3[0x20];
4728 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4730 u8 reserved_0[0x18];
4735 u8 reserved_1[0x1f];
4737 u8 reserved_2[0x160];
4739 struct mlx5_ifc_cmd_pas_bits pas;
4742 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4744 u8 reserved_0[0x10];
4746 u8 reserved_1[0x10];
4749 u8 reserved_2[0x40];
4752 struct mlx5_ifc_query_cq_out_bits {
4754 u8 reserved_0[0x18];
4758 u8 reserved_1[0x40];
4760 struct mlx5_ifc_cqc_bits cq_context;
4762 u8 reserved_2[0x600];
4767 struct mlx5_ifc_query_cq_in_bits {
4769 u8 reserved_0[0x10];
4771 u8 reserved_1[0x10];
4777 u8 reserved_3[0x20];
4780 struct mlx5_ifc_query_cong_status_out_bits {
4782 u8 reserved_0[0x18];
4786 u8 reserved_1[0x20];
4790 u8 reserved_2[0x1e];
4793 struct mlx5_ifc_query_cong_status_in_bits {
4795 u8 reserved_0[0x10];
4797 u8 reserved_1[0x10];
4800 u8 reserved_2[0x18];
4802 u8 cong_protocol[0x4];
4804 u8 reserved_3[0x20];
4807 struct mlx5_ifc_query_cong_statistics_out_bits {
4809 u8 reserved_0[0x18];
4813 u8 reserved_1[0x40];
4819 u8 cnp_ignored_high[0x20];
4821 u8 cnp_ignored_low[0x20];
4823 u8 cnp_handled_high[0x20];
4825 u8 cnp_handled_low[0x20];
4827 u8 reserved_2[0x100];
4829 u8 time_stamp_high[0x20];
4831 u8 time_stamp_low[0x20];
4833 u8 accumulators_period[0x20];
4835 u8 ecn_marked_roce_packets_high[0x20];
4837 u8 ecn_marked_roce_packets_low[0x20];
4839 u8 cnps_sent_high[0x20];
4841 u8 cnps_sent_low[0x20];
4843 u8 reserved_3[0x560];
4846 struct mlx5_ifc_query_cong_statistics_in_bits {
4848 u8 reserved_0[0x10];
4850 u8 reserved_1[0x10];
4854 u8 reserved_2[0x1f];
4856 u8 reserved_3[0x20];
4859 struct mlx5_ifc_query_cong_params_out_bits {
4861 u8 reserved_0[0x18];
4865 u8 reserved_1[0x40];
4867 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4870 struct mlx5_ifc_query_cong_params_in_bits {
4872 u8 reserved_0[0x10];
4874 u8 reserved_1[0x10];
4877 u8 reserved_2[0x1c];
4878 u8 cong_protocol[0x4];
4880 u8 reserved_3[0x20];
4883 struct mlx5_ifc_query_burst_size_out_bits {
4885 u8 reserved_0[0x18];
4889 u8 reserved_1[0x20];
4892 u8 device_burst_size[0x17];
4895 struct mlx5_ifc_query_burst_size_in_bits {
4897 u8 reserved_0[0x10];
4899 u8 reserved_1[0x10];
4902 u8 reserved_2[0x40];
4905 struct mlx5_ifc_query_adapter_out_bits {
4907 u8 reserved_0[0x18];
4911 u8 reserved_1[0x40];
4913 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4916 struct mlx5_ifc_query_adapter_in_bits {
4918 u8 reserved_0[0x10];
4920 u8 reserved_1[0x10];
4923 u8 reserved_2[0x40];
4926 struct mlx5_ifc_qp_2rst_out_bits {
4928 u8 reserved_0[0x18];
4932 u8 reserved_1[0x40];
4935 struct mlx5_ifc_qp_2rst_in_bits {
4937 u8 reserved_0[0x10];
4939 u8 reserved_1[0x10];
4945 u8 reserved_3[0x20];
4948 struct mlx5_ifc_qp_2err_out_bits {
4950 u8 reserved_0[0x18];
4954 u8 reserved_1[0x40];
4957 struct mlx5_ifc_qp_2err_in_bits {
4959 u8 reserved_0[0x10];
4961 u8 reserved_1[0x10];
4967 u8 reserved_3[0x20];
4970 struct mlx5_ifc_para_vport_element_bits {
4971 u8 reserved_at_0[0xc];
4972 u8 traffic_class[0x4];
4973 u8 qos_para_vport_number[0x10];
4976 struct mlx5_ifc_page_fault_resume_out_bits {
4978 u8 reserved_0[0x18];
4982 u8 reserved_1[0x40];
4985 struct mlx5_ifc_page_fault_resume_in_bits {
4987 u8 reserved_0[0x10];
4989 u8 reserved_1[0x10];
4999 u8 reserved_3[0x20];
5002 struct mlx5_ifc_nop_out_bits {
5004 u8 reserved_0[0x18];
5008 u8 reserved_1[0x40];
5011 struct mlx5_ifc_nop_in_bits {
5013 u8 reserved_0[0x10];
5015 u8 reserved_1[0x10];
5018 u8 reserved_2[0x40];
5021 struct mlx5_ifc_modify_vport_state_out_bits {
5023 u8 reserved_0[0x18];
5027 u8 reserved_1[0x40];
5031 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0,
5032 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
5033 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
5037 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0,
5038 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1,
5039 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2,
5042 struct mlx5_ifc_modify_vport_state_in_bits {
5044 u8 reserved_0[0x10];
5046 u8 reserved_1[0x10];
5049 u8 other_vport[0x1];
5051 u8 vport_number[0x10];
5053 u8 reserved_3[0x18];
5054 u8 admin_state[0x4];
5058 struct mlx5_ifc_modify_tis_out_bits {
5060 u8 reserved_0[0x18];
5064 u8 reserved_1[0x40];
5067 struct mlx5_ifc_modify_tis_in_bits {
5069 u8 reserved_0[0x10];
5071 u8 reserved_1[0x10];
5077 u8 reserved_3[0x20];
5079 u8 modify_bitmask[0x40];
5081 u8 reserved_4[0x40];
5083 struct mlx5_ifc_tisc_bits ctx;
5086 struct mlx5_ifc_modify_tir_out_bits {
5088 u8 reserved_0[0x18];
5092 u8 reserved_1[0x40];
5097 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5098 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1
5101 struct mlx5_ifc_modify_tir_in_bits {
5103 u8 reserved_0[0x10];
5105 u8 reserved_1[0x10];
5111 u8 reserved_3[0x20];
5113 u8 modify_bitmask[0x40];
5115 u8 reserved_4[0x40];
5117 struct mlx5_ifc_tirc_bits tir_context;
5120 struct mlx5_ifc_modify_sq_out_bits {
5122 u8 reserved_0[0x18];
5126 u8 reserved_1[0x40];
5129 struct mlx5_ifc_modify_sq_in_bits {
5131 u8 reserved_0[0x10];
5133 u8 reserved_1[0x10];
5140 u8 reserved_3[0x20];
5142 u8 modify_bitmask[0x40];
5144 u8 reserved_4[0x40];
5146 struct mlx5_ifc_sqc_bits ctx;
5149 struct mlx5_ifc_modify_scheduling_element_out_bits {
5151 u8 reserved_at_8[0x18];
5155 u8 reserved_at_40[0x1c0];
5159 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5163 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1,
5164 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2,
5167 struct mlx5_ifc_modify_scheduling_element_in_bits {
5169 u8 reserved_at_10[0x10];
5171 u8 reserved_at_20[0x10];
5174 u8 scheduling_hierarchy[0x8];
5175 u8 reserved_at_48[0x18];
5177 u8 scheduling_element_id[0x20];
5179 u8 reserved_at_80[0x20];
5181 u8 modify_bitmask[0x20];
5183 u8 reserved_at_c0[0x40];
5185 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5187 u8 reserved_at_300[0x100];
5190 struct mlx5_ifc_modify_rqt_out_bits {
5192 u8 reserved_0[0x18];
5196 u8 reserved_1[0x40];
5199 struct mlx5_ifc_modify_rqt_in_bits {
5201 u8 reserved_0[0x10];
5203 u8 reserved_1[0x10];
5209 u8 reserved_3[0x20];
5211 u8 modify_bitmask[0x40];
5213 u8 reserved_4[0x40];
5215 struct mlx5_ifc_rqtc_bits ctx;
5218 struct mlx5_ifc_modify_rq_out_bits {
5220 u8 reserved_0[0x18];
5224 u8 reserved_1[0x40];
5227 struct mlx5_ifc_rq_bitmask_bits {
5231 u8 vlan_strip_disable[0x1];
5235 struct mlx5_ifc_modify_rq_in_bits {
5237 u8 reserved_0[0x10];
5239 u8 reserved_1[0x10];
5246 u8 reserved_3[0x20];
5248 struct mlx5_ifc_rq_bitmask_bits bitmask;
5250 u8 reserved_4[0x40];
5252 struct mlx5_ifc_rqc_bits ctx;
5255 struct mlx5_ifc_modify_rmp_out_bits {
5257 u8 reserved_0[0x18];
5261 u8 reserved_1[0x40];
5264 struct mlx5_ifc_rmp_bitmask_bits {
5271 struct mlx5_ifc_modify_rmp_in_bits {
5273 u8 reserved_0[0x10];
5275 u8 reserved_1[0x10];
5282 u8 reserved_3[0x20];
5284 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5286 u8 reserved_4[0x40];
5288 struct mlx5_ifc_rmpc_bits ctx;
5291 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5293 u8 reserved_0[0x18];
5297 u8 reserved_1[0x40];
5300 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5301 u8 reserved_0[0x14];
5302 u8 disable_uc_local_lb[0x1];
5303 u8 disable_mc_local_lb[0x1];
5306 u8 min_wqe_inline_mode[0x1];
5308 u8 change_event[0x1];
5310 u8 permanent_address[0x1];
5311 u8 addresses_list[0x1];
5316 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5318 u8 reserved_0[0x10];
5320 u8 reserved_1[0x10];
5323 u8 other_vport[0x1];
5325 u8 vport_number[0x10];
5327 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5329 u8 reserved_3[0x780];
5331 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5334 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5336 u8 reserved_0[0x18];
5340 u8 reserved_1[0x40];
5343 struct mlx5_ifc_grh_bits {
5345 u8 traffic_class[8];
5347 u8 payload_length[16];
5354 struct mlx5_ifc_bth_bits {
5368 struct mlx5_ifc_aeth_bits {
5373 struct mlx5_ifc_dceth_bits {
5380 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5382 u8 reserved_0[0x10];
5384 u8 reserved_1[0x10];
5387 u8 other_vport[0x1];
5390 u8 vport_number[0x10];
5392 u8 reserved_3[0x20];
5394 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5397 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5399 u8 reserved_0[0x18];
5403 u8 reserved_1[0x40];
5406 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5408 u8 vport_cvlan_insert[0x1];
5409 u8 vport_svlan_insert[0x1];
5410 u8 vport_cvlan_strip[0x1];
5411 u8 vport_svlan_strip[0x1];
5414 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5416 u8 reserved_0[0x10];
5418 u8 reserved_1[0x10];
5421 u8 other_vport[0x1];
5423 u8 vport_number[0x10];
5425 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5427 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5430 struct mlx5_ifc_modify_cq_out_bits {
5432 u8 reserved_0[0x18];
5436 u8 reserved_1[0x40];
5440 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5441 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5444 struct mlx5_ifc_modify_cq_in_bits {
5446 u8 reserved_0[0x10];
5448 u8 reserved_1[0x10];
5454 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5456 struct mlx5_ifc_cqc_bits cq_context;
5458 u8 reserved_3[0x600];
5463 struct mlx5_ifc_modify_cong_status_out_bits {
5465 u8 reserved_0[0x18];
5469 u8 reserved_1[0x40];
5472 struct mlx5_ifc_modify_cong_status_in_bits {
5474 u8 reserved_0[0x10];
5476 u8 reserved_1[0x10];
5479 u8 reserved_2[0x18];
5481 u8 cong_protocol[0x4];
5485 u8 reserved_3[0x1e];
5488 struct mlx5_ifc_modify_cong_params_out_bits {
5490 u8 reserved_0[0x18];
5494 u8 reserved_1[0x40];
5497 struct mlx5_ifc_modify_cong_params_in_bits {
5499 u8 reserved_0[0x10];
5501 u8 reserved_1[0x10];
5504 u8 reserved_2[0x1c];
5505 u8 cong_protocol[0x4];
5507 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5509 u8 reserved_3[0x80];
5511 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5514 struct mlx5_ifc_manage_pages_out_bits {
5516 u8 reserved_0[0x18];
5520 u8 output_num_entries[0x20];
5522 u8 reserved_1[0x20];
5528 MLX5_PAGES_CANT_GIVE = 0x0,
5529 MLX5_PAGES_GIVE = 0x1,
5530 MLX5_PAGES_TAKE = 0x2,
5533 struct mlx5_ifc_manage_pages_in_bits {
5535 u8 reserved_0[0x10];
5537 u8 reserved_1[0x10];
5540 u8 reserved_2[0x10];
5541 u8 function_id[0x10];
5543 u8 input_num_entries[0x20];
5548 struct mlx5_ifc_mad_ifc_out_bits {
5550 u8 reserved_0[0x18];
5554 u8 reserved_1[0x40];
5556 u8 response_mad_packet[256][0x8];
5559 struct mlx5_ifc_mad_ifc_in_bits {
5561 u8 reserved_0[0x10];
5563 u8 reserved_1[0x10];
5566 u8 remote_lid[0x10];
5570 u8 reserved_3[0x20];
5575 struct mlx5_ifc_init_hca_out_bits {
5577 u8 reserved_0[0x18];
5581 u8 reserved_1[0x40];
5585 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0,
5586 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1,
5589 struct mlx5_ifc_init_hca_in_bits {
5591 u8 reserved_0[0x10];
5593 u8 reserved_1[0x10];
5596 u8 reserved_2[0x40];
5599 struct mlx5_ifc_init2rtr_qp_out_bits {
5601 u8 reserved_0[0x18];
5605 u8 reserved_1[0x40];
5608 struct mlx5_ifc_init2rtr_qp_in_bits {
5610 u8 reserved_0[0x10];
5612 u8 reserved_1[0x10];
5618 u8 reserved_3[0x20];
5620 u8 opt_param_mask[0x20];
5622 u8 reserved_4[0x20];
5624 struct mlx5_ifc_qpc_bits qpc;
5626 u8 reserved_5[0x80];
5629 struct mlx5_ifc_init2init_qp_out_bits {
5631 u8 reserved_0[0x18];
5635 u8 reserved_1[0x40];
5638 struct mlx5_ifc_init2init_qp_in_bits {
5640 u8 reserved_0[0x10];
5642 u8 reserved_1[0x10];
5648 u8 reserved_3[0x20];
5650 u8 opt_param_mask[0x20];
5652 u8 reserved_4[0x20];
5654 struct mlx5_ifc_qpc_bits qpc;
5656 u8 reserved_5[0x80];
5659 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5661 u8 reserved_0[0x18];
5665 u8 reserved_1[0x40];
5667 u8 packet_headers_log[128][0x8];
5669 u8 packet_syndrome[64][0x8];
5672 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5674 u8 reserved_0[0x10];
5676 u8 reserved_1[0x10];
5679 u8 reserved_2[0x40];
5682 struct mlx5_ifc_gen_eqe_in_bits {
5684 u8 reserved_0[0x10];
5686 u8 reserved_1[0x10];
5689 u8 reserved_2[0x18];
5692 u8 reserved_3[0x20];
5697 struct mlx5_ifc_gen_eq_out_bits {
5699 u8 reserved_0[0x18];
5703 u8 reserved_1[0x40];
5706 struct mlx5_ifc_enable_hca_out_bits {
5708 u8 reserved_0[0x18];
5712 u8 reserved_1[0x20];
5715 struct mlx5_ifc_enable_hca_in_bits {
5717 u8 reserved_0[0x10];
5719 u8 reserved_1[0x10];
5722 u8 reserved_2[0x10];
5723 u8 function_id[0x10];
5725 u8 reserved_3[0x20];
5728 struct mlx5_ifc_drain_dct_out_bits {
5730 u8 reserved_0[0x18];
5734 u8 reserved_1[0x40];
5737 struct mlx5_ifc_drain_dct_in_bits {
5739 u8 reserved_0[0x10];
5741 u8 reserved_1[0x10];
5747 u8 reserved_3[0x20];
5750 struct mlx5_ifc_disable_hca_out_bits {
5752 u8 reserved_0[0x18];
5756 u8 reserved_1[0x20];
5759 struct mlx5_ifc_disable_hca_in_bits {
5761 u8 reserved_0[0x10];
5763 u8 reserved_1[0x10];
5766 u8 reserved_2[0x10];
5767 u8 function_id[0x10];
5769 u8 reserved_3[0x20];
5772 struct mlx5_ifc_detach_from_mcg_out_bits {
5774 u8 reserved_0[0x18];
5778 u8 reserved_1[0x40];
5781 struct mlx5_ifc_detach_from_mcg_in_bits {
5783 u8 reserved_0[0x10];
5785 u8 reserved_1[0x10];
5791 u8 reserved_3[0x20];
5793 u8 multicast_gid[16][0x8];
5796 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5798 u8 reserved_0[0x18];
5802 u8 reserved_1[0x40];
5805 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5807 u8 reserved_0[0x10];
5809 u8 reserved_1[0x10];
5815 u8 reserved_3[0x20];
5818 struct mlx5_ifc_destroy_tis_out_bits {
5820 u8 reserved_0[0x18];
5824 u8 reserved_1[0x40];
5827 struct mlx5_ifc_destroy_tis_in_bits {
5829 u8 reserved_0[0x10];
5831 u8 reserved_1[0x10];
5837 u8 reserved_3[0x20];
5840 struct mlx5_ifc_destroy_tir_out_bits {
5842 u8 reserved_0[0x18];
5846 u8 reserved_1[0x40];
5849 struct mlx5_ifc_destroy_tir_in_bits {
5851 u8 reserved_0[0x10];
5853 u8 reserved_1[0x10];
5859 u8 reserved_3[0x20];
5862 struct mlx5_ifc_destroy_srq_out_bits {
5864 u8 reserved_0[0x18];
5868 u8 reserved_1[0x40];
5871 struct mlx5_ifc_destroy_srq_in_bits {
5873 u8 reserved_0[0x10];
5875 u8 reserved_1[0x10];
5881 u8 reserved_3[0x20];
5884 struct mlx5_ifc_destroy_sq_out_bits {
5886 u8 reserved_0[0x18];
5890 u8 reserved_1[0x40];
5893 struct mlx5_ifc_destroy_sq_in_bits {
5895 u8 reserved_0[0x10];
5897 u8 reserved_1[0x10];
5903 u8 reserved_3[0x20];
5906 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5908 u8 reserved_at_8[0x18];
5912 u8 reserved_at_40[0x1c0];
5916 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5919 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5921 u8 reserved_at_10[0x10];
5923 u8 reserved_at_20[0x10];
5926 u8 scheduling_hierarchy[0x8];
5927 u8 reserved_at_48[0x18];
5929 u8 scheduling_element_id[0x20];
5931 u8 reserved_at_80[0x180];
5934 struct mlx5_ifc_destroy_rqt_out_bits {
5936 u8 reserved_0[0x18];
5940 u8 reserved_1[0x40];
5943 struct mlx5_ifc_destroy_rqt_in_bits {
5945 u8 reserved_0[0x10];
5947 u8 reserved_1[0x10];
5953 u8 reserved_3[0x20];
5956 struct mlx5_ifc_destroy_rq_out_bits {
5958 u8 reserved_0[0x18];
5962 u8 reserved_1[0x40];
5965 struct mlx5_ifc_destroy_rq_in_bits {
5967 u8 reserved_0[0x10];
5969 u8 reserved_1[0x10];
5975 u8 reserved_3[0x20];
5978 struct mlx5_ifc_destroy_rmp_out_bits {
5980 u8 reserved_0[0x18];
5984 u8 reserved_1[0x40];
5987 struct mlx5_ifc_destroy_rmp_in_bits {
5989 u8 reserved_0[0x10];
5991 u8 reserved_1[0x10];
5997 u8 reserved_3[0x20];
6000 struct mlx5_ifc_destroy_qp_out_bits {
6002 u8 reserved_0[0x18];
6006 u8 reserved_1[0x40];
6009 struct mlx5_ifc_destroy_qp_in_bits {
6011 u8 reserved_0[0x10];
6013 u8 reserved_1[0x10];
6019 u8 reserved_3[0x20];
6022 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6024 u8 reserved_at_8[0x18];
6028 u8 reserved_at_40[0x1c0];
6031 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6033 u8 reserved_at_10[0x10];
6035 u8 reserved_at_20[0x10];
6038 u8 reserved_at_40[0x20];
6040 u8 reserved_at_60[0x10];
6041 u8 qos_para_vport_number[0x10];
6043 u8 reserved_at_80[0x180];
6046 struct mlx5_ifc_destroy_psv_out_bits {
6048 u8 reserved_0[0x18];
6052 u8 reserved_1[0x40];
6055 struct mlx5_ifc_destroy_psv_in_bits {
6057 u8 reserved_0[0x10];
6059 u8 reserved_1[0x10];
6065 u8 reserved_3[0x20];
6068 struct mlx5_ifc_destroy_mkey_out_bits {
6070 u8 reserved_0[0x18];
6074 u8 reserved_1[0x40];
6077 struct mlx5_ifc_destroy_mkey_in_bits {
6079 u8 reserved_0[0x10];
6081 u8 reserved_1[0x10];
6085 u8 mkey_index[0x18];
6087 u8 reserved_3[0x20];
6090 struct mlx5_ifc_destroy_flow_table_out_bits {
6092 u8 reserved_0[0x18];
6096 u8 reserved_1[0x40];
6099 struct mlx5_ifc_destroy_flow_table_in_bits {
6101 u8 reserved_0[0x10];
6103 u8 reserved_1[0x10];
6106 u8 other_vport[0x1];
6108 u8 vport_number[0x10];
6110 u8 reserved_3[0x20];
6113 u8 reserved_4[0x18];
6118 u8 reserved_6[0x140];
6121 struct mlx5_ifc_destroy_flow_group_out_bits {
6123 u8 reserved_0[0x18];
6127 u8 reserved_1[0x40];
6130 struct mlx5_ifc_destroy_flow_group_in_bits {
6132 u8 reserved_0[0x10];
6134 u8 reserved_1[0x10];
6137 u8 other_vport[0x1];
6139 u8 vport_number[0x10];
6141 u8 reserved_3[0x20];
6144 u8 reserved_4[0x18];
6151 u8 reserved_6[0x120];
6154 struct mlx5_ifc_destroy_eq_out_bits {
6156 u8 reserved_0[0x18];
6160 u8 reserved_1[0x40];
6163 struct mlx5_ifc_destroy_eq_in_bits {
6165 u8 reserved_0[0x10];
6167 u8 reserved_1[0x10];
6170 u8 reserved_2[0x18];
6173 u8 reserved_3[0x20];
6176 struct mlx5_ifc_destroy_dct_out_bits {
6178 u8 reserved_0[0x18];
6182 u8 reserved_1[0x40];
6185 struct mlx5_ifc_destroy_dct_in_bits {
6187 u8 reserved_0[0x10];
6189 u8 reserved_1[0x10];
6195 u8 reserved_3[0x20];
6198 struct mlx5_ifc_destroy_cq_out_bits {
6200 u8 reserved_0[0x18];
6204 u8 reserved_1[0x40];
6207 struct mlx5_ifc_destroy_cq_in_bits {
6209 u8 reserved_0[0x10];
6211 u8 reserved_1[0x10];
6217 u8 reserved_3[0x20];
6220 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6222 u8 reserved_0[0x18];
6226 u8 reserved_1[0x40];
6229 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6231 u8 reserved_0[0x10];
6233 u8 reserved_1[0x10];
6236 u8 reserved_2[0x20];
6238 u8 reserved_3[0x10];
6239 u8 vxlan_udp_port[0x10];
6242 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6244 u8 reserved_0[0x18];
6248 u8 reserved_1[0x40];
6251 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6253 u8 reserved_0[0x10];
6255 u8 reserved_1[0x10];
6258 u8 reserved_2[0x60];
6261 u8 table_index[0x18];
6263 u8 reserved_4[0x140];
6266 struct mlx5_ifc_delete_fte_out_bits {
6268 u8 reserved_0[0x18];
6272 u8 reserved_1[0x40];
6275 struct mlx5_ifc_delete_fte_in_bits {
6277 u8 reserved_0[0x10];
6279 u8 reserved_1[0x10];
6282 u8 other_vport[0x1];
6284 u8 vport_number[0x10];
6286 u8 reserved_3[0x20];
6289 u8 reserved_4[0x18];
6294 u8 reserved_6[0x40];
6296 u8 flow_index[0x20];
6298 u8 reserved_7[0xe0];
6301 struct mlx5_ifc_dealloc_xrcd_out_bits {
6303 u8 reserved_0[0x18];
6307 u8 reserved_1[0x40];
6310 struct mlx5_ifc_dealloc_xrcd_in_bits {
6312 u8 reserved_0[0x10];
6314 u8 reserved_1[0x10];
6320 u8 reserved_3[0x20];
6323 struct mlx5_ifc_dealloc_uar_out_bits {
6325 u8 reserved_0[0x18];
6329 u8 reserved_1[0x40];
6332 struct mlx5_ifc_dealloc_uar_in_bits {
6334 u8 reserved_0[0x10];
6336 u8 reserved_1[0x10];
6342 u8 reserved_3[0x20];
6345 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6347 u8 reserved_0[0x18];
6351 u8 reserved_1[0x40];
6354 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6356 u8 reserved_0[0x10];
6358 u8 reserved_1[0x10];
6362 u8 transport_domain[0x18];
6364 u8 reserved_3[0x20];
6367 struct mlx5_ifc_dealloc_q_counter_out_bits {
6369 u8 reserved_0[0x18];
6373 u8 reserved_1[0x40];
6376 struct mlx5_ifc_counter_id_bits {
6378 u8 counter_id[0x10];
6381 struct mlx5_ifc_diagnostic_params_context_bits {
6382 u8 num_of_counters[0x10];
6384 u8 log_num_of_samples[0x8];
6392 u8 reserved_3[0x12];
6393 u8 log_sample_period[0x8];
6395 u8 reserved_4[0x80];
6397 struct mlx5_ifc_counter_id_bits counter_id[0];
6400 struct mlx5_ifc_set_diagnostic_params_in_bits {
6402 u8 reserved_0[0x10];
6404 u8 reserved_1[0x10];
6407 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6410 struct mlx5_ifc_set_diagnostic_params_out_bits {
6412 u8 reserved_0[0x18];
6416 u8 reserved_1[0x40];
6419 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6421 u8 reserved_0[0x10];
6423 u8 reserved_1[0x10];
6426 u8 num_of_samples[0x10];
6427 u8 sample_index[0x10];
6429 u8 reserved_2[0x20];
6432 struct mlx5_ifc_diagnostic_counter_bits {
6433 u8 counter_id[0x10];
6436 u8 time_stamp_31_0[0x20];
6438 u8 counter_value_h[0x20];
6440 u8 counter_value_l[0x20];
6443 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6445 u8 reserved_0[0x18];
6449 u8 reserved_1[0x40];
6451 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6454 struct mlx5_ifc_dealloc_q_counter_in_bits {
6456 u8 reserved_0[0x10];
6458 u8 reserved_1[0x10];
6461 u8 reserved_2[0x18];
6462 u8 counter_set_id[0x8];
6464 u8 reserved_3[0x20];
6467 struct mlx5_ifc_dealloc_pd_out_bits {
6469 u8 reserved_0[0x18];
6473 u8 reserved_1[0x40];
6476 struct mlx5_ifc_dealloc_pd_in_bits {
6478 u8 reserved_0[0x10];
6480 u8 reserved_1[0x10];
6486 u8 reserved_3[0x20];
6489 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6491 u8 reserved_0[0x18];
6495 u8 reserved_1[0x40];
6498 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6500 u8 reserved_0[0x10];
6502 u8 reserved_1[0x10];
6505 u8 reserved_2[0x10];
6506 u8 flow_counter_id[0x10];
6508 u8 reserved_3[0x20];
6511 struct mlx5_ifc_deactivate_tracer_out_bits {
6513 u8 reserved_0[0x18];
6517 u8 reserved_1[0x40];
6520 struct mlx5_ifc_deactivate_tracer_in_bits {
6522 u8 reserved_0[0x10];
6524 u8 reserved_1[0x10];
6529 u8 reserved_2[0x20];
6532 struct mlx5_ifc_create_xrc_srq_out_bits {
6534 u8 reserved_0[0x18];
6541 u8 reserved_2[0x20];
6544 struct mlx5_ifc_create_xrc_srq_in_bits {
6546 u8 reserved_0[0x10];
6548 u8 reserved_1[0x10];
6551 u8 reserved_2[0x40];
6553 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6555 u8 reserved_3[0x600];
6560 struct mlx5_ifc_create_tis_out_bits {
6562 u8 reserved_0[0x18];
6569 u8 reserved_2[0x20];
6572 struct mlx5_ifc_create_tis_in_bits {
6574 u8 reserved_0[0x10];
6576 u8 reserved_1[0x10];
6579 u8 reserved_2[0xc0];
6581 struct mlx5_ifc_tisc_bits ctx;
6584 struct mlx5_ifc_create_tir_out_bits {
6586 u8 reserved_0[0x18];
6593 u8 reserved_2[0x20];
6596 struct mlx5_ifc_create_tir_in_bits {
6598 u8 reserved_0[0x10];
6600 u8 reserved_1[0x10];
6603 u8 reserved_2[0xc0];
6605 struct mlx5_ifc_tirc_bits tir_context;
6608 struct mlx5_ifc_create_srq_out_bits {
6610 u8 reserved_0[0x18];
6617 u8 reserved_2[0x20];
6620 struct mlx5_ifc_create_srq_in_bits {
6622 u8 reserved_0[0x10];
6624 u8 reserved_1[0x10];
6627 u8 reserved_2[0x40];
6629 struct mlx5_ifc_srqc_bits srq_context_entry;
6631 u8 reserved_3[0x600];
6636 struct mlx5_ifc_create_sq_out_bits {
6638 u8 reserved_0[0x18];
6645 u8 reserved_2[0x20];
6648 struct mlx5_ifc_create_sq_in_bits {
6650 u8 reserved_0[0x10];
6652 u8 reserved_1[0x10];
6655 u8 reserved_2[0xc0];
6657 struct mlx5_ifc_sqc_bits ctx;
6660 struct mlx5_ifc_create_scheduling_element_out_bits {
6662 u8 reserved_at_8[0x18];
6666 u8 reserved_at_40[0x40];
6668 u8 scheduling_element_id[0x20];
6670 u8 reserved_at_a0[0x160];
6674 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6677 struct mlx5_ifc_create_scheduling_element_in_bits {
6679 u8 reserved_at_10[0x10];
6681 u8 reserved_at_20[0x10];
6684 u8 scheduling_hierarchy[0x8];
6685 u8 reserved_at_48[0x18];
6687 u8 reserved_at_60[0xa0];
6689 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6691 u8 reserved_at_300[0x100];
6694 struct mlx5_ifc_create_rqt_out_bits {
6696 u8 reserved_0[0x18];
6703 u8 reserved_2[0x20];
6706 struct mlx5_ifc_create_rqt_in_bits {
6708 u8 reserved_0[0x10];
6710 u8 reserved_1[0x10];
6713 u8 reserved_2[0xc0];
6715 struct mlx5_ifc_rqtc_bits rqt_context;
6718 struct mlx5_ifc_create_rq_out_bits {
6720 u8 reserved_0[0x18];
6727 u8 reserved_2[0x20];
6730 struct mlx5_ifc_create_rq_in_bits {
6732 u8 reserved_0[0x10];
6734 u8 reserved_1[0x10];
6737 u8 reserved_2[0xc0];
6739 struct mlx5_ifc_rqc_bits ctx;
6742 struct mlx5_ifc_create_rmp_out_bits {
6744 u8 reserved_0[0x18];
6751 u8 reserved_2[0x20];
6754 struct mlx5_ifc_create_rmp_in_bits {
6756 u8 reserved_0[0x10];
6758 u8 reserved_1[0x10];
6761 u8 reserved_2[0xc0];
6763 struct mlx5_ifc_rmpc_bits ctx;
6766 struct mlx5_ifc_create_qp_out_bits {
6768 u8 reserved_0[0x18];
6775 u8 reserved_2[0x20];
6778 struct mlx5_ifc_create_qp_in_bits {
6780 u8 reserved_0[0x10];
6782 u8 reserved_1[0x10];
6788 u8 reserved_3[0x20];
6790 u8 opt_param_mask[0x20];
6792 u8 reserved_4[0x20];
6794 struct mlx5_ifc_qpc_bits qpc;
6796 u8 reserved_5[0x80];
6801 struct mlx5_ifc_create_qos_para_vport_out_bits {
6803 u8 reserved_at_8[0x18];
6807 u8 reserved_at_40[0x20];
6809 u8 reserved_at_60[0x10];
6810 u8 qos_para_vport_number[0x10];
6812 u8 reserved_at_80[0x180];
6815 struct mlx5_ifc_create_qos_para_vport_in_bits {
6817 u8 reserved_at_10[0x10];
6819 u8 reserved_at_20[0x10];
6822 u8 reserved_at_40[0x1c0];
6825 struct mlx5_ifc_create_psv_out_bits {
6827 u8 reserved_0[0x18];
6831 u8 reserved_1[0x40];
6834 u8 psv0_index[0x18];
6837 u8 psv1_index[0x18];
6840 u8 psv2_index[0x18];
6843 u8 psv3_index[0x18];
6846 struct mlx5_ifc_create_psv_in_bits {
6848 u8 reserved_0[0x10];
6850 u8 reserved_1[0x10];
6857 u8 reserved_3[0x20];
6860 struct mlx5_ifc_create_mkey_out_bits {
6862 u8 reserved_0[0x18];
6867 u8 mkey_index[0x18];
6869 u8 reserved_2[0x20];
6872 struct mlx5_ifc_create_mkey_in_bits {
6874 u8 reserved_0[0x10];
6876 u8 reserved_1[0x10];
6879 u8 reserved_2[0x20];
6882 u8 reserved_3[0x1f];
6884 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6886 u8 reserved_4[0x80];
6888 u8 translations_octword_actual_size[0x20];
6890 u8 reserved_5[0x560];
6892 u8 klm_pas_mtt[0][0x20];
6895 struct mlx5_ifc_create_flow_table_out_bits {
6897 u8 reserved_0[0x18];
6904 u8 reserved_2[0x20];
6907 struct mlx5_ifc_create_flow_table_in_bits {
6909 u8 reserved_0[0x10];
6911 u8 reserved_1[0x10];
6914 u8 other_vport[0x1];
6916 u8 vport_number[0x10];
6918 u8 reserved_3[0x20];
6921 u8 reserved_4[0x18];
6923 u8 reserved_5[0x20];
6930 u8 reserved_8[0x120];
6933 struct mlx5_ifc_create_flow_group_out_bits {
6935 u8 reserved_0[0x18];
6942 u8 reserved_2[0x20];
6946 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6947 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6948 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6951 struct mlx5_ifc_create_flow_group_in_bits {
6953 u8 reserved_0[0x10];
6955 u8 reserved_1[0x10];
6958 u8 other_vport[0x1];
6960 u8 vport_number[0x10];
6962 u8 reserved_3[0x20];
6965 u8 reserved_4[0x18];
6970 u8 reserved_6[0x20];
6972 u8 start_flow_index[0x20];
6974 u8 reserved_7[0x20];
6976 u8 end_flow_index[0x20];
6978 u8 reserved_8[0xa0];
6980 u8 reserved_9[0x18];
6981 u8 match_criteria_enable[0x8];
6983 struct mlx5_ifc_fte_match_param_bits match_criteria;
6985 u8 reserved_10[0xe00];
6988 struct mlx5_ifc_create_eq_out_bits {
6990 u8 reserved_0[0x18];
6994 u8 reserved_1[0x18];
6997 u8 reserved_2[0x20];
7000 struct mlx5_ifc_create_eq_in_bits {
7002 u8 reserved_0[0x10];
7004 u8 reserved_1[0x10];
7007 u8 reserved_2[0x40];
7009 struct mlx5_ifc_eqc_bits eq_context_entry;
7011 u8 reserved_3[0x40];
7013 u8 event_bitmask[0x40];
7015 u8 reserved_4[0x580];
7020 struct mlx5_ifc_create_dct_out_bits {
7022 u8 reserved_0[0x18];
7029 u8 reserved_2[0x20];
7032 struct mlx5_ifc_create_dct_in_bits {
7034 u8 reserved_0[0x10];
7036 u8 reserved_1[0x10];
7039 u8 reserved_2[0x40];
7041 struct mlx5_ifc_dctc_bits dct_context_entry;
7043 u8 reserved_3[0x180];
7046 struct mlx5_ifc_create_cq_out_bits {
7048 u8 reserved_0[0x18];
7055 u8 reserved_2[0x20];
7058 struct mlx5_ifc_create_cq_in_bits {
7060 u8 reserved_0[0x10];
7062 u8 reserved_1[0x10];
7065 u8 reserved_2[0x40];
7067 struct mlx5_ifc_cqc_bits cq_context;
7069 u8 reserved_3[0x600];
7074 struct mlx5_ifc_config_int_moderation_out_bits {
7076 u8 reserved_0[0x18];
7082 u8 int_vector[0x10];
7084 u8 reserved_2[0x20];
7088 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7089 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7092 struct mlx5_ifc_config_int_moderation_in_bits {
7094 u8 reserved_0[0x10];
7096 u8 reserved_1[0x10];
7101 u8 int_vector[0x10];
7103 u8 reserved_3[0x20];
7106 struct mlx5_ifc_attach_to_mcg_out_bits {
7108 u8 reserved_0[0x18];
7112 u8 reserved_1[0x40];
7115 struct mlx5_ifc_attach_to_mcg_in_bits {
7117 u8 reserved_0[0x10];
7119 u8 reserved_1[0x10];
7125 u8 reserved_3[0x20];
7127 u8 multicast_gid[16][0x8];
7130 struct mlx5_ifc_arm_xrc_srq_out_bits {
7132 u8 reserved_0[0x18];
7136 u8 reserved_1[0x40];
7140 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7143 struct mlx5_ifc_arm_xrc_srq_in_bits {
7145 u8 reserved_0[0x10];
7147 u8 reserved_1[0x10];
7153 u8 reserved_3[0x10];
7157 struct mlx5_ifc_arm_rq_out_bits {
7159 u8 reserved_0[0x18];
7163 u8 reserved_1[0x40];
7167 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7170 struct mlx5_ifc_arm_rq_in_bits {
7172 u8 reserved_0[0x10];
7174 u8 reserved_1[0x10];
7178 u8 srq_number[0x18];
7180 u8 reserved_3[0x10];
7184 struct mlx5_ifc_arm_dct_out_bits {
7186 u8 reserved_0[0x18];
7190 u8 reserved_1[0x40];
7193 struct mlx5_ifc_arm_dct_in_bits {
7195 u8 reserved_0[0x10];
7197 u8 reserved_1[0x10];
7203 u8 reserved_3[0x20];
7206 struct mlx5_ifc_alloc_xrcd_out_bits {
7208 u8 reserved_0[0x18];
7215 u8 reserved_2[0x20];
7218 struct mlx5_ifc_alloc_xrcd_in_bits {
7220 u8 reserved_0[0x10];
7222 u8 reserved_1[0x10];
7225 u8 reserved_2[0x40];
7228 struct mlx5_ifc_alloc_uar_out_bits {
7230 u8 reserved_0[0x18];
7237 u8 reserved_2[0x20];
7240 struct mlx5_ifc_alloc_uar_in_bits {
7242 u8 reserved_0[0x10];
7244 u8 reserved_1[0x10];
7247 u8 reserved_2[0x40];
7250 struct mlx5_ifc_alloc_transport_domain_out_bits {
7252 u8 reserved_0[0x18];
7257 u8 transport_domain[0x18];
7259 u8 reserved_2[0x20];
7262 struct mlx5_ifc_alloc_transport_domain_in_bits {
7264 u8 reserved_0[0x10];
7266 u8 reserved_1[0x10];
7269 u8 reserved_2[0x40];
7272 struct mlx5_ifc_alloc_q_counter_out_bits {
7274 u8 reserved_0[0x18];
7278 u8 reserved_1[0x18];
7279 u8 counter_set_id[0x8];
7281 u8 reserved_2[0x20];
7284 struct mlx5_ifc_alloc_q_counter_in_bits {
7286 u8 reserved_0[0x10];
7288 u8 reserved_1[0x10];
7291 u8 reserved_2[0x40];
7294 struct mlx5_ifc_alloc_pd_out_bits {
7296 u8 reserved_0[0x18];
7303 u8 reserved_2[0x20];
7306 struct mlx5_ifc_alloc_pd_in_bits {
7308 u8 reserved_0[0x10];
7310 u8 reserved_1[0x10];
7313 u8 reserved_2[0x40];
7316 struct mlx5_ifc_alloc_flow_counter_out_bits {
7318 u8 reserved_0[0x18];
7322 u8 reserved_1[0x10];
7323 u8 flow_counter_id[0x10];
7325 u8 reserved_2[0x20];
7328 struct mlx5_ifc_alloc_flow_counter_in_bits {
7330 u8 reserved_0[0x10];
7332 u8 reserved_1[0x10];
7335 u8 reserved_2[0x40];
7338 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7340 u8 reserved_0[0x18];
7344 u8 reserved_1[0x40];
7347 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7349 u8 reserved_0[0x10];
7351 u8 reserved_1[0x10];
7354 u8 reserved_2[0x20];
7356 u8 reserved_3[0x10];
7357 u8 vxlan_udp_port[0x10];
7360 struct mlx5_ifc_activate_tracer_out_bits {
7362 u8 reserved_0[0x18];
7366 u8 reserved_1[0x40];
7369 struct mlx5_ifc_activate_tracer_in_bits {
7371 u8 reserved_0[0x10];
7373 u8 reserved_1[0x10];
7378 u8 reserved_2[0x20];
7381 struct mlx5_ifc_set_rate_limit_out_bits {
7383 u8 reserved_at_8[0x18];
7387 u8 reserved_at_40[0x40];
7390 struct mlx5_ifc_set_rate_limit_in_bits {
7392 u8 reserved_at_10[0x10];
7394 u8 reserved_at_20[0x10];
7397 u8 reserved_at_40[0x10];
7398 u8 rate_limit_index[0x10];
7400 u8 reserved_at_60[0x20];
7402 u8 rate_limit[0x20];
7403 u8 burst_upper_bound[0x20];
7406 struct mlx5_ifc_access_register_out_bits {
7408 u8 reserved_0[0x18];
7412 u8 reserved_1[0x40];
7414 u8 register_data[0][0x20];
7418 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7419 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7422 struct mlx5_ifc_access_register_in_bits {
7424 u8 reserved_0[0x10];
7426 u8 reserved_1[0x10];
7429 u8 reserved_2[0x10];
7430 u8 register_id[0x10];
7434 u8 register_data[0][0x20];
7437 struct mlx5_ifc_sltp_reg_bits {
7446 u8 reserved_2[0x20];
7455 u8 ob_preemp_mode[0x4];
7459 u8 reserved_5[0x20];
7462 struct mlx5_ifc_slrp_reg_bits {
7472 u8 reserved_2[0x11];
7488 u8 mixerbias_tap_amp[0x8];
7492 u8 ffe_tap_offset0[0x8];
7493 u8 ffe_tap_offset1[0x8];
7494 u8 slicer_offset0[0x10];
7496 u8 mixer_offset0[0x10];
7497 u8 mixer_offset1[0x10];
7499 u8 mixerbgn_inp[0x8];
7500 u8 mixerbgn_inn[0x8];
7501 u8 mixerbgn_refp[0x8];
7502 u8 mixerbgn_refn[0x8];
7504 u8 sel_slicer_lctrl_h[0x1];
7505 u8 sel_slicer_lctrl_l[0x1];
7507 u8 ref_mixer_vreg[0x5];
7508 u8 slicer_gctrl[0x8];
7509 u8 lctrl_input[0x8];
7510 u8 mixer_offset_cm1[0x8];
7512 u8 common_mode[0x6];
7514 u8 mixer_offset_cm0[0x9];
7516 u8 slicer_offset_cm[0x9];
7519 struct mlx5_ifc_slrg_reg_bits {
7528 u8 time_to_link_up[0x10];
7530 u8 grade_lane_speed[0x4];
7532 u8 grade_version[0x8];
7536 u8 height_grade_type[0x4];
7537 u8 height_grade[0x18];
7542 u8 reserved_4[0x10];
7543 u8 height_sigma[0x10];
7545 u8 reserved_5[0x20];
7548 u8 phase_grade_type[0x4];
7549 u8 phase_grade[0x18];
7552 u8 phase_eo_pos[0x8];
7554 u8 phase_eo_neg[0x8];
7556 u8 ffe_set_tested[0x10];
7557 u8 test_errors_per_lane[0x10];
7560 struct mlx5_ifc_pvlc_reg_bits {
7563 u8 reserved_1[0x10];
7565 u8 reserved_2[0x1c];
7568 u8 reserved_3[0x1c];
7571 u8 reserved_4[0x1c];
7572 u8 vl_operational[0x4];
7575 struct mlx5_ifc_pude_reg_bits {
7579 u8 admin_status[0x4];
7581 u8 oper_status[0x4];
7583 u8 reserved_2[0x60];
7587 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1,
7588 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4,
7591 struct mlx5_ifc_ptys_reg_bits {
7593 u8 an_disable_admin[0x1];
7594 u8 an_disable_cap[0x1];
7596 u8 force_tx_aba_param[0x1];
7603 u8 data_rate_oper[0x10];
7605 u8 fc_proto_capability[0x20];
7607 u8 eth_proto_capability[0x20];
7609 u8 ib_link_width_capability[0x10];
7610 u8 ib_proto_capability[0x10];
7612 u8 fc_proto_admin[0x20];
7614 u8 eth_proto_admin[0x20];
7616 u8 ib_link_width_admin[0x10];
7617 u8 ib_proto_admin[0x10];
7619 u8 fc_proto_oper[0x20];
7621 u8 eth_proto_oper[0x20];
7623 u8 ib_link_width_oper[0x10];
7624 u8 ib_proto_oper[0x10];
7626 u8 reserved_4[0x20];
7628 u8 eth_proto_lp_advertise[0x20];
7630 u8 reserved_5[0x60];
7633 struct mlx5_ifc_ptas_reg_bits {
7634 u8 reserved_0[0x20];
7636 u8 algorithm_options[0x10];
7638 u8 repetitions_mode[0x4];
7639 u8 num_of_repetitions[0x8];
7641 u8 grade_version[0x8];
7642 u8 height_grade_type[0x4];
7643 u8 phase_grade_type[0x4];
7644 u8 height_grade_weight[0x8];
7645 u8 phase_grade_weight[0x8];
7647 u8 gisim_measure_bits[0x10];
7648 u8 adaptive_tap_measure_bits[0x10];
7650 u8 ber_bath_high_error_threshold[0x10];
7651 u8 ber_bath_mid_error_threshold[0x10];
7653 u8 ber_bath_low_error_threshold[0x10];
7654 u8 one_ratio_high_threshold[0x10];
7656 u8 one_ratio_high_mid_threshold[0x10];
7657 u8 one_ratio_low_mid_threshold[0x10];
7659 u8 one_ratio_low_threshold[0x10];
7660 u8 ndeo_error_threshold[0x10];
7662 u8 mixer_offset_step_size[0x10];
7664 u8 mix90_phase_for_voltage_bath[0x8];
7666 u8 mixer_offset_start[0x10];
7667 u8 mixer_offset_end[0x10];
7669 u8 reserved_3[0x15];
7670 u8 ber_test_time[0xb];
7673 struct mlx5_ifc_pspa_reg_bits {
7679 u8 reserved_1[0x20];
7682 struct mlx5_ifc_ppsc_reg_bits {
7685 u8 reserved_1[0x10];
7687 u8 reserved_2[0x60];
7689 u8 reserved_3[0x1c];
7692 u8 reserved_4[0x1c];
7693 u8 wrps_status[0x4];
7696 u8 down_th_vld[0x1];
7698 u8 up_threshold[0x8];
7700 u8 down_threshold[0x8];
7702 u8 reserved_7[0x20];
7704 u8 reserved_8[0x1c];
7707 u8 reserved_9[0x60];
7710 struct mlx5_ifc_pplr_reg_bits {
7713 u8 reserved_1[0x10];
7721 struct mlx5_ifc_pplm_reg_bits {
7724 u8 reserved_1[0x10];
7726 u8 reserved_2[0x20];
7728 u8 port_profile_mode[0x8];
7729 u8 static_port_profile[0x8];
7730 u8 active_port_profile[0x8];
7733 u8 retransmission_active[0x8];
7734 u8 fec_mode_active[0x18];
7736 u8 reserved_4[0x10];
7737 u8 v_100g_fec_override_cap[0x4];
7738 u8 v_50g_fec_override_cap[0x4];
7739 u8 v_25g_fec_override_cap[0x4];
7740 u8 v_10g_40g_fec_override_cap[0x4];
7742 u8 reserved_5[0x10];
7743 u8 v_100g_fec_override_admin[0x4];
7744 u8 v_50g_fec_override_admin[0x4];
7745 u8 v_25g_fec_override_admin[0x4];
7746 u8 v_10g_40g_fec_override_admin[0x4];
7749 struct mlx5_ifc_ppll_reg_bits {
7750 u8 num_pll_groups[0x8];
7756 u8 reserved_2[0x1f];
7759 u8 pll_status[4][0x40];
7762 struct mlx5_ifc_ppad_reg_bits {
7771 u8 reserved_2[0x40];
7774 struct mlx5_ifc_pmtu_reg_bits {
7777 u8 reserved_1[0x10];
7780 u8 reserved_2[0x10];
7783 u8 reserved_3[0x10];
7786 u8 reserved_4[0x10];
7789 struct mlx5_ifc_pmpr_reg_bits {
7792 u8 reserved_1[0x10];
7794 u8 reserved_2[0x18];
7795 u8 attenuation_5g[0x8];
7797 u8 reserved_3[0x18];
7798 u8 attenuation_7g[0x8];
7800 u8 reserved_4[0x18];
7801 u8 attenuation_12g[0x8];
7804 struct mlx5_ifc_pmpe_reg_bits {
7808 u8 module_status[0x4];
7810 u8 reserved_2[0x14];
7814 u8 reserved_4[0x40];
7817 struct mlx5_ifc_pmpc_reg_bits {
7818 u8 module_state_updated[32][0x8];
7821 struct mlx5_ifc_pmlpn_reg_bits {
7823 u8 mlpn_status[0x4];
7825 u8 reserved_1[0x10];
7828 u8 reserved_2[0x1f];
7831 struct mlx5_ifc_pmlp_reg_bits {
7838 u8 lane0_module_mapping[0x20];
7840 u8 lane1_module_mapping[0x20];
7842 u8 lane2_module_mapping[0x20];
7844 u8 lane3_module_mapping[0x20];
7846 u8 reserved_2[0x160];
7849 struct mlx5_ifc_pmaos_reg_bits {
7853 u8 admin_status[0x4];
7855 u8 oper_status[0x4];
7859 u8 reserved_3[0x12];
7864 u8 reserved_5[0x40];
7867 struct mlx5_ifc_plpc_reg_bits {
7874 u8 reserved_3[0x10];
7875 u8 lane_speed[0x10];
7877 u8 reserved_4[0x17];
7879 u8 fec_mode_policy[0x8];
7881 u8 retransmission_capability[0x8];
7882 u8 fec_mode_capability[0x18];
7884 u8 retransmission_support_admin[0x8];
7885 u8 fec_mode_support_admin[0x18];
7887 u8 retransmission_request_admin[0x8];
7888 u8 fec_mode_request_admin[0x18];
7890 u8 reserved_5[0x80];
7893 struct mlx5_ifc_pll_status_data_bits {
7896 u8 lock_status[0x2];
7898 u8 algo_f_ctrl[0xa];
7899 u8 analog_algo_num_var[0x6];
7900 u8 f_ctrl_measure[0xa];
7912 struct mlx5_ifc_plib_reg_bits {
7918 u8 reserved_2[0x60];
7921 struct mlx5_ifc_plbf_reg_bits {
7927 u8 reserved_2[0x20];
7930 struct mlx5_ifc_pipg_reg_bits {
7933 u8 reserved_1[0x10];
7936 u8 reserved_2[0x19];
7941 struct mlx5_ifc_pifr_reg_bits {
7944 u8 reserved_1[0x10];
7946 u8 reserved_2[0xe0];
7948 u8 port_filter[8][0x20];
7950 u8 port_filter_update_en[8][0x20];
7953 struct mlx5_ifc_phys_layer_cntrs_bits {
7954 u8 time_since_last_clear_high[0x20];
7956 u8 time_since_last_clear_low[0x20];
7958 u8 symbol_errors_high[0x20];
7960 u8 symbol_errors_low[0x20];
7962 u8 sync_headers_errors_high[0x20];
7964 u8 sync_headers_errors_low[0x20];
7966 u8 edpl_bip_errors_lane0_high[0x20];
7968 u8 edpl_bip_errors_lane0_low[0x20];
7970 u8 edpl_bip_errors_lane1_high[0x20];
7972 u8 edpl_bip_errors_lane1_low[0x20];
7974 u8 edpl_bip_errors_lane2_high[0x20];
7976 u8 edpl_bip_errors_lane2_low[0x20];
7978 u8 edpl_bip_errors_lane3_high[0x20];
7980 u8 edpl_bip_errors_lane3_low[0x20];
7982 u8 fc_fec_corrected_blocks_lane0_high[0x20];
7984 u8 fc_fec_corrected_blocks_lane0_low[0x20];
7986 u8 fc_fec_corrected_blocks_lane1_high[0x20];
7988 u8 fc_fec_corrected_blocks_lane1_low[0x20];
7990 u8 fc_fec_corrected_blocks_lane2_high[0x20];
7992 u8 fc_fec_corrected_blocks_lane2_low[0x20];
7994 u8 fc_fec_corrected_blocks_lane3_high[0x20];
7996 u8 fc_fec_corrected_blocks_lane3_low[0x20];
7998 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
8000 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
8002 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
8004 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
8006 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
8008 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
8010 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
8012 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
8014 u8 rs_fec_corrected_blocks_high[0x20];
8016 u8 rs_fec_corrected_blocks_low[0x20];
8018 u8 rs_fec_uncorrectable_blocks_high[0x20];
8020 u8 rs_fec_uncorrectable_blocks_low[0x20];
8022 u8 rs_fec_no_errors_blocks_high[0x20];
8024 u8 rs_fec_no_errors_blocks_low[0x20];
8026 u8 rs_fec_single_error_blocks_high[0x20];
8028 u8 rs_fec_single_error_blocks_low[0x20];
8030 u8 rs_fec_corrected_symbols_total_high[0x20];
8032 u8 rs_fec_corrected_symbols_total_low[0x20];
8034 u8 rs_fec_corrected_symbols_lane0_high[0x20];
8036 u8 rs_fec_corrected_symbols_lane0_low[0x20];
8038 u8 rs_fec_corrected_symbols_lane1_high[0x20];
8040 u8 rs_fec_corrected_symbols_lane1_low[0x20];
8042 u8 rs_fec_corrected_symbols_lane2_high[0x20];
8044 u8 rs_fec_corrected_symbols_lane2_low[0x20];
8046 u8 rs_fec_corrected_symbols_lane3_high[0x20];
8048 u8 rs_fec_corrected_symbols_lane3_low[0x20];
8050 u8 link_down_events[0x20];
8052 u8 successful_recovery_events[0x20];
8054 u8 reserved_0[0x180];
8057 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8058 u8 time_since_last_clear_high[0x20];
8060 u8 time_since_last_clear_low[0x20];
8062 u8 phy_received_bits_high[0x20];
8064 u8 phy_received_bits_low[0x20];
8066 u8 phy_symbol_errors_high[0x20];
8068 u8 phy_symbol_errors_low[0x20];
8070 u8 phy_corrected_bits_high[0x20];
8072 u8 phy_corrected_bits_low[0x20];
8074 u8 phy_corrected_bits_lane0_high[0x20];
8076 u8 phy_corrected_bits_lane0_low[0x20];
8078 u8 phy_corrected_bits_lane1_high[0x20];
8080 u8 phy_corrected_bits_lane1_low[0x20];
8082 u8 phy_corrected_bits_lane2_high[0x20];
8084 u8 phy_corrected_bits_lane2_low[0x20];
8086 u8 phy_corrected_bits_lane3_high[0x20];
8088 u8 phy_corrected_bits_lane3_low[0x20];
8090 u8 reserved_at_200[0x5c0];
8093 struct mlx5_ifc_infiniband_port_cntrs_bits {
8094 u8 symbol_error_counter[0x10];
8095 u8 link_error_recovery_counter[0x8];
8096 u8 link_downed_counter[0x8];
8098 u8 port_rcv_errors[0x10];
8099 u8 port_rcv_remote_physical_errors[0x10];
8101 u8 port_rcv_switch_relay_errors[0x10];
8102 u8 port_xmit_discards[0x10];
8104 u8 port_xmit_constraint_errors[0x8];
8105 u8 port_rcv_constraint_errors[0x8];
8107 u8 local_link_integrity_errors[0x4];
8108 u8 excessive_buffer_overrun_errors[0x4];
8110 u8 reserved_1[0x10];
8111 u8 vl_15_dropped[0x10];
8113 u8 port_xmit_data[0x20];
8115 u8 port_rcv_data[0x20];
8117 u8 port_xmit_pkts[0x20];
8119 u8 port_rcv_pkts[0x20];
8121 u8 port_xmit_wait[0x20];
8123 u8 reserved_2[0x680];
8126 struct mlx5_ifc_phrr_reg_bits {
8130 u8 reserved_1[0x10];
8133 u8 reserved_2[0x10];
8136 u8 reserved_3[0x40];
8138 u8 time_since_last_clear_high[0x20];
8140 u8 time_since_last_clear_low[0x20];
8145 struct mlx5_ifc_phbr_for_prio_reg_bits {
8146 u8 reserved_0[0x18];
8150 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8151 u8 reserved_0[0x18];
8155 struct mlx5_ifc_phbr_binding_reg_bits {
8163 u8 reserved_2[0x10];
8166 u8 reserved_3[0x10];
8169 u8 hist_parameters[0x20];
8171 u8 hist_min_value[0x20];
8173 u8 hist_max_value[0x20];
8175 u8 sample_time[0x20];
8179 MLX5_PFCC_REG_PPAN_DISABLED = 0x0,
8180 MLX5_PFCC_REG_PPAN_ENABLED = 0x1,
8183 struct mlx5_ifc_pfcc_reg_bits {
8184 u8 dcbx_operation_type[0x2];
8185 u8 cap_local_admin[0x1];
8186 u8 cap_remote_admin[0x1];
8196 u8 prio_mask_tx[0x8];
8198 u8 prio_mask_rx[0x8];
8214 u8 device_stall_minor_watermark[0x10];
8215 u8 device_stall_critical_watermark[0x10];
8217 u8 reserved_8[0x60];
8220 struct mlx5_ifc_pelc_reg_bits {
8224 u8 reserved_1[0x10];
8227 u8 op_capability[0x8];
8233 u8 capability[0x40];
8239 u8 reserved_2[0x80];
8242 struct mlx5_ifc_peir_reg_bits {
8245 u8 reserved_1[0x10];
8248 u8 error_count[0x4];
8249 u8 reserved_3[0x10];
8257 struct mlx5_ifc_pcap_reg_bits {
8260 u8 reserved_1[0x10];
8262 u8 port_capability_mask[4][0x20];
8265 struct mlx5_ifc_pbmc_reg_bits {
8268 u8 reserved_1[0x10];
8270 u8 xoff_timer_value[0x10];
8271 u8 xoff_refresh[0x10];
8273 u8 reserved_2[0x10];
8274 u8 port_buffer_size[0x10];
8276 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8278 u8 reserved_3[0x40];
8280 u8 port_shared_buffer[0x40];
8283 struct mlx5_ifc_paos_reg_bits {
8287 u8 admin_status[0x4];
8289 u8 oper_status[0x4];
8293 u8 reserved_2[0x1c];
8296 u8 reserved_3[0x40];
8299 struct mlx5_ifc_pamp_reg_bits {
8301 u8 opamp_group[0x8];
8303 u8 opamp_group_type[0x4];
8305 u8 start_index[0x10];
8307 u8 num_of_indices[0xc];
8309 u8 index_data[18][0x10];
8312 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8313 u8 llr_rx_cells_high[0x20];
8315 u8 llr_rx_cells_low[0x20];
8317 u8 llr_rx_error_high[0x20];
8319 u8 llr_rx_error_low[0x20];
8321 u8 llr_rx_crc_error_high[0x20];
8323 u8 llr_rx_crc_error_low[0x20];
8325 u8 llr_tx_cells_high[0x20];
8327 u8 llr_tx_cells_low[0x20];
8329 u8 llr_tx_ret_cells_high[0x20];
8331 u8 llr_tx_ret_cells_low[0x20];
8333 u8 llr_tx_ret_events_high[0x20];
8335 u8 llr_tx_ret_events_low[0x20];
8337 u8 reserved_0[0x640];
8340 struct mlx5_ifc_lane_2_module_mapping_bits {
8349 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8350 u8 transmit_queue_high[0x20];
8352 u8 transmit_queue_low[0x20];
8354 u8 reserved_0[0x780];
8357 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8358 u8 no_buffer_discard_uc_high[0x20];
8360 u8 no_buffer_discard_uc_low[0x20];
8362 u8 wred_discard_high[0x20];
8364 u8 wred_discard_low[0x20];
8366 u8 reserved_0[0x740];
8369 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8370 u8 rx_octets_high[0x20];
8372 u8 rx_octets_low[0x20];
8374 u8 reserved_0[0xc0];
8376 u8 rx_frames_high[0x20];
8378 u8 rx_frames_low[0x20];
8380 u8 tx_octets_high[0x20];
8382 u8 tx_octets_low[0x20];
8384 u8 reserved_1[0xc0];
8386 u8 tx_frames_high[0x20];
8388 u8 tx_frames_low[0x20];
8390 u8 rx_pause_high[0x20];
8392 u8 rx_pause_low[0x20];
8394 u8 rx_pause_duration_high[0x20];
8396 u8 rx_pause_duration_low[0x20];
8398 u8 tx_pause_high[0x20];
8400 u8 tx_pause_low[0x20];
8402 u8 tx_pause_duration_high[0x20];
8404 u8 tx_pause_duration_low[0x20];
8406 u8 rx_pause_transition_high[0x20];
8408 u8 rx_pause_transition_low[0x20];
8410 u8 rx_discards_high[0x20];
8412 u8 rx_discards_low[0x20];
8414 u8 device_stall_minor_watermark_cnt_high[0x20];
8416 u8 device_stall_minor_watermark_cnt_low[0x20];
8418 u8 device_stall_critical_watermark_cnt_high[0x20];
8420 u8 device_stall_critical_watermark_cnt_low[0x20];
8422 u8 reserved_2[0x340];
8425 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8426 u8 port_transmit_wait_high[0x20];
8428 u8 port_transmit_wait_low[0x20];
8430 u8 ecn_marked_high[0x20];
8432 u8 ecn_marked_low[0x20];
8434 u8 no_buffer_discard_mc_high[0x20];
8436 u8 no_buffer_discard_mc_low[0x20];
8438 u8 reserved_0[0x700];
8441 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8442 u8 a_frames_transmitted_ok_high[0x20];
8444 u8 a_frames_transmitted_ok_low[0x20];
8446 u8 a_frames_received_ok_high[0x20];
8448 u8 a_frames_received_ok_low[0x20];
8450 u8 a_frame_check_sequence_errors_high[0x20];
8452 u8 a_frame_check_sequence_errors_low[0x20];
8454 u8 a_alignment_errors_high[0x20];
8456 u8 a_alignment_errors_low[0x20];
8458 u8 a_octets_transmitted_ok_high[0x20];
8460 u8 a_octets_transmitted_ok_low[0x20];
8462 u8 a_octets_received_ok_high[0x20];
8464 u8 a_octets_received_ok_low[0x20];
8466 u8 a_multicast_frames_xmitted_ok_high[0x20];
8468 u8 a_multicast_frames_xmitted_ok_low[0x20];
8470 u8 a_broadcast_frames_xmitted_ok_high[0x20];
8472 u8 a_broadcast_frames_xmitted_ok_low[0x20];
8474 u8 a_multicast_frames_received_ok_high[0x20];
8476 u8 a_multicast_frames_received_ok_low[0x20];
8478 u8 a_broadcast_frames_recieved_ok_high[0x20];
8480 u8 a_broadcast_frames_recieved_ok_low[0x20];
8482 u8 a_in_range_length_errors_high[0x20];
8484 u8 a_in_range_length_errors_low[0x20];
8486 u8 a_out_of_range_length_field_high[0x20];
8488 u8 a_out_of_range_length_field_low[0x20];
8490 u8 a_frame_too_long_errors_high[0x20];
8492 u8 a_frame_too_long_errors_low[0x20];
8494 u8 a_symbol_error_during_carrier_high[0x20];
8496 u8 a_symbol_error_during_carrier_low[0x20];
8498 u8 a_mac_control_frames_transmitted_high[0x20];
8500 u8 a_mac_control_frames_transmitted_low[0x20];
8502 u8 a_mac_control_frames_received_high[0x20];
8504 u8 a_mac_control_frames_received_low[0x20];
8506 u8 a_unsupported_opcodes_received_high[0x20];
8508 u8 a_unsupported_opcodes_received_low[0x20];
8510 u8 a_pause_mac_ctrl_frames_received_high[0x20];
8512 u8 a_pause_mac_ctrl_frames_received_low[0x20];
8514 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
8516 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
8518 u8 reserved_0[0x300];
8521 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8522 u8 dot3stats_alignment_errors_high[0x20];
8524 u8 dot3stats_alignment_errors_low[0x20];
8526 u8 dot3stats_fcs_errors_high[0x20];
8528 u8 dot3stats_fcs_errors_low[0x20];
8530 u8 dot3stats_single_collision_frames_high[0x20];
8532 u8 dot3stats_single_collision_frames_low[0x20];
8534 u8 dot3stats_multiple_collision_frames_high[0x20];
8536 u8 dot3stats_multiple_collision_frames_low[0x20];
8538 u8 dot3stats_sqe_test_errors_high[0x20];
8540 u8 dot3stats_sqe_test_errors_low[0x20];
8542 u8 dot3stats_deferred_transmissions_high[0x20];
8544 u8 dot3stats_deferred_transmissions_low[0x20];
8546 u8 dot3stats_late_collisions_high[0x20];
8548 u8 dot3stats_late_collisions_low[0x20];
8550 u8 dot3stats_excessive_collisions_high[0x20];
8552 u8 dot3stats_excessive_collisions_low[0x20];
8554 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
8556 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
8558 u8 dot3stats_carrier_sense_errors_high[0x20];
8560 u8 dot3stats_carrier_sense_errors_low[0x20];
8562 u8 dot3stats_frame_too_longs_high[0x20];
8564 u8 dot3stats_frame_too_longs_low[0x20];
8566 u8 dot3stats_internal_mac_receive_errors_high[0x20];
8568 u8 dot3stats_internal_mac_receive_errors_low[0x20];
8570 u8 dot3stats_symbol_errors_high[0x20];
8572 u8 dot3stats_symbol_errors_low[0x20];
8574 u8 dot3control_in_unknown_opcodes_high[0x20];
8576 u8 dot3control_in_unknown_opcodes_low[0x20];
8578 u8 dot3in_pause_frames_high[0x20];
8580 u8 dot3in_pause_frames_low[0x20];
8582 u8 dot3out_pause_frames_high[0x20];
8584 u8 dot3out_pause_frames_low[0x20];
8586 u8 reserved_0[0x3c0];
8589 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8590 u8 if_in_octets_high[0x20];
8592 u8 if_in_octets_low[0x20];
8594 u8 if_in_ucast_pkts_high[0x20];
8596 u8 if_in_ucast_pkts_low[0x20];
8598 u8 if_in_discards_high[0x20];
8600 u8 if_in_discards_low[0x20];
8602 u8 if_in_errors_high[0x20];
8604 u8 if_in_errors_low[0x20];
8606 u8 if_in_unknown_protos_high[0x20];
8608 u8 if_in_unknown_protos_low[0x20];
8610 u8 if_out_octets_high[0x20];
8612 u8 if_out_octets_low[0x20];
8614 u8 if_out_ucast_pkts_high[0x20];
8616 u8 if_out_ucast_pkts_low[0x20];
8618 u8 if_out_discards_high[0x20];
8620 u8 if_out_discards_low[0x20];
8622 u8 if_out_errors_high[0x20];
8624 u8 if_out_errors_low[0x20];
8626 u8 if_in_multicast_pkts_high[0x20];
8628 u8 if_in_multicast_pkts_low[0x20];
8630 u8 if_in_broadcast_pkts_high[0x20];
8632 u8 if_in_broadcast_pkts_low[0x20];
8634 u8 if_out_multicast_pkts_high[0x20];
8636 u8 if_out_multicast_pkts_low[0x20];
8638 u8 if_out_broadcast_pkts_high[0x20];
8640 u8 if_out_broadcast_pkts_low[0x20];
8642 u8 reserved_0[0x480];
8645 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8646 u8 ether_stats_drop_events_high[0x20];
8648 u8 ether_stats_drop_events_low[0x20];
8650 u8 ether_stats_octets_high[0x20];
8652 u8 ether_stats_octets_low[0x20];
8654 u8 ether_stats_pkts_high[0x20];
8656 u8 ether_stats_pkts_low[0x20];
8658 u8 ether_stats_broadcast_pkts_high[0x20];
8660 u8 ether_stats_broadcast_pkts_low[0x20];
8662 u8 ether_stats_multicast_pkts_high[0x20];
8664 u8 ether_stats_multicast_pkts_low[0x20];
8666 u8 ether_stats_crc_align_errors_high[0x20];
8668 u8 ether_stats_crc_align_errors_low[0x20];
8670 u8 ether_stats_undersize_pkts_high[0x20];
8672 u8 ether_stats_undersize_pkts_low[0x20];
8674 u8 ether_stats_oversize_pkts_high[0x20];
8676 u8 ether_stats_oversize_pkts_low[0x20];
8678 u8 ether_stats_fragments_high[0x20];
8680 u8 ether_stats_fragments_low[0x20];
8682 u8 ether_stats_jabbers_high[0x20];
8684 u8 ether_stats_jabbers_low[0x20];
8686 u8 ether_stats_collisions_high[0x20];
8688 u8 ether_stats_collisions_low[0x20];
8690 u8 ether_stats_pkts64octets_high[0x20];
8692 u8 ether_stats_pkts64octets_low[0x20];
8694 u8 ether_stats_pkts65to127octets_high[0x20];
8696 u8 ether_stats_pkts65to127octets_low[0x20];
8698 u8 ether_stats_pkts128to255octets_high[0x20];
8700 u8 ether_stats_pkts128to255octets_low[0x20];
8702 u8 ether_stats_pkts256to511octets_high[0x20];
8704 u8 ether_stats_pkts256to511octets_low[0x20];
8706 u8 ether_stats_pkts512to1023octets_high[0x20];
8708 u8 ether_stats_pkts512to1023octets_low[0x20];
8710 u8 ether_stats_pkts1024to1518octets_high[0x20];
8712 u8 ether_stats_pkts1024to1518octets_low[0x20];
8714 u8 ether_stats_pkts1519to2047octets_high[0x20];
8716 u8 ether_stats_pkts1519to2047octets_low[0x20];
8718 u8 ether_stats_pkts2048to4095octets_high[0x20];
8720 u8 ether_stats_pkts2048to4095octets_low[0x20];
8722 u8 ether_stats_pkts4096to8191octets_high[0x20];
8724 u8 ether_stats_pkts4096to8191octets_low[0x20];
8726 u8 ether_stats_pkts8192to10239octets_high[0x20];
8728 u8 ether_stats_pkts8192to10239octets_low[0x20];
8730 u8 reserved_0[0x280];
8733 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8734 u8 symbol_error_counter[0x10];
8735 u8 link_error_recovery_counter[0x8];
8736 u8 link_downed_counter[0x8];
8738 u8 port_rcv_errors[0x10];
8739 u8 port_rcv_remote_physical_errors[0x10];
8741 u8 port_rcv_switch_relay_errors[0x10];
8742 u8 port_xmit_discards[0x10];
8744 u8 port_xmit_constraint_errors[0x8];
8745 u8 port_rcv_constraint_errors[0x8];
8747 u8 local_link_integrity_errors[0x4];
8748 u8 excessive_buffer_overrun_errors[0x4];
8750 u8 reserved_1[0x10];
8751 u8 vl_15_dropped[0x10];
8753 u8 port_xmit_data[0x20];
8755 u8 port_rcv_data[0x20];
8757 u8 port_xmit_pkts[0x20];
8759 u8 port_rcv_pkts[0x20];
8761 u8 port_xmit_wait[0x20];
8763 u8 reserved_2[0x680];
8766 struct mlx5_ifc_trc_tlb_reg_bits {
8767 u8 reserved_0[0x80];
8769 u8 tlb_addr[0][0x40];
8772 struct mlx5_ifc_trc_read_fifo_reg_bits {
8773 u8 reserved_0[0x10];
8774 u8 requested_event_num[0x10];
8776 u8 reserved_1[0x20];
8778 u8 reserved_2[0x10];
8779 u8 acual_event_num[0x10];
8781 u8 reserved_3[0x20];
8786 struct mlx5_ifc_trc_lock_reg_bits {
8787 u8 reserved_0[0x1f];
8790 u8 reserved_1[0x60];
8793 struct mlx5_ifc_trc_filter_reg_bits {
8796 u8 filter_index[0x10];
8798 u8 reserved_1[0x20];
8800 u8 filter_val[0x20];
8802 u8 reserved_2[0x1a0];
8805 struct mlx5_ifc_trc_event_reg_bits {
8808 u8 event_index[0x10];
8810 u8 reserved_1[0x20];
8814 u8 event_selector_val[0x10];
8815 u8 event_selector_size[0x10];
8817 u8 reserved_2[0x180];
8820 struct mlx5_ifc_trc_conf_reg_bits {
8824 u8 reserved_1[0x15];
8827 u8 reserved_2[0x20];
8829 u8 limit_event_index[0x20];
8833 u8 fifo_ready_ev_num[0x20];
8835 u8 reserved_3[0x160];
8838 struct mlx5_ifc_trc_cap_reg_bits {
8839 u8 reserved_0[0x18];
8842 u8 reserved_1[0x20];
8844 u8 num_of_events[0x10];
8845 u8 num_of_filters[0x10];
8850 u8 event_size[0x10];
8852 u8 reserved_2[0x160];
8855 struct mlx5_ifc_set_node_in_bits {
8856 u8 node_description[64][0x8];
8859 struct mlx5_ifc_register_power_settings_bits {
8860 u8 reserved_0[0x18];
8861 u8 power_settings_level[0x8];
8863 u8 reserved_1[0x60];
8866 struct mlx5_ifc_register_host_endianess_bits {
8868 u8 reserved_0[0x1f];
8870 u8 reserved_1[0x60];
8873 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
8874 u8 physical_address[0x40];
8877 struct mlx5_ifc_qtct_reg_bits {
8878 u8 operation_type[0x2];
8879 u8 cap_local_admin[0x1];
8880 u8 cap_remote_admin[0x1];
8882 u8 port_number[0x8];
8886 u8 reserved_2[0x1d];
8890 struct mlx5_ifc_qpdp_reg_bits {
8892 u8 port_number[0x8];
8893 u8 reserved_1[0x10];
8895 u8 reserved_2[0x1d];
8899 struct mlx5_ifc_port_info_ro_fields_param_bits {
8904 u8 reserved_1[0x20];
8909 struct mlx5_ifc_nvqc_reg_bits {
8912 u8 reserved_0[0x18];
8919 struct mlx5_ifc_nvia_reg_bits {
8920 u8 reserved_0[0x1d];
8923 u8 reserved_1[0x20];
8926 struct mlx5_ifc_nvdi_reg_bits {
8927 struct mlx5_ifc_config_item_bits configuration_item_header;
8930 struct mlx5_ifc_nvda_reg_bits {
8931 struct mlx5_ifc_config_item_bits configuration_item_header;
8933 u8 configuration_item_data[0x20];
8936 struct mlx5_ifc_node_info_ro_fields_param_bits {
8937 u8 system_image_guid[0x40];
8939 u8 reserved_0[0x40];
8943 u8 reserved_1[0x10];
8946 u8 reserved_2[0x20];
8949 struct mlx5_ifc_ets_tcn_config_reg_bits {
8956 u8 bw_allocation[0x7];
8959 u8 max_bw_units[0x4];
8961 u8 max_bw_value[0x8];
8964 struct mlx5_ifc_ets_global_config_reg_bits {
8967 u8 reserved_1[0x1d];
8970 u8 max_bw_units[0x4];
8972 u8 max_bw_value[0x8];
8975 struct mlx5_ifc_nodnic_mac_filters_bits {
8976 struct mlx5_ifc_mac_address_layout_bits mac_filter0;
8978 struct mlx5_ifc_mac_address_layout_bits mac_filter1;
8980 struct mlx5_ifc_mac_address_layout_bits mac_filter2;
8982 struct mlx5_ifc_mac_address_layout_bits mac_filter3;
8984 struct mlx5_ifc_mac_address_layout_bits mac_filter4;
8986 u8 reserved_0[0xc0];
8989 struct mlx5_ifc_nodnic_gid_filters_bits {
8990 u8 mgid_filter0[16][0x8];
8992 u8 mgid_filter1[16][0x8];
8994 u8 mgid_filter2[16][0x8];
8996 u8 mgid_filter3[16][0x8];
9000 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0,
9001 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1,
9005 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0,
9006 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1,
9009 struct mlx5_ifc_nodnic_config_reg_bits {
9010 u8 no_dram_nic_revision[0x8];
9011 u8 hardware_format[0x8];
9012 u8 support_receive_filter[0x1];
9013 u8 support_promisc_filter[0x1];
9014 u8 support_promisc_multicast_filter[0x1];
9016 u8 log_working_buffer_size[0x3];
9017 u8 log_pkey_table_size[0x4];
9022 u8 log_max_ring_size[0x6];
9023 u8 reserved_3[0x18];
9028 u8 reserved_4[0x1c];
9032 u8 reserved_5[0x740];
9034 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9036 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9039 struct mlx5_ifc_vlan_layout_bits {
9040 u8 reserved_0[0x14];
9043 u8 reserved_1[0x20];
9046 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9047 u8 reserved_0[0x20];
9051 u8 addressh_63_32[0x20];
9053 u8 addressl_31_0[0x20];
9056 struct mlx5_ifc_ud_adrs_vector_bits {
9061 u8 destination_qp_dct[0x18];
9063 u8 static_rate[0x4];
9064 u8 sl_eth_prio[0x4];
9067 u8 rlid_udp_sport[0x10];
9069 u8 reserved_1[0x20];
9071 u8 rmac_47_16[0x20];
9080 u8 src_addr_index[0x8];
9081 u8 flow_label[0x14];
9083 u8 rgid_rip[16][0x8];
9086 struct mlx5_ifc_port_module_event_bits {
9090 u8 module_status[0x4];
9092 u8 reserved_2[0x14];
9096 u8 reserved_4[0xa0];
9099 struct mlx5_ifc_icmd_control_bits {
9106 struct mlx5_ifc_eqe_bits {
9110 u8 event_sub_type[0x8];
9112 u8 reserved_2[0xe0];
9114 union mlx5_ifc_event_auto_bits event_data;
9116 u8 reserved_3[0x10];
9123 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9126 struct mlx5_ifc_cmd_queue_entry_bits {
9128 u8 reserved_0[0x18];
9130 u8 input_length[0x20];
9132 u8 input_mailbox_pointer_63_32[0x20];
9134 u8 input_mailbox_pointer_31_9[0x17];
9137 u8 command_input_inline_data[16][0x8];
9139 u8 command_output_inline_data[16][0x8];
9141 u8 output_mailbox_pointer_63_32[0x20];
9143 u8 output_mailbox_pointer_31_9[0x17];
9146 u8 output_length[0x20];
9155 struct mlx5_ifc_cmd_out_bits {
9157 u8 reserved_0[0x18];
9161 u8 command_output[0x20];
9164 struct mlx5_ifc_cmd_in_bits {
9166 u8 reserved_0[0x10];
9168 u8 reserved_1[0x10];
9171 u8 command[0][0x20];
9174 struct mlx5_ifc_cmd_if_box_bits {
9175 u8 mailbox_data[512][0x8];
9177 u8 reserved_0[0x180];
9179 u8 next_pointer_63_32[0x20];
9181 u8 next_pointer_31_10[0x16];
9184 u8 block_number[0x20];
9188 u8 ctrl_signature[0x8];
9192 struct mlx5_ifc_mtt_bits {
9193 u8 ptag_63_32[0x20];
9201 struct mlx5_ifc_vendor_specific_cap_bits {
9204 u8 next_pointer[0x8];
9205 u8 capability_id[0x8];
9223 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9224 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9225 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9229 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9230 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9231 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9235 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
9236 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
9237 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
9238 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
9239 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
9240 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
9241 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
9242 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
9243 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
9244 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
9245 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10,
9248 struct mlx5_ifc_initial_seg_bits {
9249 u8 fw_rev_minor[0x10];
9250 u8 fw_rev_major[0x10];
9252 u8 cmd_interface_rev[0x10];
9253 u8 fw_rev_subminor[0x10];
9255 u8 reserved_0[0x40];
9257 u8 cmdq_phy_addr_63_32[0x20];
9259 u8 cmdq_phy_addr_31_12[0x14];
9261 u8 nic_interface[0x2];
9262 u8 log_cmdq_size[0x4];
9263 u8 log_cmdq_stride[0x4];
9265 u8 command_doorbell_vector[0x20];
9267 u8 reserved_2[0xf00];
9269 u8 initializing[0x1];
9271 u8 nic_interface_supported[0x3];
9272 u8 reserved_4[0x18];
9274 struct mlx5_ifc_health_buffer_bits health_buffer;
9276 u8 no_dram_nic_offset[0x20];
9278 u8 reserved_5[0x6de0];
9280 u8 internal_timer_h[0x20];
9282 u8 internal_timer_l[0x20];
9284 u8 reserved_6[0x20];
9286 u8 reserved_7[0x1f];
9289 u8 health_syndrome[0x8];
9290 u8 health_counter[0x18];
9292 u8 reserved_8[0x17fc0];
9295 union mlx5_ifc_icmd_interface_document_bits {
9296 struct mlx5_ifc_fw_version_bits fw_version;
9297 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9298 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9299 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9300 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9301 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9302 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9303 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9304 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9305 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9306 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9307 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9308 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9309 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9310 u8 reserved_0[0x42c0];
9313 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9314 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9315 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9316 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9317 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9318 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9319 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9320 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9321 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9322 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9323 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9324 u8 reserved_0[0x7c0];
9327 struct mlx5_ifc_ppcnt_reg_bits {
9335 u8 reserved_1[0x1c];
9338 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9341 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9342 u8 life_time_counter_high[0x20];
9344 u8 life_time_counter_low[0x20];
9350 u8 l0_to_recovery_eieos[0x20];
9352 u8 l0_to_recovery_ts[0x20];
9354 u8 l0_to_recovery_framing[0x20];
9356 u8 l0_to_recovery_retrain[0x20];
9358 u8 crc_error_dllp[0x20];
9360 u8 crc_error_tlp[0x20];
9362 u8 reserved_0[0x680];
9365 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9366 u8 life_time_counter_high[0x20];
9368 u8 life_time_counter_low[0x20];
9370 u8 time_to_boot_image_start[0x20];
9372 u8 time_to_link_image[0x20];
9374 u8 calibration_time[0x20];
9376 u8 time_to_first_perst[0x20];
9378 u8 time_to_detect_state[0x20];
9380 u8 time_to_l0[0x20];
9382 u8 time_to_crs_en[0x20];
9384 u8 time_to_plastic_image_start[0x20];
9386 u8 time_to_iron_image_start[0x20];
9388 u8 perst_handler[0x20];
9390 u8 times_in_l1[0x20];
9392 u8 times_in_l23[0x20];
9396 u8 config_cycle1usec[0x20];
9398 u8 config_cycle2to7usec[0x20];
9400 u8 config_cycle8to15usec[0x20];
9402 u8 config_cycle16to63usec[0x20];
9404 u8 config_cycle64usec[0x20];
9406 u8 correctable_err_msg_sent[0x20];
9408 u8 non_fatal_err_msg_sent[0x20];
9410 u8 fatal_err_msg_sent[0x20];
9412 u8 reserved_0[0x4e0];
9415 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9416 u8 life_time_counter_high[0x20];
9418 u8 life_time_counter_low[0x20];
9420 u8 error_counter_lane0[0x20];
9422 u8 error_counter_lane1[0x20];
9424 u8 error_counter_lane2[0x20];
9426 u8 error_counter_lane3[0x20];
9428 u8 error_counter_lane4[0x20];
9430 u8 error_counter_lane5[0x20];
9432 u8 error_counter_lane6[0x20];
9434 u8 error_counter_lane7[0x20];
9436 u8 error_counter_lane8[0x20];
9438 u8 error_counter_lane9[0x20];
9440 u8 error_counter_lane10[0x20];
9442 u8 error_counter_lane11[0x20];
9444 u8 error_counter_lane12[0x20];
9446 u8 error_counter_lane13[0x20];
9448 u8 error_counter_lane14[0x20];
9450 u8 error_counter_lane15[0x20];
9452 u8 reserved_0[0x580];
9455 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9456 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9457 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9458 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9459 u8 reserved_0[0xf8];
9462 struct mlx5_ifc_mpcnt_reg_bits {
9469 u8 reserved_2[0x1f];
9471 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9474 union mlx5_ifc_ports_control_registers_document_bits {
9475 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9476 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9477 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9478 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9479 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9480 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9481 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9482 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9483 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9484 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9485 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9486 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9487 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9488 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9489 struct mlx5_ifc_paos_reg_bits paos_reg;
9490 struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9491 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9492 struct mlx5_ifc_peir_reg_bits peir_reg;
9493 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9494 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9495 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9496 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9497 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9498 struct mlx5_ifc_phrr_reg_bits phrr_reg;
9499 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9500 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9501 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9502 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9503 struct mlx5_ifc_plib_reg_bits plib_reg;
9504 struct mlx5_ifc_pll_status_data_bits pll_status_data;
9505 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9506 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9507 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9508 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9509 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9510 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9511 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9512 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9513 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9514 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9515 struct mlx5_ifc_ppll_reg_bits ppll_reg;
9516 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9517 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9518 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9519 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9520 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9521 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9522 struct mlx5_ifc_pude_reg_bits pude_reg;
9523 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9524 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9525 struct mlx5_ifc_slrp_reg_bits slrp_reg;
9526 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9527 u8 reserved_0[0x7880];
9530 union mlx5_ifc_debug_enhancements_document_bits {
9531 struct mlx5_ifc_health_buffer_bits health_buffer;
9532 u8 reserved_0[0x200];
9535 union mlx5_ifc_no_dram_nic_document_bits {
9536 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9537 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9538 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9539 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9540 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9541 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9542 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9543 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9544 u8 reserved_0[0x3160];
9547 union mlx5_ifc_uplink_pci_interface_document_bits {
9548 struct mlx5_ifc_initial_seg_bits initial_seg;
9549 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9550 u8 reserved_0[0x20120];
9554 #endif /* MLX5_IFC_H */