sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
  32
  33 enum {
  34         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  35         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  36         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  37         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  38         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  39         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  40         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  41         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  42         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  43         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  44         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  45         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  46         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  47         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  48         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  49         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  50         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  51         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  52         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  53         MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
  54         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  56         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  57         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  58         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  59         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  60         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  61         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  62         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  63         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
  64         MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
  65         MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
  66         MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT                   = 0x27,
  67 };
  68
  69 enum {
  70         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  71         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  72         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  73         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  74         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  75 };
  76
  77 enum {
  78         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  79 };
  80
  81 enum {
  82         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  83         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  84 };
  85
  86 enum {
  87         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  88         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  89         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  90         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  91         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  92         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  93         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  94         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  95         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  96         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  97         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  98         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  99         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
 100         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 107         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 108         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 109         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 110         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 111         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 112         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 113         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 114         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 115         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 116         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 117         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 118         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 119         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 120         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 121         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 122         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 123         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 124         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 125         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 126         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 127         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 128         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 129         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 130         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 131         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 132         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 133         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 134         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 135         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 136         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 137         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 138         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 139         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 140         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 141         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 142         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 143         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 144         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 145         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 146         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 147         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 148         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 149         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 150         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 151         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 152         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 153         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 154         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 155         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 156         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 157         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 158         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 159         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 160         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 161         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 162         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 163         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 164         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 165         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 166         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 167         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 168         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 169         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 170         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 171         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 172         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 173         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 174         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 175         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 176         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 177         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 178         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 179         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 180         MLX5_CMD_OP_NOP                           = 0x80d,
 181         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 182         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 183         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 184         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 185         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 186         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 190         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 191         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 192         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 193         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 194         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 195         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 196         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 197         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 198         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 199         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 200         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 201         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 202         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 203         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 204         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 205         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 206         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 207         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 208         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 209         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 210         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 211         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 212         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 213         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 214         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 215         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 216         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 217         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 218         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 219         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 220         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 221         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 222         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 223         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 224         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 225         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 226         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 227         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 228         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 229         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 230         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 231         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 232         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 233         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 234         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 235         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 236         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 237         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 238         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 239         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 240         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 241         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 242         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 243         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 244         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 245         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 246         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 247         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 248         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 249         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 250         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
 260
 261 };
 262
 263 enum {
 264         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 265         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 266         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 267         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 268         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 269         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 270         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 271         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 272         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 273         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 274         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 275         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 276 };
 277
 278 enum {
 279         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
 280 };
 281
 282 enum {
 283         MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
 284 };
 285
 286 enum {
 287         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
 288         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
 289 };
 290
 291 enum {
 292         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
 293 };
 294
 295 struct mlx5_ifc_flow_table_fields_supported_bits {
 296         u8         outer_dmac[0x1];
 297         u8         outer_smac[0x1];
 298         u8         outer_ether_type[0x1];
 299         u8         reserved_0[0x1];
 300         u8         outer_first_prio[0x1];
 301         u8         outer_first_cfi[0x1];
 302         u8         outer_first_vid[0x1];
 303         u8         reserved_1[0x1];
 304         u8         outer_second_prio[0x1];
 305         u8         outer_second_cfi[0x1];
 306         u8         outer_second_vid[0x1];
 307         u8         outer_ipv6_flow_label[0x1];
 308         u8         outer_sip[0x1];
 309         u8         outer_dip[0x1];
 310         u8         outer_frag[0x1];
 311         u8         outer_ip_protocol[0x1];
 312         u8         outer_ip_ecn[0x1];
 313         u8         outer_ip_dscp[0x1];
 314         u8         outer_udp_sport[0x1];
 315         u8         outer_udp_dport[0x1];
 316         u8         outer_tcp_sport[0x1];
 317         u8         outer_tcp_dport[0x1];
 318         u8         outer_tcp_flags[0x1];
 319         u8         outer_gre_protocol[0x1];
 320         u8         outer_gre_key[0x1];
 321         u8         outer_vxlan_vni[0x1];
 322         u8         outer_geneve_vni[0x1];
 323         u8         outer_geneve_oam[0x1];
 324         u8         outer_geneve_protocol_type[0x1];
 325         u8         outer_geneve_opt_len[0x1];
 326         u8         reserved_2[0x1];
 327         u8         source_eswitch_port[0x1];
 328
 329         u8         inner_dmac[0x1];
 330         u8         inner_smac[0x1];
 331         u8         inner_ether_type[0x1];
 332         u8         reserved_3[0x1];
 333         u8         inner_first_prio[0x1];
 334         u8         inner_first_cfi[0x1];
 335         u8         inner_first_vid[0x1];
 336         u8         reserved_4[0x1];
 337         u8         inner_second_prio[0x1];
 338         u8         inner_second_cfi[0x1];
 339         u8         inner_second_vid[0x1];
 340         u8         inner_ipv6_flow_label[0x1];
 341         u8         inner_sip[0x1];
 342         u8         inner_dip[0x1];
 343         u8         inner_frag[0x1];
 344         u8         inner_ip_protocol[0x1];
 345         u8         inner_ip_ecn[0x1];
 346         u8         inner_ip_dscp[0x1];
 347         u8         inner_udp_sport[0x1];
 348         u8         inner_udp_dport[0x1];
 349         u8         inner_tcp_sport[0x1];
 350         u8         inner_tcp_dport[0x1];
 351         u8         inner_tcp_flags[0x1];
 352         u8         reserved_5[0x9];
 353
 354         u8         reserved_6[0x1a];
 355         u8         bth_dst_qp[0x1];
 356         u8         reserved_7[0x4];
 357         u8         source_sqn[0x1];
 358
 359         u8         reserved_8[0x20];
 360 };
 361
 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 363         u8         ingress_general_high[0x20];
 364
 365         u8         ingress_general_low[0x20];
 366
 367         u8         ingress_policy_engine_high[0x20];
 368
 369         u8         ingress_policy_engine_low[0x20];
 370
 371         u8         ingress_vlan_membership_high[0x20];
 372
 373         u8         ingress_vlan_membership_low[0x20];
 374
 375         u8         ingress_tag_frame_type_high[0x20];
 376
 377         u8         ingress_tag_frame_type_low[0x20];
 378
 379         u8         egress_vlan_membership_high[0x20];
 380
 381         u8         egress_vlan_membership_low[0x20];
 382
 383         u8         loopback_filter_high[0x20];
 384
 385         u8         loopback_filter_low[0x20];
 386
 387         u8         egress_general_high[0x20];
 388
 389         u8         egress_general_low[0x20];
 390
 391         u8         reserved_at_1c0[0x40];
 392
 393         u8         egress_hoq_high[0x20];
 394
 395         u8         egress_hoq_low[0x20];
 396
 397         u8         port_isolation_high[0x20];
 398
 399         u8         port_isolation_low[0x20];
 400
 401         u8         egress_policy_engine_high[0x20];
 402
 403         u8         egress_policy_engine_low[0x20];
 404
 405         u8         ingress_tx_link_down_high[0x20];
 406
 407         u8         ingress_tx_link_down_low[0x20];
 408
 409         u8         egress_stp_filter_high[0x20];
 410
 411         u8         egress_stp_filter_low[0x20];
 412
 413         u8         egress_hoq_stall_high[0x20];
 414
 415         u8         egress_hoq_stall_low[0x20];
 416
 417         u8         reserved_at_340[0x440];
 418 };
 419 struct mlx5_ifc_flow_table_prop_layout_bits {
 420         u8         ft_support[0x1];
 421         u8         flow_tag[0x1];
 422         u8         flow_counter[0x1];
 423         u8         flow_modify_en[0x1];
 424         u8         modify_root[0x1];
 425         u8         identified_miss_table[0x1];
 426         u8         flow_table_modify[0x1];
 427         u8         encap[0x1];
 428         u8         decap[0x1];
 429         u8         reset_root_to_default[0x1];
 430         u8         reserved_at_a[0x16];
 431
 432         u8         reserved_at_20[0x2];
 433         u8         log_max_ft_size[0x6];
 434         u8         reserved_at_28[0x10];
 435         u8         max_ft_level[0x8];
 436
 437         u8         reserved_at_40[0x20];
 438
 439         u8         reserved_at_60[0x18];
 440         u8         log_max_ft_num[0x8];
 441
 442         u8         reserved_at_80[0x10];
 443         u8         log_max_flow_counter[0x8];
 444         u8         log_max_destination[0x8];
 445
 446         u8         reserved_at_a0[0x18];
 447         u8         log_max_flow[0x8];
 448
 449         u8         reserved_at_c0[0x40];
 450
 451         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 452
 453         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 454 };
 455
 456 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 457         u8         send[0x1];
 458         u8         receive[0x1];
 459         u8         write[0x1];
 460         u8         read[0x1];
 461         u8         atomic[0x1];
 462         u8         srq_receive[0x1];
 463         u8         reserved_0[0x1a];
 464 };
 465
 466 struct mlx5_ifc_flow_counter_list_bits {
 467         u8         reserved_0[0x10];
 468         u8         flow_counter_id[0x10];
 469
 470         u8         reserved_1[0x20];
 471 };
 472
 473 enum {
 474         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 475         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 476         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 477         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 478 };
 479
 480 struct mlx5_ifc_dest_format_struct_bits {
 481         u8         destination_type[0x8];
 482         u8         destination_id[0x18];
 483
 484         u8         reserved_0[0x20];
 485 };
 486
 487 struct mlx5_ifc_ipv4_layout_bits {
 488         u8         reserved_at_0[0x60];
 489
 490         u8         ipv4[0x20];
 491 };
 492
 493 struct mlx5_ifc_ipv6_layout_bits {
 494         u8         ipv6[16][0x8];
 495 };
 496
 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 498         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 499         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 500         u8         reserved_at_0[0x80];
 501 };
 502
 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 504         u8         smac_47_16[0x20];
 505
 506         u8         smac_15_0[0x10];
 507         u8         ethertype[0x10];
 508
 509         u8         dmac_47_16[0x20];
 510
 511         u8         dmac_15_0[0x10];
 512         u8         first_prio[0x3];
 513         u8         first_cfi[0x1];
 514         u8         first_vid[0xc];
 515
 516         u8         ip_protocol[0x8];
 517         u8         ip_dscp[0x6];
 518         u8         ip_ecn[0x2];
 519         u8         cvlan_tag[0x1];
 520         u8         svlan_tag[0x1];
 521         u8         frag[0x1];
 522         u8         reserved_1[0x4];
 523         u8         tcp_flags[0x9];
 524
 525         u8         tcp_sport[0x10];
 526         u8         tcp_dport[0x10];
 527
 528         u8         reserved_2[0x20];
 529
 530         u8         udp_sport[0x10];
 531         u8         udp_dport[0x10];
 532
 533         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 534
 535         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 536 };
 537
 538 struct mlx5_ifc_fte_match_set_misc_bits {
 539         u8         reserved_0[0x8];
 540         u8         source_sqn[0x18];
 541
 542         u8         reserved_1[0x10];
 543         u8         source_port[0x10];
 544
 545         u8         outer_second_prio[0x3];
 546         u8         outer_second_cfi[0x1];
 547         u8         outer_second_vid[0xc];
 548         u8         inner_second_prio[0x3];
 549         u8         inner_second_cfi[0x1];
 550         u8         inner_second_vid[0xc];
 551
 552         u8         outer_second_vlan_tag[0x1];
 553         u8         inner_second_vlan_tag[0x1];
 554         u8         reserved_2[0xe];
 555         u8         gre_protocol[0x10];
 556
 557         u8         gre_key_h[0x18];
 558         u8         gre_key_l[0x8];
 559
 560         u8         vxlan_vni[0x18];
 561         u8         reserved_3[0x8];
 562
 563         u8         geneve_vni[0x18];
 564         u8         reserved4[0x7];
 565         u8         geneve_oam[0x1];
 566
 567         u8         reserved_5[0xc];
 568         u8         outer_ipv6_flow_label[0x14];
 569
 570         u8         reserved_6[0xc];
 571         u8         inner_ipv6_flow_label[0x14];
 572
 573         u8         reserved_7[0xa];
 574         u8         geneve_opt_len[0x6];
 575         u8         geneve_protocol_type[0x10];
 576
 577         u8         reserved_8[0x8];
 578         u8         bth_dst_qp[0x18];
 579
 580         u8         reserved_9[0xa0];
 581 };
 582
 583 struct mlx5_ifc_cmd_pas_bits {
 584         u8         pa_h[0x20];
 585
 586         u8         pa_l[0x14];
 587         u8         reserved_0[0xc];
 588 };
 589
 590 struct mlx5_ifc_uint64_bits {
 591         u8         hi[0x20];
 592
 593         u8         lo[0x20];
 594 };
 595
 596 struct mlx5_ifc_application_prio_entry_bits {
 597         u8         reserved_0[0x8];
 598         u8         priority[0x3];
 599         u8         reserved_1[0x2];
 600         u8         sel[0x3];
 601         u8         protocol_id[0x10];
 602 };
 603
 604 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 605         u8         reserved_0[0x8];
 606         u8         ring_pi[0x10];
 607         u8         reserved_1[0x8];
 608 };
 609
 610 enum {
 611         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 612         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 613         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 614         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 615         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 616         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 617         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 618         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 619         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 620         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 621 };
 622
 623 struct mlx5_ifc_ads_bits {
 624         u8         fl[0x1];
 625         u8         free_ar[0x1];
 626         u8         reserved_0[0xe];
 627         u8         pkey_index[0x10];
 628
 629         u8         reserved_1[0x8];
 630         u8         grh[0x1];
 631         u8         mlid[0x7];
 632         u8         rlid[0x10];
 633
 634         u8         ack_timeout[0x5];
 635         u8         reserved_2[0x3];
 636         u8         src_addr_index[0x8];
 637         u8         log_rtm[0x4];
 638         u8         stat_rate[0x4];
 639         u8         hop_limit[0x8];
 640
 641         u8         reserved_3[0x4];
 642         u8         tclass[0x8];
 643         u8         flow_label[0x14];
 644
 645         u8         rgid_rip[16][0x8];
 646
 647         u8         reserved_4[0x4];
 648         u8         f_dscp[0x1];
 649         u8         f_ecn[0x1];
 650         u8         reserved_5[0x1];
 651         u8         f_eth_prio[0x1];
 652         u8         ecn[0x2];
 653         u8         dscp[0x6];
 654         u8         udp_sport[0x10];
 655
 656         u8         dei_cfi[0x1];
 657         u8         eth_prio[0x3];
 658         u8         sl[0x4];
 659         u8         port[0x8];
 660         u8         rmac_47_32[0x10];
 661
 662         u8         rmac_31_0[0x20];
 663 };
 664
 665 struct mlx5_ifc_diagnostic_counter_cap_bits {
 666         u8         sync[0x1];
 667         u8         reserved_0[0xf];
 668         u8         counter_id[0x10];
 669 };
 670
 671 struct mlx5_ifc_debug_cap_bits {
 672         u8         reserved_0[0x18];
 673         u8         log_max_samples[0x8];
 674
 675         u8         single[0x1];
 676         u8         repetitive[0x1];
 677         u8         health_mon_rx_activity[0x1];
 678         u8         reserved_1[0x15];
 679         u8         log_min_sample_period[0x8];
 680
 681         u8         reserved_2[0x1c0];
 682
 683         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 684 };
 685
 686 struct mlx5_ifc_qos_cap_bits {
 687         u8         packet_pacing[0x1];
 688         u8         esw_scheduling[0x1];
 689         u8         esw_bw_share[0x1];
 690         u8         esw_rate_limit[0x1];
 691         u8         hll[0x1];
 692         u8         packet_pacing_burst_bound[0x1];
 693         u8         reserved_at_6[0x1a];
 694
 695         u8         reserved_at_20[0x20];
 696
 697         u8         packet_pacing_max_rate[0x20];
 698
 699         u8         packet_pacing_min_rate[0x20];
 700
 701         u8         reserved_at_80[0x10];
 702         u8         packet_pacing_rate_table_size[0x10];
 703
 704         u8         esw_element_type[0x10];
 705         u8         esw_tsar_type[0x10];
 706
 707         u8         reserved_at_c0[0x10];
 708         u8         max_qos_para_vport[0x10];
 709
 710         u8         max_tsar_bw_share[0x20];
 711
 712         u8         reserved_at_100[0x700];
 713 };
 714
 715 struct mlx5_ifc_snapshot_cap_bits {
 716         u8         reserved_0[0x1d];
 717         u8         suspend_qp_uc[0x1];
 718         u8         suspend_qp_ud[0x1];
 719         u8         suspend_qp_rc[0x1];
 720
 721         u8         reserved_1[0x1c];
 722         u8         restore_pd[0x1];
 723         u8         restore_uar[0x1];
 724         u8         restore_mkey[0x1];
 725         u8         restore_qp[0x1];
 726
 727         u8         reserved_2[0x1e];
 728         u8         named_mkey[0x1];
 729         u8         named_qp[0x1];
 730
 731         u8         reserved_3[0x7a0];
 732 };
 733
 734 struct mlx5_ifc_e_switch_cap_bits {
 735         u8         vport_svlan_strip[0x1];
 736         u8         vport_cvlan_strip[0x1];
 737         u8         vport_svlan_insert[0x1];
 738         u8         vport_cvlan_insert_if_not_exist[0x1];
 739         u8         vport_cvlan_insert_overwrite[0x1];
 740
 741         u8         reserved_0[0x19];
 742
 743         u8         nic_vport_node_guid_modify[0x1];
 744         u8         nic_vport_port_guid_modify[0x1];
 745
 746         u8         reserved_1[0x7e0];
 747 };
 748
 749 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 750         u8         reserved_0[0x200];
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 757
 758         u8         reserved_1[0x7800];
 759 };
 760
 761 struct mlx5_ifc_flow_table_nic_cap_bits {
 762         u8         nic_rx_multi_path_tirs[0x1];
 763         u8         nic_rx_multi_path_tirs_fts[0x1];
 764         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 765         u8         reserved_at_3[0x1fd];
 766
 767         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 768
 769         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 770
 771         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 772
 773         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 774
 775         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 776
 777         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 778
 779         u8         reserved_1[0x7200];
 780 };
 781
 782 enum {
 783         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR                   = 0x5031,
 784 };
 785
 786 struct mlx5_ifc_pddr_module_info_bits {
 787         u8         cable_technology[0x8];
 788         u8         cable_breakout[0x8];
 789         u8         ext_ethernet_compliance_code[0x8];
 790         u8         ethernet_compliance_code[0x8];
 791
 792         u8         cable_type[0x4];
 793         u8         cable_vendor[0x4];
 794         u8         cable_length[0x8];
 795         u8         cable_identifier[0x8];
 796         u8         cable_power_class[0x8];
 797
 798         u8         reserved_at_40[0x8];
 799         u8         cable_rx_amp[0x8];
 800         u8         cable_rx_emphasis[0x8];
 801         u8         cable_tx_equalization[0x8];
 802
 803         u8         reserved_at_60[0x8];
 804         u8         cable_attenuation_12g[0x8];
 805         u8         cable_attenuation_7g[0x8];
 806         u8         cable_attenuation_5g[0x8];
 807
 808         u8         reserved_at_80[0x8];
 809         u8         rx_cdr_cap[0x4];
 810         u8         tx_cdr_cap[0x4];
 811         u8         reserved_at_90[0x4];
 812         u8         rx_cdr_state[0x4];
 813         u8         reserved_at_98[0x4];
 814         u8         tx_cdr_state[0x4];
 815
 816         u8         vendor_name[16][0x8];
 817
 818         u8         vendor_pn[16][0x8];
 819
 820         u8         vendor_rev[0x20];
 821
 822         u8         fw_version[0x20];
 823
 824         u8         vendor_sn[16][0x8];
 825
 826         u8         temperature[0x10];
 827         u8         voltage[0x10];
 828
 829         u8         rx_power_lane0[0x10];
 830         u8         rx_power_lane1[0x10];
 831
 832         u8         rx_power_lane2[0x10];
 833         u8         rx_power_lane3[0x10];
 834
 835         u8         reserved_at_2c0[0x40];
 836
 837         u8         tx_power_lane0[0x10];
 838         u8         tx_power_lane1[0x10];
 839
 840         u8         tx_power_lane2[0x10];
 841         u8         tx_power_lane3[0x10];
 842
 843         u8         reserved_at_340[0x40];
 844
 845         u8         tx_bias_lane0[0x10];
 846         u8         tx_bias_lane1[0x10];
 847
 848         u8         tx_bias_lane2[0x10];
 849         u8         tx_bias_lane3[0x10];
 850
 851         u8         reserved_at_3c0[0x40];
 852
 853         u8         temperature_high_th[0x10];
 854         u8         temperature_low_th[0x10];
 855
 856         u8         voltage_high_th[0x10];
 857         u8         voltage_low_th[0x10];
 858
 859         u8         rx_power_high_th[0x10];
 860         u8         rx_power_low_th[0x10];
 861
 862         u8         tx_power_high_th[0x10];
 863         u8         tx_power_low_th[0x10];
 864
 865         u8         tx_bias_high_th[0x10];
 866         u8         tx_bias_low_th[0x10];
 867
 868         u8         reserved_at_4a0[0x10];
 869         u8         wavelength[0x10];
 870
 871         u8         reserved_at_4c0[0x300];
 872 };
 873
 874 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
 875         struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
 876         u8         reserved_at_0[0x7c0];
 877 };
 878
 879 struct mlx5_ifc_pddr_reg_bits {
 880         u8         reserved_at_0[0x8];
 881         u8         local_port[0x8];
 882         u8         pnat[0x2];
 883         u8         reserved_at_12[0xe];
 884
 885         u8         reserved_at_20[0x18];
 886         u8         page_select[0x8];
 887
 888         union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
 889 };
 890
 891 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 892         u8         csum_cap[0x1];
 893         u8         vlan_cap[0x1];
 894         u8         lro_cap[0x1];
 895         u8         lro_psh_flag[0x1];
 896         u8         lro_time_stamp[0x1];
 897         u8         lro_max_msg_sz_mode[0x2];
 898         u8         wqe_vlan_insert[0x1];
 899         u8         self_lb_en_modifiable[0x1];
 900         u8         self_lb_mc[0x1];
 901         u8         self_lb_uc[0x1];
 902         u8         max_lso_cap[0x5];
 903         u8         multi_pkt_send_wqe[0x2];
 904         u8         wqe_inline_mode[0x2];
 905         u8         rss_ind_tbl_cap[0x4];
 906         u8         scatter_fcs[0x1];
 907         u8         reserved_1[0x2];
 908         u8         tunnel_lso_const_out_ip_id[0x1];
 909         u8         tunnel_lro_gre[0x1];
 910         u8         tunnel_lro_vxlan[0x1];
 911         u8         tunnel_statless_gre[0x1];
 912         u8         tunnel_stateless_vxlan[0x1];
 913
 914         u8         swp[0x1];
 915         u8         swp_csum[0x1];
 916         u8         swp_lso[0x1];
 917         u8         reserved_2[0x1b];
 918         u8         max_geneve_opt_len[0x1];
 919         u8         tunnel_stateless_geneve_rx[0x1];
 920
 921         u8         reserved_3[0x10];
 922         u8         lro_min_mss_size[0x10];
 923
 924         u8         reserved_4[0x120];
 925
 926         u8         lro_timer_supported_periods[4][0x20];
 927
 928         u8         reserved_5[0x600];
 929 };
 930
 931 enum {
 932         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 933         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 934         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 935 };
 936
 937 struct mlx5_ifc_roce_cap_bits {
 938         u8         roce_apm[0x1];
 939         u8         rts2rts_primary_eth_prio[0x1];
 940         u8         roce_rx_allow_untagged[0x1];
 941         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 942
 943         u8         reserved_0[0x1c];
 944
 945         u8         reserved_1[0x60];
 946
 947         u8         reserved_2[0xc];
 948         u8         l3_type[0x4];
 949         u8         reserved_3[0x8];
 950         u8         roce_version[0x8];
 951
 952         u8         reserved_4[0x10];
 953         u8         r_roce_dest_udp_port[0x10];
 954
 955         u8         r_roce_max_src_udp_port[0x10];
 956         u8         r_roce_min_src_udp_port[0x10];
 957
 958         u8         reserved_5[0x10];
 959         u8         roce_address_table_size[0x10];
 960
 961         u8         reserved_6[0x700];
 962 };
 963
 964 enum {
 965         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 966         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 967         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 968         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 969         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 970         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 971         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 972         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 973         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 974 };
 975
 976 enum {
 977         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 978         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 979         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 980         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 981         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 982         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 983         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 984         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 985         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 986 };
 987
 988 struct mlx5_ifc_atomic_caps_bits {
 989         u8         reserved_0[0x40];
 990
 991         u8         atomic_req_8B_endianess_mode[0x2];
 992         u8         reserved_1[0x4];
 993         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 994
 995         u8         reserved_2[0x19];
 996
 997         u8         reserved_3[0x20];
 998
 999         u8         reserved_4[0x10];
1000         u8         atomic_operations[0x10];
1001
1002         u8         reserved_5[0x10];
1003         u8         atomic_size_qp[0x10];
1004
1005         u8         reserved_6[0x10];
1006         u8         atomic_size_dc[0x10];
1007
1008         u8         reserved_7[0x720];
1009 };
1010
1011 struct mlx5_ifc_odp_cap_bits {
1012         u8         reserved_0[0x40];
1013
1014         u8         sig[0x1];
1015         u8         reserved_1[0x1f];
1016
1017         u8         reserved_2[0x20];
1018
1019         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1020
1021         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1022
1023         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1024
1025         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1026
1027         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1028
1029         u8         reserved_3[0x6e0];
1030 };
1031
1032 enum {
1033         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1034         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1035         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1036         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1037         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1038 };
1039
1040 enum {
1041         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1042         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1043         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1044         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1045         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1046         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1047 };
1048
1049 enum {
1050         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1051         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1052 };
1053
1054 enum {
1055         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1056         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1057         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1058 };
1059
1060 struct mlx5_ifc_cmd_hca_cap_bits {
1061         u8         reserved_0[0x80];
1062
1063         u8         log_max_srq_sz[0x8];
1064         u8         log_max_qp_sz[0x8];
1065         u8         reserved_1[0xb];
1066         u8         log_max_qp[0x5];
1067
1068         u8         reserved_2[0xb];
1069         u8         log_max_srq[0x5];
1070         u8         reserved_3[0x10];
1071
1072         u8         reserved_4[0x8];
1073         u8         log_max_cq_sz[0x8];
1074         u8         reserved_5[0xb];
1075         u8         log_max_cq[0x5];
1076
1077         u8         log_max_eq_sz[0x8];
1078         u8         relaxed_ordering_write[1];
1079         u8         reserved_6[0x1];
1080         u8         log_max_mkey[0x6];
1081         u8         reserved_7[0xb];
1082         u8         fast_teardown[0x1];
1083         u8         log_max_eq[0x4];
1084
1085         u8         max_indirection[0x8];
1086         u8         reserved_8[0x1];
1087         u8         log_max_mrw_sz[0x7];
1088         u8         force_teardown[0x1];
1089         u8         reserved_9[0x1];
1090         u8         log_max_bsf_list_size[0x6];
1091         u8         reserved_10[0x2];
1092         u8         log_max_klm_list_size[0x6];
1093
1094         u8         reserved_11[0xa];
1095         u8         log_max_ra_req_dc[0x6];
1096         u8         reserved_12[0xa];
1097         u8         log_max_ra_res_dc[0x6];
1098
1099         u8         reserved_13[0xa];
1100         u8         log_max_ra_req_qp[0x6];
1101         u8         reserved_14[0xa];
1102         u8         log_max_ra_res_qp[0x6];
1103
1104         u8         pad_cap[0x1];
1105         u8         cc_query_allowed[0x1];
1106         u8         cc_modify_allowed[0x1];
1107         u8         start_pad[0x1];
1108         u8         cache_line_128byte[0x1];
1109         u8         reserved_at_165[0xa];
1110         u8         qcam_reg[0x1];
1111         u8         gid_table_size[0x10];
1112
1113         u8         out_of_seq_cnt[0x1];
1114         u8         vport_counters[0x1];
1115         u8         retransmission_q_counters[0x1];
1116         u8         debug[0x1];
1117         u8         modify_rq_counters_set_id[0x1];
1118         u8         rq_delay_drop[0x1];
1119         u8         max_qp_cnt[0xa];
1120         u8         pkey_table_size[0x10];
1121
1122         u8         vport_group_manager[0x1];
1123         u8         vhca_group_manager[0x1];
1124         u8         ib_virt[0x1];
1125         u8         eth_virt[0x1];
1126         u8         reserved_17[0x1];
1127         u8         ets[0x1];
1128         u8         nic_flow_table[0x1];
1129         u8         eswitch_flow_table[0x1];
1130         u8         reserved_18[0x1];
1131         u8         mcam_reg[0x1];
1132         u8         pcam_reg[0x1];
1133         u8         local_ca_ack_delay[0x5];
1134         u8         port_module_event[0x1];
1135         u8         reserved_19[0x5];
1136         u8         port_type[0x2];
1137         u8         num_ports[0x8];
1138
1139         u8         snapshot[0x1];
1140         u8         reserved_20[0x2];
1141         u8         log_max_msg[0x5];
1142         u8         reserved_21[0x4];
1143         u8         max_tc[0x4];
1144         u8         temp_warn_event[0x1];
1145         u8         dcbx[0x1];
1146         u8         general_notification_event[0x1];
1147         u8         reserved_at_1d3[0x2];
1148         u8         fpga[0x1];
1149         u8         rol_s[0x1];
1150         u8         rol_g[0x1];
1151         u8         reserved_23[0x1];
1152         u8         wol_s[0x1];
1153         u8         wol_g[0x1];
1154         u8         wol_a[0x1];
1155         u8         wol_b[0x1];
1156         u8         wol_m[0x1];
1157         u8         wol_u[0x1];
1158         u8         wol_p[0x1];
1159
1160         u8         stat_rate_support[0x10];
1161         u8         reserved_24[0xc];
1162         u8         cqe_version[0x4];
1163
1164         u8         compact_address_vector[0x1];
1165         u8         striding_rq[0x1];
1166         u8         reserved_25[0x1];
1167         u8         ipoib_enhanced_offloads[0x1];
1168         u8         ipoib_ipoib_offloads[0x1];
1169         u8         reserved_26[0x8];
1170         u8         dc_connect_qp[0x1];
1171         u8         dc_cnak_trace[0x1];
1172         u8         drain_sigerr[0x1];
1173         u8         cmdif_checksum[0x2];
1174         u8         sigerr_cqe[0x1];
1175         u8         reserved_27[0x1];
1176         u8         wq_signature[0x1];
1177         u8         sctr_data_cqe[0x1];
1178         u8         reserved_28[0x1];
1179         u8         sho[0x1];
1180         u8         tph[0x1];
1181         u8         rf[0x1];
1182         u8         dct[0x1];
1183         u8         qos[0x1];
1184         u8         eth_net_offloads[0x1];
1185         u8         roce[0x1];
1186         u8         atomic[0x1];
1187         u8         reserved_30[0x1];
1188
1189         u8         cq_oi[0x1];
1190         u8         cq_resize[0x1];
1191         u8         cq_moderation[0x1];
1192         u8         cq_period_mode_modify[0x1];
1193         u8         cq_invalidate[0x1];
1194         u8         reserved_at_225[0x1];
1195         u8         cq_eq_remap[0x1];
1196         u8         pg[0x1];
1197         u8         block_lb_mc[0x1];
1198         u8         exponential_backoff[0x1];
1199         u8         scqe_break_moderation[0x1];
1200         u8         cq_period_start_from_cqe[0x1];
1201         u8         cd[0x1];
1202         u8         atm[0x1];
1203         u8         apm[0x1];
1204         u8         imaicl[0x1];
1205         u8         reserved_32[0x6];
1206         u8         qkv[0x1];
1207         u8         pkv[0x1];
1208         u8         set_deth_sqpn[0x1];
1209         u8         reserved_33[0x3];
1210         u8         xrc[0x1];
1211         u8         ud[0x1];
1212         u8         uc[0x1];
1213         u8         rc[0x1];
1214
1215         u8         reserved_34[0xa];
1216         u8         uar_sz[0x6];
1217         u8         reserved_35[0x8];
1218         u8         log_pg_sz[0x8];
1219
1220         u8         bf[0x1];
1221         u8         driver_version[0x1];
1222         u8         pad_tx_eth_packet[0x1];
1223         u8         reserved_36[0x8];
1224         u8         log_bf_reg_size[0x5];
1225         u8         reserved_37[0x10];
1226
1227         u8         num_of_diagnostic_counters[0x10];
1228         u8         max_wqe_sz_sq[0x10];
1229
1230         u8         reserved_38[0x10];
1231         u8         max_wqe_sz_rq[0x10];
1232
1233         u8         reserved_39[0x10];
1234         u8         max_wqe_sz_sq_dc[0x10];
1235
1236         u8         reserved_40[0x7];
1237         u8         max_qp_mcg[0x19];
1238
1239         u8         reserved_41[0x18];
1240         u8         log_max_mcg[0x8];
1241
1242         u8         reserved_42[0x3];
1243         u8         log_max_transport_domain[0x5];
1244         u8         reserved_43[0x3];
1245         u8         log_max_pd[0x5];
1246         u8         reserved_44[0xb];
1247         u8         log_max_xrcd[0x5];
1248
1249         u8         nic_receive_steering_discard[0x1];
1250         u8         reserved_45[0x7];
1251         u8         log_max_flow_counter_bulk[0x8];
1252         u8         max_flow_counter[0x10];
1253
1254         u8         reserved_46[0x3];
1255         u8         log_max_rq[0x5];
1256         u8         reserved_47[0x3];
1257         u8         log_max_sq[0x5];
1258         u8         reserved_48[0x3];
1259         u8         log_max_tir[0x5];
1260         u8         reserved_49[0x3];
1261         u8         log_max_tis[0x5];
1262
1263         u8         basic_cyclic_rcv_wqe[0x1];
1264         u8         reserved_50[0x2];
1265         u8         log_max_rmp[0x5];
1266         u8         reserved_51[0x3];
1267         u8         log_max_rqt[0x5];
1268         u8         reserved_52[0x3];
1269         u8         log_max_rqt_size[0x5];
1270         u8         reserved_53[0x3];
1271         u8         log_max_tis_per_sq[0x5];
1272
1273         u8         reserved_54[0x3];
1274         u8         log_max_stride_sz_rq[0x5];
1275         u8         reserved_55[0x3];
1276         u8         log_min_stride_sz_rq[0x5];
1277         u8         reserved_56[0x3];
1278         u8         log_max_stride_sz_sq[0x5];
1279         u8         reserved_57[0x3];
1280         u8         log_min_stride_sz_sq[0x5];
1281
1282         u8         reserved_58[0x1b];
1283         u8         log_max_wq_sz[0x5];
1284
1285         u8         nic_vport_change_event[0x1];
1286         u8         disable_local_lb[0x1];
1287         u8         reserved_59[0x9];
1288         u8         log_max_vlan_list[0x5];
1289         u8         reserved_60[0x3];
1290         u8         log_max_current_mc_list[0x5];
1291         u8         reserved_61[0x3];
1292         u8         log_max_current_uc_list[0x5];
1293
1294         u8         general_obj_types[0x40];
1295
1296         u8         reserved_at_440[0x8];
1297         u8         create_qp_start_hint[0x18];
1298
1299         u8         reserved_at_460[0x3];
1300         u8         log_max_uctx[0x5];
1301         u8         reserved_at_468[0x3];
1302         u8         log_max_umem[0x5];
1303         u8         max_num_eqs[0x10];
1304
1305         u8         reserved_at_480[0x1];
1306         u8         tls_tx[0x1];
1307         u8         reserved_at_482[0x1];
1308         u8         log_max_l2_table[0x5];
1309         u8         reserved_64[0x8];
1310         u8         log_uar_page_sz[0x10];
1311
1312         u8         reserved_65[0x20];
1313
1314         u8         device_frequency_mhz[0x20];
1315
1316         u8         device_frequency_khz[0x20];
1317
1318         u8         reserved_66[0x80];
1319
1320         u8         log_max_atomic_size_qp[0x8];
1321         u8         reserved_67[0x10];
1322         u8         log_max_atomic_size_dc[0x8];
1323
1324         u8         reserved_at_5a0[0x13];
1325         u8         log_max_dek[0x5];
1326         u8         reserved_at_5b8[0x4];
1327         u8         mini_cqe_resp_stride_index[0x1];
1328         u8         cqe_128_always[0x1];
1329         u8         cqe_compression_128b[0x1];
1330
1331         u8         cqe_compression[0x1];
1332
1333         u8         cqe_compression_timeout[0x10];
1334         u8         cqe_compression_max_num[0x10];
1335
1336         u8         reserved_69[0x220];
1337 };
1338
1339 enum mlx5_flow_destination_type {
1340         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1341         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1342         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1343 };
1344
1345 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1346         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1347         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1348         u8         reserved_0[0x40];
1349 };
1350
1351 struct mlx5_ifc_fte_match_param_bits {
1352         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1353
1354         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1355
1356         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1357
1358         u8         reserved_0[0xa00];
1359 };
1360
1361 enum {
1362         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1363         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1364         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1365         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1366         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1367 };
1368
1369 struct mlx5_ifc_rx_hash_field_select_bits {
1370         u8         l3_prot_type[0x1];
1371         u8         l4_prot_type[0x1];
1372         u8         selected_fields[0x1e];
1373 };
1374
1375 struct mlx5_ifc_tls_capabilities_bits {
1376         u8         tls_1_2_aes_gcm_128[0x1];
1377         u8         tls_1_3_aes_gcm_128[0x1];
1378         u8         tls_1_2_aes_gcm_256[0x1];
1379         u8         tls_1_3_aes_gcm_256[0x1];
1380         u8         reserved_at_4[0x1c];
1381
1382         u8         reserved_at_20[0x7e0];
1383 };
1384
1385 enum {
1386         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1387         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1388         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1389         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1390 };
1391
1392 enum rq_type {
1393         RQ_TYPE_NONE,
1394         RQ_TYPE_STRIDE,
1395 };
1396
1397 enum {
1398         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1399         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1400 };
1401
1402 struct mlx5_ifc_wq_bits {
1403         u8         wq_type[0x4];
1404         u8         wq_signature[0x1];
1405         u8         end_padding_mode[0x2];
1406         u8         cd_slave[0x1];
1407         u8         reserved_0[0x18];
1408
1409         u8         hds_skip_first_sge[0x1];
1410         u8         log2_hds_buf_size[0x3];
1411         u8         reserved_1[0x7];
1412         u8         page_offset[0x5];
1413         u8         lwm[0x10];
1414
1415         u8         reserved_2[0x8];
1416         u8         pd[0x18];
1417
1418         u8         reserved_3[0x8];
1419         u8         uar_page[0x18];
1420
1421         u8         dbr_addr[0x40];
1422
1423         u8         hw_counter[0x20];
1424
1425         u8         sw_counter[0x20];
1426
1427         u8         reserved_4[0xc];
1428         u8         log_wq_stride[0x4];
1429         u8         reserved_5[0x3];
1430         u8         log_wq_pg_sz[0x5];
1431         u8         reserved_6[0x3];
1432         u8         log_wq_sz[0x5];
1433
1434         u8         reserved_7[0x15];
1435         u8         single_wqe_log_num_of_strides[0x3];
1436         u8         two_byte_shift_en[0x1];
1437         u8         reserved_8[0x4];
1438         u8         single_stride_log_num_of_bytes[0x3];
1439
1440         u8         reserved_9[0x4c0];
1441
1442         struct mlx5_ifc_cmd_pas_bits pas[0];
1443 };
1444
1445 struct mlx5_ifc_rq_num_bits {
1446         u8         reserved_0[0x8];
1447         u8         rq_num[0x18];
1448 };
1449
1450 struct mlx5_ifc_mac_address_layout_bits {
1451         u8         reserved_0[0x10];
1452         u8         mac_addr_47_32[0x10];
1453
1454         u8         mac_addr_31_0[0x20];
1455 };
1456
1457 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1458         u8         reserved_0[0xa0];
1459
1460         u8         min_time_between_cnps[0x20];
1461
1462         u8         reserved_1[0x12];
1463         u8         cnp_dscp[0x6];
1464         u8         reserved_2[0x4];
1465         u8         cnp_prio_mode[0x1];
1466         u8         cnp_802p_prio[0x3];
1467
1468         u8         reserved_3[0x720];
1469 };
1470
1471 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1472         u8         reserved_0[0x60];
1473
1474         u8         reserved_1[0x4];
1475         u8         clamp_tgt_rate[0x1];
1476         u8         reserved_2[0x3];
1477         u8         clamp_tgt_rate_after_time_inc[0x1];
1478         u8         reserved_3[0x17];
1479
1480         u8         reserved_4[0x20];
1481
1482         u8         rpg_time_reset[0x20];
1483
1484         u8         rpg_byte_reset[0x20];
1485
1486         u8         rpg_threshold[0x20];
1487
1488         u8         rpg_max_rate[0x20];
1489
1490         u8         rpg_ai_rate[0x20];
1491
1492         u8         rpg_hai_rate[0x20];
1493
1494         u8         rpg_gd[0x20];
1495
1496         u8         rpg_min_dec_fac[0x20];
1497
1498         u8         rpg_min_rate[0x20];
1499
1500         u8         reserved_5[0xe0];
1501
1502         u8         rate_to_set_on_first_cnp[0x20];
1503
1504         u8         dce_tcp_g[0x20];
1505
1506         u8         dce_tcp_rtt[0x20];
1507
1508         u8         rate_reduce_monitor_period[0x20];
1509
1510         u8         reserved_6[0x20];
1511
1512         u8         initial_alpha_value[0x20];
1513
1514         u8         reserved_7[0x4a0];
1515 };
1516
1517 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1518         u8         reserved_0[0x80];
1519
1520         u8         rppp_max_rps[0x20];
1521
1522         u8         rpg_time_reset[0x20];
1523
1524         u8         rpg_byte_reset[0x20];
1525
1526         u8         rpg_threshold[0x20];
1527
1528         u8         rpg_max_rate[0x20];
1529
1530         u8         rpg_ai_rate[0x20];
1531
1532         u8         rpg_hai_rate[0x20];
1533
1534         u8         rpg_gd[0x20];
1535
1536         u8         rpg_min_dec_fac[0x20];
1537
1538         u8         rpg_min_rate[0x20];
1539
1540         u8         reserved_1[0x640];
1541 };
1542
1543 enum {
1544         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1545         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1546         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1547 };
1548
1549 struct mlx5_ifc_resize_field_select_bits {
1550         u8         resize_field_select[0x20];
1551 };
1552
1553 enum {
1554         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1555         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1556         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1557         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1558         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1559         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1560 };
1561
1562 struct mlx5_ifc_modify_field_select_bits {
1563         u8         modify_field_select[0x20];
1564 };
1565
1566 struct mlx5_ifc_field_select_r_roce_np_bits {
1567         u8         field_select_r_roce_np[0x20];
1568 };
1569
1570 enum {
1571         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1572         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1573         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1574         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1575         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1576         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1577         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1578         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1579         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1580         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1581         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1582         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1583         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1584         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1585         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1586 };
1587
1588 struct mlx5_ifc_field_select_r_roce_rp_bits {
1589         u8         field_select_r_roce_rp[0x20];
1590 };
1591
1592 enum {
1593         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1594         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1595         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1596         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1597         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1598         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1599         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1600         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1601         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1602         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1603 };
1604
1605 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1606         u8         field_select_8021qaurp[0x20];
1607 };
1608
1609 struct mlx5_ifc_pptb_reg_bits {
1610         u8         reserved_at_0[0x2];
1611         u8         mm[0x2];
1612         u8         reserved_at_4[0x4];
1613         u8         local_port[0x8];
1614         u8         reserved_at_10[0x6];
1615         u8         cm[0x1];
1616         u8         um[0x1];
1617         u8         pm[0x8];
1618
1619         u8         prio_x_buff[0x20];
1620
1621         u8         pm_msb[0x8];
1622         u8         reserved_at_48[0x10];
1623         u8         ctrl_buff[0x4];
1624         u8         untagged_buff[0x4];
1625 };
1626
1627 struct mlx5_ifc_dcbx_app_reg_bits {
1628         u8         reserved_0[0x8];
1629         u8         port_number[0x8];
1630         u8         reserved_1[0x10];
1631
1632         u8         reserved_2[0x1a];
1633         u8         num_app_prio[0x6];
1634
1635         u8         reserved_3[0x40];
1636
1637         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1638 };
1639
1640 struct mlx5_ifc_dcbx_param_reg_bits {
1641         u8         dcbx_cee_cap[0x1];
1642         u8         dcbx_ieee_cap[0x1];
1643         u8         dcbx_standby_cap[0x1];
1644         u8         reserved_0[0x5];
1645         u8         port_number[0x8];
1646         u8         reserved_1[0xa];
1647         u8         max_application_table_size[0x6];
1648
1649         u8         reserved_2[0x15];
1650         u8         version_oper[0x3];
1651         u8         reserved_3[0x5];
1652         u8         version_admin[0x3];
1653
1654         u8         willing_admin[0x1];
1655         u8         reserved_4[0x3];
1656         u8         pfc_cap_oper[0x4];
1657         u8         reserved_5[0x4];
1658         u8         pfc_cap_admin[0x4];
1659         u8         reserved_6[0x4];
1660         u8         num_of_tc_oper[0x4];
1661         u8         reserved_7[0x4];
1662         u8         num_of_tc_admin[0x4];
1663
1664         u8         remote_willing[0x1];
1665         u8         reserved_8[0x3];
1666         u8         remote_pfc_cap[0x4];
1667         u8         reserved_9[0x14];
1668         u8         remote_num_of_tc[0x4];
1669
1670         u8         reserved_10[0x18];
1671         u8         error[0x8];
1672
1673         u8         reserved_11[0x160];
1674 };
1675
1676 struct mlx5_ifc_qhll_bits {
1677         u8         reserved_at_0[0x8];
1678         u8         local_port[0x8];
1679         u8         reserved_at_10[0x10];
1680
1681         u8         reserved_at_20[0x1b];
1682         u8         hll_time[0x5];
1683
1684         u8         stall_en[0x1];
1685         u8         reserved_at_41[0x1c];
1686         u8         stall_cnt[0x3];
1687 };
1688
1689 struct mlx5_ifc_qetcr_reg_bits {
1690         u8         operation_type[0x2];
1691         u8         cap_local_admin[0x1];
1692         u8         cap_remote_admin[0x1];
1693         u8         reserved_0[0x4];
1694         u8         port_number[0x8];
1695         u8         reserved_1[0x10];
1696
1697         u8         reserved_2[0x20];
1698
1699         u8         tc[8][0x40];
1700
1701         u8         global_configuration[0x40];
1702 };
1703
1704 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1705         u8         queue_address_63_32[0x20];
1706
1707         u8         queue_address_31_12[0x14];
1708         u8         reserved_0[0x6];
1709         u8         log_size[0x6];
1710
1711         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1712
1713         u8         reserved_1[0x8];
1714         u8         queue_number[0x18];
1715
1716         u8         q_key[0x20];
1717
1718         u8         reserved_2[0x10];
1719         u8         pkey_index[0x10];
1720
1721         u8         reserved_3[0x40];
1722 };
1723
1724 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1725         u8         reserved_0[0x8];
1726         u8         cq_ci[0x10];
1727         u8         reserved_1[0x8];
1728 };
1729
1730 enum {
1731         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1732         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1733 };
1734
1735 enum {
1736         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1737         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1738         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1739         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1740 };
1741
1742 struct mlx5_ifc_nodnic_event_word_bits {
1743         u8         driver_reset_needed[0x1];
1744         u8         port_management_change_event[0x1];
1745         u8         reserved_0[0x19];
1746         u8         link_type[0x1];
1747         u8         port_state[0x4];
1748 };
1749
1750 struct mlx5_ifc_nic_vport_change_event_bits {
1751         u8         reserved_0[0x10];
1752         u8         vport_num[0x10];
1753
1754         u8         reserved_1[0xc0];
1755 };
1756
1757 struct mlx5_ifc_pages_req_event_bits {
1758         u8         reserved_0[0x10];
1759         u8         function_id[0x10];
1760
1761         u8         num_pages[0x20];
1762
1763         u8         reserved_1[0xa0];
1764 };
1765
1766 struct mlx5_ifc_cmd_inter_comp_event_bits {
1767         u8         command_completion_vector[0x20];
1768
1769         u8         reserved_0[0xc0];
1770 };
1771
1772 struct mlx5_ifc_stall_vl_event_bits {
1773         u8         reserved_0[0x18];
1774         u8         port_num[0x1];
1775         u8         reserved_1[0x3];
1776         u8         vl[0x4];
1777
1778         u8         reserved_2[0xa0];
1779 };
1780
1781 struct mlx5_ifc_db_bf_congestion_event_bits {
1782         u8         event_subtype[0x8];
1783         u8         reserved_0[0x8];
1784         u8         congestion_level[0x8];
1785         u8         reserved_1[0x8];
1786
1787         u8         reserved_2[0xa0];
1788 };
1789
1790 struct mlx5_ifc_gpio_event_bits {
1791         u8         reserved_0[0x60];
1792
1793         u8         gpio_event_hi[0x20];
1794
1795         u8         gpio_event_lo[0x20];
1796
1797         u8         reserved_1[0x40];
1798 };
1799
1800 struct mlx5_ifc_port_state_change_event_bits {
1801         u8         reserved_0[0x40];
1802
1803         u8         port_num[0x4];
1804         u8         reserved_1[0x1c];
1805
1806         u8         reserved_2[0x80];
1807 };
1808
1809 struct mlx5_ifc_dropped_packet_logged_bits {
1810         u8         reserved_0[0xe0];
1811 };
1812
1813 enum {
1814         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1815         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1816 };
1817
1818 struct mlx5_ifc_cq_error_bits {
1819         u8         reserved_0[0x8];
1820         u8         cqn[0x18];
1821
1822         u8         reserved_1[0x20];
1823
1824         u8         reserved_2[0x18];
1825         u8         syndrome[0x8];
1826
1827         u8         reserved_3[0x80];
1828 };
1829
1830 struct mlx5_ifc_rdma_page_fault_event_bits {
1831         u8         bytes_commited[0x20];
1832
1833         u8         r_key[0x20];
1834
1835         u8         reserved_0[0x10];
1836         u8         packet_len[0x10];
1837
1838         u8         rdma_op_len[0x20];
1839
1840         u8         rdma_va[0x40];
1841
1842         u8         reserved_1[0x5];
1843         u8         rdma[0x1];
1844         u8         write[0x1];
1845         u8         requestor[0x1];
1846         u8         qp_number[0x18];
1847 };
1848
1849 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1850         u8         bytes_committed[0x20];
1851
1852         u8         reserved_0[0x10];
1853         u8         wqe_index[0x10];
1854
1855         u8         reserved_1[0x10];
1856         u8         len[0x10];
1857
1858         u8         reserved_2[0x60];
1859
1860         u8         reserved_3[0x5];
1861         u8         rdma[0x1];
1862         u8         write_read[0x1];
1863         u8         requestor[0x1];
1864         u8         qpn[0x18];
1865 };
1866
1867 enum {
1868         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1869         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1870         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1871 };
1872
1873 struct mlx5_ifc_qp_events_bits {
1874         u8         reserved_0[0xa0];
1875
1876         u8         type[0x8];
1877         u8         reserved_1[0x18];
1878
1879         u8         reserved_2[0x8];
1880         u8         qpn_rqn_sqn[0x18];
1881 };
1882
1883 struct mlx5_ifc_dct_events_bits {
1884         u8         reserved_0[0xc0];
1885
1886         u8         reserved_1[0x8];
1887         u8         dct_number[0x18];
1888 };
1889
1890 struct mlx5_ifc_comp_event_bits {
1891         u8         reserved_0[0xc0];
1892
1893         u8         reserved_1[0x8];
1894         u8         cq_number[0x18];
1895 };
1896
1897 struct mlx5_ifc_fw_version_bits {
1898         u8         major[0x10];
1899         u8         reserved_0[0x10];
1900
1901         u8         minor[0x10];
1902         u8         subminor[0x10];
1903
1904         u8         second[0x8];
1905         u8         minute[0x8];
1906         u8         hour[0x8];
1907         u8         reserved_1[0x8];
1908
1909         u8         year[0x10];
1910         u8         month[0x8];
1911         u8         day[0x8];
1912 };
1913
1914 enum {
1915         MLX5_QPC_STATE_RST        = 0x0,
1916         MLX5_QPC_STATE_INIT       = 0x1,
1917         MLX5_QPC_STATE_RTR        = 0x2,
1918         MLX5_QPC_STATE_RTS        = 0x3,
1919         MLX5_QPC_STATE_SQER       = 0x4,
1920         MLX5_QPC_STATE_SQD        = 0x5,
1921         MLX5_QPC_STATE_ERR        = 0x6,
1922         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1923 };
1924
1925 enum {
1926         MLX5_QPC_ST_RC            = 0x0,
1927         MLX5_QPC_ST_UC            = 0x1,
1928         MLX5_QPC_ST_UD            = 0x2,
1929         MLX5_QPC_ST_XRC           = 0x3,
1930         MLX5_QPC_ST_DCI           = 0x5,
1931         MLX5_QPC_ST_QP0           = 0x7,
1932         MLX5_QPC_ST_QP1           = 0x8,
1933         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1934         MLX5_QPC_ST_REG_UMR       = 0xc,
1935 };
1936
1937 enum {
1938         MLX5_QP_PM_ARMED            = 0x0,
1939         MLX5_QP_PM_REARM            = 0x1,
1940         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1941         MLX5_QP_PM_MIGRATED         = 0x3,
1942 };
1943
1944 enum {
1945         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1946         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1947 };
1948
1949 enum {
1950         MLX5_QPC_MTU_256_BYTES        = 0x1,
1951         MLX5_QPC_MTU_512_BYTES        = 0x2,
1952         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1953         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1954         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1955         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1956 };
1957
1958 enum {
1959         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1960         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1961         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1962         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1963         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1964         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1965         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1966         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1967 };
1968
1969 enum {
1970         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1971         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1972         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1973 };
1974
1975 enum {
1976         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1977         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1978         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1979 };
1980
1981 struct mlx5_ifc_qpc_bits {
1982         u8         state[0x4];
1983         u8         lag_tx_port_affinity[0x4];
1984         u8         st[0x8];
1985         u8         reserved_1[0x3];
1986         u8         pm_state[0x2];
1987         u8         reserved_2[0x7];
1988         u8         end_padding_mode[0x2];
1989         u8         reserved_3[0x2];
1990
1991         u8         wq_signature[0x1];
1992         u8         block_lb_mc[0x1];
1993         u8         atomic_like_write_en[0x1];
1994         u8         latency_sensitive[0x1];
1995         u8         reserved_4[0x1];
1996         u8         drain_sigerr[0x1];
1997         u8         reserved_5[0x2];
1998         u8         pd[0x18];
1999
2000         u8         mtu[0x3];
2001         u8         log_msg_max[0x5];
2002         u8         reserved_6[0x1];
2003         u8         log_rq_size[0x4];
2004         u8         log_rq_stride[0x3];
2005         u8         no_sq[0x1];
2006         u8         log_sq_size[0x4];
2007         u8         reserved_7[0x6];
2008         u8         rlky[0x1];
2009         u8         ulp_stateless_offload_mode[0x4];
2010
2011         u8         counter_set_id[0x8];
2012         u8         uar_page[0x18];
2013
2014         u8         reserved_8[0x8];
2015         u8         user_index[0x18];
2016
2017         u8         reserved_9[0x3];
2018         u8         log_page_size[0x5];
2019         u8         remote_qpn[0x18];
2020
2021         struct mlx5_ifc_ads_bits primary_address_path;
2022
2023         struct mlx5_ifc_ads_bits secondary_address_path;
2024
2025         u8         log_ack_req_freq[0x4];
2026         u8         reserved_10[0x4];
2027         u8         log_sra_max[0x3];
2028         u8         reserved_11[0x2];
2029         u8         retry_count[0x3];
2030         u8         rnr_retry[0x3];
2031         u8         reserved_12[0x1];
2032         u8         fre[0x1];
2033         u8         cur_rnr_retry[0x3];
2034         u8         cur_retry_count[0x3];
2035         u8         reserved_13[0x5];
2036
2037         u8         reserved_14[0x20];
2038
2039         u8         reserved_15[0x8];
2040         u8         next_send_psn[0x18];
2041
2042         u8         reserved_16[0x8];
2043         u8         cqn_snd[0x18];
2044
2045         u8         reserved_at_400[0x8];
2046
2047         u8         deth_sqpn[0x18];
2048         u8         reserved_17[0x20];
2049
2050         u8         reserved_18[0x8];
2051         u8         last_acked_psn[0x18];
2052
2053         u8         reserved_19[0x8];
2054         u8         ssn[0x18];
2055
2056         u8         reserved_20[0x8];
2057         u8         log_rra_max[0x3];
2058         u8         reserved_21[0x1];
2059         u8         atomic_mode[0x4];
2060         u8         rre[0x1];
2061         u8         rwe[0x1];
2062         u8         rae[0x1];
2063         u8         reserved_22[0x1];
2064         u8         page_offset[0x6];
2065         u8         reserved_23[0x3];
2066         u8         cd_slave_receive[0x1];
2067         u8         cd_slave_send[0x1];
2068         u8         cd_master[0x1];
2069
2070         u8         reserved_24[0x3];
2071         u8         min_rnr_nak[0x5];
2072         u8         next_rcv_psn[0x18];
2073
2074         u8         reserved_25[0x8];
2075         u8         xrcd[0x18];
2076
2077         u8         reserved_26[0x8];
2078         u8         cqn_rcv[0x18];
2079
2080         u8         dbr_addr[0x40];
2081
2082         u8         q_key[0x20];
2083
2084         u8         reserved_27[0x5];
2085         u8         rq_type[0x3];
2086         u8         srqn_rmpn[0x18];
2087
2088         u8         reserved_28[0x8];
2089         u8         rmsn[0x18];
2090
2091         u8         hw_sq_wqebb_counter[0x10];
2092         u8         sw_sq_wqebb_counter[0x10];
2093
2094         u8         hw_rq_counter[0x20];
2095
2096         u8         sw_rq_counter[0x20];
2097
2098         u8         reserved_29[0x20];
2099
2100         u8         reserved_30[0xf];
2101         u8         cgs[0x1];
2102         u8         cs_req[0x8];
2103         u8         cs_res[0x8];
2104
2105         u8         dc_access_key[0x40];
2106
2107         u8         rdma_active[0x1];
2108         u8         comm_est[0x1];
2109         u8         suspended[0x1];
2110         u8         reserved_31[0x5];
2111         u8         send_msg_psn[0x18];
2112
2113         u8         reserved_32[0x8];
2114         u8         rcv_msg_psn[0x18];
2115
2116         u8         rdma_va[0x40];
2117
2118         u8         rdma_key[0x20];
2119
2120         u8         reserved_33[0x20];
2121 };
2122
2123 struct mlx5_ifc_roce_addr_layout_bits {
2124         u8         source_l3_address[16][0x8];
2125
2126         u8         reserved_0[0x3];
2127         u8         vlan_valid[0x1];
2128         u8         vlan_id[0xc];
2129         u8         source_mac_47_32[0x10];
2130
2131         u8         source_mac_31_0[0x20];
2132
2133         u8         reserved_1[0x14];
2134         u8         roce_l3_type[0x4];
2135         u8         roce_version[0x8];
2136
2137         u8         reserved_2[0x20];
2138 };
2139
2140 struct mlx5_ifc_rdbc_bits {
2141         u8         reserved_0[0x1c];
2142         u8         type[0x4];
2143
2144         u8         reserved_1[0x20];
2145
2146         u8         reserved_2[0x8];
2147         u8         psn[0x18];
2148
2149         u8         rkey[0x20];
2150
2151         u8         address[0x40];
2152
2153         u8         byte_count[0x20];
2154
2155         u8         reserved_3[0x20];
2156
2157         u8         atomic_resp[32][0x8];
2158 };
2159
2160 enum {
2161         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2162         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2163         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2164         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2165 };
2166
2167 struct mlx5_ifc_flow_context_bits {
2168         u8         reserved_0[0x20];
2169
2170         u8         group_id[0x20];
2171
2172         u8         reserved_1[0x8];
2173         u8         flow_tag[0x18];
2174
2175         u8         reserved_2[0x10];
2176         u8         action[0x10];
2177
2178         u8         reserved_3[0x8];
2179         u8         destination_list_size[0x18];
2180
2181         u8         reserved_4[0x8];
2182         u8         flow_counter_list_size[0x18];
2183
2184         u8         reserved_5[0x140];
2185
2186         struct mlx5_ifc_fte_match_param_bits match_value;
2187
2188         u8         reserved_6[0x600];
2189
2190         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2191 };
2192
2193 enum {
2194         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2195         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2196 };
2197
2198 struct mlx5_ifc_xrc_srqc_bits {
2199         u8         state[0x4];
2200         u8         log_xrc_srq_size[0x4];
2201         u8         reserved_0[0x18];
2202
2203         u8         wq_signature[0x1];
2204         u8         cont_srq[0x1];
2205         u8         reserved_1[0x1];
2206         u8         rlky[0x1];
2207         u8         basic_cyclic_rcv_wqe[0x1];
2208         u8         log_rq_stride[0x3];
2209         u8         xrcd[0x18];
2210
2211         u8         page_offset[0x6];
2212         u8         reserved_2[0x2];
2213         u8         cqn[0x18];
2214
2215         u8         reserved_3[0x20];
2216
2217         u8         reserved_4[0x2];
2218         u8         log_page_size[0x6];
2219         u8         user_index[0x18];
2220
2221         u8         reserved_5[0x20];
2222
2223         u8         reserved_6[0x8];
2224         u8         pd[0x18];
2225
2226         u8         lwm[0x10];
2227         u8         wqe_cnt[0x10];
2228
2229         u8         reserved_7[0x40];
2230
2231         u8         db_record_addr_h[0x20];
2232
2233         u8         db_record_addr_l[0x1e];
2234         u8         reserved_8[0x2];
2235
2236         u8         reserved_9[0x80];
2237 };
2238
2239 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2240         u8         counter_error_queues[0x20];
2241
2242         u8         total_error_queues[0x20];
2243
2244         u8         send_queue_priority_update_flow[0x20];
2245
2246         u8         reserved_at_60[0x20];
2247
2248         u8         nic_receive_steering_discard[0x40];
2249
2250         u8         receive_discard_vport_down[0x40];
2251
2252         u8         transmit_discard_vport_down[0x40];
2253
2254         u8         reserved_at_140[0xec0];
2255 };
2256
2257 struct mlx5_ifc_traffic_counter_bits {
2258         u8         packets[0x40];
2259
2260         u8         octets[0x40];
2261 };
2262
2263 struct mlx5_ifc_tisc_bits {
2264         u8         strict_lag_tx_port_affinity[0x1];
2265         u8         tls_en[0x1];
2266         u8         reserved_at_2[0x2];
2267         u8         lag_tx_port_affinity[0x04];
2268
2269         u8         reserved_at_8[0x4];
2270         u8         prio[0x4];
2271         u8         reserved_1[0x10];
2272
2273         u8         reserved_2[0x100];
2274
2275         u8         reserved_3[0x8];
2276         u8         transport_domain[0x18];
2277
2278         u8         reserved_4[0x8];
2279         u8         underlay_qpn[0x18];
2280
2281         u8         reserved_5[0x8];
2282         u8         pd[0x18];
2283
2284         u8         reserved_6[0x380];
2285 };
2286
2287 enum {
2288         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2289         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2290 };
2291
2292 enum {
2293         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2294         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2295 };
2296
2297 enum {
2298         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2299         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2300         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2301 };
2302
2303 enum {
2304         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2305         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2306 };
2307
2308 struct mlx5_ifc_tirc_bits {
2309         u8         reserved_0[0x20];
2310
2311         u8         disp_type[0x4];
2312         u8         tls_en[0x1];
2313         u8         reserved_at_25[0x1b];
2314
2315         u8         reserved_2[0x40];
2316
2317         u8         reserved_3[0x4];
2318         u8         lro_timeout_period_usecs[0x10];
2319         u8         lro_enable_mask[0x4];
2320         u8         lro_max_msg_sz[0x8];
2321
2322         u8         reserved_4[0x40];
2323
2324         u8         reserved_5[0x8];
2325         u8         inline_rqn[0x18];
2326
2327         u8         rx_hash_symmetric[0x1];
2328         u8         reserved_6[0x1];
2329         u8         tunneled_offload_en[0x1];
2330         u8         reserved_7[0x5];
2331         u8         indirect_table[0x18];
2332
2333         u8         rx_hash_fn[0x4];
2334         u8         reserved_8[0x2];
2335         u8         self_lb_en[0x2];
2336         u8         transport_domain[0x18];
2337
2338         u8         rx_hash_toeplitz_key[10][0x20];
2339
2340         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2341
2342         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2343
2344         u8         reserved_9[0x4c0];
2345 };
2346
2347 enum {
2348         MLX5_SRQC_STATE_GOOD   = 0x0,
2349         MLX5_SRQC_STATE_ERROR  = 0x1,
2350 };
2351
2352 struct mlx5_ifc_srqc_bits {
2353         u8         state[0x4];
2354         u8         log_srq_size[0x4];
2355         u8         reserved_0[0x18];
2356
2357         u8         wq_signature[0x1];
2358         u8         cont_srq[0x1];
2359         u8         reserved_1[0x1];
2360         u8         rlky[0x1];
2361         u8         reserved_2[0x1];
2362         u8         log_rq_stride[0x3];
2363         u8         xrcd[0x18];
2364
2365         u8         page_offset[0x6];
2366         u8         reserved_3[0x2];
2367         u8         cqn[0x18];
2368
2369         u8         reserved_4[0x20];
2370
2371         u8         reserved_5[0x2];
2372         u8         log_page_size[0x6];
2373         u8         reserved_6[0x18];
2374
2375         u8         reserved_7[0x20];
2376
2377         u8         reserved_8[0x8];
2378         u8         pd[0x18];
2379
2380         u8         lwm[0x10];
2381         u8         wqe_cnt[0x10];
2382
2383         u8         reserved_9[0x40];
2384
2385         u8         dbr_addr[0x40];
2386
2387         u8         reserved_10[0x80];
2388 };
2389
2390 enum {
2391         MLX5_SQC_STATE_RST  = 0x0,
2392         MLX5_SQC_STATE_RDY  = 0x1,
2393         MLX5_SQC_STATE_ERR  = 0x3,
2394 };
2395
2396 struct mlx5_ifc_sqc_bits {
2397         u8         rlkey[0x1];
2398         u8         cd_master[0x1];
2399         u8         fre[0x1];
2400         u8         flush_in_error_en[0x1];
2401         u8         allow_multi_pkt_send_wqe[0x1];
2402         u8         min_wqe_inline_mode[0x3];
2403         u8         state[0x4];
2404         u8         reg_umr[0x1];
2405         u8         allow_swp[0x1];
2406         u8         reserved_0[0x12];
2407
2408         u8         reserved_1[0x8];
2409         u8         user_index[0x18];
2410
2411         u8         reserved_2[0x8];
2412         u8         cqn[0x18];
2413
2414         u8         reserved_3[0x80];
2415
2416         u8         qos_para_vport_number[0x10];
2417         u8         packet_pacing_rate_limit_index[0x10];
2418
2419         u8         tis_lst_sz[0x10];
2420         u8         reserved_4[0x10];
2421
2422         u8         reserved_5[0x40];
2423
2424         u8         reserved_6[0x8];
2425         u8         tis_num_0[0x18];
2426
2427         struct mlx5_ifc_wq_bits wq;
2428 };
2429
2430 enum {
2431         MLX5_TSAR_TYPE_DWRR = 0,
2432         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2433         MLX5_TSAR_TYPE_ETS = 2
2434 };
2435
2436 struct mlx5_ifc_tsar_element_attributes_bits {
2437         u8         reserved_0[0x8];
2438         u8         tsar_type[0x8];
2439         u8         reserved_1[0x10];
2440 };
2441
2442 struct mlx5_ifc_vport_element_attributes_bits {
2443         u8         reserved_0[0x10];
2444         u8         vport_number[0x10];
2445 };
2446
2447 struct mlx5_ifc_vport_tc_element_attributes_bits {
2448         u8         traffic_class[0x10];
2449         u8         vport_number[0x10];
2450 };
2451
2452 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2453         u8         reserved_0[0x0C];
2454         u8         traffic_class[0x04];
2455         u8         qos_para_vport_number[0x10];
2456 };
2457
2458 enum {
2459         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2460         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2461         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2462         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2463 };
2464
2465 struct mlx5_ifc_scheduling_context_bits {
2466         u8         element_type[0x8];
2467         u8         reserved_at_8[0x18];
2468
2469         u8         element_attributes[0x20];
2470
2471         u8         parent_element_id[0x20];
2472
2473         u8         reserved_at_60[0x40];
2474
2475         u8         bw_share[0x20];
2476
2477         u8         max_average_bw[0x20];
2478
2479         u8         reserved_at_e0[0x120];
2480 };
2481
2482 struct mlx5_ifc_rqtc_bits {
2483         u8         reserved_0[0xa0];
2484
2485         u8         reserved_1[0x10];
2486         u8         rqt_max_size[0x10];
2487
2488         u8         reserved_2[0x10];
2489         u8         rqt_actual_size[0x10];
2490
2491         u8         reserved_3[0x6a0];
2492
2493         struct mlx5_ifc_rq_num_bits rq_num[0];
2494 };
2495
2496 enum {
2497         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2498         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2499 };
2500
2501 enum {
2502         MLX5_RQC_STATE_RST  = 0x0,
2503         MLX5_RQC_STATE_RDY  = 0x1,
2504         MLX5_RQC_STATE_ERR  = 0x3,
2505 };
2506
2507 enum {
2508         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2509         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2510 };
2511
2512 struct mlx5_ifc_rqc_bits {
2513         u8         rlkey[0x1];
2514         u8         delay_drop_en[0x1];
2515         u8         scatter_fcs[0x1];
2516         u8         vlan_strip_disable[0x1];
2517         u8         mem_rq_type[0x4];
2518         u8         state[0x4];
2519         u8         reserved_1[0x1];
2520         u8         flush_in_error_en[0x1];
2521         u8         reserved_2[0x12];
2522
2523         u8         reserved_3[0x8];
2524         u8         user_index[0x18];
2525
2526         u8         reserved_4[0x8];
2527         u8         cqn[0x18];
2528
2529         u8         counter_set_id[0x8];
2530         u8         reserved_5[0x18];
2531
2532         u8         reserved_6[0x8];
2533         u8         rmpn[0x18];
2534
2535         u8         reserved_7[0xe0];
2536
2537         struct mlx5_ifc_wq_bits wq;
2538 };
2539
2540 enum {
2541         MLX5_RMPC_STATE_RDY  = 0x1,
2542         MLX5_RMPC_STATE_ERR  = 0x3,
2543 };
2544
2545 struct mlx5_ifc_rmpc_bits {
2546         u8         reserved_0[0x8];
2547         u8         state[0x4];
2548         u8         reserved_1[0x14];
2549
2550         u8         basic_cyclic_rcv_wqe[0x1];
2551         u8         reserved_2[0x1f];
2552
2553         u8         reserved_3[0x140];
2554
2555         struct mlx5_ifc_wq_bits wq;
2556 };
2557
2558 enum {
2559         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2560         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2561         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2562 };
2563
2564 struct mlx5_ifc_nic_vport_context_bits {
2565         u8         reserved_0[0x5];
2566         u8         min_wqe_inline_mode[0x3];
2567         u8         reserved_1[0x15];
2568         u8         disable_mc_local_lb[0x1];
2569         u8         disable_uc_local_lb[0x1];
2570         u8         roce_en[0x1];
2571
2572         u8         arm_change_event[0x1];
2573         u8         reserved_2[0x1a];
2574         u8         event_on_mtu[0x1];
2575         u8         event_on_promisc_change[0x1];
2576         u8         event_on_vlan_change[0x1];
2577         u8         event_on_mc_address_change[0x1];
2578         u8         event_on_uc_address_change[0x1];
2579
2580         u8         reserved_3[0xe0];
2581
2582         u8         reserved_4[0x10];
2583         u8         mtu[0x10];
2584
2585         u8         system_image_guid[0x40];
2586
2587         u8         port_guid[0x40];
2588
2589         u8         node_guid[0x40];
2590
2591         u8         reserved_5[0x140];
2592
2593         u8         qkey_violation_counter[0x10];
2594         u8         reserved_6[0x10];
2595
2596         u8         reserved_7[0x420];
2597
2598         u8         promisc_uc[0x1];
2599         u8         promisc_mc[0x1];
2600         u8         promisc_all[0x1];
2601         u8         reserved_8[0x2];
2602         u8         allowed_list_type[0x3];
2603         u8         reserved_9[0xc];
2604         u8         allowed_list_size[0xc];
2605
2606         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2607
2608         u8         reserved_10[0x20];
2609
2610         u8         current_uc_mac_address[0][0x40];
2611 };
2612
2613 enum {
2614         MLX5_ACCESS_MODE_PA        = 0x0,
2615         MLX5_ACCESS_MODE_MTT       = 0x1,
2616         MLX5_ACCESS_MODE_KLM       = 0x2,
2617 };
2618
2619 struct mlx5_ifc_mkc_bits {
2620         u8         reserved_at_0[0x1];
2621         u8         free[0x1];
2622         u8         reserved_at_2[0x1];
2623         u8         access_mode_4_2[0x3];
2624         u8         reserved_at_6[0x7];
2625         u8         relaxed_ordering_write[0x1];
2626         u8         reserved_at_e[0x1];
2627         u8         small_fence_on_rdma_read_response[0x1];
2628         u8         umr_en[0x1];
2629         u8         a[0x1];
2630         u8         rw[0x1];
2631         u8         rr[0x1];
2632         u8         lw[0x1];
2633         u8         lr[0x1];
2634         u8         access_mode[0x2];
2635         u8         reserved_2[0x8];
2636
2637         u8         qpn[0x18];
2638         u8         mkey_7_0[0x8];
2639
2640         u8         reserved_3[0x20];
2641
2642         u8         length64[0x1];
2643         u8         bsf_en[0x1];
2644         u8         sync_umr[0x1];
2645         u8         reserved_4[0x2];
2646         u8         expected_sigerr_count[0x1];
2647         u8         reserved_5[0x1];
2648         u8         en_rinval[0x1];
2649         u8         pd[0x18];
2650
2651         u8         start_addr[0x40];
2652
2653         u8         len[0x40];
2654
2655         u8         bsf_octword_size[0x20];
2656
2657         u8         reserved_6[0x80];
2658
2659         u8         translations_octword_size[0x20];
2660
2661         u8         reserved_7[0x1b];
2662         u8         log_page_size[0x5];
2663
2664         u8         reserved_8[0x20];
2665 };
2666
2667 struct mlx5_ifc_pkey_bits {
2668         u8         reserved_0[0x10];
2669         u8         pkey[0x10];
2670 };
2671
2672 struct mlx5_ifc_array128_auto_bits {
2673         u8         array128_auto[16][0x8];
2674 };
2675
2676 enum {
2677         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2678         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2679         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2680 };
2681
2682 enum {
2683         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2684         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2685         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2686         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2687         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2688         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2689         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2690 };
2691
2692 enum {
2693         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2694         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2695         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2696 };
2697
2698 enum {
2699         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2700         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2701         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2702         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2703 };
2704
2705 enum {
2706         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2707         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2708         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2709         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2710 };
2711
2712 struct mlx5_ifc_hca_vport_context_bits {
2713         u8         field_select[0x20];
2714
2715         u8         reserved_0[0xe0];
2716
2717         u8         sm_virt_aware[0x1];
2718         u8         has_smi[0x1];
2719         u8         has_raw[0x1];
2720         u8         grh_required[0x1];
2721         u8         reserved_1[0x1];
2722         u8         min_wqe_inline_mode[0x3];
2723         u8         reserved_2[0x8];
2724         u8         port_physical_state[0x4];
2725         u8         vport_state_policy[0x4];
2726         u8         port_state[0x4];
2727         u8         vport_state[0x4];
2728
2729         u8         reserved_3[0x20];
2730
2731         u8         system_image_guid[0x40];
2732
2733         u8         port_guid[0x40];
2734
2735         u8         node_guid[0x40];
2736
2737         u8         cap_mask1[0x20];
2738
2739         u8         cap_mask1_field_select[0x20];
2740
2741         u8         cap_mask2[0x20];
2742
2743         u8         cap_mask2_field_select[0x20];
2744
2745         u8         reserved_4[0x80];
2746
2747         u8         lid[0x10];
2748         u8         reserved_5[0x4];
2749         u8         init_type_reply[0x4];
2750         u8         lmc[0x3];
2751         u8         subnet_timeout[0x5];
2752
2753         u8         sm_lid[0x10];
2754         u8         sm_sl[0x4];
2755         u8         reserved_6[0xc];
2756
2757         u8         qkey_violation_counter[0x10];
2758         u8         pkey_violation_counter[0x10];
2759
2760         u8         reserved_7[0xca0];
2761 };
2762
2763 union mlx5_ifc_hca_cap_union_bits {
2764         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2765         struct mlx5_ifc_odp_cap_bits odp_cap;
2766         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2767         struct mlx5_ifc_roce_cap_bits roce_cap;
2768         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2769         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2770         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2771         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2772         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2773         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2774         struct mlx5_ifc_qos_cap_bits qos_cap;
2775         struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2776         u8         reserved_0[0x8000];
2777 };
2778
2779 enum {
2780         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2781         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2782 };
2783
2784 struct mlx5_ifc_flow_table_context_bits {
2785         u8         encap_en[0x1];
2786         u8         decap_en[0x1];
2787         u8         reserved_at_2[0x2];
2788         u8         table_miss_action[0x4];
2789         u8         level[0x8];
2790         u8         reserved_at_10[0x8];
2791         u8         log_size[0x8];
2792
2793         u8         reserved_at_20[0x8];
2794         u8         table_miss_id[0x18];
2795
2796         u8         reserved_at_40[0x8];
2797         u8         lag_master_next_table_id[0x18];
2798
2799         u8         reserved_at_60[0xe0];
2800 };
2801
2802 struct mlx5_ifc_esw_vport_context_bits {
2803         u8         reserved_0[0x3];
2804         u8         vport_svlan_strip[0x1];
2805         u8         vport_cvlan_strip[0x1];
2806         u8         vport_svlan_insert[0x1];
2807         u8         vport_cvlan_insert[0x2];
2808         u8         reserved_1[0x18];
2809
2810         u8         reserved_2[0x20];
2811
2812         u8         svlan_cfi[0x1];
2813         u8         svlan_pcp[0x3];
2814         u8         svlan_id[0xc];
2815         u8         cvlan_cfi[0x1];
2816         u8         cvlan_pcp[0x3];
2817         u8         cvlan_id[0xc];
2818
2819         u8         reserved_3[0x7a0];
2820 };
2821
2822 enum {
2823         MLX5_EQC_STATUS_OK                = 0x0,
2824         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2825 };
2826
2827 enum {
2828         MLX5_EQ_STATE_ARMED = 0x9,
2829         MLX5_EQ_STATE_FIRED = 0xa,
2830 };
2831
2832 struct mlx5_ifc_eqc_bits {
2833         u8         status[0x4];
2834         u8         reserved_0[0x9];
2835         u8         ec[0x1];
2836         u8         oi[0x1];
2837         u8         reserved_1[0x5];
2838         u8         st[0x4];
2839         u8         reserved_2[0x8];
2840
2841         u8         reserved_3[0x20];
2842
2843         u8         reserved_4[0x14];
2844         u8         page_offset[0x6];
2845         u8         reserved_5[0x6];
2846
2847         u8         reserved_6[0x3];
2848         u8         log_eq_size[0x5];
2849         u8         uar_page[0x18];
2850
2851         u8         reserved_7[0x20];
2852
2853         u8         reserved_8[0x18];
2854         u8         intr[0x8];
2855
2856         u8         reserved_9[0x3];
2857         u8         log_page_size[0x5];
2858         u8         reserved_10[0x18];
2859
2860         u8         reserved_11[0x60];
2861
2862         u8         reserved_12[0x8];
2863         u8         consumer_counter[0x18];
2864
2865         u8         reserved_13[0x8];
2866         u8         producer_counter[0x18];
2867
2868         u8         reserved_14[0x80];
2869 };
2870
2871 enum {
2872         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2873         MLX5_DCTC_STATE_DRAINING  = 0x1,
2874         MLX5_DCTC_STATE_DRAINED   = 0x2,
2875 };
2876
2877 enum {
2878         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2879         MLX5_DCTC_CS_RES_NA         = 0x1,
2880         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2881 };
2882
2883 enum {
2884         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2885         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2886         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2887         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2888         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2889 };
2890
2891 struct mlx5_ifc_dctc_bits {
2892         u8         reserved_0[0x4];
2893         u8         state[0x4];
2894         u8         reserved_1[0x18];
2895
2896         u8         reserved_2[0x8];
2897         u8         user_index[0x18];
2898
2899         u8         reserved_3[0x8];
2900         u8         cqn[0x18];
2901
2902         u8         counter_set_id[0x8];
2903         u8         atomic_mode[0x4];
2904         u8         rre[0x1];
2905         u8         rwe[0x1];
2906         u8         rae[0x1];
2907         u8         atomic_like_write_en[0x1];
2908         u8         latency_sensitive[0x1];
2909         u8         rlky[0x1];
2910         u8         reserved_4[0xe];
2911
2912         u8         reserved_5[0x8];
2913         u8         cs_res[0x8];
2914         u8         reserved_6[0x3];
2915         u8         min_rnr_nak[0x5];
2916         u8         reserved_7[0x8];
2917
2918         u8         reserved_8[0x8];
2919         u8         srqn[0x18];
2920
2921         u8         reserved_9[0x8];
2922         u8         pd[0x18];
2923
2924         u8         tclass[0x8];
2925         u8         reserved_10[0x4];
2926         u8         flow_label[0x14];
2927
2928         u8         dc_access_key[0x40];
2929
2930         u8         reserved_11[0x5];
2931         u8         mtu[0x3];
2932         u8         port[0x8];
2933         u8         pkey_index[0x10];
2934
2935         u8         reserved_12[0x8];
2936         u8         my_addr_index[0x8];
2937         u8         reserved_13[0x8];
2938         u8         hop_limit[0x8];
2939
2940         u8         dc_access_key_violation_count[0x20];
2941
2942         u8         reserved_14[0x14];
2943         u8         dei_cfi[0x1];
2944         u8         eth_prio[0x3];
2945         u8         ecn[0x2];
2946         u8         dscp[0x6];
2947
2948         u8         reserved_15[0x40];
2949 };
2950
2951 enum {
2952         MLX5_CQC_STATUS_OK             = 0x0,
2953         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2954         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2955 };
2956
2957 enum {
2958         CQE_SIZE_64                = 0x0,
2959         CQE_SIZE_128               = 0x1,
2960 };
2961
2962 enum {
2963         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2964         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2965 };
2966
2967 enum {
2968         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2969         MLX5_CQ_STATE_ARMED                               = 0x9,
2970         MLX5_CQ_STATE_FIRED                               = 0xa,
2971 };
2972
2973 struct mlx5_ifc_cqc_bits {
2974         u8         status[0x4];
2975         u8         reserved_0[0x4];
2976         u8         cqe_sz[0x3];
2977         u8         cc[0x1];
2978         u8         reserved_1[0x1];
2979         u8         scqe_break_moderation_en[0x1];
2980         u8         oi[0x1];
2981         u8         cq_period_mode[0x2];
2982         u8         cqe_compression_en[0x1];
2983         u8         mini_cqe_res_format[0x2];
2984         u8         st[0x4];
2985         u8         reserved_2[0x8];
2986
2987         u8         reserved_3[0x20];
2988
2989         u8         reserved_4[0x14];
2990         u8         page_offset[0x6];
2991         u8         reserved_5[0x6];
2992
2993         u8         reserved_6[0x3];
2994         u8         log_cq_size[0x5];
2995         u8         uar_page[0x18];
2996
2997         u8         reserved_7[0x4];
2998         u8         cq_period[0xc];
2999         u8         cq_max_count[0x10];
3000
3001         u8         reserved_8[0x18];
3002         u8         c_eqn[0x8];
3003
3004         u8         reserved_9[0x3];
3005         u8         log_page_size[0x5];
3006         u8         reserved_10[0x18];
3007
3008         u8         reserved_11[0x20];
3009
3010         u8         reserved_12[0x8];
3011         u8         last_notified_index[0x18];
3012
3013         u8         reserved_13[0x8];
3014         u8         last_solicit_index[0x18];
3015
3016         u8         reserved_14[0x8];
3017         u8         consumer_counter[0x18];
3018
3019         u8         reserved_15[0x8];
3020         u8         producer_counter[0x18];
3021
3022         u8         reserved_16[0x40];
3023
3024         u8         dbr_addr[0x40];
3025 };
3026
3027 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3028         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3029         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3030         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3031         u8         reserved_0[0x800];
3032 };
3033
3034 struct mlx5_ifc_query_adapter_param_block_bits {
3035         u8         reserved_0[0xc0];
3036
3037         u8         reserved_1[0x8];
3038         u8         ieee_vendor_id[0x18];
3039
3040         u8         reserved_2[0x10];
3041         u8         vsd_vendor_id[0x10];
3042
3043         u8         vsd[208][0x8];
3044
3045         u8         vsd_contd_psid[16][0x8];
3046 };
3047
3048 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3049         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3050         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3051         u8         reserved_0[0x20];
3052 };
3053
3054 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3055         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3056         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3057         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3058         u8         reserved_0[0x20];
3059 };
3060
3061 struct mlx5_ifc_bufferx_reg_bits {
3062         u8         reserved_0[0x6];
3063         u8         lossy[0x1];
3064         u8         epsb[0x1];
3065         u8         reserved_1[0xc];
3066         u8         size[0xc];
3067
3068         u8         xoff_threshold[0x10];
3069         u8         xon_threshold[0x10];
3070 };
3071
3072 struct mlx5_ifc_config_item_bits {
3073         u8         valid[0x2];
3074         u8         reserved_0[0x2];
3075         u8         header_type[0x2];
3076         u8         reserved_1[0x2];
3077         u8         default_location[0x1];
3078         u8         reserved_2[0x7];
3079         u8         version[0x4];
3080         u8         reserved_3[0x3];
3081         u8         length[0x9];
3082
3083         u8         type[0x20];
3084
3085         u8         reserved_4[0x10];
3086         u8         crc16[0x10];
3087 };
3088
3089 struct mlx5_ifc_nodnic_port_config_reg_bits {
3090         struct mlx5_ifc_nodnic_event_word_bits event;
3091
3092         u8         network_en[0x1];
3093         u8         dma_en[0x1];
3094         u8         promisc_en[0x1];
3095         u8         promisc_multicast_en[0x1];
3096         u8         reserved_0[0x17];
3097         u8         receive_filter_en[0x5];
3098
3099         u8         reserved_1[0x10];
3100         u8         mac_47_32[0x10];
3101
3102         u8         mac_31_0[0x20];
3103
3104         u8         receive_filters_mgid_mac[64][0x8];
3105
3106         u8         gid[16][0x8];
3107
3108         u8         reserved_2[0x10];
3109         u8         lid[0x10];
3110
3111         u8         reserved_3[0xc];
3112         u8         sm_sl[0x4];
3113         u8         sm_lid[0x10];
3114
3115         u8         completion_address_63_32[0x20];
3116
3117         u8         completion_address_31_12[0x14];
3118         u8         reserved_4[0x6];
3119         u8         log_cq_size[0x6];
3120
3121         u8         working_buffer_address_63_32[0x20];
3122
3123         u8         working_buffer_address_31_12[0x14];
3124         u8         reserved_5[0xc];
3125
3126         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3127
3128         u8         pkey_index[0x10];
3129         u8         pkey[0x10];
3130
3131         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3132
3133         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3134
3135         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3136
3137         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3138
3139         u8         reserved_6[0x400];
3140 };
3141
3142 union mlx5_ifc_event_auto_bits {
3143         struct mlx5_ifc_comp_event_bits comp_event;
3144         struct mlx5_ifc_dct_events_bits dct_events;
3145         struct mlx5_ifc_qp_events_bits qp_events;
3146         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3147         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3148         struct mlx5_ifc_cq_error_bits cq_error;
3149         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3150         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3151         struct mlx5_ifc_gpio_event_bits gpio_event;
3152         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3153         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3154         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3155         struct mlx5_ifc_pages_req_event_bits pages_req_event;
3156         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3157         u8         reserved_0[0xe0];
3158 };
3159
3160 struct mlx5_ifc_health_buffer_bits {
3161         u8         reserved_0[0x100];
3162
3163         u8         assert_existptr[0x20];
3164
3165         u8         assert_callra[0x20];
3166
3167         u8         reserved_1[0x40];
3168
3169         u8         fw_version[0x20];
3170
3171         u8         hw_id[0x20];
3172
3173         u8         reserved_2[0x20];
3174
3175         u8         irisc_index[0x8];
3176         u8         synd[0x8];
3177         u8         ext_synd[0x10];
3178 };
3179
3180 struct mlx5_ifc_register_loopback_control_bits {
3181         u8         no_lb[0x1];
3182         u8         reserved_0[0x7];
3183         u8         port[0x8];
3184         u8         reserved_1[0x10];
3185
3186         u8         reserved_2[0x60];
3187 };
3188
3189 struct mlx5_ifc_lrh_bits {
3190         u8      vl[4];
3191         u8      lver[4];
3192         u8      sl[4];
3193         u8      reserved2[2];
3194         u8      lnh[2];
3195         u8      dlid[16];
3196         u8      reserved5[5];
3197         u8      pkt_len[11];
3198         u8      slid[16];
3199 };
3200
3201 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3202         u8         reserved_0[0x40];
3203
3204         u8         reserved_1[0x10];
3205         u8         rol_mode[0x8];
3206         u8         wol_mode[0x8];
3207 };
3208
3209 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3210         u8         reserved_0[0x40];
3211
3212         u8         rol_mode_valid[0x1];
3213         u8         wol_mode_valid[0x1];
3214         u8         reserved_1[0xe];
3215         u8         rol_mode[0x8];
3216         u8         wol_mode[0x8];
3217
3218         u8         reserved_2[0x7a0];
3219 };
3220
3221 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3222         u8         virtual_mac_en[0x1];
3223         u8         mac_aux_v[0x1];
3224         u8         reserved_0[0x1e];
3225
3226         u8         reserved_1[0x40];
3227
3228         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3229
3230         u8         reserved_2[0x760];
3231 };
3232
3233 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3234         u8         virtual_mac_en[0x1];
3235         u8         mac_aux_v[0x1];
3236         u8         reserved_0[0x1e];
3237
3238         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3239
3240         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3241
3242         u8         reserved_1[0x760];
3243 };
3244
3245 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3246         struct mlx5_ifc_fw_version_bits fw_version;
3247
3248         u8         reserved_0[0x10];
3249         u8         hash_signature[0x10];
3250
3251         u8         psid[16][0x8];
3252
3253         u8         reserved_1[0x6e0];
3254 };
3255
3256 struct mlx5_ifc_icmd_query_cap_in_bits {
3257         u8         reserved_0[0x10];
3258         u8         capability_group[0x10];
3259 };
3260
3261 struct mlx5_ifc_icmd_query_cap_general_bits {
3262         u8         nv_access[0x1];
3263         u8         fw_info_psid[0x1];
3264         u8         reserved_0[0x1e];
3265
3266         u8         reserved_1[0x16];
3267         u8         rol_s[0x1];
3268         u8         rol_g[0x1];
3269         u8         reserved_2[0x1];
3270         u8         wol_s[0x1];
3271         u8         wol_g[0x1];
3272         u8         wol_a[0x1];
3273         u8         wol_b[0x1];
3274         u8         wol_m[0x1];
3275         u8         wol_u[0x1];
3276         u8         wol_p[0x1];
3277 };
3278
3279 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3280         u8         status[0x8];
3281         u8         reserved_0[0x18];
3282
3283         u8         reserved_1[0x7e0];
3284 };
3285
3286 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3287         u8         status[0x8];
3288         u8         reserved_0[0x18];
3289
3290         u8         reserved_1[0x7e0];
3291 };
3292
3293 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3294         u8         address_hi[0x20];
3295
3296         u8         address_lo[0x20];
3297
3298         u8         reserved_0[0x7c0];
3299 };
3300
3301 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3302         u8         reserved_0[0x20];
3303
3304         u8         address_hi[0x20];
3305
3306         u8         address_lo[0x20];
3307
3308         u8         reserved_1[0x7a0];
3309 };
3310
3311 struct mlx5_ifc_icmd_access_reg_out_bits {
3312         u8         reserved_0[0x11];
3313         u8         status[0x7];
3314         u8         reserved_1[0x8];
3315
3316         u8         register_id[0x10];
3317         u8         reserved_2[0x10];
3318
3319         u8         reserved_3[0x40];
3320
3321         u8         reserved_4[0x5];
3322         u8         len[0xb];
3323         u8         reserved_5[0x10];
3324
3325         u8         register_data[0][0x20];
3326 };
3327
3328 enum {
3329         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3330         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3331 };
3332
3333 struct mlx5_ifc_icmd_access_reg_in_bits {
3334         u8         constant_1[0x5];
3335         u8         constant_2[0xb];
3336         u8         reserved_0[0x10];
3337
3338         u8         register_id[0x10];
3339         u8         reserved_1[0x1];
3340         u8         method[0x7];
3341         u8         constant_3[0x8];
3342
3343         u8         reserved_2[0x40];
3344
3345         u8         constant_4[0x5];
3346         u8         len[0xb];
3347         u8         reserved_3[0x10];
3348
3349         u8         register_data[0][0x20];
3350 };
3351
3352 enum {
3353         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3354         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3355 };
3356
3357 struct mlx5_ifc_teardown_hca_out_bits {
3358         u8         status[0x8];
3359         u8         reserved_0[0x18];
3360
3361         u8         syndrome[0x20];
3362
3363         u8         reserved_1[0x3f];
3364
3365         u8         state[0x1];
3366 };
3367
3368 enum {
3369         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3370         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3371         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3372 };
3373
3374 struct mlx5_ifc_teardown_hca_in_bits {
3375         u8         opcode[0x10];
3376         u8         reserved_0[0x10];
3377
3378         u8         reserved_1[0x10];
3379         u8         op_mod[0x10];
3380
3381         u8         reserved_2[0x10];
3382         u8         profile[0x10];
3383
3384         u8         reserved_3[0x20];
3385 };
3386
3387 struct mlx5_ifc_set_delay_drop_params_out_bits {
3388         u8         status[0x8];
3389         u8         reserved_at_8[0x18];
3390
3391         u8         syndrome[0x20];
3392
3393         u8         reserved_at_40[0x40];
3394 };
3395
3396 struct mlx5_ifc_set_delay_drop_params_in_bits {
3397         u8         opcode[0x10];
3398         u8         reserved_at_10[0x10];
3399
3400         u8         reserved_at_20[0x10];
3401         u8         op_mod[0x10];
3402
3403         u8         reserved_at_40[0x20];
3404
3405         u8         reserved_at_60[0x10];
3406         u8         delay_drop_timeout[0x10];
3407 };
3408
3409 struct mlx5_ifc_query_delay_drop_params_out_bits {
3410         u8         status[0x8];
3411         u8         reserved_at_8[0x18];
3412
3413         u8         syndrome[0x20];
3414
3415         u8         reserved_at_40[0x20];
3416
3417         u8         reserved_at_60[0x10];
3418         u8         delay_drop_timeout[0x10];
3419 };
3420
3421 struct mlx5_ifc_query_delay_drop_params_in_bits {
3422         u8         opcode[0x10];
3423         u8         reserved_at_10[0x10];
3424
3425         u8         reserved_at_20[0x10];
3426         u8         op_mod[0x10];
3427
3428         u8         reserved_at_40[0x40];
3429 };
3430
3431 struct mlx5_ifc_suspend_qp_out_bits {
3432         u8         status[0x8];
3433         u8         reserved_0[0x18];
3434
3435         u8         syndrome[0x20];
3436
3437         u8         reserved_1[0x40];
3438 };
3439
3440 struct mlx5_ifc_suspend_qp_in_bits {
3441         u8         opcode[0x10];
3442         u8         reserved_0[0x10];
3443
3444         u8         reserved_1[0x10];
3445         u8         op_mod[0x10];
3446
3447         u8         reserved_2[0x8];
3448         u8         qpn[0x18];
3449
3450         u8         reserved_3[0x20];
3451 };
3452
3453 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3454         u8         status[0x8];
3455         u8         reserved_0[0x18];
3456
3457         u8         syndrome[0x20];
3458
3459         u8         reserved_1[0x40];
3460 };
3461
3462 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_0[0x10];
3465
3466         u8         reserved_1[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_2[0x8];
3470         u8         qpn[0x18];
3471
3472         u8         reserved_3[0x20];
3473
3474         u8         opt_param_mask[0x20];
3475
3476         u8         reserved_4[0x20];
3477
3478         struct mlx5_ifc_qpc_bits qpc;
3479
3480         u8         reserved_5[0x80];
3481 };
3482
3483 struct mlx5_ifc_sqd2rts_qp_out_bits {
3484         u8         status[0x8];
3485         u8         reserved_0[0x18];
3486
3487         u8         syndrome[0x20];
3488
3489         u8         reserved_1[0x40];
3490 };
3491
3492 struct mlx5_ifc_sqd2rts_qp_in_bits {
3493         u8         opcode[0x10];
3494         u8         reserved_0[0x10];
3495
3496         u8         reserved_1[0x10];
3497         u8         op_mod[0x10];
3498
3499         u8         reserved_2[0x8];
3500         u8         qpn[0x18];
3501
3502         u8         reserved_3[0x20];
3503
3504         u8         opt_param_mask[0x20];
3505
3506         u8         reserved_4[0x20];
3507
3508         struct mlx5_ifc_qpc_bits qpc;
3509
3510         u8         reserved_5[0x80];
3511 };
3512
3513 struct mlx5_ifc_set_wol_rol_out_bits {
3514         u8         status[0x8];
3515         u8         reserved_0[0x18];
3516
3517         u8         syndrome[0x20];
3518
3519         u8         reserved_1[0x40];
3520 };
3521
3522 struct mlx5_ifc_set_wol_rol_in_bits {
3523         u8         opcode[0x10];
3524         u8         reserved_0[0x10];
3525
3526         u8         reserved_1[0x10];
3527         u8         op_mod[0x10];
3528
3529         u8         rol_mode_valid[0x1];
3530         u8         wol_mode_valid[0x1];
3531         u8         reserved_2[0xe];
3532         u8         rol_mode[0x8];
3533         u8         wol_mode[0x8];
3534
3535         u8         reserved_3[0x20];
3536 };
3537
3538 struct mlx5_ifc_set_roce_address_out_bits {
3539         u8         status[0x8];
3540         u8         reserved_0[0x18];
3541
3542         u8         syndrome[0x20];
3543
3544         u8         reserved_1[0x40];
3545 };
3546
3547 struct mlx5_ifc_set_roce_address_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_0[0x10];
3550
3551         u8         reserved_1[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         roce_address_index[0x10];
3555         u8         reserved_2[0x10];
3556
3557         u8         reserved_3[0x20];
3558
3559         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3560 };
3561
3562 struct mlx5_ifc_set_rdb_out_bits {
3563         u8         status[0x8];
3564         u8         reserved_0[0x18];
3565
3566         u8         syndrome[0x20];
3567
3568         u8         reserved_1[0x40];
3569 };
3570
3571 struct mlx5_ifc_set_rdb_in_bits {
3572         u8         opcode[0x10];
3573         u8         reserved_0[0x10];
3574
3575         u8         reserved_1[0x10];
3576         u8         op_mod[0x10];
3577
3578         u8         reserved_2[0x8];
3579         u8         qpn[0x18];
3580
3581         u8         reserved_3[0x18];
3582         u8         rdb_list_size[0x8];
3583
3584         struct mlx5_ifc_rdbc_bits rdb_context[0];
3585 };
3586
3587 struct mlx5_ifc_set_mad_demux_out_bits {
3588         u8         status[0x8];
3589         u8         reserved_0[0x18];
3590
3591         u8         syndrome[0x20];
3592
3593         u8         reserved_1[0x40];
3594 };
3595
3596 enum {
3597         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3598         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3599 };
3600
3601 struct mlx5_ifc_set_mad_demux_in_bits {
3602         u8         opcode[0x10];
3603         u8         reserved_0[0x10];
3604
3605         u8         reserved_1[0x10];
3606         u8         op_mod[0x10];
3607
3608         u8         reserved_2[0x20];
3609
3610         u8         reserved_3[0x6];
3611         u8         demux_mode[0x2];
3612         u8         reserved_4[0x18];
3613 };
3614
3615 struct mlx5_ifc_set_l2_table_entry_out_bits {
3616         u8         status[0x8];
3617         u8         reserved_0[0x18];
3618
3619         u8         syndrome[0x20];
3620
3621         u8         reserved_1[0x40];
3622 };
3623
3624 struct mlx5_ifc_set_l2_table_entry_in_bits {
3625         u8         opcode[0x10];
3626         u8         reserved_0[0x10];
3627
3628         u8         reserved_1[0x10];
3629         u8         op_mod[0x10];
3630
3631         u8         reserved_2[0x60];
3632
3633         u8         reserved_3[0x8];
3634         u8         table_index[0x18];
3635
3636         u8         reserved_4[0x20];
3637
3638         u8         reserved_5[0x13];
3639         u8         vlan_valid[0x1];
3640         u8         vlan[0xc];
3641
3642         struct mlx5_ifc_mac_address_layout_bits mac_address;
3643
3644         u8         reserved_6[0xc0];
3645 };
3646
3647 struct mlx5_ifc_set_issi_out_bits {
3648         u8         status[0x8];
3649         u8         reserved_0[0x18];
3650
3651         u8         syndrome[0x20];
3652
3653         u8         reserved_1[0x40];
3654 };
3655
3656 struct mlx5_ifc_set_issi_in_bits {
3657         u8         opcode[0x10];
3658         u8         reserved_0[0x10];
3659
3660         u8         reserved_1[0x10];
3661         u8         op_mod[0x10];
3662
3663         u8         reserved_2[0x10];
3664         u8         current_issi[0x10];
3665
3666         u8         reserved_3[0x20];
3667 };
3668
3669 struct mlx5_ifc_set_hca_cap_out_bits {
3670         u8         status[0x8];
3671         u8         reserved_0[0x18];
3672
3673         u8         syndrome[0x20];
3674
3675         u8         reserved_1[0x40];
3676 };
3677
3678 struct mlx5_ifc_set_hca_cap_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_0[0x10];
3681
3682         u8         reserved_1[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         reserved_2[0x40];
3686
3687         union mlx5_ifc_hca_cap_union_bits capability;
3688 };
3689
3690 enum {
3691         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3692         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3693         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3694         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3695 };
3696
3697 struct mlx5_ifc_set_flow_table_root_out_bits {
3698         u8         status[0x8];
3699         u8         reserved_0[0x18];
3700
3701         u8         syndrome[0x20];
3702
3703         u8         reserved_1[0x40];
3704 };
3705
3706 struct mlx5_ifc_set_flow_table_root_in_bits {
3707         u8         opcode[0x10];
3708         u8         reserved_0[0x10];
3709
3710         u8         reserved_1[0x10];
3711         u8         op_mod[0x10];
3712
3713         u8         other_vport[0x1];
3714         u8         reserved_2[0xf];
3715         u8         vport_number[0x10];
3716
3717         u8         reserved_3[0x20];
3718
3719         u8         table_type[0x8];
3720         u8         reserved_4[0x18];
3721
3722         u8         reserved_5[0x8];
3723         u8         table_id[0x18];
3724
3725         u8         reserved_6[0x8];
3726         u8         underlay_qpn[0x18];
3727
3728         u8         reserved_7[0x120];
3729 };
3730
3731 struct mlx5_ifc_set_fte_out_bits {
3732         u8         status[0x8];
3733         u8         reserved_0[0x18];
3734
3735         u8         syndrome[0x20];
3736
3737         u8         reserved_1[0x40];
3738 };
3739
3740 struct mlx5_ifc_set_fte_in_bits {
3741         u8         opcode[0x10];
3742         u8         reserved_0[0x10];
3743
3744         u8         reserved_1[0x10];
3745         u8         op_mod[0x10];
3746
3747         u8         other_vport[0x1];
3748         u8         reserved_2[0xf];
3749         u8         vport_number[0x10];
3750
3751         u8         reserved_3[0x20];
3752
3753         u8         table_type[0x8];
3754         u8         reserved_4[0x18];
3755
3756         u8         reserved_5[0x8];
3757         u8         table_id[0x18];
3758
3759         u8         reserved_6[0x18];
3760         u8         modify_enable_mask[0x8];
3761
3762         u8         reserved_7[0x20];
3763
3764         u8         flow_index[0x20];
3765
3766         u8         reserved_8[0xe0];
3767
3768         struct mlx5_ifc_flow_context_bits flow_context;
3769 };
3770
3771 struct mlx5_ifc_set_driver_version_out_bits {
3772         u8         status[0x8];
3773         u8         reserved_0[0x18];
3774
3775         u8         syndrome[0x20];
3776
3777         u8         reserved_1[0x40];
3778 };
3779
3780 struct mlx5_ifc_set_driver_version_in_bits {
3781         u8         opcode[0x10];
3782         u8         reserved_0[0x10];
3783
3784         u8         reserved_1[0x10];
3785         u8         op_mod[0x10];
3786
3787         u8         reserved_2[0x40];
3788
3789         u8         driver_version[64][0x8];
3790 };
3791
3792 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3793         u8         status[0x8];
3794         u8         reserved_0[0x18];
3795
3796         u8         syndrome[0x20];
3797
3798         u8         reserved_1[0x40];
3799 };
3800
3801 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3802         u8         opcode[0x10];
3803         u8         reserved_0[0x10];
3804
3805         u8         reserved_1[0x10];
3806         u8         op_mod[0x10];
3807
3808         u8         enable[0x1];
3809         u8         reserved_2[0x1f];
3810
3811         u8         reserved_3[0x160];
3812
3813         struct mlx5_ifc_cmd_pas_bits pas;
3814 };
3815
3816 struct mlx5_ifc_set_burst_size_out_bits {
3817         u8         status[0x8];
3818         u8         reserved_0[0x18];
3819
3820         u8         syndrome[0x20];
3821
3822         u8         reserved_1[0x40];
3823 };
3824
3825 struct mlx5_ifc_set_burst_size_in_bits {
3826         u8         opcode[0x10];
3827         u8         reserved_0[0x10];
3828
3829         u8         reserved_1[0x10];
3830         u8         op_mod[0x10];
3831
3832         u8         reserved_2[0x20];
3833
3834         u8         reserved_3[0x9];
3835         u8         device_burst_size[0x17];
3836 };
3837
3838 struct mlx5_ifc_rts2rts_qp_out_bits {
3839         u8         status[0x8];
3840         u8         reserved_0[0x18];
3841
3842         u8         syndrome[0x20];
3843
3844         u8         reserved_1[0x40];
3845 };
3846
3847 struct mlx5_ifc_rts2rts_qp_in_bits {
3848         u8         opcode[0x10];
3849         u8         reserved_0[0x10];
3850
3851         u8         reserved_1[0x10];
3852         u8         op_mod[0x10];
3853
3854         u8         reserved_2[0x8];
3855         u8         qpn[0x18];
3856
3857         u8         reserved_3[0x20];
3858
3859         u8         opt_param_mask[0x20];
3860
3861         u8         reserved_4[0x20];
3862
3863         struct mlx5_ifc_qpc_bits qpc;
3864
3865         u8         reserved_5[0x80];
3866 };
3867
3868 struct mlx5_ifc_rtr2rts_qp_out_bits {
3869         u8         status[0x8];
3870         u8         reserved_0[0x18];
3871
3872         u8         syndrome[0x20];
3873
3874         u8         reserved_1[0x40];
3875 };
3876
3877 struct mlx5_ifc_rtr2rts_qp_in_bits {
3878         u8         opcode[0x10];
3879         u8         reserved_0[0x10];
3880
3881         u8         reserved_1[0x10];
3882         u8         op_mod[0x10];
3883
3884         u8         reserved_2[0x8];
3885         u8         qpn[0x18];
3886
3887         u8         reserved_3[0x20];
3888
3889         u8         opt_param_mask[0x20];
3890
3891         u8         reserved_4[0x20];
3892
3893         struct mlx5_ifc_qpc_bits qpc;
3894
3895         u8         reserved_5[0x80];
3896 };
3897
3898 struct mlx5_ifc_rst2init_qp_out_bits {
3899         u8         status[0x8];
3900         u8         reserved_0[0x18];
3901
3902         u8         syndrome[0x20];
3903
3904         u8         reserved_1[0x40];
3905 };
3906
3907 struct mlx5_ifc_rst2init_qp_in_bits {
3908         u8         opcode[0x10];
3909         u8         reserved_0[0x10];
3910
3911         u8         reserved_1[0x10];
3912         u8         op_mod[0x10];
3913
3914         u8         reserved_2[0x8];
3915         u8         qpn[0x18];
3916
3917         u8         reserved_3[0x20];
3918
3919         u8         opt_param_mask[0x20];
3920
3921         u8         reserved_4[0x20];
3922
3923         struct mlx5_ifc_qpc_bits qpc;
3924
3925         u8         reserved_5[0x80];
3926 };
3927
3928 struct mlx5_ifc_resume_qp_out_bits {
3929         u8         status[0x8];
3930         u8         reserved_0[0x18];
3931
3932         u8         syndrome[0x20];
3933
3934         u8         reserved_1[0x40];
3935 };
3936
3937 struct mlx5_ifc_resume_qp_in_bits {
3938         u8         opcode[0x10];
3939         u8         reserved_0[0x10];
3940
3941         u8         reserved_1[0x10];
3942         u8         op_mod[0x10];
3943
3944         u8         reserved_2[0x8];
3945         u8         qpn[0x18];
3946
3947         u8         reserved_3[0x20];
3948 };
3949
3950 struct mlx5_ifc_query_xrc_srq_out_bits {
3951         u8         status[0x8];
3952         u8         reserved_0[0x18];
3953
3954         u8         syndrome[0x20];
3955
3956         u8         reserved_1[0x40];
3957
3958         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3959
3960         u8         reserved_2[0x600];
3961
3962         u8         pas[0][0x40];
3963 };
3964
3965 struct mlx5_ifc_query_xrc_srq_in_bits {
3966         u8         opcode[0x10];
3967         u8         reserved_0[0x10];
3968
3969         u8         reserved_1[0x10];
3970         u8         op_mod[0x10];
3971
3972         u8         reserved_2[0x8];
3973         u8         xrc_srqn[0x18];
3974
3975         u8         reserved_3[0x20];
3976 };
3977
3978 struct mlx5_ifc_query_wol_rol_out_bits {
3979         u8         status[0x8];
3980         u8         reserved_0[0x18];
3981
3982         u8         syndrome[0x20];
3983
3984         u8         reserved_1[0x10];
3985         u8         rol_mode[0x8];
3986         u8         wol_mode[0x8];
3987
3988         u8         reserved_2[0x20];
3989 };
3990
3991 struct mlx5_ifc_query_wol_rol_in_bits {
3992         u8         opcode[0x10];
3993         u8         reserved_0[0x10];
3994
3995         u8         reserved_1[0x10];
3996         u8         op_mod[0x10];
3997
3998         u8         reserved_2[0x40];
3999 };
4000
4001 enum {
4002         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4003         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4004 };
4005
4006 struct mlx5_ifc_query_vport_state_out_bits {
4007         u8         status[0x8];
4008         u8         reserved_0[0x18];
4009
4010         u8         syndrome[0x20];
4011
4012         u8         reserved_1[0x20];
4013
4014         u8         reserved_2[0x18];
4015         u8         admin_state[0x4];
4016         u8         state[0x4];
4017 };
4018
4019 enum {
4020         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4021         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4022         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4023 };
4024
4025 struct mlx5_ifc_query_vport_state_in_bits {
4026         u8         opcode[0x10];
4027         u8         reserved_0[0x10];
4028
4029         u8         reserved_1[0x10];
4030         u8         op_mod[0x10];
4031
4032         u8         other_vport[0x1];
4033         u8         reserved_2[0xf];
4034         u8         vport_number[0x10];
4035
4036         u8         reserved_3[0x20];
4037 };
4038
4039 struct mlx5_ifc_query_vnic_env_out_bits {
4040         u8         status[0x8];
4041         u8         reserved_at_8[0x18];
4042
4043         u8         syndrome[0x20];
4044
4045         u8         reserved_at_40[0x40];
4046
4047         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4048 };
4049
4050 enum {
4051         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4052 };
4053
4054 struct mlx5_ifc_query_vnic_env_in_bits {
4055         u8         opcode[0x10];
4056         u8         reserved_at_10[0x10];
4057
4058         u8         reserved_at_20[0x10];
4059         u8         op_mod[0x10];
4060
4061         u8         other_vport[0x1];
4062         u8         reserved_at_41[0xf];
4063         u8         vport_number[0x10];
4064
4065         u8         reserved_at_60[0x20];
4066 };
4067
4068 struct mlx5_ifc_query_vport_counter_out_bits {
4069         u8         status[0x8];
4070         u8         reserved_0[0x18];
4071
4072         u8         syndrome[0x20];
4073
4074         u8         reserved_1[0x40];
4075
4076         struct mlx5_ifc_traffic_counter_bits received_errors;
4077
4078         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4079
4080         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4081
4082         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4083
4084         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4085
4086         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4087
4088         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4089
4090         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4091
4092         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4093
4094         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4095
4096         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4097
4098         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4099
4100         u8         reserved_2[0xa00];
4101 };
4102
4103 enum {
4104         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4105 };
4106
4107 struct mlx5_ifc_query_vport_counter_in_bits {
4108         u8         opcode[0x10];
4109         u8         reserved_0[0x10];
4110
4111         u8         reserved_1[0x10];
4112         u8         op_mod[0x10];
4113
4114         u8         other_vport[0x1];
4115         u8         reserved_2[0xb];
4116         u8         port_num[0x4];
4117         u8         vport_number[0x10];
4118
4119         u8         reserved_3[0x60];
4120
4121         u8         clear[0x1];
4122         u8         reserved_4[0x1f];
4123
4124         u8         reserved_5[0x20];
4125 };
4126
4127 struct mlx5_ifc_query_tis_out_bits {
4128         u8         status[0x8];
4129         u8         reserved_0[0x18];
4130
4131         u8         syndrome[0x20];
4132
4133         u8         reserved_1[0x40];
4134
4135         struct mlx5_ifc_tisc_bits tis_context;
4136 };
4137
4138 struct mlx5_ifc_query_tis_in_bits {
4139         u8         opcode[0x10];
4140         u8         reserved_0[0x10];
4141
4142         u8         reserved_1[0x10];
4143         u8         op_mod[0x10];
4144
4145         u8         reserved_2[0x8];
4146         u8         tisn[0x18];
4147
4148         u8         reserved_3[0x20];
4149 };
4150
4151 struct mlx5_ifc_query_tir_out_bits {
4152         u8         status[0x8];
4153         u8         reserved_0[0x18];
4154
4155         u8         syndrome[0x20];
4156
4157         u8         reserved_1[0xc0];
4158
4159         struct mlx5_ifc_tirc_bits tir_context;
4160 };
4161
4162 struct mlx5_ifc_query_tir_in_bits {
4163         u8         opcode[0x10];
4164         u8         reserved_0[0x10];
4165
4166         u8         reserved_1[0x10];
4167         u8         op_mod[0x10];
4168
4169         u8         reserved_2[0x8];
4170         u8         tirn[0x18];
4171
4172         u8         reserved_3[0x20];
4173 };
4174
4175 struct mlx5_ifc_query_srq_out_bits {
4176         u8         status[0x8];
4177         u8         reserved_0[0x18];
4178
4179         u8         syndrome[0x20];
4180
4181         u8         reserved_1[0x40];
4182
4183         struct mlx5_ifc_srqc_bits srq_context_entry;
4184
4185         u8         reserved_2[0x600];
4186
4187         u8         pas[0][0x40];
4188 };
4189
4190 struct mlx5_ifc_query_srq_in_bits {
4191         u8         opcode[0x10];
4192         u8         reserved_0[0x10];
4193
4194         u8         reserved_1[0x10];
4195         u8         op_mod[0x10];
4196
4197         u8         reserved_2[0x8];
4198         u8         srqn[0x18];
4199
4200         u8         reserved_3[0x20];
4201 };
4202
4203 struct mlx5_ifc_query_sq_out_bits {
4204         u8         status[0x8];
4205         u8         reserved_0[0x18];
4206
4207         u8         syndrome[0x20];
4208
4209         u8         reserved_1[0xc0];
4210
4211         struct mlx5_ifc_sqc_bits sq_context;
4212 };
4213
4214 struct mlx5_ifc_query_sq_in_bits {
4215         u8         opcode[0x10];
4216         u8         reserved_0[0x10];
4217
4218         u8         reserved_1[0x10];
4219         u8         op_mod[0x10];
4220
4221         u8         reserved_2[0x8];
4222         u8         sqn[0x18];
4223
4224         u8         reserved_3[0x20];
4225 };
4226
4227 struct mlx5_ifc_query_special_contexts_out_bits {
4228         u8         status[0x8];
4229         u8         reserved_0[0x18];
4230
4231         u8         syndrome[0x20];
4232
4233         u8         dump_fill_mkey[0x20];
4234
4235         u8         resd_lkey[0x20];
4236 };
4237
4238 struct mlx5_ifc_query_special_contexts_in_bits {
4239         u8         opcode[0x10];
4240         u8         reserved_0[0x10];
4241
4242         u8         reserved_1[0x10];
4243         u8         op_mod[0x10];
4244
4245         u8         reserved_2[0x40];
4246 };
4247
4248 struct mlx5_ifc_query_scheduling_element_out_bits {
4249         u8         status[0x8];
4250         u8         reserved_at_8[0x18];
4251
4252         u8         syndrome[0x20];
4253
4254         u8         reserved_at_40[0xc0];
4255
4256         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4257
4258         u8         reserved_at_300[0x100];
4259 };
4260
4261 enum {
4262         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4263 };
4264
4265 struct mlx5_ifc_query_scheduling_element_in_bits {
4266         u8         opcode[0x10];
4267         u8         reserved_at_10[0x10];
4268
4269         u8         reserved_at_20[0x10];
4270         u8         op_mod[0x10];
4271
4272         u8         scheduling_hierarchy[0x8];
4273         u8         reserved_at_48[0x18];
4274
4275         u8         scheduling_element_id[0x20];
4276
4277         u8         reserved_at_80[0x180];
4278 };
4279
4280 struct mlx5_ifc_query_rqt_out_bits {
4281         u8         status[0x8];
4282         u8         reserved_0[0x18];
4283
4284         u8         syndrome[0x20];
4285
4286         u8         reserved_1[0xc0];
4287
4288         struct mlx5_ifc_rqtc_bits rqt_context;
4289 };
4290
4291 struct mlx5_ifc_query_rqt_in_bits {
4292         u8         opcode[0x10];
4293         u8         reserved_0[0x10];
4294
4295         u8         reserved_1[0x10];
4296         u8         op_mod[0x10];
4297
4298         u8         reserved_2[0x8];
4299         u8         rqtn[0x18];
4300
4301         u8         reserved_3[0x20];
4302 };
4303
4304 struct mlx5_ifc_query_rq_out_bits {
4305         u8         status[0x8];
4306         u8         reserved_0[0x18];
4307
4308         u8         syndrome[0x20];
4309
4310         u8         reserved_1[0xc0];
4311
4312         struct mlx5_ifc_rqc_bits rq_context;
4313 };
4314
4315 struct mlx5_ifc_query_rq_in_bits {
4316         u8         opcode[0x10];
4317         u8         reserved_0[0x10];
4318
4319         u8         reserved_1[0x10];
4320         u8         op_mod[0x10];
4321
4322         u8         reserved_2[0x8];
4323         u8         rqn[0x18];
4324
4325         u8         reserved_3[0x20];
4326 };
4327
4328 struct mlx5_ifc_query_roce_address_out_bits {
4329         u8         status[0x8];
4330         u8         reserved_0[0x18];
4331
4332         u8         syndrome[0x20];
4333
4334         u8         reserved_1[0x40];
4335
4336         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4337 };
4338
4339 struct mlx5_ifc_query_roce_address_in_bits {
4340         u8         opcode[0x10];
4341         u8         reserved_0[0x10];
4342
4343         u8         reserved_1[0x10];
4344         u8         op_mod[0x10];
4345
4346         u8         roce_address_index[0x10];
4347         u8         reserved_2[0x10];
4348
4349         u8         reserved_3[0x20];
4350 };
4351
4352 struct mlx5_ifc_query_rmp_out_bits {
4353         u8         status[0x8];
4354         u8         reserved_0[0x18];
4355
4356         u8         syndrome[0x20];
4357
4358         u8         reserved_1[0xc0];
4359
4360         struct mlx5_ifc_rmpc_bits rmp_context;
4361 };
4362
4363 struct mlx5_ifc_query_rmp_in_bits {
4364         u8         opcode[0x10];
4365         u8         reserved_0[0x10];
4366
4367         u8         reserved_1[0x10];
4368         u8         op_mod[0x10];
4369
4370         u8         reserved_2[0x8];
4371         u8         rmpn[0x18];
4372
4373         u8         reserved_3[0x20];
4374 };
4375
4376 struct mlx5_ifc_query_rdb_out_bits {
4377         u8         status[0x8];
4378         u8         reserved_0[0x18];
4379
4380         u8         syndrome[0x20];
4381
4382         u8         reserved_1[0x20];
4383
4384         u8         reserved_2[0x18];
4385         u8         rdb_list_size[0x8];
4386
4387         struct mlx5_ifc_rdbc_bits rdb_context[0];
4388 };
4389
4390 struct mlx5_ifc_query_rdb_in_bits {
4391         u8         opcode[0x10];
4392         u8         reserved_0[0x10];
4393
4394         u8         reserved_1[0x10];
4395         u8         op_mod[0x10];
4396
4397         u8         reserved_2[0x8];
4398         u8         qpn[0x18];
4399
4400         u8         reserved_3[0x20];
4401 };
4402
4403 struct mlx5_ifc_query_qp_out_bits {
4404         u8         status[0x8];
4405         u8         reserved_0[0x18];
4406
4407         u8         syndrome[0x20];
4408
4409         u8         reserved_1[0x40];
4410
4411         u8         opt_param_mask[0x20];
4412
4413         u8         reserved_2[0x20];
4414
4415         struct mlx5_ifc_qpc_bits qpc;
4416
4417         u8         reserved_3[0x80];
4418
4419         u8         pas[0][0x40];
4420 };
4421
4422 struct mlx5_ifc_query_qp_in_bits {
4423         u8         opcode[0x10];
4424         u8         reserved_0[0x10];
4425
4426         u8         reserved_1[0x10];
4427         u8         op_mod[0x10];
4428
4429         u8         reserved_2[0x8];
4430         u8         qpn[0x18];
4431
4432         u8         reserved_3[0x20];
4433 };
4434
4435 struct mlx5_ifc_query_q_counter_out_bits {
4436         u8         status[0x8];
4437         u8         reserved_0[0x18];
4438
4439         u8         syndrome[0x20];
4440
4441         u8         reserved_1[0x40];
4442
4443         u8         rx_write_requests[0x20];
4444
4445         u8         reserved_2[0x20];
4446
4447         u8         rx_read_requests[0x20];
4448
4449         u8         reserved_3[0x20];
4450
4451         u8         rx_atomic_requests[0x20];
4452
4453         u8         reserved_4[0x20];
4454
4455         u8         rx_dct_connect[0x20];
4456
4457         u8         reserved_5[0x20];
4458
4459         u8         out_of_buffer[0x20];
4460
4461         u8         reserved_7[0x20];
4462
4463         u8         out_of_sequence[0x20];
4464
4465         u8         reserved_8[0x20];
4466
4467         u8         duplicate_request[0x20];
4468
4469         u8         reserved_9[0x20];
4470
4471         u8         rnr_nak_retry_err[0x20];
4472
4473         u8         reserved_10[0x20];
4474
4475         u8         packet_seq_err[0x20];
4476
4477         u8         reserved_11[0x20];
4478
4479         u8         implied_nak_seq_err[0x20];
4480
4481         u8         reserved_12[0x20];
4482
4483         u8         local_ack_timeout_err[0x20];
4484
4485         u8         reserved_13[0x20];
4486
4487         u8         resp_rnr_nak[0x20];
4488
4489         u8         reserved_14[0x20];
4490
4491         u8         req_rnr_retries_exceeded[0x20];
4492
4493         u8         reserved_15[0x460];
4494 };
4495
4496 struct mlx5_ifc_query_q_counter_in_bits {
4497         u8         opcode[0x10];
4498         u8         reserved_0[0x10];
4499
4500         u8         reserved_1[0x10];
4501         u8         op_mod[0x10];
4502
4503         u8         reserved_2[0x80];
4504
4505         u8         clear[0x1];
4506         u8         reserved_3[0x1f];
4507
4508         u8         reserved_4[0x18];
4509         u8         counter_set_id[0x8];
4510 };
4511
4512 struct mlx5_ifc_query_pages_out_bits {
4513         u8         status[0x8];
4514         u8         reserved_0[0x18];
4515
4516         u8         syndrome[0x20];
4517
4518         u8         reserved_1[0x10];
4519         u8         function_id[0x10];
4520
4521         u8         num_pages[0x20];
4522 };
4523
4524 enum {
4525         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4526         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4527         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4528 };
4529
4530 struct mlx5_ifc_query_pages_in_bits {
4531         u8         opcode[0x10];
4532         u8         reserved_0[0x10];
4533
4534         u8         reserved_1[0x10];
4535         u8         op_mod[0x10];
4536
4537         u8         reserved_2[0x10];
4538         u8         function_id[0x10];
4539
4540         u8         reserved_3[0x20];
4541 };
4542
4543 struct mlx5_ifc_query_nic_vport_context_out_bits {
4544         u8         status[0x8];
4545         u8         reserved_0[0x18];
4546
4547         u8         syndrome[0x20];
4548
4549         u8         reserved_1[0x40];
4550
4551         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4552 };
4553
4554 struct mlx5_ifc_query_nic_vport_context_in_bits {
4555         u8         opcode[0x10];
4556         u8         reserved_0[0x10];
4557
4558         u8         reserved_1[0x10];
4559         u8         op_mod[0x10];
4560
4561         u8         other_vport[0x1];
4562         u8         reserved_2[0xf];
4563         u8         vport_number[0x10];
4564
4565         u8         reserved_3[0x5];
4566         u8         allowed_list_type[0x3];
4567         u8         reserved_4[0x18];
4568 };
4569
4570 struct mlx5_ifc_query_mkey_out_bits {
4571         u8         status[0x8];
4572         u8         reserved_0[0x18];
4573
4574         u8         syndrome[0x20];
4575
4576         u8         reserved_1[0x40];
4577
4578         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4579
4580         u8         reserved_2[0x600];
4581
4582         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4583
4584         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4585 };
4586
4587 struct mlx5_ifc_query_mkey_in_bits {
4588         u8         opcode[0x10];
4589         u8         reserved_0[0x10];
4590
4591         u8         reserved_1[0x10];
4592         u8         op_mod[0x10];
4593
4594         u8         reserved_2[0x8];
4595         u8         mkey_index[0x18];
4596
4597         u8         pg_access[0x1];
4598         u8         reserved_3[0x1f];
4599 };
4600
4601 struct mlx5_ifc_query_mad_demux_out_bits {
4602         u8         status[0x8];
4603         u8         reserved_0[0x18];
4604
4605         u8         syndrome[0x20];
4606
4607         u8         reserved_1[0x40];
4608
4609         u8         mad_dumux_parameters_block[0x20];
4610 };
4611
4612 struct mlx5_ifc_query_mad_demux_in_bits {
4613         u8         opcode[0x10];
4614         u8         reserved_0[0x10];
4615
4616         u8         reserved_1[0x10];
4617         u8         op_mod[0x10];
4618
4619         u8         reserved_2[0x40];
4620 };
4621
4622 struct mlx5_ifc_query_l2_table_entry_out_bits {
4623         u8         status[0x8];
4624         u8         reserved_0[0x18];
4625
4626         u8         syndrome[0x20];
4627
4628         u8         reserved_1[0xa0];
4629
4630         u8         reserved_2[0x13];
4631         u8         vlan_valid[0x1];
4632         u8         vlan[0xc];
4633
4634         struct mlx5_ifc_mac_address_layout_bits mac_address;
4635
4636         u8         reserved_3[0xc0];
4637 };
4638
4639 struct mlx5_ifc_query_l2_table_entry_in_bits {
4640         u8         opcode[0x10];
4641         u8         reserved_0[0x10];
4642
4643         u8         reserved_1[0x10];
4644         u8         op_mod[0x10];
4645
4646         u8         reserved_2[0x60];
4647
4648         u8         reserved_3[0x8];
4649         u8         table_index[0x18];
4650
4651         u8         reserved_4[0x140];
4652 };
4653
4654 struct mlx5_ifc_query_issi_out_bits {
4655         u8         status[0x8];
4656         u8         reserved_0[0x18];
4657
4658         u8         syndrome[0x20];
4659
4660         u8         reserved_1[0x10];
4661         u8         current_issi[0x10];
4662
4663         u8         reserved_2[0xa0];
4664
4665         u8         supported_issi_reserved[76][0x8];
4666         u8         supported_issi_dw0[0x20];
4667 };
4668
4669 struct mlx5_ifc_query_issi_in_bits {
4670         u8         opcode[0x10];
4671         u8         reserved_0[0x10];
4672
4673         u8         reserved_1[0x10];
4674         u8         op_mod[0x10];
4675
4676         u8         reserved_2[0x40];
4677 };
4678
4679 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4680         u8         status[0x8];
4681         u8         reserved_0[0x18];
4682
4683         u8         syndrome[0x20];
4684
4685         u8         reserved_1[0x40];
4686
4687         struct mlx5_ifc_pkey_bits pkey[0];
4688 };
4689
4690 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4691         u8         opcode[0x10];
4692         u8         reserved_0[0x10];
4693
4694         u8         reserved_1[0x10];
4695         u8         op_mod[0x10];
4696
4697         u8         other_vport[0x1];
4698         u8         reserved_2[0xb];
4699         u8         port_num[0x4];
4700         u8         vport_number[0x10];
4701
4702         u8         reserved_3[0x10];
4703         u8         pkey_index[0x10];
4704 };
4705
4706 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4707         u8         status[0x8];
4708         u8         reserved_0[0x18];
4709
4710         u8         syndrome[0x20];
4711
4712         u8         reserved_1[0x20];
4713
4714         u8         gids_num[0x10];
4715         u8         reserved_2[0x10];
4716
4717         struct mlx5_ifc_array128_auto_bits gid[0];
4718 };
4719
4720 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4721         u8         opcode[0x10];
4722         u8         reserved_0[0x10];
4723
4724         u8         reserved_1[0x10];
4725         u8         op_mod[0x10];
4726
4727         u8         other_vport[0x1];
4728         u8         reserved_2[0xb];
4729         u8         port_num[0x4];
4730         u8         vport_number[0x10];
4731
4732         u8         reserved_3[0x10];
4733         u8         gid_index[0x10];
4734 };
4735
4736 struct mlx5_ifc_query_hca_vport_context_out_bits {
4737         u8         status[0x8];
4738         u8         reserved_0[0x18];
4739
4740         u8         syndrome[0x20];
4741
4742         u8         reserved_1[0x40];
4743
4744         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4745 };
4746
4747 struct mlx5_ifc_query_hca_vport_context_in_bits {
4748         u8         opcode[0x10];
4749         u8         reserved_0[0x10];
4750
4751         u8         reserved_1[0x10];
4752         u8         op_mod[0x10];
4753
4754         u8         other_vport[0x1];
4755         u8         reserved_2[0xb];
4756         u8         port_num[0x4];
4757         u8         vport_number[0x10];
4758
4759         u8         reserved_3[0x20];
4760 };
4761
4762 struct mlx5_ifc_query_hca_cap_out_bits {
4763         u8         status[0x8];
4764         u8         reserved_0[0x18];
4765
4766         u8         syndrome[0x20];
4767
4768         u8         reserved_1[0x40];
4769
4770         union mlx5_ifc_hca_cap_union_bits capability;
4771 };
4772
4773 struct mlx5_ifc_query_hca_cap_in_bits {
4774         u8         opcode[0x10];
4775         u8         reserved_0[0x10];
4776
4777         u8         reserved_1[0x10];
4778         u8         op_mod[0x10];
4779
4780         u8         reserved_2[0x40];
4781 };
4782
4783 struct mlx5_ifc_query_flow_table_out_bits {
4784         u8         status[0x8];
4785         u8         reserved_at_8[0x18];
4786
4787         u8         syndrome[0x20];
4788
4789         u8         reserved_at_40[0x80];
4790
4791         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4792 };
4793
4794 struct mlx5_ifc_query_flow_table_in_bits {
4795         u8         opcode[0x10];
4796         u8         reserved_0[0x10];
4797
4798         u8         reserved_1[0x10];
4799         u8         op_mod[0x10];
4800
4801         u8         other_vport[0x1];
4802         u8         reserved_2[0xf];
4803         u8         vport_number[0x10];
4804
4805         u8         reserved_3[0x20];
4806
4807         u8         table_type[0x8];
4808         u8         reserved_4[0x18];
4809
4810         u8         reserved_5[0x8];
4811         u8         table_id[0x18];
4812
4813         u8         reserved_6[0x140];
4814 };
4815
4816 struct mlx5_ifc_query_fte_out_bits {
4817         u8         status[0x8];
4818         u8         reserved_0[0x18];
4819
4820         u8         syndrome[0x20];
4821
4822         u8         reserved_1[0x1c0];
4823
4824         struct mlx5_ifc_flow_context_bits flow_context;
4825 };
4826
4827 struct mlx5_ifc_query_fte_in_bits {
4828         u8         opcode[0x10];
4829         u8         reserved_0[0x10];
4830
4831         u8         reserved_1[0x10];
4832         u8         op_mod[0x10];
4833
4834         u8         other_vport[0x1];
4835         u8         reserved_2[0xf];
4836         u8         vport_number[0x10];
4837
4838         u8         reserved_3[0x20];
4839
4840         u8         table_type[0x8];
4841         u8         reserved_4[0x18];
4842
4843         u8         reserved_5[0x8];
4844         u8         table_id[0x18];
4845
4846         u8         reserved_6[0x40];
4847
4848         u8         flow_index[0x20];
4849
4850         u8         reserved_7[0xe0];
4851 };
4852
4853 enum {
4854         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4855         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4856         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4857 };
4858
4859 struct mlx5_ifc_query_flow_group_out_bits {
4860         u8         status[0x8];
4861         u8         reserved_0[0x18];
4862
4863         u8         syndrome[0x20];
4864
4865         u8         reserved_1[0xa0];
4866
4867         u8         start_flow_index[0x20];
4868
4869         u8         reserved_2[0x20];
4870
4871         u8         end_flow_index[0x20];
4872
4873         u8         reserved_3[0xa0];
4874
4875         u8         reserved_4[0x18];
4876         u8         match_criteria_enable[0x8];
4877
4878         struct mlx5_ifc_fte_match_param_bits match_criteria;
4879
4880         u8         reserved_5[0xe00];
4881 };
4882
4883 struct mlx5_ifc_query_flow_group_in_bits {
4884         u8         opcode[0x10];
4885         u8         reserved_0[0x10];
4886
4887         u8         reserved_1[0x10];
4888         u8         op_mod[0x10];
4889
4890         u8         other_vport[0x1];
4891         u8         reserved_2[0xf];
4892         u8         vport_number[0x10];
4893
4894         u8         reserved_3[0x20];
4895
4896         u8         table_type[0x8];
4897         u8         reserved_4[0x18];
4898
4899         u8         reserved_5[0x8];
4900         u8         table_id[0x18];
4901
4902         u8         group_id[0x20];
4903
4904         u8         reserved_6[0x120];
4905 };
4906
4907 struct mlx5_ifc_query_flow_counter_out_bits {
4908         u8         status[0x8];
4909         u8         reserved_at_8[0x18];
4910
4911         u8         syndrome[0x20];
4912
4913         u8         reserved_at_40[0x40];
4914
4915         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4916 };
4917
4918 struct mlx5_ifc_query_flow_counter_in_bits {
4919         u8         opcode[0x10];
4920         u8         reserved_at_10[0x10];
4921
4922         u8         reserved_at_20[0x10];
4923         u8         op_mod[0x10];
4924
4925         u8         reserved_at_40[0x80];
4926
4927         u8         clear[0x1];
4928         u8         reserved_at_c1[0xf];
4929         u8         num_of_counters[0x10];
4930
4931         u8         reserved_at_e0[0x10];
4932         u8         flow_counter_id[0x10];
4933 };
4934
4935 struct mlx5_ifc_query_esw_vport_context_out_bits {
4936         u8         status[0x8];
4937         u8         reserved_0[0x18];
4938
4939         u8         syndrome[0x20];
4940
4941         u8         reserved_1[0x40];
4942
4943         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4944 };
4945
4946 struct mlx5_ifc_query_esw_vport_context_in_bits {
4947         u8         opcode[0x10];
4948         u8         reserved_0[0x10];
4949
4950         u8         reserved_1[0x10];
4951         u8         op_mod[0x10];
4952
4953         u8         other_vport[0x1];
4954         u8         reserved_2[0xf];
4955         u8         vport_number[0x10];
4956
4957         u8         reserved_3[0x20];
4958 };
4959
4960 struct mlx5_ifc_query_eq_out_bits {
4961         u8         status[0x8];
4962         u8         reserved_0[0x18];
4963
4964         u8         syndrome[0x20];
4965
4966         u8         reserved_1[0x40];
4967
4968         struct mlx5_ifc_eqc_bits eq_context_entry;
4969
4970         u8         reserved_2[0x40];
4971
4972         u8         event_bitmask[0x40];
4973
4974         u8         reserved_3[0x580];
4975
4976         u8         pas[0][0x40];
4977 };
4978
4979 struct mlx5_ifc_query_eq_in_bits {
4980         u8         opcode[0x10];
4981         u8         reserved_0[0x10];
4982
4983         u8         reserved_1[0x10];
4984         u8         op_mod[0x10];
4985
4986         u8         reserved_2[0x18];
4987         u8         eq_number[0x8];
4988
4989         u8         reserved_3[0x20];
4990 };
4991
4992 struct mlx5_ifc_query_dct_out_bits {
4993         u8         status[0x8];
4994         u8         reserved_0[0x18];
4995
4996         u8         syndrome[0x20];
4997
4998         u8         reserved_1[0x40];
4999
5000         struct mlx5_ifc_dctc_bits dct_context_entry;
5001
5002         u8         reserved_2[0x180];
5003 };
5004
5005 struct mlx5_ifc_query_dct_in_bits {
5006         u8         opcode[0x10];
5007         u8         reserved_0[0x10];
5008
5009         u8         reserved_1[0x10];
5010         u8         op_mod[0x10];
5011
5012         u8         reserved_2[0x8];
5013         u8         dctn[0x18];
5014
5015         u8         reserved_3[0x20];
5016 };
5017
5018 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5019         u8         status[0x8];
5020         u8         reserved_0[0x18];
5021
5022         u8         syndrome[0x20];
5023
5024         u8         enable[0x1];
5025         u8         reserved_1[0x1f];
5026
5027         u8         reserved_2[0x160];
5028
5029         struct mlx5_ifc_cmd_pas_bits pas;
5030 };
5031
5032 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5033         u8         opcode[0x10];
5034         u8         reserved_0[0x10];
5035
5036         u8         reserved_1[0x10];
5037         u8         op_mod[0x10];
5038
5039         u8         reserved_2[0x40];
5040 };
5041
5042 struct mlx5_ifc_query_cq_out_bits {
5043         u8         status[0x8];
5044         u8         reserved_0[0x18];
5045
5046         u8         syndrome[0x20];
5047
5048         u8         reserved_1[0x40];
5049
5050         struct mlx5_ifc_cqc_bits cq_context;
5051
5052         u8         reserved_2[0x600];
5053
5054         u8         pas[0][0x40];
5055 };
5056
5057 struct mlx5_ifc_query_cq_in_bits {
5058         u8         opcode[0x10];
5059         u8         reserved_0[0x10];
5060
5061         u8         reserved_1[0x10];
5062         u8         op_mod[0x10];
5063
5064         u8         reserved_2[0x8];
5065         u8         cqn[0x18];
5066
5067         u8         reserved_3[0x20];
5068 };
5069
5070 struct mlx5_ifc_query_cong_status_out_bits {
5071         u8         status[0x8];
5072         u8         reserved_0[0x18];
5073
5074         u8         syndrome[0x20];
5075
5076         u8         reserved_1[0x20];
5077
5078         u8         enable[0x1];
5079         u8         tag_enable[0x1];
5080         u8         reserved_2[0x1e];
5081 };
5082
5083 struct mlx5_ifc_query_cong_status_in_bits {
5084         u8         opcode[0x10];
5085         u8         reserved_0[0x10];
5086
5087         u8         reserved_1[0x10];
5088         u8         op_mod[0x10];
5089
5090         u8         reserved_2[0x18];
5091         u8         priority[0x4];
5092         u8         cong_protocol[0x4];
5093
5094         u8         reserved_3[0x20];
5095 };
5096
5097 struct mlx5_ifc_query_cong_statistics_out_bits {
5098         u8         status[0x8];
5099         u8         reserved_0[0x18];
5100
5101         u8         syndrome[0x20];
5102
5103         u8         reserved_1[0x40];
5104
5105         u8         rp_cur_flows[0x20];
5106
5107         u8         sum_flows[0x20];
5108
5109         u8         rp_cnp_ignored_high[0x20];
5110
5111         u8         rp_cnp_ignored_low[0x20];
5112
5113         u8         rp_cnp_handled_high[0x20];
5114
5115         u8         rp_cnp_handled_low[0x20];
5116
5117         u8         reserved_2[0x100];
5118
5119         u8         time_stamp_high[0x20];
5120
5121         u8         time_stamp_low[0x20];
5122
5123         u8         accumulators_period[0x20];
5124
5125         u8         np_ecn_marked_roce_packets_high[0x20];
5126
5127         u8         np_ecn_marked_roce_packets_low[0x20];
5128
5129         u8         np_cnp_sent_high[0x20];
5130
5131         u8         np_cnp_sent_low[0x20];
5132
5133         u8         reserved_3[0x560];
5134 };
5135
5136 struct mlx5_ifc_query_cong_statistics_in_bits {
5137         u8         opcode[0x10];
5138         u8         reserved_0[0x10];
5139
5140         u8         reserved_1[0x10];
5141         u8         op_mod[0x10];
5142
5143         u8         clear[0x1];
5144         u8         reserved_2[0x1f];
5145
5146         u8         reserved_3[0x20];
5147 };
5148
5149 struct mlx5_ifc_query_cong_params_out_bits {
5150         u8         status[0x8];
5151         u8         reserved_0[0x18];
5152
5153         u8         syndrome[0x20];
5154
5155         u8         reserved_1[0x40];
5156
5157         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5158 };
5159
5160 struct mlx5_ifc_query_cong_params_in_bits {
5161         u8         opcode[0x10];
5162         u8         reserved_0[0x10];
5163
5164         u8         reserved_1[0x10];
5165         u8         op_mod[0x10];
5166
5167         u8         reserved_2[0x1c];
5168         u8         cong_protocol[0x4];
5169
5170         u8         reserved_3[0x20];
5171 };
5172
5173 struct mlx5_ifc_query_burst_size_out_bits {
5174         u8         status[0x8];
5175         u8         reserved_0[0x18];
5176
5177         u8         syndrome[0x20];
5178
5179         u8         reserved_1[0x20];
5180
5181         u8         reserved_2[0x9];
5182         u8         device_burst_size[0x17];
5183 };
5184
5185 struct mlx5_ifc_query_burst_size_in_bits {
5186         u8         opcode[0x10];
5187         u8         reserved_0[0x10];
5188
5189         u8         reserved_1[0x10];
5190         u8         op_mod[0x10];
5191
5192         u8         reserved_2[0x40];
5193 };
5194
5195 struct mlx5_ifc_query_adapter_out_bits {
5196         u8         status[0x8];
5197         u8         reserved_0[0x18];
5198
5199         u8         syndrome[0x20];
5200
5201         u8         reserved_1[0x40];
5202
5203         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5204 };
5205
5206 struct mlx5_ifc_query_adapter_in_bits {
5207         u8         opcode[0x10];
5208         u8         reserved_0[0x10];
5209
5210         u8         reserved_1[0x10];
5211         u8         op_mod[0x10];
5212
5213         u8         reserved_2[0x40];
5214 };
5215
5216 struct mlx5_ifc_qp_2rst_out_bits {
5217         u8         status[0x8];
5218         u8         reserved_0[0x18];
5219
5220         u8         syndrome[0x20];
5221
5222         u8         reserved_1[0x40];
5223 };
5224
5225 struct mlx5_ifc_qp_2rst_in_bits {
5226         u8         opcode[0x10];
5227         u8         reserved_0[0x10];
5228
5229         u8         reserved_1[0x10];
5230         u8         op_mod[0x10];
5231
5232         u8         reserved_2[0x8];
5233         u8         qpn[0x18];
5234
5235         u8         reserved_3[0x20];
5236 };
5237
5238 struct mlx5_ifc_qp_2err_out_bits {
5239         u8         status[0x8];
5240         u8         reserved_0[0x18];
5241
5242         u8         syndrome[0x20];
5243
5244         u8         reserved_1[0x40];
5245 };
5246
5247 struct mlx5_ifc_qp_2err_in_bits {
5248         u8         opcode[0x10];
5249         u8         reserved_0[0x10];
5250
5251         u8         reserved_1[0x10];
5252         u8         op_mod[0x10];
5253
5254         u8         reserved_2[0x8];
5255         u8         qpn[0x18];
5256
5257         u8         reserved_3[0x20];
5258 };
5259
5260 struct mlx5_ifc_para_vport_element_bits {
5261         u8         reserved_at_0[0xc];
5262         u8         traffic_class[0x4];
5263         u8         qos_para_vport_number[0x10];
5264 };
5265
5266 struct mlx5_ifc_page_fault_resume_out_bits {
5267         u8         status[0x8];
5268         u8         reserved_0[0x18];
5269
5270         u8         syndrome[0x20];
5271
5272         u8         reserved_1[0x40];
5273 };
5274
5275 struct mlx5_ifc_page_fault_resume_in_bits {
5276         u8         opcode[0x10];
5277         u8         reserved_0[0x10];
5278
5279         u8         reserved_1[0x10];
5280         u8         op_mod[0x10];
5281
5282         u8         error[0x1];
5283         u8         reserved_2[0x4];
5284         u8         rdma[0x1];
5285         u8         read_write[0x1];
5286         u8         req_res[0x1];
5287         u8         qpn[0x18];
5288
5289         u8         reserved_3[0x20];
5290 };
5291
5292 struct mlx5_ifc_nop_out_bits {
5293         u8         status[0x8];
5294         u8         reserved_0[0x18];
5295
5296         u8         syndrome[0x20];
5297
5298         u8         reserved_1[0x40];
5299 };
5300
5301 struct mlx5_ifc_nop_in_bits {
5302         u8         opcode[0x10];
5303         u8         reserved_0[0x10];
5304
5305         u8         reserved_1[0x10];
5306         u8         op_mod[0x10];
5307
5308         u8         reserved_2[0x40];
5309 };
5310
5311 struct mlx5_ifc_modify_vport_state_out_bits {
5312         u8         status[0x8];
5313         u8         reserved_0[0x18];
5314
5315         u8         syndrome[0x20];
5316
5317         u8         reserved_1[0x40];
5318 };
5319
5320 enum {
5321         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5322         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5323         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5324 };
5325
5326 enum {
5327         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5328         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5329         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5330 };
5331
5332 struct mlx5_ifc_modify_vport_state_in_bits {
5333         u8         opcode[0x10];
5334         u8         reserved_0[0x10];
5335
5336         u8         reserved_1[0x10];
5337         u8         op_mod[0x10];
5338
5339         u8         other_vport[0x1];
5340         u8         reserved_2[0xf];
5341         u8         vport_number[0x10];
5342
5343         u8         reserved_3[0x18];
5344         u8         admin_state[0x4];
5345         u8         reserved_4[0x4];
5346 };
5347
5348 struct mlx5_ifc_modify_tis_out_bits {
5349         u8         status[0x8];
5350         u8         reserved_0[0x18];
5351
5352         u8         syndrome[0x20];
5353
5354         u8         reserved_1[0x40];
5355 };
5356
5357 struct mlx5_ifc_modify_tis_bitmask_bits {
5358         u8         reserved_at_0[0x20];
5359
5360         u8         reserved_at_20[0x1d];
5361         u8         lag_tx_port_affinity[0x1];
5362         u8         strict_lag_tx_port_affinity[0x1];
5363         u8         prio[0x1];
5364 };
5365
5366 struct mlx5_ifc_modify_tis_in_bits {
5367         u8         opcode[0x10];
5368         u8         reserved_0[0x10];
5369
5370         u8         reserved_1[0x10];
5371         u8         op_mod[0x10];
5372
5373         u8         reserved_2[0x8];
5374         u8         tisn[0x18];
5375
5376         u8         reserved_3[0x20];
5377
5378         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5379
5380         u8         reserved_4[0x40];
5381
5382         struct mlx5_ifc_tisc_bits ctx;
5383 };
5384
5385 struct mlx5_ifc_modify_tir_out_bits {
5386         u8         status[0x8];
5387         u8         reserved_0[0x18];
5388
5389         u8         syndrome[0x20];
5390
5391         u8         reserved_1[0x40];
5392 };
5393
5394 enum
5395 {
5396         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5397         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5398 };
5399
5400 struct mlx5_ifc_modify_tir_in_bits {
5401         u8         opcode[0x10];
5402         u8         reserved_0[0x10];
5403
5404         u8         reserved_1[0x10];
5405         u8         op_mod[0x10];
5406
5407         u8         reserved_2[0x8];
5408         u8         tirn[0x18];
5409
5410         u8         reserved_3[0x20];
5411
5412         u8         modify_bitmask[0x40];
5413
5414         u8         reserved_4[0x40];
5415
5416         struct mlx5_ifc_tirc_bits tir_context;
5417 };
5418
5419 struct mlx5_ifc_modify_sq_out_bits {
5420         u8         status[0x8];
5421         u8         reserved_0[0x18];
5422
5423         u8         syndrome[0x20];
5424
5425         u8         reserved_1[0x40];
5426 };
5427
5428 struct mlx5_ifc_modify_sq_in_bits {
5429         u8         opcode[0x10];
5430         u8         reserved_0[0x10];
5431
5432         u8         reserved_1[0x10];
5433         u8         op_mod[0x10];
5434
5435         u8         sq_state[0x4];
5436         u8         reserved_2[0x4];
5437         u8         sqn[0x18];
5438
5439         u8         reserved_3[0x20];
5440
5441         u8         modify_bitmask[0x40];
5442
5443         u8         reserved_4[0x40];
5444
5445         struct mlx5_ifc_sqc_bits ctx;
5446 };
5447
5448 struct mlx5_ifc_modify_scheduling_element_out_bits {
5449         u8         status[0x8];
5450         u8         reserved_at_8[0x18];
5451
5452         u8         syndrome[0x20];
5453
5454         u8         reserved_at_40[0x1c0];
5455 };
5456
5457 enum {
5458         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5459 };
5460
5461 enum {
5462         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5463         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5464 };
5465
5466 struct mlx5_ifc_modify_scheduling_element_in_bits {
5467         u8         opcode[0x10];
5468         u8         reserved_at_10[0x10];
5469
5470         u8         reserved_at_20[0x10];
5471         u8         op_mod[0x10];
5472
5473         u8         scheduling_hierarchy[0x8];
5474         u8         reserved_at_48[0x18];
5475
5476         u8         scheduling_element_id[0x20];
5477
5478         u8         reserved_at_80[0x20];
5479
5480         u8         modify_bitmask[0x20];
5481
5482         u8         reserved_at_c0[0x40];
5483
5484         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5485
5486         u8         reserved_at_300[0x100];
5487 };
5488
5489 struct mlx5_ifc_modify_rqt_out_bits {
5490         u8         status[0x8];
5491         u8         reserved_0[0x18];
5492
5493         u8         syndrome[0x20];
5494
5495         u8         reserved_1[0x40];
5496 };
5497
5498 struct mlx5_ifc_modify_rqt_in_bits {
5499         u8         opcode[0x10];
5500         u8         reserved_0[0x10];
5501
5502         u8         reserved_1[0x10];
5503         u8         op_mod[0x10];
5504
5505         u8         reserved_2[0x8];
5506         u8         rqtn[0x18];
5507
5508         u8         reserved_3[0x20];
5509
5510         u8         modify_bitmask[0x40];
5511
5512         u8         reserved_4[0x40];
5513
5514         struct mlx5_ifc_rqtc_bits ctx;
5515 };
5516
5517 struct mlx5_ifc_modify_rq_out_bits {
5518         u8         status[0x8];
5519         u8         reserved_0[0x18];
5520
5521         u8         syndrome[0x20];
5522
5523         u8         reserved_1[0x40];
5524 };
5525
5526 enum {
5527         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5528         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5529 };
5530
5531 struct mlx5_ifc_modify_rq_in_bits {
5532         u8         opcode[0x10];
5533         u8         reserved_0[0x10];
5534
5535         u8         reserved_1[0x10];
5536         u8         op_mod[0x10];
5537
5538         u8         rq_state[0x4];
5539         u8         reserved_2[0x4];
5540         u8         rqn[0x18];
5541
5542         u8         reserved_3[0x20];
5543
5544         u8         modify_bitmask[0x40];
5545
5546         u8         reserved_4[0x40];
5547
5548         struct mlx5_ifc_rqc_bits ctx;
5549 };
5550
5551 struct mlx5_ifc_modify_rmp_out_bits {
5552         u8         status[0x8];
5553         u8         reserved_0[0x18];
5554
5555         u8         syndrome[0x20];
5556
5557         u8         reserved_1[0x40];
5558 };
5559
5560 struct mlx5_ifc_rmp_bitmask_bits {
5561         u8         reserved[0x20];
5562
5563         u8         reserved1[0x1f];
5564         u8         lwm[0x1];
5565 };
5566
5567 struct mlx5_ifc_modify_rmp_in_bits {
5568         u8         opcode[0x10];
5569         u8         reserved_0[0x10];
5570
5571         u8         reserved_1[0x10];
5572         u8         op_mod[0x10];
5573
5574         u8         rmp_state[0x4];
5575         u8         reserved_2[0x4];
5576         u8         rmpn[0x18];
5577
5578         u8         reserved_3[0x20];
5579
5580         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5581
5582         u8         reserved_4[0x40];
5583
5584         struct mlx5_ifc_rmpc_bits ctx;
5585 };
5586
5587 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5588         u8         status[0x8];
5589         u8         reserved_0[0x18];
5590
5591         u8         syndrome[0x20];
5592
5593         u8         reserved_1[0x40];
5594 };
5595
5596 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5597         u8         reserved_0[0x14];
5598         u8         disable_uc_local_lb[0x1];
5599         u8         disable_mc_local_lb[0x1];
5600         u8         node_guid[0x1];
5601         u8         port_guid[0x1];
5602         u8         min_wqe_inline_mode[0x1];
5603         u8         mtu[0x1];
5604         u8         change_event[0x1];
5605         u8         promisc[0x1];
5606         u8         permanent_address[0x1];
5607         u8         addresses_list[0x1];
5608         u8         roce_en[0x1];
5609         u8         reserved_1[0x1];
5610 };
5611
5612 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_0[0x10];
5615
5616         u8         reserved_1[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         other_vport[0x1];
5620         u8         reserved_2[0xf];
5621         u8         vport_number[0x10];
5622
5623         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5624
5625         u8         reserved_3[0x780];
5626
5627         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5628 };
5629
5630 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5631         u8         status[0x8];
5632         u8         reserved_0[0x18];
5633
5634         u8         syndrome[0x20];
5635
5636         u8         reserved_1[0x40];
5637 };
5638
5639 struct mlx5_ifc_grh_bits {
5640         u8      ip_version[4];
5641         u8      traffic_class[8];
5642         u8      flow_label[20];
5643         u8      payload_length[16];
5644         u8      next_header[8];
5645         u8      hop_limit[8];
5646         u8      sgid[128];
5647         u8      dgid[128];
5648 };
5649
5650 struct mlx5_ifc_bth_bits {
5651         u8      opcode[8];
5652         u8      se[1];
5653         u8      migreq[1];
5654         u8      pad_count[2];
5655         u8      tver[4];
5656         u8      p_key[16];
5657         u8      reserved8[8];
5658         u8      dest_qp[24];
5659         u8      ack_req[1];
5660         u8      reserved7[7];
5661         u8      psn[24];
5662 };
5663
5664 struct mlx5_ifc_aeth_bits {
5665         u8      syndrome[8];
5666         u8      msn[24];
5667 };
5668
5669 struct mlx5_ifc_dceth_bits {
5670         u8      reserved0[8];
5671         u8      session_id[24];
5672         u8      reserved1[8];
5673         u8      dci_dct[24];
5674 };
5675
5676 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5677         u8         opcode[0x10];
5678         u8         reserved_0[0x10];
5679
5680         u8         reserved_1[0x10];
5681         u8         op_mod[0x10];
5682
5683         u8         other_vport[0x1];
5684         u8         reserved_2[0xb];
5685         u8         port_num[0x4];
5686         u8         vport_number[0x10];
5687
5688         u8         reserved_3[0x20];
5689
5690         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5691 };
5692
5693 struct mlx5_ifc_modify_flow_table_out_bits {
5694         u8         status[0x8];
5695         u8         reserved_at_8[0x18];
5696
5697         u8         syndrome[0x20];
5698
5699         u8         reserved_at_40[0x40];
5700 };
5701
5702 enum {
5703         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5704         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5705 };
5706
5707 struct mlx5_ifc_modify_flow_table_in_bits {
5708         u8         opcode[0x10];
5709         u8         reserved_at_10[0x10];
5710
5711         u8         reserved_at_20[0x10];
5712         u8         op_mod[0x10];
5713
5714         u8         other_vport[0x1];
5715         u8         reserved_at_41[0xf];
5716         u8         vport_number[0x10];
5717
5718         u8         reserved_at_60[0x10];
5719         u8         modify_field_select[0x10];
5720
5721         u8         table_type[0x8];
5722         u8         reserved_at_88[0x18];
5723
5724         u8         reserved_at_a0[0x8];
5725         u8         table_id[0x18];
5726
5727         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5728 };
5729
5730 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5731         u8         status[0x8];
5732         u8         reserved_0[0x18];
5733
5734         u8         syndrome[0x20];
5735
5736         u8         reserved_1[0x40];
5737 };
5738
5739 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5740         u8         reserved[0x1c];
5741         u8         vport_cvlan_insert[0x1];
5742         u8         vport_svlan_insert[0x1];
5743         u8         vport_cvlan_strip[0x1];
5744         u8         vport_svlan_strip[0x1];
5745 };
5746
5747 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5748         u8         opcode[0x10];
5749         u8         reserved_0[0x10];
5750
5751         u8         reserved_1[0x10];
5752         u8         op_mod[0x10];
5753
5754         u8         other_vport[0x1];
5755         u8         reserved_2[0xf];
5756         u8         vport_number[0x10];
5757
5758         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5759
5760         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5761 };
5762
5763 struct mlx5_ifc_modify_cq_out_bits {
5764         u8         status[0x8];
5765         u8         reserved_0[0x18];
5766
5767         u8         syndrome[0x20];
5768
5769         u8         reserved_1[0x40];
5770 };
5771
5772 enum {
5773         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5774         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5775 };
5776
5777 struct mlx5_ifc_modify_cq_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_0[0x10];
5780
5781         u8         reserved_1[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         reserved_2[0x8];
5785         u8         cqn[0x18];
5786
5787         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5788
5789         struct mlx5_ifc_cqc_bits cq_context;
5790
5791         u8         reserved_3[0x600];
5792
5793         u8         pas[0][0x40];
5794 };
5795
5796 struct mlx5_ifc_modify_cong_status_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_0[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_1[0x40];
5803 };
5804
5805 struct mlx5_ifc_modify_cong_status_in_bits {
5806         u8         opcode[0x10];
5807         u8         reserved_0[0x10];
5808
5809         u8         reserved_1[0x10];
5810         u8         op_mod[0x10];
5811
5812         u8         reserved_2[0x18];
5813         u8         priority[0x4];
5814         u8         cong_protocol[0x4];
5815
5816         u8         enable[0x1];
5817         u8         tag_enable[0x1];
5818         u8         reserved_3[0x1e];
5819 };
5820
5821 struct mlx5_ifc_modify_cong_params_out_bits {
5822         u8         status[0x8];
5823         u8         reserved_0[0x18];
5824
5825         u8         syndrome[0x20];
5826
5827         u8         reserved_1[0x40];
5828 };
5829
5830 struct mlx5_ifc_modify_cong_params_in_bits {
5831         u8         opcode[0x10];
5832         u8         reserved_0[0x10];
5833
5834         u8         reserved_1[0x10];
5835         u8         op_mod[0x10];
5836
5837         u8         reserved_2[0x1c];
5838         u8         cong_protocol[0x4];
5839
5840         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5841
5842         u8         reserved_3[0x80];
5843
5844         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5845 };
5846
5847 struct mlx5_ifc_manage_pages_out_bits {
5848         u8         status[0x8];
5849         u8         reserved_0[0x18];
5850
5851         u8         syndrome[0x20];
5852
5853         u8         output_num_entries[0x20];
5854
5855         u8         reserved_1[0x20];
5856
5857         u8         pas[0][0x40];
5858 };
5859
5860 enum {
5861         MLX5_PAGES_CANT_GIVE                            = 0x0,
5862         MLX5_PAGES_GIVE                                 = 0x1,
5863         MLX5_PAGES_TAKE                                 = 0x2,
5864 };
5865
5866 struct mlx5_ifc_manage_pages_in_bits {
5867         u8         opcode[0x10];
5868         u8         reserved_0[0x10];
5869
5870         u8         reserved_1[0x10];
5871         u8         op_mod[0x10];
5872
5873         u8         reserved_2[0x10];
5874         u8         function_id[0x10];
5875
5876         u8         input_num_entries[0x20];
5877
5878         u8         pas[0][0x40];
5879 };
5880
5881 struct mlx5_ifc_mad_ifc_out_bits {
5882         u8         status[0x8];
5883         u8         reserved_0[0x18];
5884
5885         u8         syndrome[0x20];
5886
5887         u8         reserved_1[0x40];
5888
5889         u8         response_mad_packet[256][0x8];
5890 };
5891
5892 struct mlx5_ifc_mad_ifc_in_bits {
5893         u8         opcode[0x10];
5894         u8         reserved_0[0x10];
5895
5896         u8         reserved_1[0x10];
5897         u8         op_mod[0x10];
5898
5899         u8         remote_lid[0x10];
5900         u8         reserved_2[0x8];
5901         u8         port[0x8];
5902
5903         u8         reserved_3[0x20];
5904
5905         u8         mad[256][0x8];
5906 };
5907
5908 struct mlx5_ifc_init_hca_out_bits {
5909         u8         status[0x8];
5910         u8         reserved_0[0x18];
5911
5912         u8         syndrome[0x20];
5913
5914         u8         reserved_1[0x40];
5915 };
5916
5917 enum {
5918         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5919         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5920 };
5921
5922 struct mlx5_ifc_init_hca_in_bits {
5923         u8         opcode[0x10];
5924         u8         reserved_0[0x10];
5925
5926         u8         reserved_1[0x10];
5927         u8         op_mod[0x10];
5928
5929         u8         reserved_2[0x40];
5930 };
5931
5932 struct mlx5_ifc_init2rtr_qp_out_bits {
5933         u8         status[0x8];
5934         u8         reserved_0[0x18];
5935
5936         u8         syndrome[0x20];
5937
5938         u8         reserved_1[0x40];
5939 };
5940
5941 struct mlx5_ifc_init2rtr_qp_in_bits {
5942         u8         opcode[0x10];
5943         u8         reserved_0[0x10];
5944
5945         u8         reserved_1[0x10];
5946         u8         op_mod[0x10];
5947
5948         u8         reserved_2[0x8];
5949         u8         qpn[0x18];
5950
5951         u8         reserved_3[0x20];
5952
5953         u8         opt_param_mask[0x20];
5954
5955         u8         reserved_4[0x20];
5956
5957         struct mlx5_ifc_qpc_bits qpc;
5958
5959         u8         reserved_5[0x80];
5960 };
5961
5962 struct mlx5_ifc_init2init_qp_out_bits {
5963         u8         status[0x8];
5964         u8         reserved_0[0x18];
5965
5966         u8         syndrome[0x20];
5967
5968         u8         reserved_1[0x40];
5969 };
5970
5971 struct mlx5_ifc_init2init_qp_in_bits {
5972         u8         opcode[0x10];
5973         u8         reserved_0[0x10];
5974
5975         u8         reserved_1[0x10];
5976         u8         op_mod[0x10];
5977
5978         u8         reserved_2[0x8];
5979         u8         qpn[0x18];
5980
5981         u8         reserved_3[0x20];
5982
5983         u8         opt_param_mask[0x20];
5984
5985         u8         reserved_4[0x20];
5986
5987         struct mlx5_ifc_qpc_bits qpc;
5988
5989         u8         reserved_5[0x80];
5990 };
5991
5992 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5993         u8         status[0x8];
5994         u8         reserved_0[0x18];
5995
5996         u8         syndrome[0x20];
5997
5998         u8         reserved_1[0x40];
5999
6000         u8         packet_headers_log[128][0x8];
6001
6002         u8         packet_syndrome[64][0x8];
6003 };
6004
6005 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6006         u8         opcode[0x10];
6007         u8         reserved_0[0x10];
6008
6009         u8         reserved_1[0x10];
6010         u8         op_mod[0x10];
6011
6012         u8         reserved_2[0x40];
6013 };
6014
6015 struct mlx5_ifc_encryption_key_obj_bits {
6016         u8         modify_field_select[0x40];
6017
6018         u8         reserved_at_40[0x14];
6019         u8         key_size[0x4];
6020         u8         reserved_at_58[0x4];
6021         u8         key_type[0x4];
6022
6023         u8         reserved_at_60[0x8];
6024         u8         pd[0x18];
6025
6026         u8         reserved_at_80[0x180];
6027
6028         u8         key[8][0x20];
6029
6030         u8         reserved_at_300[0x500];
6031 };
6032
6033 struct mlx5_ifc_gen_eqe_in_bits {
6034         u8         opcode[0x10];
6035         u8         reserved_0[0x10];
6036
6037         u8         reserved_1[0x10];
6038         u8         op_mod[0x10];
6039
6040         u8         reserved_2[0x18];
6041         u8         eq_number[0x8];
6042
6043         u8         reserved_3[0x20];
6044
6045         u8         eqe[64][0x8];
6046 };
6047
6048 struct mlx5_ifc_gen_eq_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_0[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_1[0x40];
6055 };
6056
6057 struct mlx5_ifc_enable_hca_out_bits {
6058         u8         status[0x8];
6059         u8         reserved_0[0x18];
6060
6061         u8         syndrome[0x20];
6062
6063         u8         reserved_1[0x20];
6064 };
6065
6066 struct mlx5_ifc_enable_hca_in_bits {
6067         u8         opcode[0x10];
6068         u8         reserved_0[0x10];
6069
6070         u8         reserved_1[0x10];
6071         u8         op_mod[0x10];
6072
6073         u8         reserved_2[0x10];
6074         u8         function_id[0x10];
6075
6076         u8         reserved_3[0x20];
6077 };
6078
6079 struct mlx5_ifc_drain_dct_out_bits {
6080         u8         status[0x8];
6081         u8         reserved_0[0x18];
6082
6083         u8         syndrome[0x20];
6084
6085         u8         reserved_1[0x40];
6086 };
6087
6088 struct mlx5_ifc_drain_dct_in_bits {
6089         u8         opcode[0x10];
6090         u8         reserved_0[0x10];
6091
6092         u8         reserved_1[0x10];
6093         u8         op_mod[0x10];
6094
6095         u8         reserved_2[0x8];
6096         u8         dctn[0x18];
6097
6098         u8         reserved_3[0x20];
6099 };
6100
6101 struct mlx5_ifc_disable_hca_out_bits {
6102         u8         status[0x8];
6103         u8         reserved_0[0x18];
6104
6105         u8         syndrome[0x20];
6106
6107         u8         reserved_1[0x20];
6108 };
6109
6110 struct mlx5_ifc_disable_hca_in_bits {
6111         u8         opcode[0x10];
6112         u8         reserved_0[0x10];
6113
6114         u8         reserved_1[0x10];
6115         u8         op_mod[0x10];
6116
6117         u8         reserved_2[0x10];
6118         u8         function_id[0x10];
6119
6120         u8         reserved_3[0x20];
6121 };
6122
6123 struct mlx5_ifc_detach_from_mcg_out_bits {
6124         u8         status[0x8];
6125         u8         reserved_0[0x18];
6126
6127         u8         syndrome[0x20];
6128
6129         u8         reserved_1[0x40];
6130 };
6131
6132 struct mlx5_ifc_detach_from_mcg_in_bits {
6133         u8         opcode[0x10];
6134         u8         reserved_0[0x10];
6135
6136         u8         reserved_1[0x10];
6137         u8         op_mod[0x10];
6138
6139         u8         reserved_2[0x8];
6140         u8         qpn[0x18];
6141
6142         u8         reserved_3[0x20];
6143
6144         u8         multicast_gid[16][0x8];
6145 };
6146
6147 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6148         u8         status[0x8];
6149         u8         reserved_0[0x18];
6150
6151         u8         syndrome[0x20];
6152
6153         u8         reserved_1[0x40];
6154 };
6155
6156 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6157         u8         opcode[0x10];
6158         u8         reserved_0[0x10];
6159
6160         u8         reserved_1[0x10];
6161         u8         op_mod[0x10];
6162
6163         u8         reserved_2[0x8];
6164         u8         xrc_srqn[0x18];
6165
6166         u8         reserved_3[0x20];
6167 };
6168
6169 struct mlx5_ifc_destroy_tis_out_bits {
6170         u8         status[0x8];
6171         u8         reserved_0[0x18];
6172
6173         u8         syndrome[0x20];
6174
6175         u8         reserved_1[0x40];
6176 };
6177
6178 struct mlx5_ifc_destroy_tis_in_bits {
6179         u8         opcode[0x10];
6180         u8         reserved_0[0x10];
6181
6182         u8         reserved_1[0x10];
6183         u8         op_mod[0x10];
6184
6185         u8         reserved_2[0x8];
6186         u8         tisn[0x18];
6187
6188         u8         reserved_3[0x20];
6189 };
6190
6191 struct mlx5_ifc_destroy_tir_out_bits {
6192         u8         status[0x8];
6193         u8         reserved_0[0x18];
6194
6195         u8         syndrome[0x20];
6196
6197         u8         reserved_1[0x40];
6198 };
6199
6200 struct mlx5_ifc_destroy_tir_in_bits {
6201         u8         opcode[0x10];
6202         u8         reserved_0[0x10];
6203
6204         u8         reserved_1[0x10];
6205         u8         op_mod[0x10];
6206
6207         u8         reserved_2[0x8];
6208         u8         tirn[0x18];
6209
6210         u8         reserved_3[0x20];
6211 };
6212
6213 struct mlx5_ifc_destroy_srq_out_bits {
6214         u8         status[0x8];
6215         u8         reserved_0[0x18];
6216
6217         u8         syndrome[0x20];
6218
6219         u8         reserved_1[0x40];
6220 };
6221
6222 struct mlx5_ifc_destroy_srq_in_bits {
6223         u8         opcode[0x10];
6224         u8         reserved_0[0x10];
6225
6226         u8         reserved_1[0x10];
6227         u8         op_mod[0x10];
6228
6229         u8         reserved_2[0x8];
6230         u8         srqn[0x18];
6231
6232         u8         reserved_3[0x20];
6233 };
6234
6235 struct mlx5_ifc_destroy_sq_out_bits {
6236         u8         status[0x8];
6237         u8         reserved_0[0x18];
6238
6239         u8         syndrome[0x20];
6240
6241         u8         reserved_1[0x40];
6242 };
6243
6244 struct mlx5_ifc_destroy_sq_in_bits {
6245         u8         opcode[0x10];
6246         u8         reserved_0[0x10];
6247
6248         u8         reserved_1[0x10];
6249         u8         op_mod[0x10];
6250
6251         u8         reserved_2[0x8];
6252         u8         sqn[0x18];
6253
6254         u8         reserved_3[0x20];
6255 };
6256
6257 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6258         u8         status[0x8];
6259         u8         reserved_at_8[0x18];
6260
6261         u8         syndrome[0x20];
6262
6263         u8         reserved_at_40[0x1c0];
6264 };
6265
6266 enum {
6267         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6268 };
6269
6270 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6271         u8         opcode[0x10];
6272         u8         reserved_at_10[0x10];
6273
6274         u8         reserved_at_20[0x10];
6275         u8         op_mod[0x10];
6276
6277         u8         scheduling_hierarchy[0x8];
6278         u8         reserved_at_48[0x18];
6279
6280         u8         scheduling_element_id[0x20];
6281
6282         u8         reserved_at_80[0x180];
6283 };
6284
6285 struct mlx5_ifc_destroy_rqt_out_bits {
6286         u8         status[0x8];
6287         u8         reserved_0[0x18];
6288
6289         u8         syndrome[0x20];
6290
6291         u8         reserved_1[0x40];
6292 };
6293
6294 struct mlx5_ifc_destroy_rqt_in_bits {
6295         u8         opcode[0x10];
6296         u8         reserved_0[0x10];
6297
6298         u8         reserved_1[0x10];
6299         u8         op_mod[0x10];
6300
6301         u8         reserved_2[0x8];
6302         u8         rqtn[0x18];
6303
6304         u8         reserved_3[0x20];
6305 };
6306
6307 struct mlx5_ifc_destroy_rq_out_bits {
6308         u8         status[0x8];
6309         u8         reserved_0[0x18];
6310
6311         u8         syndrome[0x20];
6312
6313         u8         reserved_1[0x40];
6314 };
6315
6316 struct mlx5_ifc_destroy_rq_in_bits {
6317         u8         opcode[0x10];
6318         u8         reserved_0[0x10];
6319
6320         u8         reserved_1[0x10];
6321         u8         op_mod[0x10];
6322
6323         u8         reserved_2[0x8];
6324         u8         rqn[0x18];
6325
6326         u8         reserved_3[0x20];
6327 };
6328
6329 struct mlx5_ifc_destroy_rmp_out_bits {
6330         u8         status[0x8];
6331         u8         reserved_0[0x18];
6332
6333         u8         syndrome[0x20];
6334
6335         u8         reserved_1[0x40];
6336 };
6337
6338 struct mlx5_ifc_destroy_rmp_in_bits {
6339         u8         opcode[0x10];
6340         u8         reserved_0[0x10];
6341
6342         u8         reserved_1[0x10];
6343         u8         op_mod[0x10];
6344
6345         u8         reserved_2[0x8];
6346         u8         rmpn[0x18];
6347
6348         u8         reserved_3[0x20];
6349 };
6350
6351 struct mlx5_ifc_destroy_qp_out_bits {
6352         u8         status[0x8];
6353         u8         reserved_0[0x18];
6354
6355         u8         syndrome[0x20];
6356
6357         u8         reserved_1[0x40];
6358 };
6359
6360 struct mlx5_ifc_destroy_qp_in_bits {
6361         u8         opcode[0x10];
6362         u8         reserved_0[0x10];
6363
6364         u8         reserved_1[0x10];
6365         u8         op_mod[0x10];
6366
6367         u8         reserved_2[0x8];
6368         u8         qpn[0x18];
6369
6370         u8         reserved_3[0x20];
6371 };
6372
6373 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6374         u8         status[0x8];
6375         u8         reserved_at_8[0x18];
6376
6377         u8         syndrome[0x20];
6378
6379         u8         reserved_at_40[0x1c0];
6380 };
6381
6382 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6383         u8         opcode[0x10];
6384         u8         reserved_at_10[0x10];
6385
6386         u8         reserved_at_20[0x10];
6387         u8         op_mod[0x10];
6388
6389         u8         reserved_at_40[0x20];
6390
6391         u8         reserved_at_60[0x10];
6392         u8         qos_para_vport_number[0x10];
6393
6394         u8         reserved_at_80[0x180];
6395 };
6396
6397 struct mlx5_ifc_destroy_psv_out_bits {
6398         u8         status[0x8];
6399         u8         reserved_0[0x18];
6400
6401         u8         syndrome[0x20];
6402
6403         u8         reserved_1[0x40];
6404 };
6405
6406 struct mlx5_ifc_destroy_psv_in_bits {
6407         u8         opcode[0x10];
6408         u8         reserved_0[0x10];
6409
6410         u8         reserved_1[0x10];
6411         u8         op_mod[0x10];
6412
6413         u8         reserved_2[0x8];
6414         u8         psvn[0x18];
6415
6416         u8         reserved_3[0x20];
6417 };
6418
6419 struct mlx5_ifc_destroy_mkey_out_bits {
6420         u8         status[0x8];
6421         u8         reserved_0[0x18];
6422
6423         u8         syndrome[0x20];
6424
6425         u8         reserved_1[0x40];
6426 };
6427
6428 struct mlx5_ifc_destroy_mkey_in_bits {
6429         u8         opcode[0x10];
6430         u8         reserved_0[0x10];
6431
6432         u8         reserved_1[0x10];
6433         u8         op_mod[0x10];
6434
6435         u8         reserved_2[0x8];
6436         u8         mkey_index[0x18];
6437
6438         u8         reserved_3[0x20];
6439 };
6440
6441 struct mlx5_ifc_destroy_flow_table_out_bits {
6442         u8         status[0x8];
6443         u8         reserved_0[0x18];
6444
6445         u8         syndrome[0x20];
6446
6447         u8         reserved_1[0x40];
6448 };
6449
6450 struct mlx5_ifc_destroy_flow_table_in_bits {
6451         u8         opcode[0x10];
6452         u8         reserved_0[0x10];
6453
6454         u8         reserved_1[0x10];
6455         u8         op_mod[0x10];
6456
6457         u8         other_vport[0x1];
6458         u8         reserved_2[0xf];
6459         u8         vport_number[0x10];
6460
6461         u8         reserved_3[0x20];
6462
6463         u8         table_type[0x8];
6464         u8         reserved_4[0x18];
6465
6466         u8         reserved_5[0x8];
6467         u8         table_id[0x18];
6468
6469         u8         reserved_6[0x140];
6470 };
6471
6472 struct mlx5_ifc_destroy_flow_group_out_bits {
6473         u8         status[0x8];
6474         u8         reserved_0[0x18];
6475
6476         u8         syndrome[0x20];
6477
6478         u8         reserved_1[0x40];
6479 };
6480
6481 struct mlx5_ifc_destroy_flow_group_in_bits {
6482         u8         opcode[0x10];
6483         u8         reserved_0[0x10];
6484
6485         u8         reserved_1[0x10];
6486         u8         op_mod[0x10];
6487
6488         u8         other_vport[0x1];
6489         u8         reserved_2[0xf];
6490         u8         vport_number[0x10];
6491
6492         u8         reserved_3[0x20];
6493
6494         u8         table_type[0x8];
6495         u8         reserved_4[0x18];
6496
6497         u8         reserved_5[0x8];
6498         u8         table_id[0x18];
6499
6500         u8         group_id[0x20];
6501
6502         u8         reserved_6[0x120];
6503 };
6504
6505 struct mlx5_ifc_destroy_encryption_key_out_bits {
6506         u8         status[0x8];
6507         u8         reserved_at_8[0x18];
6508
6509         u8         syndrome[0x20];
6510
6511         u8         reserved_at_40[0x40];
6512 };
6513
6514 struct mlx5_ifc_destroy_encryption_key_in_bits {
6515         u8         opcode[0x10];
6516         u8         reserved_at_10[0x10];
6517
6518         u8         reserved_at_20[0x10];
6519         u8         obj_type[0x10];
6520
6521         u8         obj_id[0x20];
6522
6523         u8         reserved_at_60[0x20];
6524 };
6525
6526 struct mlx5_ifc_destroy_eq_out_bits {
6527         u8         status[0x8];
6528         u8         reserved_0[0x18];
6529
6530         u8         syndrome[0x20];
6531
6532         u8         reserved_1[0x40];
6533 };
6534
6535 struct mlx5_ifc_destroy_eq_in_bits {
6536         u8         opcode[0x10];
6537         u8         reserved_0[0x10];
6538
6539         u8         reserved_1[0x10];
6540         u8         op_mod[0x10];
6541
6542         u8         reserved_2[0x18];
6543         u8         eq_number[0x8];
6544
6545         u8         reserved_3[0x20];
6546 };
6547
6548 struct mlx5_ifc_destroy_dct_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_0[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_1[0x40];
6555 };
6556
6557 struct mlx5_ifc_destroy_dct_in_bits {
6558         u8         opcode[0x10];
6559         u8         reserved_0[0x10];
6560
6561         u8         reserved_1[0x10];
6562         u8         op_mod[0x10];
6563
6564         u8         reserved_2[0x8];
6565         u8         dctn[0x18];
6566
6567         u8         reserved_3[0x20];
6568 };
6569
6570 struct mlx5_ifc_destroy_cq_out_bits {
6571         u8         status[0x8];
6572         u8         reserved_0[0x18];
6573
6574         u8         syndrome[0x20];
6575
6576         u8         reserved_1[0x40];
6577 };
6578
6579 struct mlx5_ifc_destroy_cq_in_bits {
6580         u8         opcode[0x10];
6581         u8         reserved_0[0x10];
6582
6583         u8         reserved_1[0x10];
6584         u8         op_mod[0x10];
6585
6586         u8         reserved_2[0x8];
6587         u8         cqn[0x18];
6588
6589         u8         reserved_3[0x20];
6590 };
6591
6592 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6593         u8         status[0x8];
6594         u8         reserved_0[0x18];
6595
6596         u8         syndrome[0x20];
6597
6598         u8         reserved_1[0x40];
6599 };
6600
6601 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6602         u8         opcode[0x10];
6603         u8         reserved_0[0x10];
6604
6605         u8         reserved_1[0x10];
6606         u8         op_mod[0x10];
6607
6608         u8         reserved_2[0x20];
6609
6610         u8         reserved_3[0x10];
6611         u8         vxlan_udp_port[0x10];
6612 };
6613
6614 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6615         u8         status[0x8];
6616         u8         reserved_0[0x18];
6617
6618         u8         syndrome[0x20];
6619
6620         u8         reserved_1[0x40];
6621 };
6622
6623 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6624         u8         opcode[0x10];
6625         u8         reserved_0[0x10];
6626
6627         u8         reserved_1[0x10];
6628         u8         op_mod[0x10];
6629
6630         u8         reserved_2[0x60];
6631
6632         u8         reserved_3[0x8];
6633         u8         table_index[0x18];
6634
6635         u8         reserved_4[0x140];
6636 };
6637
6638 struct mlx5_ifc_delete_fte_out_bits {
6639         u8         status[0x8];
6640         u8         reserved_0[0x18];
6641
6642         u8         syndrome[0x20];
6643
6644         u8         reserved_1[0x40];
6645 };
6646
6647 struct mlx5_ifc_delete_fte_in_bits {
6648         u8         opcode[0x10];
6649         u8         reserved_0[0x10];
6650
6651         u8         reserved_1[0x10];
6652         u8         op_mod[0x10];
6653
6654         u8         other_vport[0x1];
6655         u8         reserved_2[0xf];
6656         u8         vport_number[0x10];
6657
6658         u8         reserved_3[0x20];
6659
6660         u8         table_type[0x8];
6661         u8         reserved_4[0x18];
6662
6663         u8         reserved_5[0x8];
6664         u8         table_id[0x18];
6665
6666         u8         reserved_6[0x40];
6667
6668         u8         flow_index[0x20];
6669
6670         u8         reserved_7[0xe0];
6671 };
6672
6673 struct mlx5_ifc_dealloc_xrcd_out_bits {
6674         u8         status[0x8];
6675         u8         reserved_0[0x18];
6676
6677         u8         syndrome[0x20];
6678
6679         u8         reserved_1[0x40];
6680 };
6681
6682 struct mlx5_ifc_dealloc_xrcd_in_bits {
6683         u8         opcode[0x10];
6684         u8         reserved_0[0x10];
6685
6686         u8         reserved_1[0x10];
6687         u8         op_mod[0x10];
6688
6689         u8         reserved_2[0x8];
6690         u8         xrcd[0x18];
6691
6692         u8         reserved_3[0x20];
6693 };
6694
6695 struct mlx5_ifc_dealloc_uar_out_bits {
6696         u8         status[0x8];
6697         u8         reserved_0[0x18];
6698
6699         u8         syndrome[0x20];
6700
6701         u8         reserved_1[0x40];
6702 };
6703
6704 struct mlx5_ifc_dealloc_uar_in_bits {
6705         u8         opcode[0x10];
6706         u8         reserved_0[0x10];
6707
6708         u8         reserved_1[0x10];
6709         u8         op_mod[0x10];
6710
6711         u8         reserved_2[0x8];
6712         u8         uar[0x18];
6713
6714         u8         reserved_3[0x20];
6715 };
6716
6717 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6718         u8         status[0x8];
6719         u8         reserved_0[0x18];
6720
6721         u8         syndrome[0x20];
6722
6723         u8         reserved_1[0x40];
6724 };
6725
6726 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6727         u8         opcode[0x10];
6728         u8         reserved_0[0x10];
6729
6730         u8         reserved_1[0x10];
6731         u8         op_mod[0x10];
6732
6733         u8         reserved_2[0x8];
6734         u8         transport_domain[0x18];
6735
6736         u8         reserved_3[0x20];
6737 };
6738
6739 struct mlx5_ifc_dealloc_q_counter_out_bits {
6740         u8         status[0x8];
6741         u8         reserved_0[0x18];
6742
6743         u8         syndrome[0x20];
6744
6745         u8         reserved_1[0x40];
6746 };
6747
6748 struct mlx5_ifc_counter_id_bits {
6749         u8         reserved[0x10];
6750         u8         counter_id[0x10];
6751 };
6752
6753 struct mlx5_ifc_diagnostic_params_context_bits {
6754         u8         num_of_counters[0x10];
6755         u8         reserved_2[0x8];
6756         u8         log_num_of_samples[0x8];
6757
6758         u8         single[0x1];
6759         u8         repetitive[0x1];
6760         u8         sync[0x1];
6761         u8         clear[0x1];
6762         u8         on_demand[0x1];
6763         u8         enable[0x1];
6764         u8         reserved_3[0x12];
6765         u8         log_sample_period[0x8];
6766
6767         u8         reserved_4[0x80];
6768
6769         struct mlx5_ifc_counter_id_bits counter_id[0];
6770 };
6771
6772 struct mlx5_ifc_set_diagnostic_params_in_bits {
6773         u8         opcode[0x10];
6774         u8         reserved_0[0x10];
6775
6776         u8         reserved_1[0x10];
6777         u8         op_mod[0x10];
6778
6779         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6780 };
6781
6782 struct mlx5_ifc_set_diagnostic_params_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_0[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_1[0x40];
6789 };
6790
6791 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6792         u8         opcode[0x10];
6793         u8         reserved_0[0x10];
6794
6795         u8         reserved_1[0x10];
6796         u8         op_mod[0x10];
6797
6798         u8         num_of_samples[0x10];
6799         u8         sample_index[0x10];
6800
6801         u8         reserved_2[0x20];
6802 };
6803
6804 struct mlx5_ifc_diagnostic_counter_bits {
6805         u8         counter_id[0x10];
6806         u8         sample_id[0x10];
6807
6808         u8         time_stamp_31_0[0x20];
6809
6810         u8         counter_value_h[0x20];
6811
6812         u8         counter_value_l[0x20];
6813 };
6814
6815 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6816         u8         status[0x8];
6817         u8         reserved_0[0x18];
6818
6819         u8         syndrome[0x20];
6820
6821         u8         reserved_1[0x40];
6822
6823         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6824 };
6825
6826 struct mlx5_ifc_dealloc_q_counter_in_bits {
6827         u8         opcode[0x10];
6828         u8         reserved_0[0x10];
6829
6830         u8         reserved_1[0x10];
6831         u8         op_mod[0x10];
6832
6833         u8         reserved_2[0x18];
6834         u8         counter_set_id[0x8];
6835
6836         u8         reserved_3[0x20];
6837 };
6838
6839 struct mlx5_ifc_dealloc_pd_out_bits {
6840         u8         status[0x8];
6841         u8         reserved_0[0x18];
6842
6843         u8         syndrome[0x20];
6844
6845         u8         reserved_1[0x40];
6846 };
6847
6848 struct mlx5_ifc_dealloc_pd_in_bits {
6849         u8         opcode[0x10];
6850         u8         reserved_0[0x10];
6851
6852         u8         reserved_1[0x10];
6853         u8         op_mod[0x10];
6854
6855         u8         reserved_2[0x8];
6856         u8         pd[0x18];
6857
6858         u8         reserved_3[0x20];
6859 };
6860
6861 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6862         u8         status[0x8];
6863         u8         reserved_0[0x18];
6864
6865         u8         syndrome[0x20];
6866
6867         u8         reserved_1[0x40];
6868 };
6869
6870 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6871         u8         opcode[0x10];
6872         u8         reserved_0[0x10];
6873
6874         u8         reserved_1[0x10];
6875         u8         op_mod[0x10];
6876
6877         u8         reserved_2[0x10];
6878         u8         flow_counter_id[0x10];
6879
6880         u8         reserved_3[0x20];
6881 };
6882
6883 struct mlx5_ifc_deactivate_tracer_out_bits {
6884         u8         status[0x8];
6885         u8         reserved_0[0x18];
6886
6887         u8         syndrome[0x20];
6888
6889         u8         reserved_1[0x40];
6890 };
6891
6892 struct mlx5_ifc_deactivate_tracer_in_bits {
6893         u8         opcode[0x10];
6894         u8         reserved_0[0x10];
6895
6896         u8         reserved_1[0x10];
6897         u8         op_mod[0x10];
6898
6899         u8         mkey[0x20];
6900
6901         u8         reserved_2[0x20];
6902 };
6903
6904 struct mlx5_ifc_create_xrc_srq_out_bits {
6905         u8         status[0x8];
6906         u8         reserved_0[0x18];
6907
6908         u8         syndrome[0x20];
6909
6910         u8         reserved_1[0x8];
6911         u8         xrc_srqn[0x18];
6912
6913         u8         reserved_2[0x20];
6914 };
6915
6916 struct mlx5_ifc_create_xrc_srq_in_bits {
6917         u8         opcode[0x10];
6918         u8         reserved_0[0x10];
6919
6920         u8         reserved_1[0x10];
6921         u8         op_mod[0x10];
6922
6923         u8         reserved_2[0x40];
6924
6925         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6926
6927         u8         reserved_3[0x600];
6928
6929         u8         pas[0][0x40];
6930 };
6931
6932 struct mlx5_ifc_create_tis_out_bits {
6933         u8         status[0x8];
6934         u8         reserved_0[0x18];
6935
6936         u8         syndrome[0x20];
6937
6938         u8         reserved_1[0x8];
6939         u8         tisn[0x18];
6940
6941         u8         reserved_2[0x20];
6942 };
6943
6944 struct mlx5_ifc_create_tis_in_bits {
6945         u8         opcode[0x10];
6946         u8         reserved_0[0x10];
6947
6948         u8         reserved_1[0x10];
6949         u8         op_mod[0x10];
6950
6951         u8         reserved_2[0xc0];
6952
6953         struct mlx5_ifc_tisc_bits ctx;
6954 };
6955
6956 struct mlx5_ifc_create_tir_out_bits {
6957         u8         status[0x8];
6958         u8         reserved_0[0x18];
6959
6960         u8         syndrome[0x20];
6961
6962         u8         reserved_1[0x8];
6963         u8         tirn[0x18];
6964
6965         u8         reserved_2[0x20];
6966 };
6967
6968 struct mlx5_ifc_create_tir_in_bits {
6969         u8         opcode[0x10];
6970         u8         reserved_0[0x10];
6971
6972         u8         reserved_1[0x10];
6973         u8         op_mod[0x10];
6974
6975         u8         reserved_2[0xc0];
6976
6977         struct mlx5_ifc_tirc_bits tir_context;
6978 };
6979
6980 struct mlx5_ifc_create_srq_out_bits {
6981         u8         status[0x8];
6982         u8         reserved_0[0x18];
6983
6984         u8         syndrome[0x20];
6985
6986         u8         reserved_1[0x8];
6987         u8         srqn[0x18];
6988
6989         u8         reserved_2[0x20];
6990 };
6991
6992 struct mlx5_ifc_create_srq_in_bits {
6993         u8         opcode[0x10];
6994         u8         reserved_0[0x10];
6995
6996         u8         reserved_1[0x10];
6997         u8         op_mod[0x10];
6998
6999         u8         reserved_2[0x40];
7000
7001         struct mlx5_ifc_srqc_bits srq_context_entry;
7002
7003         u8         reserved_3[0x600];
7004
7005         u8         pas[0][0x40];
7006 };
7007
7008 struct mlx5_ifc_create_sq_out_bits {
7009         u8         status[0x8];
7010         u8         reserved_0[0x18];
7011
7012         u8         syndrome[0x20];
7013
7014         u8         reserved_1[0x8];
7015         u8         sqn[0x18];
7016
7017         u8         reserved_2[0x20];
7018 };
7019
7020 struct mlx5_ifc_create_sq_in_bits {
7021         u8         opcode[0x10];
7022         u8         reserved_0[0x10];
7023
7024         u8         reserved_1[0x10];
7025         u8         op_mod[0x10];
7026
7027         u8         reserved_2[0xc0];
7028
7029         struct mlx5_ifc_sqc_bits ctx;
7030 };
7031
7032 struct mlx5_ifc_create_scheduling_element_out_bits {
7033         u8         status[0x8];
7034         u8         reserved_at_8[0x18];
7035
7036         u8         syndrome[0x20];
7037
7038         u8         reserved_at_40[0x40];
7039
7040         u8         scheduling_element_id[0x20];
7041
7042         u8         reserved_at_a0[0x160];
7043 };
7044
7045 enum {
7046         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7047 };
7048
7049 struct mlx5_ifc_create_scheduling_element_in_bits {
7050         u8         opcode[0x10];
7051         u8         reserved_at_10[0x10];
7052
7053         u8         reserved_at_20[0x10];
7054         u8         op_mod[0x10];
7055
7056         u8         scheduling_hierarchy[0x8];
7057         u8         reserved_at_48[0x18];
7058
7059         u8         reserved_at_60[0xa0];
7060
7061         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7062
7063         u8         reserved_at_300[0x100];
7064 };
7065
7066 struct mlx5_ifc_create_rqt_out_bits {
7067         u8         status[0x8];
7068         u8         reserved_0[0x18];
7069
7070         u8         syndrome[0x20];
7071
7072         u8         reserved_1[0x8];
7073         u8         rqtn[0x18];
7074
7075         u8         reserved_2[0x20];
7076 };
7077
7078 struct mlx5_ifc_create_rqt_in_bits {
7079         u8         opcode[0x10];
7080         u8         reserved_0[0x10];
7081
7082         u8         reserved_1[0x10];
7083         u8         op_mod[0x10];
7084
7085         u8         reserved_2[0xc0];
7086
7087         struct mlx5_ifc_rqtc_bits rqt_context;
7088 };
7089
7090 struct mlx5_ifc_create_rq_out_bits {
7091         u8         status[0x8];
7092         u8         reserved_0[0x18];
7093
7094         u8         syndrome[0x20];
7095
7096         u8         reserved_1[0x8];
7097         u8         rqn[0x18];
7098
7099         u8         reserved_2[0x20];
7100 };
7101
7102 struct mlx5_ifc_create_rq_in_bits {
7103         u8         opcode[0x10];
7104         u8         reserved_0[0x10];
7105
7106         u8         reserved_1[0x10];
7107         u8         op_mod[0x10];
7108
7109         u8         reserved_2[0xc0];
7110
7111         struct mlx5_ifc_rqc_bits ctx;
7112 };
7113
7114 struct mlx5_ifc_create_rmp_out_bits {
7115         u8         status[0x8];
7116         u8         reserved_0[0x18];
7117
7118         u8         syndrome[0x20];
7119
7120         u8         reserved_1[0x8];
7121         u8         rmpn[0x18];
7122
7123         u8         reserved_2[0x20];
7124 };
7125
7126 struct mlx5_ifc_create_rmp_in_bits {
7127         u8         opcode[0x10];
7128         u8         reserved_0[0x10];
7129
7130         u8         reserved_1[0x10];
7131         u8         op_mod[0x10];
7132
7133         u8         reserved_2[0xc0];
7134
7135         struct mlx5_ifc_rmpc_bits ctx;
7136 };
7137
7138 struct mlx5_ifc_create_qp_out_bits {
7139         u8         status[0x8];
7140         u8         reserved_0[0x18];
7141
7142         u8         syndrome[0x20];
7143
7144         u8         reserved_1[0x8];
7145         u8         qpn[0x18];
7146
7147         u8         reserved_2[0x20];
7148 };
7149
7150 struct mlx5_ifc_create_qp_in_bits {
7151         u8         opcode[0x10];
7152         u8         reserved_0[0x10];
7153
7154         u8         reserved_1[0x10];
7155         u8         op_mod[0x10];
7156
7157         u8         reserved_2[0x8];
7158         u8         input_qpn[0x18];
7159
7160         u8         reserved_3[0x20];
7161
7162         u8         opt_param_mask[0x20];
7163
7164         u8         reserved_4[0x20];
7165
7166         struct mlx5_ifc_qpc_bits qpc;
7167
7168         u8         reserved_5[0x80];
7169
7170         u8         pas[0][0x40];
7171 };
7172
7173 struct mlx5_ifc_create_qos_para_vport_out_bits {
7174         u8         status[0x8];
7175         u8         reserved_at_8[0x18];
7176
7177         u8         syndrome[0x20];
7178
7179         u8         reserved_at_40[0x20];
7180
7181         u8         reserved_at_60[0x10];
7182         u8         qos_para_vport_number[0x10];
7183
7184         u8         reserved_at_80[0x180];
7185 };
7186
7187 struct mlx5_ifc_create_qos_para_vport_in_bits {
7188         u8         opcode[0x10];
7189         u8         reserved_at_10[0x10];
7190
7191         u8         reserved_at_20[0x10];
7192         u8         op_mod[0x10];
7193
7194         u8         reserved_at_40[0x1c0];
7195 };
7196
7197 struct mlx5_ifc_create_psv_out_bits {
7198         u8         status[0x8];
7199         u8         reserved_0[0x18];
7200
7201         u8         syndrome[0x20];
7202
7203         u8         reserved_1[0x40];
7204
7205         u8         reserved_2[0x8];
7206         u8         psv0_index[0x18];
7207
7208         u8         reserved_3[0x8];
7209         u8         psv1_index[0x18];
7210
7211         u8         reserved_4[0x8];
7212         u8         psv2_index[0x18];
7213
7214         u8         reserved_5[0x8];
7215         u8         psv3_index[0x18];
7216 };
7217
7218 struct mlx5_ifc_create_psv_in_bits {
7219         u8         opcode[0x10];
7220         u8         reserved_0[0x10];
7221
7222         u8         reserved_1[0x10];
7223         u8         op_mod[0x10];
7224
7225         u8         num_psv[0x4];
7226         u8         reserved_2[0x4];
7227         u8         pd[0x18];
7228
7229         u8         reserved_3[0x20];
7230 };
7231
7232 struct mlx5_ifc_create_mkey_out_bits {
7233         u8         status[0x8];
7234         u8         reserved_0[0x18];
7235
7236         u8         syndrome[0x20];
7237
7238         u8         reserved_1[0x8];
7239         u8         mkey_index[0x18];
7240
7241         u8         reserved_2[0x20];
7242 };
7243
7244 struct mlx5_ifc_create_mkey_in_bits {
7245         u8         opcode[0x10];
7246         u8         reserved_0[0x10];
7247
7248         u8         reserved_1[0x10];
7249         u8         op_mod[0x10];
7250
7251         u8         reserved_2[0x20];
7252
7253         u8         pg_access[0x1];
7254         u8         reserved_3[0x1f];
7255
7256         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7257
7258         u8         reserved_4[0x80];
7259
7260         u8         translations_octword_actual_size[0x20];
7261
7262         u8         reserved_5[0x560];
7263
7264         u8         klm_pas_mtt[0][0x20];
7265 };
7266
7267 struct mlx5_ifc_create_flow_table_out_bits {
7268         u8         status[0x8];
7269         u8         reserved_0[0x18];
7270
7271         u8         syndrome[0x20];
7272
7273         u8         reserved_1[0x8];
7274         u8         table_id[0x18];
7275
7276         u8         reserved_2[0x20];
7277 };
7278
7279 struct mlx5_ifc_create_flow_table_in_bits {
7280         u8         opcode[0x10];
7281         u8         reserved_at_10[0x10];
7282
7283         u8         reserved_at_20[0x10];
7284         u8         op_mod[0x10];
7285
7286         u8         other_vport[0x1];
7287         u8         reserved_at_41[0xf];
7288         u8         vport_number[0x10];
7289
7290         u8         reserved_at_60[0x20];
7291
7292         u8         table_type[0x8];
7293         u8         reserved_at_88[0x18];
7294
7295         u8         reserved_at_a0[0x20];
7296
7297         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7298 };
7299
7300 struct mlx5_ifc_create_flow_group_out_bits {
7301         u8         status[0x8];
7302         u8         reserved_0[0x18];
7303
7304         u8         syndrome[0x20];
7305
7306         u8         reserved_1[0x8];
7307         u8         group_id[0x18];
7308
7309         u8         reserved_2[0x20];
7310 };
7311
7312 enum {
7313         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7314         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7315         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7316 };
7317
7318 struct mlx5_ifc_create_flow_group_in_bits {
7319         u8         opcode[0x10];
7320         u8         reserved_0[0x10];
7321
7322         u8         reserved_1[0x10];
7323         u8         op_mod[0x10];
7324
7325         u8         other_vport[0x1];
7326         u8         reserved_2[0xf];
7327         u8         vport_number[0x10];
7328
7329         u8         reserved_3[0x20];
7330
7331         u8         table_type[0x8];
7332         u8         reserved_4[0x18];
7333
7334         u8         reserved_5[0x8];
7335         u8         table_id[0x18];
7336
7337         u8         reserved_6[0x20];
7338
7339         u8         start_flow_index[0x20];
7340
7341         u8         reserved_7[0x20];
7342
7343         u8         end_flow_index[0x20];
7344
7345         u8         reserved_8[0xa0];
7346
7347         u8         reserved_9[0x18];
7348         u8         match_criteria_enable[0x8];
7349
7350         struct mlx5_ifc_fte_match_param_bits match_criteria;
7351
7352         u8         reserved_10[0xe00];
7353 };
7354
7355 struct mlx5_ifc_create_encryption_key_out_bits {
7356         u8         status[0x8];
7357         u8         reserved_at_8[0x18];
7358
7359         u8         syndrome[0x20];
7360
7361         u8         obj_id[0x20];
7362
7363         u8         reserved_at_60[0x20];
7364 };
7365
7366 struct mlx5_ifc_create_encryption_key_in_bits {
7367         u8         opcode[0x10];
7368         u8         reserved_at_10[0x10];
7369
7370         u8         reserved_at_20[0x10];
7371         u8         obj_type[0x10];
7372
7373         u8         reserved_at_40[0x40];
7374
7375         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7376 };
7377
7378 struct mlx5_ifc_create_eq_out_bits {
7379         u8         status[0x8];
7380         u8         reserved_0[0x18];
7381
7382         u8         syndrome[0x20];
7383
7384         u8         reserved_1[0x18];
7385         u8         eq_number[0x8];
7386
7387         u8         reserved_2[0x20];
7388 };
7389
7390 struct mlx5_ifc_create_eq_in_bits {
7391         u8         opcode[0x10];
7392         u8         reserved_0[0x10];
7393
7394         u8         reserved_1[0x10];
7395         u8         op_mod[0x10];
7396
7397         u8         reserved_2[0x40];
7398
7399         struct mlx5_ifc_eqc_bits eq_context_entry;
7400
7401         u8         reserved_3[0x40];
7402
7403         u8         event_bitmask[0x40];
7404
7405         u8         reserved_4[0x580];
7406
7407         u8         pas[0][0x40];
7408 };
7409
7410 struct mlx5_ifc_create_dct_out_bits {
7411         u8         status[0x8];
7412         u8         reserved_0[0x18];
7413
7414         u8         syndrome[0x20];
7415
7416         u8         reserved_1[0x8];
7417         u8         dctn[0x18];
7418
7419         u8         reserved_2[0x20];
7420 };
7421
7422 struct mlx5_ifc_create_dct_in_bits {
7423         u8         opcode[0x10];
7424         u8         reserved_0[0x10];
7425
7426         u8         reserved_1[0x10];
7427         u8         op_mod[0x10];
7428
7429         u8         reserved_2[0x40];
7430
7431         struct mlx5_ifc_dctc_bits dct_context_entry;
7432
7433         u8         reserved_3[0x180];
7434 };
7435
7436 struct mlx5_ifc_create_cq_out_bits {
7437         u8         status[0x8];
7438         u8         reserved_0[0x18];
7439
7440         u8         syndrome[0x20];
7441
7442         u8         reserved_1[0x8];
7443         u8         cqn[0x18];
7444
7445         u8         reserved_2[0x20];
7446 };
7447
7448 struct mlx5_ifc_create_cq_in_bits {
7449         u8         opcode[0x10];
7450         u8         reserved_0[0x10];
7451
7452         u8         reserved_1[0x10];
7453         u8         op_mod[0x10];
7454
7455         u8         reserved_2[0x40];
7456
7457         struct mlx5_ifc_cqc_bits cq_context;
7458
7459         u8         reserved_3[0x600];
7460
7461         u8         pas[0][0x40];
7462 };
7463
7464 struct mlx5_ifc_config_int_moderation_out_bits {
7465         u8         status[0x8];
7466         u8         reserved_0[0x18];
7467
7468         u8         syndrome[0x20];
7469
7470         u8         reserved_1[0x4];
7471         u8         min_delay[0xc];
7472         u8         int_vector[0x10];
7473
7474         u8         reserved_2[0x20];
7475 };
7476
7477 enum {
7478         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7479         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7480 };
7481
7482 struct mlx5_ifc_config_int_moderation_in_bits {
7483         u8         opcode[0x10];
7484         u8         reserved_0[0x10];
7485
7486         u8         reserved_1[0x10];
7487         u8         op_mod[0x10];
7488
7489         u8         reserved_2[0x4];
7490         u8         min_delay[0xc];
7491         u8         int_vector[0x10];
7492
7493         u8         reserved_3[0x20];
7494 };
7495
7496 struct mlx5_ifc_attach_to_mcg_out_bits {
7497         u8         status[0x8];
7498         u8         reserved_0[0x18];
7499
7500         u8         syndrome[0x20];
7501
7502         u8         reserved_1[0x40];
7503 };
7504
7505 struct mlx5_ifc_attach_to_mcg_in_bits {
7506         u8         opcode[0x10];
7507         u8         reserved_0[0x10];
7508
7509         u8         reserved_1[0x10];
7510         u8         op_mod[0x10];
7511
7512         u8         reserved_2[0x8];
7513         u8         qpn[0x18];
7514
7515         u8         reserved_3[0x20];
7516
7517         u8         multicast_gid[16][0x8];
7518 };
7519
7520 struct mlx5_ifc_arm_xrc_srq_out_bits {
7521         u8         status[0x8];
7522         u8         reserved_0[0x18];
7523
7524         u8         syndrome[0x20];
7525
7526         u8         reserved_1[0x40];
7527 };
7528
7529 enum {
7530         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7531 };
7532
7533 struct mlx5_ifc_arm_xrc_srq_in_bits {
7534         u8         opcode[0x10];
7535         u8         reserved_0[0x10];
7536
7537         u8         reserved_1[0x10];
7538         u8         op_mod[0x10];
7539
7540         u8         reserved_2[0x8];
7541         u8         xrc_srqn[0x18];
7542
7543         u8         reserved_3[0x10];
7544         u8         lwm[0x10];
7545 };
7546
7547 struct mlx5_ifc_arm_rq_out_bits {
7548         u8         status[0x8];
7549         u8         reserved_0[0x18];
7550
7551         u8         syndrome[0x20];
7552
7553         u8         reserved_1[0x40];
7554 };
7555
7556 enum {
7557         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7558 };
7559
7560 struct mlx5_ifc_arm_rq_in_bits {
7561         u8         opcode[0x10];
7562         u8         reserved_0[0x10];
7563
7564         u8         reserved_1[0x10];
7565         u8         op_mod[0x10];
7566
7567         u8         reserved_2[0x8];
7568         u8         srq_number[0x18];
7569
7570         u8         reserved_3[0x10];
7571         u8         lwm[0x10];
7572 };
7573
7574 struct mlx5_ifc_arm_dct_out_bits {
7575         u8         status[0x8];
7576         u8         reserved_0[0x18];
7577
7578         u8         syndrome[0x20];
7579
7580         u8         reserved_1[0x40];
7581 };
7582
7583 struct mlx5_ifc_arm_dct_in_bits {
7584         u8         opcode[0x10];
7585         u8         reserved_0[0x10];
7586
7587         u8         reserved_1[0x10];
7588         u8         op_mod[0x10];
7589
7590         u8         reserved_2[0x8];
7591         u8         dctn[0x18];
7592
7593         u8         reserved_3[0x20];
7594 };
7595
7596 struct mlx5_ifc_alloc_xrcd_out_bits {
7597         u8         status[0x8];
7598         u8         reserved_0[0x18];
7599
7600         u8         syndrome[0x20];
7601
7602         u8         reserved_1[0x8];
7603         u8         xrcd[0x18];
7604
7605         u8         reserved_2[0x20];
7606 };
7607
7608 struct mlx5_ifc_alloc_xrcd_in_bits {
7609         u8         opcode[0x10];
7610         u8         reserved_0[0x10];
7611
7612         u8         reserved_1[0x10];
7613         u8         op_mod[0x10];
7614
7615         u8         reserved_2[0x40];
7616 };
7617
7618 struct mlx5_ifc_alloc_uar_out_bits {
7619         u8         status[0x8];
7620         u8         reserved_0[0x18];
7621
7622         u8         syndrome[0x20];
7623
7624         u8         reserved_1[0x8];
7625         u8         uar[0x18];
7626
7627         u8         reserved_2[0x20];
7628 };
7629
7630 struct mlx5_ifc_alloc_uar_in_bits {
7631         u8         opcode[0x10];
7632         u8         reserved_0[0x10];
7633
7634         u8         reserved_1[0x10];
7635         u8         op_mod[0x10];
7636
7637         u8         reserved_2[0x40];
7638 };
7639
7640 struct mlx5_ifc_alloc_transport_domain_out_bits {
7641         u8         status[0x8];
7642         u8         reserved_0[0x18];
7643
7644         u8         syndrome[0x20];
7645
7646         u8         reserved_1[0x8];
7647         u8         transport_domain[0x18];
7648
7649         u8         reserved_2[0x20];
7650 };
7651
7652 struct mlx5_ifc_alloc_transport_domain_in_bits {
7653         u8         opcode[0x10];
7654         u8         reserved_0[0x10];
7655
7656         u8         reserved_1[0x10];
7657         u8         op_mod[0x10];
7658
7659         u8         reserved_2[0x40];
7660 };
7661
7662 struct mlx5_ifc_alloc_q_counter_out_bits {
7663         u8         status[0x8];
7664         u8         reserved_0[0x18];
7665
7666         u8         syndrome[0x20];
7667
7668         u8         reserved_1[0x18];
7669         u8         counter_set_id[0x8];
7670
7671         u8         reserved_2[0x20];
7672 };
7673
7674 struct mlx5_ifc_alloc_q_counter_in_bits {
7675         u8         opcode[0x10];
7676         u8         reserved_0[0x10];
7677
7678         u8         reserved_1[0x10];
7679         u8         op_mod[0x10];
7680
7681         u8         reserved_2[0x40];
7682 };
7683
7684 struct mlx5_ifc_alloc_pd_out_bits {
7685         u8         status[0x8];
7686         u8         reserved_0[0x18];
7687
7688         u8         syndrome[0x20];
7689
7690         u8         reserved_1[0x8];
7691         u8         pd[0x18];
7692
7693         u8         reserved_2[0x20];
7694 };
7695
7696 struct mlx5_ifc_alloc_pd_in_bits {
7697         u8         opcode[0x10];
7698         u8         reserved_0[0x10];
7699
7700         u8         reserved_1[0x10];
7701         u8         op_mod[0x10];
7702
7703         u8         reserved_2[0x40];
7704 };
7705
7706 struct mlx5_ifc_alloc_flow_counter_out_bits {
7707         u8         status[0x8];
7708         u8         reserved_0[0x18];
7709
7710         u8         syndrome[0x20];
7711
7712         u8         reserved_1[0x10];
7713         u8         flow_counter_id[0x10];
7714
7715         u8         reserved_2[0x20];
7716 };
7717
7718 struct mlx5_ifc_alloc_flow_counter_in_bits {
7719         u8         opcode[0x10];
7720         u8         reserved_0[0x10];
7721
7722         u8         reserved_1[0x10];
7723         u8         op_mod[0x10];
7724
7725         u8         reserved_2[0x40];
7726 };
7727
7728 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7729         u8         status[0x8];
7730         u8         reserved_0[0x18];
7731
7732         u8         syndrome[0x20];
7733
7734         u8         reserved_1[0x40];
7735 };
7736
7737 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7738         u8         opcode[0x10];
7739         u8         reserved_0[0x10];
7740
7741         u8         reserved_1[0x10];
7742         u8         op_mod[0x10];
7743
7744         u8         reserved_2[0x20];
7745
7746         u8         reserved_3[0x10];
7747         u8         vxlan_udp_port[0x10];
7748 };
7749
7750 struct mlx5_ifc_activate_tracer_out_bits {
7751         u8         status[0x8];
7752         u8         reserved_0[0x18];
7753
7754         u8         syndrome[0x20];
7755
7756         u8         reserved_1[0x40];
7757 };
7758
7759 struct mlx5_ifc_activate_tracer_in_bits {
7760         u8         opcode[0x10];
7761         u8         reserved_0[0x10];
7762
7763         u8         reserved_1[0x10];
7764         u8         op_mod[0x10];
7765
7766         u8         mkey[0x20];
7767
7768         u8         reserved_2[0x20];
7769 };
7770
7771 struct mlx5_ifc_set_rate_limit_out_bits {
7772         u8         status[0x8];
7773         u8         reserved_at_8[0x18];
7774
7775         u8         syndrome[0x20];
7776
7777         u8         reserved_at_40[0x40];
7778 };
7779
7780 struct mlx5_ifc_set_rate_limit_in_bits {
7781         u8         opcode[0x10];
7782         u8         reserved_at_10[0x10];
7783
7784         u8         reserved_at_20[0x10];
7785         u8         op_mod[0x10];
7786
7787         u8         reserved_at_40[0x10];
7788         u8         rate_limit_index[0x10];
7789
7790         u8         reserved_at_60[0x20];
7791
7792         u8         rate_limit[0x20];
7793         u8         burst_upper_bound[0x20];
7794 };
7795
7796 struct mlx5_ifc_access_register_out_bits {
7797         u8         status[0x8];
7798         u8         reserved_0[0x18];
7799
7800         u8         syndrome[0x20];
7801
7802         u8         reserved_1[0x40];
7803
7804         u8         register_data[0][0x20];
7805 };
7806
7807 enum {
7808         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7809         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7810 };
7811
7812 struct mlx5_ifc_access_register_in_bits {
7813         u8         opcode[0x10];
7814         u8         reserved_0[0x10];
7815
7816         u8         reserved_1[0x10];
7817         u8         op_mod[0x10];
7818
7819         u8         reserved_2[0x10];
7820         u8         register_id[0x10];
7821
7822         u8         argument[0x20];
7823
7824         u8         register_data[0][0x20];
7825 };
7826
7827 struct mlx5_ifc_sltp_reg_bits {
7828         u8         status[0x4];
7829         u8         version[0x4];
7830         u8         local_port[0x8];
7831         u8         pnat[0x2];
7832         u8         reserved_0[0x2];
7833         u8         lane[0x4];
7834         u8         reserved_1[0x8];
7835
7836         u8         reserved_2[0x20];
7837
7838         u8         reserved_3[0x7];
7839         u8         polarity[0x1];
7840         u8         ob_tap0[0x8];
7841         u8         ob_tap1[0x8];
7842         u8         ob_tap2[0x8];
7843
7844         u8         reserved_4[0xc];
7845         u8         ob_preemp_mode[0x4];
7846         u8         ob_reg[0x8];
7847         u8         ob_bias[0x8];
7848
7849         u8         reserved_5[0x20];
7850 };
7851
7852 struct mlx5_ifc_slrp_reg_bits {
7853         u8         status[0x4];
7854         u8         version[0x4];
7855         u8         local_port[0x8];
7856         u8         pnat[0x2];
7857         u8         reserved_0[0x2];
7858         u8         lane[0x4];
7859         u8         reserved_1[0x8];
7860
7861         u8         ib_sel[0x2];
7862         u8         reserved_2[0x11];
7863         u8         dp_sel[0x1];
7864         u8         dp90sel[0x4];
7865         u8         mix90phase[0x8];
7866
7867         u8         ffe_tap0[0x8];
7868         u8         ffe_tap1[0x8];
7869         u8         ffe_tap2[0x8];
7870         u8         ffe_tap3[0x8];
7871
7872         u8         ffe_tap4[0x8];
7873         u8         ffe_tap5[0x8];
7874         u8         ffe_tap6[0x8];
7875         u8         ffe_tap7[0x8];
7876
7877         u8         ffe_tap8[0x8];
7878         u8         mixerbias_tap_amp[0x8];
7879         u8         reserved_3[0x7];
7880         u8         ffe_tap_en[0x9];
7881
7882         u8         ffe_tap_offset0[0x8];
7883         u8         ffe_tap_offset1[0x8];
7884         u8         slicer_offset0[0x10];
7885
7886         u8         mixer_offset0[0x10];
7887         u8         mixer_offset1[0x10];
7888
7889         u8         mixerbgn_inp[0x8];
7890         u8         mixerbgn_inn[0x8];
7891         u8         mixerbgn_refp[0x8];
7892         u8         mixerbgn_refn[0x8];
7893
7894         u8         sel_slicer_lctrl_h[0x1];
7895         u8         sel_slicer_lctrl_l[0x1];
7896         u8         reserved_4[0x1];
7897         u8         ref_mixer_vreg[0x5];
7898         u8         slicer_gctrl[0x8];
7899         u8         lctrl_input[0x8];
7900         u8         mixer_offset_cm1[0x8];
7901
7902         u8         common_mode[0x6];
7903         u8         reserved_5[0x1];
7904         u8         mixer_offset_cm0[0x9];
7905         u8         reserved_6[0x7];
7906         u8         slicer_offset_cm[0x9];
7907 };
7908
7909 struct mlx5_ifc_slrg_reg_bits {
7910         u8         status[0x4];
7911         u8         version[0x4];
7912         u8         local_port[0x8];
7913         u8         pnat[0x2];
7914         u8         reserved_0[0x2];
7915         u8         lane[0x4];
7916         u8         reserved_1[0x8];
7917
7918         u8         time_to_link_up[0x10];
7919         u8         reserved_2[0xc];
7920         u8         grade_lane_speed[0x4];
7921
7922         u8         grade_version[0x8];
7923         u8         grade[0x18];
7924
7925         u8         reserved_3[0x4];
7926         u8         height_grade_type[0x4];
7927         u8         height_grade[0x18];
7928
7929         u8         height_dz[0x10];
7930         u8         height_dv[0x10];
7931
7932         u8         reserved_4[0x10];
7933         u8         height_sigma[0x10];
7934
7935         u8         reserved_5[0x20];
7936
7937         u8         reserved_6[0x4];
7938         u8         phase_grade_type[0x4];
7939         u8         phase_grade[0x18];
7940
7941         u8         reserved_7[0x8];
7942         u8         phase_eo_pos[0x8];
7943         u8         reserved_8[0x8];
7944         u8         phase_eo_neg[0x8];
7945
7946         u8         ffe_set_tested[0x10];
7947         u8         test_errors_per_lane[0x10];
7948 };
7949
7950 struct mlx5_ifc_pvlc_reg_bits {
7951         u8         reserved_0[0x8];
7952         u8         local_port[0x8];
7953         u8         reserved_1[0x10];
7954
7955         u8         reserved_2[0x1c];
7956         u8         vl_hw_cap[0x4];
7957
7958         u8         reserved_3[0x1c];
7959         u8         vl_admin[0x4];
7960
7961         u8         reserved_4[0x1c];
7962         u8         vl_operational[0x4];
7963 };
7964
7965 struct mlx5_ifc_pude_reg_bits {
7966         u8         swid[0x8];
7967         u8         local_port[0x8];
7968         u8         reserved_0[0x4];
7969         u8         admin_status[0x4];
7970         u8         reserved_1[0x4];
7971         u8         oper_status[0x4];
7972
7973         u8         reserved_2[0x60];
7974 };
7975
7976 enum {
7977         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7978         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7979 };
7980
7981 struct mlx5_ifc_ptys_reg_bits {
7982         u8         reserved_0[0x1];
7983         u8         an_disable_admin[0x1];
7984         u8         an_disable_cap[0x1];
7985         u8         reserved_1[0x4];
7986         u8         force_tx_aba_param[0x1];
7987         u8         local_port[0x8];
7988         u8         reserved_2[0xd];
7989         u8         proto_mask[0x3];
7990
7991         u8         an_status[0x4];
7992         u8         reserved_3[0xc];
7993         u8         data_rate_oper[0x10];
7994
7995         u8         ext_eth_proto_capability[0x20];
7996
7997         u8         eth_proto_capability[0x20];
7998
7999         u8         ib_link_width_capability[0x10];
8000         u8         ib_proto_capability[0x10];
8001
8002         u8         ext_eth_proto_admin[0x20];
8003
8004         u8         eth_proto_admin[0x20];
8005
8006         u8         ib_link_width_admin[0x10];
8007         u8         ib_proto_admin[0x10];
8008
8009         u8         ext_eth_proto_oper[0x20];
8010
8011         u8         eth_proto_oper[0x20];
8012
8013         u8         ib_link_width_oper[0x10];
8014         u8         ib_proto_oper[0x10];
8015
8016         u8         reserved_4[0x1c];
8017         u8         connector_type[0x4];
8018
8019         u8         eth_proto_lp_advertise[0x20];
8020
8021         u8         reserved_5[0x60];
8022 };
8023
8024 struct mlx5_ifc_ptas_reg_bits {
8025         u8         reserved_0[0x20];
8026
8027         u8         algorithm_options[0x10];
8028         u8         reserved_1[0x4];
8029         u8         repetitions_mode[0x4];
8030         u8         num_of_repetitions[0x8];
8031
8032         u8         grade_version[0x8];
8033         u8         height_grade_type[0x4];
8034         u8         phase_grade_type[0x4];
8035         u8         height_grade_weight[0x8];
8036         u8         phase_grade_weight[0x8];
8037
8038         u8         gisim_measure_bits[0x10];
8039         u8         adaptive_tap_measure_bits[0x10];
8040
8041         u8         ber_bath_high_error_threshold[0x10];
8042         u8         ber_bath_mid_error_threshold[0x10];
8043
8044         u8         ber_bath_low_error_threshold[0x10];
8045         u8         one_ratio_high_threshold[0x10];
8046
8047         u8         one_ratio_high_mid_threshold[0x10];
8048         u8         one_ratio_low_mid_threshold[0x10];
8049
8050         u8         one_ratio_low_threshold[0x10];
8051         u8         ndeo_error_threshold[0x10];
8052
8053         u8         mixer_offset_step_size[0x10];
8054         u8         reserved_2[0x8];
8055         u8         mix90_phase_for_voltage_bath[0x8];
8056
8057         u8         mixer_offset_start[0x10];
8058         u8         mixer_offset_end[0x10];
8059
8060         u8         reserved_3[0x15];
8061         u8         ber_test_time[0xb];
8062 };
8063
8064 struct mlx5_ifc_pspa_reg_bits {
8065         u8         swid[0x8];
8066         u8         local_port[0x8];
8067         u8         sub_port[0x8];
8068         u8         reserved_0[0x8];
8069
8070         u8         reserved_1[0x20];
8071 };
8072
8073 struct mlx5_ifc_ppsc_reg_bits {
8074         u8         reserved_0[0x8];
8075         u8         local_port[0x8];
8076         u8         reserved_1[0x10];
8077
8078         u8         reserved_2[0x60];
8079
8080         u8         reserved_3[0x1c];
8081         u8         wrps_admin[0x4];
8082
8083         u8         reserved_4[0x1c];
8084         u8         wrps_status[0x4];
8085
8086         u8         up_th_vld[0x1];
8087         u8         down_th_vld[0x1];
8088         u8         reserved_5[0x6];
8089         u8         up_threshold[0x8];
8090         u8         reserved_6[0x8];
8091         u8         down_threshold[0x8];
8092
8093         u8         reserved_7[0x20];
8094
8095         u8         reserved_8[0x1c];
8096         u8         srps_admin[0x4];
8097
8098         u8         reserved_9[0x60];
8099 };
8100
8101 struct mlx5_ifc_pplr_reg_bits {
8102         u8         reserved_0[0x8];
8103         u8         local_port[0x8];
8104         u8         reserved_1[0x10];
8105
8106         u8         reserved_2[0x8];
8107         u8         lb_cap[0x8];
8108         u8         reserved_3[0x8];
8109         u8         lb_en[0x8];
8110 };
8111
8112 struct mlx5_ifc_pplm_reg_bits {
8113         u8         reserved_at_0[0x8];
8114         u8         local_port[0x8];
8115         u8         reserved_at_10[0x10];
8116
8117         u8         reserved_at_20[0x20];
8118
8119         u8         port_profile_mode[0x8];
8120         u8         static_port_profile[0x8];
8121         u8         active_port_profile[0x8];
8122         u8         reserved_at_58[0x8];
8123
8124         u8         retransmission_active[0x8];
8125         u8         fec_mode_active[0x18];
8126
8127         u8         rs_fec_correction_bypass_cap[0x4];
8128         u8         reserved_at_84[0x8];
8129         u8         fec_override_cap_56g[0x4];
8130         u8         fec_override_cap_100g[0x4];
8131         u8         fec_override_cap_50g[0x4];
8132         u8         fec_override_cap_25g[0x4];
8133         u8         fec_override_cap_10g_40g[0x4];
8134
8135         u8         rs_fec_correction_bypass_admin[0x4];
8136         u8         reserved_at_a4[0x8];
8137         u8         fec_override_admin_56g[0x4];
8138         u8         fec_override_admin_100g[0x4];
8139         u8         fec_override_admin_50g[0x4];
8140         u8         fec_override_admin_25g[0x4];
8141         u8         fec_override_admin_10g_40g[0x4];
8142
8143         u8         fec_override_cap_400g_8x[0x10];
8144         u8         fec_override_cap_200g_4x[0x10];
8145         u8         fec_override_cap_100g_2x[0x10];
8146         u8         fec_override_cap_50g_1x[0x10];
8147
8148         u8         fec_override_admin_400g_8x[0x10];
8149         u8         fec_override_admin_200g_4x[0x10];
8150         u8         fec_override_admin_100g_2x[0x10];
8151         u8         fec_override_admin_50g_1x[0x10];
8152
8153         u8         reserved_at_140[0xC0];
8154 };
8155
8156 struct mlx5_ifc_ppll_reg_bits {
8157         u8         num_pll_groups[0x8];
8158         u8         pll_group[0x8];
8159         u8         reserved_0[0x4];
8160         u8         num_plls[0x4];
8161         u8         reserved_1[0x8];
8162
8163         u8         reserved_2[0x1f];
8164         u8         ae[0x1];
8165
8166         u8         pll_status[4][0x40];
8167 };
8168
8169 struct mlx5_ifc_ppad_reg_bits {
8170         u8         reserved_0[0x3];
8171         u8         single_mac[0x1];
8172         u8         reserved_1[0x4];
8173         u8         local_port[0x8];
8174         u8         mac_47_32[0x10];
8175
8176         u8         mac_31_0[0x20];
8177
8178         u8         reserved_2[0x40];
8179 };
8180
8181 struct mlx5_ifc_pmtu_reg_bits {
8182         u8         reserved_0[0x8];
8183         u8         local_port[0x8];
8184         u8         reserved_1[0x10];
8185
8186         u8         max_mtu[0x10];
8187         u8         reserved_2[0x10];
8188
8189         u8         admin_mtu[0x10];
8190         u8         reserved_3[0x10];
8191
8192         u8         oper_mtu[0x10];
8193         u8         reserved_4[0x10];
8194 };
8195
8196 struct mlx5_ifc_pmpr_reg_bits {
8197         u8         reserved_0[0x8];
8198         u8         module[0x8];
8199         u8         reserved_1[0x10];
8200
8201         u8         reserved_2[0x18];
8202         u8         attenuation_5g[0x8];
8203
8204         u8         reserved_3[0x18];
8205         u8         attenuation_7g[0x8];
8206
8207         u8         reserved_4[0x18];
8208         u8         attenuation_12g[0x8];
8209 };
8210
8211 struct mlx5_ifc_pmpe_reg_bits {
8212         u8         reserved_0[0x8];
8213         u8         module[0x8];
8214         u8         reserved_1[0xc];
8215         u8         module_status[0x4];
8216
8217         u8         reserved_2[0x14];
8218         u8         error_type[0x4];
8219         u8         reserved_3[0x8];
8220
8221         u8         reserved_4[0x40];
8222 };
8223
8224 struct mlx5_ifc_pmpc_reg_bits {
8225         u8         module_state_updated[32][0x8];
8226 };
8227
8228 struct mlx5_ifc_pmlpn_reg_bits {
8229         u8         reserved_0[0x4];
8230         u8         mlpn_status[0x4];
8231         u8         local_port[0x8];
8232         u8         reserved_1[0x10];
8233
8234         u8         e[0x1];
8235         u8         reserved_2[0x1f];
8236 };
8237
8238 struct mlx5_ifc_pmlp_reg_bits {
8239         u8         rxtx[0x1];
8240         u8         reserved_0[0x7];
8241         u8         local_port[0x8];
8242         u8         reserved_1[0x8];
8243         u8         width[0x8];
8244
8245         u8         lane0_module_mapping[0x20];
8246
8247         u8         lane1_module_mapping[0x20];
8248
8249         u8         lane2_module_mapping[0x20];
8250
8251         u8         lane3_module_mapping[0x20];
8252
8253         u8         reserved_2[0x160];
8254 };
8255
8256 struct mlx5_ifc_pmaos_reg_bits {
8257         u8         reserved_0[0x8];
8258         u8         module[0x8];
8259         u8         reserved_1[0x4];
8260         u8         admin_status[0x4];
8261         u8         reserved_2[0x4];
8262         u8         oper_status[0x4];
8263
8264         u8         ase[0x1];
8265         u8         ee[0x1];
8266         u8         reserved_3[0x12];
8267         u8         error_type[0x4];
8268         u8         reserved_4[0x6];
8269         u8         e[0x2];
8270
8271         u8         reserved_5[0x40];
8272 };
8273
8274 struct mlx5_ifc_plpc_reg_bits {
8275         u8         reserved_0[0x4];
8276         u8         profile_id[0xc];
8277         u8         reserved_1[0x4];
8278         u8         proto_mask[0x4];
8279         u8         reserved_2[0x8];
8280
8281         u8         reserved_3[0x10];
8282         u8         lane_speed[0x10];
8283
8284         u8         reserved_4[0x17];
8285         u8         lpbf[0x1];
8286         u8         fec_mode_policy[0x8];
8287
8288         u8         retransmission_capability[0x8];
8289         u8         fec_mode_capability[0x18];
8290
8291         u8         retransmission_support_admin[0x8];
8292         u8         fec_mode_support_admin[0x18];
8293
8294         u8         retransmission_request_admin[0x8];
8295         u8         fec_mode_request_admin[0x18];
8296
8297         u8         reserved_5[0x80];
8298 };
8299
8300 struct mlx5_ifc_pll_status_data_bits {
8301         u8         reserved_0[0x1];
8302         u8         lock_cal[0x1];
8303         u8         lock_status[0x2];
8304         u8         reserved_1[0x2];
8305         u8         algo_f_ctrl[0xa];
8306         u8         analog_algo_num_var[0x6];
8307         u8         f_ctrl_measure[0xa];
8308
8309         u8         reserved_2[0x2];
8310         u8         analog_var[0x6];
8311         u8         reserved_3[0x2];
8312         u8         high_var[0x6];
8313         u8         reserved_4[0x2];
8314         u8         low_var[0x6];
8315         u8         reserved_5[0x2];
8316         u8         mid_val[0x6];
8317 };
8318
8319 struct mlx5_ifc_plib_reg_bits {
8320         u8         reserved_0[0x8];
8321         u8         local_port[0x8];
8322         u8         reserved_1[0x8];
8323         u8         ib_port[0x8];
8324
8325         u8         reserved_2[0x60];
8326 };
8327
8328 struct mlx5_ifc_plbf_reg_bits {
8329         u8         reserved_0[0x8];
8330         u8         local_port[0x8];
8331         u8         reserved_1[0xd];
8332         u8         lbf_mode[0x3];
8333
8334         u8         reserved_2[0x20];
8335 };
8336
8337 struct mlx5_ifc_pipg_reg_bits {
8338         u8         reserved_0[0x8];
8339         u8         local_port[0x8];
8340         u8         reserved_1[0x10];
8341
8342         u8         dic[0x1];
8343         u8         reserved_2[0x19];
8344         u8         ipg[0x4];
8345         u8         reserved_3[0x2];
8346 };
8347
8348 struct mlx5_ifc_pifr_reg_bits {
8349         u8         reserved_0[0x8];
8350         u8         local_port[0x8];
8351         u8         reserved_1[0x10];
8352
8353         u8         reserved_2[0xe0];
8354
8355         u8         port_filter[8][0x20];
8356
8357         u8         port_filter_update_en[8][0x20];
8358 };
8359
8360 struct mlx5_ifc_phys_layer_cntrs_bits {
8361         u8         time_since_last_clear_high[0x20];
8362
8363         u8         time_since_last_clear_low[0x20];
8364
8365         u8         symbol_errors_high[0x20];
8366
8367         u8         symbol_errors_low[0x20];
8368
8369         u8         sync_headers_errors_high[0x20];
8370
8371         u8         sync_headers_errors_low[0x20];
8372
8373         u8         edpl_bip_errors_lane0_high[0x20];
8374
8375         u8         edpl_bip_errors_lane0_low[0x20];
8376
8377         u8         edpl_bip_errors_lane1_high[0x20];
8378
8379         u8         edpl_bip_errors_lane1_low[0x20];
8380
8381         u8         edpl_bip_errors_lane2_high[0x20];
8382
8383         u8         edpl_bip_errors_lane2_low[0x20];
8384
8385         u8         edpl_bip_errors_lane3_high[0x20];
8386
8387         u8         edpl_bip_errors_lane3_low[0x20];
8388
8389         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8390
8391         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8392
8393         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8394
8395         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8396
8397         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8398
8399         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8400
8401         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8402
8403         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8404
8405         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8406
8407         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8408
8409         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8410
8411         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8412
8413         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8414
8415         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8416
8417         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8418
8419         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8420
8421         u8         rs_fec_corrected_blocks_high[0x20];
8422
8423         u8         rs_fec_corrected_blocks_low[0x20];
8424
8425         u8         rs_fec_uncorrectable_blocks_high[0x20];
8426
8427         u8         rs_fec_uncorrectable_blocks_low[0x20];
8428
8429         u8         rs_fec_no_errors_blocks_high[0x20];
8430
8431         u8         rs_fec_no_errors_blocks_low[0x20];
8432
8433         u8         rs_fec_single_error_blocks_high[0x20];
8434
8435         u8         rs_fec_single_error_blocks_low[0x20];
8436
8437         u8         rs_fec_corrected_symbols_total_high[0x20];
8438
8439         u8         rs_fec_corrected_symbols_total_low[0x20];
8440
8441         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8442
8443         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8444
8445         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8446
8447         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8448
8449         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8450
8451         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8452
8453         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8454
8455         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8456
8457         u8         link_down_events[0x20];
8458
8459         u8         successful_recovery_events[0x20];
8460
8461         u8         reserved_0[0x180];
8462 };
8463
8464 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8465         u8         symbol_error_counter[0x10];
8466
8467         u8         link_error_recovery_counter[0x8];
8468
8469         u8         link_downed_counter[0x8];
8470
8471         u8         port_rcv_errors[0x10];
8472
8473         u8         port_rcv_remote_physical_errors[0x10];
8474
8475         u8         port_rcv_switch_relay_errors[0x10];
8476
8477         u8         port_xmit_discards[0x10];
8478
8479         u8         port_xmit_constraint_errors[0x8];
8480
8481         u8         port_rcv_constraint_errors[0x8];
8482
8483         u8         reserved_at_70[0x8];
8484
8485         u8         link_overrun_errors[0x8];
8486
8487         u8         reserved_at_80[0x10];
8488
8489         u8         vl_15_dropped[0x10];
8490
8491         u8         reserved_at_a0[0xa0];
8492 };
8493
8494 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8495         u8         time_since_last_clear_high[0x20];
8496
8497         u8         time_since_last_clear_low[0x20];
8498
8499         u8         phy_received_bits_high[0x20];
8500
8501         u8         phy_received_bits_low[0x20];
8502
8503         u8         phy_symbol_errors_high[0x20];
8504
8505         u8         phy_symbol_errors_low[0x20];
8506
8507         u8         phy_corrected_bits_high[0x20];
8508
8509         u8         phy_corrected_bits_low[0x20];
8510
8511         u8         phy_corrected_bits_lane0_high[0x20];
8512
8513         u8         phy_corrected_bits_lane0_low[0x20];
8514
8515         u8         phy_corrected_bits_lane1_high[0x20];
8516
8517         u8         phy_corrected_bits_lane1_low[0x20];
8518
8519         u8         phy_corrected_bits_lane2_high[0x20];
8520
8521         u8         phy_corrected_bits_lane2_low[0x20];
8522
8523         u8         phy_corrected_bits_lane3_high[0x20];
8524
8525         u8         phy_corrected_bits_lane3_low[0x20];
8526
8527         u8         reserved_at_200[0x5c0];
8528 };
8529
8530 struct mlx5_ifc_infiniband_port_cntrs_bits {
8531         u8         symbol_error_counter[0x10];
8532         u8         link_error_recovery_counter[0x8];
8533         u8         link_downed_counter[0x8];
8534
8535         u8         port_rcv_errors[0x10];
8536         u8         port_rcv_remote_physical_errors[0x10];
8537
8538         u8         port_rcv_switch_relay_errors[0x10];
8539         u8         port_xmit_discards[0x10];
8540
8541         u8         port_xmit_constraint_errors[0x8];
8542         u8         port_rcv_constraint_errors[0x8];
8543         u8         reserved_0[0x8];
8544         u8         local_link_integrity_errors[0x4];
8545         u8         excessive_buffer_overrun_errors[0x4];
8546
8547         u8         reserved_1[0x10];
8548         u8         vl_15_dropped[0x10];
8549
8550         u8         port_xmit_data[0x20];
8551
8552         u8         port_rcv_data[0x20];
8553
8554         u8         port_xmit_pkts[0x20];
8555
8556         u8         port_rcv_pkts[0x20];
8557
8558         u8         port_xmit_wait[0x20];
8559
8560         u8         reserved_2[0x680];
8561 };
8562
8563 struct mlx5_ifc_phrr_reg_bits {
8564         u8         clr[0x1];
8565         u8         reserved_0[0x7];
8566         u8         local_port[0x8];
8567         u8         reserved_1[0x10];
8568
8569         u8         hist_group[0x8];
8570         u8         reserved_2[0x10];
8571         u8         hist_id[0x8];
8572
8573         u8         reserved_3[0x40];
8574
8575         u8         time_since_last_clear_high[0x20];
8576
8577         u8         time_since_last_clear_low[0x20];
8578
8579         u8         bin[10][0x20];
8580 };
8581
8582 struct mlx5_ifc_phbr_for_prio_reg_bits {
8583         u8         reserved_0[0x18];
8584         u8         prio[0x8];
8585 };
8586
8587 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8588         u8         reserved_0[0x18];
8589         u8         tclass[0x8];
8590 };
8591
8592 struct mlx5_ifc_phbr_binding_reg_bits {
8593         u8         opcode[0x4];
8594         u8         reserved_0[0x4];
8595         u8         local_port[0x8];
8596         u8         pnat[0x2];
8597         u8         reserved_1[0xe];
8598
8599         u8         hist_group[0x8];
8600         u8         reserved_2[0x10];
8601         u8         hist_id[0x8];
8602
8603         u8         reserved_3[0x10];
8604         u8         hist_type[0x10];
8605
8606         u8         hist_parameters[0x20];
8607
8608         u8         hist_min_value[0x20];
8609
8610         u8         hist_max_value[0x20];
8611
8612         u8         sample_time[0x20];
8613 };
8614
8615 enum {
8616         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8617         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8618 };
8619
8620 struct mlx5_ifc_pfcc_reg_bits {
8621         u8         dcbx_operation_type[0x2];
8622         u8         cap_local_admin[0x1];
8623         u8         cap_remote_admin[0x1];
8624         u8         reserved_0[0x4];
8625         u8         local_port[0x8];
8626         u8         pnat[0x2];
8627         u8         reserved_1[0xc];
8628         u8         shl_cap[0x1];
8629         u8         shl_opr[0x1];
8630
8631         u8         ppan[0x4];
8632         u8         reserved_2[0x4];
8633         u8         prio_mask_tx[0x8];
8634         u8         reserved_3[0x8];
8635         u8         prio_mask_rx[0x8];
8636
8637         u8         pptx[0x1];
8638         u8         aptx[0x1];
8639         u8         reserved_4[0x6];
8640         u8         pfctx[0x8];
8641         u8         reserved_5[0x8];
8642         u8         cbftx[0x8];
8643
8644         u8         pprx[0x1];
8645         u8         aprx[0x1];
8646         u8         reserved_6[0x6];
8647         u8         pfcrx[0x8];
8648         u8         reserved_7[0x8];
8649         u8         cbfrx[0x8];
8650
8651         u8         device_stall_minor_watermark[0x10];
8652         u8         device_stall_critical_watermark[0x10];
8653
8654         u8         reserved_8[0x60];
8655 };
8656
8657 struct mlx5_ifc_pelc_reg_bits {
8658         u8         op[0x4];
8659         u8         reserved_0[0x4];
8660         u8         local_port[0x8];
8661         u8         reserved_1[0x10];
8662
8663         u8         op_admin[0x8];
8664         u8         op_capability[0x8];
8665         u8         op_request[0x8];
8666         u8         op_active[0x8];
8667
8668         u8         admin[0x40];
8669
8670         u8         capability[0x40];
8671
8672         u8         request[0x40];
8673
8674         u8         active[0x40];
8675
8676         u8         reserved_2[0x80];
8677 };
8678
8679 struct mlx5_ifc_peir_reg_bits {
8680         u8         reserved_0[0x8];
8681         u8         local_port[0x8];
8682         u8         reserved_1[0x10];
8683
8684         u8         reserved_2[0xc];
8685         u8         error_count[0x4];
8686         u8         reserved_3[0x10];
8687
8688         u8         reserved_4[0xc];
8689         u8         lane[0x4];
8690         u8         reserved_5[0x8];
8691         u8         error_type[0x8];
8692 };
8693
8694 struct mlx5_ifc_qcam_access_reg_cap_mask {
8695         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8696         u8         qpdpm[0x1];
8697         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8698         u8         qdpm[0x1];
8699         u8         qpts[0x1];
8700         u8         qcap[0x1];
8701         u8         qcam_access_reg_cap_mask_0[0x1];
8702 };
8703
8704 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8705         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8706         u8         qpts_trust_both[0x1];
8707 };
8708
8709 struct mlx5_ifc_qcam_reg_bits {
8710         u8         reserved_at_0[0x8];
8711         u8         feature_group[0x8];
8712         u8         reserved_at_10[0x8];
8713         u8         access_reg_group[0x8];
8714         u8         reserved_at_20[0x20];
8715
8716         union {
8717                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8718                 u8  reserved_at_0[0x80];
8719         } qos_access_reg_cap_mask;
8720
8721         u8         reserved_at_c0[0x80];
8722
8723         union {
8724                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8725                 u8  reserved_at_0[0x80];
8726         } qos_feature_cap_mask;
8727
8728         u8         reserved_at_1c0[0x80];
8729 };
8730
8731 struct mlx5_ifc_pcam_enhanced_features_bits {
8732         u8         reserved_at_0[0x6d];
8733         u8         rx_icrc_encapsulated_counter[0x1];
8734         u8         reserved_at_6e[0x4];
8735         u8         ptys_extended_ethernet[0x1];
8736         u8         reserved_at_73[0x3];
8737         u8         pfcc_mask[0x1];
8738         u8         reserved_at_77[0x3];
8739         u8         per_lane_error_counters[0x1];
8740         u8         rx_buffer_fullness_counters[0x1];
8741         u8         ptys_connector_type[0x1];
8742         u8         reserved_at_7d[0x1];
8743         u8         ppcnt_discard_group[0x1];
8744         u8         ppcnt_statistical_group[0x1];
8745 };
8746
8747 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8748         u8         port_access_reg_cap_mask_127_to_96[0x20];
8749         u8         port_access_reg_cap_mask_95_to_64[0x20];
8750
8751         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8752         u8         pplm[0x1];
8753         u8         port_access_reg_cap_mask_34_to_32[0x3];
8754
8755         u8         port_access_reg_cap_mask_31_to_13[0x13];
8756         u8         pbmc[0x1];
8757         u8         pptb[0x1];
8758         u8         port_access_reg_cap_mask_10_to_09[0x2];
8759         u8         ppcnt[0x1];
8760         u8         port_access_reg_cap_mask_07_to_00[0x8];
8761 };
8762
8763 struct mlx5_ifc_pcam_reg_bits {
8764         u8         reserved_at_0[0x8];
8765         u8         feature_group[0x8];
8766         u8         reserved_at_10[0x8];
8767         u8         access_reg_group[0x8];
8768
8769         u8         reserved_at_20[0x20];
8770
8771         union {
8772                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8773                 u8         reserved_at_0[0x80];
8774         } port_access_reg_cap_mask;
8775
8776         u8         reserved_at_c0[0x80];
8777
8778         union {
8779                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8780                 u8         reserved_at_0[0x80];
8781         } feature_cap_mask;
8782
8783         u8         reserved_at_1c0[0xc0];
8784 };
8785
8786 struct mlx5_ifc_mcam_enhanced_features_bits {
8787         u8         reserved_at_0[0x6e];
8788         u8         pcie_status_and_power[0x1];
8789         u8         reserved_at_111[0x10];
8790         u8         pcie_performance_group[0x1];
8791 };
8792
8793 struct mlx5_ifc_mcam_access_reg_bits {
8794         u8         reserved_at_0[0x1c];
8795         u8         mcda[0x1];
8796         u8         mcc[0x1];
8797         u8         mcqi[0x1];
8798         u8         reserved_at_1f[0x1];
8799
8800         u8         regs_95_to_64[0x20];
8801         u8         regs_63_to_32[0x20];
8802         u8         regs_31_to_0[0x20];
8803 };
8804
8805 struct mlx5_ifc_mcam_reg_bits {
8806         u8         reserved_at_0[0x8];
8807         u8         feature_group[0x8];
8808         u8         reserved_at_10[0x8];
8809         u8         access_reg_group[0x8];
8810
8811         u8         reserved_at_20[0x20];
8812
8813         union {
8814                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8815                 u8         reserved_at_0[0x80];
8816         } mng_access_reg_cap_mask;
8817
8818         u8         reserved_at_c0[0x80];
8819
8820         union {
8821                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8822                 u8         reserved_at_0[0x80];
8823         } mng_feature_cap_mask;
8824
8825         u8         reserved_at_1c0[0x80];
8826 };
8827
8828 struct mlx5_ifc_pcap_reg_bits {
8829         u8         reserved_0[0x8];
8830         u8         local_port[0x8];
8831         u8         reserved_1[0x10];
8832
8833         u8         port_capability_mask[4][0x20];
8834 };
8835
8836 struct mlx5_ifc_pbmc_reg_bits {
8837         u8         reserved_at_0[0x8];
8838         u8         local_port[0x8];
8839         u8         reserved_at_10[0x10];
8840
8841         u8         xoff_timer_value[0x10];
8842         u8         xoff_refresh[0x10];
8843
8844         u8         reserved_at_40[0x9];
8845         u8         fullness_threshold[0x7];
8846         u8         port_buffer_size[0x10];
8847
8848         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8849
8850         u8         reserved_at_2e0[0x40];
8851 };
8852
8853 struct mlx5_ifc_paos_reg_bits {
8854         u8         swid[0x8];
8855         u8         local_port[0x8];
8856         u8         reserved_0[0x4];
8857         u8         admin_status[0x4];
8858         u8         reserved_1[0x4];
8859         u8         oper_status[0x4];
8860
8861         u8         ase[0x1];
8862         u8         ee[0x1];
8863         u8         reserved_2[0x1c];
8864         u8         e[0x2];
8865
8866         u8         reserved_3[0x40];
8867 };
8868
8869 struct mlx5_ifc_pamp_reg_bits {
8870         u8         reserved_0[0x8];
8871         u8         opamp_group[0x8];
8872         u8         reserved_1[0xc];
8873         u8         opamp_group_type[0x4];
8874
8875         u8         start_index[0x10];
8876         u8         reserved_2[0x4];
8877         u8         num_of_indices[0xc];
8878
8879         u8         index_data[18][0x10];
8880 };
8881
8882 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8883         u8         llr_rx_cells_high[0x20];
8884
8885         u8         llr_rx_cells_low[0x20];
8886
8887         u8         llr_rx_error_high[0x20];
8888
8889         u8         llr_rx_error_low[0x20];
8890
8891         u8         llr_rx_crc_error_high[0x20];
8892
8893         u8         llr_rx_crc_error_low[0x20];
8894
8895         u8         llr_tx_cells_high[0x20];
8896
8897         u8         llr_tx_cells_low[0x20];
8898
8899         u8         llr_tx_ret_cells_high[0x20];
8900
8901         u8         llr_tx_ret_cells_low[0x20];
8902
8903         u8         llr_tx_ret_events_high[0x20];
8904
8905         u8         llr_tx_ret_events_low[0x20];
8906
8907         u8         reserved_0[0x640];
8908 };
8909
8910 struct mlx5_ifc_mtmp_reg_bits {
8911         u8         i[0x1];
8912         u8         reserved_at_1[0x18];
8913         u8         sensor_index[0x7];
8914
8915         u8         reserved_at_20[0x10];
8916         u8         temperature[0x10];
8917
8918         u8         mte[0x1];
8919         u8         mtr[0x1];
8920         u8         reserved_at_42[0x0e];
8921         u8         max_temperature[0x10];
8922
8923         u8         tee[0x2];
8924         u8         reserved_at_62[0x0e];
8925         u8         temperature_threshold_hi[0x10];
8926
8927         u8         reserved_at_80[0x10];
8928         u8         temperature_threshold_lo[0x10];
8929
8930         u8         reserved_at_100[0x20];
8931
8932         u8         sensor_name[0x40];
8933 };
8934
8935 struct mlx5_ifc_lane_2_module_mapping_bits {
8936         u8         reserved_0[0x6];
8937         u8         rx_lane[0x2];
8938         u8         reserved_1[0x6];
8939         u8         tx_lane[0x2];
8940         u8         reserved_2[0x8];
8941         u8         module[0x8];
8942 };
8943
8944 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8945         u8         transmit_queue_high[0x20];
8946
8947         u8         transmit_queue_low[0x20];
8948
8949         u8         reserved_0[0x780];
8950 };
8951
8952 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8953         u8         no_buffer_discard_uc_high[0x20];
8954
8955         u8         no_buffer_discard_uc_low[0x20];
8956
8957         u8         wred_discard_high[0x20];
8958
8959         u8         wred_discard_low[0x20];
8960
8961         u8         reserved_0[0x740];
8962 };
8963
8964 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8965         u8         rx_octets_high[0x20];
8966
8967         u8         rx_octets_low[0x20];
8968
8969         u8         reserved_0[0xc0];
8970
8971         u8         rx_frames_high[0x20];
8972
8973         u8         rx_frames_low[0x20];
8974
8975         u8         tx_octets_high[0x20];
8976
8977         u8         tx_octets_low[0x20];
8978
8979         u8         reserved_1[0xc0];
8980
8981         u8         tx_frames_high[0x20];
8982
8983         u8         tx_frames_low[0x20];
8984
8985         u8         rx_pause_high[0x20];
8986
8987         u8         rx_pause_low[0x20];
8988
8989         u8         rx_pause_duration_high[0x20];
8990
8991         u8         rx_pause_duration_low[0x20];
8992
8993         u8         tx_pause_high[0x20];
8994
8995         u8         tx_pause_low[0x20];
8996
8997         u8         tx_pause_duration_high[0x20];
8998
8999         u8         tx_pause_duration_low[0x20];
9000
9001         u8         rx_pause_transition_high[0x20];
9002
9003         u8         rx_pause_transition_low[0x20];
9004
9005         u8         rx_discards_high[0x20];
9006
9007         u8         rx_discards_low[0x20];
9008
9009         u8         device_stall_minor_watermark_cnt_high[0x20];
9010
9011         u8         device_stall_minor_watermark_cnt_low[0x20];
9012
9013         u8         device_stall_critical_watermark_cnt_high[0x20];
9014
9015         u8         device_stall_critical_watermark_cnt_low[0x20];
9016
9017         u8         reserved_2[0x340];
9018 };
9019
9020 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9021         u8         port_transmit_wait_high[0x20];
9022
9023         u8         port_transmit_wait_low[0x20];
9024
9025         u8         ecn_marked_high[0x20];
9026
9027         u8         ecn_marked_low[0x20];
9028
9029         u8         no_buffer_discard_mc_high[0x20];
9030
9031         u8         no_buffer_discard_mc_low[0x20];
9032
9033         u8         rx_ebp_high[0x20];
9034
9035         u8         rx_ebp_low[0x20];
9036
9037         u8         tx_ebp_high[0x20];
9038
9039         u8         tx_ebp_low[0x20];
9040
9041         u8         rx_buffer_almost_full_high[0x20];
9042
9043         u8         rx_buffer_almost_full_low[0x20];
9044
9045         u8         rx_buffer_full_high[0x20];
9046
9047         u8         rx_buffer_full_low[0x20];
9048
9049         u8         rx_icrc_encapsulated_high[0x20];
9050
9051         u8         rx_icrc_encapsulated_low[0x20];
9052
9053         u8         reserved_0[0x80];
9054
9055         u8         tx_stats_pkts64octets_high[0x20];
9056
9057         u8         tx_stats_pkts64octets_low[0x20];
9058
9059         u8         tx_stats_pkts65to127octets_high[0x20];
9060
9061         u8         tx_stats_pkts65to127octets_low[0x20];
9062
9063         u8         tx_stats_pkts128to255octets_high[0x20];
9064
9065         u8         tx_stats_pkts128to255octets_low[0x20];
9066
9067         u8         tx_stats_pkts256to511octets_high[0x20];
9068
9069         u8         tx_stats_pkts256to511octets_low[0x20];
9070
9071         u8         tx_stats_pkts512to1023octets_high[0x20];
9072
9073         u8         tx_stats_pkts512to1023octets_low[0x20];
9074
9075         u8         tx_stats_pkts1024to1518octets_high[0x20];
9076
9077         u8         tx_stats_pkts1024to1518octets_low[0x20];
9078
9079         u8         tx_stats_pkts1519to2047octets_high[0x20];
9080
9081         u8         tx_stats_pkts1519to2047octets_low[0x20];
9082
9083         u8         tx_stats_pkts2048to4095octets_high[0x20];
9084
9085         u8         tx_stats_pkts2048to4095octets_low[0x20];
9086
9087         u8         tx_stats_pkts4096to8191octets_high[0x20];
9088
9089         u8         tx_stats_pkts4096to8191octets_low[0x20];
9090
9091         u8         tx_stats_pkts8192to10239octets_high[0x20];
9092
9093         u8         tx_stats_pkts8192to10239octets_low[0x20];
9094
9095         u8         reserved_1[0x2C0];
9096 };
9097
9098 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9099         u8         a_frames_transmitted_ok_high[0x20];
9100
9101         u8         a_frames_transmitted_ok_low[0x20];
9102
9103         u8         a_frames_received_ok_high[0x20];
9104
9105         u8         a_frames_received_ok_low[0x20];
9106
9107         u8         a_frame_check_sequence_errors_high[0x20];
9108
9109         u8         a_frame_check_sequence_errors_low[0x20];
9110
9111         u8         a_alignment_errors_high[0x20];
9112
9113         u8         a_alignment_errors_low[0x20];
9114
9115         u8         a_octets_transmitted_ok_high[0x20];
9116
9117         u8         a_octets_transmitted_ok_low[0x20];
9118
9119         u8         a_octets_received_ok_high[0x20];
9120
9121         u8         a_octets_received_ok_low[0x20];
9122
9123         u8         a_multicast_frames_xmitted_ok_high[0x20];
9124
9125         u8         a_multicast_frames_xmitted_ok_low[0x20];
9126
9127         u8         a_broadcast_frames_xmitted_ok_high[0x20];
9128
9129         u8         a_broadcast_frames_xmitted_ok_low[0x20];
9130
9131         u8         a_multicast_frames_received_ok_high[0x20];
9132
9133         u8         a_multicast_frames_received_ok_low[0x20];
9134
9135         u8         a_broadcast_frames_recieved_ok_high[0x20];
9136
9137         u8         a_broadcast_frames_recieved_ok_low[0x20];
9138
9139         u8         a_in_range_length_errors_high[0x20];
9140
9141         u8         a_in_range_length_errors_low[0x20];
9142
9143         u8         a_out_of_range_length_field_high[0x20];
9144
9145         u8         a_out_of_range_length_field_low[0x20];
9146
9147         u8         a_frame_too_long_errors_high[0x20];
9148
9149         u8         a_frame_too_long_errors_low[0x20];
9150
9151         u8         a_symbol_error_during_carrier_high[0x20];
9152
9153         u8         a_symbol_error_during_carrier_low[0x20];
9154
9155         u8         a_mac_control_frames_transmitted_high[0x20];
9156
9157         u8         a_mac_control_frames_transmitted_low[0x20];
9158
9159         u8         a_mac_control_frames_received_high[0x20];
9160
9161         u8         a_mac_control_frames_received_low[0x20];
9162
9163         u8         a_unsupported_opcodes_received_high[0x20];
9164
9165         u8         a_unsupported_opcodes_received_low[0x20];
9166
9167         u8         a_pause_mac_ctrl_frames_received_high[0x20];
9168
9169         u8         a_pause_mac_ctrl_frames_received_low[0x20];
9170
9171         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9172
9173         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9174
9175         u8         reserved_0[0x300];
9176 };
9177
9178 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9179         u8         dot3stats_alignment_errors_high[0x20];
9180
9181         u8         dot3stats_alignment_errors_low[0x20];
9182
9183         u8         dot3stats_fcs_errors_high[0x20];
9184
9185         u8         dot3stats_fcs_errors_low[0x20];
9186
9187         u8         dot3stats_single_collision_frames_high[0x20];
9188
9189         u8         dot3stats_single_collision_frames_low[0x20];
9190
9191         u8         dot3stats_multiple_collision_frames_high[0x20];
9192
9193         u8         dot3stats_multiple_collision_frames_low[0x20];
9194
9195         u8         dot3stats_sqe_test_errors_high[0x20];
9196
9197         u8         dot3stats_sqe_test_errors_low[0x20];
9198
9199         u8         dot3stats_deferred_transmissions_high[0x20];
9200
9201         u8         dot3stats_deferred_transmissions_low[0x20];
9202
9203         u8         dot3stats_late_collisions_high[0x20];
9204
9205         u8         dot3stats_late_collisions_low[0x20];
9206
9207         u8         dot3stats_excessive_collisions_high[0x20];
9208
9209         u8         dot3stats_excessive_collisions_low[0x20];
9210
9211         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9212
9213         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9214
9215         u8         dot3stats_carrier_sense_errors_high[0x20];
9216
9217         u8         dot3stats_carrier_sense_errors_low[0x20];
9218
9219         u8         dot3stats_frame_too_longs_high[0x20];
9220
9221         u8         dot3stats_frame_too_longs_low[0x20];
9222
9223         u8         dot3stats_internal_mac_receive_errors_high[0x20];
9224
9225         u8         dot3stats_internal_mac_receive_errors_low[0x20];
9226
9227         u8         dot3stats_symbol_errors_high[0x20];
9228
9229         u8         dot3stats_symbol_errors_low[0x20];
9230
9231         u8         dot3control_in_unknown_opcodes_high[0x20];
9232
9233         u8         dot3control_in_unknown_opcodes_low[0x20];
9234
9235         u8         dot3in_pause_frames_high[0x20];
9236
9237         u8         dot3in_pause_frames_low[0x20];
9238
9239         u8         dot3out_pause_frames_high[0x20];
9240
9241         u8         dot3out_pause_frames_low[0x20];
9242
9243         u8         reserved_0[0x3c0];
9244 };
9245
9246 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9247         u8         if_in_octets_high[0x20];
9248
9249         u8         if_in_octets_low[0x20];
9250
9251         u8         if_in_ucast_pkts_high[0x20];
9252
9253         u8         if_in_ucast_pkts_low[0x20];
9254
9255         u8         if_in_discards_high[0x20];
9256
9257         u8         if_in_discards_low[0x20];
9258
9259         u8         if_in_errors_high[0x20];
9260
9261         u8         if_in_errors_low[0x20];
9262
9263         u8         if_in_unknown_protos_high[0x20];
9264
9265         u8         if_in_unknown_protos_low[0x20];
9266
9267         u8         if_out_octets_high[0x20];
9268
9269         u8         if_out_octets_low[0x20];
9270
9271         u8         if_out_ucast_pkts_high[0x20];
9272
9273         u8         if_out_ucast_pkts_low[0x20];
9274
9275         u8         if_out_discards_high[0x20];
9276
9277         u8         if_out_discards_low[0x20];
9278
9279         u8         if_out_errors_high[0x20];
9280
9281         u8         if_out_errors_low[0x20];
9282
9283         u8         if_in_multicast_pkts_high[0x20];
9284
9285         u8         if_in_multicast_pkts_low[0x20];
9286
9287         u8         if_in_broadcast_pkts_high[0x20];
9288
9289         u8         if_in_broadcast_pkts_low[0x20];
9290
9291         u8         if_out_multicast_pkts_high[0x20];
9292
9293         u8         if_out_multicast_pkts_low[0x20];
9294
9295         u8         if_out_broadcast_pkts_high[0x20];
9296
9297         u8         if_out_broadcast_pkts_low[0x20];
9298
9299         u8         reserved_0[0x480];
9300 };
9301
9302 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9303         u8         ether_stats_drop_events_high[0x20];
9304
9305         u8         ether_stats_drop_events_low[0x20];
9306
9307         u8         ether_stats_octets_high[0x20];
9308
9309         u8         ether_stats_octets_low[0x20];
9310
9311         u8         ether_stats_pkts_high[0x20];
9312
9313         u8         ether_stats_pkts_low[0x20];
9314
9315         u8         ether_stats_broadcast_pkts_high[0x20];
9316
9317         u8         ether_stats_broadcast_pkts_low[0x20];
9318
9319         u8         ether_stats_multicast_pkts_high[0x20];
9320
9321         u8         ether_stats_multicast_pkts_low[0x20];
9322
9323         u8         ether_stats_crc_align_errors_high[0x20];
9324
9325         u8         ether_stats_crc_align_errors_low[0x20];
9326
9327         u8         ether_stats_undersize_pkts_high[0x20];
9328
9329         u8         ether_stats_undersize_pkts_low[0x20];
9330
9331         u8         ether_stats_oversize_pkts_high[0x20];
9332
9333         u8         ether_stats_oversize_pkts_low[0x20];
9334
9335         u8         ether_stats_fragments_high[0x20];
9336
9337         u8         ether_stats_fragments_low[0x20];
9338
9339         u8         ether_stats_jabbers_high[0x20];
9340
9341         u8         ether_stats_jabbers_low[0x20];
9342
9343         u8         ether_stats_collisions_high[0x20];
9344
9345         u8         ether_stats_collisions_low[0x20];
9346
9347         u8         ether_stats_pkts64octets_high[0x20];
9348
9349         u8         ether_stats_pkts64octets_low[0x20];
9350
9351         u8         ether_stats_pkts65to127octets_high[0x20];
9352
9353         u8         ether_stats_pkts65to127octets_low[0x20];
9354
9355         u8         ether_stats_pkts128to255octets_high[0x20];
9356
9357         u8         ether_stats_pkts128to255octets_low[0x20];
9358
9359         u8         ether_stats_pkts256to511octets_high[0x20];
9360
9361         u8         ether_stats_pkts256to511octets_low[0x20];
9362
9363         u8         ether_stats_pkts512to1023octets_high[0x20];
9364
9365         u8         ether_stats_pkts512to1023octets_low[0x20];
9366
9367         u8         ether_stats_pkts1024to1518octets_high[0x20];
9368
9369         u8         ether_stats_pkts1024to1518octets_low[0x20];
9370
9371         u8         ether_stats_pkts1519to2047octets_high[0x20];
9372
9373         u8         ether_stats_pkts1519to2047octets_low[0x20];
9374
9375         u8         ether_stats_pkts2048to4095octets_high[0x20];
9376
9377         u8         ether_stats_pkts2048to4095octets_low[0x20];
9378
9379         u8         ether_stats_pkts4096to8191octets_high[0x20];
9380
9381         u8         ether_stats_pkts4096to8191octets_low[0x20];
9382
9383         u8         ether_stats_pkts8192to10239octets_high[0x20];
9384
9385         u8         ether_stats_pkts8192to10239octets_low[0x20];
9386
9387         u8         reserved_0[0x280];
9388 };
9389
9390 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9391         u8         symbol_error_counter[0x10];
9392         u8         link_error_recovery_counter[0x8];
9393         u8         link_downed_counter[0x8];
9394
9395         u8         port_rcv_errors[0x10];
9396         u8         port_rcv_remote_physical_errors[0x10];
9397
9398         u8         port_rcv_switch_relay_errors[0x10];
9399         u8         port_xmit_discards[0x10];
9400
9401         u8         port_xmit_constraint_errors[0x8];
9402         u8         port_rcv_constraint_errors[0x8];
9403         u8         reserved_0[0x8];
9404         u8         local_link_integrity_errors[0x4];
9405         u8         excessive_buffer_overrun_errors[0x4];
9406
9407         u8         reserved_1[0x10];
9408         u8         vl_15_dropped[0x10];
9409
9410         u8         port_xmit_data[0x20];
9411
9412         u8         port_rcv_data[0x20];
9413
9414         u8         port_xmit_pkts[0x20];
9415
9416         u8         port_rcv_pkts[0x20];
9417
9418         u8         port_xmit_wait[0x20];
9419
9420         u8         reserved_2[0x680];
9421 };
9422
9423 struct mlx5_ifc_trc_tlb_reg_bits {
9424         u8         reserved_0[0x80];
9425
9426         u8         tlb_addr[0][0x40];
9427 };
9428
9429 struct mlx5_ifc_trc_read_fifo_reg_bits {
9430         u8         reserved_0[0x10];
9431         u8         requested_event_num[0x10];
9432
9433         u8         reserved_1[0x20];
9434
9435         u8         reserved_2[0x10];
9436         u8         acual_event_num[0x10];
9437
9438         u8         reserved_3[0x20];
9439
9440         u8         event[0][0x40];
9441 };
9442
9443 struct mlx5_ifc_trc_lock_reg_bits {
9444         u8         reserved_0[0x1f];
9445         u8         lock[0x1];
9446
9447         u8         reserved_1[0x60];
9448 };
9449
9450 struct mlx5_ifc_trc_filter_reg_bits {
9451         u8         status[0x1];
9452         u8         reserved_0[0xf];
9453         u8         filter_index[0x10];
9454
9455         u8         reserved_1[0x20];
9456
9457         u8         filter_val[0x20];
9458
9459         u8         reserved_2[0x1a0];
9460 };
9461
9462 struct mlx5_ifc_trc_event_reg_bits {
9463         u8         status[0x1];
9464         u8         reserved_0[0xf];
9465         u8         event_index[0x10];
9466
9467         u8         reserved_1[0x20];
9468
9469         u8         event_id[0x20];
9470
9471         u8         event_selector_val[0x10];
9472         u8         event_selector_size[0x10];
9473
9474         u8         reserved_2[0x180];
9475 };
9476
9477 struct mlx5_ifc_trc_conf_reg_bits {
9478         u8         limit_en[0x1];
9479         u8         reserved_0[0x3];
9480         u8         dump_mode[0x4];
9481         u8         reserved_1[0x15];
9482         u8         state[0x3];
9483
9484         u8         reserved_2[0x20];
9485
9486         u8         limit_event_index[0x20];
9487
9488         u8         mkey[0x20];
9489
9490         u8         fifo_ready_ev_num[0x20];
9491
9492         u8         reserved_3[0x160];
9493 };
9494
9495 struct mlx5_ifc_trc_cap_reg_bits {
9496         u8         reserved_0[0x18];
9497         u8         dump_mode[0x8];
9498
9499         u8         reserved_1[0x20];
9500
9501         u8         num_of_events[0x10];
9502         u8         num_of_filters[0x10];
9503
9504         u8         fifo_size[0x20];
9505
9506         u8         tlb_size[0x10];
9507         u8         event_size[0x10];
9508
9509         u8         reserved_2[0x160];
9510 };
9511
9512 struct mlx5_ifc_set_node_in_bits {
9513         u8         node_description[64][0x8];
9514 };
9515
9516 struct mlx5_ifc_register_power_settings_bits {
9517         u8         reserved_0[0x18];
9518         u8         power_settings_level[0x8];
9519
9520         u8         reserved_1[0x60];
9521 };
9522
9523 struct mlx5_ifc_register_host_endianess_bits {
9524         u8         he[0x1];
9525         u8         reserved_0[0x1f];
9526
9527         u8         reserved_1[0x60];
9528 };
9529
9530 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9531         u8         physical_address[0x40];
9532 };
9533
9534 struct mlx5_ifc_qtct_reg_bits {
9535         u8         operation_type[0x2];
9536         u8         cap_local_admin[0x1];
9537         u8         cap_remote_admin[0x1];
9538         u8         reserved_0[0x4];
9539         u8         port_number[0x8];
9540         u8         reserved_1[0xd];
9541         u8         prio[0x3];
9542
9543         u8         reserved_2[0x1d];
9544         u8         tclass[0x3];
9545 };
9546
9547 struct mlx5_ifc_qpdp_reg_bits {
9548         u8         reserved_0[0x8];
9549         u8         port_number[0x8];
9550         u8         reserved_1[0x10];
9551
9552         u8         reserved_2[0x1d];
9553         u8         pprio[0x3];
9554 };
9555
9556 struct mlx5_ifc_port_info_ro_fields_param_bits {
9557         u8         reserved_0[0x8];
9558         u8         port[0x8];
9559         u8         max_gid[0x10];
9560
9561         u8         reserved_1[0x20];
9562
9563         u8         port_guid[0x40];
9564 };
9565
9566 struct mlx5_ifc_nvqc_reg_bits {
9567         u8         type[0x20];
9568
9569         u8         reserved_0[0x18];
9570         u8         version[0x4];
9571         u8         reserved_1[0x2];
9572         u8         support_wr[0x1];
9573         u8         support_rd[0x1];
9574 };
9575
9576 struct mlx5_ifc_nvia_reg_bits {
9577         u8         reserved_0[0x1d];
9578         u8         target[0x3];
9579
9580         u8         reserved_1[0x20];
9581 };
9582
9583 struct mlx5_ifc_nvdi_reg_bits {
9584         struct mlx5_ifc_config_item_bits configuration_item_header;
9585 };
9586
9587 struct mlx5_ifc_nvda_reg_bits {
9588         struct mlx5_ifc_config_item_bits configuration_item_header;
9589
9590         u8         configuration_item_data[0x20];
9591 };
9592
9593 struct mlx5_ifc_node_info_ro_fields_param_bits {
9594         u8         system_image_guid[0x40];
9595
9596         u8         reserved_0[0x40];
9597
9598         u8         node_guid[0x40];
9599
9600         u8         reserved_1[0x10];
9601         u8         max_pkey[0x10];
9602
9603         u8         reserved_2[0x20];
9604 };
9605
9606 struct mlx5_ifc_ets_tcn_config_reg_bits {
9607         u8         g[0x1];
9608         u8         b[0x1];
9609         u8         r[0x1];
9610         u8         reserved_0[0x9];
9611         u8         group[0x4];
9612         u8         reserved_1[0x9];
9613         u8         bw_allocation[0x7];
9614
9615         u8         reserved_2[0xc];
9616         u8         max_bw_units[0x4];
9617         u8         reserved_3[0x8];
9618         u8         max_bw_value[0x8];
9619 };
9620
9621 struct mlx5_ifc_ets_global_config_reg_bits {
9622         u8         reserved_0[0x2];
9623         u8         r[0x1];
9624         u8         reserved_1[0x1d];
9625
9626         u8         reserved_2[0xc];
9627         u8         max_bw_units[0x4];
9628         u8         reserved_3[0x8];
9629         u8         max_bw_value[0x8];
9630 };
9631
9632 struct mlx5_ifc_qetc_reg_bits {
9633         u8                                         reserved_at_0[0x8];
9634         u8                                         port_number[0x8];
9635         u8                                         reserved_at_10[0x30];
9636
9637         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9638         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9639 };
9640
9641 struct mlx5_ifc_nodnic_mac_filters_bits {
9642         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9643
9644         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9645
9646         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9647
9648         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9649
9650         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9651
9652         u8         reserved_0[0xc0];
9653 };
9654
9655 struct mlx5_ifc_nodnic_gid_filters_bits {
9656         u8         mgid_filter0[16][0x8];
9657
9658         u8         mgid_filter1[16][0x8];
9659
9660         u8         mgid_filter2[16][0x8];
9661
9662         u8         mgid_filter3[16][0x8];
9663 };
9664
9665 enum {
9666         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9667         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9668 };
9669
9670 enum {
9671         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9672         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9673 };
9674
9675 struct mlx5_ifc_nodnic_config_reg_bits {
9676         u8         no_dram_nic_revision[0x8];
9677         u8         hardware_format[0x8];
9678         u8         support_receive_filter[0x1];
9679         u8         support_promisc_filter[0x1];
9680         u8         support_promisc_multicast_filter[0x1];
9681         u8         reserved_0[0x2];
9682         u8         log_working_buffer_size[0x3];
9683         u8         log_pkey_table_size[0x4];
9684         u8         reserved_1[0x3];
9685         u8         num_ports[0x1];
9686
9687         u8         reserved_2[0x2];
9688         u8         log_max_ring_size[0x6];
9689         u8         reserved_3[0x18];
9690
9691         u8         lkey[0x20];
9692
9693         u8         cqe_format[0x4];
9694         u8         reserved_4[0x1c];
9695
9696         u8         node_guid[0x40];
9697
9698         u8         reserved_5[0x740];
9699
9700         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9701
9702         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9703 };
9704
9705 struct mlx5_ifc_vlan_layout_bits {
9706         u8         reserved_0[0x14];
9707         u8         vlan[0xc];
9708
9709         u8         reserved_1[0x20];
9710 };
9711
9712 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9713         u8         reserved_0[0x20];
9714
9715         u8         mkey[0x20];
9716
9717         u8         addressh_63_32[0x20];
9718
9719         u8         addressl_31_0[0x20];
9720 };
9721
9722 struct mlx5_ifc_ud_adrs_vector_bits {
9723         u8         dc_key[0x40];
9724
9725         u8         ext[0x1];
9726         u8         reserved_0[0x7];
9727         u8         destination_qp_dct[0x18];
9728
9729         u8         static_rate[0x4];
9730         u8         sl_eth_prio[0x4];
9731         u8         fl[0x1];
9732         u8         mlid[0x7];
9733         u8         rlid_udp_sport[0x10];
9734
9735         u8         reserved_1[0x20];
9736
9737         u8         rmac_47_16[0x20];
9738
9739         u8         rmac_15_0[0x10];
9740         u8         tclass[0x8];
9741         u8         hop_limit[0x8];
9742
9743         u8         reserved_2[0x1];
9744         u8         grh[0x1];
9745         u8         reserved_3[0x2];
9746         u8         src_addr_index[0x8];
9747         u8         flow_label[0x14];
9748
9749         u8         rgid_rip[16][0x8];
9750 };
9751
9752 struct mlx5_ifc_port_module_event_bits {
9753         u8         reserved_0[0x8];
9754         u8         module[0x8];
9755         u8         reserved_1[0xc];
9756         u8         module_status[0x4];
9757
9758         u8         reserved_2[0x14];
9759         u8         error_type[0x4];
9760         u8         reserved_3[0x8];
9761
9762         u8         reserved_4[0xa0];
9763 };
9764
9765 struct mlx5_ifc_icmd_control_bits {
9766         u8         opcode[0x10];
9767         u8         status[0x8];
9768         u8         reserved_0[0x7];
9769         u8         busy[0x1];
9770 };
9771
9772 struct mlx5_ifc_eqe_bits {
9773         u8         reserved_0[0x8];
9774         u8         event_type[0x8];
9775         u8         reserved_1[0x8];
9776         u8         event_sub_type[0x8];
9777
9778         u8         reserved_2[0xe0];
9779
9780         union mlx5_ifc_event_auto_bits event_data;
9781
9782         u8         reserved_3[0x10];
9783         u8         signature[0x8];
9784         u8         reserved_4[0x7];
9785         u8         owner[0x1];
9786 };
9787
9788 enum {
9789         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9790 };
9791
9792 struct mlx5_ifc_cmd_queue_entry_bits {
9793         u8         type[0x8];
9794         u8         reserved_0[0x18];
9795
9796         u8         input_length[0x20];
9797
9798         u8         input_mailbox_pointer_63_32[0x20];
9799
9800         u8         input_mailbox_pointer_31_9[0x17];
9801         u8         reserved_1[0x9];
9802
9803         u8         command_input_inline_data[16][0x8];
9804
9805         u8         command_output_inline_data[16][0x8];
9806
9807         u8         output_mailbox_pointer_63_32[0x20];
9808
9809         u8         output_mailbox_pointer_31_9[0x17];
9810         u8         reserved_2[0x9];
9811
9812         u8         output_length[0x20];
9813
9814         u8         token[0x8];
9815         u8         signature[0x8];
9816         u8         reserved_3[0x8];
9817         u8         status[0x7];
9818         u8         ownership[0x1];
9819 };
9820
9821 struct mlx5_ifc_cmd_out_bits {
9822         u8         status[0x8];
9823         u8         reserved_0[0x18];
9824
9825         u8         syndrome[0x20];
9826
9827         u8         command_output[0x20];
9828 };
9829
9830 struct mlx5_ifc_cmd_in_bits {
9831         u8         opcode[0x10];
9832         u8         reserved_0[0x10];
9833
9834         u8         reserved_1[0x10];
9835         u8         op_mod[0x10];
9836
9837         u8         command[0][0x20];
9838 };
9839
9840 struct mlx5_ifc_cmd_if_box_bits {
9841         u8         mailbox_data[512][0x8];
9842
9843         u8         reserved_0[0x180];
9844
9845         u8         next_pointer_63_32[0x20];
9846
9847         u8         next_pointer_31_10[0x16];
9848         u8         reserved_1[0xa];
9849
9850         u8         block_number[0x20];
9851
9852         u8         reserved_2[0x8];
9853         u8         token[0x8];
9854         u8         ctrl_signature[0x8];
9855         u8         signature[0x8];
9856 };
9857
9858 struct mlx5_ifc_mtt_bits {
9859         u8         ptag_63_32[0x20];
9860
9861         u8         ptag_31_8[0x18];
9862         u8         reserved_0[0x6];
9863         u8         wr_en[0x1];
9864         u8         rd_en[0x1];
9865 };
9866
9867 struct mlx5_ifc_tls_progress_params_bits {
9868         u8         valid[0x1];
9869         u8         reserved_at_1[0x7];
9870         u8         pd[0x18];
9871
9872         u8         next_record_tcp_sn[0x20];
9873
9874         u8         hw_resync_tcp_sn[0x20];
9875
9876         u8         record_tracker_state[0x2];
9877         u8         auth_state[0x2];
9878         u8         reserved_at_64[0x4];
9879         u8         hw_offset_record_number[0x18];
9880 };
9881
9882 struct mlx5_ifc_tls_static_params_bits {
9883         u8         const_2[0x2];
9884         u8         tls_version[0x4];
9885         u8         const_1[0x2];
9886         u8         reserved_at_8[0x14];
9887         u8         encryption_standard[0x4];
9888
9889         u8         reserved_at_20[0x20];
9890
9891         u8         initial_record_number[0x40];
9892
9893         u8         resync_tcp_sn[0x20];
9894
9895         u8         gcm_iv[0x20];
9896
9897         u8         implicit_iv[0x40];
9898
9899         u8         reserved_at_100[0x8];
9900         u8         dek_index[0x18];
9901
9902         u8         reserved_at_120[0xe0];
9903 };
9904
9905 /* Vendor Specific Capabilities, VSC */
9906 enum {
9907         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9908         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9909         MLX5_VSC_DOMAIN_SCAN_CRSPACE            = 0x7,
9910         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9911 };
9912
9913 struct mlx5_ifc_vendor_specific_cap_bits {
9914         u8         type[0x8];
9915         u8         length[0x8];
9916         u8         next_pointer[0x8];
9917         u8         capability_id[0x8];
9918
9919         u8         status[0x3];
9920         u8         reserved_0[0xd];
9921         u8         space[0x10];
9922
9923         u8         counter[0x20];
9924
9925         u8         semaphore[0x20];
9926
9927         u8         flag[0x1];
9928         u8         reserved_1[0x1];
9929         u8         address[0x1e];
9930
9931         u8         data[0x20];
9932 };
9933
9934 struct mlx5_ifc_vsc_space_bits {
9935         u8 status[0x3];
9936         u8 reserved0[0xd];
9937         u8 space[0x10];
9938 };
9939
9940 struct mlx5_ifc_vsc_addr_bits {
9941         u8 flag[0x1];
9942         u8 reserved0[0x1];
9943         u8 address[0x1e];
9944 };
9945
9946 enum {
9947         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9948         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9949         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9950 };
9951
9952 enum {
9953         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9954         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9955         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9956 };
9957
9958 enum {
9959         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9960         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9961         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9962         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9963         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9964         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9965         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9966         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9967         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9968         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9969         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9970 };
9971
9972 struct mlx5_ifc_initial_seg_bits {
9973         u8         fw_rev_minor[0x10];
9974         u8         fw_rev_major[0x10];
9975
9976         u8         cmd_interface_rev[0x10];
9977         u8         fw_rev_subminor[0x10];
9978
9979         u8         reserved_0[0x40];
9980
9981         u8         cmdq_phy_addr_63_32[0x20];
9982
9983         u8         cmdq_phy_addr_31_12[0x14];
9984         u8         reserved_1[0x2];
9985         u8         nic_interface[0x2];
9986         u8         log_cmdq_size[0x4];
9987         u8         log_cmdq_stride[0x4];
9988
9989         u8         command_doorbell_vector[0x20];
9990
9991         u8         reserved_2[0xf00];
9992
9993         u8         initializing[0x1];
9994         u8         reserved_3[0x4];
9995         u8         nic_interface_supported[0x3];
9996         u8         reserved_4[0x18];
9997
9998         struct mlx5_ifc_health_buffer_bits health_buffer;
9999
10000         u8         no_dram_nic_offset[0x20];
10001
10002         u8         reserved_5[0x6de0];
10003
10004         u8         internal_timer_h[0x20];
10005
10006         u8         internal_timer_l[0x20];
10007
10008         u8         reserved_6[0x20];
10009
10010         u8         reserved_7[0x1f];
10011         u8         clear_int[0x1];
10012
10013         u8         health_syndrome[0x8];
10014         u8         health_counter[0x18];
10015
10016         u8         reserved_8[0x17fc0];
10017 };
10018
10019 union mlx5_ifc_icmd_interface_document_bits {
10020         struct mlx5_ifc_fw_version_bits fw_version;
10021         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10022         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10023         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10024         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10025         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10026         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10027         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10028         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10029         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10030         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10031         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10032         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10033         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10034         u8         reserved_0[0x42c0];
10035 };
10036
10037 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10038         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10039         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10040         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10041         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10042         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10043         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10044         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10045         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10046         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10047         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10048         u8         reserved_0[0x7c0];
10049 };
10050
10051 struct mlx5_ifc_ppcnt_reg_bits {
10052         u8         swid[0x8];
10053         u8         local_port[0x8];
10054         u8         pnat[0x2];
10055         u8         reserved_0[0x8];
10056         u8         grp[0x6];
10057
10058         u8         clr[0x1];
10059         u8         reserved_1[0x1c];
10060         u8         prio_tc[0x3];
10061
10062         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10063 };
10064
10065 struct mlx5_ifc_pcie_lanes_counters_bits {
10066         u8         life_time_counter_high[0x20];
10067
10068         u8         life_time_counter_low[0x20];
10069
10070         u8         error_counter_lane0[0x20];
10071
10072         u8         error_counter_lane1[0x20];
10073
10074         u8         error_counter_lane2[0x20];
10075
10076         u8         error_counter_lane3[0x20];
10077
10078         u8         error_counter_lane4[0x20];
10079
10080         u8         error_counter_lane5[0x20];
10081
10082         u8         error_counter_lane6[0x20];
10083
10084         u8         error_counter_lane7[0x20];
10085
10086         u8         error_counter_lane8[0x20];
10087
10088         u8         error_counter_lane9[0x20];
10089
10090         u8         error_counter_lane10[0x20];
10091
10092         u8         error_counter_lane11[0x20];
10093
10094         u8         error_counter_lane12[0x20];
10095
10096         u8         error_counter_lane13[0x20];
10097
10098         u8         error_counter_lane14[0x20];
10099
10100         u8         error_counter_lane15[0x20];
10101
10102         u8         reserved_at_240[0x580];
10103 };
10104
10105 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10106         u8         reserved_at_0[0x40];
10107
10108         u8         error_counter_lane0[0x20];
10109
10110         u8         error_counter_lane1[0x20];
10111
10112         u8         error_counter_lane2[0x20];
10113
10114         u8         error_counter_lane3[0x20];
10115
10116         u8         error_counter_lane4[0x20];
10117
10118         u8         error_counter_lane5[0x20];
10119
10120         u8         error_counter_lane6[0x20];
10121
10122         u8         error_counter_lane7[0x20];
10123
10124         u8         error_counter_lane8[0x20];
10125
10126         u8         error_counter_lane9[0x20];
10127
10128         u8         error_counter_lane10[0x20];
10129
10130         u8         error_counter_lane11[0x20];
10131
10132         u8         error_counter_lane12[0x20];
10133
10134         u8         error_counter_lane13[0x20];
10135
10136         u8         error_counter_lane14[0x20];
10137
10138         u8         error_counter_lane15[0x20];
10139
10140         u8         reserved_at_240[0x580];
10141 };
10142
10143 struct mlx5_ifc_pcie_perf_counters_bits {
10144         u8         life_time_counter_high[0x20];
10145
10146         u8         life_time_counter_low[0x20];
10147
10148         u8         rx_errors[0x20];
10149
10150         u8         tx_errors[0x20];
10151
10152         u8         l0_to_recovery_eieos[0x20];
10153
10154         u8         l0_to_recovery_ts[0x20];
10155
10156         u8         l0_to_recovery_framing[0x20];
10157
10158         u8         l0_to_recovery_retrain[0x20];
10159
10160         u8         crc_error_dllp[0x20];
10161
10162         u8         crc_error_tlp[0x20];
10163
10164         u8         tx_overflow_buffer_pkt[0x40];
10165
10166         u8         outbound_stalled_reads[0x20];
10167
10168         u8         outbound_stalled_writes[0x20];
10169
10170         u8         outbound_stalled_reads_events[0x20];
10171
10172         u8         outbound_stalled_writes_events[0x20];
10173
10174         u8         tx_overflow_buffer_marked_pkt[0x40];
10175
10176         u8         reserved_at_240[0x580];
10177 };
10178
10179 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10180         u8         reserved_at_0[0x40];
10181
10182         u8         rx_errors[0x20];
10183
10184         u8         tx_errors[0x20];
10185
10186         u8         reserved_at_80[0xc0];
10187
10188         u8         tx_overflow_buffer_pkt[0x40];
10189
10190         u8         outbound_stalled_reads[0x20];
10191
10192         u8         outbound_stalled_writes[0x20];
10193
10194         u8         outbound_stalled_reads_events[0x20];
10195
10196         u8         outbound_stalled_writes_events[0x20];
10197
10198         u8         tx_overflow_buffer_marked_pkt[0x40];
10199
10200         u8         reserved_at_240[0x580];
10201 };
10202
10203 struct mlx5_ifc_pcie_timers_states_bits {
10204         u8         life_time_counter_high[0x20];
10205
10206         u8         life_time_counter_low[0x20];
10207
10208         u8         time_to_boot_image_start[0x20];
10209
10210         u8         time_to_link_image[0x20];
10211
10212         u8         calibration_time[0x20];
10213
10214         u8         time_to_first_perst[0x20];
10215
10216         u8         time_to_detect_state[0x20];
10217
10218         u8         time_to_l0[0x20];
10219
10220         u8         time_to_crs_en[0x20];
10221
10222         u8         time_to_plastic_image_start[0x20];
10223
10224         u8         time_to_iron_image_start[0x20];
10225
10226         u8         perst_handler[0x20];
10227
10228         u8         times_in_l1[0x20];
10229
10230         u8         times_in_l23[0x20];
10231
10232         u8         dl_down[0x20];
10233
10234         u8         config_cycle1usec[0x20];
10235
10236         u8         config_cycle2to7usec[0x20];
10237
10238         u8         config_cycle8to15usec[0x20];
10239
10240         u8         config_cycle16to63usec[0x20];
10241
10242         u8         config_cycle64usec[0x20];
10243
10244         u8         correctable_err_msg_sent[0x20];
10245
10246         u8         non_fatal_err_msg_sent[0x20];
10247
10248         u8         fatal_err_msg_sent[0x20];
10249
10250         u8         reserved_at_2e0[0x4e0];
10251 };
10252
10253 struct mlx5_ifc_pcie_timers_states_ext_bits {
10254         u8         reserved_at_0[0x40];
10255
10256         u8         time_to_boot_image_start[0x20];
10257
10258         u8         time_to_link_image[0x20];
10259
10260         u8         calibration_time[0x20];
10261
10262         u8         time_to_first_perst[0x20];
10263
10264         u8         time_to_detect_state[0x20];
10265
10266         u8         time_to_l0[0x20];
10267
10268         u8         time_to_crs_en[0x20];
10269
10270         u8         time_to_plastic_image_start[0x20];
10271
10272         u8         time_to_iron_image_start[0x20];
10273
10274         u8         perst_handler[0x20];
10275
10276         u8         times_in_l1[0x20];
10277
10278         u8         times_in_l23[0x20];
10279
10280         u8         dl_down[0x20];
10281
10282         u8         config_cycle1usec[0x20];
10283
10284         u8         config_cycle2to7usec[0x20];
10285
10286         u8         config_cycle8to15usec[0x20];
10287
10288         u8         config_cycle16to63usec[0x20];
10289
10290         u8         config_cycle64usec[0x20];
10291
10292         u8         correctable_err_msg_sent[0x20];
10293
10294         u8         non_fatal_err_msg_sent[0x20];
10295
10296         u8         fatal_err_msg_sent[0x20];
10297
10298         u8         reserved_at_2e0[0x4e0];
10299 };
10300
10301 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10302         struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10303         struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10304         struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10305         u8         reserved_at_0[0x7c0];
10306 };
10307
10308 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10309         struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10310         struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10311         struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10312         u8         reserved_at_0[0x7c0];
10313 };
10314
10315 struct mlx5_ifc_mpcnt_reg_bits {
10316         u8         reserved_at_0[0x2];
10317         u8         depth[0x6];
10318         u8         pcie_index[0x8];
10319         u8         node[0x8];
10320         u8         reserved_at_18[0x2];
10321         u8         grp[0x6];
10322
10323         u8         clr[0x1];
10324         u8         reserved_at_21[0x1f];
10325
10326         union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10327 };
10328
10329 struct mlx5_ifc_mpcnt_reg_ext_bits {
10330         u8         reserved_at_0[0x2];
10331         u8         depth[0x6];
10332         u8         pcie_index[0x8];
10333         u8         node[0x8];
10334         u8         reserved_at_18[0x2];
10335         u8         grp[0x6];
10336
10337         u8         clr[0x1];
10338         u8         reserved_at_21[0x1f];
10339
10340         union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10341 };
10342
10343 enum {
10344         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10345         MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10346         MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10347         MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10348 };
10349
10350 struct mlx5_ifc_mpein_reg_bits {
10351         u8         reserved_at_0[0x2];
10352         u8         depth[0x6];
10353         u8         pcie_index[0x8];
10354         u8         node[0x8];
10355         u8         reserved_at_18[0x8];
10356
10357         u8         capability_mask[0x20];
10358
10359         u8         reserved_at_40[0x8];
10360         u8         link_width_enabled[0x8];
10361         u8         link_speed_enabled[0x10];
10362
10363         u8         lane0_physical_position[0x8];
10364         u8         link_width_active[0x8];
10365         u8         link_speed_active[0x10];
10366
10367         u8         num_of_pfs[0x10];
10368         u8         num_of_vfs[0x10];
10369
10370         u8         bdf0[0x10];
10371         u8         reserved_at_b0[0x10];
10372
10373         u8         max_read_request_size[0x4];
10374         u8         max_payload_size[0x4];
10375         u8         reserved_at_c8[0x5];
10376         u8         pwr_status[0x3];
10377         u8         port_type[0x4];
10378         u8         reserved_at_d4[0xb];
10379         u8         lane_reversal[0x1];
10380
10381         u8         reserved_at_e0[0x14];
10382         u8         pci_power[0xc];
10383
10384         u8         reserved_at_100[0x20];
10385
10386         u8         device_status[0x10];
10387         u8         port_state[0x8];
10388         u8         reserved_at_138[0x8];
10389
10390         u8         reserved_at_140[0x10];
10391         u8         receiver_detect_result[0x10];
10392
10393         u8         reserved_at_160[0x20];
10394 };
10395
10396 struct mlx5_ifc_mpein_reg_ext_bits {
10397         u8         reserved_at_0[0x2];
10398         u8         depth[0x6];
10399         u8         pcie_index[0x8];
10400         u8         node[0x8];
10401         u8         reserved_at_18[0x8];
10402
10403         u8         reserved_at_20[0x20];
10404
10405         u8         reserved_at_40[0x8];
10406         u8         link_width_enabled[0x8];
10407         u8         link_speed_enabled[0x10];
10408
10409         u8         lane0_physical_position[0x8];
10410         u8         link_width_active[0x8];
10411         u8         link_speed_active[0x10];
10412
10413         u8         num_of_pfs[0x10];
10414         u8         num_of_vfs[0x10];
10415
10416         u8         bdf0[0x10];
10417         u8         reserved_at_b0[0x10];
10418
10419         u8         max_read_request_size[0x4];
10420         u8         max_payload_size[0x4];
10421         u8         reserved_at_c8[0x5];
10422         u8         pwr_status[0x3];
10423         u8         port_type[0x4];
10424         u8         reserved_at_d4[0xb];
10425         u8         lane_reversal[0x1];
10426 };
10427
10428 struct mlx5_ifc_mcqi_cap_bits {
10429         u8         supported_info_bitmask[0x20];
10430
10431         u8         component_size[0x20];
10432
10433         u8         max_component_size[0x20];
10434
10435         u8         log_mcda_word_size[0x4];
10436         u8         reserved_at_64[0xc];
10437         u8         mcda_max_write_size[0x10];
10438
10439         u8         rd_en[0x1];
10440         u8         reserved_at_81[0x1];
10441         u8         match_chip_id[0x1];
10442         u8         match_psid[0x1];
10443         u8         check_user_timestamp[0x1];
10444         u8         match_base_guid_mac[0x1];
10445         u8         reserved_at_86[0x1a];
10446 };
10447
10448 struct mlx5_ifc_mcqi_reg_bits {
10449         u8         read_pending_component[0x1];
10450         u8         reserved_at_1[0xf];
10451         u8         component_index[0x10];
10452
10453         u8         reserved_at_20[0x20];
10454
10455         u8         reserved_at_40[0x1b];
10456         u8         info_type[0x5];
10457
10458         u8         info_size[0x20];
10459
10460         u8         offset[0x20];
10461
10462         u8         reserved_at_a0[0x10];
10463         u8         data_size[0x10];
10464
10465         u8         data[0][0x20];
10466 };
10467
10468 struct mlx5_ifc_mcc_reg_bits {
10469         u8         reserved_at_0[0x4];
10470         u8         time_elapsed_since_last_cmd[0xc];
10471         u8         reserved_at_10[0x8];
10472         u8         instruction[0x8];
10473
10474         u8         reserved_at_20[0x10];
10475         u8         component_index[0x10];
10476
10477         u8         reserved_at_40[0x8];
10478         u8         update_handle[0x18];
10479
10480         u8         handle_owner_type[0x4];
10481         u8         handle_owner_host_id[0x4];
10482         u8         reserved_at_68[0x1];
10483         u8         control_progress[0x7];
10484         u8         error_code[0x8];
10485         u8         reserved_at_78[0x4];
10486         u8         control_state[0x4];
10487
10488         u8         component_size[0x20];
10489
10490         u8         reserved_at_a0[0x60];
10491 };
10492
10493 struct mlx5_ifc_mcda_reg_bits {
10494         u8         reserved_at_0[0x8];
10495         u8         update_handle[0x18];
10496
10497         u8         offset[0x20];
10498
10499         u8         reserved_at_40[0x10];
10500         u8         size[0x10];
10501
10502         u8         reserved_at_60[0x20];
10503
10504         u8         data[0][0x20];
10505 };
10506
10507 union mlx5_ifc_ports_control_registers_document_bits {
10508         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10509         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10510         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10511         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10512         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10513         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10514         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10515         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10516         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10517         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10518         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10519         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10520         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10521         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10522         struct mlx5_ifc_paos_reg_bits paos_reg;
10523         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10524         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10525         struct mlx5_ifc_peir_reg_bits peir_reg;
10526         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10527         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10528         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10529         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10530         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10531         struct mlx5_ifc_phrr_reg_bits phrr_reg;
10532         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10533         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10534         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10535         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10536         struct mlx5_ifc_plib_reg_bits plib_reg;
10537         struct mlx5_ifc_pll_status_data_bits pll_status_data;
10538         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10539         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10540         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10541         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10542         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10543         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10544         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10545         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10546         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10547         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10548         struct mlx5_ifc_ppll_reg_bits ppll_reg;
10549         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10550         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10551         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10552         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10553         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10554         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10555         struct mlx5_ifc_pude_reg_bits pude_reg;
10556         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10557         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10558         struct mlx5_ifc_slrp_reg_bits slrp_reg;
10559         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10560         u8         reserved_0[0x7880];
10561 };
10562
10563 union mlx5_ifc_debug_enhancements_document_bits {
10564         struct mlx5_ifc_health_buffer_bits health_buffer;
10565         u8         reserved_0[0x200];
10566 };
10567
10568 union mlx5_ifc_no_dram_nic_document_bits {
10569         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10570         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10571         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10572         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10573         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10574         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10575         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10576         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10577         u8         reserved_0[0x3160];
10578 };
10579
10580 union mlx5_ifc_uplink_pci_interface_document_bits {
10581         struct mlx5_ifc_initial_seg_bits initial_seg;
10582         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10583         u8         reserved_0[0x20120];
10584 };
10585
10586 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10587         u8         e[0x1];
10588         u8         reserved_at_01[0x0b];
10589         u8         prio[0x04];
10590 };
10591
10592 struct mlx5_ifc_qpdpm_reg_bits {
10593         u8                                     reserved_at_0[0x8];
10594         u8                                     local_port[0x8];
10595         u8                                     reserved_at_10[0x10];
10596         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10597 };
10598
10599 struct mlx5_ifc_qpts_reg_bits {
10600         u8         reserved_at_0[0x8];
10601         u8         local_port[0x8];
10602         u8         reserved_at_10[0x2d];
10603         u8         trust_state[0x3];
10604 };
10605
10606 struct mlx5_ifc_mfrl_reg_bits {
10607         u8         reserved_at_0[0x38];
10608         u8         reset_level[0x8];
10609 };
10610
10611 enum {
10612       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP     = 0x9009,
10613       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR     = 0x9109,
10614       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP      = 0x900a,
10615       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE      = 0x900b,
10616       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR      = 0x900f,
10617       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE     = 0x910b,
10618       MLX5_MAX_TEMPERATURE = 16,
10619 };
10620
10621 struct mlx5_ifc_mtbr_temp_record_bits {
10622         u8         max_temperature[0x10];
10623         u8         temperature[0x10];
10624 };
10625
10626 struct mlx5_ifc_mtbr_reg_bits {
10627         u8         reserved_at_0[0x14];
10628         u8         base_sensor_index[0xc];
10629
10630         u8         reserved_at_20[0x18];
10631         u8         num_rec[0x8];
10632
10633         u8         reserved_at_40[0x40];
10634
10635         struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10636 };
10637
10638 struct mlx5_ifc_mtbr_reg_ext_bits {
10639         u8         reserved_at_0[0x14];
10640         u8         base_sensor_index[0xc];
10641
10642         u8         reserved_at_20[0x18];
10643         u8         num_rec[0x8];
10644
10645         u8         reserved_at_40[0x40];
10646
10647     struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10648 };
10649
10650 struct mlx5_ifc_mtcap_bits {
10651         u8         reserved_at_0[0x19];
10652         u8         sensor_count[0x7];
10653
10654         u8         reserved_at_20[0x19];
10655         u8         internal_sensor_count[0x7];
10656
10657         u8         sensor_map[0x40];
10658 };
10659
10660 struct mlx5_ifc_mtcap_ext_bits {
10661         u8         reserved_at_0[0x19];
10662         u8         sensor_count[0x7];
10663
10664         u8         reserved_at_20[0x20];
10665
10666         u8         sensor_map[0x40];
10667 };
10668
10669 struct mlx5_ifc_mtecr_bits {
10670         u8         reserved_at_0[0x4];
10671         u8         last_sensor[0xc];
10672         u8         reserved_at_10[0x4];
10673         u8         sensor_count[0xc];
10674
10675         u8         reserved_at_20[0x19];
10676         u8         internal_sensor_count[0x7];
10677
10678         u8         sensor_map_0[0x20];
10679
10680         u8         reserved_at_60[0x2a0];
10681 };
10682
10683 struct mlx5_ifc_mtecr_ext_bits {
10684         u8         reserved_at_0[0x4];
10685         u8         last_sensor[0xc];
10686         u8         reserved_at_10[0x4];
10687         u8         sensor_count[0xc];
10688
10689         u8         reserved_at_20[0x20];
10690
10691         u8         sensor_map_0[0x20];
10692
10693         u8         reserved_at_60[0x2a0];
10694 };
10695
10696 struct mlx5_ifc_mtewe_bits {
10697         u8         reserved_at_0[0x4];
10698         u8         last_sensor[0xc];
10699         u8         reserved_at_10[0x4];
10700         u8         sensor_count[0xc];
10701
10702         u8         sensor_warning_0[0x20];
10703
10704         u8         reserved_at_40[0x2a0];
10705 };
10706
10707 struct mlx5_ifc_mtewe_ext_bits {
10708         u8         reserved_at_0[0x4];
10709         u8         last_sensor[0xc];
10710         u8         reserved_at_10[0x4];
10711         u8         sensor_count[0xc];
10712
10713         u8         sensor_warning_0[0x20];
10714
10715         u8         reserved_at_40[0x2a0];
10716 };
10717
10718 struct mlx5_ifc_mtmp_bits {
10719         u8         reserved_at_0[0x14];
10720         u8         sensor_index[0xc];
10721
10722         u8         reserved_at_20[0x10];
10723         u8         temperature[0x10];
10724
10725         u8         mte[0x1];
10726         u8         mtr[0x1];
10727         u8         reserved_at_42[0xe];
10728         u8         max_temperature[0x10];
10729
10730         u8         tee[0x2];
10731         u8         reserved_at_62[0xe];
10732         u8         temperature_threshold_hi[0x10];
10733
10734         u8         reserved_at_80[0x10];
10735         u8         temperature_threshold_lo[0x10];
10736
10737         u8         reserved_at_a0[0x20];
10738
10739         u8         sensor_name_hi[0x20];
10740
10741         u8         sensor_name_lo[0x20];
10742 };
10743
10744 struct mlx5_ifc_mtmp_ext_bits {
10745         u8         reserved_at_0[0x14];
10746         u8         sensor_index[0xc];
10747
10748         u8         reserved_at_20[0x10];
10749         u8         temperature[0x10];
10750
10751         u8         mte[0x1];
10752         u8         mtr[0x1];
10753         u8         reserved_at_42[0xe];
10754         u8         max_temperature[0x10];
10755
10756         u8         tee[0x2];
10757         u8         reserved_at_62[0xe];
10758         u8         temperature_threshold_hi[0x10];
10759
10760         u8         reserved_at_80[0x10];
10761         u8         temperature_threshold_lo[0x10];
10762
10763         u8         reserved_at_a0[0x20];
10764
10765         u8         sensor_name_hi[0x20];
10766
10767         u8         sensor_name_lo[0x20];
10768 };
10769
10770 #endif /* MLX5_IFC_H */