2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
34 MLX5_EVENT_TYPE_COMP = 0x0,
35 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
36 MLX5_EVENT_TYPE_COMM_EST = 0x2,
37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5,
44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8,
50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9,
51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16,
53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
61 MLX5_EVENT_TYPE_CMD = 0xa,
62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27,
70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4
78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1,
82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
87 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
88 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
89 MLX5_CMD_OP_INIT_HCA = 0x102,
90 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
91 MLX5_CMD_OP_ENABLE_HCA = 0x104,
92 MLX5_CMD_OP_DISABLE_HCA = 0x105,
93 MLX5_CMD_OP_QUERY_PAGES = 0x107,
94 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
95 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
96 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
97 MLX5_CMD_OP_SET_ISSI = 0x10b,
98 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
99 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
100 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
101 MLX5_CMD_OP_CREATE_MKEY = 0x200,
102 MLX5_CMD_OP_QUERY_MKEY = 0x201,
103 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
106 MLX5_CMD_OP_CREATE_EQ = 0x301,
107 MLX5_CMD_OP_DESTROY_EQ = 0x302,
108 MLX5_CMD_OP_QUERY_EQ = 0x303,
109 MLX5_CMD_OP_GEN_EQE = 0x304,
110 MLX5_CMD_OP_CREATE_CQ = 0x400,
111 MLX5_CMD_OP_DESTROY_CQ = 0x401,
112 MLX5_CMD_OP_QUERY_CQ = 0x402,
113 MLX5_CMD_OP_MODIFY_CQ = 0x403,
114 MLX5_CMD_OP_CREATE_QP = 0x500,
115 MLX5_CMD_OP_DESTROY_QP = 0x501,
116 MLX5_CMD_OP_RST2INIT_QP = 0x502,
117 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
118 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
119 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
120 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
121 MLX5_CMD_OP_2ERR_QP = 0x507,
122 MLX5_CMD_OP_2RST_QP = 0x50a,
123 MLX5_CMD_OP_QUERY_QP = 0x50b,
124 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
125 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
126 MLX5_CMD_OP_CREATE_PSV = 0x600,
127 MLX5_CMD_OP_DESTROY_PSV = 0x601,
128 MLX5_CMD_OP_CREATE_SRQ = 0x700,
129 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
130 MLX5_CMD_OP_QUERY_SRQ = 0x702,
131 MLX5_CMD_OP_ARM_RQ = 0x703,
132 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
133 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
134 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
135 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
136 MLX5_CMD_OP_CREATE_DCT = 0x710,
137 MLX5_CMD_OP_DESTROY_DCT = 0x711,
138 MLX5_CMD_OP_DRAIN_DCT = 0x712,
139 MLX5_CMD_OP_QUERY_DCT = 0x713,
140 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
141 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715,
142 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
143 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
144 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
145 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
146 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
147 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
148 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
149 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
150 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
151 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
152 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
153 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
154 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
155 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
156 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
157 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
158 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
159 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
160 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
161 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
162 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
163 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
164 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
165 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
166 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
167 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
168 MLX5_CMD_OP_ALLOC_PD = 0x800,
169 MLX5_CMD_OP_DEALLOC_PD = 0x801,
170 MLX5_CMD_OP_ALLOC_UAR = 0x802,
171 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
172 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
173 MLX5_CMD_OP_ACCESS_REG = 0x805,
174 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
175 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
176 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
177 MLX5_CMD_OP_MAD_IFC = 0x50d,
178 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
179 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
180 MLX5_CMD_OP_NOP = 0x80d,
181 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
182 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
183 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
184 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
185 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
186 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
189 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820,
190 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821,
191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
201 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
203 MLX5_CMD_OP_CREATE_LAG = 0x840,
204 MLX5_CMD_OP_MODIFY_LAG = 0x841,
205 MLX5_CMD_OP_QUERY_LAG = 0x842,
206 MLX5_CMD_OP_DESTROY_LAG = 0x843,
207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
209 MLX5_CMD_OP_CREATE_TIR = 0x900,
210 MLX5_CMD_OP_MODIFY_TIR = 0x901,
211 MLX5_CMD_OP_DESTROY_TIR = 0x902,
212 MLX5_CMD_OP_QUERY_TIR = 0x903,
213 MLX5_CMD_OP_CREATE_SQ = 0x904,
214 MLX5_CMD_OP_MODIFY_SQ = 0x905,
215 MLX5_CMD_OP_DESTROY_SQ = 0x906,
216 MLX5_CMD_OP_QUERY_SQ = 0x907,
217 MLX5_CMD_OP_CREATE_RQ = 0x908,
218 MLX5_CMD_OP_MODIFY_RQ = 0x909,
219 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
220 MLX5_CMD_OP_QUERY_RQ = 0x90b,
221 MLX5_CMD_OP_CREATE_RMP = 0x90c,
222 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
223 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
224 MLX5_CMD_OP_QUERY_RMP = 0x90f,
225 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
226 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
227 MLX5_CMD_OP_CREATE_TIS = 0x912,
228 MLX5_CMD_OP_MODIFY_TIS = 0x913,
229 MLX5_CMD_OP_DESTROY_TIS = 0x914,
230 MLX5_CMD_OP_QUERY_TIS = 0x915,
231 MLX5_CMD_OP_CREATE_RQT = 0x916,
232 MLX5_CMD_OP_MODIFY_RQT = 0x917,
233 MLX5_CMD_OP_DESTROY_RQT = 0x918,
234 MLX5_CMD_OP_QUERY_RQT = 0x919,
235 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
236 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
237 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
238 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
239 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
240 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
241 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
242 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
243 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
244 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
245 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
246 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
247 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
248 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
249 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
250 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
256 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00,
257 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01,
258 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02,
259 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03,
264 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007,
265 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400,
266 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001,
267 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003,
268 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004,
269 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005,
270 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006,
271 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007,
272 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
273 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009,
274 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a,
275 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004
279 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
283 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
295 struct mlx5_ifc_flow_table_fields_supported_bits {
298 u8 outer_ether_type[0x1];
300 u8 outer_first_prio[0x1];
301 u8 outer_first_cfi[0x1];
302 u8 outer_first_vid[0x1];
304 u8 outer_second_prio[0x1];
305 u8 outer_second_cfi[0x1];
306 u8 outer_second_vid[0x1];
307 u8 outer_ipv6_flow_label[0x1];
311 u8 outer_ip_protocol[0x1];
312 u8 outer_ip_ecn[0x1];
313 u8 outer_ip_dscp[0x1];
314 u8 outer_udp_sport[0x1];
315 u8 outer_udp_dport[0x1];
316 u8 outer_tcp_sport[0x1];
317 u8 outer_tcp_dport[0x1];
318 u8 outer_tcp_flags[0x1];
319 u8 outer_gre_protocol[0x1];
320 u8 outer_gre_key[0x1];
321 u8 outer_vxlan_vni[0x1];
322 u8 outer_geneve_vni[0x1];
323 u8 outer_geneve_oam[0x1];
324 u8 outer_geneve_protocol_type[0x1];
325 u8 outer_geneve_opt_len[0x1];
327 u8 source_eswitch_port[0x1];
331 u8 inner_ether_type[0x1];
333 u8 inner_first_prio[0x1];
334 u8 inner_first_cfi[0x1];
335 u8 inner_first_vid[0x1];
337 u8 inner_second_prio[0x1];
338 u8 inner_second_cfi[0x1];
339 u8 inner_second_vid[0x1];
340 u8 inner_ipv6_flow_label[0x1];
344 u8 inner_ip_protocol[0x1];
345 u8 inner_ip_ecn[0x1];
346 u8 inner_ip_dscp[0x1];
347 u8 inner_udp_sport[0x1];
348 u8 inner_udp_dport[0x1];
349 u8 inner_tcp_sport[0x1];
350 u8 inner_tcp_dport[0x1];
351 u8 inner_tcp_flags[0x1];
362 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
363 u8 ingress_general_high[0x20];
365 u8 ingress_general_low[0x20];
367 u8 ingress_policy_engine_high[0x20];
369 u8 ingress_policy_engine_low[0x20];
371 u8 ingress_vlan_membership_high[0x20];
373 u8 ingress_vlan_membership_low[0x20];
375 u8 ingress_tag_frame_type_high[0x20];
377 u8 ingress_tag_frame_type_low[0x20];
379 u8 egress_vlan_membership_high[0x20];
381 u8 egress_vlan_membership_low[0x20];
383 u8 loopback_filter_high[0x20];
385 u8 loopback_filter_low[0x20];
387 u8 egress_general_high[0x20];
389 u8 egress_general_low[0x20];
391 u8 reserved_at_1c0[0x40];
393 u8 egress_hoq_high[0x20];
395 u8 egress_hoq_low[0x20];
397 u8 port_isolation_high[0x20];
399 u8 port_isolation_low[0x20];
401 u8 egress_policy_engine_high[0x20];
403 u8 egress_policy_engine_low[0x20];
405 u8 ingress_tx_link_down_high[0x20];
407 u8 ingress_tx_link_down_low[0x20];
409 u8 egress_stp_filter_high[0x20];
411 u8 egress_stp_filter_low[0x20];
413 u8 egress_hoq_stall_high[0x20];
415 u8 egress_hoq_stall_low[0x20];
417 u8 reserved_at_340[0x440];
419 struct mlx5_ifc_flow_table_prop_layout_bits {
422 u8 flow_counter[0x1];
423 u8 flow_modify_en[0x1];
425 u8 identified_miss_table[0x1];
426 u8 flow_table_modify[0x1];
429 u8 reset_root_to_default[0x1];
430 u8 reserved_at_a[0x16];
432 u8 reserved_at_20[0x2];
433 u8 log_max_ft_size[0x6];
434 u8 reserved_at_28[0x10];
435 u8 max_ft_level[0x8];
437 u8 reserved_at_40[0x20];
439 u8 reserved_at_60[0x18];
440 u8 log_max_ft_num[0x8];
442 u8 reserved_at_80[0x10];
443 u8 log_max_flow_counter[0x8];
444 u8 log_max_destination[0x8];
446 u8 reserved_at_a0[0x18];
447 u8 log_max_flow[0x8];
449 u8 reserved_at_c0[0x40];
451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
456 struct mlx5_ifc_odp_per_transport_service_cap_bits {
466 struct mlx5_ifc_flow_counter_list_bits {
468 u8 flow_counter_id[0x10];
474 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,
475 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1,
476 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2,
477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
480 struct mlx5_ifc_dest_format_struct_bits {
481 u8 destination_type[0x8];
482 u8 destination_id[0x18];
487 struct mlx5_ifc_ipv4_layout_bits {
488 u8 reserved_at_0[0x60];
493 struct mlx5_ifc_ipv6_layout_bits {
497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
500 u8 reserved_at_0[0x80];
503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
533 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
535 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
538 struct mlx5_ifc_fte_match_set_misc_bits {
543 u8 source_port[0x10];
545 u8 outer_second_prio[0x3];
546 u8 outer_second_cfi[0x1];
547 u8 outer_second_vid[0xc];
548 u8 inner_second_prio[0x3];
549 u8 inner_second_cfi[0x1];
550 u8 inner_second_vid[0xc];
552 u8 outer_second_vlan_tag[0x1];
553 u8 inner_second_vlan_tag[0x1];
555 u8 gre_protocol[0x10];
568 u8 outer_ipv6_flow_label[0x14];
571 u8 inner_ipv6_flow_label[0x14];
574 u8 geneve_opt_len[0x6];
575 u8 geneve_protocol_type[0x10];
583 struct mlx5_ifc_cmd_pas_bits {
590 struct mlx5_ifc_uint64_bits {
596 struct mlx5_ifc_application_prio_entry_bits {
601 u8 protocol_id[0x10];
604 struct mlx5_ifc_nodnic_ring_doorbell_bits {
611 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
613 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
614 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
615 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
616 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
617 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
618 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
619 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
620 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
623 struct mlx5_ifc_ads_bits {
636 u8 src_addr_index[0x8];
645 u8 rgid_rip[16][0x8];
665 struct mlx5_ifc_diagnostic_counter_cap_bits {
671 struct mlx5_ifc_debug_cap_bits {
673 u8 log_max_samples[0x8];
677 u8 health_mon_rx_activity[0x1];
679 u8 log_min_sample_period[0x8];
681 u8 reserved_2[0x1c0];
683 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
686 struct mlx5_ifc_qos_cap_bits {
687 u8 packet_pacing[0x1];
688 u8 esw_scheduling[0x1];
689 u8 esw_bw_share[0x1];
690 u8 esw_rate_limit[0x1];
692 u8 packet_pacing_burst_bound[0x1];
693 u8 packet_pacing_typical_size[0x1];
694 u8 reserved_at_7[0x19];
696 u8 reserved_at_20[0x20];
698 u8 packet_pacing_max_rate[0x20];
700 u8 packet_pacing_min_rate[0x20];
702 u8 reserved_at_80[0x10];
703 u8 packet_pacing_rate_table_size[0x10];
705 u8 esw_element_type[0x10];
706 u8 esw_tsar_type[0x10];
708 u8 reserved_at_c0[0x10];
709 u8 max_qos_para_vport[0x10];
711 u8 max_tsar_bw_share[0x20];
713 u8 reserved_at_100[0x700];
716 struct mlx5_ifc_snapshot_cap_bits {
718 u8 suspend_qp_uc[0x1];
719 u8 suspend_qp_ud[0x1];
720 u8 suspend_qp_rc[0x1];
725 u8 restore_mkey[0x1];
732 u8 reserved_3[0x7a0];
735 struct mlx5_ifc_e_switch_cap_bits {
736 u8 vport_svlan_strip[0x1];
737 u8 vport_cvlan_strip[0x1];
738 u8 vport_svlan_insert[0x1];
739 u8 vport_cvlan_insert_if_not_exist[0x1];
740 u8 vport_cvlan_insert_overwrite[0x1];
744 u8 nic_vport_node_guid_modify[0x1];
745 u8 nic_vport_port_guid_modify[0x1];
747 u8 reserved_1[0x7e0];
750 struct mlx5_ifc_flow_table_eswitch_cap_bits {
751 u8 reserved_0[0x200];
753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
759 u8 reserved_1[0x7800];
762 struct mlx5_ifc_flow_table_nic_cap_bits {
763 u8 nic_rx_multi_path_tirs[0x1];
764 u8 nic_rx_multi_path_tirs_fts[0x1];
765 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
766 u8 reserved_at_3[0x1fd];
768 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
770 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
772 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
774 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
776 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
780 u8 reserved_1[0x7200];
784 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR = 0x5031,
787 struct mlx5_ifc_pddr_module_info_bits {
788 u8 cable_technology[0x8];
789 u8 cable_breakout[0x8];
790 u8 ext_ethernet_compliance_code[0x8];
791 u8 ethernet_compliance_code[0x8];
794 u8 cable_vendor[0x4];
795 u8 cable_length[0x8];
796 u8 cable_identifier[0x8];
797 u8 cable_power_class[0x8];
799 u8 reserved_at_40[0x8];
800 u8 cable_rx_amp[0x8];
801 u8 cable_rx_emphasis[0x8];
802 u8 cable_tx_equalization[0x8];
804 u8 reserved_at_60[0x8];
805 u8 cable_attenuation_12g[0x8];
806 u8 cable_attenuation_7g[0x8];
807 u8 cable_attenuation_5g[0x8];
809 u8 reserved_at_80[0x8];
812 u8 reserved_at_90[0x4];
813 u8 rx_cdr_state[0x4];
814 u8 reserved_at_98[0x4];
815 u8 tx_cdr_state[0x4];
817 u8 vendor_name[16][0x8];
819 u8 vendor_pn[16][0x8];
825 u8 vendor_sn[16][0x8];
827 u8 temperature[0x10];
830 u8 rx_power_lane0[0x10];
831 u8 rx_power_lane1[0x10];
833 u8 rx_power_lane2[0x10];
834 u8 rx_power_lane3[0x10];
836 u8 reserved_at_2c0[0x40];
838 u8 tx_power_lane0[0x10];
839 u8 tx_power_lane1[0x10];
841 u8 tx_power_lane2[0x10];
842 u8 tx_power_lane3[0x10];
844 u8 reserved_at_340[0x40];
846 u8 tx_bias_lane0[0x10];
847 u8 tx_bias_lane1[0x10];
849 u8 tx_bias_lane2[0x10];
850 u8 tx_bias_lane3[0x10];
852 u8 reserved_at_3c0[0x40];
854 u8 temperature_high_th[0x10];
855 u8 temperature_low_th[0x10];
857 u8 voltage_high_th[0x10];
858 u8 voltage_low_th[0x10];
860 u8 rx_power_high_th[0x10];
861 u8 rx_power_low_th[0x10];
863 u8 tx_power_high_th[0x10];
864 u8 tx_power_low_th[0x10];
866 u8 tx_bias_high_th[0x10];
867 u8 tx_bias_low_th[0x10];
869 u8 reserved_at_4a0[0x10];
872 u8 reserved_at_4c0[0x300];
875 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
876 struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
877 u8 reserved_at_0[0x7c0];
880 struct mlx5_ifc_pddr_reg_bits {
881 u8 reserved_at_0[0x8];
884 u8 reserved_at_12[0xe];
886 u8 reserved_at_20[0x18];
889 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
892 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
896 u8 lro_psh_flag[0x1];
897 u8 lro_time_stamp[0x1];
898 u8 lro_max_msg_sz_mode[0x2];
899 u8 wqe_vlan_insert[0x1];
900 u8 self_lb_en_modifiable[0x1];
904 u8 multi_pkt_send_wqe[0x2];
905 u8 wqe_inline_mode[0x2];
906 u8 rss_ind_tbl_cap[0x4];
909 u8 tunnel_lso_const_out_ip_id[0x1];
910 u8 tunnel_lro_gre[0x1];
911 u8 tunnel_lro_vxlan[0x1];
912 u8 tunnel_statless_gre[0x1];
913 u8 tunnel_stateless_vxlan[0x1];
919 u8 max_geneve_opt_len[0x1];
920 u8 tunnel_stateless_geneve_rx[0x1];
923 u8 lro_min_mss_size[0x10];
925 u8 reserved_4[0x120];
927 u8 lro_timer_supported_periods[4][0x20];
929 u8 reserved_5[0x600];
933 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1,
934 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2,
935 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
938 struct mlx5_ifc_roce_cap_bits {
940 u8 rts2rts_primary_eth_prio[0x1];
941 u8 roce_rx_allow_untagged[0x1];
942 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
951 u8 roce_version[0x8];
954 u8 r_roce_dest_udp_port[0x10];
956 u8 r_roce_max_src_udp_port[0x10];
957 u8 r_roce_min_src_udp_port[0x10];
960 u8 roce_address_table_size[0x10];
962 u8 reserved_6[0x700];
966 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1,
967 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
968 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
978 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
979 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
980 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
981 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
982 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
983 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
984 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
989 struct mlx5_ifc_atomic_caps_bits {
992 u8 atomic_req_8B_endianess_mode[0x2];
994 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
1000 u8 reserved_4[0x10];
1001 u8 atomic_operations[0x10];
1003 u8 reserved_5[0x10];
1004 u8 atomic_size_qp[0x10];
1006 u8 reserved_6[0x10];
1007 u8 atomic_size_dc[0x10];
1009 u8 reserved_7[0x720];
1012 struct mlx5_ifc_odp_cap_bits {
1013 u8 reserved_0[0x40];
1016 u8 reserved_1[0x1f];
1018 u8 reserved_2[0x20];
1020 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1022 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1024 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1026 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1028 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1030 u8 reserved_3[0x6e0];
1034 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1035 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1036 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1037 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1038 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1042 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1043 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1044 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1045 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1046 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1047 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1051 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1052 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1056 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1057 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1058 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1061 struct mlx5_ifc_cmd_hca_cap_bits {
1062 u8 reserved_0[0x80];
1064 u8 log_max_srq_sz[0x8];
1065 u8 log_max_qp_sz[0x8];
1070 u8 log_max_srq[0x5];
1071 u8 reserved_3[0x10];
1074 u8 log_max_cq_sz[0x8];
1078 u8 log_max_eq_sz[0x8];
1079 u8 relaxed_ordering_write[1];
1081 u8 log_max_mkey[0x6];
1083 u8 fast_teardown[0x1];
1086 u8 max_indirection[0x8];
1088 u8 log_max_mrw_sz[0x7];
1089 u8 force_teardown[0x1];
1091 u8 log_max_bsf_list_size[0x6];
1092 u8 reserved_10[0x2];
1093 u8 log_max_klm_list_size[0x6];
1095 u8 reserved_11[0xa];
1096 u8 log_max_ra_req_dc[0x6];
1097 u8 reserved_12[0xa];
1098 u8 log_max_ra_res_dc[0x6];
1100 u8 reserved_13[0xa];
1101 u8 log_max_ra_req_qp[0x6];
1102 u8 reserved_14[0xa];
1103 u8 log_max_ra_res_qp[0x6];
1106 u8 cc_query_allowed[0x1];
1107 u8 cc_modify_allowed[0x1];
1109 u8 cache_line_128byte[0x1];
1110 u8 reserved_at_165[0xa];
1112 u8 gid_table_size[0x10];
1114 u8 out_of_seq_cnt[0x1];
1115 u8 vport_counters[0x1];
1116 u8 retransmission_q_counters[0x1];
1118 u8 modify_rq_counters_set_id[0x1];
1119 u8 rq_delay_drop[0x1];
1121 u8 pkey_table_size[0x10];
1123 u8 vport_group_manager[0x1];
1124 u8 vhca_group_manager[0x1];
1127 u8 reserved_17[0x1];
1129 u8 nic_flow_table[0x1];
1130 u8 eswitch_flow_table[0x1];
1131 u8 reserved_18[0x1];
1134 u8 local_ca_ack_delay[0x5];
1135 u8 port_module_event[0x1];
1136 u8 reserved_19[0x5];
1141 u8 reserved_20[0x2];
1142 u8 log_max_msg[0x5];
1143 u8 reserved_21[0x4];
1145 u8 temp_warn_event[0x1];
1147 u8 general_notification_event[0x1];
1148 u8 reserved_at_1d3[0x2];
1152 u8 reserved_23[0x1];
1161 u8 stat_rate_support[0x10];
1162 u8 reserved_24[0xc];
1163 u8 cqe_version[0x4];
1165 u8 compact_address_vector[0x1];
1166 u8 striding_rq[0x1];
1167 u8 reserved_25[0x1];
1168 u8 ipoib_enhanced_offloads[0x1];
1169 u8 ipoib_ipoib_offloads[0x1];
1170 u8 reserved_26[0x8];
1171 u8 dc_connect_qp[0x1];
1172 u8 dc_cnak_trace[0x1];
1173 u8 drain_sigerr[0x1];
1174 u8 cmdif_checksum[0x2];
1176 u8 reserved_27[0x1];
1177 u8 wq_signature[0x1];
1178 u8 sctr_data_cqe[0x1];
1179 u8 reserved_28[0x1];
1185 u8 eth_net_offloads[0x1];
1188 u8 reserved_30[0x1];
1192 u8 cq_moderation[0x1];
1193 u8 cq_period_mode_modify[0x1];
1194 u8 cq_invalidate[0x1];
1195 u8 reserved_at_225[0x1];
1196 u8 cq_eq_remap[0x1];
1198 u8 block_lb_mc[0x1];
1199 u8 exponential_backoff[0x1];
1200 u8 scqe_break_moderation[0x1];
1201 u8 cq_period_start_from_cqe[0x1];
1206 u8 reserved_32[0x6];
1209 u8 set_deth_sqpn[0x1];
1210 u8 reserved_33[0x3];
1216 u8 reserved_34[0xa];
1218 u8 reserved_35[0x8];
1222 u8 driver_version[0x1];
1223 u8 pad_tx_eth_packet[0x1];
1224 u8 reserved_36[0x8];
1225 u8 log_bf_reg_size[0x5];
1226 u8 reserved_37[0x10];
1228 u8 num_of_diagnostic_counters[0x10];
1229 u8 max_wqe_sz_sq[0x10];
1231 u8 reserved_38[0x10];
1232 u8 max_wqe_sz_rq[0x10];
1234 u8 reserved_39[0x10];
1235 u8 max_wqe_sz_sq_dc[0x10];
1237 u8 reserved_40[0x7];
1238 u8 max_qp_mcg[0x19];
1240 u8 reserved_41[0x18];
1241 u8 log_max_mcg[0x8];
1243 u8 reserved_42[0x3];
1244 u8 log_max_transport_domain[0x5];
1245 u8 reserved_43[0x3];
1247 u8 reserved_44[0xb];
1248 u8 log_max_xrcd[0x5];
1250 u8 nic_receive_steering_discard[0x1];
1251 u8 reserved_45[0x7];
1252 u8 log_max_flow_counter_bulk[0x8];
1253 u8 max_flow_counter[0x10];
1255 u8 reserved_46[0x3];
1257 u8 reserved_47[0x3];
1259 u8 reserved_48[0x3];
1260 u8 log_max_tir[0x5];
1261 u8 reserved_49[0x3];
1262 u8 log_max_tis[0x5];
1264 u8 basic_cyclic_rcv_wqe[0x1];
1265 u8 reserved_50[0x2];
1266 u8 log_max_rmp[0x5];
1267 u8 reserved_51[0x3];
1268 u8 log_max_rqt[0x5];
1269 u8 reserved_52[0x3];
1270 u8 log_max_rqt_size[0x5];
1271 u8 reserved_53[0x3];
1272 u8 log_max_tis_per_sq[0x5];
1274 u8 reserved_54[0x3];
1275 u8 log_max_stride_sz_rq[0x5];
1276 u8 reserved_55[0x3];
1277 u8 log_min_stride_sz_rq[0x5];
1278 u8 reserved_56[0x3];
1279 u8 log_max_stride_sz_sq[0x5];
1280 u8 reserved_57[0x3];
1281 u8 log_min_stride_sz_sq[0x5];
1283 u8 reserved_58[0x1b];
1284 u8 log_max_wq_sz[0x5];
1286 u8 nic_vport_change_event[0x1];
1287 u8 disable_local_lb[0x1];
1288 u8 reserved_59[0x9];
1289 u8 log_max_vlan_list[0x5];
1290 u8 reserved_60[0x3];
1291 u8 log_max_current_mc_list[0x5];
1292 u8 reserved_61[0x3];
1293 u8 log_max_current_uc_list[0x5];
1295 u8 general_obj_types[0x40];
1297 u8 reserved_at_440[0x8];
1298 u8 create_qp_start_hint[0x18];
1300 u8 reserved_at_460[0x3];
1301 u8 log_max_uctx[0x5];
1302 u8 reserved_at_468[0x3];
1303 u8 log_max_umem[0x5];
1304 u8 max_num_eqs[0x10];
1306 u8 reserved_at_480[0x1];
1308 u8 reserved_at_482[0x1];
1309 u8 log_max_l2_table[0x5];
1310 u8 reserved_64[0x8];
1311 u8 log_uar_page_sz[0x10];
1313 u8 reserved_65[0x20];
1315 u8 device_frequency_mhz[0x20];
1317 u8 device_frequency_khz[0x20];
1319 u8 reserved_66[0x80];
1321 u8 log_max_atomic_size_qp[0x8];
1322 u8 reserved_67[0x10];
1323 u8 log_max_atomic_size_dc[0x8];
1325 u8 reserved_at_5a0[0x13];
1326 u8 log_max_dek[0x5];
1327 u8 reserved_at_5b8[0x4];
1328 u8 mini_cqe_resp_stride_index[0x1];
1329 u8 cqe_128_always[0x1];
1330 u8 cqe_compression_128b[0x1];
1332 u8 cqe_compression[0x1];
1334 u8 cqe_compression_timeout[0x10];
1335 u8 cqe_compression_max_num[0x10];
1337 u8 reserved_69[0x220];
1340 enum mlx5_flow_destination_type {
1341 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1342 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1343 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1346 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1347 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1348 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1349 u8 reserved_0[0x40];
1352 struct mlx5_ifc_fte_match_param_bits {
1353 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1355 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1357 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1359 u8 reserved_0[0xa00];
1363 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1364 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1365 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1366 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1367 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1370 struct mlx5_ifc_rx_hash_field_select_bits {
1371 u8 l3_prot_type[0x1];
1372 u8 l4_prot_type[0x1];
1373 u8 selected_fields[0x1e];
1376 struct mlx5_ifc_tls_capabilities_bits {
1377 u8 tls_1_2_aes_gcm_128[0x1];
1378 u8 tls_1_3_aes_gcm_128[0x1];
1379 u8 tls_1_2_aes_gcm_256[0x1];
1380 u8 tls_1_3_aes_gcm_256[0x1];
1381 u8 reserved_at_4[0x1c];
1383 u8 reserved_at_20[0x7e0];
1387 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1388 MLX5_WQ_TYPE_CYCLIC = 0x1,
1389 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2,
1390 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1399 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1400 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1403 struct mlx5_ifc_wq_bits {
1405 u8 wq_signature[0x1];
1406 u8 end_padding_mode[0x2];
1408 u8 reserved_0[0x18];
1410 u8 hds_skip_first_sge[0x1];
1411 u8 log2_hds_buf_size[0x3];
1413 u8 page_offset[0x5];
1424 u8 hw_counter[0x20];
1426 u8 sw_counter[0x20];
1429 u8 log_wq_stride[0x4];
1431 u8 log_wq_pg_sz[0x5];
1435 u8 reserved_7[0x15];
1436 u8 single_wqe_log_num_of_strides[0x3];
1437 u8 two_byte_shift_en[0x1];
1439 u8 single_stride_log_num_of_bytes[0x3];
1441 u8 reserved_9[0x4c0];
1443 struct mlx5_ifc_cmd_pas_bits pas[0];
1446 struct mlx5_ifc_rq_num_bits {
1451 struct mlx5_ifc_mac_address_layout_bits {
1452 u8 reserved_0[0x10];
1453 u8 mac_addr_47_32[0x10];
1455 u8 mac_addr_31_0[0x20];
1458 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1459 u8 reserved_0[0xa0];
1461 u8 min_time_between_cnps[0x20];
1463 u8 reserved_1[0x12];
1466 u8 cnp_prio_mode[0x1];
1467 u8 cnp_802p_prio[0x3];
1469 u8 reserved_3[0x720];
1472 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1473 u8 reserved_0[0x60];
1476 u8 clamp_tgt_rate[0x1];
1478 u8 clamp_tgt_rate_after_time_inc[0x1];
1479 u8 reserved_3[0x17];
1481 u8 reserved_4[0x20];
1483 u8 rpg_time_reset[0x20];
1485 u8 rpg_byte_reset[0x20];
1487 u8 rpg_threshold[0x20];
1489 u8 rpg_max_rate[0x20];
1491 u8 rpg_ai_rate[0x20];
1493 u8 rpg_hai_rate[0x20];
1497 u8 rpg_min_dec_fac[0x20];
1499 u8 rpg_min_rate[0x20];
1501 u8 reserved_5[0xe0];
1503 u8 rate_to_set_on_first_cnp[0x20];
1507 u8 dce_tcp_rtt[0x20];
1509 u8 rate_reduce_monitor_period[0x20];
1511 u8 reserved_6[0x20];
1513 u8 initial_alpha_value[0x20];
1515 u8 reserved_7[0x4a0];
1518 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1519 u8 reserved_0[0x80];
1521 u8 rppp_max_rps[0x20];
1523 u8 rpg_time_reset[0x20];
1525 u8 rpg_byte_reset[0x20];
1527 u8 rpg_threshold[0x20];
1529 u8 rpg_max_rate[0x20];
1531 u8 rpg_ai_rate[0x20];
1533 u8 rpg_hai_rate[0x20];
1537 u8 rpg_min_dec_fac[0x20];
1539 u8 rpg_min_rate[0x20];
1541 u8 reserved_1[0x640];
1545 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1546 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1547 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1550 struct mlx5_ifc_resize_field_select_bits {
1551 u8 resize_field_select[0x20];
1555 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1556 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1557 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1558 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1559 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
1560 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
1563 struct mlx5_ifc_modify_field_select_bits {
1564 u8 modify_field_select[0x20];
1567 struct mlx5_ifc_field_select_r_roce_np_bits {
1568 u8 field_select_r_roce_np[0x20];
1572 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2,
1573 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4,
1574 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8,
1575 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10,
1576 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20,
1577 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40,
1578 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80,
1579 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100,
1580 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200,
1581 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400,
1582 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800,
1583 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000,
1584 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000,
1585 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000,
1586 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000,
1589 struct mlx5_ifc_field_select_r_roce_rp_bits {
1590 u8 field_select_r_roce_rp[0x20];
1594 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1595 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1596 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1597 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1598 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1599 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1600 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1601 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1602 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1603 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1606 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1607 u8 field_select_8021qaurp[0x20];
1610 struct mlx5_ifc_pptb_reg_bits {
1611 u8 reserved_at_0[0x2];
1613 u8 reserved_at_4[0x4];
1615 u8 reserved_at_10[0x6];
1620 u8 prio_x_buff[0x20];
1623 u8 reserved_at_48[0x10];
1625 u8 untagged_buff[0x4];
1628 struct mlx5_ifc_dcbx_app_reg_bits {
1630 u8 port_number[0x8];
1631 u8 reserved_1[0x10];
1633 u8 reserved_2[0x1a];
1634 u8 num_app_prio[0x6];
1636 u8 reserved_3[0x40];
1638 struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1641 struct mlx5_ifc_dcbx_param_reg_bits {
1642 u8 dcbx_cee_cap[0x1];
1643 u8 dcbx_ieee_cap[0x1];
1644 u8 dcbx_standby_cap[0x1];
1646 u8 port_number[0x8];
1648 u8 max_application_table_size[0x6];
1650 u8 reserved_2[0x15];
1651 u8 version_oper[0x3];
1653 u8 version_admin[0x3];
1655 u8 willing_admin[0x1];
1657 u8 pfc_cap_oper[0x4];
1659 u8 pfc_cap_admin[0x4];
1661 u8 num_of_tc_oper[0x4];
1663 u8 num_of_tc_admin[0x4];
1665 u8 remote_willing[0x1];
1667 u8 remote_pfc_cap[0x4];
1668 u8 reserved_9[0x14];
1669 u8 remote_num_of_tc[0x4];
1671 u8 reserved_10[0x18];
1674 u8 reserved_11[0x160];
1677 struct mlx5_ifc_qhll_bits {
1678 u8 reserved_at_0[0x8];
1680 u8 reserved_at_10[0x10];
1682 u8 reserved_at_20[0x1b];
1686 u8 reserved_at_41[0x1c];
1690 struct mlx5_ifc_qetcr_reg_bits {
1691 u8 operation_type[0x2];
1692 u8 cap_local_admin[0x1];
1693 u8 cap_remote_admin[0x1];
1695 u8 port_number[0x8];
1696 u8 reserved_1[0x10];
1698 u8 reserved_2[0x20];
1702 u8 global_configuration[0x40];
1705 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1706 u8 queue_address_63_32[0x20];
1708 u8 queue_address_31_12[0x14];
1712 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1715 u8 queue_number[0x18];
1719 u8 reserved_2[0x10];
1720 u8 pkey_index[0x10];
1722 u8 reserved_3[0x40];
1725 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1732 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0,
1733 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1,
1737 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0,
1738 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1,
1739 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2,
1740 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
1743 struct mlx5_ifc_nodnic_event_word_bits {
1744 u8 driver_reset_needed[0x1];
1745 u8 port_management_change_event[0x1];
1746 u8 reserved_0[0x19];
1751 struct mlx5_ifc_nic_vport_change_event_bits {
1752 u8 reserved_0[0x10];
1755 u8 reserved_1[0xc0];
1758 struct mlx5_ifc_pages_req_event_bits {
1759 u8 reserved_0[0x10];
1760 u8 function_id[0x10];
1764 u8 reserved_1[0xa0];
1767 struct mlx5_ifc_cmd_inter_comp_event_bits {
1768 u8 command_completion_vector[0x20];
1770 u8 reserved_0[0xc0];
1773 struct mlx5_ifc_stall_vl_event_bits {
1774 u8 reserved_0[0x18];
1779 u8 reserved_2[0xa0];
1782 struct mlx5_ifc_db_bf_congestion_event_bits {
1783 u8 event_subtype[0x8];
1785 u8 congestion_level[0x8];
1788 u8 reserved_2[0xa0];
1791 struct mlx5_ifc_gpio_event_bits {
1792 u8 reserved_0[0x60];
1794 u8 gpio_event_hi[0x20];
1796 u8 gpio_event_lo[0x20];
1798 u8 reserved_1[0x40];
1801 struct mlx5_ifc_port_state_change_event_bits {
1802 u8 reserved_0[0x40];
1805 u8 reserved_1[0x1c];
1807 u8 reserved_2[0x80];
1810 struct mlx5_ifc_dropped_packet_logged_bits {
1811 u8 reserved_0[0xe0];
1815 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1816 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1819 struct mlx5_ifc_cq_error_bits {
1823 u8 reserved_1[0x20];
1825 u8 reserved_2[0x18];
1828 u8 reserved_3[0x80];
1831 struct mlx5_ifc_rdma_page_fault_event_bits {
1832 u8 bytes_commited[0x20];
1836 u8 reserved_0[0x10];
1837 u8 packet_len[0x10];
1839 u8 rdma_op_len[0x20];
1850 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1851 u8 bytes_committed[0x20];
1853 u8 reserved_0[0x10];
1856 u8 reserved_1[0x10];
1859 u8 reserved_2[0x60];
1869 MLX5_QP_EVENTS_TYPE_QP = 0x0,
1870 MLX5_QP_EVENTS_TYPE_RQ = 0x1,
1871 MLX5_QP_EVENTS_TYPE_SQ = 0x2,
1874 struct mlx5_ifc_qp_events_bits {
1875 u8 reserved_0[0xa0];
1878 u8 reserved_1[0x18];
1881 u8 qpn_rqn_sqn[0x18];
1884 struct mlx5_ifc_dct_events_bits {
1885 u8 reserved_0[0xc0];
1888 u8 dct_number[0x18];
1891 struct mlx5_ifc_comp_event_bits {
1892 u8 reserved_0[0xc0];
1898 struct mlx5_ifc_fw_version_bits {
1900 u8 reserved_0[0x10];
1916 MLX5_QPC_STATE_RST = 0x0,
1917 MLX5_QPC_STATE_INIT = 0x1,
1918 MLX5_QPC_STATE_RTR = 0x2,
1919 MLX5_QPC_STATE_RTS = 0x3,
1920 MLX5_QPC_STATE_SQER = 0x4,
1921 MLX5_QPC_STATE_SQD = 0x5,
1922 MLX5_QPC_STATE_ERR = 0x6,
1923 MLX5_QPC_STATE_SUSPENDED = 0x9,
1927 MLX5_QPC_ST_RC = 0x0,
1928 MLX5_QPC_ST_UC = 0x1,
1929 MLX5_QPC_ST_UD = 0x2,
1930 MLX5_QPC_ST_XRC = 0x3,
1931 MLX5_QPC_ST_DCI = 0x5,
1932 MLX5_QPC_ST_QP0 = 0x7,
1933 MLX5_QPC_ST_QP1 = 0x8,
1934 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1935 MLX5_QPC_ST_REG_UMR = 0xc,
1939 MLX5_QP_PM_ARMED = 0x0,
1940 MLX5_QP_PM_REARM = 0x1,
1941 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1942 MLX5_QP_PM_MIGRATED = 0x3,
1946 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1947 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1951 MLX5_QPC_MTU_256_BYTES = 0x1,
1952 MLX5_QPC_MTU_512_BYTES = 0x2,
1953 MLX5_QPC_MTU_1K_BYTES = 0x3,
1954 MLX5_QPC_MTU_2K_BYTES = 0x4,
1955 MLX5_QPC_MTU_4K_BYTES = 0x5,
1956 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1960 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1961 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1962 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1963 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1964 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1965 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1966 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1967 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1971 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1972 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1973 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1977 MLX5_QPC_CS_RES_DISABLE = 0x0,
1978 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1979 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1982 struct mlx5_ifc_qpc_bits {
1984 u8 lag_tx_port_affinity[0x4];
1989 u8 end_padding_mode[0x2];
1992 u8 wq_signature[0x1];
1993 u8 block_lb_mc[0x1];
1994 u8 atomic_like_write_en[0x1];
1995 u8 latency_sensitive[0x1];
1997 u8 drain_sigerr[0x1];
2002 u8 log_msg_max[0x5];
2004 u8 log_rq_size[0x4];
2005 u8 log_rq_stride[0x3];
2007 u8 log_sq_size[0x4];
2010 u8 ulp_stateless_offload_mode[0x4];
2012 u8 counter_set_id[0x8];
2016 u8 user_index[0x18];
2019 u8 log_page_size[0x5];
2020 u8 remote_qpn[0x18];
2022 struct mlx5_ifc_ads_bits primary_address_path;
2024 struct mlx5_ifc_ads_bits secondary_address_path;
2026 u8 log_ack_req_freq[0x4];
2027 u8 reserved_10[0x4];
2028 u8 log_sra_max[0x3];
2029 u8 reserved_11[0x2];
2030 u8 retry_count[0x3];
2032 u8 reserved_12[0x1];
2034 u8 cur_rnr_retry[0x3];
2035 u8 cur_retry_count[0x3];
2036 u8 reserved_13[0x5];
2038 u8 reserved_14[0x20];
2040 u8 reserved_15[0x8];
2041 u8 next_send_psn[0x18];
2043 u8 reserved_16[0x8];
2046 u8 reserved_at_400[0x8];
2049 u8 reserved_17[0x20];
2051 u8 reserved_18[0x8];
2052 u8 last_acked_psn[0x18];
2054 u8 reserved_19[0x8];
2057 u8 reserved_20[0x8];
2058 u8 log_rra_max[0x3];
2059 u8 reserved_21[0x1];
2060 u8 atomic_mode[0x4];
2064 u8 reserved_22[0x1];
2065 u8 page_offset[0x6];
2066 u8 reserved_23[0x3];
2067 u8 cd_slave_receive[0x1];
2068 u8 cd_slave_send[0x1];
2071 u8 reserved_24[0x3];
2072 u8 min_rnr_nak[0x5];
2073 u8 next_rcv_psn[0x18];
2075 u8 reserved_25[0x8];
2078 u8 reserved_26[0x8];
2085 u8 reserved_27[0x5];
2089 u8 reserved_28[0x8];
2092 u8 hw_sq_wqebb_counter[0x10];
2093 u8 sw_sq_wqebb_counter[0x10];
2095 u8 hw_rq_counter[0x20];
2097 u8 sw_rq_counter[0x20];
2099 u8 reserved_29[0x20];
2101 u8 reserved_30[0xf];
2106 u8 dc_access_key[0x40];
2108 u8 rdma_active[0x1];
2111 u8 reserved_31[0x5];
2112 u8 send_msg_psn[0x18];
2114 u8 reserved_32[0x8];
2115 u8 rcv_msg_psn[0x18];
2121 u8 reserved_33[0x20];
2124 struct mlx5_ifc_roce_addr_layout_bits {
2125 u8 source_l3_address[16][0x8];
2130 u8 source_mac_47_32[0x10];
2132 u8 source_mac_31_0[0x20];
2134 u8 reserved_1[0x14];
2135 u8 roce_l3_type[0x4];
2136 u8 roce_version[0x8];
2138 u8 reserved_2[0x20];
2141 struct mlx5_ifc_rdbc_bits {
2142 u8 reserved_0[0x1c];
2145 u8 reserved_1[0x20];
2154 u8 byte_count[0x20];
2156 u8 reserved_3[0x20];
2158 u8 atomic_resp[32][0x8];
2162 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2163 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2164 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2165 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2168 struct mlx5_ifc_flow_context_bits {
2169 u8 reserved_0[0x20];
2176 u8 reserved_2[0x10];
2180 u8 destination_list_size[0x18];
2183 u8 flow_counter_list_size[0x18];
2185 u8 reserved_5[0x140];
2187 struct mlx5_ifc_fte_match_param_bits match_value;
2189 u8 reserved_6[0x600];
2191 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2195 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2196 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2199 struct mlx5_ifc_xrc_srqc_bits {
2201 u8 log_xrc_srq_size[0x4];
2202 u8 reserved_0[0x18];
2204 u8 wq_signature[0x1];
2208 u8 basic_cyclic_rcv_wqe[0x1];
2209 u8 log_rq_stride[0x3];
2212 u8 page_offset[0x6];
2216 u8 reserved_3[0x20];
2219 u8 log_page_size[0x6];
2220 u8 user_index[0x18];
2222 u8 reserved_5[0x20];
2230 u8 reserved_7[0x40];
2232 u8 db_record_addr_h[0x20];
2234 u8 db_record_addr_l[0x1e];
2237 u8 reserved_9[0x80];
2240 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2241 u8 counter_error_queues[0x20];
2243 u8 total_error_queues[0x20];
2245 u8 send_queue_priority_update_flow[0x20];
2247 u8 reserved_at_60[0x20];
2249 u8 nic_receive_steering_discard[0x40];
2251 u8 receive_discard_vport_down[0x40];
2253 u8 transmit_discard_vport_down[0x40];
2255 u8 reserved_at_140[0xec0];
2258 struct mlx5_ifc_traffic_counter_bits {
2264 struct mlx5_ifc_tisc_bits {
2265 u8 strict_lag_tx_port_affinity[0x1];
2267 u8 reserved_at_2[0x2];
2268 u8 lag_tx_port_affinity[0x04];
2270 u8 reserved_at_8[0x4];
2272 u8 reserved_1[0x10];
2274 u8 reserved_2[0x100];
2277 u8 transport_domain[0x18];
2280 u8 underlay_qpn[0x18];
2285 u8 reserved_6[0x380];
2289 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2290 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2294 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2295 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2299 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
2300 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
2301 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
2305 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1,
2306 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2,
2309 struct mlx5_ifc_tirc_bits {
2310 u8 reserved_0[0x20];
2314 u8 reserved_at_25[0x1b];
2316 u8 reserved_2[0x40];
2319 u8 lro_timeout_period_usecs[0x10];
2320 u8 lro_enable_mask[0x4];
2321 u8 lro_max_msg_sz[0x8];
2323 u8 reserved_4[0x40];
2326 u8 inline_rqn[0x18];
2328 u8 rx_hash_symmetric[0x1];
2330 u8 tunneled_offload_en[0x1];
2332 u8 indirect_table[0x18];
2337 u8 transport_domain[0x18];
2339 u8 rx_hash_toeplitz_key[10][0x20];
2341 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2343 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2345 u8 reserved_9[0x4c0];
2349 MLX5_SRQC_STATE_GOOD = 0x0,
2350 MLX5_SRQC_STATE_ERROR = 0x1,
2353 struct mlx5_ifc_srqc_bits {
2355 u8 log_srq_size[0x4];
2356 u8 reserved_0[0x18];
2358 u8 wq_signature[0x1];
2363 u8 log_rq_stride[0x3];
2366 u8 page_offset[0x6];
2370 u8 reserved_4[0x20];
2373 u8 log_page_size[0x6];
2374 u8 reserved_6[0x18];
2376 u8 reserved_7[0x20];
2384 u8 reserved_9[0x40];
2388 u8 reserved_10[0x80];
2392 MLX5_SQC_STATE_RST = 0x0,
2393 MLX5_SQC_STATE_RDY = 0x1,
2394 MLX5_SQC_STATE_ERR = 0x3,
2397 struct mlx5_ifc_sqc_bits {
2401 u8 flush_in_error_en[0x1];
2402 u8 allow_multi_pkt_send_wqe[0x1];
2403 u8 min_wqe_inline_mode[0x3];
2407 u8 reserved_0[0x12];
2410 u8 user_index[0x18];
2415 u8 reserved_3[0x80];
2417 u8 qos_para_vport_number[0x10];
2418 u8 packet_pacing_rate_limit_index[0x10];
2420 u8 tis_lst_sz[0x10];
2421 u8 reserved_4[0x10];
2423 u8 reserved_5[0x40];
2428 struct mlx5_ifc_wq_bits wq;
2432 MLX5_TSAR_TYPE_DWRR = 0,
2433 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2434 MLX5_TSAR_TYPE_ETS = 2
2437 struct mlx5_ifc_tsar_element_attributes_bits {
2440 u8 reserved_1[0x10];
2443 struct mlx5_ifc_vport_element_attributes_bits {
2444 u8 reserved_0[0x10];
2445 u8 vport_number[0x10];
2448 struct mlx5_ifc_vport_tc_element_attributes_bits {
2449 u8 traffic_class[0x10];
2450 u8 vport_number[0x10];
2453 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2454 u8 reserved_0[0x0C];
2455 u8 traffic_class[0x04];
2456 u8 qos_para_vport_number[0x10];
2460 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2461 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2462 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2463 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2466 struct mlx5_ifc_scheduling_context_bits {
2467 u8 element_type[0x8];
2468 u8 reserved_at_8[0x18];
2470 u8 element_attributes[0x20];
2472 u8 parent_element_id[0x20];
2474 u8 reserved_at_60[0x40];
2478 u8 max_average_bw[0x20];
2480 u8 reserved_at_e0[0x120];
2483 struct mlx5_ifc_rqtc_bits {
2484 u8 reserved_0[0xa0];
2486 u8 reserved_1[0x10];
2487 u8 rqt_max_size[0x10];
2489 u8 reserved_2[0x10];
2490 u8 rqt_actual_size[0x10];
2492 u8 reserved_3[0x6a0];
2494 struct mlx5_ifc_rq_num_bits rq_num[0];
2498 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2499 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2503 MLX5_RQC_STATE_RST = 0x0,
2504 MLX5_RQC_STATE_RDY = 0x1,
2505 MLX5_RQC_STATE_ERR = 0x3,
2509 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
2510 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
2513 struct mlx5_ifc_rqc_bits {
2515 u8 delay_drop_en[0x1];
2516 u8 scatter_fcs[0x1];
2517 u8 vlan_strip_disable[0x1];
2518 u8 mem_rq_type[0x4];
2521 u8 flush_in_error_en[0x1];
2522 u8 reserved_2[0x12];
2525 u8 user_index[0x18];
2530 u8 counter_set_id[0x8];
2531 u8 reserved_5[0x18];
2536 u8 reserved_7[0xe0];
2538 struct mlx5_ifc_wq_bits wq;
2542 MLX5_RMPC_STATE_RDY = 0x1,
2543 MLX5_RMPC_STATE_ERR = 0x3,
2546 struct mlx5_ifc_rmpc_bits {
2549 u8 reserved_1[0x14];
2551 u8 basic_cyclic_rcv_wqe[0x1];
2552 u8 reserved_2[0x1f];
2554 u8 reserved_3[0x140];
2556 struct mlx5_ifc_wq_bits wq;
2560 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2561 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1,
2562 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2,
2565 struct mlx5_ifc_nic_vport_context_bits {
2567 u8 min_wqe_inline_mode[0x3];
2568 u8 reserved_1[0x15];
2569 u8 disable_mc_local_lb[0x1];
2570 u8 disable_uc_local_lb[0x1];
2573 u8 arm_change_event[0x1];
2574 u8 reserved_2[0x1a];
2575 u8 event_on_mtu[0x1];
2576 u8 event_on_promisc_change[0x1];
2577 u8 event_on_vlan_change[0x1];
2578 u8 event_on_mc_address_change[0x1];
2579 u8 event_on_uc_address_change[0x1];
2581 u8 reserved_3[0xe0];
2583 u8 reserved_4[0x10];
2586 u8 system_image_guid[0x40];
2592 u8 reserved_5[0x140];
2594 u8 qkey_violation_counter[0x10];
2595 u8 reserved_6[0x10];
2597 u8 reserved_7[0x420];
2601 u8 promisc_all[0x1];
2603 u8 allowed_list_type[0x3];
2605 u8 allowed_list_size[0xc];
2607 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2609 u8 reserved_10[0x20];
2611 u8 current_uc_mac_address[0][0x40];
2615 MLX5_ACCESS_MODE_PA = 0x0,
2616 MLX5_ACCESS_MODE_MTT = 0x1,
2617 MLX5_ACCESS_MODE_KLM = 0x2,
2620 struct mlx5_ifc_mkc_bits {
2621 u8 reserved_at_0[0x1];
2623 u8 reserved_at_2[0x1];
2624 u8 access_mode_4_2[0x3];
2625 u8 reserved_at_6[0x7];
2626 u8 relaxed_ordering_write[0x1];
2627 u8 reserved_at_e[0x1];
2628 u8 small_fence_on_rdma_read_response[0x1];
2635 u8 access_mode[0x2];
2641 u8 reserved_3[0x20];
2647 u8 expected_sigerr_count[0x1];
2652 u8 start_addr[0x40];
2656 u8 bsf_octword_size[0x20];
2658 u8 reserved_6[0x80];
2660 u8 translations_octword_size[0x20];
2662 u8 reserved_7[0x1b];
2663 u8 log_page_size[0x5];
2665 u8 reserved_8[0x20];
2668 struct mlx5_ifc_pkey_bits {
2669 u8 reserved_0[0x10];
2673 struct mlx5_ifc_array128_auto_bits {
2674 u8 array128_auto[16][0x8];
2678 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0,
2679 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1,
2680 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2,
2684 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1,
2685 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2,
2686 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
2687 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4,
2688 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5,
2689 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6,
2690 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
2694 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0,
2695 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1,
2696 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2,
2700 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1,
2701 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2,
2702 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
2703 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4,
2707 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1,
2708 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2,
2709 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
2710 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4,
2713 struct mlx5_ifc_hca_vport_context_bits {
2714 u8 field_select[0x20];
2716 u8 reserved_0[0xe0];
2718 u8 sm_virt_aware[0x1];
2721 u8 grh_required[0x1];
2723 u8 min_wqe_inline_mode[0x3];
2725 u8 port_physical_state[0x4];
2726 u8 vport_state_policy[0x4];
2728 u8 vport_state[0x4];
2730 u8 reserved_3[0x20];
2732 u8 system_image_guid[0x40];
2740 u8 cap_mask1_field_select[0x20];
2744 u8 cap_mask2_field_select[0x20];
2746 u8 reserved_4[0x80];
2750 u8 init_type_reply[0x4];
2752 u8 subnet_timeout[0x5];
2758 u8 qkey_violation_counter[0x10];
2759 u8 pkey_violation_counter[0x10];
2761 u8 reserved_7[0xca0];
2764 union mlx5_ifc_hca_cap_union_bits {
2765 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2766 struct mlx5_ifc_odp_cap_bits odp_cap;
2767 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2768 struct mlx5_ifc_roce_cap_bits roce_cap;
2769 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2770 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2771 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2772 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2773 struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2774 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2775 struct mlx5_ifc_qos_cap_bits qos_cap;
2776 struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2777 u8 reserved_0[0x8000];
2781 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2782 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2785 struct mlx5_ifc_flow_table_context_bits {
2788 u8 reserved_at_2[0x2];
2789 u8 table_miss_action[0x4];
2791 u8 reserved_at_10[0x8];
2794 u8 reserved_at_20[0x8];
2795 u8 table_miss_id[0x18];
2797 u8 reserved_at_40[0x8];
2798 u8 lag_master_next_table_id[0x18];
2800 u8 reserved_at_60[0xe0];
2803 struct mlx5_ifc_esw_vport_context_bits {
2805 u8 vport_svlan_strip[0x1];
2806 u8 vport_cvlan_strip[0x1];
2807 u8 vport_svlan_insert[0x1];
2808 u8 vport_cvlan_insert[0x2];
2809 u8 reserved_1[0x18];
2811 u8 reserved_2[0x20];
2820 u8 reserved_3[0x7a0];
2824 MLX5_EQC_STATUS_OK = 0x0,
2825 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2829 MLX5_EQ_STATE_ARMED = 0x9,
2830 MLX5_EQ_STATE_FIRED = 0xa,
2833 struct mlx5_ifc_eqc_bits {
2842 u8 reserved_3[0x20];
2844 u8 reserved_4[0x14];
2845 u8 page_offset[0x6];
2849 u8 log_eq_size[0x5];
2852 u8 reserved_7[0x20];
2854 u8 reserved_8[0x18];
2858 u8 log_page_size[0x5];
2859 u8 reserved_10[0x18];
2861 u8 reserved_11[0x60];
2863 u8 reserved_12[0x8];
2864 u8 consumer_counter[0x18];
2866 u8 reserved_13[0x8];
2867 u8 producer_counter[0x18];
2869 u8 reserved_14[0x80];
2873 MLX5_DCTC_STATE_ACTIVE = 0x0,
2874 MLX5_DCTC_STATE_DRAINING = 0x1,
2875 MLX5_DCTC_STATE_DRAINED = 0x2,
2879 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2880 MLX5_DCTC_CS_RES_NA = 0x1,
2881 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2885 MLX5_DCTC_MTU_256_BYTES = 0x1,
2886 MLX5_DCTC_MTU_512_BYTES = 0x2,
2887 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2888 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2889 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2892 struct mlx5_ifc_dctc_bits {
2895 u8 reserved_1[0x18];
2898 u8 user_index[0x18];
2903 u8 counter_set_id[0x8];
2904 u8 atomic_mode[0x4];
2908 u8 atomic_like_write_en[0x1];
2909 u8 latency_sensitive[0x1];
2916 u8 min_rnr_nak[0x5];
2926 u8 reserved_10[0x4];
2927 u8 flow_label[0x14];
2929 u8 dc_access_key[0x40];
2931 u8 reserved_11[0x5];
2934 u8 pkey_index[0x10];
2936 u8 reserved_12[0x8];
2937 u8 my_addr_index[0x8];
2938 u8 reserved_13[0x8];
2941 u8 dc_access_key_violation_count[0x20];
2943 u8 reserved_14[0x14];
2949 u8 reserved_15[0x40];
2953 MLX5_CQC_STATUS_OK = 0x0,
2954 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2955 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2964 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2965 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2969 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6,
2970 MLX5_CQ_STATE_ARMED = 0x9,
2971 MLX5_CQ_STATE_FIRED = 0xa,
2974 struct mlx5_ifc_cqc_bits {
2980 u8 scqe_break_moderation_en[0x1];
2982 u8 cq_period_mode[0x2];
2983 u8 cqe_compression_en[0x1];
2984 u8 mini_cqe_res_format[0x2];
2988 u8 reserved_3[0x20];
2990 u8 reserved_4[0x14];
2991 u8 page_offset[0x6];
2995 u8 log_cq_size[0x5];
3000 u8 cq_max_count[0x10];
3002 u8 reserved_8[0x18];
3006 u8 log_page_size[0x5];
3007 u8 reserved_10[0x18];
3009 u8 reserved_11[0x20];
3011 u8 reserved_12[0x8];
3012 u8 last_notified_index[0x18];
3014 u8 reserved_13[0x8];
3015 u8 last_solicit_index[0x18];
3017 u8 reserved_14[0x8];
3018 u8 consumer_counter[0x18];
3020 u8 reserved_15[0x8];
3021 u8 producer_counter[0x18];
3023 u8 reserved_16[0x40];
3028 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3029 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3030 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3031 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3032 u8 reserved_0[0x800];
3035 struct mlx5_ifc_query_adapter_param_block_bits {
3036 u8 reserved_0[0xc0];
3039 u8 ieee_vendor_id[0x18];
3041 u8 reserved_2[0x10];
3042 u8 vsd_vendor_id[0x10];
3046 u8 vsd_contd_psid[16][0x8];
3049 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3050 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3051 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3052 u8 reserved_0[0x20];
3055 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3056 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3057 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3058 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3059 u8 reserved_0[0x20];
3062 struct mlx5_ifc_bufferx_reg_bits {
3069 u8 xoff_threshold[0x10];
3070 u8 xon_threshold[0x10];
3073 struct mlx5_ifc_config_item_bits {
3076 u8 header_type[0x2];
3078 u8 default_location[0x1];
3086 u8 reserved_4[0x10];
3090 struct mlx5_ifc_nodnic_port_config_reg_bits {
3091 struct mlx5_ifc_nodnic_event_word_bits event;
3096 u8 promisc_multicast_en[0x1];
3097 u8 reserved_0[0x17];
3098 u8 receive_filter_en[0x5];
3100 u8 reserved_1[0x10];
3105 u8 receive_filters_mgid_mac[64][0x8];
3109 u8 reserved_2[0x10];
3116 u8 completion_address_63_32[0x20];
3118 u8 completion_address_31_12[0x14];
3120 u8 log_cq_size[0x6];
3122 u8 working_buffer_address_63_32[0x20];
3124 u8 working_buffer_address_31_12[0x14];
3127 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3129 u8 pkey_index[0x10];
3132 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3134 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3136 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3138 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3140 u8 reserved_6[0x400];
3143 union mlx5_ifc_event_auto_bits {
3144 struct mlx5_ifc_comp_event_bits comp_event;
3145 struct mlx5_ifc_dct_events_bits dct_events;
3146 struct mlx5_ifc_qp_events_bits qp_events;
3147 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3148 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3149 struct mlx5_ifc_cq_error_bits cq_error;
3150 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3151 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3152 struct mlx5_ifc_gpio_event_bits gpio_event;
3153 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3154 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3155 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3156 struct mlx5_ifc_pages_req_event_bits pages_req_event;
3157 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3158 u8 reserved_0[0xe0];
3161 struct mlx5_ifc_health_buffer_bits {
3162 u8 reserved_0[0x100];
3164 u8 assert_existptr[0x20];
3166 u8 assert_callra[0x20];
3168 u8 reserved_1[0x40];
3170 u8 fw_version[0x20];
3174 u8 reserved_2[0x20];
3176 u8 irisc_index[0x8];
3181 struct mlx5_ifc_register_loopback_control_bits {
3185 u8 reserved_1[0x10];
3187 u8 reserved_2[0x60];
3190 struct mlx5_ifc_lrh_bits {
3202 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3203 u8 reserved_0[0x40];
3205 u8 reserved_1[0x10];
3210 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3211 u8 reserved_0[0x40];
3213 u8 rol_mode_valid[0x1];
3214 u8 wol_mode_valid[0x1];
3219 u8 reserved_2[0x7a0];
3222 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3223 u8 virtual_mac_en[0x1];
3225 u8 reserved_0[0x1e];
3227 u8 reserved_1[0x40];
3229 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3231 u8 reserved_2[0x760];
3234 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3235 u8 virtual_mac_en[0x1];
3237 u8 reserved_0[0x1e];
3239 struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3241 struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3243 u8 reserved_1[0x760];
3246 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3247 struct mlx5_ifc_fw_version_bits fw_version;
3249 u8 reserved_0[0x10];
3250 u8 hash_signature[0x10];
3254 u8 reserved_1[0x6e0];
3257 struct mlx5_ifc_icmd_query_cap_in_bits {
3258 u8 reserved_0[0x10];
3259 u8 capability_group[0x10];
3262 struct mlx5_ifc_icmd_query_cap_general_bits {
3264 u8 fw_info_psid[0x1];
3265 u8 reserved_0[0x1e];
3267 u8 reserved_1[0x16];
3280 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3282 u8 reserved_0[0x18];
3284 u8 reserved_1[0x7e0];
3287 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3289 u8 reserved_0[0x18];
3291 u8 reserved_1[0x7e0];
3294 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3295 u8 address_hi[0x20];
3297 u8 address_lo[0x20];
3299 u8 reserved_0[0x7c0];
3302 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3303 u8 reserved_0[0x20];
3305 u8 address_hi[0x20];
3307 u8 address_lo[0x20];
3309 u8 reserved_1[0x7a0];
3312 struct mlx5_ifc_icmd_access_reg_out_bits {
3313 u8 reserved_0[0x11];
3317 u8 register_id[0x10];
3318 u8 reserved_2[0x10];
3320 u8 reserved_3[0x40];
3324 u8 reserved_5[0x10];
3326 u8 register_data[0][0x20];
3330 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1,
3331 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2,
3334 struct mlx5_ifc_icmd_access_reg_in_bits {
3337 u8 reserved_0[0x10];
3339 u8 register_id[0x10];
3344 u8 reserved_2[0x40];
3348 u8 reserved_3[0x10];
3350 u8 register_data[0][0x20];
3354 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3355 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3358 struct mlx5_ifc_teardown_hca_out_bits {
3360 u8 reserved_0[0x18];
3364 u8 reserved_1[0x3f];
3370 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3371 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3372 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3375 struct mlx5_ifc_teardown_hca_in_bits {
3377 u8 reserved_0[0x10];
3379 u8 reserved_1[0x10];
3382 u8 reserved_2[0x10];
3385 u8 reserved_3[0x20];
3388 struct mlx5_ifc_set_delay_drop_params_out_bits {
3390 u8 reserved_at_8[0x18];
3394 u8 reserved_at_40[0x40];
3397 struct mlx5_ifc_set_delay_drop_params_in_bits {
3399 u8 reserved_at_10[0x10];
3401 u8 reserved_at_20[0x10];
3404 u8 reserved_at_40[0x20];
3406 u8 reserved_at_60[0x10];
3407 u8 delay_drop_timeout[0x10];
3410 struct mlx5_ifc_query_delay_drop_params_out_bits {
3412 u8 reserved_at_8[0x18];
3416 u8 reserved_at_40[0x20];
3418 u8 reserved_at_60[0x10];
3419 u8 delay_drop_timeout[0x10];
3422 struct mlx5_ifc_query_delay_drop_params_in_bits {
3424 u8 reserved_at_10[0x10];
3426 u8 reserved_at_20[0x10];
3429 u8 reserved_at_40[0x40];
3432 struct mlx5_ifc_suspend_qp_out_bits {
3434 u8 reserved_0[0x18];
3438 u8 reserved_1[0x40];
3441 struct mlx5_ifc_suspend_qp_in_bits {
3443 u8 reserved_0[0x10];
3445 u8 reserved_1[0x10];
3451 u8 reserved_3[0x20];
3454 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3456 u8 reserved_0[0x18];
3460 u8 reserved_1[0x40];
3463 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3465 u8 reserved_0[0x10];
3467 u8 reserved_1[0x10];
3473 u8 reserved_3[0x20];
3475 u8 opt_param_mask[0x20];
3477 u8 reserved_4[0x20];
3479 struct mlx5_ifc_qpc_bits qpc;
3481 u8 reserved_5[0x80];
3484 struct mlx5_ifc_sqd2rts_qp_out_bits {
3486 u8 reserved_0[0x18];
3490 u8 reserved_1[0x40];
3493 struct mlx5_ifc_sqd2rts_qp_in_bits {
3495 u8 reserved_0[0x10];
3497 u8 reserved_1[0x10];
3503 u8 reserved_3[0x20];
3505 u8 opt_param_mask[0x20];
3507 u8 reserved_4[0x20];
3509 struct mlx5_ifc_qpc_bits qpc;
3511 u8 reserved_5[0x80];
3514 struct mlx5_ifc_set_wol_rol_out_bits {
3516 u8 reserved_0[0x18];
3520 u8 reserved_1[0x40];
3523 struct mlx5_ifc_set_wol_rol_in_bits {
3525 u8 reserved_0[0x10];
3527 u8 reserved_1[0x10];
3530 u8 rol_mode_valid[0x1];
3531 u8 wol_mode_valid[0x1];
3536 u8 reserved_3[0x20];
3539 struct mlx5_ifc_set_roce_address_out_bits {
3541 u8 reserved_0[0x18];
3545 u8 reserved_1[0x40];
3548 struct mlx5_ifc_set_roce_address_in_bits {
3550 u8 reserved_0[0x10];
3552 u8 reserved_1[0x10];
3555 u8 roce_address_index[0x10];
3556 u8 reserved_2[0x10];
3558 u8 reserved_3[0x20];
3560 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3563 struct mlx5_ifc_set_rdb_out_bits {
3565 u8 reserved_0[0x18];
3569 u8 reserved_1[0x40];
3572 struct mlx5_ifc_set_rdb_in_bits {
3574 u8 reserved_0[0x10];
3576 u8 reserved_1[0x10];
3582 u8 reserved_3[0x18];
3583 u8 rdb_list_size[0x8];
3585 struct mlx5_ifc_rdbc_bits rdb_context[0];
3588 struct mlx5_ifc_set_mad_demux_out_bits {
3590 u8 reserved_0[0x18];
3594 u8 reserved_1[0x40];
3598 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3599 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3602 struct mlx5_ifc_set_mad_demux_in_bits {
3604 u8 reserved_0[0x10];
3606 u8 reserved_1[0x10];
3609 u8 reserved_2[0x20];
3613 u8 reserved_4[0x18];
3616 struct mlx5_ifc_set_l2_table_entry_out_bits {
3618 u8 reserved_0[0x18];
3622 u8 reserved_1[0x40];
3625 struct mlx5_ifc_set_l2_table_entry_in_bits {
3627 u8 reserved_0[0x10];
3629 u8 reserved_1[0x10];
3632 u8 reserved_2[0x60];
3635 u8 table_index[0x18];
3637 u8 reserved_4[0x20];
3639 u8 reserved_5[0x13];
3643 struct mlx5_ifc_mac_address_layout_bits mac_address;
3645 u8 reserved_6[0xc0];
3648 struct mlx5_ifc_set_issi_out_bits {
3650 u8 reserved_0[0x18];
3654 u8 reserved_1[0x40];
3657 struct mlx5_ifc_set_issi_in_bits {
3659 u8 reserved_0[0x10];
3661 u8 reserved_1[0x10];
3664 u8 reserved_2[0x10];
3665 u8 current_issi[0x10];
3667 u8 reserved_3[0x20];
3670 struct mlx5_ifc_set_hca_cap_out_bits {
3672 u8 reserved_0[0x18];
3676 u8 reserved_1[0x40];
3679 struct mlx5_ifc_set_hca_cap_in_bits {
3681 u8 reserved_0[0x10];
3683 u8 reserved_1[0x10];
3686 u8 reserved_2[0x40];
3688 union mlx5_ifc_hca_cap_union_bits capability;
3692 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3693 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3694 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3695 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3698 struct mlx5_ifc_set_flow_table_root_out_bits {
3700 u8 reserved_0[0x18];
3704 u8 reserved_1[0x40];
3707 struct mlx5_ifc_set_flow_table_root_in_bits {
3709 u8 reserved_0[0x10];
3711 u8 reserved_1[0x10];
3714 u8 other_vport[0x1];
3716 u8 vport_number[0x10];
3718 u8 reserved_3[0x20];
3721 u8 reserved_4[0x18];
3727 u8 underlay_qpn[0x18];
3729 u8 reserved_7[0x120];
3732 struct mlx5_ifc_set_fte_out_bits {
3734 u8 reserved_0[0x18];
3738 u8 reserved_1[0x40];
3741 struct mlx5_ifc_set_fte_in_bits {
3743 u8 reserved_0[0x10];
3745 u8 reserved_1[0x10];
3748 u8 other_vport[0x1];
3750 u8 vport_number[0x10];
3752 u8 reserved_3[0x20];
3755 u8 reserved_4[0x18];
3760 u8 reserved_6[0x18];
3761 u8 modify_enable_mask[0x8];
3763 u8 reserved_7[0x20];
3765 u8 flow_index[0x20];
3767 u8 reserved_8[0xe0];
3769 struct mlx5_ifc_flow_context_bits flow_context;
3772 struct mlx5_ifc_set_driver_version_out_bits {
3774 u8 reserved_0[0x18];
3778 u8 reserved_1[0x40];
3781 struct mlx5_ifc_set_driver_version_in_bits {
3783 u8 reserved_0[0x10];
3785 u8 reserved_1[0x10];
3788 u8 reserved_2[0x40];
3790 u8 driver_version[64][0x8];
3793 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3795 u8 reserved_0[0x18];
3799 u8 reserved_1[0x40];
3802 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3804 u8 reserved_0[0x10];
3806 u8 reserved_1[0x10];
3810 u8 reserved_2[0x1f];
3812 u8 reserved_3[0x160];
3814 struct mlx5_ifc_cmd_pas_bits pas;
3817 struct mlx5_ifc_set_burst_size_out_bits {
3819 u8 reserved_0[0x18];
3823 u8 reserved_1[0x40];
3826 struct mlx5_ifc_set_burst_size_in_bits {
3828 u8 reserved_0[0x10];
3830 u8 reserved_1[0x10];
3833 u8 reserved_2[0x20];
3836 u8 device_burst_size[0x17];
3839 struct mlx5_ifc_rts2rts_qp_out_bits {
3841 u8 reserved_0[0x18];
3845 u8 reserved_1[0x40];
3848 struct mlx5_ifc_rts2rts_qp_in_bits {
3850 u8 reserved_0[0x10];
3852 u8 reserved_1[0x10];
3858 u8 reserved_3[0x20];
3860 u8 opt_param_mask[0x20];
3862 u8 reserved_4[0x20];
3864 struct mlx5_ifc_qpc_bits qpc;
3866 u8 reserved_5[0x80];
3869 struct mlx5_ifc_rtr2rts_qp_out_bits {
3871 u8 reserved_0[0x18];
3875 u8 reserved_1[0x40];
3878 struct mlx5_ifc_rtr2rts_qp_in_bits {
3880 u8 reserved_0[0x10];
3882 u8 reserved_1[0x10];
3888 u8 reserved_3[0x20];
3890 u8 opt_param_mask[0x20];
3892 u8 reserved_4[0x20];
3894 struct mlx5_ifc_qpc_bits qpc;
3896 u8 reserved_5[0x80];
3899 struct mlx5_ifc_rst2init_qp_out_bits {
3901 u8 reserved_0[0x18];
3905 u8 reserved_1[0x40];
3908 struct mlx5_ifc_rst2init_qp_in_bits {
3910 u8 reserved_0[0x10];
3912 u8 reserved_1[0x10];
3918 u8 reserved_3[0x20];
3920 u8 opt_param_mask[0x20];
3922 u8 reserved_4[0x20];
3924 struct mlx5_ifc_qpc_bits qpc;
3926 u8 reserved_5[0x80];
3929 struct mlx5_ifc_resume_qp_out_bits {
3931 u8 reserved_0[0x18];
3935 u8 reserved_1[0x40];
3938 struct mlx5_ifc_resume_qp_in_bits {
3940 u8 reserved_0[0x10];
3942 u8 reserved_1[0x10];
3948 u8 reserved_3[0x20];
3951 struct mlx5_ifc_query_xrc_srq_out_bits {
3953 u8 reserved_0[0x18];
3957 u8 reserved_1[0x40];
3959 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3961 u8 reserved_2[0x600];
3966 struct mlx5_ifc_query_xrc_srq_in_bits {
3968 u8 reserved_0[0x10];
3970 u8 reserved_1[0x10];
3976 u8 reserved_3[0x20];
3979 struct mlx5_ifc_query_wol_rol_out_bits {
3981 u8 reserved_0[0x18];
3985 u8 reserved_1[0x10];
3989 u8 reserved_2[0x20];
3992 struct mlx5_ifc_query_wol_rol_in_bits {
3994 u8 reserved_0[0x10];
3996 u8 reserved_1[0x10];
3999 u8 reserved_2[0x40];
4003 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4004 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4007 struct mlx5_ifc_query_vport_state_out_bits {
4009 u8 reserved_0[0x18];
4013 u8 reserved_1[0x20];
4015 u8 reserved_2[0x18];
4016 u8 admin_state[0x4];
4021 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
4022 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
4023 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
4026 struct mlx5_ifc_query_vport_state_in_bits {
4028 u8 reserved_0[0x10];
4030 u8 reserved_1[0x10];
4033 u8 other_vport[0x1];
4035 u8 vport_number[0x10];
4037 u8 reserved_3[0x20];
4040 struct mlx5_ifc_query_vnic_env_out_bits {
4042 u8 reserved_at_8[0x18];
4046 u8 reserved_at_40[0x40];
4048 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4052 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4055 struct mlx5_ifc_query_vnic_env_in_bits {
4057 u8 reserved_at_10[0x10];
4059 u8 reserved_at_20[0x10];
4062 u8 other_vport[0x1];
4063 u8 reserved_at_41[0xf];
4064 u8 vport_number[0x10];
4066 u8 reserved_at_60[0x20];
4069 struct mlx5_ifc_query_vport_counter_out_bits {
4071 u8 reserved_0[0x18];
4075 u8 reserved_1[0x40];
4077 struct mlx5_ifc_traffic_counter_bits received_errors;
4079 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4081 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4083 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4085 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4087 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4089 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4091 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4093 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4095 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4097 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4099 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4101 u8 reserved_2[0xa00];
4105 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4108 struct mlx5_ifc_query_vport_counter_in_bits {
4110 u8 reserved_0[0x10];
4112 u8 reserved_1[0x10];
4115 u8 other_vport[0x1];
4118 u8 vport_number[0x10];
4120 u8 reserved_3[0x60];
4123 u8 reserved_4[0x1f];
4125 u8 reserved_5[0x20];
4128 struct mlx5_ifc_query_tis_out_bits {
4130 u8 reserved_0[0x18];
4134 u8 reserved_1[0x40];
4136 struct mlx5_ifc_tisc_bits tis_context;
4139 struct mlx5_ifc_query_tis_in_bits {
4141 u8 reserved_0[0x10];
4143 u8 reserved_1[0x10];
4149 u8 reserved_3[0x20];
4152 struct mlx5_ifc_query_tir_out_bits {
4154 u8 reserved_0[0x18];
4158 u8 reserved_1[0xc0];
4160 struct mlx5_ifc_tirc_bits tir_context;
4163 struct mlx5_ifc_query_tir_in_bits {
4165 u8 reserved_0[0x10];
4167 u8 reserved_1[0x10];
4173 u8 reserved_3[0x20];
4176 struct mlx5_ifc_query_srq_out_bits {
4178 u8 reserved_0[0x18];
4182 u8 reserved_1[0x40];
4184 struct mlx5_ifc_srqc_bits srq_context_entry;
4186 u8 reserved_2[0x600];
4191 struct mlx5_ifc_query_srq_in_bits {
4193 u8 reserved_0[0x10];
4195 u8 reserved_1[0x10];
4201 u8 reserved_3[0x20];
4204 struct mlx5_ifc_query_sq_out_bits {
4206 u8 reserved_0[0x18];
4210 u8 reserved_1[0xc0];
4212 struct mlx5_ifc_sqc_bits sq_context;
4215 struct mlx5_ifc_query_sq_in_bits {
4217 u8 reserved_0[0x10];
4219 u8 reserved_1[0x10];
4225 u8 reserved_3[0x20];
4228 struct mlx5_ifc_query_special_contexts_out_bits {
4230 u8 reserved_0[0x18];
4234 u8 dump_fill_mkey[0x20];
4239 struct mlx5_ifc_query_special_contexts_in_bits {
4241 u8 reserved_0[0x10];
4243 u8 reserved_1[0x10];
4246 u8 reserved_2[0x40];
4249 struct mlx5_ifc_query_scheduling_element_out_bits {
4251 u8 reserved_at_8[0x18];
4255 u8 reserved_at_40[0xc0];
4257 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4259 u8 reserved_at_300[0x100];
4263 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4266 struct mlx5_ifc_query_scheduling_element_in_bits {
4268 u8 reserved_at_10[0x10];
4270 u8 reserved_at_20[0x10];
4273 u8 scheduling_hierarchy[0x8];
4274 u8 reserved_at_48[0x18];
4276 u8 scheduling_element_id[0x20];
4278 u8 reserved_at_80[0x180];
4281 struct mlx5_ifc_query_rqt_out_bits {
4283 u8 reserved_0[0x18];
4287 u8 reserved_1[0xc0];
4289 struct mlx5_ifc_rqtc_bits rqt_context;
4292 struct mlx5_ifc_query_rqt_in_bits {
4294 u8 reserved_0[0x10];
4296 u8 reserved_1[0x10];
4302 u8 reserved_3[0x20];
4305 struct mlx5_ifc_query_rq_out_bits {
4307 u8 reserved_0[0x18];
4311 u8 reserved_1[0xc0];
4313 struct mlx5_ifc_rqc_bits rq_context;
4316 struct mlx5_ifc_query_rq_in_bits {
4318 u8 reserved_0[0x10];
4320 u8 reserved_1[0x10];
4326 u8 reserved_3[0x20];
4329 struct mlx5_ifc_query_roce_address_out_bits {
4331 u8 reserved_0[0x18];
4335 u8 reserved_1[0x40];
4337 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4340 struct mlx5_ifc_query_roce_address_in_bits {
4342 u8 reserved_0[0x10];
4344 u8 reserved_1[0x10];
4347 u8 roce_address_index[0x10];
4348 u8 reserved_2[0x10];
4350 u8 reserved_3[0x20];
4353 struct mlx5_ifc_query_rmp_out_bits {
4355 u8 reserved_0[0x18];
4359 u8 reserved_1[0xc0];
4361 struct mlx5_ifc_rmpc_bits rmp_context;
4364 struct mlx5_ifc_query_rmp_in_bits {
4366 u8 reserved_0[0x10];
4368 u8 reserved_1[0x10];
4374 u8 reserved_3[0x20];
4377 struct mlx5_ifc_query_rdb_out_bits {
4379 u8 reserved_0[0x18];
4383 u8 reserved_1[0x20];
4385 u8 reserved_2[0x18];
4386 u8 rdb_list_size[0x8];
4388 struct mlx5_ifc_rdbc_bits rdb_context[0];
4391 struct mlx5_ifc_query_rdb_in_bits {
4393 u8 reserved_0[0x10];
4395 u8 reserved_1[0x10];
4401 u8 reserved_3[0x20];
4404 struct mlx5_ifc_query_qp_out_bits {
4406 u8 reserved_0[0x18];
4410 u8 reserved_1[0x40];
4412 u8 opt_param_mask[0x20];
4414 u8 reserved_2[0x20];
4416 struct mlx5_ifc_qpc_bits qpc;
4418 u8 reserved_3[0x80];
4423 struct mlx5_ifc_query_qp_in_bits {
4425 u8 reserved_0[0x10];
4427 u8 reserved_1[0x10];
4433 u8 reserved_3[0x20];
4436 struct mlx5_ifc_query_q_counter_out_bits {
4438 u8 reserved_0[0x18];
4442 u8 reserved_1[0x40];
4444 u8 rx_write_requests[0x20];
4446 u8 reserved_2[0x20];
4448 u8 rx_read_requests[0x20];
4450 u8 reserved_3[0x20];
4452 u8 rx_atomic_requests[0x20];
4454 u8 reserved_4[0x20];
4456 u8 rx_dct_connect[0x20];
4458 u8 reserved_5[0x20];
4460 u8 out_of_buffer[0x20];
4462 u8 reserved_7[0x20];
4464 u8 out_of_sequence[0x20];
4466 u8 reserved_8[0x20];
4468 u8 duplicate_request[0x20];
4470 u8 reserved_9[0x20];
4472 u8 rnr_nak_retry_err[0x20];
4474 u8 reserved_10[0x20];
4476 u8 packet_seq_err[0x20];
4478 u8 reserved_11[0x20];
4480 u8 implied_nak_seq_err[0x20];
4482 u8 reserved_12[0x20];
4484 u8 local_ack_timeout_err[0x20];
4486 u8 reserved_13[0x20];
4488 u8 resp_rnr_nak[0x20];
4490 u8 reserved_14[0x20];
4492 u8 req_rnr_retries_exceeded[0x20];
4494 u8 reserved_15[0x460];
4497 struct mlx5_ifc_query_q_counter_in_bits {
4499 u8 reserved_0[0x10];
4501 u8 reserved_1[0x10];
4504 u8 reserved_2[0x80];
4507 u8 reserved_3[0x1f];
4509 u8 reserved_4[0x18];
4510 u8 counter_set_id[0x8];
4513 struct mlx5_ifc_query_pages_out_bits {
4515 u8 reserved_0[0x18];
4519 u8 reserved_1[0x10];
4520 u8 function_id[0x10];
4526 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4527 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4528 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4531 struct mlx5_ifc_query_pages_in_bits {
4533 u8 reserved_0[0x10];
4535 u8 reserved_1[0x10];
4538 u8 reserved_2[0x10];
4539 u8 function_id[0x10];
4541 u8 reserved_3[0x20];
4544 struct mlx5_ifc_query_nic_vport_context_out_bits {
4546 u8 reserved_0[0x18];
4550 u8 reserved_1[0x40];
4552 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4555 struct mlx5_ifc_query_nic_vport_context_in_bits {
4557 u8 reserved_0[0x10];
4559 u8 reserved_1[0x10];
4562 u8 other_vport[0x1];
4564 u8 vport_number[0x10];
4567 u8 allowed_list_type[0x3];
4568 u8 reserved_4[0x18];
4571 struct mlx5_ifc_query_mkey_out_bits {
4573 u8 reserved_0[0x18];
4577 u8 reserved_1[0x40];
4579 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4581 u8 reserved_2[0x600];
4583 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4585 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4588 struct mlx5_ifc_query_mkey_in_bits {
4590 u8 reserved_0[0x10];
4592 u8 reserved_1[0x10];
4596 u8 mkey_index[0x18];
4599 u8 reserved_3[0x1f];
4602 struct mlx5_ifc_query_mad_demux_out_bits {
4604 u8 reserved_0[0x18];
4608 u8 reserved_1[0x40];
4610 u8 mad_dumux_parameters_block[0x20];
4613 struct mlx5_ifc_query_mad_demux_in_bits {
4615 u8 reserved_0[0x10];
4617 u8 reserved_1[0x10];
4620 u8 reserved_2[0x40];
4623 struct mlx5_ifc_query_l2_table_entry_out_bits {
4625 u8 reserved_0[0x18];
4629 u8 reserved_1[0xa0];
4631 u8 reserved_2[0x13];
4635 struct mlx5_ifc_mac_address_layout_bits mac_address;
4637 u8 reserved_3[0xc0];
4640 struct mlx5_ifc_query_l2_table_entry_in_bits {
4642 u8 reserved_0[0x10];
4644 u8 reserved_1[0x10];
4647 u8 reserved_2[0x60];
4650 u8 table_index[0x18];
4652 u8 reserved_4[0x140];
4655 struct mlx5_ifc_query_issi_out_bits {
4657 u8 reserved_0[0x18];
4661 u8 reserved_1[0x10];
4662 u8 current_issi[0x10];
4664 u8 reserved_2[0xa0];
4666 u8 supported_issi_reserved[76][0x8];
4667 u8 supported_issi_dw0[0x20];
4670 struct mlx5_ifc_query_issi_in_bits {
4672 u8 reserved_0[0x10];
4674 u8 reserved_1[0x10];
4677 u8 reserved_2[0x40];
4680 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4682 u8 reserved_0[0x18];
4686 u8 reserved_1[0x40];
4688 struct mlx5_ifc_pkey_bits pkey[0];
4691 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4693 u8 reserved_0[0x10];
4695 u8 reserved_1[0x10];
4698 u8 other_vport[0x1];
4701 u8 vport_number[0x10];
4703 u8 reserved_3[0x10];
4704 u8 pkey_index[0x10];
4707 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4709 u8 reserved_0[0x18];
4713 u8 reserved_1[0x20];
4716 u8 reserved_2[0x10];
4718 struct mlx5_ifc_array128_auto_bits gid[0];
4721 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4723 u8 reserved_0[0x10];
4725 u8 reserved_1[0x10];
4728 u8 other_vport[0x1];
4731 u8 vport_number[0x10];
4733 u8 reserved_3[0x10];
4737 struct mlx5_ifc_query_hca_vport_context_out_bits {
4739 u8 reserved_0[0x18];
4743 u8 reserved_1[0x40];
4745 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4748 struct mlx5_ifc_query_hca_vport_context_in_bits {
4750 u8 reserved_0[0x10];
4752 u8 reserved_1[0x10];
4755 u8 other_vport[0x1];
4758 u8 vport_number[0x10];
4760 u8 reserved_3[0x20];
4763 struct mlx5_ifc_query_hca_cap_out_bits {
4765 u8 reserved_0[0x18];
4769 u8 reserved_1[0x40];
4771 union mlx5_ifc_hca_cap_union_bits capability;
4774 struct mlx5_ifc_query_hca_cap_in_bits {
4776 u8 reserved_0[0x10];
4778 u8 reserved_1[0x10];
4781 u8 reserved_2[0x40];
4784 struct mlx5_ifc_query_flow_table_out_bits {
4786 u8 reserved_at_8[0x18];
4790 u8 reserved_at_40[0x80];
4792 struct mlx5_ifc_flow_table_context_bits flow_table_context;
4795 struct mlx5_ifc_query_flow_table_in_bits {
4797 u8 reserved_0[0x10];
4799 u8 reserved_1[0x10];
4802 u8 other_vport[0x1];
4804 u8 vport_number[0x10];
4806 u8 reserved_3[0x20];
4809 u8 reserved_4[0x18];
4814 u8 reserved_6[0x140];
4817 struct mlx5_ifc_query_fte_out_bits {
4819 u8 reserved_0[0x18];
4823 u8 reserved_1[0x1c0];
4825 struct mlx5_ifc_flow_context_bits flow_context;
4828 struct mlx5_ifc_query_fte_in_bits {
4830 u8 reserved_0[0x10];
4832 u8 reserved_1[0x10];
4835 u8 other_vport[0x1];
4837 u8 vport_number[0x10];
4839 u8 reserved_3[0x20];
4842 u8 reserved_4[0x18];
4847 u8 reserved_6[0x40];
4849 u8 flow_index[0x20];
4851 u8 reserved_7[0xe0];
4855 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4856 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4857 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4860 struct mlx5_ifc_query_flow_group_out_bits {
4862 u8 reserved_0[0x18];
4866 u8 reserved_1[0xa0];
4868 u8 start_flow_index[0x20];
4870 u8 reserved_2[0x20];
4872 u8 end_flow_index[0x20];
4874 u8 reserved_3[0xa0];
4876 u8 reserved_4[0x18];
4877 u8 match_criteria_enable[0x8];
4879 struct mlx5_ifc_fte_match_param_bits match_criteria;
4881 u8 reserved_5[0xe00];
4884 struct mlx5_ifc_query_flow_group_in_bits {
4886 u8 reserved_0[0x10];
4888 u8 reserved_1[0x10];
4891 u8 other_vport[0x1];
4893 u8 vport_number[0x10];
4895 u8 reserved_3[0x20];
4898 u8 reserved_4[0x18];
4905 u8 reserved_6[0x120];
4908 struct mlx5_ifc_query_flow_counter_out_bits {
4910 u8 reserved_at_8[0x18];
4914 u8 reserved_at_40[0x40];
4916 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4919 struct mlx5_ifc_query_flow_counter_in_bits {
4921 u8 reserved_at_10[0x10];
4923 u8 reserved_at_20[0x10];
4926 u8 reserved_at_40[0x80];
4929 u8 reserved_at_c1[0xf];
4930 u8 num_of_counters[0x10];
4932 u8 reserved_at_e0[0x10];
4933 u8 flow_counter_id[0x10];
4936 struct mlx5_ifc_query_esw_vport_context_out_bits {
4938 u8 reserved_0[0x18];
4942 u8 reserved_1[0x40];
4944 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4947 struct mlx5_ifc_query_esw_vport_context_in_bits {
4949 u8 reserved_0[0x10];
4951 u8 reserved_1[0x10];
4954 u8 other_vport[0x1];
4956 u8 vport_number[0x10];
4958 u8 reserved_3[0x20];
4961 struct mlx5_ifc_query_eq_out_bits {
4963 u8 reserved_0[0x18];
4967 u8 reserved_1[0x40];
4969 struct mlx5_ifc_eqc_bits eq_context_entry;
4971 u8 reserved_2[0x40];
4973 u8 event_bitmask[0x40];
4975 u8 reserved_3[0x580];
4980 struct mlx5_ifc_query_eq_in_bits {
4982 u8 reserved_0[0x10];
4984 u8 reserved_1[0x10];
4987 u8 reserved_2[0x18];
4990 u8 reserved_3[0x20];
4993 struct mlx5_ifc_query_dct_out_bits {
4995 u8 reserved_0[0x18];
4999 u8 reserved_1[0x40];
5001 struct mlx5_ifc_dctc_bits dct_context_entry;
5003 u8 reserved_2[0x180];
5006 struct mlx5_ifc_query_dct_in_bits {
5008 u8 reserved_0[0x10];
5010 u8 reserved_1[0x10];
5016 u8 reserved_3[0x20];
5019 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5021 u8 reserved_0[0x18];
5026 u8 reserved_1[0x1f];
5028 u8 reserved_2[0x160];
5030 struct mlx5_ifc_cmd_pas_bits pas;
5033 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5035 u8 reserved_0[0x10];
5037 u8 reserved_1[0x10];
5040 u8 reserved_2[0x40];
5043 struct mlx5_ifc_query_cq_out_bits {
5045 u8 reserved_0[0x18];
5049 u8 reserved_1[0x40];
5051 struct mlx5_ifc_cqc_bits cq_context;
5053 u8 reserved_2[0x600];
5058 struct mlx5_ifc_query_cq_in_bits {
5060 u8 reserved_0[0x10];
5062 u8 reserved_1[0x10];
5068 u8 reserved_3[0x20];
5071 struct mlx5_ifc_query_cong_status_out_bits {
5073 u8 reserved_0[0x18];
5077 u8 reserved_1[0x20];
5081 u8 reserved_2[0x1e];
5084 struct mlx5_ifc_query_cong_status_in_bits {
5086 u8 reserved_0[0x10];
5088 u8 reserved_1[0x10];
5091 u8 reserved_2[0x18];
5093 u8 cong_protocol[0x4];
5095 u8 reserved_3[0x20];
5098 struct mlx5_ifc_query_cong_statistics_out_bits {
5100 u8 reserved_0[0x18];
5104 u8 reserved_1[0x40];
5106 u8 rp_cur_flows[0x20];
5110 u8 rp_cnp_ignored_high[0x20];
5112 u8 rp_cnp_ignored_low[0x20];
5114 u8 rp_cnp_handled_high[0x20];
5116 u8 rp_cnp_handled_low[0x20];
5118 u8 reserved_2[0x100];
5120 u8 time_stamp_high[0x20];
5122 u8 time_stamp_low[0x20];
5124 u8 accumulators_period[0x20];
5126 u8 np_ecn_marked_roce_packets_high[0x20];
5128 u8 np_ecn_marked_roce_packets_low[0x20];
5130 u8 np_cnp_sent_high[0x20];
5132 u8 np_cnp_sent_low[0x20];
5134 u8 reserved_3[0x560];
5137 struct mlx5_ifc_query_cong_statistics_in_bits {
5139 u8 reserved_0[0x10];
5141 u8 reserved_1[0x10];
5145 u8 reserved_2[0x1f];
5147 u8 reserved_3[0x20];
5150 struct mlx5_ifc_query_cong_params_out_bits {
5152 u8 reserved_0[0x18];
5156 u8 reserved_1[0x40];
5158 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5161 struct mlx5_ifc_query_cong_params_in_bits {
5163 u8 reserved_0[0x10];
5165 u8 reserved_1[0x10];
5168 u8 reserved_2[0x1c];
5169 u8 cong_protocol[0x4];
5171 u8 reserved_3[0x20];
5174 struct mlx5_ifc_query_burst_size_out_bits {
5176 u8 reserved_0[0x18];
5180 u8 reserved_1[0x20];
5183 u8 device_burst_size[0x17];
5186 struct mlx5_ifc_query_burst_size_in_bits {
5188 u8 reserved_0[0x10];
5190 u8 reserved_1[0x10];
5193 u8 reserved_2[0x40];
5196 struct mlx5_ifc_query_adapter_out_bits {
5198 u8 reserved_0[0x18];
5202 u8 reserved_1[0x40];
5204 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5207 struct mlx5_ifc_query_adapter_in_bits {
5209 u8 reserved_0[0x10];
5211 u8 reserved_1[0x10];
5214 u8 reserved_2[0x40];
5217 struct mlx5_ifc_qp_2rst_out_bits {
5219 u8 reserved_0[0x18];
5223 u8 reserved_1[0x40];
5226 struct mlx5_ifc_qp_2rst_in_bits {
5228 u8 reserved_0[0x10];
5230 u8 reserved_1[0x10];
5236 u8 reserved_3[0x20];
5239 struct mlx5_ifc_qp_2err_out_bits {
5241 u8 reserved_0[0x18];
5245 u8 reserved_1[0x40];
5248 struct mlx5_ifc_qp_2err_in_bits {
5250 u8 reserved_0[0x10];
5252 u8 reserved_1[0x10];
5258 u8 reserved_3[0x20];
5261 struct mlx5_ifc_para_vport_element_bits {
5262 u8 reserved_at_0[0xc];
5263 u8 traffic_class[0x4];
5264 u8 qos_para_vport_number[0x10];
5267 struct mlx5_ifc_page_fault_resume_out_bits {
5269 u8 reserved_0[0x18];
5273 u8 reserved_1[0x40];
5276 struct mlx5_ifc_page_fault_resume_in_bits {
5278 u8 reserved_0[0x10];
5280 u8 reserved_1[0x10];
5290 u8 reserved_3[0x20];
5293 struct mlx5_ifc_nop_out_bits {
5295 u8 reserved_0[0x18];
5299 u8 reserved_1[0x40];
5302 struct mlx5_ifc_nop_in_bits {
5304 u8 reserved_0[0x10];
5306 u8 reserved_1[0x10];
5309 u8 reserved_2[0x40];
5312 struct mlx5_ifc_modify_vport_state_out_bits {
5314 u8 reserved_0[0x18];
5318 u8 reserved_1[0x40];
5322 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0,
5323 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
5324 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
5328 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0,
5329 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1,
5330 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2,
5333 struct mlx5_ifc_modify_vport_state_in_bits {
5335 u8 reserved_0[0x10];
5337 u8 reserved_1[0x10];
5340 u8 other_vport[0x1];
5342 u8 vport_number[0x10];
5344 u8 reserved_3[0x18];
5345 u8 admin_state[0x4];
5349 struct mlx5_ifc_modify_tis_out_bits {
5351 u8 reserved_0[0x18];
5355 u8 reserved_1[0x40];
5358 struct mlx5_ifc_modify_tis_bitmask_bits {
5359 u8 reserved_at_0[0x20];
5361 u8 reserved_at_20[0x1d];
5362 u8 lag_tx_port_affinity[0x1];
5363 u8 strict_lag_tx_port_affinity[0x1];
5367 struct mlx5_ifc_modify_tis_in_bits {
5369 u8 reserved_0[0x10];
5371 u8 reserved_1[0x10];
5377 u8 reserved_3[0x20];
5379 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5381 u8 reserved_4[0x40];
5383 struct mlx5_ifc_tisc_bits ctx;
5386 struct mlx5_ifc_modify_tir_out_bits {
5388 u8 reserved_0[0x18];
5392 u8 reserved_1[0x40];
5397 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5398 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1
5401 struct mlx5_ifc_modify_tir_in_bits {
5403 u8 reserved_0[0x10];
5405 u8 reserved_1[0x10];
5411 u8 reserved_3[0x20];
5413 u8 modify_bitmask[0x40];
5415 u8 reserved_4[0x40];
5417 struct mlx5_ifc_tirc_bits tir_context;
5420 struct mlx5_ifc_modify_sq_out_bits {
5422 u8 reserved_0[0x18];
5426 u8 reserved_1[0x40];
5429 struct mlx5_ifc_modify_sq_in_bits {
5431 u8 reserved_0[0x10];
5433 u8 reserved_1[0x10];
5440 u8 reserved_3[0x20];
5442 u8 modify_bitmask[0x40];
5444 u8 reserved_4[0x40];
5446 struct mlx5_ifc_sqc_bits ctx;
5449 struct mlx5_ifc_modify_scheduling_element_out_bits {
5451 u8 reserved_at_8[0x18];
5455 u8 reserved_at_40[0x1c0];
5459 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5463 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1,
5464 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2,
5467 struct mlx5_ifc_modify_scheduling_element_in_bits {
5469 u8 reserved_at_10[0x10];
5471 u8 reserved_at_20[0x10];
5474 u8 scheduling_hierarchy[0x8];
5475 u8 reserved_at_48[0x18];
5477 u8 scheduling_element_id[0x20];
5479 u8 reserved_at_80[0x20];
5481 u8 modify_bitmask[0x20];
5483 u8 reserved_at_c0[0x40];
5485 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5487 u8 reserved_at_300[0x100];
5490 struct mlx5_ifc_modify_rqt_out_bits {
5492 u8 reserved_0[0x18];
5496 u8 reserved_1[0x40];
5499 struct mlx5_ifc_modify_rqt_in_bits {
5501 u8 reserved_0[0x10];
5503 u8 reserved_1[0x10];
5509 u8 reserved_3[0x20];
5511 u8 modify_bitmask[0x40];
5513 u8 reserved_4[0x40];
5515 struct mlx5_ifc_rqtc_bits ctx;
5518 struct mlx5_ifc_modify_rq_out_bits {
5520 u8 reserved_0[0x18];
5524 u8 reserved_1[0x40];
5528 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5529 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5532 struct mlx5_ifc_modify_rq_in_bits {
5534 u8 reserved_0[0x10];
5536 u8 reserved_1[0x10];
5543 u8 reserved_3[0x20];
5545 u8 modify_bitmask[0x40];
5547 u8 reserved_4[0x40];
5549 struct mlx5_ifc_rqc_bits ctx;
5552 struct mlx5_ifc_modify_rmp_out_bits {
5554 u8 reserved_0[0x18];
5558 u8 reserved_1[0x40];
5561 struct mlx5_ifc_rmp_bitmask_bits {
5568 struct mlx5_ifc_modify_rmp_in_bits {
5570 u8 reserved_0[0x10];
5572 u8 reserved_1[0x10];
5579 u8 reserved_3[0x20];
5581 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5583 u8 reserved_4[0x40];
5585 struct mlx5_ifc_rmpc_bits ctx;
5588 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5590 u8 reserved_0[0x18];
5594 u8 reserved_1[0x40];
5597 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5598 u8 reserved_0[0x14];
5599 u8 disable_uc_local_lb[0x1];
5600 u8 disable_mc_local_lb[0x1];
5603 u8 min_wqe_inline_mode[0x1];
5605 u8 change_event[0x1];
5607 u8 permanent_address[0x1];
5608 u8 addresses_list[0x1];
5613 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5615 u8 reserved_0[0x10];
5617 u8 reserved_1[0x10];
5620 u8 other_vport[0x1];
5622 u8 vport_number[0x10];
5624 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5626 u8 reserved_3[0x780];
5628 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5631 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5633 u8 reserved_0[0x18];
5637 u8 reserved_1[0x40];
5640 struct mlx5_ifc_grh_bits {
5642 u8 traffic_class[8];
5644 u8 payload_length[16];
5651 struct mlx5_ifc_bth_bits {
5665 struct mlx5_ifc_aeth_bits {
5670 struct mlx5_ifc_dceth_bits {
5677 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5679 u8 reserved_0[0x10];
5681 u8 reserved_1[0x10];
5684 u8 other_vport[0x1];
5687 u8 vport_number[0x10];
5689 u8 reserved_3[0x20];
5691 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5694 struct mlx5_ifc_modify_flow_table_out_bits {
5696 u8 reserved_at_8[0x18];
5700 u8 reserved_at_40[0x40];
5704 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5705 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5708 struct mlx5_ifc_modify_flow_table_in_bits {
5710 u8 reserved_at_10[0x10];
5712 u8 reserved_at_20[0x10];
5715 u8 other_vport[0x1];
5716 u8 reserved_at_41[0xf];
5717 u8 vport_number[0x10];
5719 u8 reserved_at_60[0x10];
5720 u8 modify_field_select[0x10];
5723 u8 reserved_at_88[0x18];
5725 u8 reserved_at_a0[0x8];
5728 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5731 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5733 u8 reserved_0[0x18];
5737 u8 reserved_1[0x40];
5740 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5742 u8 vport_cvlan_insert[0x1];
5743 u8 vport_svlan_insert[0x1];
5744 u8 vport_cvlan_strip[0x1];
5745 u8 vport_svlan_strip[0x1];
5748 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5750 u8 reserved_0[0x10];
5752 u8 reserved_1[0x10];
5755 u8 other_vport[0x1];
5757 u8 vport_number[0x10];
5759 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5761 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5764 struct mlx5_ifc_modify_cq_out_bits {
5766 u8 reserved_0[0x18];
5770 u8 reserved_1[0x40];
5774 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5775 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5778 struct mlx5_ifc_modify_cq_in_bits {
5780 u8 reserved_0[0x10];
5782 u8 reserved_1[0x10];
5788 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5790 struct mlx5_ifc_cqc_bits cq_context;
5792 u8 reserved_3[0x600];
5797 struct mlx5_ifc_modify_cong_status_out_bits {
5799 u8 reserved_0[0x18];
5803 u8 reserved_1[0x40];
5806 struct mlx5_ifc_modify_cong_status_in_bits {
5808 u8 reserved_0[0x10];
5810 u8 reserved_1[0x10];
5813 u8 reserved_2[0x18];
5815 u8 cong_protocol[0x4];
5819 u8 reserved_3[0x1e];
5822 struct mlx5_ifc_modify_cong_params_out_bits {
5824 u8 reserved_0[0x18];
5828 u8 reserved_1[0x40];
5831 struct mlx5_ifc_modify_cong_params_in_bits {
5833 u8 reserved_0[0x10];
5835 u8 reserved_1[0x10];
5838 u8 reserved_2[0x1c];
5839 u8 cong_protocol[0x4];
5841 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5843 u8 reserved_3[0x80];
5845 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5848 struct mlx5_ifc_manage_pages_out_bits {
5850 u8 reserved_0[0x18];
5854 u8 output_num_entries[0x20];
5856 u8 reserved_1[0x20];
5862 MLX5_PAGES_CANT_GIVE = 0x0,
5863 MLX5_PAGES_GIVE = 0x1,
5864 MLX5_PAGES_TAKE = 0x2,
5867 struct mlx5_ifc_manage_pages_in_bits {
5869 u8 reserved_0[0x10];
5871 u8 reserved_1[0x10];
5874 u8 reserved_2[0x10];
5875 u8 function_id[0x10];
5877 u8 input_num_entries[0x20];
5882 struct mlx5_ifc_mad_ifc_out_bits {
5884 u8 reserved_0[0x18];
5888 u8 reserved_1[0x40];
5890 u8 response_mad_packet[256][0x8];
5893 struct mlx5_ifc_mad_ifc_in_bits {
5895 u8 reserved_0[0x10];
5897 u8 reserved_1[0x10];
5900 u8 remote_lid[0x10];
5904 u8 reserved_3[0x20];
5909 struct mlx5_ifc_init_hca_out_bits {
5911 u8 reserved_0[0x18];
5915 u8 reserved_1[0x40];
5919 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0,
5920 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1,
5923 struct mlx5_ifc_init_hca_in_bits {
5925 u8 reserved_0[0x10];
5927 u8 reserved_1[0x10];
5930 u8 reserved_2[0x40];
5933 struct mlx5_ifc_init2rtr_qp_out_bits {
5935 u8 reserved_0[0x18];
5939 u8 reserved_1[0x40];
5942 struct mlx5_ifc_init2rtr_qp_in_bits {
5944 u8 reserved_0[0x10];
5946 u8 reserved_1[0x10];
5952 u8 reserved_3[0x20];
5954 u8 opt_param_mask[0x20];
5956 u8 reserved_4[0x20];
5958 struct mlx5_ifc_qpc_bits qpc;
5960 u8 reserved_5[0x80];
5963 struct mlx5_ifc_init2init_qp_out_bits {
5965 u8 reserved_0[0x18];
5969 u8 reserved_1[0x40];
5972 struct mlx5_ifc_init2init_qp_in_bits {
5974 u8 reserved_0[0x10];
5976 u8 reserved_1[0x10];
5982 u8 reserved_3[0x20];
5984 u8 opt_param_mask[0x20];
5986 u8 reserved_4[0x20];
5988 struct mlx5_ifc_qpc_bits qpc;
5990 u8 reserved_5[0x80];
5993 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5995 u8 reserved_0[0x18];
5999 u8 reserved_1[0x40];
6001 u8 packet_headers_log[128][0x8];
6003 u8 packet_syndrome[64][0x8];
6006 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6008 u8 reserved_0[0x10];
6010 u8 reserved_1[0x10];
6013 u8 reserved_2[0x40];
6016 struct mlx5_ifc_encryption_key_obj_bits {
6017 u8 modify_field_select[0x40];
6019 u8 reserved_at_40[0x14];
6021 u8 reserved_at_58[0x4];
6024 u8 reserved_at_60[0x8];
6027 u8 reserved_at_80[0x180];
6031 u8 reserved_at_300[0x500];
6034 struct mlx5_ifc_gen_eqe_in_bits {
6036 u8 reserved_0[0x10];
6038 u8 reserved_1[0x10];
6041 u8 reserved_2[0x18];
6044 u8 reserved_3[0x20];
6049 struct mlx5_ifc_gen_eq_out_bits {
6051 u8 reserved_0[0x18];
6055 u8 reserved_1[0x40];
6058 struct mlx5_ifc_enable_hca_out_bits {
6060 u8 reserved_0[0x18];
6064 u8 reserved_1[0x20];
6067 struct mlx5_ifc_enable_hca_in_bits {
6069 u8 reserved_0[0x10];
6071 u8 reserved_1[0x10];
6074 u8 reserved_2[0x10];
6075 u8 function_id[0x10];
6077 u8 reserved_3[0x20];
6080 struct mlx5_ifc_drain_dct_out_bits {
6082 u8 reserved_0[0x18];
6086 u8 reserved_1[0x40];
6089 struct mlx5_ifc_drain_dct_in_bits {
6091 u8 reserved_0[0x10];
6093 u8 reserved_1[0x10];
6099 u8 reserved_3[0x20];
6102 struct mlx5_ifc_disable_hca_out_bits {
6104 u8 reserved_0[0x18];
6108 u8 reserved_1[0x20];
6111 struct mlx5_ifc_disable_hca_in_bits {
6113 u8 reserved_0[0x10];
6115 u8 reserved_1[0x10];
6118 u8 reserved_2[0x10];
6119 u8 function_id[0x10];
6121 u8 reserved_3[0x20];
6124 struct mlx5_ifc_detach_from_mcg_out_bits {
6126 u8 reserved_0[0x18];
6130 u8 reserved_1[0x40];
6133 struct mlx5_ifc_detach_from_mcg_in_bits {
6135 u8 reserved_0[0x10];
6137 u8 reserved_1[0x10];
6143 u8 reserved_3[0x20];
6145 u8 multicast_gid[16][0x8];
6148 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6150 u8 reserved_0[0x18];
6154 u8 reserved_1[0x40];
6157 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6159 u8 reserved_0[0x10];
6161 u8 reserved_1[0x10];
6167 u8 reserved_3[0x20];
6170 struct mlx5_ifc_destroy_tis_out_bits {
6172 u8 reserved_0[0x18];
6176 u8 reserved_1[0x40];
6179 struct mlx5_ifc_destroy_tis_in_bits {
6181 u8 reserved_0[0x10];
6183 u8 reserved_1[0x10];
6189 u8 reserved_3[0x20];
6192 struct mlx5_ifc_destroy_tir_out_bits {
6194 u8 reserved_0[0x18];
6198 u8 reserved_1[0x40];
6201 struct mlx5_ifc_destroy_tir_in_bits {
6203 u8 reserved_0[0x10];
6205 u8 reserved_1[0x10];
6211 u8 reserved_3[0x20];
6214 struct mlx5_ifc_destroy_srq_out_bits {
6216 u8 reserved_0[0x18];
6220 u8 reserved_1[0x40];
6223 struct mlx5_ifc_destroy_srq_in_bits {
6225 u8 reserved_0[0x10];
6227 u8 reserved_1[0x10];
6233 u8 reserved_3[0x20];
6236 struct mlx5_ifc_destroy_sq_out_bits {
6238 u8 reserved_0[0x18];
6242 u8 reserved_1[0x40];
6245 struct mlx5_ifc_destroy_sq_in_bits {
6247 u8 reserved_0[0x10];
6249 u8 reserved_1[0x10];
6255 u8 reserved_3[0x20];
6258 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6260 u8 reserved_at_8[0x18];
6264 u8 reserved_at_40[0x1c0];
6268 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6271 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6273 u8 reserved_at_10[0x10];
6275 u8 reserved_at_20[0x10];
6278 u8 scheduling_hierarchy[0x8];
6279 u8 reserved_at_48[0x18];
6281 u8 scheduling_element_id[0x20];
6283 u8 reserved_at_80[0x180];
6286 struct mlx5_ifc_destroy_rqt_out_bits {
6288 u8 reserved_0[0x18];
6292 u8 reserved_1[0x40];
6295 struct mlx5_ifc_destroy_rqt_in_bits {
6297 u8 reserved_0[0x10];
6299 u8 reserved_1[0x10];
6305 u8 reserved_3[0x20];
6308 struct mlx5_ifc_destroy_rq_out_bits {
6310 u8 reserved_0[0x18];
6314 u8 reserved_1[0x40];
6317 struct mlx5_ifc_destroy_rq_in_bits {
6319 u8 reserved_0[0x10];
6321 u8 reserved_1[0x10];
6327 u8 reserved_3[0x20];
6330 struct mlx5_ifc_destroy_rmp_out_bits {
6332 u8 reserved_0[0x18];
6336 u8 reserved_1[0x40];
6339 struct mlx5_ifc_destroy_rmp_in_bits {
6341 u8 reserved_0[0x10];
6343 u8 reserved_1[0x10];
6349 u8 reserved_3[0x20];
6352 struct mlx5_ifc_destroy_qp_out_bits {
6354 u8 reserved_0[0x18];
6358 u8 reserved_1[0x40];
6361 struct mlx5_ifc_destroy_qp_in_bits {
6363 u8 reserved_0[0x10];
6365 u8 reserved_1[0x10];
6371 u8 reserved_3[0x20];
6374 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6376 u8 reserved_at_8[0x18];
6380 u8 reserved_at_40[0x1c0];
6383 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6385 u8 reserved_at_10[0x10];
6387 u8 reserved_at_20[0x10];
6390 u8 reserved_at_40[0x20];
6392 u8 reserved_at_60[0x10];
6393 u8 qos_para_vport_number[0x10];
6395 u8 reserved_at_80[0x180];
6398 struct mlx5_ifc_destroy_psv_out_bits {
6400 u8 reserved_0[0x18];
6404 u8 reserved_1[0x40];
6407 struct mlx5_ifc_destroy_psv_in_bits {
6409 u8 reserved_0[0x10];
6411 u8 reserved_1[0x10];
6417 u8 reserved_3[0x20];
6420 struct mlx5_ifc_destroy_mkey_out_bits {
6422 u8 reserved_0[0x18];
6426 u8 reserved_1[0x40];
6429 struct mlx5_ifc_destroy_mkey_in_bits {
6431 u8 reserved_0[0x10];
6433 u8 reserved_1[0x10];
6437 u8 mkey_index[0x18];
6439 u8 reserved_3[0x20];
6442 struct mlx5_ifc_destroy_flow_table_out_bits {
6444 u8 reserved_0[0x18];
6448 u8 reserved_1[0x40];
6451 struct mlx5_ifc_destroy_flow_table_in_bits {
6453 u8 reserved_0[0x10];
6455 u8 reserved_1[0x10];
6458 u8 other_vport[0x1];
6460 u8 vport_number[0x10];
6462 u8 reserved_3[0x20];
6465 u8 reserved_4[0x18];
6470 u8 reserved_6[0x140];
6473 struct mlx5_ifc_destroy_flow_group_out_bits {
6475 u8 reserved_0[0x18];
6479 u8 reserved_1[0x40];
6482 struct mlx5_ifc_destroy_flow_group_in_bits {
6484 u8 reserved_0[0x10];
6486 u8 reserved_1[0x10];
6489 u8 other_vport[0x1];
6491 u8 vport_number[0x10];
6493 u8 reserved_3[0x20];
6496 u8 reserved_4[0x18];
6503 u8 reserved_6[0x120];
6506 struct mlx5_ifc_destroy_encryption_key_out_bits {
6508 u8 reserved_at_8[0x18];
6512 u8 reserved_at_40[0x40];
6515 struct mlx5_ifc_destroy_encryption_key_in_bits {
6517 u8 reserved_at_10[0x10];
6519 u8 reserved_at_20[0x10];
6524 u8 reserved_at_60[0x20];
6527 struct mlx5_ifc_destroy_eq_out_bits {
6529 u8 reserved_0[0x18];
6533 u8 reserved_1[0x40];
6536 struct mlx5_ifc_destroy_eq_in_bits {
6538 u8 reserved_0[0x10];
6540 u8 reserved_1[0x10];
6543 u8 reserved_2[0x18];
6546 u8 reserved_3[0x20];
6549 struct mlx5_ifc_destroy_dct_out_bits {
6551 u8 reserved_0[0x18];
6555 u8 reserved_1[0x40];
6558 struct mlx5_ifc_destroy_dct_in_bits {
6560 u8 reserved_0[0x10];
6562 u8 reserved_1[0x10];
6568 u8 reserved_3[0x20];
6571 struct mlx5_ifc_destroy_cq_out_bits {
6573 u8 reserved_0[0x18];
6577 u8 reserved_1[0x40];
6580 struct mlx5_ifc_destroy_cq_in_bits {
6582 u8 reserved_0[0x10];
6584 u8 reserved_1[0x10];
6590 u8 reserved_3[0x20];
6593 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6595 u8 reserved_0[0x18];
6599 u8 reserved_1[0x40];
6602 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6604 u8 reserved_0[0x10];
6606 u8 reserved_1[0x10];
6609 u8 reserved_2[0x20];
6611 u8 reserved_3[0x10];
6612 u8 vxlan_udp_port[0x10];
6615 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6617 u8 reserved_0[0x18];
6621 u8 reserved_1[0x40];
6624 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6626 u8 reserved_0[0x10];
6628 u8 reserved_1[0x10];
6631 u8 reserved_2[0x60];
6634 u8 table_index[0x18];
6636 u8 reserved_4[0x140];
6639 struct mlx5_ifc_delete_fte_out_bits {
6641 u8 reserved_0[0x18];
6645 u8 reserved_1[0x40];
6648 struct mlx5_ifc_delete_fte_in_bits {
6650 u8 reserved_0[0x10];
6652 u8 reserved_1[0x10];
6655 u8 other_vport[0x1];
6657 u8 vport_number[0x10];
6659 u8 reserved_3[0x20];
6662 u8 reserved_4[0x18];
6667 u8 reserved_6[0x40];
6669 u8 flow_index[0x20];
6671 u8 reserved_7[0xe0];
6674 struct mlx5_ifc_dealloc_xrcd_out_bits {
6676 u8 reserved_0[0x18];
6680 u8 reserved_1[0x40];
6683 struct mlx5_ifc_dealloc_xrcd_in_bits {
6685 u8 reserved_0[0x10];
6687 u8 reserved_1[0x10];
6693 u8 reserved_3[0x20];
6696 struct mlx5_ifc_dealloc_uar_out_bits {
6698 u8 reserved_0[0x18];
6702 u8 reserved_1[0x40];
6705 struct mlx5_ifc_dealloc_uar_in_bits {
6707 u8 reserved_0[0x10];
6709 u8 reserved_1[0x10];
6715 u8 reserved_3[0x20];
6718 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6720 u8 reserved_0[0x18];
6724 u8 reserved_1[0x40];
6727 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6729 u8 reserved_0[0x10];
6731 u8 reserved_1[0x10];
6735 u8 transport_domain[0x18];
6737 u8 reserved_3[0x20];
6740 struct mlx5_ifc_dealloc_q_counter_out_bits {
6742 u8 reserved_0[0x18];
6746 u8 reserved_1[0x40];
6749 struct mlx5_ifc_counter_id_bits {
6751 u8 counter_id[0x10];
6754 struct mlx5_ifc_diagnostic_params_context_bits {
6755 u8 num_of_counters[0x10];
6757 u8 log_num_of_samples[0x8];
6765 u8 reserved_3[0x12];
6766 u8 log_sample_period[0x8];
6768 u8 reserved_4[0x80];
6770 struct mlx5_ifc_counter_id_bits counter_id[0];
6773 struct mlx5_ifc_set_diagnostic_params_in_bits {
6775 u8 reserved_0[0x10];
6777 u8 reserved_1[0x10];
6780 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6783 struct mlx5_ifc_set_diagnostic_params_out_bits {
6785 u8 reserved_0[0x18];
6789 u8 reserved_1[0x40];
6792 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6794 u8 reserved_0[0x10];
6796 u8 reserved_1[0x10];
6799 u8 num_of_samples[0x10];
6800 u8 sample_index[0x10];
6802 u8 reserved_2[0x20];
6805 struct mlx5_ifc_diagnostic_counter_bits {
6806 u8 counter_id[0x10];
6809 u8 time_stamp_31_0[0x20];
6811 u8 counter_value_h[0x20];
6813 u8 counter_value_l[0x20];
6816 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6818 u8 reserved_0[0x18];
6822 u8 reserved_1[0x40];
6824 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6827 struct mlx5_ifc_dealloc_q_counter_in_bits {
6829 u8 reserved_0[0x10];
6831 u8 reserved_1[0x10];
6834 u8 reserved_2[0x18];
6835 u8 counter_set_id[0x8];
6837 u8 reserved_3[0x20];
6840 struct mlx5_ifc_dealloc_pd_out_bits {
6842 u8 reserved_0[0x18];
6846 u8 reserved_1[0x40];
6849 struct mlx5_ifc_dealloc_pd_in_bits {
6851 u8 reserved_0[0x10];
6853 u8 reserved_1[0x10];
6859 u8 reserved_3[0x20];
6862 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6864 u8 reserved_0[0x18];
6868 u8 reserved_1[0x40];
6871 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6873 u8 reserved_0[0x10];
6875 u8 reserved_1[0x10];
6878 u8 reserved_2[0x10];
6879 u8 flow_counter_id[0x10];
6881 u8 reserved_3[0x20];
6884 struct mlx5_ifc_deactivate_tracer_out_bits {
6886 u8 reserved_0[0x18];
6890 u8 reserved_1[0x40];
6893 struct mlx5_ifc_deactivate_tracer_in_bits {
6895 u8 reserved_0[0x10];
6897 u8 reserved_1[0x10];
6902 u8 reserved_2[0x20];
6905 struct mlx5_ifc_create_xrc_srq_out_bits {
6907 u8 reserved_0[0x18];
6914 u8 reserved_2[0x20];
6917 struct mlx5_ifc_create_xrc_srq_in_bits {
6919 u8 reserved_0[0x10];
6921 u8 reserved_1[0x10];
6924 u8 reserved_2[0x40];
6926 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6928 u8 reserved_3[0x600];
6933 struct mlx5_ifc_create_tis_out_bits {
6935 u8 reserved_0[0x18];
6942 u8 reserved_2[0x20];
6945 struct mlx5_ifc_create_tis_in_bits {
6947 u8 reserved_0[0x10];
6949 u8 reserved_1[0x10];
6952 u8 reserved_2[0xc0];
6954 struct mlx5_ifc_tisc_bits ctx;
6957 struct mlx5_ifc_create_tir_out_bits {
6959 u8 reserved_0[0x18];
6966 u8 reserved_2[0x20];
6969 struct mlx5_ifc_create_tir_in_bits {
6971 u8 reserved_0[0x10];
6973 u8 reserved_1[0x10];
6976 u8 reserved_2[0xc0];
6978 struct mlx5_ifc_tirc_bits tir_context;
6981 struct mlx5_ifc_create_srq_out_bits {
6983 u8 reserved_0[0x18];
6990 u8 reserved_2[0x20];
6993 struct mlx5_ifc_create_srq_in_bits {
6995 u8 reserved_0[0x10];
6997 u8 reserved_1[0x10];
7000 u8 reserved_2[0x40];
7002 struct mlx5_ifc_srqc_bits srq_context_entry;
7004 u8 reserved_3[0x600];
7009 struct mlx5_ifc_create_sq_out_bits {
7011 u8 reserved_0[0x18];
7018 u8 reserved_2[0x20];
7021 struct mlx5_ifc_create_sq_in_bits {
7023 u8 reserved_0[0x10];
7025 u8 reserved_1[0x10];
7028 u8 reserved_2[0xc0];
7030 struct mlx5_ifc_sqc_bits ctx;
7033 struct mlx5_ifc_create_scheduling_element_out_bits {
7035 u8 reserved_at_8[0x18];
7039 u8 reserved_at_40[0x40];
7041 u8 scheduling_element_id[0x20];
7043 u8 reserved_at_a0[0x160];
7047 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
7050 struct mlx5_ifc_create_scheduling_element_in_bits {
7052 u8 reserved_at_10[0x10];
7054 u8 reserved_at_20[0x10];
7057 u8 scheduling_hierarchy[0x8];
7058 u8 reserved_at_48[0x18];
7060 u8 reserved_at_60[0xa0];
7062 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7064 u8 reserved_at_300[0x100];
7067 struct mlx5_ifc_create_rqt_out_bits {
7069 u8 reserved_0[0x18];
7076 u8 reserved_2[0x20];
7079 struct mlx5_ifc_create_rqt_in_bits {
7081 u8 reserved_0[0x10];
7083 u8 reserved_1[0x10];
7086 u8 reserved_2[0xc0];
7088 struct mlx5_ifc_rqtc_bits rqt_context;
7091 struct mlx5_ifc_create_rq_out_bits {
7093 u8 reserved_0[0x18];
7100 u8 reserved_2[0x20];
7103 struct mlx5_ifc_create_rq_in_bits {
7105 u8 reserved_0[0x10];
7107 u8 reserved_1[0x10];
7110 u8 reserved_2[0xc0];
7112 struct mlx5_ifc_rqc_bits ctx;
7115 struct mlx5_ifc_create_rmp_out_bits {
7117 u8 reserved_0[0x18];
7124 u8 reserved_2[0x20];
7127 struct mlx5_ifc_create_rmp_in_bits {
7129 u8 reserved_0[0x10];
7131 u8 reserved_1[0x10];
7134 u8 reserved_2[0xc0];
7136 struct mlx5_ifc_rmpc_bits ctx;
7139 struct mlx5_ifc_create_qp_out_bits {
7141 u8 reserved_0[0x18];
7148 u8 reserved_2[0x20];
7151 struct mlx5_ifc_create_qp_in_bits {
7153 u8 reserved_0[0x10];
7155 u8 reserved_1[0x10];
7161 u8 reserved_3[0x20];
7163 u8 opt_param_mask[0x20];
7165 u8 reserved_4[0x20];
7167 struct mlx5_ifc_qpc_bits qpc;
7169 u8 reserved_5[0x80];
7174 struct mlx5_ifc_create_qos_para_vport_out_bits {
7176 u8 reserved_at_8[0x18];
7180 u8 reserved_at_40[0x20];
7182 u8 reserved_at_60[0x10];
7183 u8 qos_para_vport_number[0x10];
7185 u8 reserved_at_80[0x180];
7188 struct mlx5_ifc_create_qos_para_vport_in_bits {
7190 u8 reserved_at_10[0x10];
7192 u8 reserved_at_20[0x10];
7195 u8 reserved_at_40[0x1c0];
7198 struct mlx5_ifc_create_psv_out_bits {
7200 u8 reserved_0[0x18];
7204 u8 reserved_1[0x40];
7207 u8 psv0_index[0x18];
7210 u8 psv1_index[0x18];
7213 u8 psv2_index[0x18];
7216 u8 psv3_index[0x18];
7219 struct mlx5_ifc_create_psv_in_bits {
7221 u8 reserved_0[0x10];
7223 u8 reserved_1[0x10];
7230 u8 reserved_3[0x20];
7233 struct mlx5_ifc_create_mkey_out_bits {
7235 u8 reserved_0[0x18];
7240 u8 mkey_index[0x18];
7242 u8 reserved_2[0x20];
7245 struct mlx5_ifc_create_mkey_in_bits {
7247 u8 reserved_0[0x10];
7249 u8 reserved_1[0x10];
7252 u8 reserved_2[0x20];
7255 u8 reserved_3[0x1f];
7257 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7259 u8 reserved_4[0x80];
7261 u8 translations_octword_actual_size[0x20];
7263 u8 reserved_5[0x560];
7265 u8 klm_pas_mtt[0][0x20];
7268 struct mlx5_ifc_create_flow_table_out_bits {
7270 u8 reserved_0[0x18];
7277 u8 reserved_2[0x20];
7280 struct mlx5_ifc_create_flow_table_in_bits {
7282 u8 reserved_at_10[0x10];
7284 u8 reserved_at_20[0x10];
7287 u8 other_vport[0x1];
7288 u8 reserved_at_41[0xf];
7289 u8 vport_number[0x10];
7291 u8 reserved_at_60[0x20];
7294 u8 reserved_at_88[0x18];
7296 u8 reserved_at_a0[0x20];
7298 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7301 struct mlx5_ifc_create_flow_group_out_bits {
7303 u8 reserved_0[0x18];
7310 u8 reserved_2[0x20];
7314 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7315 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7316 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7319 struct mlx5_ifc_create_flow_group_in_bits {
7321 u8 reserved_0[0x10];
7323 u8 reserved_1[0x10];
7326 u8 other_vport[0x1];
7328 u8 vport_number[0x10];
7330 u8 reserved_3[0x20];
7333 u8 reserved_4[0x18];
7338 u8 reserved_6[0x20];
7340 u8 start_flow_index[0x20];
7342 u8 reserved_7[0x20];
7344 u8 end_flow_index[0x20];
7346 u8 reserved_8[0xa0];
7348 u8 reserved_9[0x18];
7349 u8 match_criteria_enable[0x8];
7351 struct mlx5_ifc_fte_match_param_bits match_criteria;
7353 u8 reserved_10[0xe00];
7356 struct mlx5_ifc_create_encryption_key_out_bits {
7358 u8 reserved_at_8[0x18];
7364 u8 reserved_at_60[0x20];
7367 struct mlx5_ifc_create_encryption_key_in_bits {
7369 u8 reserved_at_10[0x10];
7371 u8 reserved_at_20[0x10];
7374 u8 reserved_at_40[0x40];
7376 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7379 struct mlx5_ifc_create_eq_out_bits {
7381 u8 reserved_0[0x18];
7385 u8 reserved_1[0x18];
7388 u8 reserved_2[0x20];
7391 struct mlx5_ifc_create_eq_in_bits {
7393 u8 reserved_0[0x10];
7395 u8 reserved_1[0x10];
7398 u8 reserved_2[0x40];
7400 struct mlx5_ifc_eqc_bits eq_context_entry;
7402 u8 reserved_3[0x40];
7404 u8 event_bitmask[0x40];
7406 u8 reserved_4[0x580];
7411 struct mlx5_ifc_create_dct_out_bits {
7413 u8 reserved_0[0x18];
7420 u8 reserved_2[0x20];
7423 struct mlx5_ifc_create_dct_in_bits {
7425 u8 reserved_0[0x10];
7427 u8 reserved_1[0x10];
7430 u8 reserved_2[0x40];
7432 struct mlx5_ifc_dctc_bits dct_context_entry;
7434 u8 reserved_3[0x180];
7437 struct mlx5_ifc_create_cq_out_bits {
7439 u8 reserved_0[0x18];
7446 u8 reserved_2[0x20];
7449 struct mlx5_ifc_create_cq_in_bits {
7451 u8 reserved_0[0x10];
7453 u8 reserved_1[0x10];
7456 u8 reserved_2[0x40];
7458 struct mlx5_ifc_cqc_bits cq_context;
7460 u8 reserved_3[0x600];
7465 struct mlx5_ifc_config_int_moderation_out_bits {
7467 u8 reserved_0[0x18];
7473 u8 int_vector[0x10];
7475 u8 reserved_2[0x20];
7479 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7480 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7483 struct mlx5_ifc_config_int_moderation_in_bits {
7485 u8 reserved_0[0x10];
7487 u8 reserved_1[0x10];
7492 u8 int_vector[0x10];
7494 u8 reserved_3[0x20];
7497 struct mlx5_ifc_attach_to_mcg_out_bits {
7499 u8 reserved_0[0x18];
7503 u8 reserved_1[0x40];
7506 struct mlx5_ifc_attach_to_mcg_in_bits {
7508 u8 reserved_0[0x10];
7510 u8 reserved_1[0x10];
7516 u8 reserved_3[0x20];
7518 u8 multicast_gid[16][0x8];
7521 struct mlx5_ifc_arm_xrc_srq_out_bits {
7523 u8 reserved_0[0x18];
7527 u8 reserved_1[0x40];
7531 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7534 struct mlx5_ifc_arm_xrc_srq_in_bits {
7536 u8 reserved_0[0x10];
7538 u8 reserved_1[0x10];
7544 u8 reserved_3[0x10];
7548 struct mlx5_ifc_arm_rq_out_bits {
7550 u8 reserved_0[0x18];
7554 u8 reserved_1[0x40];
7558 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7561 struct mlx5_ifc_arm_rq_in_bits {
7563 u8 reserved_0[0x10];
7565 u8 reserved_1[0x10];
7569 u8 srq_number[0x18];
7571 u8 reserved_3[0x10];
7575 struct mlx5_ifc_arm_dct_out_bits {
7577 u8 reserved_0[0x18];
7581 u8 reserved_1[0x40];
7584 struct mlx5_ifc_arm_dct_in_bits {
7586 u8 reserved_0[0x10];
7588 u8 reserved_1[0x10];
7594 u8 reserved_3[0x20];
7597 struct mlx5_ifc_alloc_xrcd_out_bits {
7599 u8 reserved_0[0x18];
7606 u8 reserved_2[0x20];
7609 struct mlx5_ifc_alloc_xrcd_in_bits {
7611 u8 reserved_0[0x10];
7613 u8 reserved_1[0x10];
7616 u8 reserved_2[0x40];
7619 struct mlx5_ifc_alloc_uar_out_bits {
7621 u8 reserved_0[0x18];
7628 u8 reserved_2[0x20];
7631 struct mlx5_ifc_alloc_uar_in_bits {
7633 u8 reserved_0[0x10];
7635 u8 reserved_1[0x10];
7638 u8 reserved_2[0x40];
7641 struct mlx5_ifc_alloc_transport_domain_out_bits {
7643 u8 reserved_0[0x18];
7648 u8 transport_domain[0x18];
7650 u8 reserved_2[0x20];
7653 struct mlx5_ifc_alloc_transport_domain_in_bits {
7655 u8 reserved_0[0x10];
7657 u8 reserved_1[0x10];
7660 u8 reserved_2[0x40];
7663 struct mlx5_ifc_alloc_q_counter_out_bits {
7665 u8 reserved_0[0x18];
7669 u8 reserved_1[0x18];
7670 u8 counter_set_id[0x8];
7672 u8 reserved_2[0x20];
7675 struct mlx5_ifc_alloc_q_counter_in_bits {
7677 u8 reserved_0[0x10];
7679 u8 reserved_1[0x10];
7682 u8 reserved_2[0x40];
7685 struct mlx5_ifc_alloc_pd_out_bits {
7687 u8 reserved_0[0x18];
7694 u8 reserved_2[0x20];
7697 struct mlx5_ifc_alloc_pd_in_bits {
7699 u8 reserved_0[0x10];
7701 u8 reserved_1[0x10];
7704 u8 reserved_2[0x40];
7707 struct mlx5_ifc_alloc_flow_counter_out_bits {
7709 u8 reserved_0[0x18];
7713 u8 reserved_1[0x10];
7714 u8 flow_counter_id[0x10];
7716 u8 reserved_2[0x20];
7719 struct mlx5_ifc_alloc_flow_counter_in_bits {
7721 u8 reserved_0[0x10];
7723 u8 reserved_1[0x10];
7726 u8 reserved_2[0x40];
7729 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7731 u8 reserved_0[0x18];
7735 u8 reserved_1[0x40];
7738 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7740 u8 reserved_0[0x10];
7742 u8 reserved_1[0x10];
7745 u8 reserved_2[0x20];
7747 u8 reserved_3[0x10];
7748 u8 vxlan_udp_port[0x10];
7751 struct mlx5_ifc_activate_tracer_out_bits {
7753 u8 reserved_0[0x18];
7757 u8 reserved_1[0x40];
7760 struct mlx5_ifc_activate_tracer_in_bits {
7762 u8 reserved_0[0x10];
7764 u8 reserved_1[0x10];
7769 u8 reserved_2[0x20];
7772 struct mlx5_ifc_set_rate_limit_out_bits {
7774 u8 reserved_at_8[0x18];
7778 u8 reserved_at_40[0x40];
7781 struct mlx5_ifc_set_rate_limit_in_bits {
7783 u8 reserved_at_10[0x10];
7785 u8 reserved_at_20[0x10];
7788 u8 reserved_at_40[0x10];
7789 u8 rate_limit_index[0x10];
7791 u8 reserved_at_60[0x20];
7793 u8 rate_limit[0x20];
7795 u8 burst_upper_bound[0x20];
7797 u8 reserved_at_c0[0x10];
7798 u8 typical_packet_size[0x10];
7800 u8 reserved_at_e0[0x120];
7803 struct mlx5_ifc_access_register_out_bits {
7805 u8 reserved_0[0x18];
7809 u8 reserved_1[0x40];
7811 u8 register_data[0][0x20];
7815 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7816 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7819 struct mlx5_ifc_access_register_in_bits {
7821 u8 reserved_0[0x10];
7823 u8 reserved_1[0x10];
7826 u8 reserved_2[0x10];
7827 u8 register_id[0x10];
7831 u8 register_data[0][0x20];
7834 struct mlx5_ifc_sltp_reg_bits {
7843 u8 reserved_2[0x20];
7852 u8 ob_preemp_mode[0x4];
7856 u8 reserved_5[0x20];
7859 struct mlx5_ifc_slrp_reg_bits {
7869 u8 reserved_2[0x11];
7885 u8 mixerbias_tap_amp[0x8];
7889 u8 ffe_tap_offset0[0x8];
7890 u8 ffe_tap_offset1[0x8];
7891 u8 slicer_offset0[0x10];
7893 u8 mixer_offset0[0x10];
7894 u8 mixer_offset1[0x10];
7896 u8 mixerbgn_inp[0x8];
7897 u8 mixerbgn_inn[0x8];
7898 u8 mixerbgn_refp[0x8];
7899 u8 mixerbgn_refn[0x8];
7901 u8 sel_slicer_lctrl_h[0x1];
7902 u8 sel_slicer_lctrl_l[0x1];
7904 u8 ref_mixer_vreg[0x5];
7905 u8 slicer_gctrl[0x8];
7906 u8 lctrl_input[0x8];
7907 u8 mixer_offset_cm1[0x8];
7909 u8 common_mode[0x6];
7911 u8 mixer_offset_cm0[0x9];
7913 u8 slicer_offset_cm[0x9];
7916 struct mlx5_ifc_slrg_reg_bits {
7925 u8 time_to_link_up[0x10];
7927 u8 grade_lane_speed[0x4];
7929 u8 grade_version[0x8];
7933 u8 height_grade_type[0x4];
7934 u8 height_grade[0x18];
7939 u8 reserved_4[0x10];
7940 u8 height_sigma[0x10];
7942 u8 reserved_5[0x20];
7945 u8 phase_grade_type[0x4];
7946 u8 phase_grade[0x18];
7949 u8 phase_eo_pos[0x8];
7951 u8 phase_eo_neg[0x8];
7953 u8 ffe_set_tested[0x10];
7954 u8 test_errors_per_lane[0x10];
7957 struct mlx5_ifc_pvlc_reg_bits {
7960 u8 reserved_1[0x10];
7962 u8 reserved_2[0x1c];
7965 u8 reserved_3[0x1c];
7968 u8 reserved_4[0x1c];
7969 u8 vl_operational[0x4];
7972 struct mlx5_ifc_pude_reg_bits {
7976 u8 admin_status[0x4];
7978 u8 oper_status[0x4];
7980 u8 reserved_2[0x60];
7984 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1,
7985 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4,
7988 struct mlx5_ifc_ptys_reg_bits {
7990 u8 an_disable_admin[0x1];
7991 u8 an_disable_cap[0x1];
7993 u8 force_tx_aba_param[0x1];
8000 u8 data_rate_oper[0x10];
8002 u8 ext_eth_proto_capability[0x20];
8004 u8 eth_proto_capability[0x20];
8006 u8 ib_link_width_capability[0x10];
8007 u8 ib_proto_capability[0x10];
8009 u8 ext_eth_proto_admin[0x20];
8011 u8 eth_proto_admin[0x20];
8013 u8 ib_link_width_admin[0x10];
8014 u8 ib_proto_admin[0x10];
8016 u8 ext_eth_proto_oper[0x20];
8018 u8 eth_proto_oper[0x20];
8020 u8 ib_link_width_oper[0x10];
8021 u8 ib_proto_oper[0x10];
8023 u8 reserved_4[0x1c];
8024 u8 connector_type[0x4];
8026 u8 eth_proto_lp_advertise[0x20];
8028 u8 reserved_5[0x60];
8031 struct mlx5_ifc_ptas_reg_bits {
8032 u8 reserved_0[0x20];
8034 u8 algorithm_options[0x10];
8036 u8 repetitions_mode[0x4];
8037 u8 num_of_repetitions[0x8];
8039 u8 grade_version[0x8];
8040 u8 height_grade_type[0x4];
8041 u8 phase_grade_type[0x4];
8042 u8 height_grade_weight[0x8];
8043 u8 phase_grade_weight[0x8];
8045 u8 gisim_measure_bits[0x10];
8046 u8 adaptive_tap_measure_bits[0x10];
8048 u8 ber_bath_high_error_threshold[0x10];
8049 u8 ber_bath_mid_error_threshold[0x10];
8051 u8 ber_bath_low_error_threshold[0x10];
8052 u8 one_ratio_high_threshold[0x10];
8054 u8 one_ratio_high_mid_threshold[0x10];
8055 u8 one_ratio_low_mid_threshold[0x10];
8057 u8 one_ratio_low_threshold[0x10];
8058 u8 ndeo_error_threshold[0x10];
8060 u8 mixer_offset_step_size[0x10];
8062 u8 mix90_phase_for_voltage_bath[0x8];
8064 u8 mixer_offset_start[0x10];
8065 u8 mixer_offset_end[0x10];
8067 u8 reserved_3[0x15];
8068 u8 ber_test_time[0xb];
8071 struct mlx5_ifc_pspa_reg_bits {
8077 u8 reserved_1[0x20];
8080 struct mlx5_ifc_ppsc_reg_bits {
8083 u8 reserved_1[0x10];
8085 u8 reserved_2[0x60];
8087 u8 reserved_3[0x1c];
8090 u8 reserved_4[0x1c];
8091 u8 wrps_status[0x4];
8094 u8 down_th_vld[0x1];
8096 u8 up_threshold[0x8];
8098 u8 down_threshold[0x8];
8100 u8 reserved_7[0x20];
8102 u8 reserved_8[0x1c];
8105 u8 reserved_9[0x60];
8108 struct mlx5_ifc_pplr_reg_bits {
8111 u8 reserved_1[0x10];
8119 struct mlx5_ifc_pplm_reg_bits {
8120 u8 reserved_at_0[0x8];
8122 u8 reserved_at_10[0x10];
8124 u8 reserved_at_20[0x20];
8126 u8 port_profile_mode[0x8];
8127 u8 static_port_profile[0x8];
8128 u8 active_port_profile[0x8];
8129 u8 reserved_at_58[0x8];
8131 u8 retransmission_active[0x8];
8132 u8 fec_mode_active[0x18];
8134 u8 rs_fec_correction_bypass_cap[0x4];
8135 u8 reserved_at_84[0x8];
8136 u8 fec_override_cap_56g[0x4];
8137 u8 fec_override_cap_100g[0x4];
8138 u8 fec_override_cap_50g[0x4];
8139 u8 fec_override_cap_25g[0x4];
8140 u8 fec_override_cap_10g_40g[0x4];
8142 u8 rs_fec_correction_bypass_admin[0x4];
8143 u8 reserved_at_a4[0x8];
8144 u8 fec_override_admin_56g[0x4];
8145 u8 fec_override_admin_100g[0x4];
8146 u8 fec_override_admin_50g[0x4];
8147 u8 fec_override_admin_25g[0x4];
8148 u8 fec_override_admin_10g_40g[0x4];
8150 u8 fec_override_cap_400g_8x[0x10];
8151 u8 fec_override_cap_200g_4x[0x10];
8152 u8 fec_override_cap_100g_2x[0x10];
8153 u8 fec_override_cap_50g_1x[0x10];
8155 u8 fec_override_admin_400g_8x[0x10];
8156 u8 fec_override_admin_200g_4x[0x10];
8157 u8 fec_override_admin_100g_2x[0x10];
8158 u8 fec_override_admin_50g_1x[0x10];
8160 u8 reserved_at_140[0xC0];
8163 struct mlx5_ifc_ppll_reg_bits {
8164 u8 num_pll_groups[0x8];
8170 u8 reserved_2[0x1f];
8173 u8 pll_status[4][0x40];
8176 struct mlx5_ifc_ppad_reg_bits {
8185 u8 reserved_2[0x40];
8188 struct mlx5_ifc_pmtu_reg_bits {
8191 u8 reserved_1[0x10];
8194 u8 reserved_2[0x10];
8197 u8 reserved_3[0x10];
8200 u8 reserved_4[0x10];
8203 struct mlx5_ifc_pmpr_reg_bits {
8206 u8 reserved_1[0x10];
8208 u8 reserved_2[0x18];
8209 u8 attenuation_5g[0x8];
8211 u8 reserved_3[0x18];
8212 u8 attenuation_7g[0x8];
8214 u8 reserved_4[0x18];
8215 u8 attenuation_12g[0x8];
8218 struct mlx5_ifc_pmpe_reg_bits {
8222 u8 module_status[0x4];
8224 u8 reserved_2[0x14];
8228 u8 reserved_4[0x40];
8231 struct mlx5_ifc_pmpc_reg_bits {
8232 u8 module_state_updated[32][0x8];
8235 struct mlx5_ifc_pmlpn_reg_bits {
8237 u8 mlpn_status[0x4];
8239 u8 reserved_1[0x10];
8242 u8 reserved_2[0x1f];
8245 struct mlx5_ifc_pmlp_reg_bits {
8252 u8 lane0_module_mapping[0x20];
8254 u8 lane1_module_mapping[0x20];
8256 u8 lane2_module_mapping[0x20];
8258 u8 lane3_module_mapping[0x20];
8260 u8 reserved_2[0x160];
8263 struct mlx5_ifc_pmaos_reg_bits {
8267 u8 admin_status[0x4];
8269 u8 oper_status[0x4];
8273 u8 reserved_3[0x12];
8278 u8 reserved_5[0x40];
8281 struct mlx5_ifc_plpc_reg_bits {
8288 u8 reserved_3[0x10];
8289 u8 lane_speed[0x10];
8291 u8 reserved_4[0x17];
8293 u8 fec_mode_policy[0x8];
8295 u8 retransmission_capability[0x8];
8296 u8 fec_mode_capability[0x18];
8298 u8 retransmission_support_admin[0x8];
8299 u8 fec_mode_support_admin[0x18];
8301 u8 retransmission_request_admin[0x8];
8302 u8 fec_mode_request_admin[0x18];
8304 u8 reserved_5[0x80];
8307 struct mlx5_ifc_pll_status_data_bits {
8310 u8 lock_status[0x2];
8312 u8 algo_f_ctrl[0xa];
8313 u8 analog_algo_num_var[0x6];
8314 u8 f_ctrl_measure[0xa];
8326 struct mlx5_ifc_plib_reg_bits {
8332 u8 reserved_2[0x60];
8335 struct mlx5_ifc_plbf_reg_bits {
8341 u8 reserved_2[0x20];
8344 struct mlx5_ifc_pipg_reg_bits {
8347 u8 reserved_1[0x10];
8350 u8 reserved_2[0x19];
8355 struct mlx5_ifc_pifr_reg_bits {
8358 u8 reserved_1[0x10];
8360 u8 reserved_2[0xe0];
8362 u8 port_filter[8][0x20];
8364 u8 port_filter_update_en[8][0x20];
8367 struct mlx5_ifc_phys_layer_cntrs_bits {
8368 u8 time_since_last_clear_high[0x20];
8370 u8 time_since_last_clear_low[0x20];
8372 u8 symbol_errors_high[0x20];
8374 u8 symbol_errors_low[0x20];
8376 u8 sync_headers_errors_high[0x20];
8378 u8 sync_headers_errors_low[0x20];
8380 u8 edpl_bip_errors_lane0_high[0x20];
8382 u8 edpl_bip_errors_lane0_low[0x20];
8384 u8 edpl_bip_errors_lane1_high[0x20];
8386 u8 edpl_bip_errors_lane1_low[0x20];
8388 u8 edpl_bip_errors_lane2_high[0x20];
8390 u8 edpl_bip_errors_lane2_low[0x20];
8392 u8 edpl_bip_errors_lane3_high[0x20];
8394 u8 edpl_bip_errors_lane3_low[0x20];
8396 u8 fc_fec_corrected_blocks_lane0_high[0x20];
8398 u8 fc_fec_corrected_blocks_lane0_low[0x20];
8400 u8 fc_fec_corrected_blocks_lane1_high[0x20];
8402 u8 fc_fec_corrected_blocks_lane1_low[0x20];
8404 u8 fc_fec_corrected_blocks_lane2_high[0x20];
8406 u8 fc_fec_corrected_blocks_lane2_low[0x20];
8408 u8 fc_fec_corrected_blocks_lane3_high[0x20];
8410 u8 fc_fec_corrected_blocks_lane3_low[0x20];
8412 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
8414 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
8416 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
8418 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
8420 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
8422 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
8424 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
8426 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
8428 u8 rs_fec_corrected_blocks_high[0x20];
8430 u8 rs_fec_corrected_blocks_low[0x20];
8432 u8 rs_fec_uncorrectable_blocks_high[0x20];
8434 u8 rs_fec_uncorrectable_blocks_low[0x20];
8436 u8 rs_fec_no_errors_blocks_high[0x20];
8438 u8 rs_fec_no_errors_blocks_low[0x20];
8440 u8 rs_fec_single_error_blocks_high[0x20];
8442 u8 rs_fec_single_error_blocks_low[0x20];
8444 u8 rs_fec_corrected_symbols_total_high[0x20];
8446 u8 rs_fec_corrected_symbols_total_low[0x20];
8448 u8 rs_fec_corrected_symbols_lane0_high[0x20];
8450 u8 rs_fec_corrected_symbols_lane0_low[0x20];
8452 u8 rs_fec_corrected_symbols_lane1_high[0x20];
8454 u8 rs_fec_corrected_symbols_lane1_low[0x20];
8456 u8 rs_fec_corrected_symbols_lane2_high[0x20];
8458 u8 rs_fec_corrected_symbols_lane2_low[0x20];
8460 u8 rs_fec_corrected_symbols_lane3_high[0x20];
8462 u8 rs_fec_corrected_symbols_lane3_low[0x20];
8464 u8 link_down_events[0x20];
8466 u8 successful_recovery_events[0x20];
8468 u8 reserved_0[0x180];
8471 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8472 u8 symbol_error_counter[0x10];
8474 u8 link_error_recovery_counter[0x8];
8476 u8 link_downed_counter[0x8];
8478 u8 port_rcv_errors[0x10];
8480 u8 port_rcv_remote_physical_errors[0x10];
8482 u8 port_rcv_switch_relay_errors[0x10];
8484 u8 port_xmit_discards[0x10];
8486 u8 port_xmit_constraint_errors[0x8];
8488 u8 port_rcv_constraint_errors[0x8];
8490 u8 reserved_at_70[0x8];
8492 u8 link_overrun_errors[0x8];
8494 u8 reserved_at_80[0x10];
8496 u8 vl_15_dropped[0x10];
8498 u8 reserved_at_a0[0xa0];
8501 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8502 u8 time_since_last_clear_high[0x20];
8504 u8 time_since_last_clear_low[0x20];
8506 u8 phy_received_bits_high[0x20];
8508 u8 phy_received_bits_low[0x20];
8510 u8 phy_symbol_errors_high[0x20];
8512 u8 phy_symbol_errors_low[0x20];
8514 u8 phy_corrected_bits_high[0x20];
8516 u8 phy_corrected_bits_low[0x20];
8518 u8 phy_corrected_bits_lane0_high[0x20];
8520 u8 phy_corrected_bits_lane0_low[0x20];
8522 u8 phy_corrected_bits_lane1_high[0x20];
8524 u8 phy_corrected_bits_lane1_low[0x20];
8526 u8 phy_corrected_bits_lane2_high[0x20];
8528 u8 phy_corrected_bits_lane2_low[0x20];
8530 u8 phy_corrected_bits_lane3_high[0x20];
8532 u8 phy_corrected_bits_lane3_low[0x20];
8534 u8 reserved_at_200[0x5c0];
8537 struct mlx5_ifc_infiniband_port_cntrs_bits {
8538 u8 symbol_error_counter[0x10];
8539 u8 link_error_recovery_counter[0x8];
8540 u8 link_downed_counter[0x8];
8542 u8 port_rcv_errors[0x10];
8543 u8 port_rcv_remote_physical_errors[0x10];
8545 u8 port_rcv_switch_relay_errors[0x10];
8546 u8 port_xmit_discards[0x10];
8548 u8 port_xmit_constraint_errors[0x8];
8549 u8 port_rcv_constraint_errors[0x8];
8551 u8 local_link_integrity_errors[0x4];
8552 u8 excessive_buffer_overrun_errors[0x4];
8554 u8 reserved_1[0x10];
8555 u8 vl_15_dropped[0x10];
8557 u8 port_xmit_data[0x20];
8559 u8 port_rcv_data[0x20];
8561 u8 port_xmit_pkts[0x20];
8563 u8 port_rcv_pkts[0x20];
8565 u8 port_xmit_wait[0x20];
8567 u8 reserved_2[0x680];
8570 struct mlx5_ifc_phrr_reg_bits {
8574 u8 reserved_1[0x10];
8577 u8 reserved_2[0x10];
8580 u8 reserved_3[0x40];
8582 u8 time_since_last_clear_high[0x20];
8584 u8 time_since_last_clear_low[0x20];
8589 struct mlx5_ifc_phbr_for_prio_reg_bits {
8590 u8 reserved_0[0x18];
8594 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8595 u8 reserved_0[0x18];
8599 struct mlx5_ifc_phbr_binding_reg_bits {
8607 u8 reserved_2[0x10];
8610 u8 reserved_3[0x10];
8613 u8 hist_parameters[0x20];
8615 u8 hist_min_value[0x20];
8617 u8 hist_max_value[0x20];
8619 u8 sample_time[0x20];
8623 MLX5_PFCC_REG_PPAN_DISABLED = 0x0,
8624 MLX5_PFCC_REG_PPAN_ENABLED = 0x1,
8627 struct mlx5_ifc_pfcc_reg_bits {
8628 u8 dcbx_operation_type[0x2];
8629 u8 cap_local_admin[0x1];
8630 u8 cap_remote_admin[0x1];
8640 u8 prio_mask_tx[0x8];
8642 u8 prio_mask_rx[0x8];
8658 u8 device_stall_minor_watermark[0x10];
8659 u8 device_stall_critical_watermark[0x10];
8661 u8 reserved_8[0x60];
8664 struct mlx5_ifc_pelc_reg_bits {
8668 u8 reserved_1[0x10];
8671 u8 op_capability[0x8];
8677 u8 capability[0x40];
8683 u8 reserved_2[0x80];
8686 struct mlx5_ifc_peir_reg_bits {
8689 u8 reserved_1[0x10];
8692 u8 error_count[0x4];
8693 u8 reserved_3[0x10];
8701 struct mlx5_ifc_qcam_access_reg_cap_mask {
8702 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8704 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8708 u8 qcam_access_reg_cap_mask_0[0x1];
8711 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8712 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8713 u8 qpts_trust_both[0x1];
8716 struct mlx5_ifc_qcam_reg_bits {
8717 u8 reserved_at_0[0x8];
8718 u8 feature_group[0x8];
8719 u8 reserved_at_10[0x8];
8720 u8 access_reg_group[0x8];
8721 u8 reserved_at_20[0x20];
8724 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8725 u8 reserved_at_0[0x80];
8726 } qos_access_reg_cap_mask;
8728 u8 reserved_at_c0[0x80];
8731 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8732 u8 reserved_at_0[0x80];
8733 } qos_feature_cap_mask;
8735 u8 reserved_at_1c0[0x80];
8738 struct mlx5_ifc_pcam_enhanced_features_bits {
8739 u8 reserved_at_0[0x6d];
8740 u8 rx_icrc_encapsulated_counter[0x1];
8741 u8 reserved_at_6e[0x4];
8742 u8 ptys_extended_ethernet[0x1];
8743 u8 reserved_at_73[0x3];
8745 u8 reserved_at_77[0x3];
8746 u8 per_lane_error_counters[0x1];
8747 u8 rx_buffer_fullness_counters[0x1];
8748 u8 ptys_connector_type[0x1];
8749 u8 reserved_at_7d[0x1];
8750 u8 ppcnt_discard_group[0x1];
8751 u8 ppcnt_statistical_group[0x1];
8754 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8755 u8 port_access_reg_cap_mask_127_to_96[0x20];
8756 u8 port_access_reg_cap_mask_95_to_64[0x20];
8758 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8760 u8 port_access_reg_cap_mask_34_to_32[0x3];
8762 u8 port_access_reg_cap_mask_31_to_13[0x13];
8765 u8 port_access_reg_cap_mask_10_to_09[0x2];
8767 u8 port_access_reg_cap_mask_07_to_00[0x8];
8770 struct mlx5_ifc_pcam_reg_bits {
8771 u8 reserved_at_0[0x8];
8772 u8 feature_group[0x8];
8773 u8 reserved_at_10[0x8];
8774 u8 access_reg_group[0x8];
8776 u8 reserved_at_20[0x20];
8779 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8780 u8 reserved_at_0[0x80];
8781 } port_access_reg_cap_mask;
8783 u8 reserved_at_c0[0x80];
8786 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8787 u8 reserved_at_0[0x80];
8790 u8 reserved_at_1c0[0xc0];
8793 struct mlx5_ifc_mcam_enhanced_features_bits {
8794 u8 reserved_at_0[0x6e];
8795 u8 pcie_status_and_power[0x1];
8796 u8 reserved_at_111[0x10];
8797 u8 pcie_performance_group[0x1];
8800 struct mlx5_ifc_mcam_access_reg_bits {
8801 u8 reserved_at_0[0x1c];
8805 u8 reserved_at_1f[0x1];
8807 u8 regs_95_to_64[0x20];
8808 u8 regs_63_to_32[0x20];
8809 u8 regs_31_to_0[0x20];
8812 struct mlx5_ifc_mcam_reg_bits {
8813 u8 reserved_at_0[0x8];
8814 u8 feature_group[0x8];
8815 u8 reserved_at_10[0x8];
8816 u8 access_reg_group[0x8];
8818 u8 reserved_at_20[0x20];
8821 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8822 u8 reserved_at_0[0x80];
8823 } mng_access_reg_cap_mask;
8825 u8 reserved_at_c0[0x80];
8828 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8829 u8 reserved_at_0[0x80];
8830 } mng_feature_cap_mask;
8832 u8 reserved_at_1c0[0x80];
8835 struct mlx5_ifc_pcap_reg_bits {
8838 u8 reserved_1[0x10];
8840 u8 port_capability_mask[4][0x20];
8843 struct mlx5_ifc_pbmc_reg_bits {
8844 u8 reserved_at_0[0x8];
8846 u8 reserved_at_10[0x10];
8848 u8 xoff_timer_value[0x10];
8849 u8 xoff_refresh[0x10];
8851 u8 reserved_at_40[0x9];
8852 u8 fullness_threshold[0x7];
8853 u8 port_buffer_size[0x10];
8855 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8857 u8 reserved_at_2e0[0x40];
8860 struct mlx5_ifc_paos_reg_bits {
8864 u8 admin_status[0x4];
8866 u8 oper_status[0x4];
8870 u8 reserved_2[0x1c];
8873 u8 reserved_3[0x40];
8876 struct mlx5_ifc_pamp_reg_bits {
8878 u8 opamp_group[0x8];
8880 u8 opamp_group_type[0x4];
8882 u8 start_index[0x10];
8884 u8 num_of_indices[0xc];
8886 u8 index_data[18][0x10];
8889 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8890 u8 llr_rx_cells_high[0x20];
8892 u8 llr_rx_cells_low[0x20];
8894 u8 llr_rx_error_high[0x20];
8896 u8 llr_rx_error_low[0x20];
8898 u8 llr_rx_crc_error_high[0x20];
8900 u8 llr_rx_crc_error_low[0x20];
8902 u8 llr_tx_cells_high[0x20];
8904 u8 llr_tx_cells_low[0x20];
8906 u8 llr_tx_ret_cells_high[0x20];
8908 u8 llr_tx_ret_cells_low[0x20];
8910 u8 llr_tx_ret_events_high[0x20];
8912 u8 llr_tx_ret_events_low[0x20];
8914 u8 reserved_0[0x640];
8917 struct mlx5_ifc_mtmp_reg_bits {
8919 u8 reserved_at_1[0x18];
8920 u8 sensor_index[0x7];
8922 u8 reserved_at_20[0x10];
8923 u8 temperature[0x10];
8927 u8 reserved_at_42[0x0e];
8928 u8 max_temperature[0x10];
8931 u8 reserved_at_62[0x0e];
8932 u8 temperature_threshold_hi[0x10];
8934 u8 reserved_at_80[0x10];
8935 u8 temperature_threshold_lo[0x10];
8937 u8 reserved_at_100[0x20];
8939 u8 sensor_name[0x40];
8942 struct mlx5_ifc_lane_2_module_mapping_bits {
8951 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8952 u8 transmit_queue_high[0x20];
8954 u8 transmit_queue_low[0x20];
8956 u8 reserved_0[0x780];
8959 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8960 u8 no_buffer_discard_uc_high[0x20];
8962 u8 no_buffer_discard_uc_low[0x20];
8964 u8 wred_discard_high[0x20];
8966 u8 wred_discard_low[0x20];
8968 u8 reserved_0[0x740];
8971 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8972 u8 rx_octets_high[0x20];
8974 u8 rx_octets_low[0x20];
8976 u8 reserved_0[0xc0];
8978 u8 rx_frames_high[0x20];
8980 u8 rx_frames_low[0x20];
8982 u8 tx_octets_high[0x20];
8984 u8 tx_octets_low[0x20];
8986 u8 reserved_1[0xc0];
8988 u8 tx_frames_high[0x20];
8990 u8 tx_frames_low[0x20];
8992 u8 rx_pause_high[0x20];
8994 u8 rx_pause_low[0x20];
8996 u8 rx_pause_duration_high[0x20];
8998 u8 rx_pause_duration_low[0x20];
9000 u8 tx_pause_high[0x20];
9002 u8 tx_pause_low[0x20];
9004 u8 tx_pause_duration_high[0x20];
9006 u8 tx_pause_duration_low[0x20];
9008 u8 rx_pause_transition_high[0x20];
9010 u8 rx_pause_transition_low[0x20];
9012 u8 rx_discards_high[0x20];
9014 u8 rx_discards_low[0x20];
9016 u8 device_stall_minor_watermark_cnt_high[0x20];
9018 u8 device_stall_minor_watermark_cnt_low[0x20];
9020 u8 device_stall_critical_watermark_cnt_high[0x20];
9022 u8 device_stall_critical_watermark_cnt_low[0x20];
9024 u8 reserved_2[0x340];
9027 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9028 u8 port_transmit_wait_high[0x20];
9030 u8 port_transmit_wait_low[0x20];
9032 u8 ecn_marked_high[0x20];
9034 u8 ecn_marked_low[0x20];
9036 u8 no_buffer_discard_mc_high[0x20];
9038 u8 no_buffer_discard_mc_low[0x20];
9040 u8 rx_ebp_high[0x20];
9042 u8 rx_ebp_low[0x20];
9044 u8 tx_ebp_high[0x20];
9046 u8 tx_ebp_low[0x20];
9048 u8 rx_buffer_almost_full_high[0x20];
9050 u8 rx_buffer_almost_full_low[0x20];
9052 u8 rx_buffer_full_high[0x20];
9054 u8 rx_buffer_full_low[0x20];
9056 u8 rx_icrc_encapsulated_high[0x20];
9058 u8 rx_icrc_encapsulated_low[0x20];
9060 u8 reserved_0[0x80];
9062 u8 tx_stats_pkts64octets_high[0x20];
9064 u8 tx_stats_pkts64octets_low[0x20];
9066 u8 tx_stats_pkts65to127octets_high[0x20];
9068 u8 tx_stats_pkts65to127octets_low[0x20];
9070 u8 tx_stats_pkts128to255octets_high[0x20];
9072 u8 tx_stats_pkts128to255octets_low[0x20];
9074 u8 tx_stats_pkts256to511octets_high[0x20];
9076 u8 tx_stats_pkts256to511octets_low[0x20];
9078 u8 tx_stats_pkts512to1023octets_high[0x20];
9080 u8 tx_stats_pkts512to1023octets_low[0x20];
9082 u8 tx_stats_pkts1024to1518octets_high[0x20];
9084 u8 tx_stats_pkts1024to1518octets_low[0x20];
9086 u8 tx_stats_pkts1519to2047octets_high[0x20];
9088 u8 tx_stats_pkts1519to2047octets_low[0x20];
9090 u8 tx_stats_pkts2048to4095octets_high[0x20];
9092 u8 tx_stats_pkts2048to4095octets_low[0x20];
9094 u8 tx_stats_pkts4096to8191octets_high[0x20];
9096 u8 tx_stats_pkts4096to8191octets_low[0x20];
9098 u8 tx_stats_pkts8192to10239octets_high[0x20];
9100 u8 tx_stats_pkts8192to10239octets_low[0x20];
9102 u8 reserved_1[0x2C0];
9105 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9106 u8 a_frames_transmitted_ok_high[0x20];
9108 u8 a_frames_transmitted_ok_low[0x20];
9110 u8 a_frames_received_ok_high[0x20];
9112 u8 a_frames_received_ok_low[0x20];
9114 u8 a_frame_check_sequence_errors_high[0x20];
9116 u8 a_frame_check_sequence_errors_low[0x20];
9118 u8 a_alignment_errors_high[0x20];
9120 u8 a_alignment_errors_low[0x20];
9122 u8 a_octets_transmitted_ok_high[0x20];
9124 u8 a_octets_transmitted_ok_low[0x20];
9126 u8 a_octets_received_ok_high[0x20];
9128 u8 a_octets_received_ok_low[0x20];
9130 u8 a_multicast_frames_xmitted_ok_high[0x20];
9132 u8 a_multicast_frames_xmitted_ok_low[0x20];
9134 u8 a_broadcast_frames_xmitted_ok_high[0x20];
9136 u8 a_broadcast_frames_xmitted_ok_low[0x20];
9138 u8 a_multicast_frames_received_ok_high[0x20];
9140 u8 a_multicast_frames_received_ok_low[0x20];
9142 u8 a_broadcast_frames_recieved_ok_high[0x20];
9144 u8 a_broadcast_frames_recieved_ok_low[0x20];
9146 u8 a_in_range_length_errors_high[0x20];
9148 u8 a_in_range_length_errors_low[0x20];
9150 u8 a_out_of_range_length_field_high[0x20];
9152 u8 a_out_of_range_length_field_low[0x20];
9154 u8 a_frame_too_long_errors_high[0x20];
9156 u8 a_frame_too_long_errors_low[0x20];
9158 u8 a_symbol_error_during_carrier_high[0x20];
9160 u8 a_symbol_error_during_carrier_low[0x20];
9162 u8 a_mac_control_frames_transmitted_high[0x20];
9164 u8 a_mac_control_frames_transmitted_low[0x20];
9166 u8 a_mac_control_frames_received_high[0x20];
9168 u8 a_mac_control_frames_received_low[0x20];
9170 u8 a_unsupported_opcodes_received_high[0x20];
9172 u8 a_unsupported_opcodes_received_low[0x20];
9174 u8 a_pause_mac_ctrl_frames_received_high[0x20];
9176 u8 a_pause_mac_ctrl_frames_received_low[0x20];
9178 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
9180 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
9182 u8 reserved_0[0x300];
9185 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9186 u8 dot3stats_alignment_errors_high[0x20];
9188 u8 dot3stats_alignment_errors_low[0x20];
9190 u8 dot3stats_fcs_errors_high[0x20];
9192 u8 dot3stats_fcs_errors_low[0x20];
9194 u8 dot3stats_single_collision_frames_high[0x20];
9196 u8 dot3stats_single_collision_frames_low[0x20];
9198 u8 dot3stats_multiple_collision_frames_high[0x20];
9200 u8 dot3stats_multiple_collision_frames_low[0x20];
9202 u8 dot3stats_sqe_test_errors_high[0x20];
9204 u8 dot3stats_sqe_test_errors_low[0x20];
9206 u8 dot3stats_deferred_transmissions_high[0x20];
9208 u8 dot3stats_deferred_transmissions_low[0x20];
9210 u8 dot3stats_late_collisions_high[0x20];
9212 u8 dot3stats_late_collisions_low[0x20];
9214 u8 dot3stats_excessive_collisions_high[0x20];
9216 u8 dot3stats_excessive_collisions_low[0x20];
9218 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
9220 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
9222 u8 dot3stats_carrier_sense_errors_high[0x20];
9224 u8 dot3stats_carrier_sense_errors_low[0x20];
9226 u8 dot3stats_frame_too_longs_high[0x20];
9228 u8 dot3stats_frame_too_longs_low[0x20];
9230 u8 dot3stats_internal_mac_receive_errors_high[0x20];
9232 u8 dot3stats_internal_mac_receive_errors_low[0x20];
9234 u8 dot3stats_symbol_errors_high[0x20];
9236 u8 dot3stats_symbol_errors_low[0x20];
9238 u8 dot3control_in_unknown_opcodes_high[0x20];
9240 u8 dot3control_in_unknown_opcodes_low[0x20];
9242 u8 dot3in_pause_frames_high[0x20];
9244 u8 dot3in_pause_frames_low[0x20];
9246 u8 dot3out_pause_frames_high[0x20];
9248 u8 dot3out_pause_frames_low[0x20];
9250 u8 reserved_0[0x3c0];
9253 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9254 u8 if_in_octets_high[0x20];
9256 u8 if_in_octets_low[0x20];
9258 u8 if_in_ucast_pkts_high[0x20];
9260 u8 if_in_ucast_pkts_low[0x20];
9262 u8 if_in_discards_high[0x20];
9264 u8 if_in_discards_low[0x20];
9266 u8 if_in_errors_high[0x20];
9268 u8 if_in_errors_low[0x20];
9270 u8 if_in_unknown_protos_high[0x20];
9272 u8 if_in_unknown_protos_low[0x20];
9274 u8 if_out_octets_high[0x20];
9276 u8 if_out_octets_low[0x20];
9278 u8 if_out_ucast_pkts_high[0x20];
9280 u8 if_out_ucast_pkts_low[0x20];
9282 u8 if_out_discards_high[0x20];
9284 u8 if_out_discards_low[0x20];
9286 u8 if_out_errors_high[0x20];
9288 u8 if_out_errors_low[0x20];
9290 u8 if_in_multicast_pkts_high[0x20];
9292 u8 if_in_multicast_pkts_low[0x20];
9294 u8 if_in_broadcast_pkts_high[0x20];
9296 u8 if_in_broadcast_pkts_low[0x20];
9298 u8 if_out_multicast_pkts_high[0x20];
9300 u8 if_out_multicast_pkts_low[0x20];
9302 u8 if_out_broadcast_pkts_high[0x20];
9304 u8 if_out_broadcast_pkts_low[0x20];
9306 u8 reserved_0[0x480];
9309 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9310 u8 ether_stats_drop_events_high[0x20];
9312 u8 ether_stats_drop_events_low[0x20];
9314 u8 ether_stats_octets_high[0x20];
9316 u8 ether_stats_octets_low[0x20];
9318 u8 ether_stats_pkts_high[0x20];
9320 u8 ether_stats_pkts_low[0x20];
9322 u8 ether_stats_broadcast_pkts_high[0x20];
9324 u8 ether_stats_broadcast_pkts_low[0x20];
9326 u8 ether_stats_multicast_pkts_high[0x20];
9328 u8 ether_stats_multicast_pkts_low[0x20];
9330 u8 ether_stats_crc_align_errors_high[0x20];
9332 u8 ether_stats_crc_align_errors_low[0x20];
9334 u8 ether_stats_undersize_pkts_high[0x20];
9336 u8 ether_stats_undersize_pkts_low[0x20];
9338 u8 ether_stats_oversize_pkts_high[0x20];
9340 u8 ether_stats_oversize_pkts_low[0x20];
9342 u8 ether_stats_fragments_high[0x20];
9344 u8 ether_stats_fragments_low[0x20];
9346 u8 ether_stats_jabbers_high[0x20];
9348 u8 ether_stats_jabbers_low[0x20];
9350 u8 ether_stats_collisions_high[0x20];
9352 u8 ether_stats_collisions_low[0x20];
9354 u8 ether_stats_pkts64octets_high[0x20];
9356 u8 ether_stats_pkts64octets_low[0x20];
9358 u8 ether_stats_pkts65to127octets_high[0x20];
9360 u8 ether_stats_pkts65to127octets_low[0x20];
9362 u8 ether_stats_pkts128to255octets_high[0x20];
9364 u8 ether_stats_pkts128to255octets_low[0x20];
9366 u8 ether_stats_pkts256to511octets_high[0x20];
9368 u8 ether_stats_pkts256to511octets_low[0x20];
9370 u8 ether_stats_pkts512to1023octets_high[0x20];
9372 u8 ether_stats_pkts512to1023octets_low[0x20];
9374 u8 ether_stats_pkts1024to1518octets_high[0x20];
9376 u8 ether_stats_pkts1024to1518octets_low[0x20];
9378 u8 ether_stats_pkts1519to2047octets_high[0x20];
9380 u8 ether_stats_pkts1519to2047octets_low[0x20];
9382 u8 ether_stats_pkts2048to4095octets_high[0x20];
9384 u8 ether_stats_pkts2048to4095octets_low[0x20];
9386 u8 ether_stats_pkts4096to8191octets_high[0x20];
9388 u8 ether_stats_pkts4096to8191octets_low[0x20];
9390 u8 ether_stats_pkts8192to10239octets_high[0x20];
9392 u8 ether_stats_pkts8192to10239octets_low[0x20];
9394 u8 reserved_0[0x280];
9397 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9398 u8 symbol_error_counter[0x10];
9399 u8 link_error_recovery_counter[0x8];
9400 u8 link_downed_counter[0x8];
9402 u8 port_rcv_errors[0x10];
9403 u8 port_rcv_remote_physical_errors[0x10];
9405 u8 port_rcv_switch_relay_errors[0x10];
9406 u8 port_xmit_discards[0x10];
9408 u8 port_xmit_constraint_errors[0x8];
9409 u8 port_rcv_constraint_errors[0x8];
9411 u8 local_link_integrity_errors[0x4];
9412 u8 excessive_buffer_overrun_errors[0x4];
9414 u8 reserved_1[0x10];
9415 u8 vl_15_dropped[0x10];
9417 u8 port_xmit_data[0x20];
9419 u8 port_rcv_data[0x20];
9421 u8 port_xmit_pkts[0x20];
9423 u8 port_rcv_pkts[0x20];
9425 u8 port_xmit_wait[0x20];
9427 u8 reserved_2[0x680];
9430 struct mlx5_ifc_trc_tlb_reg_bits {
9431 u8 reserved_0[0x80];
9433 u8 tlb_addr[0][0x40];
9436 struct mlx5_ifc_trc_read_fifo_reg_bits {
9437 u8 reserved_0[0x10];
9438 u8 requested_event_num[0x10];
9440 u8 reserved_1[0x20];
9442 u8 reserved_2[0x10];
9443 u8 acual_event_num[0x10];
9445 u8 reserved_3[0x20];
9450 struct mlx5_ifc_trc_lock_reg_bits {
9451 u8 reserved_0[0x1f];
9454 u8 reserved_1[0x60];
9457 struct mlx5_ifc_trc_filter_reg_bits {
9460 u8 filter_index[0x10];
9462 u8 reserved_1[0x20];
9464 u8 filter_val[0x20];
9466 u8 reserved_2[0x1a0];
9469 struct mlx5_ifc_trc_event_reg_bits {
9472 u8 event_index[0x10];
9474 u8 reserved_1[0x20];
9478 u8 event_selector_val[0x10];
9479 u8 event_selector_size[0x10];
9481 u8 reserved_2[0x180];
9484 struct mlx5_ifc_trc_conf_reg_bits {
9488 u8 reserved_1[0x15];
9491 u8 reserved_2[0x20];
9493 u8 limit_event_index[0x20];
9497 u8 fifo_ready_ev_num[0x20];
9499 u8 reserved_3[0x160];
9502 struct mlx5_ifc_trc_cap_reg_bits {
9503 u8 reserved_0[0x18];
9506 u8 reserved_1[0x20];
9508 u8 num_of_events[0x10];
9509 u8 num_of_filters[0x10];
9514 u8 event_size[0x10];
9516 u8 reserved_2[0x160];
9519 struct mlx5_ifc_set_node_in_bits {
9520 u8 node_description[64][0x8];
9523 struct mlx5_ifc_register_power_settings_bits {
9524 u8 reserved_0[0x18];
9525 u8 power_settings_level[0x8];
9527 u8 reserved_1[0x60];
9530 struct mlx5_ifc_register_host_endianess_bits {
9532 u8 reserved_0[0x1f];
9534 u8 reserved_1[0x60];
9537 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9538 u8 physical_address[0x40];
9541 struct mlx5_ifc_qtct_reg_bits {
9542 u8 operation_type[0x2];
9543 u8 cap_local_admin[0x1];
9544 u8 cap_remote_admin[0x1];
9546 u8 port_number[0x8];
9550 u8 reserved_2[0x1d];
9554 struct mlx5_ifc_qpdp_reg_bits {
9556 u8 port_number[0x8];
9557 u8 reserved_1[0x10];
9559 u8 reserved_2[0x1d];
9563 struct mlx5_ifc_port_info_ro_fields_param_bits {
9568 u8 reserved_1[0x20];
9573 struct mlx5_ifc_nvqc_reg_bits {
9576 u8 reserved_0[0x18];
9583 struct mlx5_ifc_nvia_reg_bits {
9584 u8 reserved_0[0x1d];
9587 u8 reserved_1[0x20];
9590 struct mlx5_ifc_nvdi_reg_bits {
9591 struct mlx5_ifc_config_item_bits configuration_item_header;
9594 struct mlx5_ifc_nvda_reg_bits {
9595 struct mlx5_ifc_config_item_bits configuration_item_header;
9597 u8 configuration_item_data[0x20];
9600 struct mlx5_ifc_node_info_ro_fields_param_bits {
9601 u8 system_image_guid[0x40];
9603 u8 reserved_0[0x40];
9607 u8 reserved_1[0x10];
9610 u8 reserved_2[0x20];
9613 struct mlx5_ifc_ets_tcn_config_reg_bits {
9620 u8 bw_allocation[0x7];
9623 u8 max_bw_units[0x4];
9625 u8 max_bw_value[0x8];
9628 struct mlx5_ifc_ets_global_config_reg_bits {
9631 u8 reserved_1[0x1d];
9634 u8 max_bw_units[0x4];
9636 u8 max_bw_value[0x8];
9639 struct mlx5_ifc_qetc_reg_bits {
9640 u8 reserved_at_0[0x8];
9641 u8 port_number[0x8];
9642 u8 reserved_at_10[0x30];
9644 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9645 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9648 struct mlx5_ifc_nodnic_mac_filters_bits {
9649 struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9651 struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9653 struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9655 struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9657 struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9659 u8 reserved_0[0xc0];
9662 struct mlx5_ifc_nodnic_gid_filters_bits {
9663 u8 mgid_filter0[16][0x8];
9665 u8 mgid_filter1[16][0x8];
9667 u8 mgid_filter2[16][0x8];
9669 u8 mgid_filter3[16][0x8];
9673 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0,
9674 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1,
9678 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0,
9679 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1,
9682 struct mlx5_ifc_nodnic_config_reg_bits {
9683 u8 no_dram_nic_revision[0x8];
9684 u8 hardware_format[0x8];
9685 u8 support_receive_filter[0x1];
9686 u8 support_promisc_filter[0x1];
9687 u8 support_promisc_multicast_filter[0x1];
9689 u8 log_working_buffer_size[0x3];
9690 u8 log_pkey_table_size[0x4];
9695 u8 log_max_ring_size[0x6];
9696 u8 reserved_3[0x18];
9701 u8 reserved_4[0x1c];
9705 u8 reserved_5[0x740];
9707 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9709 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9712 struct mlx5_ifc_vlan_layout_bits {
9713 u8 reserved_0[0x14];
9716 u8 reserved_1[0x20];
9719 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9720 u8 reserved_0[0x20];
9724 u8 addressh_63_32[0x20];
9726 u8 addressl_31_0[0x20];
9729 struct mlx5_ifc_ud_adrs_vector_bits {
9734 u8 destination_qp_dct[0x18];
9736 u8 static_rate[0x4];
9737 u8 sl_eth_prio[0x4];
9740 u8 rlid_udp_sport[0x10];
9742 u8 reserved_1[0x20];
9744 u8 rmac_47_16[0x20];
9753 u8 src_addr_index[0x8];
9754 u8 flow_label[0x14];
9756 u8 rgid_rip[16][0x8];
9759 struct mlx5_ifc_port_module_event_bits {
9763 u8 module_status[0x4];
9765 u8 reserved_2[0x14];
9769 u8 reserved_4[0xa0];
9772 struct mlx5_ifc_icmd_control_bits {
9779 struct mlx5_ifc_eqe_bits {
9783 u8 event_sub_type[0x8];
9785 u8 reserved_2[0xe0];
9787 union mlx5_ifc_event_auto_bits event_data;
9789 u8 reserved_3[0x10];
9796 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9799 struct mlx5_ifc_cmd_queue_entry_bits {
9801 u8 reserved_0[0x18];
9803 u8 input_length[0x20];
9805 u8 input_mailbox_pointer_63_32[0x20];
9807 u8 input_mailbox_pointer_31_9[0x17];
9810 u8 command_input_inline_data[16][0x8];
9812 u8 command_output_inline_data[16][0x8];
9814 u8 output_mailbox_pointer_63_32[0x20];
9816 u8 output_mailbox_pointer_31_9[0x17];
9819 u8 output_length[0x20];
9828 struct mlx5_ifc_cmd_out_bits {
9830 u8 reserved_0[0x18];
9834 u8 command_output[0x20];
9837 struct mlx5_ifc_cmd_in_bits {
9839 u8 reserved_0[0x10];
9841 u8 reserved_1[0x10];
9844 u8 command[0][0x20];
9847 struct mlx5_ifc_cmd_if_box_bits {
9848 u8 mailbox_data[512][0x8];
9850 u8 reserved_0[0x180];
9852 u8 next_pointer_63_32[0x20];
9854 u8 next_pointer_31_10[0x16];
9857 u8 block_number[0x20];
9861 u8 ctrl_signature[0x8];
9865 struct mlx5_ifc_mtt_bits {
9866 u8 ptag_63_32[0x20];
9874 struct mlx5_ifc_tls_progress_params_bits {
9876 u8 reserved_at_1[0x7];
9879 u8 next_record_tcp_sn[0x20];
9881 u8 hw_resync_tcp_sn[0x20];
9883 u8 record_tracker_state[0x2];
9885 u8 reserved_at_64[0x4];
9886 u8 hw_offset_record_number[0x18];
9889 struct mlx5_ifc_tls_static_params_bits {
9891 u8 tls_version[0x4];
9893 u8 reserved_at_8[0x14];
9894 u8 encryption_standard[0x4];
9896 u8 reserved_at_20[0x20];
9898 u8 initial_record_number[0x40];
9900 u8 resync_tcp_sn[0x20];
9904 u8 implicit_iv[0x40];
9906 u8 reserved_at_100[0x8];
9909 u8 reserved_at_120[0xe0];
9912 /* Vendor Specific Capabilities, VSC */
9914 MLX5_VSC_DOMAIN_ICMD = 0x1,
9915 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6,
9916 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7,
9917 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA,
9920 struct mlx5_ifc_vendor_specific_cap_bits {
9923 u8 next_pointer[0x8];
9924 u8 capability_id[0x8];
9941 struct mlx5_ifc_vsc_space_bits {
9947 struct mlx5_ifc_vsc_addr_bits {
9954 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9955 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9956 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9960 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9961 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9962 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9966 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
9967 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
9968 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
9969 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
9970 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
9971 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
9972 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
9973 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
9974 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
9975 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
9976 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10,
9979 struct mlx5_ifc_initial_seg_bits {
9980 u8 fw_rev_minor[0x10];
9981 u8 fw_rev_major[0x10];
9983 u8 cmd_interface_rev[0x10];
9984 u8 fw_rev_subminor[0x10];
9986 u8 reserved_0[0x40];
9988 u8 cmdq_phy_addr_63_32[0x20];
9990 u8 cmdq_phy_addr_31_12[0x14];
9992 u8 nic_interface[0x2];
9993 u8 log_cmdq_size[0x4];
9994 u8 log_cmdq_stride[0x4];
9996 u8 command_doorbell_vector[0x20];
9998 u8 reserved_2[0xf00];
10000 u8 initializing[0x1];
10001 u8 reserved_3[0x4];
10002 u8 nic_interface_supported[0x3];
10003 u8 reserved_4[0x18];
10005 struct mlx5_ifc_health_buffer_bits health_buffer;
10007 u8 no_dram_nic_offset[0x20];
10009 u8 reserved_5[0x6de0];
10011 u8 internal_timer_h[0x20];
10013 u8 internal_timer_l[0x20];
10015 u8 reserved_6[0x20];
10017 u8 reserved_7[0x1f];
10020 u8 health_syndrome[0x8];
10021 u8 health_counter[0x18];
10023 u8 reserved_8[0x17fc0];
10026 union mlx5_ifc_icmd_interface_document_bits {
10027 struct mlx5_ifc_fw_version_bits fw_version;
10028 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10029 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10030 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10031 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10032 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10033 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10034 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10035 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10036 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10037 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10038 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10039 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10040 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10041 u8 reserved_0[0x42c0];
10044 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10045 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10046 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10047 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10048 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10049 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10050 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10051 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10052 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10053 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10054 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10055 u8 reserved_0[0x7c0];
10058 struct mlx5_ifc_ppcnt_reg_bits {
10060 u8 local_port[0x8];
10062 u8 reserved_0[0x8];
10066 u8 reserved_1[0x1c];
10069 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10072 struct mlx5_ifc_pcie_lanes_counters_bits {
10073 u8 life_time_counter_high[0x20];
10075 u8 life_time_counter_low[0x20];
10077 u8 error_counter_lane0[0x20];
10079 u8 error_counter_lane1[0x20];
10081 u8 error_counter_lane2[0x20];
10083 u8 error_counter_lane3[0x20];
10085 u8 error_counter_lane4[0x20];
10087 u8 error_counter_lane5[0x20];
10089 u8 error_counter_lane6[0x20];
10091 u8 error_counter_lane7[0x20];
10093 u8 error_counter_lane8[0x20];
10095 u8 error_counter_lane9[0x20];
10097 u8 error_counter_lane10[0x20];
10099 u8 error_counter_lane11[0x20];
10101 u8 error_counter_lane12[0x20];
10103 u8 error_counter_lane13[0x20];
10105 u8 error_counter_lane14[0x20];
10107 u8 error_counter_lane15[0x20];
10109 u8 reserved_at_240[0x580];
10112 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10113 u8 reserved_at_0[0x40];
10115 u8 error_counter_lane0[0x20];
10117 u8 error_counter_lane1[0x20];
10119 u8 error_counter_lane2[0x20];
10121 u8 error_counter_lane3[0x20];
10123 u8 error_counter_lane4[0x20];
10125 u8 error_counter_lane5[0x20];
10127 u8 error_counter_lane6[0x20];
10129 u8 error_counter_lane7[0x20];
10131 u8 error_counter_lane8[0x20];
10133 u8 error_counter_lane9[0x20];
10135 u8 error_counter_lane10[0x20];
10137 u8 error_counter_lane11[0x20];
10139 u8 error_counter_lane12[0x20];
10141 u8 error_counter_lane13[0x20];
10143 u8 error_counter_lane14[0x20];
10145 u8 error_counter_lane15[0x20];
10147 u8 reserved_at_240[0x580];
10150 struct mlx5_ifc_pcie_perf_counters_bits {
10151 u8 life_time_counter_high[0x20];
10153 u8 life_time_counter_low[0x20];
10155 u8 rx_errors[0x20];
10157 u8 tx_errors[0x20];
10159 u8 l0_to_recovery_eieos[0x20];
10161 u8 l0_to_recovery_ts[0x20];
10163 u8 l0_to_recovery_framing[0x20];
10165 u8 l0_to_recovery_retrain[0x20];
10167 u8 crc_error_dllp[0x20];
10169 u8 crc_error_tlp[0x20];
10171 u8 tx_overflow_buffer_pkt[0x40];
10173 u8 outbound_stalled_reads[0x20];
10175 u8 outbound_stalled_writes[0x20];
10177 u8 outbound_stalled_reads_events[0x20];
10179 u8 outbound_stalled_writes_events[0x20];
10181 u8 tx_overflow_buffer_marked_pkt[0x40];
10183 u8 reserved_at_240[0x580];
10186 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10187 u8 reserved_at_0[0x40];
10189 u8 rx_errors[0x20];
10191 u8 tx_errors[0x20];
10193 u8 reserved_at_80[0xc0];
10195 u8 tx_overflow_buffer_pkt[0x40];
10197 u8 outbound_stalled_reads[0x20];
10199 u8 outbound_stalled_writes[0x20];
10201 u8 outbound_stalled_reads_events[0x20];
10203 u8 outbound_stalled_writes_events[0x20];
10205 u8 tx_overflow_buffer_marked_pkt[0x40];
10207 u8 reserved_at_240[0x580];
10210 struct mlx5_ifc_pcie_timers_states_bits {
10211 u8 life_time_counter_high[0x20];
10213 u8 life_time_counter_low[0x20];
10215 u8 time_to_boot_image_start[0x20];
10217 u8 time_to_link_image[0x20];
10219 u8 calibration_time[0x20];
10221 u8 time_to_first_perst[0x20];
10223 u8 time_to_detect_state[0x20];
10225 u8 time_to_l0[0x20];
10227 u8 time_to_crs_en[0x20];
10229 u8 time_to_plastic_image_start[0x20];
10231 u8 time_to_iron_image_start[0x20];
10233 u8 perst_handler[0x20];
10235 u8 times_in_l1[0x20];
10237 u8 times_in_l23[0x20];
10241 u8 config_cycle1usec[0x20];
10243 u8 config_cycle2to7usec[0x20];
10245 u8 config_cycle8to15usec[0x20];
10247 u8 config_cycle16to63usec[0x20];
10249 u8 config_cycle64usec[0x20];
10251 u8 correctable_err_msg_sent[0x20];
10253 u8 non_fatal_err_msg_sent[0x20];
10255 u8 fatal_err_msg_sent[0x20];
10257 u8 reserved_at_2e0[0x4e0];
10260 struct mlx5_ifc_pcie_timers_states_ext_bits {
10261 u8 reserved_at_0[0x40];
10263 u8 time_to_boot_image_start[0x20];
10265 u8 time_to_link_image[0x20];
10267 u8 calibration_time[0x20];
10269 u8 time_to_first_perst[0x20];
10271 u8 time_to_detect_state[0x20];
10273 u8 time_to_l0[0x20];
10275 u8 time_to_crs_en[0x20];
10277 u8 time_to_plastic_image_start[0x20];
10279 u8 time_to_iron_image_start[0x20];
10281 u8 perst_handler[0x20];
10283 u8 times_in_l1[0x20];
10285 u8 times_in_l23[0x20];
10289 u8 config_cycle1usec[0x20];
10291 u8 config_cycle2to7usec[0x20];
10293 u8 config_cycle8to15usec[0x20];
10295 u8 config_cycle16to63usec[0x20];
10297 u8 config_cycle64usec[0x20];
10299 u8 correctable_err_msg_sent[0x20];
10301 u8 non_fatal_err_msg_sent[0x20];
10303 u8 fatal_err_msg_sent[0x20];
10305 u8 reserved_at_2e0[0x4e0];
10308 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10309 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10310 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10311 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10312 u8 reserved_at_0[0x7c0];
10315 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10316 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10317 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10318 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10319 u8 reserved_at_0[0x7c0];
10322 struct mlx5_ifc_mpcnt_reg_bits {
10323 u8 reserved_at_0[0x2];
10325 u8 pcie_index[0x8];
10327 u8 reserved_at_18[0x2];
10331 u8 reserved_at_21[0x1f];
10333 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10336 struct mlx5_ifc_mpcnt_reg_ext_bits {
10337 u8 reserved_at_0[0x2];
10339 u8 pcie_index[0x8];
10341 u8 reserved_at_18[0x2];
10345 u8 reserved_at_21[0x1f];
10347 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10351 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10352 MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10353 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10354 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10357 struct mlx5_ifc_mpein_reg_bits {
10358 u8 reserved_at_0[0x2];
10360 u8 pcie_index[0x8];
10362 u8 reserved_at_18[0x8];
10364 u8 capability_mask[0x20];
10366 u8 reserved_at_40[0x8];
10367 u8 link_width_enabled[0x8];
10368 u8 link_speed_enabled[0x10];
10370 u8 lane0_physical_position[0x8];
10371 u8 link_width_active[0x8];
10372 u8 link_speed_active[0x10];
10374 u8 num_of_pfs[0x10];
10375 u8 num_of_vfs[0x10];
10378 u8 reserved_at_b0[0x10];
10380 u8 max_read_request_size[0x4];
10381 u8 max_payload_size[0x4];
10382 u8 reserved_at_c8[0x5];
10383 u8 pwr_status[0x3];
10385 u8 reserved_at_d4[0xb];
10386 u8 lane_reversal[0x1];
10388 u8 reserved_at_e0[0x14];
10391 u8 reserved_at_100[0x20];
10393 u8 device_status[0x10];
10394 u8 port_state[0x8];
10395 u8 reserved_at_138[0x8];
10397 u8 reserved_at_140[0x10];
10398 u8 receiver_detect_result[0x10];
10400 u8 reserved_at_160[0x20];
10403 struct mlx5_ifc_mpein_reg_ext_bits {
10404 u8 reserved_at_0[0x2];
10406 u8 pcie_index[0x8];
10408 u8 reserved_at_18[0x8];
10410 u8 reserved_at_20[0x20];
10412 u8 reserved_at_40[0x8];
10413 u8 link_width_enabled[0x8];
10414 u8 link_speed_enabled[0x10];
10416 u8 lane0_physical_position[0x8];
10417 u8 link_width_active[0x8];
10418 u8 link_speed_active[0x10];
10420 u8 num_of_pfs[0x10];
10421 u8 num_of_vfs[0x10];
10424 u8 reserved_at_b0[0x10];
10426 u8 max_read_request_size[0x4];
10427 u8 max_payload_size[0x4];
10428 u8 reserved_at_c8[0x5];
10429 u8 pwr_status[0x3];
10431 u8 reserved_at_d4[0xb];
10432 u8 lane_reversal[0x1];
10435 struct mlx5_ifc_mcqi_cap_bits {
10436 u8 supported_info_bitmask[0x20];
10438 u8 component_size[0x20];
10440 u8 max_component_size[0x20];
10442 u8 log_mcda_word_size[0x4];
10443 u8 reserved_at_64[0xc];
10444 u8 mcda_max_write_size[0x10];
10447 u8 reserved_at_81[0x1];
10448 u8 match_chip_id[0x1];
10449 u8 match_psid[0x1];
10450 u8 check_user_timestamp[0x1];
10451 u8 match_base_guid_mac[0x1];
10452 u8 reserved_at_86[0x1a];
10455 struct mlx5_ifc_mcqi_reg_bits {
10456 u8 read_pending_component[0x1];
10457 u8 reserved_at_1[0xf];
10458 u8 component_index[0x10];
10460 u8 reserved_at_20[0x20];
10462 u8 reserved_at_40[0x1b];
10465 u8 info_size[0x20];
10469 u8 reserved_at_a0[0x10];
10470 u8 data_size[0x10];
10475 struct mlx5_ifc_mcc_reg_bits {
10476 u8 reserved_at_0[0x4];
10477 u8 time_elapsed_since_last_cmd[0xc];
10478 u8 reserved_at_10[0x8];
10479 u8 instruction[0x8];
10481 u8 reserved_at_20[0x10];
10482 u8 component_index[0x10];
10484 u8 reserved_at_40[0x8];
10485 u8 update_handle[0x18];
10487 u8 handle_owner_type[0x4];
10488 u8 handle_owner_host_id[0x4];
10489 u8 reserved_at_68[0x1];
10490 u8 control_progress[0x7];
10491 u8 error_code[0x8];
10492 u8 reserved_at_78[0x4];
10493 u8 control_state[0x4];
10495 u8 component_size[0x20];
10497 u8 reserved_at_a0[0x60];
10500 struct mlx5_ifc_mcda_reg_bits {
10501 u8 reserved_at_0[0x8];
10502 u8 update_handle[0x18];
10506 u8 reserved_at_40[0x10];
10509 u8 reserved_at_60[0x20];
10514 union mlx5_ifc_ports_control_registers_document_bits {
10515 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10516 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10517 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10518 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10519 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10520 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10521 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10522 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10523 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10524 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10525 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10526 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10527 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10528 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10529 struct mlx5_ifc_paos_reg_bits paos_reg;
10530 struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10531 struct mlx5_ifc_pcap_reg_bits pcap_reg;
10532 struct mlx5_ifc_peir_reg_bits peir_reg;
10533 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10534 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10535 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10536 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10537 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10538 struct mlx5_ifc_phrr_reg_bits phrr_reg;
10539 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10540 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10541 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10542 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10543 struct mlx5_ifc_plib_reg_bits plib_reg;
10544 struct mlx5_ifc_pll_status_data_bits pll_status_data;
10545 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10546 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10547 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10548 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10549 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10550 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10551 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10552 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10553 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10554 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10555 struct mlx5_ifc_ppll_reg_bits ppll_reg;
10556 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10557 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10558 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10559 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10560 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10561 struct mlx5_ifc_ptys_reg_bits ptys_reg;
10562 struct mlx5_ifc_pude_reg_bits pude_reg;
10563 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10564 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10565 struct mlx5_ifc_slrp_reg_bits slrp_reg;
10566 struct mlx5_ifc_sltp_reg_bits sltp_reg;
10567 u8 reserved_0[0x7880];
10570 union mlx5_ifc_debug_enhancements_document_bits {
10571 struct mlx5_ifc_health_buffer_bits health_buffer;
10572 u8 reserved_0[0x200];
10575 union mlx5_ifc_no_dram_nic_document_bits {
10576 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10577 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10578 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10579 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10580 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10581 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10582 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10583 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10584 u8 reserved_0[0x3160];
10587 union mlx5_ifc_uplink_pci_interface_document_bits {
10588 struct mlx5_ifc_initial_seg_bits initial_seg;
10589 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10590 u8 reserved_0[0x20120];
10593 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10595 u8 reserved_at_01[0x0b];
10599 struct mlx5_ifc_qpdpm_reg_bits {
10600 u8 reserved_at_0[0x8];
10601 u8 local_port[0x8];
10602 u8 reserved_at_10[0x10];
10603 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10606 struct mlx5_ifc_qpts_reg_bits {
10607 u8 reserved_at_0[0x8];
10608 u8 local_port[0x8];
10609 u8 reserved_at_10[0x2d];
10610 u8 trust_state[0x3];
10613 struct mlx5_ifc_mfrl_reg_bits {
10614 u8 reserved_at_0[0x38];
10615 u8 reset_level[0x8];
10619 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009,
10620 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109,
10621 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a,
10622 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b,
10623 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f,
10624 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b,
10625 MLX5_MAX_TEMPERATURE = 16,
10628 struct mlx5_ifc_mtbr_temp_record_bits {
10629 u8 max_temperature[0x10];
10630 u8 temperature[0x10];
10633 struct mlx5_ifc_mtbr_reg_bits {
10634 u8 reserved_at_0[0x14];
10635 u8 base_sensor_index[0xc];
10637 u8 reserved_at_20[0x18];
10640 u8 reserved_at_40[0x40];
10642 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10645 struct mlx5_ifc_mtbr_reg_ext_bits {
10646 u8 reserved_at_0[0x14];
10647 u8 base_sensor_index[0xc];
10649 u8 reserved_at_20[0x18];
10652 u8 reserved_at_40[0x40];
10654 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10657 struct mlx5_ifc_mtcap_bits {
10658 u8 reserved_at_0[0x19];
10659 u8 sensor_count[0x7];
10661 u8 reserved_at_20[0x19];
10662 u8 internal_sensor_count[0x7];
10664 u8 sensor_map[0x40];
10667 struct mlx5_ifc_mtcap_ext_bits {
10668 u8 reserved_at_0[0x19];
10669 u8 sensor_count[0x7];
10671 u8 reserved_at_20[0x20];
10673 u8 sensor_map[0x40];
10676 struct mlx5_ifc_mtecr_bits {
10677 u8 reserved_at_0[0x4];
10678 u8 last_sensor[0xc];
10679 u8 reserved_at_10[0x4];
10680 u8 sensor_count[0xc];
10682 u8 reserved_at_20[0x19];
10683 u8 internal_sensor_count[0x7];
10685 u8 sensor_map_0[0x20];
10687 u8 reserved_at_60[0x2a0];
10690 struct mlx5_ifc_mtecr_ext_bits {
10691 u8 reserved_at_0[0x4];
10692 u8 last_sensor[0xc];
10693 u8 reserved_at_10[0x4];
10694 u8 sensor_count[0xc];
10696 u8 reserved_at_20[0x20];
10698 u8 sensor_map_0[0x20];
10700 u8 reserved_at_60[0x2a0];
10703 struct mlx5_ifc_mtewe_bits {
10704 u8 reserved_at_0[0x4];
10705 u8 last_sensor[0xc];
10706 u8 reserved_at_10[0x4];
10707 u8 sensor_count[0xc];
10709 u8 sensor_warning_0[0x20];
10711 u8 reserved_at_40[0x2a0];
10714 struct mlx5_ifc_mtewe_ext_bits {
10715 u8 reserved_at_0[0x4];
10716 u8 last_sensor[0xc];
10717 u8 reserved_at_10[0x4];
10718 u8 sensor_count[0xc];
10720 u8 sensor_warning_0[0x20];
10722 u8 reserved_at_40[0x2a0];
10725 struct mlx5_ifc_mtmp_bits {
10726 u8 reserved_at_0[0x14];
10727 u8 sensor_index[0xc];
10729 u8 reserved_at_20[0x10];
10730 u8 temperature[0x10];
10734 u8 reserved_at_42[0xe];
10735 u8 max_temperature[0x10];
10738 u8 reserved_at_62[0xe];
10739 u8 temperature_threshold_hi[0x10];
10741 u8 reserved_at_80[0x10];
10742 u8 temperature_threshold_lo[0x10];
10744 u8 reserved_at_a0[0x20];
10746 u8 sensor_name_hi[0x20];
10748 u8 sensor_name_lo[0x20];
10751 struct mlx5_ifc_mtmp_ext_bits {
10752 u8 reserved_at_0[0x14];
10753 u8 sensor_index[0xc];
10755 u8 reserved_at_20[0x10];
10756 u8 temperature[0x10];
10760 u8 reserved_at_42[0xe];
10761 u8 max_temperature[0x10];
10764 u8 reserved_at_62[0xe];
10765 u8 temperature_threshold_hi[0x10];
10767 u8 reserved_at_80[0x10];
10768 u8 temperature_threshold_lo[0x10];
10770 u8 reserved_at_a0[0x20];
10772 u8 sensor_name_hi[0x20];
10774 u8 sensor_name_lo[0x20];
10777 #endif /* MLX5_IFC_H */