sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
  32
  33 enum {
  34         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  35         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  36         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  37         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  38         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  39         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  40         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  41         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  42         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  43         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  44         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  45         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  46         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  47         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  48         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  49         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  50         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  51         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  52         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  53         MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
  54         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  56         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  57         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  58         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  59         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  60         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  61         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  62         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  63         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
  64         MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
  65         MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
  66         MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT                   = 0x27,
  67 };
  68
  69 enum {
  70         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  71         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  72         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  73         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  74         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  75 };
  76
  77 enum {
  78         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  79 };
  80
  81 enum {
  82         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  83         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  84 };
  85
  86 enum {
  87         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  88         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  89         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  90         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  91         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  92         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  93         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  94         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  95         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  96         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  97         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  98         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  99         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
 100         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 107         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 108         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 109         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 110         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 111         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 112         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 113         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 114         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 115         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 116         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 117         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 118         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 119         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 120         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 121         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 122         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 123         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 124         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 125         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 126         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 127         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 128         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 129         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 130         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 131         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 132         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 133         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 134         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 135         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 136         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 137         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 138         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 139         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 140         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 141         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 142         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 143         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 144         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 145         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 146         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 147         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 148         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 149         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 150         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 151         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 152         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 153         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 154         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 155         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 156         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 157         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 158         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 159         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 160         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 161         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 162         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 163         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 164         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 165         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 166         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 167         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 168         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 169         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 170         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 171         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 172         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 173         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 174         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 175         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 176         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 177         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 178         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 179         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 180         MLX5_CMD_OP_NOP                           = 0x80d,
 181         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 182         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 183         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 184         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 185         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 186         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 190         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 191         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 192         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 193         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 194         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 195         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 196         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 197         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 198         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 199         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 200         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 201         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 202         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 203         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 204         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 205         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 206         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 207         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 208         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 209         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 210         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 211         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 212         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 213         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 214         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 215         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 216         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 217         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 218         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 219         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 220         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 221         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 222         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 223         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 224         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 225         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 226         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 227         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 228         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 229         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 230         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 231         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 232         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 233         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 234         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 235         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 236         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 237         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 238         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 239         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 240         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 241         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 242         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 243         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 244         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 245         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 246         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 247         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 248         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 249         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 250         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
 260
 261 };
 262
 263 enum {
 264         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 265         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 266         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 267         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 268         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 269         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 270         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 271         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 272         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 273         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 274         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 275         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 276 };
 277
 278 enum {
 279         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
 280 };
 281
 282 enum {
 283         MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
 284 };
 285
 286 enum {
 287         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
 288         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
 289 };
 290
 291 enum {
 292         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
 293 };
 294
 295 struct mlx5_ifc_flow_table_fields_supported_bits {
 296         u8         outer_dmac[0x1];
 297         u8         outer_smac[0x1];
 298         u8         outer_ether_type[0x1];
 299         u8         reserved_0[0x1];
 300         u8         outer_first_prio[0x1];
 301         u8         outer_first_cfi[0x1];
 302         u8         outer_first_vid[0x1];
 303         u8         reserved_1[0x1];
 304         u8         outer_second_prio[0x1];
 305         u8         outer_second_cfi[0x1];
 306         u8         outer_second_vid[0x1];
 307         u8         outer_ipv6_flow_label[0x1];
 308         u8         outer_sip[0x1];
 309         u8         outer_dip[0x1];
 310         u8         outer_frag[0x1];
 311         u8         outer_ip_protocol[0x1];
 312         u8         outer_ip_ecn[0x1];
 313         u8         outer_ip_dscp[0x1];
 314         u8         outer_udp_sport[0x1];
 315         u8         outer_udp_dport[0x1];
 316         u8         outer_tcp_sport[0x1];
 317         u8         outer_tcp_dport[0x1];
 318         u8         outer_tcp_flags[0x1];
 319         u8         outer_gre_protocol[0x1];
 320         u8         outer_gre_key[0x1];
 321         u8         outer_vxlan_vni[0x1];
 322         u8         outer_geneve_vni[0x1];
 323         u8         outer_geneve_oam[0x1];
 324         u8         outer_geneve_protocol_type[0x1];
 325         u8         outer_geneve_opt_len[0x1];
 326         u8         reserved_2[0x1];
 327         u8         source_eswitch_port[0x1];
 328
 329         u8         inner_dmac[0x1];
 330         u8         inner_smac[0x1];
 331         u8         inner_ether_type[0x1];
 332         u8         reserved_3[0x1];
 333         u8         inner_first_prio[0x1];
 334         u8         inner_first_cfi[0x1];
 335         u8         inner_first_vid[0x1];
 336         u8         reserved_4[0x1];
 337         u8         inner_second_prio[0x1];
 338         u8         inner_second_cfi[0x1];
 339         u8         inner_second_vid[0x1];
 340         u8         inner_ipv6_flow_label[0x1];
 341         u8         inner_sip[0x1];
 342         u8         inner_dip[0x1];
 343         u8         inner_frag[0x1];
 344         u8         inner_ip_protocol[0x1];
 345         u8         inner_ip_ecn[0x1];
 346         u8         inner_ip_dscp[0x1];
 347         u8         inner_udp_sport[0x1];
 348         u8         inner_udp_dport[0x1];
 349         u8         inner_tcp_sport[0x1];
 350         u8         inner_tcp_dport[0x1];
 351         u8         inner_tcp_flags[0x1];
 352         u8         reserved_5[0x9];
 353
 354         u8         reserved_6[0x1a];
 355         u8         bth_dst_qp[0x1];
 356         u8         reserved_7[0x4];
 357         u8         source_sqn[0x1];
 358
 359         u8         reserved_8[0x20];
 360 };
 361
 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 363         u8         ingress_general_high[0x20];
 364
 365         u8         ingress_general_low[0x20];
 366
 367         u8         ingress_policy_engine_high[0x20];
 368
 369         u8         ingress_policy_engine_low[0x20];
 370
 371         u8         ingress_vlan_membership_high[0x20];
 372
 373         u8         ingress_vlan_membership_low[0x20];
 374
 375         u8         ingress_tag_frame_type_high[0x20];
 376
 377         u8         ingress_tag_frame_type_low[0x20];
 378
 379         u8         egress_vlan_membership_high[0x20];
 380
 381         u8         egress_vlan_membership_low[0x20];
 382
 383         u8         loopback_filter_high[0x20];
 384
 385         u8         loopback_filter_low[0x20];
 386
 387         u8         egress_general_high[0x20];
 388
 389         u8         egress_general_low[0x20];
 390
 391         u8         reserved_at_1c0[0x40];
 392
 393         u8         egress_hoq_high[0x20];
 394
 395         u8         egress_hoq_low[0x20];
 396
 397         u8         port_isolation_high[0x20];
 398
 399         u8         port_isolation_low[0x20];
 400
 401         u8         egress_policy_engine_high[0x20];
 402
 403         u8         egress_policy_engine_low[0x20];
 404
 405         u8         ingress_tx_link_down_high[0x20];
 406
 407         u8         ingress_tx_link_down_low[0x20];
 408
 409         u8         egress_stp_filter_high[0x20];
 410
 411         u8         egress_stp_filter_low[0x20];
 412
 413         u8         egress_hoq_stall_high[0x20];
 414
 415         u8         egress_hoq_stall_low[0x20];
 416
 417         u8         reserved_at_340[0x440];
 418 };
 419 struct mlx5_ifc_flow_table_prop_layout_bits {
 420         u8         ft_support[0x1];
 421         u8         flow_tag[0x1];
 422         u8         flow_counter[0x1];
 423         u8         flow_modify_en[0x1];
 424         u8         modify_root[0x1];
 425         u8         identified_miss_table[0x1];
 426         u8         flow_table_modify[0x1];
 427         u8         encap[0x1];
 428         u8         decap[0x1];
 429         u8         reset_root_to_default[0x1];
 430         u8         reserved_at_a[0x16];
 431
 432         u8         reserved_at_20[0x2];
 433         u8         log_max_ft_size[0x6];
 434         u8         reserved_at_28[0x10];
 435         u8         max_ft_level[0x8];
 436
 437         u8         reserved_at_40[0x20];
 438
 439         u8         reserved_at_60[0x18];
 440         u8         log_max_ft_num[0x8];
 441
 442         u8         reserved_at_80[0x10];
 443         u8         log_max_flow_counter[0x8];
 444         u8         log_max_destination[0x8];
 445
 446         u8         reserved_at_a0[0x18];
 447         u8         log_max_flow[0x8];
 448
 449         u8         reserved_at_c0[0x40];
 450
 451         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 452
 453         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 454 };
 455
 456 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 457         u8         send[0x1];
 458         u8         receive[0x1];
 459         u8         write[0x1];
 460         u8         read[0x1];
 461         u8         atomic[0x1];
 462         u8         srq_receive[0x1];
 463         u8         reserved_0[0x1a];
 464 };
 465
 466 struct mlx5_ifc_flow_counter_list_bits {
 467         u8         reserved_0[0x10];
 468         u8         flow_counter_id[0x10];
 469
 470         u8         reserved_1[0x20];
 471 };
 472
 473 enum {
 474         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 475         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 476         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 477         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 478 };
 479
 480 struct mlx5_ifc_dest_format_struct_bits {
 481         u8         destination_type[0x8];
 482         u8         destination_id[0x18];
 483
 484         u8         reserved_0[0x20];
 485 };
 486
 487 struct mlx5_ifc_ipv4_layout_bits {
 488         u8         reserved_at_0[0x60];
 489
 490         u8         ipv4[0x20];
 491 };
 492
 493 struct mlx5_ifc_ipv6_layout_bits {
 494         u8         ipv6[16][0x8];
 495 };
 496
 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 498         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 499         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 500         u8         reserved_at_0[0x80];
 501 };
 502
 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 504         u8         smac_47_16[0x20];
 505
 506         u8         smac_15_0[0x10];
 507         u8         ethertype[0x10];
 508
 509         u8         dmac_47_16[0x20];
 510
 511         u8         dmac_15_0[0x10];
 512         u8         first_prio[0x3];
 513         u8         first_cfi[0x1];
 514         u8         first_vid[0xc];
 515
 516         u8         ip_protocol[0x8];
 517         u8         ip_dscp[0x6];
 518         u8         ip_ecn[0x2];
 519         u8         cvlan_tag[0x1];
 520         u8         svlan_tag[0x1];
 521         u8         frag[0x1];
 522         u8         reserved_1[0x4];
 523         u8         tcp_flags[0x9];
 524
 525         u8         tcp_sport[0x10];
 526         u8         tcp_dport[0x10];
 527
 528         u8         reserved_2[0x20];
 529
 530         u8         udp_sport[0x10];
 531         u8         udp_dport[0x10];
 532
 533         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 534
 535         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 536 };
 537
 538 struct mlx5_ifc_fte_match_set_misc_bits {
 539         u8         reserved_0[0x8];
 540         u8         source_sqn[0x18];
 541
 542         u8         reserved_1[0x10];
 543         u8         source_port[0x10];
 544
 545         u8         outer_second_prio[0x3];
 546         u8         outer_second_cfi[0x1];
 547         u8         outer_second_vid[0xc];
 548         u8         inner_second_prio[0x3];
 549         u8         inner_second_cfi[0x1];
 550         u8         inner_second_vid[0xc];
 551
 552         u8         outer_second_vlan_tag[0x1];
 553         u8         inner_second_vlan_tag[0x1];
 554         u8         reserved_2[0xe];
 555         u8         gre_protocol[0x10];
 556
 557         u8         gre_key_h[0x18];
 558         u8         gre_key_l[0x8];
 559
 560         u8         vxlan_vni[0x18];
 561         u8         reserved_3[0x8];
 562
 563         u8         geneve_vni[0x18];
 564         u8         reserved4[0x7];
 565         u8         geneve_oam[0x1];
 566
 567         u8         reserved_5[0xc];
 568         u8         outer_ipv6_flow_label[0x14];
 569
 570         u8         reserved_6[0xc];
 571         u8         inner_ipv6_flow_label[0x14];
 572
 573         u8         reserved_7[0xa];
 574         u8         geneve_opt_len[0x6];
 575         u8         geneve_protocol_type[0x10];
 576
 577         u8         reserved_8[0x8];
 578         u8         bth_dst_qp[0x18];
 579
 580         u8         reserved_9[0xa0];
 581 };
 582
 583 struct mlx5_ifc_cmd_pas_bits {
 584         u8         pa_h[0x20];
 585
 586         u8         pa_l[0x14];
 587         u8         reserved_0[0xc];
 588 };
 589
 590 struct mlx5_ifc_uint64_bits {
 591         u8         hi[0x20];
 592
 593         u8         lo[0x20];
 594 };
 595
 596 struct mlx5_ifc_application_prio_entry_bits {
 597         u8         reserved_0[0x8];
 598         u8         priority[0x3];
 599         u8         reserved_1[0x2];
 600         u8         sel[0x3];
 601         u8         protocol_id[0x10];
 602 };
 603
 604 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 605         u8         reserved_0[0x8];
 606         u8         ring_pi[0x10];
 607         u8         reserved_1[0x8];
 608 };
 609
 610 enum {
 611         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 612         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 613         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 614         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 615         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 616         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 617         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 618         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 619         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 620         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 621 };
 622
 623 struct mlx5_ifc_ads_bits {
 624         u8         fl[0x1];
 625         u8         free_ar[0x1];
 626         u8         reserved_0[0xe];
 627         u8         pkey_index[0x10];
 628
 629         u8         reserved_1[0x8];
 630         u8         grh[0x1];
 631         u8         mlid[0x7];
 632         u8         rlid[0x10];
 633
 634         u8         ack_timeout[0x5];
 635         u8         reserved_2[0x3];
 636         u8         src_addr_index[0x8];
 637         u8         log_rtm[0x4];
 638         u8         stat_rate[0x4];
 639         u8         hop_limit[0x8];
 640
 641         u8         reserved_3[0x4];
 642         u8         tclass[0x8];
 643         u8         flow_label[0x14];
 644
 645         u8         rgid_rip[16][0x8];
 646
 647         u8         reserved_4[0x4];
 648         u8         f_dscp[0x1];
 649         u8         f_ecn[0x1];
 650         u8         reserved_5[0x1];
 651         u8         f_eth_prio[0x1];
 652         u8         ecn[0x2];
 653         u8         dscp[0x6];
 654         u8         udp_sport[0x10];
 655
 656         u8         dei_cfi[0x1];
 657         u8         eth_prio[0x3];
 658         u8         sl[0x4];
 659         u8         port[0x8];
 660         u8         rmac_47_32[0x10];
 661
 662         u8         rmac_31_0[0x20];
 663 };
 664
 665 struct mlx5_ifc_diagnostic_counter_cap_bits {
 666         u8         sync[0x1];
 667         u8         reserved_0[0xf];
 668         u8         counter_id[0x10];
 669 };
 670
 671 struct mlx5_ifc_debug_cap_bits {
 672         u8         reserved_0[0x18];
 673         u8         log_max_samples[0x8];
 674
 675         u8         single[0x1];
 676         u8         repetitive[0x1];
 677         u8         health_mon_rx_activity[0x1];
 678         u8         reserved_1[0x15];
 679         u8         log_min_sample_period[0x8];
 680
 681         u8         reserved_2[0x1c0];
 682
 683         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 684 };
 685
 686 struct mlx5_ifc_qos_cap_bits {
 687         u8         packet_pacing[0x1];
 688         u8         esw_scheduling[0x1];
 689         u8         esw_bw_share[0x1];
 690         u8         esw_rate_limit[0x1];
 691         u8         hll[0x1];
 692         u8         packet_pacing_burst_bound[0x1];
 693         u8         reserved_at_6[0x1a];
 694
 695         u8         reserved_at_20[0x20];
 696
 697         u8         packet_pacing_max_rate[0x20];
 698
 699         u8         packet_pacing_min_rate[0x20];
 700
 701         u8         reserved_at_80[0x10];
 702         u8         packet_pacing_rate_table_size[0x10];
 703
 704         u8         esw_element_type[0x10];
 705         u8         esw_tsar_type[0x10];
 706
 707         u8         reserved_at_c0[0x10];
 708         u8         max_qos_para_vport[0x10];
 709
 710         u8         max_tsar_bw_share[0x20];
 711
 712         u8         reserved_at_100[0x700];
 713 };
 714
 715 struct mlx5_ifc_snapshot_cap_bits {
 716         u8         reserved_0[0x1d];
 717         u8         suspend_qp_uc[0x1];
 718         u8         suspend_qp_ud[0x1];
 719         u8         suspend_qp_rc[0x1];
 720
 721         u8         reserved_1[0x1c];
 722         u8         restore_pd[0x1];
 723         u8         restore_uar[0x1];
 724         u8         restore_mkey[0x1];
 725         u8         restore_qp[0x1];
 726
 727         u8         reserved_2[0x1e];
 728         u8         named_mkey[0x1];
 729         u8         named_qp[0x1];
 730
 731         u8         reserved_3[0x7a0];
 732 };
 733
 734 struct mlx5_ifc_e_switch_cap_bits {
 735         u8         vport_svlan_strip[0x1];
 736         u8         vport_cvlan_strip[0x1];
 737         u8         vport_svlan_insert[0x1];
 738         u8         vport_cvlan_insert_if_not_exist[0x1];
 739         u8         vport_cvlan_insert_overwrite[0x1];
 740
 741         u8         reserved_0[0x19];
 742
 743         u8         nic_vport_node_guid_modify[0x1];
 744         u8         nic_vport_port_guid_modify[0x1];
 745
 746         u8         reserved_1[0x7e0];
 747 };
 748
 749 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 750         u8         reserved_0[0x200];
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 757
 758         u8         reserved_1[0x7800];
 759 };
 760
 761 struct mlx5_ifc_flow_table_nic_cap_bits {
 762         u8         nic_rx_multi_path_tirs[0x1];
 763         u8         nic_rx_multi_path_tirs_fts[0x1];
 764         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 765         u8         reserved_at_3[0x1fd];
 766
 767         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 768
 769         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 770
 771         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 772
 773         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 774
 775         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 776
 777         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 778
 779         u8         reserved_1[0x7200];
 780 };
 781
 782 enum {
 783         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR                   = 0x5031,
 784 };
 785
 786 struct mlx5_ifc_pddr_module_info_bits {
 787         u8         cable_technology[0x8];
 788         u8         cable_breakout[0x8];
 789         u8         ext_ethernet_compliance_code[0x8];
 790         u8         ethernet_compliance_code[0x8];
 791
 792         u8         cable_type[0x4];
 793         u8         cable_vendor[0x4];
 794         u8         cable_length[0x8];
 795         u8         cable_identifier[0x8];
 796         u8         cable_power_class[0x8];
 797
 798         u8         reserved_at_40[0x8];
 799         u8         cable_rx_amp[0x8];
 800         u8         cable_rx_emphasis[0x8];
 801         u8         cable_tx_equalization[0x8];
 802
 803         u8         reserved_at_60[0x8];
 804         u8         cable_attenuation_12g[0x8];
 805         u8         cable_attenuation_7g[0x8];
 806         u8         cable_attenuation_5g[0x8];
 807
 808         u8         reserved_at_80[0x8];
 809         u8         rx_cdr_cap[0x4];
 810         u8         tx_cdr_cap[0x4];
 811         u8         reserved_at_90[0x4];
 812         u8         rx_cdr_state[0x4];
 813         u8         reserved_at_98[0x4];
 814         u8         tx_cdr_state[0x4];
 815
 816         u8         vendor_name[16][0x8];
 817
 818         u8         vendor_pn[16][0x8];
 819
 820         u8         vendor_rev[0x20];
 821
 822         u8         fw_version[0x20];
 823
 824         u8         vendor_sn[16][0x8];
 825
 826         u8         temperature[0x10];
 827         u8         voltage[0x10];
 828
 829         u8         rx_power_lane0[0x10];
 830         u8         rx_power_lane1[0x10];
 831
 832         u8         rx_power_lane2[0x10];
 833         u8         rx_power_lane3[0x10];
 834
 835         u8         reserved_at_2c0[0x40];
 836
 837         u8         tx_power_lane0[0x10];
 838         u8         tx_power_lane1[0x10];
 839
 840         u8         tx_power_lane2[0x10];
 841         u8         tx_power_lane3[0x10];
 842
 843         u8         reserved_at_340[0x40];
 844
 845         u8         tx_bias_lane0[0x10];
 846         u8         tx_bias_lane1[0x10];
 847
 848         u8         tx_bias_lane2[0x10];
 849         u8         tx_bias_lane3[0x10];
 850
 851         u8         reserved_at_3c0[0x40];
 852
 853         u8         temperature_high_th[0x10];
 854         u8         temperature_low_th[0x10];
 855
 856         u8         voltage_high_th[0x10];
 857         u8         voltage_low_th[0x10];
 858
 859         u8         rx_power_high_th[0x10];
 860         u8         rx_power_low_th[0x10];
 861
 862         u8         tx_power_high_th[0x10];
 863         u8         tx_power_low_th[0x10];
 864
 865         u8         tx_bias_high_th[0x10];
 866         u8         tx_bias_low_th[0x10];
 867
 868         u8         reserved_at_4a0[0x10];
 869         u8         wavelength[0x10];
 870
 871         u8         reserved_at_4c0[0x300];
 872 };
 873
 874 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
 875         struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
 876         u8         reserved_at_0[0x7c0];
 877 };
 878
 879 struct mlx5_ifc_pddr_reg_bits {
 880         u8         reserved_at_0[0x8];
 881         u8         local_port[0x8];
 882         u8         pnat[0x2];
 883         u8         reserved_at_12[0xe];
 884
 885         u8         reserved_at_20[0x18];
 886         u8         page_select[0x8];
 887
 888         union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
 889 };
 890
 891 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 892         u8         csum_cap[0x1];
 893         u8         vlan_cap[0x1];
 894         u8         lro_cap[0x1];
 895         u8         lro_psh_flag[0x1];
 896         u8         lro_time_stamp[0x1];
 897         u8         lro_max_msg_sz_mode[0x2];
 898         u8         wqe_vlan_insert[0x1];
 899         u8         self_lb_en_modifiable[0x1];
 900         u8         self_lb_mc[0x1];
 901         u8         self_lb_uc[0x1];
 902         u8         max_lso_cap[0x5];
 903         u8         multi_pkt_send_wqe[0x2];
 904         u8         wqe_inline_mode[0x2];
 905         u8         rss_ind_tbl_cap[0x4];
 906         u8         scatter_fcs[0x1];
 907         u8         reserved_1[0x2];
 908         u8         tunnel_lso_const_out_ip_id[0x1];
 909         u8         tunnel_lro_gre[0x1];
 910         u8         tunnel_lro_vxlan[0x1];
 911         u8         tunnel_statless_gre[0x1];
 912         u8         tunnel_stateless_vxlan[0x1];
 913
 914         u8         swp[0x1];
 915         u8         swp_csum[0x1];
 916         u8         swp_lso[0x1];
 917         u8         reserved_2[0x1b];
 918         u8         max_geneve_opt_len[0x1];
 919         u8         tunnel_stateless_geneve_rx[0x1];
 920
 921         u8         reserved_3[0x10];
 922         u8         lro_min_mss_size[0x10];
 923
 924         u8         reserved_4[0x120];
 925
 926         u8         lro_timer_supported_periods[4][0x20];
 927
 928         u8         reserved_5[0x600];
 929 };
 930
 931 enum {
 932         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 933         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 934         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 935 };
 936
 937 struct mlx5_ifc_roce_cap_bits {
 938         u8         roce_apm[0x1];
 939         u8         rts2rts_primary_eth_prio[0x1];
 940         u8         roce_rx_allow_untagged[0x1];
 941         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 942
 943         u8         reserved_0[0x1c];
 944
 945         u8         reserved_1[0x60];
 946
 947         u8         reserved_2[0xc];
 948         u8         l3_type[0x4];
 949         u8         reserved_3[0x8];
 950         u8         roce_version[0x8];
 951
 952         u8         reserved_4[0x10];
 953         u8         r_roce_dest_udp_port[0x10];
 954
 955         u8         r_roce_max_src_udp_port[0x10];
 956         u8         r_roce_min_src_udp_port[0x10];
 957
 958         u8         reserved_5[0x10];
 959         u8         roce_address_table_size[0x10];
 960
 961         u8         reserved_6[0x700];
 962 };
 963
 964 enum {
 965         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 966         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 967         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 968         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 969         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 970         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 971         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 972         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 973         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 974 };
 975
 976 enum {
 977         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 978         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 979         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 980         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 981         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 982         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 983         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 984         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 985         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 986 };
 987
 988 struct mlx5_ifc_atomic_caps_bits {
 989         u8         reserved_0[0x40];
 990
 991         u8         atomic_req_8B_endianess_mode[0x2];
 992         u8         reserved_1[0x4];
 993         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 994
 995         u8         reserved_2[0x19];
 996
 997         u8         reserved_3[0x20];
 998
 999         u8         reserved_4[0x10];
1000         u8         atomic_operations[0x10];
1001
1002         u8         reserved_5[0x10];
1003         u8         atomic_size_qp[0x10];
1004
1005         u8         reserved_6[0x10];
1006         u8         atomic_size_dc[0x10];
1007
1008         u8         reserved_7[0x720];
1009 };
1010
1011 struct mlx5_ifc_odp_cap_bits {
1012         u8         reserved_0[0x40];
1013
1014         u8         sig[0x1];
1015         u8         reserved_1[0x1f];
1016
1017         u8         reserved_2[0x20];
1018
1019         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1020
1021         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1022
1023         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1024
1025         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1026
1027         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1028
1029         u8         reserved_3[0x6e0];
1030 };
1031
1032 enum {
1033         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1034         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1035         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1036         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1037         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1038 };
1039
1040 enum {
1041         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1042         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1043         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1044         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1045         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1046         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1047 };
1048
1049 enum {
1050         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1051         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1052 };
1053
1054 enum {
1055         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1056         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1057         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1058 };
1059
1060 struct mlx5_ifc_cmd_hca_cap_bits {
1061         u8         reserved_0[0x80];
1062
1063         u8         log_max_srq_sz[0x8];
1064         u8         log_max_qp_sz[0x8];
1065         u8         reserved_1[0xb];
1066         u8         log_max_qp[0x5];
1067
1068         u8         reserved_2[0xb];
1069         u8         log_max_srq[0x5];
1070         u8         reserved_3[0x10];
1071
1072         u8         reserved_4[0x8];
1073         u8         log_max_cq_sz[0x8];
1074         u8         reserved_5[0xb];
1075         u8         log_max_cq[0x5];
1076
1077         u8         log_max_eq_sz[0x8];
1078         u8         relaxed_ordering_write[1];
1079         u8         reserved_6[0x1];
1080         u8         log_max_mkey[0x6];
1081         u8         reserved_7[0xb];
1082         u8         fast_teardown[0x1];
1083         u8         log_max_eq[0x4];
1084
1085         u8         max_indirection[0x8];
1086         u8         reserved_8[0x1];
1087         u8         log_max_mrw_sz[0x7];
1088         u8         force_teardown[0x1];
1089         u8         reserved_9[0x1];
1090         u8         log_max_bsf_list_size[0x6];
1091         u8         reserved_10[0x2];
1092         u8         log_max_klm_list_size[0x6];
1093
1094         u8         reserved_11[0xa];
1095         u8         log_max_ra_req_dc[0x6];
1096         u8         reserved_12[0xa];
1097         u8         log_max_ra_res_dc[0x6];
1098
1099         u8         reserved_13[0xa];
1100         u8         log_max_ra_req_qp[0x6];
1101         u8         reserved_14[0xa];
1102         u8         log_max_ra_res_qp[0x6];
1103
1104         u8         pad_cap[0x1];
1105         u8         cc_query_allowed[0x1];
1106         u8         cc_modify_allowed[0x1];
1107         u8         start_pad[0x1];
1108         u8         cache_line_128byte[0x1];
1109         u8         reserved_at_165[0xa];
1110         u8         qcam_reg[0x1];
1111         u8         gid_table_size[0x10];
1112
1113         u8         out_of_seq_cnt[0x1];
1114         u8         vport_counters[0x1];
1115         u8         retransmission_q_counters[0x1];
1116         u8         debug[0x1];
1117         u8         modify_rq_counters_set_id[0x1];
1118         u8         rq_delay_drop[0x1];
1119         u8         max_qp_cnt[0xa];
1120         u8         pkey_table_size[0x10];
1121
1122         u8         vport_group_manager[0x1];
1123         u8         vhca_group_manager[0x1];
1124         u8         ib_virt[0x1];
1125         u8         eth_virt[0x1];
1126         u8         reserved_17[0x1];
1127         u8         ets[0x1];
1128         u8         nic_flow_table[0x1];
1129         u8         eswitch_flow_table[0x1];
1130         u8         reserved_18[0x1];
1131         u8         mcam_reg[0x1];
1132         u8         pcam_reg[0x1];
1133         u8         local_ca_ack_delay[0x5];
1134         u8         port_module_event[0x1];
1135         u8         reserved_19[0x5];
1136         u8         port_type[0x2];
1137         u8         num_ports[0x8];
1138
1139         u8         snapshot[0x1];
1140         u8         reserved_20[0x2];
1141         u8         log_max_msg[0x5];
1142         u8         reserved_21[0x4];
1143         u8         max_tc[0x4];
1144         u8         temp_warn_event[0x1];
1145         u8         dcbx[0x1];
1146         u8         general_notification_event[0x1];
1147         u8         reserved_at_1d3[0x2];
1148         u8         fpga[0x1];
1149         u8         rol_s[0x1];
1150         u8         rol_g[0x1];
1151         u8         reserved_23[0x1];
1152         u8         wol_s[0x1];
1153         u8         wol_g[0x1];
1154         u8         wol_a[0x1];
1155         u8         wol_b[0x1];
1156         u8         wol_m[0x1];
1157         u8         wol_u[0x1];
1158         u8         wol_p[0x1];
1159
1160         u8         stat_rate_support[0x10];
1161         u8         reserved_24[0xc];
1162         u8         cqe_version[0x4];
1163
1164         u8         compact_address_vector[0x1];
1165         u8         striding_rq[0x1];
1166         u8         reserved_25[0x1];
1167         u8         ipoib_enhanced_offloads[0x1];
1168         u8         ipoib_ipoib_offloads[0x1];
1169         u8         reserved_26[0x8];
1170         u8         dc_connect_qp[0x1];
1171         u8         dc_cnak_trace[0x1];
1172         u8         drain_sigerr[0x1];
1173         u8         cmdif_checksum[0x2];
1174         u8         sigerr_cqe[0x1];
1175         u8         reserved_27[0x1];
1176         u8         wq_signature[0x1];
1177         u8         sctr_data_cqe[0x1];
1178         u8         reserved_28[0x1];
1179         u8         sho[0x1];
1180         u8         tph[0x1];
1181         u8         rf[0x1];
1182         u8         dct[0x1];
1183         u8         qos[0x1];
1184         u8         eth_net_offloads[0x1];
1185         u8         roce[0x1];
1186         u8         atomic[0x1];
1187         u8         reserved_30[0x1];
1188
1189         u8         cq_oi[0x1];
1190         u8         cq_resize[0x1];
1191         u8         cq_moderation[0x1];
1192         u8         cq_period_mode_modify[0x1];
1193         u8         cq_invalidate[0x1];
1194         u8         reserved_at_225[0x1];
1195         u8         cq_eq_remap[0x1];
1196         u8         pg[0x1];
1197         u8         block_lb_mc[0x1];
1198         u8         exponential_backoff[0x1];
1199         u8         scqe_break_moderation[0x1];
1200         u8         cq_period_start_from_cqe[0x1];
1201         u8         cd[0x1];
1202         u8         atm[0x1];
1203         u8         apm[0x1];
1204         u8         imaicl[0x1];
1205         u8         reserved_32[0x6];
1206         u8         qkv[0x1];
1207         u8         pkv[0x1];
1208         u8         set_deth_sqpn[0x1];
1209         u8         reserved_33[0x3];
1210         u8         xrc[0x1];
1211         u8         ud[0x1];
1212         u8         uc[0x1];
1213         u8         rc[0x1];
1214
1215         u8         reserved_34[0xa];
1216         u8         uar_sz[0x6];
1217         u8         reserved_35[0x8];
1218         u8         log_pg_sz[0x8];
1219
1220         u8         bf[0x1];
1221         u8         driver_version[0x1];
1222         u8         pad_tx_eth_packet[0x1];
1223         u8         reserved_36[0x8];
1224         u8         log_bf_reg_size[0x5];
1225         u8         reserved_37[0x10];
1226
1227         u8         num_of_diagnostic_counters[0x10];
1228         u8         max_wqe_sz_sq[0x10];
1229
1230         u8         reserved_38[0x10];
1231         u8         max_wqe_sz_rq[0x10];
1232
1233         u8         reserved_39[0x10];
1234         u8         max_wqe_sz_sq_dc[0x10];
1235
1236         u8         reserved_40[0x7];
1237         u8         max_qp_mcg[0x19];
1238
1239         u8         reserved_41[0x18];
1240         u8         log_max_mcg[0x8];
1241
1242         u8         reserved_42[0x3];
1243         u8         log_max_transport_domain[0x5];
1244         u8         reserved_43[0x3];
1245         u8         log_max_pd[0x5];
1246         u8         reserved_44[0xb];
1247         u8         log_max_xrcd[0x5];
1248
1249         u8         nic_receive_steering_discard[0x1];
1250         u8         reserved_45[0x7];
1251         u8         log_max_flow_counter_bulk[0x8];
1252         u8         max_flow_counter[0x10];
1253
1254         u8         reserved_46[0x3];
1255         u8         log_max_rq[0x5];
1256         u8         reserved_47[0x3];
1257         u8         log_max_sq[0x5];
1258         u8         reserved_48[0x3];
1259         u8         log_max_tir[0x5];
1260         u8         reserved_49[0x3];
1261         u8         log_max_tis[0x5];
1262
1263         u8         basic_cyclic_rcv_wqe[0x1];
1264         u8         reserved_50[0x2];
1265         u8         log_max_rmp[0x5];
1266         u8         reserved_51[0x3];
1267         u8         log_max_rqt[0x5];
1268         u8         reserved_52[0x3];
1269         u8         log_max_rqt_size[0x5];
1270         u8         reserved_53[0x3];
1271         u8         log_max_tis_per_sq[0x5];
1272
1273         u8         reserved_54[0x3];
1274         u8         log_max_stride_sz_rq[0x5];
1275         u8         reserved_55[0x3];
1276         u8         log_min_stride_sz_rq[0x5];
1277         u8         reserved_56[0x3];
1278         u8         log_max_stride_sz_sq[0x5];
1279         u8         reserved_57[0x3];
1280         u8         log_min_stride_sz_sq[0x5];
1281
1282         u8         reserved_58[0x1b];
1283         u8         log_max_wq_sz[0x5];
1284
1285         u8         nic_vport_change_event[0x1];
1286         u8         disable_local_lb[0x1];
1287         u8         reserved_59[0x9];
1288         u8         log_max_vlan_list[0x5];
1289         u8         reserved_60[0x3];
1290         u8         log_max_current_mc_list[0x5];
1291         u8         reserved_61[0x3];
1292         u8         log_max_current_uc_list[0x5];
1293
1294         u8         general_obj_types[0x40];
1295
1296         u8         reserved_at_440[0x8];
1297         u8         create_qp_start_hint[0x18];
1298
1299         u8         tls[0x1];
1300         u8         reserved_at_461[0x2];
1301         u8         log_max_uctx[0x5];
1302         u8         reserved_at_468[0x3];
1303         u8         log_max_umem[0x5];
1304         u8         max_num_eqs[0x10];
1305
1306         u8         reserved_63[0x3];
1307         u8         log_max_l2_table[0x5];
1308         u8         reserved_64[0x8];
1309         u8         log_uar_page_sz[0x10];
1310
1311         u8         reserved_65[0x20];
1312
1313         u8         device_frequency_mhz[0x20];
1314
1315         u8         device_frequency_khz[0x20];
1316
1317         u8         reserved_66[0x80];
1318
1319         u8         log_max_atomic_size_qp[0x8];
1320         u8         reserved_67[0x10];
1321         u8         log_max_atomic_size_dc[0x8];
1322
1323         u8         reserved_at_5a0[0x13];
1324         u8         log_max_dek[0x5];
1325         u8         reserved_at_5b8[0x4];
1326         u8         mini_cqe_resp_stride_index[0x1];
1327         u8         cqe_128_always[0x1];
1328         u8         cqe_compression_128b[0x1];
1329
1330         u8         cqe_compression[0x1];
1331
1332         u8         cqe_compression_timeout[0x10];
1333         u8         cqe_compression_max_num[0x10];
1334
1335         u8         reserved_69[0x220];
1336 };
1337
1338 enum mlx5_flow_destination_type {
1339         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1340         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1341         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1342 };
1343
1344 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1345         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1346         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1347         u8         reserved_0[0x40];
1348 };
1349
1350 struct mlx5_ifc_fte_match_param_bits {
1351         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1352
1353         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1354
1355         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1356
1357         u8         reserved_0[0xa00];
1358 };
1359
1360 enum {
1361         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1362         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1363         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1364         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1365         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1366 };
1367
1368 struct mlx5_ifc_rx_hash_field_select_bits {
1369         u8         l3_prot_type[0x1];
1370         u8         l4_prot_type[0x1];
1371         u8         selected_fields[0x1e];
1372 };
1373
1374 struct mlx5_ifc_tls_capabilities_bits {
1375         u8         tls_1_2_aes_gcm_128[0x1];
1376         u8         tls_1_3_aes_gcm_128[0x1];
1377         u8         tls_1_2_aes_gcm_256[0x1];
1378         u8         tls_1_3_aes_gcm_256[0x1];
1379         u8         reserved_at_4[0x1c];
1380
1381         u8         reserved_at_20[0x7e0];
1382 };
1383
1384 enum {
1385         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1386         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1387         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1388         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1389 };
1390
1391 enum rq_type {
1392         RQ_TYPE_NONE,
1393         RQ_TYPE_STRIDE,
1394 };
1395
1396 enum {
1397         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1398         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1399 };
1400
1401 struct mlx5_ifc_wq_bits {
1402         u8         wq_type[0x4];
1403         u8         wq_signature[0x1];
1404         u8         end_padding_mode[0x2];
1405         u8         cd_slave[0x1];
1406         u8         reserved_0[0x18];
1407
1408         u8         hds_skip_first_sge[0x1];
1409         u8         log2_hds_buf_size[0x3];
1410         u8         reserved_1[0x7];
1411         u8         page_offset[0x5];
1412         u8         lwm[0x10];
1413
1414         u8         reserved_2[0x8];
1415         u8         pd[0x18];
1416
1417         u8         reserved_3[0x8];
1418         u8         uar_page[0x18];
1419
1420         u8         dbr_addr[0x40];
1421
1422         u8         hw_counter[0x20];
1423
1424         u8         sw_counter[0x20];
1425
1426         u8         reserved_4[0xc];
1427         u8         log_wq_stride[0x4];
1428         u8         reserved_5[0x3];
1429         u8         log_wq_pg_sz[0x5];
1430         u8         reserved_6[0x3];
1431         u8         log_wq_sz[0x5];
1432
1433         u8         reserved_7[0x15];
1434         u8         single_wqe_log_num_of_strides[0x3];
1435         u8         two_byte_shift_en[0x1];
1436         u8         reserved_8[0x4];
1437         u8         single_stride_log_num_of_bytes[0x3];
1438
1439         u8         reserved_9[0x4c0];
1440
1441         struct mlx5_ifc_cmd_pas_bits pas[0];
1442 };
1443
1444 struct mlx5_ifc_rq_num_bits {
1445         u8         reserved_0[0x8];
1446         u8         rq_num[0x18];
1447 };
1448
1449 struct mlx5_ifc_mac_address_layout_bits {
1450         u8         reserved_0[0x10];
1451         u8         mac_addr_47_32[0x10];
1452
1453         u8         mac_addr_31_0[0x20];
1454 };
1455
1456 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1457         u8         reserved_0[0xa0];
1458
1459         u8         min_time_between_cnps[0x20];
1460
1461         u8         reserved_1[0x12];
1462         u8         cnp_dscp[0x6];
1463         u8         reserved_2[0x4];
1464         u8         cnp_prio_mode[0x1];
1465         u8         cnp_802p_prio[0x3];
1466
1467         u8         reserved_3[0x720];
1468 };
1469
1470 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1471         u8         reserved_0[0x60];
1472
1473         u8         reserved_1[0x4];
1474         u8         clamp_tgt_rate[0x1];
1475         u8         reserved_2[0x3];
1476         u8         clamp_tgt_rate_after_time_inc[0x1];
1477         u8         reserved_3[0x17];
1478
1479         u8         reserved_4[0x20];
1480
1481         u8         rpg_time_reset[0x20];
1482
1483         u8         rpg_byte_reset[0x20];
1484
1485         u8         rpg_threshold[0x20];
1486
1487         u8         rpg_max_rate[0x20];
1488
1489         u8         rpg_ai_rate[0x20];
1490
1491         u8         rpg_hai_rate[0x20];
1492
1493         u8         rpg_gd[0x20];
1494
1495         u8         rpg_min_dec_fac[0x20];
1496
1497         u8         rpg_min_rate[0x20];
1498
1499         u8         reserved_5[0xe0];
1500
1501         u8         rate_to_set_on_first_cnp[0x20];
1502
1503         u8         dce_tcp_g[0x20];
1504
1505         u8         dce_tcp_rtt[0x20];
1506
1507         u8         rate_reduce_monitor_period[0x20];
1508
1509         u8         reserved_6[0x20];
1510
1511         u8         initial_alpha_value[0x20];
1512
1513         u8         reserved_7[0x4a0];
1514 };
1515
1516 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1517         u8         reserved_0[0x80];
1518
1519         u8         rppp_max_rps[0x20];
1520
1521         u8         rpg_time_reset[0x20];
1522
1523         u8         rpg_byte_reset[0x20];
1524
1525         u8         rpg_threshold[0x20];
1526
1527         u8         rpg_max_rate[0x20];
1528
1529         u8         rpg_ai_rate[0x20];
1530
1531         u8         rpg_hai_rate[0x20];
1532
1533         u8         rpg_gd[0x20];
1534
1535         u8         rpg_min_dec_fac[0x20];
1536
1537         u8         rpg_min_rate[0x20];
1538
1539         u8         reserved_1[0x640];
1540 };
1541
1542 enum {
1543         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1544         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1545         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1546 };
1547
1548 struct mlx5_ifc_resize_field_select_bits {
1549         u8         resize_field_select[0x20];
1550 };
1551
1552 enum {
1553         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1554         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1555         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1556         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1557         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1558         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1559 };
1560
1561 struct mlx5_ifc_modify_field_select_bits {
1562         u8         modify_field_select[0x20];
1563 };
1564
1565 struct mlx5_ifc_field_select_r_roce_np_bits {
1566         u8         field_select_r_roce_np[0x20];
1567 };
1568
1569 enum {
1570         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1571         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1572         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1573         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1574         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1575         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1576         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1577         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1578         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1579         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1580         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1581         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1582         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1583         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1584         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1585 };
1586
1587 struct mlx5_ifc_field_select_r_roce_rp_bits {
1588         u8         field_select_r_roce_rp[0x20];
1589 };
1590
1591 enum {
1592         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1593         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1594         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1595         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1596         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1597         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1598         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1599         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1600         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1601         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1602 };
1603
1604 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1605         u8         field_select_8021qaurp[0x20];
1606 };
1607
1608 struct mlx5_ifc_pptb_reg_bits {
1609         u8         reserved_at_0[0x2];
1610         u8         mm[0x2];
1611         u8         reserved_at_4[0x4];
1612         u8         local_port[0x8];
1613         u8         reserved_at_10[0x6];
1614         u8         cm[0x1];
1615         u8         um[0x1];
1616         u8         pm[0x8];
1617
1618         u8         prio_x_buff[0x20];
1619
1620         u8         pm_msb[0x8];
1621         u8         reserved_at_48[0x10];
1622         u8         ctrl_buff[0x4];
1623         u8         untagged_buff[0x4];
1624 };
1625
1626 struct mlx5_ifc_dcbx_app_reg_bits {
1627         u8         reserved_0[0x8];
1628         u8         port_number[0x8];
1629         u8         reserved_1[0x10];
1630
1631         u8         reserved_2[0x1a];
1632         u8         num_app_prio[0x6];
1633
1634         u8         reserved_3[0x40];
1635
1636         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1637 };
1638
1639 struct mlx5_ifc_dcbx_param_reg_bits {
1640         u8         dcbx_cee_cap[0x1];
1641         u8         dcbx_ieee_cap[0x1];
1642         u8         dcbx_standby_cap[0x1];
1643         u8         reserved_0[0x5];
1644         u8         port_number[0x8];
1645         u8         reserved_1[0xa];
1646         u8         max_application_table_size[0x6];
1647
1648         u8         reserved_2[0x15];
1649         u8         version_oper[0x3];
1650         u8         reserved_3[0x5];
1651         u8         version_admin[0x3];
1652
1653         u8         willing_admin[0x1];
1654         u8         reserved_4[0x3];
1655         u8         pfc_cap_oper[0x4];
1656         u8         reserved_5[0x4];
1657         u8         pfc_cap_admin[0x4];
1658         u8         reserved_6[0x4];
1659         u8         num_of_tc_oper[0x4];
1660         u8         reserved_7[0x4];
1661         u8         num_of_tc_admin[0x4];
1662
1663         u8         remote_willing[0x1];
1664         u8         reserved_8[0x3];
1665         u8         remote_pfc_cap[0x4];
1666         u8         reserved_9[0x14];
1667         u8         remote_num_of_tc[0x4];
1668
1669         u8         reserved_10[0x18];
1670         u8         error[0x8];
1671
1672         u8         reserved_11[0x160];
1673 };
1674
1675 struct mlx5_ifc_qhll_bits {
1676         u8         reserved_at_0[0x8];
1677         u8         local_port[0x8];
1678         u8         reserved_at_10[0x10];
1679
1680         u8         reserved_at_20[0x1b];
1681         u8         hll_time[0x5];
1682
1683         u8         stall_en[0x1];
1684         u8         reserved_at_41[0x1c];
1685         u8         stall_cnt[0x3];
1686 };
1687
1688 struct mlx5_ifc_qetcr_reg_bits {
1689         u8         operation_type[0x2];
1690         u8         cap_local_admin[0x1];
1691         u8         cap_remote_admin[0x1];
1692         u8         reserved_0[0x4];
1693         u8         port_number[0x8];
1694         u8         reserved_1[0x10];
1695
1696         u8         reserved_2[0x20];
1697
1698         u8         tc[8][0x40];
1699
1700         u8         global_configuration[0x40];
1701 };
1702
1703 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1704         u8         queue_address_63_32[0x20];
1705
1706         u8         queue_address_31_12[0x14];
1707         u8         reserved_0[0x6];
1708         u8         log_size[0x6];
1709
1710         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1711
1712         u8         reserved_1[0x8];
1713         u8         queue_number[0x18];
1714
1715         u8         q_key[0x20];
1716
1717         u8         reserved_2[0x10];
1718         u8         pkey_index[0x10];
1719
1720         u8         reserved_3[0x40];
1721 };
1722
1723 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1724         u8         reserved_0[0x8];
1725         u8         cq_ci[0x10];
1726         u8         reserved_1[0x8];
1727 };
1728
1729 enum {
1730         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1731         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1732 };
1733
1734 enum {
1735         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1736         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1737         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1738         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1739 };
1740
1741 struct mlx5_ifc_nodnic_event_word_bits {
1742         u8         driver_reset_needed[0x1];
1743         u8         port_management_change_event[0x1];
1744         u8         reserved_0[0x19];
1745         u8         link_type[0x1];
1746         u8         port_state[0x4];
1747 };
1748
1749 struct mlx5_ifc_nic_vport_change_event_bits {
1750         u8         reserved_0[0x10];
1751         u8         vport_num[0x10];
1752
1753         u8         reserved_1[0xc0];
1754 };
1755
1756 struct mlx5_ifc_pages_req_event_bits {
1757         u8         reserved_0[0x10];
1758         u8         function_id[0x10];
1759
1760         u8         num_pages[0x20];
1761
1762         u8         reserved_1[0xa0];
1763 };
1764
1765 struct mlx5_ifc_cmd_inter_comp_event_bits {
1766         u8         command_completion_vector[0x20];
1767
1768         u8         reserved_0[0xc0];
1769 };
1770
1771 struct mlx5_ifc_stall_vl_event_bits {
1772         u8         reserved_0[0x18];
1773         u8         port_num[0x1];
1774         u8         reserved_1[0x3];
1775         u8         vl[0x4];
1776
1777         u8         reserved_2[0xa0];
1778 };
1779
1780 struct mlx5_ifc_db_bf_congestion_event_bits {
1781         u8         event_subtype[0x8];
1782         u8         reserved_0[0x8];
1783         u8         congestion_level[0x8];
1784         u8         reserved_1[0x8];
1785
1786         u8         reserved_2[0xa0];
1787 };
1788
1789 struct mlx5_ifc_gpio_event_bits {
1790         u8         reserved_0[0x60];
1791
1792         u8         gpio_event_hi[0x20];
1793
1794         u8         gpio_event_lo[0x20];
1795
1796         u8         reserved_1[0x40];
1797 };
1798
1799 struct mlx5_ifc_port_state_change_event_bits {
1800         u8         reserved_0[0x40];
1801
1802         u8         port_num[0x4];
1803         u8         reserved_1[0x1c];
1804
1805         u8         reserved_2[0x80];
1806 };
1807
1808 struct mlx5_ifc_dropped_packet_logged_bits {
1809         u8         reserved_0[0xe0];
1810 };
1811
1812 enum {
1813         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1814         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1815 };
1816
1817 struct mlx5_ifc_cq_error_bits {
1818         u8         reserved_0[0x8];
1819         u8         cqn[0x18];
1820
1821         u8         reserved_1[0x20];
1822
1823         u8         reserved_2[0x18];
1824         u8         syndrome[0x8];
1825
1826         u8         reserved_3[0x80];
1827 };
1828
1829 struct mlx5_ifc_rdma_page_fault_event_bits {
1830         u8         bytes_commited[0x20];
1831
1832         u8         r_key[0x20];
1833
1834         u8         reserved_0[0x10];
1835         u8         packet_len[0x10];
1836
1837         u8         rdma_op_len[0x20];
1838
1839         u8         rdma_va[0x40];
1840
1841         u8         reserved_1[0x5];
1842         u8         rdma[0x1];
1843         u8         write[0x1];
1844         u8         requestor[0x1];
1845         u8         qp_number[0x18];
1846 };
1847
1848 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1849         u8         bytes_committed[0x20];
1850
1851         u8         reserved_0[0x10];
1852         u8         wqe_index[0x10];
1853
1854         u8         reserved_1[0x10];
1855         u8         len[0x10];
1856
1857         u8         reserved_2[0x60];
1858
1859         u8         reserved_3[0x5];
1860         u8         rdma[0x1];
1861         u8         write_read[0x1];
1862         u8         requestor[0x1];
1863         u8         qpn[0x18];
1864 };
1865
1866 enum {
1867         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1868         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1869         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1870 };
1871
1872 struct mlx5_ifc_qp_events_bits {
1873         u8         reserved_0[0xa0];
1874
1875         u8         type[0x8];
1876         u8         reserved_1[0x18];
1877
1878         u8         reserved_2[0x8];
1879         u8         qpn_rqn_sqn[0x18];
1880 };
1881
1882 struct mlx5_ifc_dct_events_bits {
1883         u8         reserved_0[0xc0];
1884
1885         u8         reserved_1[0x8];
1886         u8         dct_number[0x18];
1887 };
1888
1889 struct mlx5_ifc_comp_event_bits {
1890         u8         reserved_0[0xc0];
1891
1892         u8         reserved_1[0x8];
1893         u8         cq_number[0x18];
1894 };
1895
1896 struct mlx5_ifc_fw_version_bits {
1897         u8         major[0x10];
1898         u8         reserved_0[0x10];
1899
1900         u8         minor[0x10];
1901         u8         subminor[0x10];
1902
1903         u8         second[0x8];
1904         u8         minute[0x8];
1905         u8         hour[0x8];
1906         u8         reserved_1[0x8];
1907
1908         u8         year[0x10];
1909         u8         month[0x8];
1910         u8         day[0x8];
1911 };
1912
1913 enum {
1914         MLX5_QPC_STATE_RST        = 0x0,
1915         MLX5_QPC_STATE_INIT       = 0x1,
1916         MLX5_QPC_STATE_RTR        = 0x2,
1917         MLX5_QPC_STATE_RTS        = 0x3,
1918         MLX5_QPC_STATE_SQER       = 0x4,
1919         MLX5_QPC_STATE_SQD        = 0x5,
1920         MLX5_QPC_STATE_ERR        = 0x6,
1921         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1922 };
1923
1924 enum {
1925         MLX5_QPC_ST_RC            = 0x0,
1926         MLX5_QPC_ST_UC            = 0x1,
1927         MLX5_QPC_ST_UD            = 0x2,
1928         MLX5_QPC_ST_XRC           = 0x3,
1929         MLX5_QPC_ST_DCI           = 0x5,
1930         MLX5_QPC_ST_QP0           = 0x7,
1931         MLX5_QPC_ST_QP1           = 0x8,
1932         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1933         MLX5_QPC_ST_REG_UMR       = 0xc,
1934 };
1935
1936 enum {
1937         MLX5_QP_PM_ARMED            = 0x0,
1938         MLX5_QP_PM_REARM            = 0x1,
1939         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1940         MLX5_QP_PM_MIGRATED         = 0x3,
1941 };
1942
1943 enum {
1944         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1945         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1946 };
1947
1948 enum {
1949         MLX5_QPC_MTU_256_BYTES        = 0x1,
1950         MLX5_QPC_MTU_512_BYTES        = 0x2,
1951         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1952         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1953         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1954         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1955 };
1956
1957 enum {
1958         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1959         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1960         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1961         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1962         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1963         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1964         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1965         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1966 };
1967
1968 enum {
1969         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1970         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1971         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1972 };
1973
1974 enum {
1975         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1976         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1977         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1978 };
1979
1980 struct mlx5_ifc_qpc_bits {
1981         u8         state[0x4];
1982         u8         lag_tx_port_affinity[0x4];
1983         u8         st[0x8];
1984         u8         reserved_1[0x3];
1985         u8         pm_state[0x2];
1986         u8         reserved_2[0x7];
1987         u8         end_padding_mode[0x2];
1988         u8         reserved_3[0x2];
1989
1990         u8         wq_signature[0x1];
1991         u8         block_lb_mc[0x1];
1992         u8         atomic_like_write_en[0x1];
1993         u8         latency_sensitive[0x1];
1994         u8         reserved_4[0x1];
1995         u8         drain_sigerr[0x1];
1996         u8         reserved_5[0x2];
1997         u8         pd[0x18];
1998
1999         u8         mtu[0x3];
2000         u8         log_msg_max[0x5];
2001         u8         reserved_6[0x1];
2002         u8         log_rq_size[0x4];
2003         u8         log_rq_stride[0x3];
2004         u8         no_sq[0x1];
2005         u8         log_sq_size[0x4];
2006         u8         reserved_7[0x6];
2007         u8         rlky[0x1];
2008         u8         ulp_stateless_offload_mode[0x4];
2009
2010         u8         counter_set_id[0x8];
2011         u8         uar_page[0x18];
2012
2013         u8         reserved_8[0x8];
2014         u8         user_index[0x18];
2015
2016         u8         reserved_9[0x3];
2017         u8         log_page_size[0x5];
2018         u8         remote_qpn[0x18];
2019
2020         struct mlx5_ifc_ads_bits primary_address_path;
2021
2022         struct mlx5_ifc_ads_bits secondary_address_path;
2023
2024         u8         log_ack_req_freq[0x4];
2025         u8         reserved_10[0x4];
2026         u8         log_sra_max[0x3];
2027         u8         reserved_11[0x2];
2028         u8         retry_count[0x3];
2029         u8         rnr_retry[0x3];
2030         u8         reserved_12[0x1];
2031         u8         fre[0x1];
2032         u8         cur_rnr_retry[0x3];
2033         u8         cur_retry_count[0x3];
2034         u8         reserved_13[0x5];
2035
2036         u8         reserved_14[0x20];
2037
2038         u8         reserved_15[0x8];
2039         u8         next_send_psn[0x18];
2040
2041         u8         reserved_16[0x8];
2042         u8         cqn_snd[0x18];
2043
2044         u8         reserved_at_400[0x8];
2045
2046         u8         deth_sqpn[0x18];
2047         u8         reserved_17[0x20];
2048
2049         u8         reserved_18[0x8];
2050         u8         last_acked_psn[0x18];
2051
2052         u8         reserved_19[0x8];
2053         u8         ssn[0x18];
2054
2055         u8         reserved_20[0x8];
2056         u8         log_rra_max[0x3];
2057         u8         reserved_21[0x1];
2058         u8         atomic_mode[0x4];
2059         u8         rre[0x1];
2060         u8         rwe[0x1];
2061         u8         rae[0x1];
2062         u8         reserved_22[0x1];
2063         u8         page_offset[0x6];
2064         u8         reserved_23[0x3];
2065         u8         cd_slave_receive[0x1];
2066         u8         cd_slave_send[0x1];
2067         u8         cd_master[0x1];
2068
2069         u8         reserved_24[0x3];
2070         u8         min_rnr_nak[0x5];
2071         u8         next_rcv_psn[0x18];
2072
2073         u8         reserved_25[0x8];
2074         u8         xrcd[0x18];
2075
2076         u8         reserved_26[0x8];
2077         u8         cqn_rcv[0x18];
2078
2079         u8         dbr_addr[0x40];
2080
2081         u8         q_key[0x20];
2082
2083         u8         reserved_27[0x5];
2084         u8         rq_type[0x3];
2085         u8         srqn_rmpn[0x18];
2086
2087         u8         reserved_28[0x8];
2088         u8         rmsn[0x18];
2089
2090         u8         hw_sq_wqebb_counter[0x10];
2091         u8         sw_sq_wqebb_counter[0x10];
2092
2093         u8         hw_rq_counter[0x20];
2094
2095         u8         sw_rq_counter[0x20];
2096
2097         u8         reserved_29[0x20];
2098
2099         u8         reserved_30[0xf];
2100         u8         cgs[0x1];
2101         u8         cs_req[0x8];
2102         u8         cs_res[0x8];
2103
2104         u8         dc_access_key[0x40];
2105
2106         u8         rdma_active[0x1];
2107         u8         comm_est[0x1];
2108         u8         suspended[0x1];
2109         u8         reserved_31[0x5];
2110         u8         send_msg_psn[0x18];
2111
2112         u8         reserved_32[0x8];
2113         u8         rcv_msg_psn[0x18];
2114
2115         u8         rdma_va[0x40];
2116
2117         u8         rdma_key[0x20];
2118
2119         u8         reserved_33[0x20];
2120 };
2121
2122 struct mlx5_ifc_roce_addr_layout_bits {
2123         u8         source_l3_address[16][0x8];
2124
2125         u8         reserved_0[0x3];
2126         u8         vlan_valid[0x1];
2127         u8         vlan_id[0xc];
2128         u8         source_mac_47_32[0x10];
2129
2130         u8         source_mac_31_0[0x20];
2131
2132         u8         reserved_1[0x14];
2133         u8         roce_l3_type[0x4];
2134         u8         roce_version[0x8];
2135
2136         u8         reserved_2[0x20];
2137 };
2138
2139 struct mlx5_ifc_rdbc_bits {
2140         u8         reserved_0[0x1c];
2141         u8         type[0x4];
2142
2143         u8         reserved_1[0x20];
2144
2145         u8         reserved_2[0x8];
2146         u8         psn[0x18];
2147
2148         u8         rkey[0x20];
2149
2150         u8         address[0x40];
2151
2152         u8         byte_count[0x20];
2153
2154         u8         reserved_3[0x20];
2155
2156         u8         atomic_resp[32][0x8];
2157 };
2158
2159 enum {
2160         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2161         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2162         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2163         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2164 };
2165
2166 struct mlx5_ifc_flow_context_bits {
2167         u8         reserved_0[0x20];
2168
2169         u8         group_id[0x20];
2170
2171         u8         reserved_1[0x8];
2172         u8         flow_tag[0x18];
2173
2174         u8         reserved_2[0x10];
2175         u8         action[0x10];
2176
2177         u8         reserved_3[0x8];
2178         u8         destination_list_size[0x18];
2179
2180         u8         reserved_4[0x8];
2181         u8         flow_counter_list_size[0x18];
2182
2183         u8         reserved_5[0x140];
2184
2185         struct mlx5_ifc_fte_match_param_bits match_value;
2186
2187         u8         reserved_6[0x600];
2188
2189         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2190 };
2191
2192 enum {
2193         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2194         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2195 };
2196
2197 struct mlx5_ifc_xrc_srqc_bits {
2198         u8         state[0x4];
2199         u8         log_xrc_srq_size[0x4];
2200         u8         reserved_0[0x18];
2201
2202         u8         wq_signature[0x1];
2203         u8         cont_srq[0x1];
2204         u8         reserved_1[0x1];
2205         u8         rlky[0x1];
2206         u8         basic_cyclic_rcv_wqe[0x1];
2207         u8         log_rq_stride[0x3];
2208         u8         xrcd[0x18];
2209
2210         u8         page_offset[0x6];
2211         u8         reserved_2[0x2];
2212         u8         cqn[0x18];
2213
2214         u8         reserved_3[0x20];
2215
2216         u8         reserved_4[0x2];
2217         u8         log_page_size[0x6];
2218         u8         user_index[0x18];
2219
2220         u8         reserved_5[0x20];
2221
2222         u8         reserved_6[0x8];
2223         u8         pd[0x18];
2224
2225         u8         lwm[0x10];
2226         u8         wqe_cnt[0x10];
2227
2228         u8         reserved_7[0x40];
2229
2230         u8         db_record_addr_h[0x20];
2231
2232         u8         db_record_addr_l[0x1e];
2233         u8         reserved_8[0x2];
2234
2235         u8         reserved_9[0x80];
2236 };
2237
2238 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2239         u8         counter_error_queues[0x20];
2240
2241         u8         total_error_queues[0x20];
2242
2243         u8         send_queue_priority_update_flow[0x20];
2244
2245         u8         reserved_at_60[0x20];
2246
2247         u8         nic_receive_steering_discard[0x40];
2248
2249         u8         receive_discard_vport_down[0x40];
2250
2251         u8         transmit_discard_vport_down[0x40];
2252
2253         u8         reserved_at_140[0xec0];
2254 };
2255
2256 struct mlx5_ifc_traffic_counter_bits {
2257         u8         packets[0x40];
2258
2259         u8         octets[0x40];
2260 };
2261
2262 struct mlx5_ifc_tisc_bits {
2263         u8         strict_lag_tx_port_affinity[0x1];
2264         u8         tls_en[0x1];
2265         u8         reserved_at_2[0x2];
2266         u8         lag_tx_port_affinity[0x04];
2267
2268         u8         reserved_at_8[0x4];
2269         u8         prio[0x4];
2270         u8         reserved_1[0x10];
2271
2272         u8         reserved_2[0x100];
2273
2274         u8         reserved_3[0x8];
2275         u8         transport_domain[0x18];
2276
2277         u8         reserved_4[0x8];
2278         u8         underlay_qpn[0x18];
2279
2280         u8         reserved_5[0x8];
2281         u8         pd[0x18];
2282
2283         u8         reserved_6[0x380];
2284 };
2285
2286 enum {
2287         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2288         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2289 };
2290
2291 enum {
2292         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2293         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2294 };
2295
2296 enum {
2297         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2298         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2299         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2300 };
2301
2302 enum {
2303         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2304         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2305 };
2306
2307 struct mlx5_ifc_tirc_bits {
2308         u8         reserved_0[0x20];
2309
2310         u8         disp_type[0x4];
2311         u8         tls_en[0x1];
2312         u8         reserved_at_25[0x1b];
2313
2314         u8         reserved_2[0x40];
2315
2316         u8         reserved_3[0x4];
2317         u8         lro_timeout_period_usecs[0x10];
2318         u8         lro_enable_mask[0x4];
2319         u8         lro_max_msg_sz[0x8];
2320
2321         u8         reserved_4[0x40];
2322
2323         u8         reserved_5[0x8];
2324         u8         inline_rqn[0x18];
2325
2326         u8         rx_hash_symmetric[0x1];
2327         u8         reserved_6[0x1];
2328         u8         tunneled_offload_en[0x1];
2329         u8         reserved_7[0x5];
2330         u8         indirect_table[0x18];
2331
2332         u8         rx_hash_fn[0x4];
2333         u8         reserved_8[0x2];
2334         u8         self_lb_en[0x2];
2335         u8         transport_domain[0x18];
2336
2337         u8         rx_hash_toeplitz_key[10][0x20];
2338
2339         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2340
2341         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2342
2343         u8         reserved_9[0x4c0];
2344 };
2345
2346 enum {
2347         MLX5_SRQC_STATE_GOOD   = 0x0,
2348         MLX5_SRQC_STATE_ERROR  = 0x1,
2349 };
2350
2351 struct mlx5_ifc_srqc_bits {
2352         u8         state[0x4];
2353         u8         log_srq_size[0x4];
2354         u8         reserved_0[0x18];
2355
2356         u8         wq_signature[0x1];
2357         u8         cont_srq[0x1];
2358         u8         reserved_1[0x1];
2359         u8         rlky[0x1];
2360         u8         reserved_2[0x1];
2361         u8         log_rq_stride[0x3];
2362         u8         xrcd[0x18];
2363
2364         u8         page_offset[0x6];
2365         u8         reserved_3[0x2];
2366         u8         cqn[0x18];
2367
2368         u8         reserved_4[0x20];
2369
2370         u8         reserved_5[0x2];
2371         u8         log_page_size[0x6];
2372         u8         reserved_6[0x18];
2373
2374         u8         reserved_7[0x20];
2375
2376         u8         reserved_8[0x8];
2377         u8         pd[0x18];
2378
2379         u8         lwm[0x10];
2380         u8         wqe_cnt[0x10];
2381
2382         u8         reserved_9[0x40];
2383
2384         u8         dbr_addr[0x40];
2385
2386         u8         reserved_10[0x80];
2387 };
2388
2389 enum {
2390         MLX5_SQC_STATE_RST  = 0x0,
2391         MLX5_SQC_STATE_RDY  = 0x1,
2392         MLX5_SQC_STATE_ERR  = 0x3,
2393 };
2394
2395 struct mlx5_ifc_sqc_bits {
2396         u8         rlkey[0x1];
2397         u8         cd_master[0x1];
2398         u8         fre[0x1];
2399         u8         flush_in_error_en[0x1];
2400         u8         allow_multi_pkt_send_wqe[0x1];
2401         u8         min_wqe_inline_mode[0x3];
2402         u8         state[0x4];
2403         u8         reg_umr[0x1];
2404         u8         allow_swp[0x1];
2405         u8         reserved_0[0x12];
2406
2407         u8         reserved_1[0x8];
2408         u8         user_index[0x18];
2409
2410         u8         reserved_2[0x8];
2411         u8         cqn[0x18];
2412
2413         u8         reserved_3[0x80];
2414
2415         u8         qos_para_vport_number[0x10];
2416         u8         packet_pacing_rate_limit_index[0x10];
2417
2418         u8         tis_lst_sz[0x10];
2419         u8         reserved_4[0x10];
2420
2421         u8         reserved_5[0x40];
2422
2423         u8         reserved_6[0x8];
2424         u8         tis_num_0[0x18];
2425
2426         struct mlx5_ifc_wq_bits wq;
2427 };
2428
2429 enum {
2430         MLX5_TSAR_TYPE_DWRR = 0,
2431         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2432         MLX5_TSAR_TYPE_ETS = 2
2433 };
2434
2435 struct mlx5_ifc_tsar_element_attributes_bits {
2436         u8         reserved_0[0x8];
2437         u8         tsar_type[0x8];
2438         u8         reserved_1[0x10];
2439 };
2440
2441 struct mlx5_ifc_vport_element_attributes_bits {
2442         u8         reserved_0[0x10];
2443         u8         vport_number[0x10];
2444 };
2445
2446 struct mlx5_ifc_vport_tc_element_attributes_bits {
2447         u8         traffic_class[0x10];
2448         u8         vport_number[0x10];
2449 };
2450
2451 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2452         u8         reserved_0[0x0C];
2453         u8         traffic_class[0x04];
2454         u8         qos_para_vport_number[0x10];
2455 };
2456
2457 enum {
2458         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2459         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2460         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2461         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2462 };
2463
2464 struct mlx5_ifc_scheduling_context_bits {
2465         u8         element_type[0x8];
2466         u8         reserved_at_8[0x18];
2467
2468         u8         element_attributes[0x20];
2469
2470         u8         parent_element_id[0x20];
2471
2472         u8         reserved_at_60[0x40];
2473
2474         u8         bw_share[0x20];
2475
2476         u8         max_average_bw[0x20];
2477
2478         u8         reserved_at_e0[0x120];
2479 };
2480
2481 struct mlx5_ifc_rqtc_bits {
2482         u8         reserved_0[0xa0];
2483
2484         u8         reserved_1[0x10];
2485         u8         rqt_max_size[0x10];
2486
2487         u8         reserved_2[0x10];
2488         u8         rqt_actual_size[0x10];
2489
2490         u8         reserved_3[0x6a0];
2491
2492         struct mlx5_ifc_rq_num_bits rq_num[0];
2493 };
2494
2495 enum {
2496         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2497         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2498 };
2499
2500 enum {
2501         MLX5_RQC_STATE_RST  = 0x0,
2502         MLX5_RQC_STATE_RDY  = 0x1,
2503         MLX5_RQC_STATE_ERR  = 0x3,
2504 };
2505
2506 enum {
2507         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2508         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2509 };
2510
2511 struct mlx5_ifc_rqc_bits {
2512         u8         rlkey[0x1];
2513         u8         delay_drop_en[0x1];
2514         u8         scatter_fcs[0x1];
2515         u8         vlan_strip_disable[0x1];
2516         u8         mem_rq_type[0x4];
2517         u8         state[0x4];
2518         u8         reserved_1[0x1];
2519         u8         flush_in_error_en[0x1];
2520         u8         reserved_2[0x12];
2521
2522         u8         reserved_3[0x8];
2523         u8         user_index[0x18];
2524
2525         u8         reserved_4[0x8];
2526         u8         cqn[0x18];
2527
2528         u8         counter_set_id[0x8];
2529         u8         reserved_5[0x18];
2530
2531         u8         reserved_6[0x8];
2532         u8         rmpn[0x18];
2533
2534         u8         reserved_7[0xe0];
2535
2536         struct mlx5_ifc_wq_bits wq;
2537 };
2538
2539 enum {
2540         MLX5_RMPC_STATE_RDY  = 0x1,
2541         MLX5_RMPC_STATE_ERR  = 0x3,
2542 };
2543
2544 struct mlx5_ifc_rmpc_bits {
2545         u8         reserved_0[0x8];
2546         u8         state[0x4];
2547         u8         reserved_1[0x14];
2548
2549         u8         basic_cyclic_rcv_wqe[0x1];
2550         u8         reserved_2[0x1f];
2551
2552         u8         reserved_3[0x140];
2553
2554         struct mlx5_ifc_wq_bits wq;
2555 };
2556
2557 enum {
2558         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2559         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2560         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2561 };
2562
2563 struct mlx5_ifc_nic_vport_context_bits {
2564         u8         reserved_0[0x5];
2565         u8         min_wqe_inline_mode[0x3];
2566         u8         reserved_1[0x15];
2567         u8         disable_mc_local_lb[0x1];
2568         u8         disable_uc_local_lb[0x1];
2569         u8         roce_en[0x1];
2570
2571         u8         arm_change_event[0x1];
2572         u8         reserved_2[0x1a];
2573         u8         event_on_mtu[0x1];
2574         u8         event_on_promisc_change[0x1];
2575         u8         event_on_vlan_change[0x1];
2576         u8         event_on_mc_address_change[0x1];
2577         u8         event_on_uc_address_change[0x1];
2578
2579         u8         reserved_3[0xe0];
2580
2581         u8         reserved_4[0x10];
2582         u8         mtu[0x10];
2583
2584         u8         system_image_guid[0x40];
2585
2586         u8         port_guid[0x40];
2587
2588         u8         node_guid[0x40];
2589
2590         u8         reserved_5[0x140];
2591
2592         u8         qkey_violation_counter[0x10];
2593         u8         reserved_6[0x10];
2594
2595         u8         reserved_7[0x420];
2596
2597         u8         promisc_uc[0x1];
2598         u8         promisc_mc[0x1];
2599         u8         promisc_all[0x1];
2600         u8         reserved_8[0x2];
2601         u8         allowed_list_type[0x3];
2602         u8         reserved_9[0xc];
2603         u8         allowed_list_size[0xc];
2604
2605         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2606
2607         u8         reserved_10[0x20];
2608
2609         u8         current_uc_mac_address[0][0x40];
2610 };
2611
2612 enum {
2613         MLX5_ACCESS_MODE_PA        = 0x0,
2614         MLX5_ACCESS_MODE_MTT       = 0x1,
2615         MLX5_ACCESS_MODE_KLM       = 0x2,
2616 };
2617
2618 struct mlx5_ifc_mkc_bits {
2619         u8         reserved_at_0[0x1];
2620         u8         free[0x1];
2621         u8         reserved_at_2[0x1];
2622         u8         access_mode_4_2[0x3];
2623         u8         reserved_at_6[0x7];
2624         u8         relaxed_ordering_write[0x1];
2625         u8         reserved_at_e[0x1];
2626         u8         small_fence_on_rdma_read_response[0x1];
2627         u8         umr_en[0x1];
2628         u8         a[0x1];
2629         u8         rw[0x1];
2630         u8         rr[0x1];
2631         u8         lw[0x1];
2632         u8         lr[0x1];
2633         u8         access_mode[0x2];
2634         u8         reserved_2[0x8];
2635
2636         u8         qpn[0x18];
2637         u8         mkey_7_0[0x8];
2638
2639         u8         reserved_3[0x20];
2640
2641         u8         length64[0x1];
2642         u8         bsf_en[0x1];
2643         u8         sync_umr[0x1];
2644         u8         reserved_4[0x2];
2645         u8         expected_sigerr_count[0x1];
2646         u8         reserved_5[0x1];
2647         u8         en_rinval[0x1];
2648         u8         pd[0x18];
2649
2650         u8         start_addr[0x40];
2651
2652         u8         len[0x40];
2653
2654         u8         bsf_octword_size[0x20];
2655
2656         u8         reserved_6[0x80];
2657
2658         u8         translations_octword_size[0x20];
2659
2660         u8         reserved_7[0x1b];
2661         u8         log_page_size[0x5];
2662
2663         u8         reserved_8[0x20];
2664 };
2665
2666 struct mlx5_ifc_pkey_bits {
2667         u8         reserved_0[0x10];
2668         u8         pkey[0x10];
2669 };
2670
2671 struct mlx5_ifc_array128_auto_bits {
2672         u8         array128_auto[16][0x8];
2673 };
2674
2675 enum {
2676         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2677         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2678         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2679 };
2680
2681 enum {
2682         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2683         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2684         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2685         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2686         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2687         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2688         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2689 };
2690
2691 enum {
2692         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2693         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2694         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2695 };
2696
2697 enum {
2698         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2699         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2700         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2701         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2702 };
2703
2704 enum {
2705         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2706         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2707         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2708         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2709 };
2710
2711 struct mlx5_ifc_hca_vport_context_bits {
2712         u8         field_select[0x20];
2713
2714         u8         reserved_0[0xe0];
2715
2716         u8         sm_virt_aware[0x1];
2717         u8         has_smi[0x1];
2718         u8         has_raw[0x1];
2719         u8         grh_required[0x1];
2720         u8         reserved_1[0x1];
2721         u8         min_wqe_inline_mode[0x3];
2722         u8         reserved_2[0x8];
2723         u8         port_physical_state[0x4];
2724         u8         vport_state_policy[0x4];
2725         u8         port_state[0x4];
2726         u8         vport_state[0x4];
2727
2728         u8         reserved_3[0x20];
2729
2730         u8         system_image_guid[0x40];
2731
2732         u8         port_guid[0x40];
2733
2734         u8         node_guid[0x40];
2735
2736         u8         cap_mask1[0x20];
2737
2738         u8         cap_mask1_field_select[0x20];
2739
2740         u8         cap_mask2[0x20];
2741
2742         u8         cap_mask2_field_select[0x20];
2743
2744         u8         reserved_4[0x80];
2745
2746         u8         lid[0x10];
2747         u8         reserved_5[0x4];
2748         u8         init_type_reply[0x4];
2749         u8         lmc[0x3];
2750         u8         subnet_timeout[0x5];
2751
2752         u8         sm_lid[0x10];
2753         u8         sm_sl[0x4];
2754         u8         reserved_6[0xc];
2755
2756         u8         qkey_violation_counter[0x10];
2757         u8         pkey_violation_counter[0x10];
2758
2759         u8         reserved_7[0xca0];
2760 };
2761
2762 union mlx5_ifc_hca_cap_union_bits {
2763         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2764         struct mlx5_ifc_odp_cap_bits odp_cap;
2765         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2766         struct mlx5_ifc_roce_cap_bits roce_cap;
2767         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2768         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2769         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2770         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2771         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2772         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2773         struct mlx5_ifc_qos_cap_bits qos_cap;
2774         struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2775         u8         reserved_0[0x8000];
2776 };
2777
2778 enum {
2779         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2780         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2781 };
2782
2783 struct mlx5_ifc_flow_table_context_bits {
2784         u8         encap_en[0x1];
2785         u8         decap_en[0x1];
2786         u8         reserved_at_2[0x2];
2787         u8         table_miss_action[0x4];
2788         u8         level[0x8];
2789         u8         reserved_at_10[0x8];
2790         u8         log_size[0x8];
2791
2792         u8         reserved_at_20[0x8];
2793         u8         table_miss_id[0x18];
2794
2795         u8         reserved_at_40[0x8];
2796         u8         lag_master_next_table_id[0x18];
2797
2798         u8         reserved_at_60[0xe0];
2799 };
2800
2801 struct mlx5_ifc_esw_vport_context_bits {
2802         u8         reserved_0[0x3];
2803         u8         vport_svlan_strip[0x1];
2804         u8         vport_cvlan_strip[0x1];
2805         u8         vport_svlan_insert[0x1];
2806         u8         vport_cvlan_insert[0x2];
2807         u8         reserved_1[0x18];
2808
2809         u8         reserved_2[0x20];
2810
2811         u8         svlan_cfi[0x1];
2812         u8         svlan_pcp[0x3];
2813         u8         svlan_id[0xc];
2814         u8         cvlan_cfi[0x1];
2815         u8         cvlan_pcp[0x3];
2816         u8         cvlan_id[0xc];
2817
2818         u8         reserved_3[0x7a0];
2819 };
2820
2821 enum {
2822         MLX5_EQC_STATUS_OK                = 0x0,
2823         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2824 };
2825
2826 enum {
2827         MLX5_EQ_STATE_ARMED = 0x9,
2828         MLX5_EQ_STATE_FIRED = 0xa,
2829 };
2830
2831 struct mlx5_ifc_eqc_bits {
2832         u8         status[0x4];
2833         u8         reserved_0[0x9];
2834         u8         ec[0x1];
2835         u8         oi[0x1];
2836         u8         reserved_1[0x5];
2837         u8         st[0x4];
2838         u8         reserved_2[0x8];
2839
2840         u8         reserved_3[0x20];
2841
2842         u8         reserved_4[0x14];
2843         u8         page_offset[0x6];
2844         u8         reserved_5[0x6];
2845
2846         u8         reserved_6[0x3];
2847         u8         log_eq_size[0x5];
2848         u8         uar_page[0x18];
2849
2850         u8         reserved_7[0x20];
2851
2852         u8         reserved_8[0x18];
2853         u8         intr[0x8];
2854
2855         u8         reserved_9[0x3];
2856         u8         log_page_size[0x5];
2857         u8         reserved_10[0x18];
2858
2859         u8         reserved_11[0x60];
2860
2861         u8         reserved_12[0x8];
2862         u8         consumer_counter[0x18];
2863
2864         u8         reserved_13[0x8];
2865         u8         producer_counter[0x18];
2866
2867         u8         reserved_14[0x80];
2868 };
2869
2870 enum {
2871         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2872         MLX5_DCTC_STATE_DRAINING  = 0x1,
2873         MLX5_DCTC_STATE_DRAINED   = 0x2,
2874 };
2875
2876 enum {
2877         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2878         MLX5_DCTC_CS_RES_NA         = 0x1,
2879         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2880 };
2881
2882 enum {
2883         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2884         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2885         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2886         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2887         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2888 };
2889
2890 struct mlx5_ifc_dctc_bits {
2891         u8         reserved_0[0x4];
2892         u8         state[0x4];
2893         u8         reserved_1[0x18];
2894
2895         u8         reserved_2[0x8];
2896         u8         user_index[0x18];
2897
2898         u8         reserved_3[0x8];
2899         u8         cqn[0x18];
2900
2901         u8         counter_set_id[0x8];
2902         u8         atomic_mode[0x4];
2903         u8         rre[0x1];
2904         u8         rwe[0x1];
2905         u8         rae[0x1];
2906         u8         atomic_like_write_en[0x1];
2907         u8         latency_sensitive[0x1];
2908         u8         rlky[0x1];
2909         u8         reserved_4[0xe];
2910
2911         u8         reserved_5[0x8];
2912         u8         cs_res[0x8];
2913         u8         reserved_6[0x3];
2914         u8         min_rnr_nak[0x5];
2915         u8         reserved_7[0x8];
2916
2917         u8         reserved_8[0x8];
2918         u8         srqn[0x18];
2919
2920         u8         reserved_9[0x8];
2921         u8         pd[0x18];
2922
2923         u8         tclass[0x8];
2924         u8         reserved_10[0x4];
2925         u8         flow_label[0x14];
2926
2927         u8         dc_access_key[0x40];
2928
2929         u8         reserved_11[0x5];
2930         u8         mtu[0x3];
2931         u8         port[0x8];
2932         u8         pkey_index[0x10];
2933
2934         u8         reserved_12[0x8];
2935         u8         my_addr_index[0x8];
2936         u8         reserved_13[0x8];
2937         u8         hop_limit[0x8];
2938
2939         u8         dc_access_key_violation_count[0x20];
2940
2941         u8         reserved_14[0x14];
2942         u8         dei_cfi[0x1];
2943         u8         eth_prio[0x3];
2944         u8         ecn[0x2];
2945         u8         dscp[0x6];
2946
2947         u8         reserved_15[0x40];
2948 };
2949
2950 enum {
2951         MLX5_CQC_STATUS_OK             = 0x0,
2952         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2953         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2954 };
2955
2956 enum {
2957         CQE_SIZE_64                = 0x0,
2958         CQE_SIZE_128               = 0x1,
2959 };
2960
2961 enum {
2962         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2963         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2964 };
2965
2966 enum {
2967         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2968         MLX5_CQ_STATE_ARMED                               = 0x9,
2969         MLX5_CQ_STATE_FIRED                               = 0xa,
2970 };
2971
2972 struct mlx5_ifc_cqc_bits {
2973         u8         status[0x4];
2974         u8         reserved_0[0x4];
2975         u8         cqe_sz[0x3];
2976         u8         cc[0x1];
2977         u8         reserved_1[0x1];
2978         u8         scqe_break_moderation_en[0x1];
2979         u8         oi[0x1];
2980         u8         cq_period_mode[0x2];
2981         u8         cqe_compression_en[0x1];
2982         u8         mini_cqe_res_format[0x2];
2983         u8         st[0x4];
2984         u8         reserved_2[0x8];
2985
2986         u8         reserved_3[0x20];
2987
2988         u8         reserved_4[0x14];
2989         u8         page_offset[0x6];
2990         u8         reserved_5[0x6];
2991
2992         u8         reserved_6[0x3];
2993         u8         log_cq_size[0x5];
2994         u8         uar_page[0x18];
2995
2996         u8         reserved_7[0x4];
2997         u8         cq_period[0xc];
2998         u8         cq_max_count[0x10];
2999
3000         u8         reserved_8[0x18];
3001         u8         c_eqn[0x8];
3002
3003         u8         reserved_9[0x3];
3004         u8         log_page_size[0x5];
3005         u8         reserved_10[0x18];
3006
3007         u8         reserved_11[0x20];
3008
3009         u8         reserved_12[0x8];
3010         u8         last_notified_index[0x18];
3011
3012         u8         reserved_13[0x8];
3013         u8         last_solicit_index[0x18];
3014
3015         u8         reserved_14[0x8];
3016         u8         consumer_counter[0x18];
3017
3018         u8         reserved_15[0x8];
3019         u8         producer_counter[0x18];
3020
3021         u8         reserved_16[0x40];
3022
3023         u8         dbr_addr[0x40];
3024 };
3025
3026 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3027         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3028         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3029         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3030         u8         reserved_0[0x800];
3031 };
3032
3033 struct mlx5_ifc_query_adapter_param_block_bits {
3034         u8         reserved_0[0xc0];
3035
3036         u8         reserved_1[0x8];
3037         u8         ieee_vendor_id[0x18];
3038
3039         u8         reserved_2[0x10];
3040         u8         vsd_vendor_id[0x10];
3041
3042         u8         vsd[208][0x8];
3043
3044         u8         vsd_contd_psid[16][0x8];
3045 };
3046
3047 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3048         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3049         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3050         u8         reserved_0[0x20];
3051 };
3052
3053 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3054         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3055         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3056         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3057         u8         reserved_0[0x20];
3058 };
3059
3060 struct mlx5_ifc_bufferx_reg_bits {
3061         u8         reserved_0[0x6];
3062         u8         lossy[0x1];
3063         u8         epsb[0x1];
3064         u8         reserved_1[0xc];
3065         u8         size[0xc];
3066
3067         u8         xoff_threshold[0x10];
3068         u8         xon_threshold[0x10];
3069 };
3070
3071 struct mlx5_ifc_config_item_bits {
3072         u8         valid[0x2];
3073         u8         reserved_0[0x2];
3074         u8         header_type[0x2];
3075         u8         reserved_1[0x2];
3076         u8         default_location[0x1];
3077         u8         reserved_2[0x7];
3078         u8         version[0x4];
3079         u8         reserved_3[0x3];
3080         u8         length[0x9];
3081
3082         u8         type[0x20];
3083
3084         u8         reserved_4[0x10];
3085         u8         crc16[0x10];
3086 };
3087
3088 struct mlx5_ifc_nodnic_port_config_reg_bits {
3089         struct mlx5_ifc_nodnic_event_word_bits event;
3090
3091         u8         network_en[0x1];
3092         u8         dma_en[0x1];
3093         u8         promisc_en[0x1];
3094         u8         promisc_multicast_en[0x1];
3095         u8         reserved_0[0x17];
3096         u8         receive_filter_en[0x5];
3097
3098         u8         reserved_1[0x10];
3099         u8         mac_47_32[0x10];
3100
3101         u8         mac_31_0[0x20];
3102
3103         u8         receive_filters_mgid_mac[64][0x8];
3104
3105         u8         gid[16][0x8];
3106
3107         u8         reserved_2[0x10];
3108         u8         lid[0x10];
3109
3110         u8         reserved_3[0xc];
3111         u8         sm_sl[0x4];
3112         u8         sm_lid[0x10];
3113
3114         u8         completion_address_63_32[0x20];
3115
3116         u8         completion_address_31_12[0x14];
3117         u8         reserved_4[0x6];
3118         u8         log_cq_size[0x6];
3119
3120         u8         working_buffer_address_63_32[0x20];
3121
3122         u8         working_buffer_address_31_12[0x14];
3123         u8         reserved_5[0xc];
3124
3125         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3126
3127         u8         pkey_index[0x10];
3128         u8         pkey[0x10];
3129
3130         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3131
3132         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3133
3134         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3135
3136         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3137
3138         u8         reserved_6[0x400];
3139 };
3140
3141 union mlx5_ifc_event_auto_bits {
3142         struct mlx5_ifc_comp_event_bits comp_event;
3143         struct mlx5_ifc_dct_events_bits dct_events;
3144         struct mlx5_ifc_qp_events_bits qp_events;
3145         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3146         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3147         struct mlx5_ifc_cq_error_bits cq_error;
3148         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3149         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3150         struct mlx5_ifc_gpio_event_bits gpio_event;
3151         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3152         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3153         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3154         struct mlx5_ifc_pages_req_event_bits pages_req_event;
3155         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3156         u8         reserved_0[0xe0];
3157 };
3158
3159 struct mlx5_ifc_health_buffer_bits {
3160         u8         reserved_0[0x100];
3161
3162         u8         assert_existptr[0x20];
3163
3164         u8         assert_callra[0x20];
3165
3166         u8         reserved_1[0x40];
3167
3168         u8         fw_version[0x20];
3169
3170         u8         hw_id[0x20];
3171
3172         u8         reserved_2[0x20];
3173
3174         u8         irisc_index[0x8];
3175         u8         synd[0x8];
3176         u8         ext_synd[0x10];
3177 };
3178
3179 struct mlx5_ifc_register_loopback_control_bits {
3180         u8         no_lb[0x1];
3181         u8         reserved_0[0x7];
3182         u8         port[0x8];
3183         u8         reserved_1[0x10];
3184
3185         u8         reserved_2[0x60];
3186 };
3187
3188 struct mlx5_ifc_lrh_bits {
3189         u8      vl[4];
3190         u8      lver[4];
3191         u8      sl[4];
3192         u8      reserved2[2];
3193         u8      lnh[2];
3194         u8      dlid[16];
3195         u8      reserved5[5];
3196         u8      pkt_len[11];
3197         u8      slid[16];
3198 };
3199
3200 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3201         u8         reserved_0[0x40];
3202
3203         u8         reserved_1[0x10];
3204         u8         rol_mode[0x8];
3205         u8         wol_mode[0x8];
3206 };
3207
3208 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3209         u8         reserved_0[0x40];
3210
3211         u8         rol_mode_valid[0x1];
3212         u8         wol_mode_valid[0x1];
3213         u8         reserved_1[0xe];
3214         u8         rol_mode[0x8];
3215         u8         wol_mode[0x8];
3216
3217         u8         reserved_2[0x7a0];
3218 };
3219
3220 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3221         u8         virtual_mac_en[0x1];
3222         u8         mac_aux_v[0x1];
3223         u8         reserved_0[0x1e];
3224
3225         u8         reserved_1[0x40];
3226
3227         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3228
3229         u8         reserved_2[0x760];
3230 };
3231
3232 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3233         u8         virtual_mac_en[0x1];
3234         u8         mac_aux_v[0x1];
3235         u8         reserved_0[0x1e];
3236
3237         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3238
3239         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3240
3241         u8         reserved_1[0x760];
3242 };
3243
3244 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3245         struct mlx5_ifc_fw_version_bits fw_version;
3246
3247         u8         reserved_0[0x10];
3248         u8         hash_signature[0x10];
3249
3250         u8         psid[16][0x8];
3251
3252         u8         reserved_1[0x6e0];
3253 };
3254
3255 struct mlx5_ifc_icmd_query_cap_in_bits {
3256         u8         reserved_0[0x10];
3257         u8         capability_group[0x10];
3258 };
3259
3260 struct mlx5_ifc_icmd_query_cap_general_bits {
3261         u8         nv_access[0x1];
3262         u8         fw_info_psid[0x1];
3263         u8         reserved_0[0x1e];
3264
3265         u8         reserved_1[0x16];
3266         u8         rol_s[0x1];
3267         u8         rol_g[0x1];
3268         u8         reserved_2[0x1];
3269         u8         wol_s[0x1];
3270         u8         wol_g[0x1];
3271         u8         wol_a[0x1];
3272         u8         wol_b[0x1];
3273         u8         wol_m[0x1];
3274         u8         wol_u[0x1];
3275         u8         wol_p[0x1];
3276 };
3277
3278 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3279         u8         status[0x8];
3280         u8         reserved_0[0x18];
3281
3282         u8         reserved_1[0x7e0];
3283 };
3284
3285 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_0[0x18];
3288
3289         u8         reserved_1[0x7e0];
3290 };
3291
3292 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3293         u8         address_hi[0x20];
3294
3295         u8         address_lo[0x20];
3296
3297         u8         reserved_0[0x7c0];
3298 };
3299
3300 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3301         u8         reserved_0[0x20];
3302
3303         u8         address_hi[0x20];
3304
3305         u8         address_lo[0x20];
3306
3307         u8         reserved_1[0x7a0];
3308 };
3309
3310 struct mlx5_ifc_icmd_access_reg_out_bits {
3311         u8         reserved_0[0x11];
3312         u8         status[0x7];
3313         u8         reserved_1[0x8];
3314
3315         u8         register_id[0x10];
3316         u8         reserved_2[0x10];
3317
3318         u8         reserved_3[0x40];
3319
3320         u8         reserved_4[0x5];
3321         u8         len[0xb];
3322         u8         reserved_5[0x10];
3323
3324         u8         register_data[0][0x20];
3325 };
3326
3327 enum {
3328         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3329         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3330 };
3331
3332 struct mlx5_ifc_icmd_access_reg_in_bits {
3333         u8         constant_1[0x5];
3334         u8         constant_2[0xb];
3335         u8         reserved_0[0x10];
3336
3337         u8         register_id[0x10];
3338         u8         reserved_1[0x1];
3339         u8         method[0x7];
3340         u8         constant_3[0x8];
3341
3342         u8         reserved_2[0x40];
3343
3344         u8         constant_4[0x5];
3345         u8         len[0xb];
3346         u8         reserved_3[0x10];
3347
3348         u8         register_data[0][0x20];
3349 };
3350
3351 enum {
3352         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3353         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3354 };
3355
3356 struct mlx5_ifc_teardown_hca_out_bits {
3357         u8         status[0x8];
3358         u8         reserved_0[0x18];
3359
3360         u8         syndrome[0x20];
3361
3362         u8         reserved_1[0x3f];
3363
3364         u8         state[0x1];
3365 };
3366
3367 enum {
3368         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3369         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3370         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3371 };
3372
3373 struct mlx5_ifc_teardown_hca_in_bits {
3374         u8         opcode[0x10];
3375         u8         reserved_0[0x10];
3376
3377         u8         reserved_1[0x10];
3378         u8         op_mod[0x10];
3379
3380         u8         reserved_2[0x10];
3381         u8         profile[0x10];
3382
3383         u8         reserved_3[0x20];
3384 };
3385
3386 struct mlx5_ifc_set_delay_drop_params_out_bits {
3387         u8         status[0x8];
3388         u8         reserved_at_8[0x18];
3389
3390         u8         syndrome[0x20];
3391
3392         u8         reserved_at_40[0x40];
3393 };
3394
3395 struct mlx5_ifc_set_delay_drop_params_in_bits {
3396         u8         opcode[0x10];
3397         u8         reserved_at_10[0x10];
3398
3399         u8         reserved_at_20[0x10];
3400         u8         op_mod[0x10];
3401
3402         u8         reserved_at_40[0x20];
3403
3404         u8         reserved_at_60[0x10];
3405         u8         delay_drop_timeout[0x10];
3406 };
3407
3408 struct mlx5_ifc_query_delay_drop_params_out_bits {
3409         u8         status[0x8];
3410         u8         reserved_at_8[0x18];
3411
3412         u8         syndrome[0x20];
3413
3414         u8         reserved_at_40[0x20];
3415
3416         u8         reserved_at_60[0x10];
3417         u8         delay_drop_timeout[0x10];
3418 };
3419
3420 struct mlx5_ifc_query_delay_drop_params_in_bits {
3421         u8         opcode[0x10];
3422         u8         reserved_at_10[0x10];
3423
3424         u8         reserved_at_20[0x10];
3425         u8         op_mod[0x10];
3426
3427         u8         reserved_at_40[0x40];
3428 };
3429
3430 struct mlx5_ifc_suspend_qp_out_bits {
3431         u8         status[0x8];
3432         u8         reserved_0[0x18];
3433
3434         u8         syndrome[0x20];
3435
3436         u8         reserved_1[0x40];
3437 };
3438
3439 struct mlx5_ifc_suspend_qp_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_0[0x10];
3442
3443         u8         reserved_1[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         reserved_2[0x8];
3447         u8         qpn[0x18];
3448
3449         u8         reserved_3[0x20];
3450 };
3451
3452 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3453         u8         status[0x8];
3454         u8         reserved_0[0x18];
3455
3456         u8         syndrome[0x20];
3457
3458         u8         reserved_1[0x40];
3459 };
3460
3461 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3462         u8         opcode[0x10];
3463         u8         reserved_0[0x10];
3464
3465         u8         reserved_1[0x10];
3466         u8         op_mod[0x10];
3467
3468         u8         reserved_2[0x8];
3469         u8         qpn[0x18];
3470
3471         u8         reserved_3[0x20];
3472
3473         u8         opt_param_mask[0x20];
3474
3475         u8         reserved_4[0x20];
3476
3477         struct mlx5_ifc_qpc_bits qpc;
3478
3479         u8         reserved_5[0x80];
3480 };
3481
3482 struct mlx5_ifc_sqd2rts_qp_out_bits {
3483         u8         status[0x8];
3484         u8         reserved_0[0x18];
3485
3486         u8         syndrome[0x20];
3487
3488         u8         reserved_1[0x40];
3489 };
3490
3491 struct mlx5_ifc_sqd2rts_qp_in_bits {
3492         u8         opcode[0x10];
3493         u8         reserved_0[0x10];
3494
3495         u8         reserved_1[0x10];
3496         u8         op_mod[0x10];
3497
3498         u8         reserved_2[0x8];
3499         u8         qpn[0x18];
3500
3501         u8         reserved_3[0x20];
3502
3503         u8         opt_param_mask[0x20];
3504
3505         u8         reserved_4[0x20];
3506
3507         struct mlx5_ifc_qpc_bits qpc;
3508
3509         u8         reserved_5[0x80];
3510 };
3511
3512 struct mlx5_ifc_set_wol_rol_out_bits {
3513         u8         status[0x8];
3514         u8         reserved_0[0x18];
3515
3516         u8         syndrome[0x20];
3517
3518         u8         reserved_1[0x40];
3519 };
3520
3521 struct mlx5_ifc_set_wol_rol_in_bits {
3522         u8         opcode[0x10];
3523         u8         reserved_0[0x10];
3524
3525         u8         reserved_1[0x10];
3526         u8         op_mod[0x10];
3527
3528         u8         rol_mode_valid[0x1];
3529         u8         wol_mode_valid[0x1];
3530         u8         reserved_2[0xe];
3531         u8         rol_mode[0x8];
3532         u8         wol_mode[0x8];
3533
3534         u8         reserved_3[0x20];
3535 };
3536
3537 struct mlx5_ifc_set_roce_address_out_bits {
3538         u8         status[0x8];
3539         u8         reserved_0[0x18];
3540
3541         u8         syndrome[0x20];
3542
3543         u8         reserved_1[0x40];
3544 };
3545
3546 struct mlx5_ifc_set_roce_address_in_bits {
3547         u8         opcode[0x10];
3548         u8         reserved_0[0x10];
3549
3550         u8         reserved_1[0x10];
3551         u8         op_mod[0x10];
3552
3553         u8         roce_address_index[0x10];
3554         u8         reserved_2[0x10];
3555
3556         u8         reserved_3[0x20];
3557
3558         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3559 };
3560
3561 struct mlx5_ifc_set_rdb_out_bits {
3562         u8         status[0x8];
3563         u8         reserved_0[0x18];
3564
3565         u8         syndrome[0x20];
3566
3567         u8         reserved_1[0x40];
3568 };
3569
3570 struct mlx5_ifc_set_rdb_in_bits {
3571         u8         opcode[0x10];
3572         u8         reserved_0[0x10];
3573
3574         u8         reserved_1[0x10];
3575         u8         op_mod[0x10];
3576
3577         u8         reserved_2[0x8];
3578         u8         qpn[0x18];
3579
3580         u8         reserved_3[0x18];
3581         u8         rdb_list_size[0x8];
3582
3583         struct mlx5_ifc_rdbc_bits rdb_context[0];
3584 };
3585
3586 struct mlx5_ifc_set_mad_demux_out_bits {
3587         u8         status[0x8];
3588         u8         reserved_0[0x18];
3589
3590         u8         syndrome[0x20];
3591
3592         u8         reserved_1[0x40];
3593 };
3594
3595 enum {
3596         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3597         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3598 };
3599
3600 struct mlx5_ifc_set_mad_demux_in_bits {
3601         u8         opcode[0x10];
3602         u8         reserved_0[0x10];
3603
3604         u8         reserved_1[0x10];
3605         u8         op_mod[0x10];
3606
3607         u8         reserved_2[0x20];
3608
3609         u8         reserved_3[0x6];
3610         u8         demux_mode[0x2];
3611         u8         reserved_4[0x18];
3612 };
3613
3614 struct mlx5_ifc_set_l2_table_entry_out_bits {
3615         u8         status[0x8];
3616         u8         reserved_0[0x18];
3617
3618         u8         syndrome[0x20];
3619
3620         u8         reserved_1[0x40];
3621 };
3622
3623 struct mlx5_ifc_set_l2_table_entry_in_bits {
3624         u8         opcode[0x10];
3625         u8         reserved_0[0x10];
3626
3627         u8         reserved_1[0x10];
3628         u8         op_mod[0x10];
3629
3630         u8         reserved_2[0x60];
3631
3632         u8         reserved_3[0x8];
3633         u8         table_index[0x18];
3634
3635         u8         reserved_4[0x20];
3636
3637         u8         reserved_5[0x13];
3638         u8         vlan_valid[0x1];
3639         u8         vlan[0xc];
3640
3641         struct mlx5_ifc_mac_address_layout_bits mac_address;
3642
3643         u8         reserved_6[0xc0];
3644 };
3645
3646 struct mlx5_ifc_set_issi_out_bits {
3647         u8         status[0x8];
3648         u8         reserved_0[0x18];
3649
3650         u8         syndrome[0x20];
3651
3652         u8         reserved_1[0x40];
3653 };
3654
3655 struct mlx5_ifc_set_issi_in_bits {
3656         u8         opcode[0x10];
3657         u8         reserved_0[0x10];
3658
3659         u8         reserved_1[0x10];
3660         u8         op_mod[0x10];
3661
3662         u8         reserved_2[0x10];
3663         u8         current_issi[0x10];
3664
3665         u8         reserved_3[0x20];
3666 };
3667
3668 struct mlx5_ifc_set_hca_cap_out_bits {
3669         u8         status[0x8];
3670         u8         reserved_0[0x18];
3671
3672         u8         syndrome[0x20];
3673
3674         u8         reserved_1[0x40];
3675 };
3676
3677 struct mlx5_ifc_set_hca_cap_in_bits {
3678         u8         opcode[0x10];
3679         u8         reserved_0[0x10];
3680
3681         u8         reserved_1[0x10];
3682         u8         op_mod[0x10];
3683
3684         u8         reserved_2[0x40];
3685
3686         union mlx5_ifc_hca_cap_union_bits capability;
3687 };
3688
3689 enum {
3690         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3691         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3692         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3693         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3694 };
3695
3696 struct mlx5_ifc_set_flow_table_root_out_bits {
3697         u8         status[0x8];
3698         u8         reserved_0[0x18];
3699
3700         u8         syndrome[0x20];
3701
3702         u8         reserved_1[0x40];
3703 };
3704
3705 struct mlx5_ifc_set_flow_table_root_in_bits {
3706         u8         opcode[0x10];
3707         u8         reserved_0[0x10];
3708
3709         u8         reserved_1[0x10];
3710         u8         op_mod[0x10];
3711
3712         u8         other_vport[0x1];
3713         u8         reserved_2[0xf];
3714         u8         vport_number[0x10];
3715
3716         u8         reserved_3[0x20];
3717
3718         u8         table_type[0x8];
3719         u8         reserved_4[0x18];
3720
3721         u8         reserved_5[0x8];
3722         u8         table_id[0x18];
3723
3724         u8         reserved_6[0x8];
3725         u8         underlay_qpn[0x18];
3726
3727         u8         reserved_7[0x120];
3728 };
3729
3730 struct mlx5_ifc_set_fte_out_bits {
3731         u8         status[0x8];
3732         u8         reserved_0[0x18];
3733
3734         u8         syndrome[0x20];
3735
3736         u8         reserved_1[0x40];
3737 };
3738
3739 struct mlx5_ifc_set_fte_in_bits {
3740         u8         opcode[0x10];
3741         u8         reserved_0[0x10];
3742
3743         u8         reserved_1[0x10];
3744         u8         op_mod[0x10];
3745
3746         u8         other_vport[0x1];
3747         u8         reserved_2[0xf];
3748         u8         vport_number[0x10];
3749
3750         u8         reserved_3[0x20];
3751
3752         u8         table_type[0x8];
3753         u8         reserved_4[0x18];
3754
3755         u8         reserved_5[0x8];
3756         u8         table_id[0x18];
3757
3758         u8         reserved_6[0x18];
3759         u8         modify_enable_mask[0x8];
3760
3761         u8         reserved_7[0x20];
3762
3763         u8         flow_index[0x20];
3764
3765         u8         reserved_8[0xe0];
3766
3767         struct mlx5_ifc_flow_context_bits flow_context;
3768 };
3769
3770 struct mlx5_ifc_set_driver_version_out_bits {
3771         u8         status[0x8];
3772         u8         reserved_0[0x18];
3773
3774         u8         syndrome[0x20];
3775
3776         u8         reserved_1[0x40];
3777 };
3778
3779 struct mlx5_ifc_set_driver_version_in_bits {
3780         u8         opcode[0x10];
3781         u8         reserved_0[0x10];
3782
3783         u8         reserved_1[0x10];
3784         u8         op_mod[0x10];
3785
3786         u8         reserved_2[0x40];
3787
3788         u8         driver_version[64][0x8];
3789 };
3790
3791 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3792         u8         status[0x8];
3793         u8         reserved_0[0x18];
3794
3795         u8         syndrome[0x20];
3796
3797         u8         reserved_1[0x40];
3798 };
3799
3800 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3801         u8         opcode[0x10];
3802         u8         reserved_0[0x10];
3803
3804         u8         reserved_1[0x10];
3805         u8         op_mod[0x10];
3806
3807         u8         enable[0x1];
3808         u8         reserved_2[0x1f];
3809
3810         u8         reserved_3[0x160];
3811
3812         struct mlx5_ifc_cmd_pas_bits pas;
3813 };
3814
3815 struct mlx5_ifc_set_burst_size_out_bits {
3816         u8         status[0x8];
3817         u8         reserved_0[0x18];
3818
3819         u8         syndrome[0x20];
3820
3821         u8         reserved_1[0x40];
3822 };
3823
3824 struct mlx5_ifc_set_burst_size_in_bits {
3825         u8         opcode[0x10];
3826         u8         reserved_0[0x10];
3827
3828         u8         reserved_1[0x10];
3829         u8         op_mod[0x10];
3830
3831         u8         reserved_2[0x20];
3832
3833         u8         reserved_3[0x9];
3834         u8         device_burst_size[0x17];
3835 };
3836
3837 struct mlx5_ifc_rts2rts_qp_out_bits {
3838         u8         status[0x8];
3839         u8         reserved_0[0x18];
3840
3841         u8         syndrome[0x20];
3842
3843         u8         reserved_1[0x40];
3844 };
3845
3846 struct mlx5_ifc_rts2rts_qp_in_bits {
3847         u8         opcode[0x10];
3848         u8         reserved_0[0x10];
3849
3850         u8         reserved_1[0x10];
3851         u8         op_mod[0x10];
3852
3853         u8         reserved_2[0x8];
3854         u8         qpn[0x18];
3855
3856         u8         reserved_3[0x20];
3857
3858         u8         opt_param_mask[0x20];
3859
3860         u8         reserved_4[0x20];
3861
3862         struct mlx5_ifc_qpc_bits qpc;
3863
3864         u8         reserved_5[0x80];
3865 };
3866
3867 struct mlx5_ifc_rtr2rts_qp_out_bits {
3868         u8         status[0x8];
3869         u8         reserved_0[0x18];
3870
3871         u8         syndrome[0x20];
3872
3873         u8         reserved_1[0x40];
3874 };
3875
3876 struct mlx5_ifc_rtr2rts_qp_in_bits {
3877         u8         opcode[0x10];
3878         u8         reserved_0[0x10];
3879
3880         u8         reserved_1[0x10];
3881         u8         op_mod[0x10];
3882
3883         u8         reserved_2[0x8];
3884         u8         qpn[0x18];
3885
3886         u8         reserved_3[0x20];
3887
3888         u8         opt_param_mask[0x20];
3889
3890         u8         reserved_4[0x20];
3891
3892         struct mlx5_ifc_qpc_bits qpc;
3893
3894         u8         reserved_5[0x80];
3895 };
3896
3897 struct mlx5_ifc_rst2init_qp_out_bits {
3898         u8         status[0x8];
3899         u8         reserved_0[0x18];
3900
3901         u8         syndrome[0x20];
3902
3903         u8         reserved_1[0x40];
3904 };
3905
3906 struct mlx5_ifc_rst2init_qp_in_bits {
3907         u8         opcode[0x10];
3908         u8         reserved_0[0x10];
3909
3910         u8         reserved_1[0x10];
3911         u8         op_mod[0x10];
3912
3913         u8         reserved_2[0x8];
3914         u8         qpn[0x18];
3915
3916         u8         reserved_3[0x20];
3917
3918         u8         opt_param_mask[0x20];
3919
3920         u8         reserved_4[0x20];
3921
3922         struct mlx5_ifc_qpc_bits qpc;
3923
3924         u8         reserved_5[0x80];
3925 };
3926
3927 struct mlx5_ifc_resume_qp_out_bits {
3928         u8         status[0x8];
3929         u8         reserved_0[0x18];
3930
3931         u8         syndrome[0x20];
3932
3933         u8         reserved_1[0x40];
3934 };
3935
3936 struct mlx5_ifc_resume_qp_in_bits {
3937         u8         opcode[0x10];
3938         u8         reserved_0[0x10];
3939
3940         u8         reserved_1[0x10];
3941         u8         op_mod[0x10];
3942
3943         u8         reserved_2[0x8];
3944         u8         qpn[0x18];
3945
3946         u8         reserved_3[0x20];
3947 };
3948
3949 struct mlx5_ifc_query_xrc_srq_out_bits {
3950         u8         status[0x8];
3951         u8         reserved_0[0x18];
3952
3953         u8         syndrome[0x20];
3954
3955         u8         reserved_1[0x40];
3956
3957         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3958
3959         u8         reserved_2[0x600];
3960
3961         u8         pas[0][0x40];
3962 };
3963
3964 struct mlx5_ifc_query_xrc_srq_in_bits {
3965         u8         opcode[0x10];
3966         u8         reserved_0[0x10];
3967
3968         u8         reserved_1[0x10];
3969         u8         op_mod[0x10];
3970
3971         u8         reserved_2[0x8];
3972         u8         xrc_srqn[0x18];
3973
3974         u8         reserved_3[0x20];
3975 };
3976
3977 struct mlx5_ifc_query_wol_rol_out_bits {
3978         u8         status[0x8];
3979         u8         reserved_0[0x18];
3980
3981         u8         syndrome[0x20];
3982
3983         u8         reserved_1[0x10];
3984         u8         rol_mode[0x8];
3985         u8         wol_mode[0x8];
3986
3987         u8         reserved_2[0x20];
3988 };
3989
3990 struct mlx5_ifc_query_wol_rol_in_bits {
3991         u8         opcode[0x10];
3992         u8         reserved_0[0x10];
3993
3994         u8         reserved_1[0x10];
3995         u8         op_mod[0x10];
3996
3997         u8         reserved_2[0x40];
3998 };
3999
4000 enum {
4001         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4002         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4003 };
4004
4005 struct mlx5_ifc_query_vport_state_out_bits {
4006         u8         status[0x8];
4007         u8         reserved_0[0x18];
4008
4009         u8         syndrome[0x20];
4010
4011         u8         reserved_1[0x20];
4012
4013         u8         reserved_2[0x18];
4014         u8         admin_state[0x4];
4015         u8         state[0x4];
4016 };
4017
4018 enum {
4019         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4020         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4021         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4022 };
4023
4024 struct mlx5_ifc_query_vport_state_in_bits {
4025         u8         opcode[0x10];
4026         u8         reserved_0[0x10];
4027
4028         u8         reserved_1[0x10];
4029         u8         op_mod[0x10];
4030
4031         u8         other_vport[0x1];
4032         u8         reserved_2[0xf];
4033         u8         vport_number[0x10];
4034
4035         u8         reserved_3[0x20];
4036 };
4037
4038 struct mlx5_ifc_query_vnic_env_out_bits {
4039         u8         status[0x8];
4040         u8         reserved_at_8[0x18];
4041
4042         u8         syndrome[0x20];
4043
4044         u8         reserved_at_40[0x40];
4045
4046         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4047 };
4048
4049 enum {
4050         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4051 };
4052
4053 struct mlx5_ifc_query_vnic_env_in_bits {
4054         u8         opcode[0x10];
4055         u8         reserved_at_10[0x10];
4056
4057         u8         reserved_at_20[0x10];
4058         u8         op_mod[0x10];
4059
4060         u8         other_vport[0x1];
4061         u8         reserved_at_41[0xf];
4062         u8         vport_number[0x10];
4063
4064         u8         reserved_at_60[0x20];
4065 };
4066
4067 struct mlx5_ifc_query_vport_counter_out_bits {
4068         u8         status[0x8];
4069         u8         reserved_0[0x18];
4070
4071         u8         syndrome[0x20];
4072
4073         u8         reserved_1[0x40];
4074
4075         struct mlx5_ifc_traffic_counter_bits received_errors;
4076
4077         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4078
4079         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4080
4081         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4082
4083         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4084
4085         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4086
4087         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4088
4089         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4090
4091         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4092
4093         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4094
4095         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4096
4097         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4098
4099         u8         reserved_2[0xa00];
4100 };
4101
4102 enum {
4103         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4104 };
4105
4106 struct mlx5_ifc_query_vport_counter_in_bits {
4107         u8         opcode[0x10];
4108         u8         reserved_0[0x10];
4109
4110         u8         reserved_1[0x10];
4111         u8         op_mod[0x10];
4112
4113         u8         other_vport[0x1];
4114         u8         reserved_2[0xb];
4115         u8         port_num[0x4];
4116         u8         vport_number[0x10];
4117
4118         u8         reserved_3[0x60];
4119
4120         u8         clear[0x1];
4121         u8         reserved_4[0x1f];
4122
4123         u8         reserved_5[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_tis_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_0[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_1[0x40];
4133
4134         struct mlx5_ifc_tisc_bits tis_context;
4135 };
4136
4137 struct mlx5_ifc_query_tis_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_0[0x10];
4140
4141         u8         reserved_1[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         reserved_2[0x8];
4145         u8         tisn[0x18];
4146
4147         u8         reserved_3[0x20];
4148 };
4149
4150 struct mlx5_ifc_query_tir_out_bits {
4151         u8         status[0x8];
4152         u8         reserved_0[0x18];
4153
4154         u8         syndrome[0x20];
4155
4156         u8         reserved_1[0xc0];
4157
4158         struct mlx5_ifc_tirc_bits tir_context;
4159 };
4160
4161 struct mlx5_ifc_query_tir_in_bits {
4162         u8         opcode[0x10];
4163         u8         reserved_0[0x10];
4164
4165         u8         reserved_1[0x10];
4166         u8         op_mod[0x10];
4167
4168         u8         reserved_2[0x8];
4169         u8         tirn[0x18];
4170
4171         u8         reserved_3[0x20];
4172 };
4173
4174 struct mlx5_ifc_query_srq_out_bits {
4175         u8         status[0x8];
4176         u8         reserved_0[0x18];
4177
4178         u8         syndrome[0x20];
4179
4180         u8         reserved_1[0x40];
4181
4182         struct mlx5_ifc_srqc_bits srq_context_entry;
4183
4184         u8         reserved_2[0x600];
4185
4186         u8         pas[0][0x40];
4187 };
4188
4189 struct mlx5_ifc_query_srq_in_bits {
4190         u8         opcode[0x10];
4191         u8         reserved_0[0x10];
4192
4193         u8         reserved_1[0x10];
4194         u8         op_mod[0x10];
4195
4196         u8         reserved_2[0x8];
4197         u8         srqn[0x18];
4198
4199         u8         reserved_3[0x20];
4200 };
4201
4202 struct mlx5_ifc_query_sq_out_bits {
4203         u8         status[0x8];
4204         u8         reserved_0[0x18];
4205
4206         u8         syndrome[0x20];
4207
4208         u8         reserved_1[0xc0];
4209
4210         struct mlx5_ifc_sqc_bits sq_context;
4211 };
4212
4213 struct mlx5_ifc_query_sq_in_bits {
4214         u8         opcode[0x10];
4215         u8         reserved_0[0x10];
4216
4217         u8         reserved_1[0x10];
4218         u8         op_mod[0x10];
4219
4220         u8         reserved_2[0x8];
4221         u8         sqn[0x18];
4222
4223         u8         reserved_3[0x20];
4224 };
4225
4226 struct mlx5_ifc_query_special_contexts_out_bits {
4227         u8         status[0x8];
4228         u8         reserved_0[0x18];
4229
4230         u8         syndrome[0x20];
4231
4232         u8         dump_fill_mkey[0x20];
4233
4234         u8         resd_lkey[0x20];
4235 };
4236
4237 struct mlx5_ifc_query_special_contexts_in_bits {
4238         u8         opcode[0x10];
4239         u8         reserved_0[0x10];
4240
4241         u8         reserved_1[0x10];
4242         u8         op_mod[0x10];
4243
4244         u8         reserved_2[0x40];
4245 };
4246
4247 struct mlx5_ifc_query_scheduling_element_out_bits {
4248         u8         status[0x8];
4249         u8         reserved_at_8[0x18];
4250
4251         u8         syndrome[0x20];
4252
4253         u8         reserved_at_40[0xc0];
4254
4255         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4256
4257         u8         reserved_at_300[0x100];
4258 };
4259
4260 enum {
4261         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4262 };
4263
4264 struct mlx5_ifc_query_scheduling_element_in_bits {
4265         u8         opcode[0x10];
4266         u8         reserved_at_10[0x10];
4267
4268         u8         reserved_at_20[0x10];
4269         u8         op_mod[0x10];
4270
4271         u8         scheduling_hierarchy[0x8];
4272         u8         reserved_at_48[0x18];
4273
4274         u8         scheduling_element_id[0x20];
4275
4276         u8         reserved_at_80[0x180];
4277 };
4278
4279 struct mlx5_ifc_query_rqt_out_bits {
4280         u8         status[0x8];
4281         u8         reserved_0[0x18];
4282
4283         u8         syndrome[0x20];
4284
4285         u8         reserved_1[0xc0];
4286
4287         struct mlx5_ifc_rqtc_bits rqt_context;
4288 };
4289
4290 struct mlx5_ifc_query_rqt_in_bits {
4291         u8         opcode[0x10];
4292         u8         reserved_0[0x10];
4293
4294         u8         reserved_1[0x10];
4295         u8         op_mod[0x10];
4296
4297         u8         reserved_2[0x8];
4298         u8         rqtn[0x18];
4299
4300         u8         reserved_3[0x20];
4301 };
4302
4303 struct mlx5_ifc_query_rq_out_bits {
4304         u8         status[0x8];
4305         u8         reserved_0[0x18];
4306
4307         u8         syndrome[0x20];
4308
4309         u8         reserved_1[0xc0];
4310
4311         struct mlx5_ifc_rqc_bits rq_context;
4312 };
4313
4314 struct mlx5_ifc_query_rq_in_bits {
4315         u8         opcode[0x10];
4316         u8         reserved_0[0x10];
4317
4318         u8         reserved_1[0x10];
4319         u8         op_mod[0x10];
4320
4321         u8         reserved_2[0x8];
4322         u8         rqn[0x18];
4323
4324         u8         reserved_3[0x20];
4325 };
4326
4327 struct mlx5_ifc_query_roce_address_out_bits {
4328         u8         status[0x8];
4329         u8         reserved_0[0x18];
4330
4331         u8         syndrome[0x20];
4332
4333         u8         reserved_1[0x40];
4334
4335         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4336 };
4337
4338 struct mlx5_ifc_query_roce_address_in_bits {
4339         u8         opcode[0x10];
4340         u8         reserved_0[0x10];
4341
4342         u8         reserved_1[0x10];
4343         u8         op_mod[0x10];
4344
4345         u8         roce_address_index[0x10];
4346         u8         reserved_2[0x10];
4347
4348         u8         reserved_3[0x20];
4349 };
4350
4351 struct mlx5_ifc_query_rmp_out_bits {
4352         u8         status[0x8];
4353         u8         reserved_0[0x18];
4354
4355         u8         syndrome[0x20];
4356
4357         u8         reserved_1[0xc0];
4358
4359         struct mlx5_ifc_rmpc_bits rmp_context;
4360 };
4361
4362 struct mlx5_ifc_query_rmp_in_bits {
4363         u8         opcode[0x10];
4364         u8         reserved_0[0x10];
4365
4366         u8         reserved_1[0x10];
4367         u8         op_mod[0x10];
4368
4369         u8         reserved_2[0x8];
4370         u8         rmpn[0x18];
4371
4372         u8         reserved_3[0x20];
4373 };
4374
4375 struct mlx5_ifc_query_rdb_out_bits {
4376         u8         status[0x8];
4377         u8         reserved_0[0x18];
4378
4379         u8         syndrome[0x20];
4380
4381         u8         reserved_1[0x20];
4382
4383         u8         reserved_2[0x18];
4384         u8         rdb_list_size[0x8];
4385
4386         struct mlx5_ifc_rdbc_bits rdb_context[0];
4387 };
4388
4389 struct mlx5_ifc_query_rdb_in_bits {
4390         u8         opcode[0x10];
4391         u8         reserved_0[0x10];
4392
4393         u8         reserved_1[0x10];
4394         u8         op_mod[0x10];
4395
4396         u8         reserved_2[0x8];
4397         u8         qpn[0x18];
4398
4399         u8         reserved_3[0x20];
4400 };
4401
4402 struct mlx5_ifc_query_qp_out_bits {
4403         u8         status[0x8];
4404         u8         reserved_0[0x18];
4405
4406         u8         syndrome[0x20];
4407
4408         u8         reserved_1[0x40];
4409
4410         u8         opt_param_mask[0x20];
4411
4412         u8         reserved_2[0x20];
4413
4414         struct mlx5_ifc_qpc_bits qpc;
4415
4416         u8         reserved_3[0x80];
4417
4418         u8         pas[0][0x40];
4419 };
4420
4421 struct mlx5_ifc_query_qp_in_bits {
4422         u8         opcode[0x10];
4423         u8         reserved_0[0x10];
4424
4425         u8         reserved_1[0x10];
4426         u8         op_mod[0x10];
4427
4428         u8         reserved_2[0x8];
4429         u8         qpn[0x18];
4430
4431         u8         reserved_3[0x20];
4432 };
4433
4434 struct mlx5_ifc_query_q_counter_out_bits {
4435         u8         status[0x8];
4436         u8         reserved_0[0x18];
4437
4438         u8         syndrome[0x20];
4439
4440         u8         reserved_1[0x40];
4441
4442         u8         rx_write_requests[0x20];
4443
4444         u8         reserved_2[0x20];
4445
4446         u8         rx_read_requests[0x20];
4447
4448         u8         reserved_3[0x20];
4449
4450         u8         rx_atomic_requests[0x20];
4451
4452         u8         reserved_4[0x20];
4453
4454         u8         rx_dct_connect[0x20];
4455
4456         u8         reserved_5[0x20];
4457
4458         u8         out_of_buffer[0x20];
4459
4460         u8         reserved_7[0x20];
4461
4462         u8         out_of_sequence[0x20];
4463
4464         u8         reserved_8[0x20];
4465
4466         u8         duplicate_request[0x20];
4467
4468         u8         reserved_9[0x20];
4469
4470         u8         rnr_nak_retry_err[0x20];
4471
4472         u8         reserved_10[0x20];
4473
4474         u8         packet_seq_err[0x20];
4475
4476         u8         reserved_11[0x20];
4477
4478         u8         implied_nak_seq_err[0x20];
4479
4480         u8         reserved_12[0x20];
4481
4482         u8         local_ack_timeout_err[0x20];
4483
4484         u8         reserved_13[0x20];
4485
4486         u8         resp_rnr_nak[0x20];
4487
4488         u8         reserved_14[0x20];
4489
4490         u8         req_rnr_retries_exceeded[0x20];
4491
4492         u8         reserved_15[0x460];
4493 };
4494
4495 struct mlx5_ifc_query_q_counter_in_bits {
4496         u8         opcode[0x10];
4497         u8         reserved_0[0x10];
4498
4499         u8         reserved_1[0x10];
4500         u8         op_mod[0x10];
4501
4502         u8         reserved_2[0x80];
4503
4504         u8         clear[0x1];
4505         u8         reserved_3[0x1f];
4506
4507         u8         reserved_4[0x18];
4508         u8         counter_set_id[0x8];
4509 };
4510
4511 struct mlx5_ifc_query_pages_out_bits {
4512         u8         status[0x8];
4513         u8         reserved_0[0x18];
4514
4515         u8         syndrome[0x20];
4516
4517         u8         reserved_1[0x10];
4518         u8         function_id[0x10];
4519
4520         u8         num_pages[0x20];
4521 };
4522
4523 enum {
4524         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4525         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4526         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4527 };
4528
4529 struct mlx5_ifc_query_pages_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_0[0x10];
4532
4533         u8         reserved_1[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         reserved_2[0x10];
4537         u8         function_id[0x10];
4538
4539         u8         reserved_3[0x20];
4540 };
4541
4542 struct mlx5_ifc_query_nic_vport_context_out_bits {
4543         u8         status[0x8];
4544         u8         reserved_0[0x18];
4545
4546         u8         syndrome[0x20];
4547
4548         u8         reserved_1[0x40];
4549
4550         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4551 };
4552
4553 struct mlx5_ifc_query_nic_vport_context_in_bits {
4554         u8         opcode[0x10];
4555         u8         reserved_0[0x10];
4556
4557         u8         reserved_1[0x10];
4558         u8         op_mod[0x10];
4559
4560         u8         other_vport[0x1];
4561         u8         reserved_2[0xf];
4562         u8         vport_number[0x10];
4563
4564         u8         reserved_3[0x5];
4565         u8         allowed_list_type[0x3];
4566         u8         reserved_4[0x18];
4567 };
4568
4569 struct mlx5_ifc_query_mkey_out_bits {
4570         u8         status[0x8];
4571         u8         reserved_0[0x18];
4572
4573         u8         syndrome[0x20];
4574
4575         u8         reserved_1[0x40];
4576
4577         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4578
4579         u8         reserved_2[0x600];
4580
4581         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4582
4583         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4584 };
4585
4586 struct mlx5_ifc_query_mkey_in_bits {
4587         u8         opcode[0x10];
4588         u8         reserved_0[0x10];
4589
4590         u8         reserved_1[0x10];
4591         u8         op_mod[0x10];
4592
4593         u8         reserved_2[0x8];
4594         u8         mkey_index[0x18];
4595
4596         u8         pg_access[0x1];
4597         u8         reserved_3[0x1f];
4598 };
4599
4600 struct mlx5_ifc_query_mad_demux_out_bits {
4601         u8         status[0x8];
4602         u8         reserved_0[0x18];
4603
4604         u8         syndrome[0x20];
4605
4606         u8         reserved_1[0x40];
4607
4608         u8         mad_dumux_parameters_block[0x20];
4609 };
4610
4611 struct mlx5_ifc_query_mad_demux_in_bits {
4612         u8         opcode[0x10];
4613         u8         reserved_0[0x10];
4614
4615         u8         reserved_1[0x10];
4616         u8         op_mod[0x10];
4617
4618         u8         reserved_2[0x40];
4619 };
4620
4621 struct mlx5_ifc_query_l2_table_entry_out_bits {
4622         u8         status[0x8];
4623         u8         reserved_0[0x18];
4624
4625         u8         syndrome[0x20];
4626
4627         u8         reserved_1[0xa0];
4628
4629         u8         reserved_2[0x13];
4630         u8         vlan_valid[0x1];
4631         u8         vlan[0xc];
4632
4633         struct mlx5_ifc_mac_address_layout_bits mac_address;
4634
4635         u8         reserved_3[0xc0];
4636 };
4637
4638 struct mlx5_ifc_query_l2_table_entry_in_bits {
4639         u8         opcode[0x10];
4640         u8         reserved_0[0x10];
4641
4642         u8         reserved_1[0x10];
4643         u8         op_mod[0x10];
4644
4645         u8         reserved_2[0x60];
4646
4647         u8         reserved_3[0x8];
4648         u8         table_index[0x18];
4649
4650         u8         reserved_4[0x140];
4651 };
4652
4653 struct mlx5_ifc_query_issi_out_bits {
4654         u8         status[0x8];
4655         u8         reserved_0[0x18];
4656
4657         u8         syndrome[0x20];
4658
4659         u8         reserved_1[0x10];
4660         u8         current_issi[0x10];
4661
4662         u8         reserved_2[0xa0];
4663
4664         u8         supported_issi_reserved[76][0x8];
4665         u8         supported_issi_dw0[0x20];
4666 };
4667
4668 struct mlx5_ifc_query_issi_in_bits {
4669         u8         opcode[0x10];
4670         u8         reserved_0[0x10];
4671
4672         u8         reserved_1[0x10];
4673         u8         op_mod[0x10];
4674
4675         u8         reserved_2[0x40];
4676 };
4677
4678 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4679         u8         status[0x8];
4680         u8         reserved_0[0x18];
4681
4682         u8         syndrome[0x20];
4683
4684         u8         reserved_1[0x40];
4685
4686         struct mlx5_ifc_pkey_bits pkey[0];
4687 };
4688
4689 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4690         u8         opcode[0x10];
4691         u8         reserved_0[0x10];
4692
4693         u8         reserved_1[0x10];
4694         u8         op_mod[0x10];
4695
4696         u8         other_vport[0x1];
4697         u8         reserved_2[0xb];
4698         u8         port_num[0x4];
4699         u8         vport_number[0x10];
4700
4701         u8         reserved_3[0x10];
4702         u8         pkey_index[0x10];
4703 };
4704
4705 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4706         u8         status[0x8];
4707         u8         reserved_0[0x18];
4708
4709         u8         syndrome[0x20];
4710
4711         u8         reserved_1[0x20];
4712
4713         u8         gids_num[0x10];
4714         u8         reserved_2[0x10];
4715
4716         struct mlx5_ifc_array128_auto_bits gid[0];
4717 };
4718
4719 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4720         u8         opcode[0x10];
4721         u8         reserved_0[0x10];
4722
4723         u8         reserved_1[0x10];
4724         u8         op_mod[0x10];
4725
4726         u8         other_vport[0x1];
4727         u8         reserved_2[0xb];
4728         u8         port_num[0x4];
4729         u8         vport_number[0x10];
4730
4731         u8         reserved_3[0x10];
4732         u8         gid_index[0x10];
4733 };
4734
4735 struct mlx5_ifc_query_hca_vport_context_out_bits {
4736         u8         status[0x8];
4737         u8         reserved_0[0x18];
4738
4739         u8         syndrome[0x20];
4740
4741         u8         reserved_1[0x40];
4742
4743         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4744 };
4745
4746 struct mlx5_ifc_query_hca_vport_context_in_bits {
4747         u8         opcode[0x10];
4748         u8         reserved_0[0x10];
4749
4750         u8         reserved_1[0x10];
4751         u8         op_mod[0x10];
4752
4753         u8         other_vport[0x1];
4754         u8         reserved_2[0xb];
4755         u8         port_num[0x4];
4756         u8         vport_number[0x10];
4757
4758         u8         reserved_3[0x20];
4759 };
4760
4761 struct mlx5_ifc_query_hca_cap_out_bits {
4762         u8         status[0x8];
4763         u8         reserved_0[0x18];
4764
4765         u8         syndrome[0x20];
4766
4767         u8         reserved_1[0x40];
4768
4769         union mlx5_ifc_hca_cap_union_bits capability;
4770 };
4771
4772 struct mlx5_ifc_query_hca_cap_in_bits {
4773         u8         opcode[0x10];
4774         u8         reserved_0[0x10];
4775
4776         u8         reserved_1[0x10];
4777         u8         op_mod[0x10];
4778
4779         u8         reserved_2[0x40];
4780 };
4781
4782 struct mlx5_ifc_query_flow_table_out_bits {
4783         u8         status[0x8];
4784         u8         reserved_at_8[0x18];
4785
4786         u8         syndrome[0x20];
4787
4788         u8         reserved_at_40[0x80];
4789
4790         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4791 };
4792
4793 struct mlx5_ifc_query_flow_table_in_bits {
4794         u8         opcode[0x10];
4795         u8         reserved_0[0x10];
4796
4797         u8         reserved_1[0x10];
4798         u8         op_mod[0x10];
4799
4800         u8         other_vport[0x1];
4801         u8         reserved_2[0xf];
4802         u8         vport_number[0x10];
4803
4804         u8         reserved_3[0x20];
4805
4806         u8         table_type[0x8];
4807         u8         reserved_4[0x18];
4808
4809         u8         reserved_5[0x8];
4810         u8         table_id[0x18];
4811
4812         u8         reserved_6[0x140];
4813 };
4814
4815 struct mlx5_ifc_query_fte_out_bits {
4816         u8         status[0x8];
4817         u8         reserved_0[0x18];
4818
4819         u8         syndrome[0x20];
4820
4821         u8         reserved_1[0x1c0];
4822
4823         struct mlx5_ifc_flow_context_bits flow_context;
4824 };
4825
4826 struct mlx5_ifc_query_fte_in_bits {
4827         u8         opcode[0x10];
4828         u8         reserved_0[0x10];
4829
4830         u8         reserved_1[0x10];
4831         u8         op_mod[0x10];
4832
4833         u8         other_vport[0x1];
4834         u8         reserved_2[0xf];
4835         u8         vport_number[0x10];
4836
4837         u8         reserved_3[0x20];
4838
4839         u8         table_type[0x8];
4840         u8         reserved_4[0x18];
4841
4842         u8         reserved_5[0x8];
4843         u8         table_id[0x18];
4844
4845         u8         reserved_6[0x40];
4846
4847         u8         flow_index[0x20];
4848
4849         u8         reserved_7[0xe0];
4850 };
4851
4852 enum {
4853         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4854         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4855         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4856 };
4857
4858 struct mlx5_ifc_query_flow_group_out_bits {
4859         u8         status[0x8];
4860         u8         reserved_0[0x18];
4861
4862         u8         syndrome[0x20];
4863
4864         u8         reserved_1[0xa0];
4865
4866         u8         start_flow_index[0x20];
4867
4868         u8         reserved_2[0x20];
4869
4870         u8         end_flow_index[0x20];
4871
4872         u8         reserved_3[0xa0];
4873
4874         u8         reserved_4[0x18];
4875         u8         match_criteria_enable[0x8];
4876
4877         struct mlx5_ifc_fte_match_param_bits match_criteria;
4878
4879         u8         reserved_5[0xe00];
4880 };
4881
4882 struct mlx5_ifc_query_flow_group_in_bits {
4883         u8         opcode[0x10];
4884         u8         reserved_0[0x10];
4885
4886         u8         reserved_1[0x10];
4887         u8         op_mod[0x10];
4888
4889         u8         other_vport[0x1];
4890         u8         reserved_2[0xf];
4891         u8         vport_number[0x10];
4892
4893         u8         reserved_3[0x20];
4894
4895         u8         table_type[0x8];
4896         u8         reserved_4[0x18];
4897
4898         u8         reserved_5[0x8];
4899         u8         table_id[0x18];
4900
4901         u8         group_id[0x20];
4902
4903         u8         reserved_6[0x120];
4904 };
4905
4906 struct mlx5_ifc_query_flow_counter_out_bits {
4907         u8         status[0x8];
4908         u8         reserved_at_8[0x18];
4909
4910         u8         syndrome[0x20];
4911
4912         u8         reserved_at_40[0x40];
4913
4914         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4915 };
4916
4917 struct mlx5_ifc_query_flow_counter_in_bits {
4918         u8         opcode[0x10];
4919         u8         reserved_at_10[0x10];
4920
4921         u8         reserved_at_20[0x10];
4922         u8         op_mod[0x10];
4923
4924         u8         reserved_at_40[0x80];
4925
4926         u8         clear[0x1];
4927         u8         reserved_at_c1[0xf];
4928         u8         num_of_counters[0x10];
4929
4930         u8         reserved_at_e0[0x10];
4931         u8         flow_counter_id[0x10];
4932 };
4933
4934 struct mlx5_ifc_query_esw_vport_context_out_bits {
4935         u8         status[0x8];
4936         u8         reserved_0[0x18];
4937
4938         u8         syndrome[0x20];
4939
4940         u8         reserved_1[0x40];
4941
4942         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4943 };
4944
4945 struct mlx5_ifc_query_esw_vport_context_in_bits {
4946         u8         opcode[0x10];
4947         u8         reserved_0[0x10];
4948
4949         u8         reserved_1[0x10];
4950         u8         op_mod[0x10];
4951
4952         u8         other_vport[0x1];
4953         u8         reserved_2[0xf];
4954         u8         vport_number[0x10];
4955
4956         u8         reserved_3[0x20];
4957 };
4958
4959 struct mlx5_ifc_query_eq_out_bits {
4960         u8         status[0x8];
4961         u8         reserved_0[0x18];
4962
4963         u8         syndrome[0x20];
4964
4965         u8         reserved_1[0x40];
4966
4967         struct mlx5_ifc_eqc_bits eq_context_entry;
4968
4969         u8         reserved_2[0x40];
4970
4971         u8         event_bitmask[0x40];
4972
4973         u8         reserved_3[0x580];
4974
4975         u8         pas[0][0x40];
4976 };
4977
4978 struct mlx5_ifc_query_eq_in_bits {
4979         u8         opcode[0x10];
4980         u8         reserved_0[0x10];
4981
4982         u8         reserved_1[0x10];
4983         u8         op_mod[0x10];
4984
4985         u8         reserved_2[0x18];
4986         u8         eq_number[0x8];
4987
4988         u8         reserved_3[0x20];
4989 };
4990
4991 struct mlx5_ifc_query_dct_out_bits {
4992         u8         status[0x8];
4993         u8         reserved_0[0x18];
4994
4995         u8         syndrome[0x20];
4996
4997         u8         reserved_1[0x40];
4998
4999         struct mlx5_ifc_dctc_bits dct_context_entry;
5000
5001         u8         reserved_2[0x180];
5002 };
5003
5004 struct mlx5_ifc_query_dct_in_bits {
5005         u8         opcode[0x10];
5006         u8         reserved_0[0x10];
5007
5008         u8         reserved_1[0x10];
5009         u8         op_mod[0x10];
5010
5011         u8         reserved_2[0x8];
5012         u8         dctn[0x18];
5013
5014         u8         reserved_3[0x20];
5015 };
5016
5017 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5018         u8         status[0x8];
5019         u8         reserved_0[0x18];
5020
5021         u8         syndrome[0x20];
5022
5023         u8         enable[0x1];
5024         u8         reserved_1[0x1f];
5025
5026         u8         reserved_2[0x160];
5027
5028         struct mlx5_ifc_cmd_pas_bits pas;
5029 };
5030
5031 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5032         u8         opcode[0x10];
5033         u8         reserved_0[0x10];
5034
5035         u8         reserved_1[0x10];
5036         u8         op_mod[0x10];
5037
5038         u8         reserved_2[0x40];
5039 };
5040
5041 struct mlx5_ifc_query_cq_out_bits {
5042         u8         status[0x8];
5043         u8         reserved_0[0x18];
5044
5045         u8         syndrome[0x20];
5046
5047         u8         reserved_1[0x40];
5048
5049         struct mlx5_ifc_cqc_bits cq_context;
5050
5051         u8         reserved_2[0x600];
5052
5053         u8         pas[0][0x40];
5054 };
5055
5056 struct mlx5_ifc_query_cq_in_bits {
5057         u8         opcode[0x10];
5058         u8         reserved_0[0x10];
5059
5060         u8         reserved_1[0x10];
5061         u8         op_mod[0x10];
5062
5063         u8         reserved_2[0x8];
5064         u8         cqn[0x18];
5065
5066         u8         reserved_3[0x20];
5067 };
5068
5069 struct mlx5_ifc_query_cong_status_out_bits {
5070         u8         status[0x8];
5071         u8         reserved_0[0x18];
5072
5073         u8         syndrome[0x20];
5074
5075         u8         reserved_1[0x20];
5076
5077         u8         enable[0x1];
5078         u8         tag_enable[0x1];
5079         u8         reserved_2[0x1e];
5080 };
5081
5082 struct mlx5_ifc_query_cong_status_in_bits {
5083         u8         opcode[0x10];
5084         u8         reserved_0[0x10];
5085
5086         u8         reserved_1[0x10];
5087         u8         op_mod[0x10];
5088
5089         u8         reserved_2[0x18];
5090         u8         priority[0x4];
5091         u8         cong_protocol[0x4];
5092
5093         u8         reserved_3[0x20];
5094 };
5095
5096 struct mlx5_ifc_query_cong_statistics_out_bits {
5097         u8         status[0x8];
5098         u8         reserved_0[0x18];
5099
5100         u8         syndrome[0x20];
5101
5102         u8         reserved_1[0x40];
5103
5104         u8         rp_cur_flows[0x20];
5105
5106         u8         sum_flows[0x20];
5107
5108         u8         rp_cnp_ignored_high[0x20];
5109
5110         u8         rp_cnp_ignored_low[0x20];
5111
5112         u8         rp_cnp_handled_high[0x20];
5113
5114         u8         rp_cnp_handled_low[0x20];
5115
5116         u8         reserved_2[0x100];
5117
5118         u8         time_stamp_high[0x20];
5119
5120         u8         time_stamp_low[0x20];
5121
5122         u8         accumulators_period[0x20];
5123
5124         u8         np_ecn_marked_roce_packets_high[0x20];
5125
5126         u8         np_ecn_marked_roce_packets_low[0x20];
5127
5128         u8         np_cnp_sent_high[0x20];
5129
5130         u8         np_cnp_sent_low[0x20];
5131
5132         u8         reserved_3[0x560];
5133 };
5134
5135 struct mlx5_ifc_query_cong_statistics_in_bits {
5136         u8         opcode[0x10];
5137         u8         reserved_0[0x10];
5138
5139         u8         reserved_1[0x10];
5140         u8         op_mod[0x10];
5141
5142         u8         clear[0x1];
5143         u8         reserved_2[0x1f];
5144
5145         u8         reserved_3[0x20];
5146 };
5147
5148 struct mlx5_ifc_query_cong_params_out_bits {
5149         u8         status[0x8];
5150         u8         reserved_0[0x18];
5151
5152         u8         syndrome[0x20];
5153
5154         u8         reserved_1[0x40];
5155
5156         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5157 };
5158
5159 struct mlx5_ifc_query_cong_params_in_bits {
5160         u8         opcode[0x10];
5161         u8         reserved_0[0x10];
5162
5163         u8         reserved_1[0x10];
5164         u8         op_mod[0x10];
5165
5166         u8         reserved_2[0x1c];
5167         u8         cong_protocol[0x4];
5168
5169         u8         reserved_3[0x20];
5170 };
5171
5172 struct mlx5_ifc_query_burst_size_out_bits {
5173         u8         status[0x8];
5174         u8         reserved_0[0x18];
5175
5176         u8         syndrome[0x20];
5177
5178         u8         reserved_1[0x20];
5179
5180         u8         reserved_2[0x9];
5181         u8         device_burst_size[0x17];
5182 };
5183
5184 struct mlx5_ifc_query_burst_size_in_bits {
5185         u8         opcode[0x10];
5186         u8         reserved_0[0x10];
5187
5188         u8         reserved_1[0x10];
5189         u8         op_mod[0x10];
5190
5191         u8         reserved_2[0x40];
5192 };
5193
5194 struct mlx5_ifc_query_adapter_out_bits {
5195         u8         status[0x8];
5196         u8         reserved_0[0x18];
5197
5198         u8         syndrome[0x20];
5199
5200         u8         reserved_1[0x40];
5201
5202         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5203 };
5204
5205 struct mlx5_ifc_query_adapter_in_bits {
5206         u8         opcode[0x10];
5207         u8         reserved_0[0x10];
5208
5209         u8         reserved_1[0x10];
5210         u8         op_mod[0x10];
5211
5212         u8         reserved_2[0x40];
5213 };
5214
5215 struct mlx5_ifc_qp_2rst_out_bits {
5216         u8         status[0x8];
5217         u8         reserved_0[0x18];
5218
5219         u8         syndrome[0x20];
5220
5221         u8         reserved_1[0x40];
5222 };
5223
5224 struct mlx5_ifc_qp_2rst_in_bits {
5225         u8         opcode[0x10];
5226         u8         reserved_0[0x10];
5227
5228         u8         reserved_1[0x10];
5229         u8         op_mod[0x10];
5230
5231         u8         reserved_2[0x8];
5232         u8         qpn[0x18];
5233
5234         u8         reserved_3[0x20];
5235 };
5236
5237 struct mlx5_ifc_qp_2err_out_bits {
5238         u8         status[0x8];
5239         u8         reserved_0[0x18];
5240
5241         u8         syndrome[0x20];
5242
5243         u8         reserved_1[0x40];
5244 };
5245
5246 struct mlx5_ifc_qp_2err_in_bits {
5247         u8         opcode[0x10];
5248         u8         reserved_0[0x10];
5249
5250         u8         reserved_1[0x10];
5251         u8         op_mod[0x10];
5252
5253         u8         reserved_2[0x8];
5254         u8         qpn[0x18];
5255
5256         u8         reserved_3[0x20];
5257 };
5258
5259 struct mlx5_ifc_para_vport_element_bits {
5260         u8         reserved_at_0[0xc];
5261         u8         traffic_class[0x4];
5262         u8         qos_para_vport_number[0x10];
5263 };
5264
5265 struct mlx5_ifc_page_fault_resume_out_bits {
5266         u8         status[0x8];
5267         u8         reserved_0[0x18];
5268
5269         u8         syndrome[0x20];
5270
5271         u8         reserved_1[0x40];
5272 };
5273
5274 struct mlx5_ifc_page_fault_resume_in_bits {
5275         u8         opcode[0x10];
5276         u8         reserved_0[0x10];
5277
5278         u8         reserved_1[0x10];
5279         u8         op_mod[0x10];
5280
5281         u8         error[0x1];
5282         u8         reserved_2[0x4];
5283         u8         rdma[0x1];
5284         u8         read_write[0x1];
5285         u8         req_res[0x1];
5286         u8         qpn[0x18];
5287
5288         u8         reserved_3[0x20];
5289 };
5290
5291 struct mlx5_ifc_nop_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_0[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_1[0x40];
5298 };
5299
5300 struct mlx5_ifc_nop_in_bits {
5301         u8         opcode[0x10];
5302         u8         reserved_0[0x10];
5303
5304         u8         reserved_1[0x10];
5305         u8         op_mod[0x10];
5306
5307         u8         reserved_2[0x40];
5308 };
5309
5310 struct mlx5_ifc_modify_vport_state_out_bits {
5311         u8         status[0x8];
5312         u8         reserved_0[0x18];
5313
5314         u8         syndrome[0x20];
5315
5316         u8         reserved_1[0x40];
5317 };
5318
5319 enum {
5320         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5321         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5322         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5323 };
5324
5325 enum {
5326         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5327         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5328         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5329 };
5330
5331 struct mlx5_ifc_modify_vport_state_in_bits {
5332         u8         opcode[0x10];
5333         u8         reserved_0[0x10];
5334
5335         u8         reserved_1[0x10];
5336         u8         op_mod[0x10];
5337
5338         u8         other_vport[0x1];
5339         u8         reserved_2[0xf];
5340         u8         vport_number[0x10];
5341
5342         u8         reserved_3[0x18];
5343         u8         admin_state[0x4];
5344         u8         reserved_4[0x4];
5345 };
5346
5347 struct mlx5_ifc_modify_tis_out_bits {
5348         u8         status[0x8];
5349         u8         reserved_0[0x18];
5350
5351         u8         syndrome[0x20];
5352
5353         u8         reserved_1[0x40];
5354 };
5355
5356 struct mlx5_ifc_modify_tis_bitmask_bits {
5357         u8         reserved_at_0[0x20];
5358
5359         u8         reserved_at_20[0x1d];
5360         u8         lag_tx_port_affinity[0x1];
5361         u8         strict_lag_tx_port_affinity[0x1];
5362         u8         prio[0x1];
5363 };
5364
5365 struct mlx5_ifc_modify_tis_in_bits {
5366         u8         opcode[0x10];
5367         u8         reserved_0[0x10];
5368
5369         u8         reserved_1[0x10];
5370         u8         op_mod[0x10];
5371
5372         u8         reserved_2[0x8];
5373         u8         tisn[0x18];
5374
5375         u8         reserved_3[0x20];
5376
5377         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5378
5379         u8         reserved_4[0x40];
5380
5381         struct mlx5_ifc_tisc_bits ctx;
5382 };
5383
5384 struct mlx5_ifc_modify_tir_out_bits {
5385         u8         status[0x8];
5386         u8         reserved_0[0x18];
5387
5388         u8         syndrome[0x20];
5389
5390         u8         reserved_1[0x40];
5391 };
5392
5393 enum
5394 {
5395         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5396         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5397 };
5398
5399 struct mlx5_ifc_modify_tir_in_bits {
5400         u8         opcode[0x10];
5401         u8         reserved_0[0x10];
5402
5403         u8         reserved_1[0x10];
5404         u8         op_mod[0x10];
5405
5406         u8         reserved_2[0x8];
5407         u8         tirn[0x18];
5408
5409         u8         reserved_3[0x20];
5410
5411         u8         modify_bitmask[0x40];
5412
5413         u8         reserved_4[0x40];
5414
5415         struct mlx5_ifc_tirc_bits tir_context;
5416 };
5417
5418 struct mlx5_ifc_modify_sq_out_bits {
5419         u8         status[0x8];
5420         u8         reserved_0[0x18];
5421
5422         u8         syndrome[0x20];
5423
5424         u8         reserved_1[0x40];
5425 };
5426
5427 struct mlx5_ifc_modify_sq_in_bits {
5428         u8         opcode[0x10];
5429         u8         reserved_0[0x10];
5430
5431         u8         reserved_1[0x10];
5432         u8         op_mod[0x10];
5433
5434         u8         sq_state[0x4];
5435         u8         reserved_2[0x4];
5436         u8         sqn[0x18];
5437
5438         u8         reserved_3[0x20];
5439
5440         u8         modify_bitmask[0x40];
5441
5442         u8         reserved_4[0x40];
5443
5444         struct mlx5_ifc_sqc_bits ctx;
5445 };
5446
5447 struct mlx5_ifc_modify_scheduling_element_out_bits {
5448         u8         status[0x8];
5449         u8         reserved_at_8[0x18];
5450
5451         u8         syndrome[0x20];
5452
5453         u8         reserved_at_40[0x1c0];
5454 };
5455
5456 enum {
5457         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5458 };
5459
5460 enum {
5461         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5462         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5463 };
5464
5465 struct mlx5_ifc_modify_scheduling_element_in_bits {
5466         u8         opcode[0x10];
5467         u8         reserved_at_10[0x10];
5468
5469         u8         reserved_at_20[0x10];
5470         u8         op_mod[0x10];
5471
5472         u8         scheduling_hierarchy[0x8];
5473         u8         reserved_at_48[0x18];
5474
5475         u8         scheduling_element_id[0x20];
5476
5477         u8         reserved_at_80[0x20];
5478
5479         u8         modify_bitmask[0x20];
5480
5481         u8         reserved_at_c0[0x40];
5482
5483         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5484
5485         u8         reserved_at_300[0x100];
5486 };
5487
5488 struct mlx5_ifc_modify_rqt_out_bits {
5489         u8         status[0x8];
5490         u8         reserved_0[0x18];
5491
5492         u8         syndrome[0x20];
5493
5494         u8         reserved_1[0x40];
5495 };
5496
5497 struct mlx5_ifc_modify_rqt_in_bits {
5498         u8         opcode[0x10];
5499         u8         reserved_0[0x10];
5500
5501         u8         reserved_1[0x10];
5502         u8         op_mod[0x10];
5503
5504         u8         reserved_2[0x8];
5505         u8         rqtn[0x18];
5506
5507         u8         reserved_3[0x20];
5508
5509         u8         modify_bitmask[0x40];
5510
5511         u8         reserved_4[0x40];
5512
5513         struct mlx5_ifc_rqtc_bits ctx;
5514 };
5515
5516 struct mlx5_ifc_modify_rq_out_bits {
5517         u8         status[0x8];
5518         u8         reserved_0[0x18];
5519
5520         u8         syndrome[0x20];
5521
5522         u8         reserved_1[0x40];
5523 };
5524
5525 enum {
5526         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5527         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5528 };
5529
5530 struct mlx5_ifc_modify_rq_in_bits {
5531         u8         opcode[0x10];
5532         u8         reserved_0[0x10];
5533
5534         u8         reserved_1[0x10];
5535         u8         op_mod[0x10];
5536
5537         u8         rq_state[0x4];
5538         u8         reserved_2[0x4];
5539         u8         rqn[0x18];
5540
5541         u8         reserved_3[0x20];
5542
5543         u8         modify_bitmask[0x40];
5544
5545         u8         reserved_4[0x40];
5546
5547         struct mlx5_ifc_rqc_bits ctx;
5548 };
5549
5550 struct mlx5_ifc_modify_rmp_out_bits {
5551         u8         status[0x8];
5552         u8         reserved_0[0x18];
5553
5554         u8         syndrome[0x20];
5555
5556         u8         reserved_1[0x40];
5557 };
5558
5559 struct mlx5_ifc_rmp_bitmask_bits {
5560         u8         reserved[0x20];
5561
5562         u8         reserved1[0x1f];
5563         u8         lwm[0x1];
5564 };
5565
5566 struct mlx5_ifc_modify_rmp_in_bits {
5567         u8         opcode[0x10];
5568         u8         reserved_0[0x10];
5569
5570         u8         reserved_1[0x10];
5571         u8         op_mod[0x10];
5572
5573         u8         rmp_state[0x4];
5574         u8         reserved_2[0x4];
5575         u8         rmpn[0x18];
5576
5577         u8         reserved_3[0x20];
5578
5579         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5580
5581         u8         reserved_4[0x40];
5582
5583         struct mlx5_ifc_rmpc_bits ctx;
5584 };
5585
5586 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5587         u8         status[0x8];
5588         u8         reserved_0[0x18];
5589
5590         u8         syndrome[0x20];
5591
5592         u8         reserved_1[0x40];
5593 };
5594
5595 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5596         u8         reserved_0[0x14];
5597         u8         disable_uc_local_lb[0x1];
5598         u8         disable_mc_local_lb[0x1];
5599         u8         node_guid[0x1];
5600         u8         port_guid[0x1];
5601         u8         min_wqe_inline_mode[0x1];
5602         u8         mtu[0x1];
5603         u8         change_event[0x1];
5604         u8         promisc[0x1];
5605         u8         permanent_address[0x1];
5606         u8         addresses_list[0x1];
5607         u8         roce_en[0x1];
5608         u8         reserved_1[0x1];
5609 };
5610
5611 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5612         u8         opcode[0x10];
5613         u8         reserved_0[0x10];
5614
5615         u8         reserved_1[0x10];
5616         u8         op_mod[0x10];
5617
5618         u8         other_vport[0x1];
5619         u8         reserved_2[0xf];
5620         u8         vport_number[0x10];
5621
5622         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5623
5624         u8         reserved_3[0x780];
5625
5626         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5627 };
5628
5629 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_0[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_1[0x40];
5636 };
5637
5638 struct mlx5_ifc_grh_bits {
5639         u8      ip_version[4];
5640         u8      traffic_class[8];
5641         u8      flow_label[20];
5642         u8      payload_length[16];
5643         u8      next_header[8];
5644         u8      hop_limit[8];
5645         u8      sgid[128];
5646         u8      dgid[128];
5647 };
5648
5649 struct mlx5_ifc_bth_bits {
5650         u8      opcode[8];
5651         u8      se[1];
5652         u8      migreq[1];
5653         u8      pad_count[2];
5654         u8      tver[4];
5655         u8      p_key[16];
5656         u8      reserved8[8];
5657         u8      dest_qp[24];
5658         u8      ack_req[1];
5659         u8      reserved7[7];
5660         u8      psn[24];
5661 };
5662
5663 struct mlx5_ifc_aeth_bits {
5664         u8      syndrome[8];
5665         u8      msn[24];
5666 };
5667
5668 struct mlx5_ifc_dceth_bits {
5669         u8      reserved0[8];
5670         u8      session_id[24];
5671         u8      reserved1[8];
5672         u8      dci_dct[24];
5673 };
5674
5675 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5676         u8         opcode[0x10];
5677         u8         reserved_0[0x10];
5678
5679         u8         reserved_1[0x10];
5680         u8         op_mod[0x10];
5681
5682         u8         other_vport[0x1];
5683         u8         reserved_2[0xb];
5684         u8         port_num[0x4];
5685         u8         vport_number[0x10];
5686
5687         u8         reserved_3[0x20];
5688
5689         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5690 };
5691
5692 struct mlx5_ifc_modify_flow_table_out_bits {
5693         u8         status[0x8];
5694         u8         reserved_at_8[0x18];
5695
5696         u8         syndrome[0x20];
5697
5698         u8         reserved_at_40[0x40];
5699 };
5700
5701 enum {
5702         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5703         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5704 };
5705
5706 struct mlx5_ifc_modify_flow_table_in_bits {
5707         u8         opcode[0x10];
5708         u8         reserved_at_10[0x10];
5709
5710         u8         reserved_at_20[0x10];
5711         u8         op_mod[0x10];
5712
5713         u8         other_vport[0x1];
5714         u8         reserved_at_41[0xf];
5715         u8         vport_number[0x10];
5716
5717         u8         reserved_at_60[0x10];
5718         u8         modify_field_select[0x10];
5719
5720         u8         table_type[0x8];
5721         u8         reserved_at_88[0x18];
5722
5723         u8         reserved_at_a0[0x8];
5724         u8         table_id[0x18];
5725
5726         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5727 };
5728
5729 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5730         u8         status[0x8];
5731         u8         reserved_0[0x18];
5732
5733         u8         syndrome[0x20];
5734
5735         u8         reserved_1[0x40];
5736 };
5737
5738 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5739         u8         reserved[0x1c];
5740         u8         vport_cvlan_insert[0x1];
5741         u8         vport_svlan_insert[0x1];
5742         u8         vport_cvlan_strip[0x1];
5743         u8         vport_svlan_strip[0x1];
5744 };
5745
5746 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5747         u8         opcode[0x10];
5748         u8         reserved_0[0x10];
5749
5750         u8         reserved_1[0x10];
5751         u8         op_mod[0x10];
5752
5753         u8         other_vport[0x1];
5754         u8         reserved_2[0xf];
5755         u8         vport_number[0x10];
5756
5757         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5758
5759         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5760 };
5761
5762 struct mlx5_ifc_modify_cq_out_bits {
5763         u8         status[0x8];
5764         u8         reserved_0[0x18];
5765
5766         u8         syndrome[0x20];
5767
5768         u8         reserved_1[0x40];
5769 };
5770
5771 enum {
5772         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5773         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5774 };
5775
5776 struct mlx5_ifc_modify_cq_in_bits {
5777         u8         opcode[0x10];
5778         u8         reserved_0[0x10];
5779
5780         u8         reserved_1[0x10];
5781         u8         op_mod[0x10];
5782
5783         u8         reserved_2[0x8];
5784         u8         cqn[0x18];
5785
5786         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5787
5788         struct mlx5_ifc_cqc_bits cq_context;
5789
5790         u8         reserved_3[0x600];
5791
5792         u8         pas[0][0x40];
5793 };
5794
5795 struct mlx5_ifc_modify_cong_status_out_bits {
5796         u8         status[0x8];
5797         u8         reserved_0[0x18];
5798
5799         u8         syndrome[0x20];
5800
5801         u8         reserved_1[0x40];
5802 };
5803
5804 struct mlx5_ifc_modify_cong_status_in_bits {
5805         u8         opcode[0x10];
5806         u8         reserved_0[0x10];
5807
5808         u8         reserved_1[0x10];
5809         u8         op_mod[0x10];
5810
5811         u8         reserved_2[0x18];
5812         u8         priority[0x4];
5813         u8         cong_protocol[0x4];
5814
5815         u8         enable[0x1];
5816         u8         tag_enable[0x1];
5817         u8         reserved_3[0x1e];
5818 };
5819
5820 struct mlx5_ifc_modify_cong_params_out_bits {
5821         u8         status[0x8];
5822         u8         reserved_0[0x18];
5823
5824         u8         syndrome[0x20];
5825
5826         u8         reserved_1[0x40];
5827 };
5828
5829 struct mlx5_ifc_modify_cong_params_in_bits {
5830         u8         opcode[0x10];
5831         u8         reserved_0[0x10];
5832
5833         u8         reserved_1[0x10];
5834         u8         op_mod[0x10];
5835
5836         u8         reserved_2[0x1c];
5837         u8         cong_protocol[0x4];
5838
5839         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5840
5841         u8         reserved_3[0x80];
5842
5843         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5844 };
5845
5846 struct mlx5_ifc_manage_pages_out_bits {
5847         u8         status[0x8];
5848         u8         reserved_0[0x18];
5849
5850         u8         syndrome[0x20];
5851
5852         u8         output_num_entries[0x20];
5853
5854         u8         reserved_1[0x20];
5855
5856         u8         pas[0][0x40];
5857 };
5858
5859 enum {
5860         MLX5_PAGES_CANT_GIVE                            = 0x0,
5861         MLX5_PAGES_GIVE                                 = 0x1,
5862         MLX5_PAGES_TAKE                                 = 0x2,
5863 };
5864
5865 struct mlx5_ifc_manage_pages_in_bits {
5866         u8         opcode[0x10];
5867         u8         reserved_0[0x10];
5868
5869         u8         reserved_1[0x10];
5870         u8         op_mod[0x10];
5871
5872         u8         reserved_2[0x10];
5873         u8         function_id[0x10];
5874
5875         u8         input_num_entries[0x20];
5876
5877         u8         pas[0][0x40];
5878 };
5879
5880 struct mlx5_ifc_mad_ifc_out_bits {
5881         u8         status[0x8];
5882         u8         reserved_0[0x18];
5883
5884         u8         syndrome[0x20];
5885
5886         u8         reserved_1[0x40];
5887
5888         u8         response_mad_packet[256][0x8];
5889 };
5890
5891 struct mlx5_ifc_mad_ifc_in_bits {
5892         u8         opcode[0x10];
5893         u8         reserved_0[0x10];
5894
5895         u8         reserved_1[0x10];
5896         u8         op_mod[0x10];
5897
5898         u8         remote_lid[0x10];
5899         u8         reserved_2[0x8];
5900         u8         port[0x8];
5901
5902         u8         reserved_3[0x20];
5903
5904         u8         mad[256][0x8];
5905 };
5906
5907 struct mlx5_ifc_init_hca_out_bits {
5908         u8         status[0x8];
5909         u8         reserved_0[0x18];
5910
5911         u8         syndrome[0x20];
5912
5913         u8         reserved_1[0x40];
5914 };
5915
5916 enum {
5917         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5918         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5919 };
5920
5921 struct mlx5_ifc_init_hca_in_bits {
5922         u8         opcode[0x10];
5923         u8         reserved_0[0x10];
5924
5925         u8         reserved_1[0x10];
5926         u8         op_mod[0x10];
5927
5928         u8         reserved_2[0x40];
5929 };
5930
5931 struct mlx5_ifc_init2rtr_qp_out_bits {
5932         u8         status[0x8];
5933         u8         reserved_0[0x18];
5934
5935         u8         syndrome[0x20];
5936
5937         u8         reserved_1[0x40];
5938 };
5939
5940 struct mlx5_ifc_init2rtr_qp_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_0[0x10];
5943
5944         u8         reserved_1[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         reserved_2[0x8];
5948         u8         qpn[0x18];
5949
5950         u8         reserved_3[0x20];
5951
5952         u8         opt_param_mask[0x20];
5953
5954         u8         reserved_4[0x20];
5955
5956         struct mlx5_ifc_qpc_bits qpc;
5957
5958         u8         reserved_5[0x80];
5959 };
5960
5961 struct mlx5_ifc_init2init_qp_out_bits {
5962         u8         status[0x8];
5963         u8         reserved_0[0x18];
5964
5965         u8         syndrome[0x20];
5966
5967         u8         reserved_1[0x40];
5968 };
5969
5970 struct mlx5_ifc_init2init_qp_in_bits {
5971         u8         opcode[0x10];
5972         u8         reserved_0[0x10];
5973
5974         u8         reserved_1[0x10];
5975         u8         op_mod[0x10];
5976
5977         u8         reserved_2[0x8];
5978         u8         qpn[0x18];
5979
5980         u8         reserved_3[0x20];
5981
5982         u8         opt_param_mask[0x20];
5983
5984         u8         reserved_4[0x20];
5985
5986         struct mlx5_ifc_qpc_bits qpc;
5987
5988         u8         reserved_5[0x80];
5989 };
5990
5991 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5992         u8         status[0x8];
5993         u8         reserved_0[0x18];
5994
5995         u8         syndrome[0x20];
5996
5997         u8         reserved_1[0x40];
5998
5999         u8         packet_headers_log[128][0x8];
6000
6001         u8         packet_syndrome[64][0x8];
6002 };
6003
6004 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6005         u8         opcode[0x10];
6006         u8         reserved_0[0x10];
6007
6008         u8         reserved_1[0x10];
6009         u8         op_mod[0x10];
6010
6011         u8         reserved_2[0x40];
6012 };
6013
6014 struct mlx5_ifc_encryption_key_obj_bits {
6015         u8         modify_field_select[0x40];
6016
6017         u8         reserved_at_40[0x14];
6018         u8         key_size[0x4];
6019         u8         reserved_at_58[0x4];
6020         u8         key_type[0x4];
6021
6022         u8         reserved_at_60[0x8];
6023         u8         pd[0x18];
6024
6025         u8         reserved_at_80[0x180];
6026
6027         u8         key[8][0x20];
6028
6029         u8         reserved_at_300[0x500];
6030 };
6031
6032 struct mlx5_ifc_gen_eqe_in_bits {
6033         u8         opcode[0x10];
6034         u8         reserved_0[0x10];
6035
6036         u8         reserved_1[0x10];
6037         u8         op_mod[0x10];
6038
6039         u8         reserved_2[0x18];
6040         u8         eq_number[0x8];
6041
6042         u8         reserved_3[0x20];
6043
6044         u8         eqe[64][0x8];
6045 };
6046
6047 struct mlx5_ifc_gen_eq_out_bits {
6048         u8         status[0x8];
6049         u8         reserved_0[0x18];
6050
6051         u8         syndrome[0x20];
6052
6053         u8         reserved_1[0x40];
6054 };
6055
6056 struct mlx5_ifc_enable_hca_out_bits {
6057         u8         status[0x8];
6058         u8         reserved_0[0x18];
6059
6060         u8         syndrome[0x20];
6061
6062         u8         reserved_1[0x20];
6063 };
6064
6065 struct mlx5_ifc_enable_hca_in_bits {
6066         u8         opcode[0x10];
6067         u8         reserved_0[0x10];
6068
6069         u8         reserved_1[0x10];
6070         u8         op_mod[0x10];
6071
6072         u8         reserved_2[0x10];
6073         u8         function_id[0x10];
6074
6075         u8         reserved_3[0x20];
6076 };
6077
6078 struct mlx5_ifc_drain_dct_out_bits {
6079         u8         status[0x8];
6080         u8         reserved_0[0x18];
6081
6082         u8         syndrome[0x20];
6083
6084         u8         reserved_1[0x40];
6085 };
6086
6087 struct mlx5_ifc_drain_dct_in_bits {
6088         u8         opcode[0x10];
6089         u8         reserved_0[0x10];
6090
6091         u8         reserved_1[0x10];
6092         u8         op_mod[0x10];
6093
6094         u8         reserved_2[0x8];
6095         u8         dctn[0x18];
6096
6097         u8         reserved_3[0x20];
6098 };
6099
6100 struct mlx5_ifc_disable_hca_out_bits {
6101         u8         status[0x8];
6102         u8         reserved_0[0x18];
6103
6104         u8         syndrome[0x20];
6105
6106         u8         reserved_1[0x20];
6107 };
6108
6109 struct mlx5_ifc_disable_hca_in_bits {
6110         u8         opcode[0x10];
6111         u8         reserved_0[0x10];
6112
6113         u8         reserved_1[0x10];
6114         u8         op_mod[0x10];
6115
6116         u8         reserved_2[0x10];
6117         u8         function_id[0x10];
6118
6119         u8         reserved_3[0x20];
6120 };
6121
6122 struct mlx5_ifc_detach_from_mcg_out_bits {
6123         u8         status[0x8];
6124         u8         reserved_0[0x18];
6125
6126         u8         syndrome[0x20];
6127
6128         u8         reserved_1[0x40];
6129 };
6130
6131 struct mlx5_ifc_detach_from_mcg_in_bits {
6132         u8         opcode[0x10];
6133         u8         reserved_0[0x10];
6134
6135         u8         reserved_1[0x10];
6136         u8         op_mod[0x10];
6137
6138         u8         reserved_2[0x8];
6139         u8         qpn[0x18];
6140
6141         u8         reserved_3[0x20];
6142
6143         u8         multicast_gid[16][0x8];
6144 };
6145
6146 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6147         u8         status[0x8];
6148         u8         reserved_0[0x18];
6149
6150         u8         syndrome[0x20];
6151
6152         u8         reserved_1[0x40];
6153 };
6154
6155 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6156         u8         opcode[0x10];
6157         u8         reserved_0[0x10];
6158
6159         u8         reserved_1[0x10];
6160         u8         op_mod[0x10];
6161
6162         u8         reserved_2[0x8];
6163         u8         xrc_srqn[0x18];
6164
6165         u8         reserved_3[0x20];
6166 };
6167
6168 struct mlx5_ifc_destroy_tis_out_bits {
6169         u8         status[0x8];
6170         u8         reserved_0[0x18];
6171
6172         u8         syndrome[0x20];
6173
6174         u8         reserved_1[0x40];
6175 };
6176
6177 struct mlx5_ifc_destroy_tis_in_bits {
6178         u8         opcode[0x10];
6179         u8         reserved_0[0x10];
6180
6181         u8         reserved_1[0x10];
6182         u8         op_mod[0x10];
6183
6184         u8         reserved_2[0x8];
6185         u8         tisn[0x18];
6186
6187         u8         reserved_3[0x20];
6188 };
6189
6190 struct mlx5_ifc_destroy_tir_out_bits {
6191         u8         status[0x8];
6192         u8         reserved_0[0x18];
6193
6194         u8         syndrome[0x20];
6195
6196         u8         reserved_1[0x40];
6197 };
6198
6199 struct mlx5_ifc_destroy_tir_in_bits {
6200         u8         opcode[0x10];
6201         u8         reserved_0[0x10];
6202
6203         u8         reserved_1[0x10];
6204         u8         op_mod[0x10];
6205
6206         u8         reserved_2[0x8];
6207         u8         tirn[0x18];
6208
6209         u8         reserved_3[0x20];
6210 };
6211
6212 struct mlx5_ifc_destroy_srq_out_bits {
6213         u8         status[0x8];
6214         u8         reserved_0[0x18];
6215
6216         u8         syndrome[0x20];
6217
6218         u8         reserved_1[0x40];
6219 };
6220
6221 struct mlx5_ifc_destroy_srq_in_bits {
6222         u8         opcode[0x10];
6223         u8         reserved_0[0x10];
6224
6225         u8         reserved_1[0x10];
6226         u8         op_mod[0x10];
6227
6228         u8         reserved_2[0x8];
6229         u8         srqn[0x18];
6230
6231         u8         reserved_3[0x20];
6232 };
6233
6234 struct mlx5_ifc_destroy_sq_out_bits {
6235         u8         status[0x8];
6236         u8         reserved_0[0x18];
6237
6238         u8         syndrome[0x20];
6239
6240         u8         reserved_1[0x40];
6241 };
6242
6243 struct mlx5_ifc_destroy_sq_in_bits {
6244         u8         opcode[0x10];
6245         u8         reserved_0[0x10];
6246
6247         u8         reserved_1[0x10];
6248         u8         op_mod[0x10];
6249
6250         u8         reserved_2[0x8];
6251         u8         sqn[0x18];
6252
6253         u8         reserved_3[0x20];
6254 };
6255
6256 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6257         u8         status[0x8];
6258         u8         reserved_at_8[0x18];
6259
6260         u8         syndrome[0x20];
6261
6262         u8         reserved_at_40[0x1c0];
6263 };
6264
6265 enum {
6266         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6267 };
6268
6269 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6270         u8         opcode[0x10];
6271         u8         reserved_at_10[0x10];
6272
6273         u8         reserved_at_20[0x10];
6274         u8         op_mod[0x10];
6275
6276         u8         scheduling_hierarchy[0x8];
6277         u8         reserved_at_48[0x18];
6278
6279         u8         scheduling_element_id[0x20];
6280
6281         u8         reserved_at_80[0x180];
6282 };
6283
6284 struct mlx5_ifc_destroy_rqt_out_bits {
6285         u8         status[0x8];
6286         u8         reserved_0[0x18];
6287
6288         u8         syndrome[0x20];
6289
6290         u8         reserved_1[0x40];
6291 };
6292
6293 struct mlx5_ifc_destroy_rqt_in_bits {
6294         u8         opcode[0x10];
6295         u8         reserved_0[0x10];
6296
6297         u8         reserved_1[0x10];
6298         u8         op_mod[0x10];
6299
6300         u8         reserved_2[0x8];
6301         u8         rqtn[0x18];
6302
6303         u8         reserved_3[0x20];
6304 };
6305
6306 struct mlx5_ifc_destroy_rq_out_bits {
6307         u8         status[0x8];
6308         u8         reserved_0[0x18];
6309
6310         u8         syndrome[0x20];
6311
6312         u8         reserved_1[0x40];
6313 };
6314
6315 struct mlx5_ifc_destroy_rq_in_bits {
6316         u8         opcode[0x10];
6317         u8         reserved_0[0x10];
6318
6319         u8         reserved_1[0x10];
6320         u8         op_mod[0x10];
6321
6322         u8         reserved_2[0x8];
6323         u8         rqn[0x18];
6324
6325         u8         reserved_3[0x20];
6326 };
6327
6328 struct mlx5_ifc_destroy_rmp_out_bits {
6329         u8         status[0x8];
6330         u8         reserved_0[0x18];
6331
6332         u8         syndrome[0x20];
6333
6334         u8         reserved_1[0x40];
6335 };
6336
6337 struct mlx5_ifc_destroy_rmp_in_bits {
6338         u8         opcode[0x10];
6339         u8         reserved_0[0x10];
6340
6341         u8         reserved_1[0x10];
6342         u8         op_mod[0x10];
6343
6344         u8         reserved_2[0x8];
6345         u8         rmpn[0x18];
6346
6347         u8         reserved_3[0x20];
6348 };
6349
6350 struct mlx5_ifc_destroy_qp_out_bits {
6351         u8         status[0x8];
6352         u8         reserved_0[0x18];
6353
6354         u8         syndrome[0x20];
6355
6356         u8         reserved_1[0x40];
6357 };
6358
6359 struct mlx5_ifc_destroy_qp_in_bits {
6360         u8         opcode[0x10];
6361         u8         reserved_0[0x10];
6362
6363         u8         reserved_1[0x10];
6364         u8         op_mod[0x10];
6365
6366         u8         reserved_2[0x8];
6367         u8         qpn[0x18];
6368
6369         u8         reserved_3[0x20];
6370 };
6371
6372 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6373         u8         status[0x8];
6374         u8         reserved_at_8[0x18];
6375
6376         u8         syndrome[0x20];
6377
6378         u8         reserved_at_40[0x1c0];
6379 };
6380
6381 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6382         u8         opcode[0x10];
6383         u8         reserved_at_10[0x10];
6384
6385         u8         reserved_at_20[0x10];
6386         u8         op_mod[0x10];
6387
6388         u8         reserved_at_40[0x20];
6389
6390         u8         reserved_at_60[0x10];
6391         u8         qos_para_vport_number[0x10];
6392
6393         u8         reserved_at_80[0x180];
6394 };
6395
6396 struct mlx5_ifc_destroy_psv_out_bits {
6397         u8         status[0x8];
6398         u8         reserved_0[0x18];
6399
6400         u8         syndrome[0x20];
6401
6402         u8         reserved_1[0x40];
6403 };
6404
6405 struct mlx5_ifc_destroy_psv_in_bits {
6406         u8         opcode[0x10];
6407         u8         reserved_0[0x10];
6408
6409         u8         reserved_1[0x10];
6410         u8         op_mod[0x10];
6411
6412         u8         reserved_2[0x8];
6413         u8         psvn[0x18];
6414
6415         u8         reserved_3[0x20];
6416 };
6417
6418 struct mlx5_ifc_destroy_mkey_out_bits {
6419         u8         status[0x8];
6420         u8         reserved_0[0x18];
6421
6422         u8         syndrome[0x20];
6423
6424         u8         reserved_1[0x40];
6425 };
6426
6427 struct mlx5_ifc_destroy_mkey_in_bits {
6428         u8         opcode[0x10];
6429         u8         reserved_0[0x10];
6430
6431         u8         reserved_1[0x10];
6432         u8         op_mod[0x10];
6433
6434         u8         reserved_2[0x8];
6435         u8         mkey_index[0x18];
6436
6437         u8         reserved_3[0x20];
6438 };
6439
6440 struct mlx5_ifc_destroy_flow_table_out_bits {
6441         u8         status[0x8];
6442         u8         reserved_0[0x18];
6443
6444         u8         syndrome[0x20];
6445
6446         u8         reserved_1[0x40];
6447 };
6448
6449 struct mlx5_ifc_destroy_flow_table_in_bits {
6450         u8         opcode[0x10];
6451         u8         reserved_0[0x10];
6452
6453         u8         reserved_1[0x10];
6454         u8         op_mod[0x10];
6455
6456         u8         other_vport[0x1];
6457         u8         reserved_2[0xf];
6458         u8         vport_number[0x10];
6459
6460         u8         reserved_3[0x20];
6461
6462         u8         table_type[0x8];
6463         u8         reserved_4[0x18];
6464
6465         u8         reserved_5[0x8];
6466         u8         table_id[0x18];
6467
6468         u8         reserved_6[0x140];
6469 };
6470
6471 struct mlx5_ifc_destroy_flow_group_out_bits {
6472         u8         status[0x8];
6473         u8         reserved_0[0x18];
6474
6475         u8         syndrome[0x20];
6476
6477         u8         reserved_1[0x40];
6478 };
6479
6480 struct mlx5_ifc_destroy_flow_group_in_bits {
6481         u8         opcode[0x10];
6482         u8         reserved_0[0x10];
6483
6484         u8         reserved_1[0x10];
6485         u8         op_mod[0x10];
6486
6487         u8         other_vport[0x1];
6488         u8         reserved_2[0xf];
6489         u8         vport_number[0x10];
6490
6491         u8         reserved_3[0x20];
6492
6493         u8         table_type[0x8];
6494         u8         reserved_4[0x18];
6495
6496         u8         reserved_5[0x8];
6497         u8         table_id[0x18];
6498
6499         u8         group_id[0x20];
6500
6501         u8         reserved_6[0x120];
6502 };
6503
6504 struct mlx5_ifc_destroy_encryption_key_out_bits {
6505         u8         status[0x8];
6506         u8         reserved_at_8[0x18];
6507
6508         u8         syndrome[0x20];
6509
6510         u8         reserved_at_40[0x40];
6511 };
6512
6513 struct mlx5_ifc_destroy_encryption_key_in_bits {
6514         u8         opcode[0x10];
6515         u8         reserved_at_10[0x10];
6516
6517         u8         reserved_at_20[0x10];
6518         u8         obj_type[0x10];
6519
6520         u8         obj_id[0x20];
6521
6522         u8         reserved_at_60[0x20];
6523 };
6524
6525 struct mlx5_ifc_destroy_eq_out_bits {
6526         u8         status[0x8];
6527         u8         reserved_0[0x18];
6528
6529         u8         syndrome[0x20];
6530
6531         u8         reserved_1[0x40];
6532 };
6533
6534 struct mlx5_ifc_destroy_eq_in_bits {
6535         u8         opcode[0x10];
6536         u8         reserved_0[0x10];
6537
6538         u8         reserved_1[0x10];
6539         u8         op_mod[0x10];
6540
6541         u8         reserved_2[0x18];
6542         u8         eq_number[0x8];
6543
6544         u8         reserved_3[0x20];
6545 };
6546
6547 struct mlx5_ifc_destroy_dct_out_bits {
6548         u8         status[0x8];
6549         u8         reserved_0[0x18];
6550
6551         u8         syndrome[0x20];
6552
6553         u8         reserved_1[0x40];
6554 };
6555
6556 struct mlx5_ifc_destroy_dct_in_bits {
6557         u8         opcode[0x10];
6558         u8         reserved_0[0x10];
6559
6560         u8         reserved_1[0x10];
6561         u8         op_mod[0x10];
6562
6563         u8         reserved_2[0x8];
6564         u8         dctn[0x18];
6565
6566         u8         reserved_3[0x20];
6567 };
6568
6569 struct mlx5_ifc_destroy_cq_out_bits {
6570         u8         status[0x8];
6571         u8         reserved_0[0x18];
6572
6573         u8         syndrome[0x20];
6574
6575         u8         reserved_1[0x40];
6576 };
6577
6578 struct mlx5_ifc_destroy_cq_in_bits {
6579         u8         opcode[0x10];
6580         u8         reserved_0[0x10];
6581
6582         u8         reserved_1[0x10];
6583         u8         op_mod[0x10];
6584
6585         u8         reserved_2[0x8];
6586         u8         cqn[0x18];
6587
6588         u8         reserved_3[0x20];
6589 };
6590
6591 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6592         u8         status[0x8];
6593         u8         reserved_0[0x18];
6594
6595         u8         syndrome[0x20];
6596
6597         u8         reserved_1[0x40];
6598 };
6599
6600 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6601         u8         opcode[0x10];
6602         u8         reserved_0[0x10];
6603
6604         u8         reserved_1[0x10];
6605         u8         op_mod[0x10];
6606
6607         u8         reserved_2[0x20];
6608
6609         u8         reserved_3[0x10];
6610         u8         vxlan_udp_port[0x10];
6611 };
6612
6613 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6614         u8         status[0x8];
6615         u8         reserved_0[0x18];
6616
6617         u8         syndrome[0x20];
6618
6619         u8         reserved_1[0x40];
6620 };
6621
6622 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6623         u8         opcode[0x10];
6624         u8         reserved_0[0x10];
6625
6626         u8         reserved_1[0x10];
6627         u8         op_mod[0x10];
6628
6629         u8         reserved_2[0x60];
6630
6631         u8         reserved_3[0x8];
6632         u8         table_index[0x18];
6633
6634         u8         reserved_4[0x140];
6635 };
6636
6637 struct mlx5_ifc_delete_fte_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_0[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_1[0x40];
6644 };
6645
6646 struct mlx5_ifc_delete_fte_in_bits {
6647         u8         opcode[0x10];
6648         u8         reserved_0[0x10];
6649
6650         u8         reserved_1[0x10];
6651         u8         op_mod[0x10];
6652
6653         u8         other_vport[0x1];
6654         u8         reserved_2[0xf];
6655         u8         vport_number[0x10];
6656
6657         u8         reserved_3[0x20];
6658
6659         u8         table_type[0x8];
6660         u8         reserved_4[0x18];
6661
6662         u8         reserved_5[0x8];
6663         u8         table_id[0x18];
6664
6665         u8         reserved_6[0x40];
6666
6667         u8         flow_index[0x20];
6668
6669         u8         reserved_7[0xe0];
6670 };
6671
6672 struct mlx5_ifc_dealloc_xrcd_out_bits {
6673         u8         status[0x8];
6674         u8         reserved_0[0x18];
6675
6676         u8         syndrome[0x20];
6677
6678         u8         reserved_1[0x40];
6679 };
6680
6681 struct mlx5_ifc_dealloc_xrcd_in_bits {
6682         u8         opcode[0x10];
6683         u8         reserved_0[0x10];
6684
6685         u8         reserved_1[0x10];
6686         u8         op_mod[0x10];
6687
6688         u8         reserved_2[0x8];
6689         u8         xrcd[0x18];
6690
6691         u8         reserved_3[0x20];
6692 };
6693
6694 struct mlx5_ifc_dealloc_uar_out_bits {
6695         u8         status[0x8];
6696         u8         reserved_0[0x18];
6697
6698         u8         syndrome[0x20];
6699
6700         u8         reserved_1[0x40];
6701 };
6702
6703 struct mlx5_ifc_dealloc_uar_in_bits {
6704         u8         opcode[0x10];
6705         u8         reserved_0[0x10];
6706
6707         u8         reserved_1[0x10];
6708         u8         op_mod[0x10];
6709
6710         u8         reserved_2[0x8];
6711         u8         uar[0x18];
6712
6713         u8         reserved_3[0x20];
6714 };
6715
6716 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6717         u8         status[0x8];
6718         u8         reserved_0[0x18];
6719
6720         u8         syndrome[0x20];
6721
6722         u8         reserved_1[0x40];
6723 };
6724
6725 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6726         u8         opcode[0x10];
6727         u8         reserved_0[0x10];
6728
6729         u8         reserved_1[0x10];
6730         u8         op_mod[0x10];
6731
6732         u8         reserved_2[0x8];
6733         u8         transport_domain[0x18];
6734
6735         u8         reserved_3[0x20];
6736 };
6737
6738 struct mlx5_ifc_dealloc_q_counter_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_0[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_1[0x40];
6745 };
6746
6747 struct mlx5_ifc_counter_id_bits {
6748         u8         reserved[0x10];
6749         u8         counter_id[0x10];
6750 };
6751
6752 struct mlx5_ifc_diagnostic_params_context_bits {
6753         u8         num_of_counters[0x10];
6754         u8         reserved_2[0x8];
6755         u8         log_num_of_samples[0x8];
6756
6757         u8         single[0x1];
6758         u8         repetitive[0x1];
6759         u8         sync[0x1];
6760         u8         clear[0x1];
6761         u8         on_demand[0x1];
6762         u8         enable[0x1];
6763         u8         reserved_3[0x12];
6764         u8         log_sample_period[0x8];
6765
6766         u8         reserved_4[0x80];
6767
6768         struct mlx5_ifc_counter_id_bits counter_id[0];
6769 };
6770
6771 struct mlx5_ifc_set_diagnostic_params_in_bits {
6772         u8         opcode[0x10];
6773         u8         reserved_0[0x10];
6774
6775         u8         reserved_1[0x10];
6776         u8         op_mod[0x10];
6777
6778         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6779 };
6780
6781 struct mlx5_ifc_set_diagnostic_params_out_bits {
6782         u8         status[0x8];
6783         u8         reserved_0[0x18];
6784
6785         u8         syndrome[0x20];
6786
6787         u8         reserved_1[0x40];
6788 };
6789
6790 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6791         u8         opcode[0x10];
6792         u8         reserved_0[0x10];
6793
6794         u8         reserved_1[0x10];
6795         u8         op_mod[0x10];
6796
6797         u8         num_of_samples[0x10];
6798         u8         sample_index[0x10];
6799
6800         u8         reserved_2[0x20];
6801 };
6802
6803 struct mlx5_ifc_diagnostic_counter_bits {
6804         u8         counter_id[0x10];
6805         u8         sample_id[0x10];
6806
6807         u8         time_stamp_31_0[0x20];
6808
6809         u8         counter_value_h[0x20];
6810
6811         u8         counter_value_l[0x20];
6812 };
6813
6814 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6815         u8         status[0x8];
6816         u8         reserved_0[0x18];
6817
6818         u8         syndrome[0x20];
6819
6820         u8         reserved_1[0x40];
6821
6822         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6823 };
6824
6825 struct mlx5_ifc_dealloc_q_counter_in_bits {
6826         u8         opcode[0x10];
6827         u8         reserved_0[0x10];
6828
6829         u8         reserved_1[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         reserved_2[0x18];
6833         u8         counter_set_id[0x8];
6834
6835         u8         reserved_3[0x20];
6836 };
6837
6838 struct mlx5_ifc_dealloc_pd_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_0[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_1[0x40];
6845 };
6846
6847 struct mlx5_ifc_dealloc_pd_in_bits {
6848         u8         opcode[0x10];
6849         u8         reserved_0[0x10];
6850
6851         u8         reserved_1[0x10];
6852         u8         op_mod[0x10];
6853
6854         u8         reserved_2[0x8];
6855         u8         pd[0x18];
6856
6857         u8         reserved_3[0x20];
6858 };
6859
6860 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_0[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_1[0x40];
6867 };
6868
6869 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6870         u8         opcode[0x10];
6871         u8         reserved_0[0x10];
6872
6873         u8         reserved_1[0x10];
6874         u8         op_mod[0x10];
6875
6876         u8         reserved_2[0x10];
6877         u8         flow_counter_id[0x10];
6878
6879         u8         reserved_3[0x20];
6880 };
6881
6882 struct mlx5_ifc_deactivate_tracer_out_bits {
6883         u8         status[0x8];
6884         u8         reserved_0[0x18];
6885
6886         u8         syndrome[0x20];
6887
6888         u8         reserved_1[0x40];
6889 };
6890
6891 struct mlx5_ifc_deactivate_tracer_in_bits {
6892         u8         opcode[0x10];
6893         u8         reserved_0[0x10];
6894
6895         u8         reserved_1[0x10];
6896         u8         op_mod[0x10];
6897
6898         u8         mkey[0x20];
6899
6900         u8         reserved_2[0x20];
6901 };
6902
6903 struct mlx5_ifc_create_xrc_srq_out_bits {
6904         u8         status[0x8];
6905         u8         reserved_0[0x18];
6906
6907         u8         syndrome[0x20];
6908
6909         u8         reserved_1[0x8];
6910         u8         xrc_srqn[0x18];
6911
6912         u8         reserved_2[0x20];
6913 };
6914
6915 struct mlx5_ifc_create_xrc_srq_in_bits {
6916         u8         opcode[0x10];
6917         u8         reserved_0[0x10];
6918
6919         u8         reserved_1[0x10];
6920         u8         op_mod[0x10];
6921
6922         u8         reserved_2[0x40];
6923
6924         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6925
6926         u8         reserved_3[0x600];
6927
6928         u8         pas[0][0x40];
6929 };
6930
6931 struct mlx5_ifc_create_tis_out_bits {
6932         u8         status[0x8];
6933         u8         reserved_0[0x18];
6934
6935         u8         syndrome[0x20];
6936
6937         u8         reserved_1[0x8];
6938         u8         tisn[0x18];
6939
6940         u8         reserved_2[0x20];
6941 };
6942
6943 struct mlx5_ifc_create_tis_in_bits {
6944         u8         opcode[0x10];
6945         u8         reserved_0[0x10];
6946
6947         u8         reserved_1[0x10];
6948         u8         op_mod[0x10];
6949
6950         u8         reserved_2[0xc0];
6951
6952         struct mlx5_ifc_tisc_bits ctx;
6953 };
6954
6955 struct mlx5_ifc_create_tir_out_bits {
6956         u8         status[0x8];
6957         u8         reserved_0[0x18];
6958
6959         u8         syndrome[0x20];
6960
6961         u8         reserved_1[0x8];
6962         u8         tirn[0x18];
6963
6964         u8         reserved_2[0x20];
6965 };
6966
6967 struct mlx5_ifc_create_tir_in_bits {
6968         u8         opcode[0x10];
6969         u8         reserved_0[0x10];
6970
6971         u8         reserved_1[0x10];
6972         u8         op_mod[0x10];
6973
6974         u8         reserved_2[0xc0];
6975
6976         struct mlx5_ifc_tirc_bits tir_context;
6977 };
6978
6979 struct mlx5_ifc_create_srq_out_bits {
6980         u8         status[0x8];
6981         u8         reserved_0[0x18];
6982
6983         u8         syndrome[0x20];
6984
6985         u8         reserved_1[0x8];
6986         u8         srqn[0x18];
6987
6988         u8         reserved_2[0x20];
6989 };
6990
6991 struct mlx5_ifc_create_srq_in_bits {
6992         u8         opcode[0x10];
6993         u8         reserved_0[0x10];
6994
6995         u8         reserved_1[0x10];
6996         u8         op_mod[0x10];
6997
6998         u8         reserved_2[0x40];
6999
7000         struct mlx5_ifc_srqc_bits srq_context_entry;
7001
7002         u8         reserved_3[0x600];
7003
7004         u8         pas[0][0x40];
7005 };
7006
7007 struct mlx5_ifc_create_sq_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_0[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_1[0x8];
7014         u8         sqn[0x18];
7015
7016         u8         reserved_2[0x20];
7017 };
7018
7019 struct mlx5_ifc_create_sq_in_bits {
7020         u8         opcode[0x10];
7021         u8         reserved_0[0x10];
7022
7023         u8         reserved_1[0x10];
7024         u8         op_mod[0x10];
7025
7026         u8         reserved_2[0xc0];
7027
7028         struct mlx5_ifc_sqc_bits ctx;
7029 };
7030
7031 struct mlx5_ifc_create_scheduling_element_out_bits {
7032         u8         status[0x8];
7033         u8         reserved_at_8[0x18];
7034
7035         u8         syndrome[0x20];
7036
7037         u8         reserved_at_40[0x40];
7038
7039         u8         scheduling_element_id[0x20];
7040
7041         u8         reserved_at_a0[0x160];
7042 };
7043
7044 enum {
7045         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7046 };
7047
7048 struct mlx5_ifc_create_scheduling_element_in_bits {
7049         u8         opcode[0x10];
7050         u8         reserved_at_10[0x10];
7051
7052         u8         reserved_at_20[0x10];
7053         u8         op_mod[0x10];
7054
7055         u8         scheduling_hierarchy[0x8];
7056         u8         reserved_at_48[0x18];
7057
7058         u8         reserved_at_60[0xa0];
7059
7060         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7061
7062         u8         reserved_at_300[0x100];
7063 };
7064
7065 struct mlx5_ifc_create_rqt_out_bits {
7066         u8         status[0x8];
7067         u8         reserved_0[0x18];
7068
7069         u8         syndrome[0x20];
7070
7071         u8         reserved_1[0x8];
7072         u8         rqtn[0x18];
7073
7074         u8         reserved_2[0x20];
7075 };
7076
7077 struct mlx5_ifc_create_rqt_in_bits {
7078         u8         opcode[0x10];
7079         u8         reserved_0[0x10];
7080
7081         u8         reserved_1[0x10];
7082         u8         op_mod[0x10];
7083
7084         u8         reserved_2[0xc0];
7085
7086         struct mlx5_ifc_rqtc_bits rqt_context;
7087 };
7088
7089 struct mlx5_ifc_create_rq_out_bits {
7090         u8         status[0x8];
7091         u8         reserved_0[0x18];
7092
7093         u8         syndrome[0x20];
7094
7095         u8         reserved_1[0x8];
7096         u8         rqn[0x18];
7097
7098         u8         reserved_2[0x20];
7099 };
7100
7101 struct mlx5_ifc_create_rq_in_bits {
7102         u8         opcode[0x10];
7103         u8         reserved_0[0x10];
7104
7105         u8         reserved_1[0x10];
7106         u8         op_mod[0x10];
7107
7108         u8         reserved_2[0xc0];
7109
7110         struct mlx5_ifc_rqc_bits ctx;
7111 };
7112
7113 struct mlx5_ifc_create_rmp_out_bits {
7114         u8         status[0x8];
7115         u8         reserved_0[0x18];
7116
7117         u8         syndrome[0x20];
7118
7119         u8         reserved_1[0x8];
7120         u8         rmpn[0x18];
7121
7122         u8         reserved_2[0x20];
7123 };
7124
7125 struct mlx5_ifc_create_rmp_in_bits {
7126         u8         opcode[0x10];
7127         u8         reserved_0[0x10];
7128
7129         u8         reserved_1[0x10];
7130         u8         op_mod[0x10];
7131
7132         u8         reserved_2[0xc0];
7133
7134         struct mlx5_ifc_rmpc_bits ctx;
7135 };
7136
7137 struct mlx5_ifc_create_qp_out_bits {
7138         u8         status[0x8];
7139         u8         reserved_0[0x18];
7140
7141         u8         syndrome[0x20];
7142
7143         u8         reserved_1[0x8];
7144         u8         qpn[0x18];
7145
7146         u8         reserved_2[0x20];
7147 };
7148
7149 struct mlx5_ifc_create_qp_in_bits {
7150         u8         opcode[0x10];
7151         u8         reserved_0[0x10];
7152
7153         u8         reserved_1[0x10];
7154         u8         op_mod[0x10];
7155
7156         u8         reserved_2[0x8];
7157         u8         input_qpn[0x18];
7158
7159         u8         reserved_3[0x20];
7160
7161         u8         opt_param_mask[0x20];
7162
7163         u8         reserved_4[0x20];
7164
7165         struct mlx5_ifc_qpc_bits qpc;
7166
7167         u8         reserved_5[0x80];
7168
7169         u8         pas[0][0x40];
7170 };
7171
7172 struct mlx5_ifc_create_qos_para_vport_out_bits {
7173         u8         status[0x8];
7174         u8         reserved_at_8[0x18];
7175
7176         u8         syndrome[0x20];
7177
7178         u8         reserved_at_40[0x20];
7179
7180         u8         reserved_at_60[0x10];
7181         u8         qos_para_vport_number[0x10];
7182
7183         u8         reserved_at_80[0x180];
7184 };
7185
7186 struct mlx5_ifc_create_qos_para_vport_in_bits {
7187         u8         opcode[0x10];
7188         u8         reserved_at_10[0x10];
7189
7190         u8         reserved_at_20[0x10];
7191         u8         op_mod[0x10];
7192
7193         u8         reserved_at_40[0x1c0];
7194 };
7195
7196 struct mlx5_ifc_create_psv_out_bits {
7197         u8         status[0x8];
7198         u8         reserved_0[0x18];
7199
7200         u8         syndrome[0x20];
7201
7202         u8         reserved_1[0x40];
7203
7204         u8         reserved_2[0x8];
7205         u8         psv0_index[0x18];
7206
7207         u8         reserved_3[0x8];
7208         u8         psv1_index[0x18];
7209
7210         u8         reserved_4[0x8];
7211         u8         psv2_index[0x18];
7212
7213         u8         reserved_5[0x8];
7214         u8         psv3_index[0x18];
7215 };
7216
7217 struct mlx5_ifc_create_psv_in_bits {
7218         u8         opcode[0x10];
7219         u8         reserved_0[0x10];
7220
7221         u8         reserved_1[0x10];
7222         u8         op_mod[0x10];
7223
7224         u8         num_psv[0x4];
7225         u8         reserved_2[0x4];
7226         u8         pd[0x18];
7227
7228         u8         reserved_3[0x20];
7229 };
7230
7231 struct mlx5_ifc_create_mkey_out_bits {
7232         u8         status[0x8];
7233         u8         reserved_0[0x18];
7234
7235         u8         syndrome[0x20];
7236
7237         u8         reserved_1[0x8];
7238         u8         mkey_index[0x18];
7239
7240         u8         reserved_2[0x20];
7241 };
7242
7243 struct mlx5_ifc_create_mkey_in_bits {
7244         u8         opcode[0x10];
7245         u8         reserved_0[0x10];
7246
7247         u8         reserved_1[0x10];
7248         u8         op_mod[0x10];
7249
7250         u8         reserved_2[0x20];
7251
7252         u8         pg_access[0x1];
7253         u8         reserved_3[0x1f];
7254
7255         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7256
7257         u8         reserved_4[0x80];
7258
7259         u8         translations_octword_actual_size[0x20];
7260
7261         u8         reserved_5[0x560];
7262
7263         u8         klm_pas_mtt[0][0x20];
7264 };
7265
7266 struct mlx5_ifc_create_flow_table_out_bits {
7267         u8         status[0x8];
7268         u8         reserved_0[0x18];
7269
7270         u8         syndrome[0x20];
7271
7272         u8         reserved_1[0x8];
7273         u8         table_id[0x18];
7274
7275         u8         reserved_2[0x20];
7276 };
7277
7278 struct mlx5_ifc_create_flow_table_in_bits {
7279         u8         opcode[0x10];
7280         u8         reserved_at_10[0x10];
7281
7282         u8         reserved_at_20[0x10];
7283         u8         op_mod[0x10];
7284
7285         u8         other_vport[0x1];
7286         u8         reserved_at_41[0xf];
7287         u8         vport_number[0x10];
7288
7289         u8         reserved_at_60[0x20];
7290
7291         u8         table_type[0x8];
7292         u8         reserved_at_88[0x18];
7293
7294         u8         reserved_at_a0[0x20];
7295
7296         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7297 };
7298
7299 struct mlx5_ifc_create_flow_group_out_bits {
7300         u8         status[0x8];
7301         u8         reserved_0[0x18];
7302
7303         u8         syndrome[0x20];
7304
7305         u8         reserved_1[0x8];
7306         u8         group_id[0x18];
7307
7308         u8         reserved_2[0x20];
7309 };
7310
7311 enum {
7312         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7313         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7314         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7315 };
7316
7317 struct mlx5_ifc_create_flow_group_in_bits {
7318         u8         opcode[0x10];
7319         u8         reserved_0[0x10];
7320
7321         u8         reserved_1[0x10];
7322         u8         op_mod[0x10];
7323
7324         u8         other_vport[0x1];
7325         u8         reserved_2[0xf];
7326         u8         vport_number[0x10];
7327
7328         u8         reserved_3[0x20];
7329
7330         u8         table_type[0x8];
7331         u8         reserved_4[0x18];
7332
7333         u8         reserved_5[0x8];
7334         u8         table_id[0x18];
7335
7336         u8         reserved_6[0x20];
7337
7338         u8         start_flow_index[0x20];
7339
7340         u8         reserved_7[0x20];
7341
7342         u8         end_flow_index[0x20];
7343
7344         u8         reserved_8[0xa0];
7345
7346         u8         reserved_9[0x18];
7347         u8         match_criteria_enable[0x8];
7348
7349         struct mlx5_ifc_fte_match_param_bits match_criteria;
7350
7351         u8         reserved_10[0xe00];
7352 };
7353
7354 struct mlx5_ifc_create_encryption_key_out_bits {
7355         u8         status[0x8];
7356         u8         reserved_at_8[0x18];
7357
7358         u8         syndrome[0x20];
7359
7360         u8         obj_id[0x20];
7361
7362         u8         reserved_at_60[0x20];
7363 };
7364
7365 struct mlx5_ifc_create_encryption_key_in_bits {
7366         u8         opcode[0x10];
7367         u8         reserved_at_10[0x10];
7368
7369         u8         reserved_at_20[0x10];
7370         u8         obj_type[0x10];
7371
7372         u8         reserved_at_40[0x40];
7373
7374         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7375 };
7376
7377 struct mlx5_ifc_create_eq_out_bits {
7378         u8         status[0x8];
7379         u8         reserved_0[0x18];
7380
7381         u8         syndrome[0x20];
7382
7383         u8         reserved_1[0x18];
7384         u8         eq_number[0x8];
7385
7386         u8         reserved_2[0x20];
7387 };
7388
7389 struct mlx5_ifc_create_eq_in_bits {
7390         u8         opcode[0x10];
7391         u8         reserved_0[0x10];
7392
7393         u8         reserved_1[0x10];
7394         u8         op_mod[0x10];
7395
7396         u8         reserved_2[0x40];
7397
7398         struct mlx5_ifc_eqc_bits eq_context_entry;
7399
7400         u8         reserved_3[0x40];
7401
7402         u8         event_bitmask[0x40];
7403
7404         u8         reserved_4[0x580];
7405
7406         u8         pas[0][0x40];
7407 };
7408
7409 struct mlx5_ifc_create_dct_out_bits {
7410         u8         status[0x8];
7411         u8         reserved_0[0x18];
7412
7413         u8         syndrome[0x20];
7414
7415         u8         reserved_1[0x8];
7416         u8         dctn[0x18];
7417
7418         u8         reserved_2[0x20];
7419 };
7420
7421 struct mlx5_ifc_create_dct_in_bits {
7422         u8         opcode[0x10];
7423         u8         reserved_0[0x10];
7424
7425         u8         reserved_1[0x10];
7426         u8         op_mod[0x10];
7427
7428         u8         reserved_2[0x40];
7429
7430         struct mlx5_ifc_dctc_bits dct_context_entry;
7431
7432         u8         reserved_3[0x180];
7433 };
7434
7435 struct mlx5_ifc_create_cq_out_bits {
7436         u8         status[0x8];
7437         u8         reserved_0[0x18];
7438
7439         u8         syndrome[0x20];
7440
7441         u8         reserved_1[0x8];
7442         u8         cqn[0x18];
7443
7444         u8         reserved_2[0x20];
7445 };
7446
7447 struct mlx5_ifc_create_cq_in_bits {
7448         u8         opcode[0x10];
7449         u8         reserved_0[0x10];
7450
7451         u8         reserved_1[0x10];
7452         u8         op_mod[0x10];
7453
7454         u8         reserved_2[0x40];
7455
7456         struct mlx5_ifc_cqc_bits cq_context;
7457
7458         u8         reserved_3[0x600];
7459
7460         u8         pas[0][0x40];
7461 };
7462
7463 struct mlx5_ifc_config_int_moderation_out_bits {
7464         u8         status[0x8];
7465         u8         reserved_0[0x18];
7466
7467         u8         syndrome[0x20];
7468
7469         u8         reserved_1[0x4];
7470         u8         min_delay[0xc];
7471         u8         int_vector[0x10];
7472
7473         u8         reserved_2[0x20];
7474 };
7475
7476 enum {
7477         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7478         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7479 };
7480
7481 struct mlx5_ifc_config_int_moderation_in_bits {
7482         u8         opcode[0x10];
7483         u8         reserved_0[0x10];
7484
7485         u8         reserved_1[0x10];
7486         u8         op_mod[0x10];
7487
7488         u8         reserved_2[0x4];
7489         u8         min_delay[0xc];
7490         u8         int_vector[0x10];
7491
7492         u8         reserved_3[0x20];
7493 };
7494
7495 struct mlx5_ifc_attach_to_mcg_out_bits {
7496         u8         status[0x8];
7497         u8         reserved_0[0x18];
7498
7499         u8         syndrome[0x20];
7500
7501         u8         reserved_1[0x40];
7502 };
7503
7504 struct mlx5_ifc_attach_to_mcg_in_bits {
7505         u8         opcode[0x10];
7506         u8         reserved_0[0x10];
7507
7508         u8         reserved_1[0x10];
7509         u8         op_mod[0x10];
7510
7511         u8         reserved_2[0x8];
7512         u8         qpn[0x18];
7513
7514         u8         reserved_3[0x20];
7515
7516         u8         multicast_gid[16][0x8];
7517 };
7518
7519 struct mlx5_ifc_arm_xrc_srq_out_bits {
7520         u8         status[0x8];
7521         u8         reserved_0[0x18];
7522
7523         u8         syndrome[0x20];
7524
7525         u8         reserved_1[0x40];
7526 };
7527
7528 enum {
7529         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7530 };
7531
7532 struct mlx5_ifc_arm_xrc_srq_in_bits {
7533         u8         opcode[0x10];
7534         u8         reserved_0[0x10];
7535
7536         u8         reserved_1[0x10];
7537         u8         op_mod[0x10];
7538
7539         u8         reserved_2[0x8];
7540         u8         xrc_srqn[0x18];
7541
7542         u8         reserved_3[0x10];
7543         u8         lwm[0x10];
7544 };
7545
7546 struct mlx5_ifc_arm_rq_out_bits {
7547         u8         status[0x8];
7548         u8         reserved_0[0x18];
7549
7550         u8         syndrome[0x20];
7551
7552         u8         reserved_1[0x40];
7553 };
7554
7555 enum {
7556         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7557 };
7558
7559 struct mlx5_ifc_arm_rq_in_bits {
7560         u8         opcode[0x10];
7561         u8         reserved_0[0x10];
7562
7563         u8         reserved_1[0x10];
7564         u8         op_mod[0x10];
7565
7566         u8         reserved_2[0x8];
7567         u8         srq_number[0x18];
7568
7569         u8         reserved_3[0x10];
7570         u8         lwm[0x10];
7571 };
7572
7573 struct mlx5_ifc_arm_dct_out_bits {
7574         u8         status[0x8];
7575         u8         reserved_0[0x18];
7576
7577         u8         syndrome[0x20];
7578
7579         u8         reserved_1[0x40];
7580 };
7581
7582 struct mlx5_ifc_arm_dct_in_bits {
7583         u8         opcode[0x10];
7584         u8         reserved_0[0x10];
7585
7586         u8         reserved_1[0x10];
7587         u8         op_mod[0x10];
7588
7589         u8         reserved_2[0x8];
7590         u8         dctn[0x18];
7591
7592         u8         reserved_3[0x20];
7593 };
7594
7595 struct mlx5_ifc_alloc_xrcd_out_bits {
7596         u8         status[0x8];
7597         u8         reserved_0[0x18];
7598
7599         u8         syndrome[0x20];
7600
7601         u8         reserved_1[0x8];
7602         u8         xrcd[0x18];
7603
7604         u8         reserved_2[0x20];
7605 };
7606
7607 struct mlx5_ifc_alloc_xrcd_in_bits {
7608         u8         opcode[0x10];
7609         u8         reserved_0[0x10];
7610
7611         u8         reserved_1[0x10];
7612         u8         op_mod[0x10];
7613
7614         u8         reserved_2[0x40];
7615 };
7616
7617 struct mlx5_ifc_alloc_uar_out_bits {
7618         u8         status[0x8];
7619         u8         reserved_0[0x18];
7620
7621         u8         syndrome[0x20];
7622
7623         u8         reserved_1[0x8];
7624         u8         uar[0x18];
7625
7626         u8         reserved_2[0x20];
7627 };
7628
7629 struct mlx5_ifc_alloc_uar_in_bits {
7630         u8         opcode[0x10];
7631         u8         reserved_0[0x10];
7632
7633         u8         reserved_1[0x10];
7634         u8         op_mod[0x10];
7635
7636         u8         reserved_2[0x40];
7637 };
7638
7639 struct mlx5_ifc_alloc_transport_domain_out_bits {
7640         u8         status[0x8];
7641         u8         reserved_0[0x18];
7642
7643         u8         syndrome[0x20];
7644
7645         u8         reserved_1[0x8];
7646         u8         transport_domain[0x18];
7647
7648         u8         reserved_2[0x20];
7649 };
7650
7651 struct mlx5_ifc_alloc_transport_domain_in_bits {
7652         u8         opcode[0x10];
7653         u8         reserved_0[0x10];
7654
7655         u8         reserved_1[0x10];
7656         u8         op_mod[0x10];
7657
7658         u8         reserved_2[0x40];
7659 };
7660
7661 struct mlx5_ifc_alloc_q_counter_out_bits {
7662         u8         status[0x8];
7663         u8         reserved_0[0x18];
7664
7665         u8         syndrome[0x20];
7666
7667         u8         reserved_1[0x18];
7668         u8         counter_set_id[0x8];
7669
7670         u8         reserved_2[0x20];
7671 };
7672
7673 struct mlx5_ifc_alloc_q_counter_in_bits {
7674         u8         opcode[0x10];
7675         u8         reserved_0[0x10];
7676
7677         u8         reserved_1[0x10];
7678         u8         op_mod[0x10];
7679
7680         u8         reserved_2[0x40];
7681 };
7682
7683 struct mlx5_ifc_alloc_pd_out_bits {
7684         u8         status[0x8];
7685         u8         reserved_0[0x18];
7686
7687         u8         syndrome[0x20];
7688
7689         u8         reserved_1[0x8];
7690         u8         pd[0x18];
7691
7692         u8         reserved_2[0x20];
7693 };
7694
7695 struct mlx5_ifc_alloc_pd_in_bits {
7696         u8         opcode[0x10];
7697         u8         reserved_0[0x10];
7698
7699         u8         reserved_1[0x10];
7700         u8         op_mod[0x10];
7701
7702         u8         reserved_2[0x40];
7703 };
7704
7705 struct mlx5_ifc_alloc_flow_counter_out_bits {
7706         u8         status[0x8];
7707         u8         reserved_0[0x18];
7708
7709         u8         syndrome[0x20];
7710
7711         u8         reserved_1[0x10];
7712         u8         flow_counter_id[0x10];
7713
7714         u8         reserved_2[0x20];
7715 };
7716
7717 struct mlx5_ifc_alloc_flow_counter_in_bits {
7718         u8         opcode[0x10];
7719         u8         reserved_0[0x10];
7720
7721         u8         reserved_1[0x10];
7722         u8         op_mod[0x10];
7723
7724         u8         reserved_2[0x40];
7725 };
7726
7727 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7728         u8         status[0x8];
7729         u8         reserved_0[0x18];
7730
7731         u8         syndrome[0x20];
7732
7733         u8         reserved_1[0x40];
7734 };
7735
7736 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7737         u8         opcode[0x10];
7738         u8         reserved_0[0x10];
7739
7740         u8         reserved_1[0x10];
7741         u8         op_mod[0x10];
7742
7743         u8         reserved_2[0x20];
7744
7745         u8         reserved_3[0x10];
7746         u8         vxlan_udp_port[0x10];
7747 };
7748
7749 struct mlx5_ifc_activate_tracer_out_bits {
7750         u8         status[0x8];
7751         u8         reserved_0[0x18];
7752
7753         u8         syndrome[0x20];
7754
7755         u8         reserved_1[0x40];
7756 };
7757
7758 struct mlx5_ifc_activate_tracer_in_bits {
7759         u8         opcode[0x10];
7760         u8         reserved_0[0x10];
7761
7762         u8         reserved_1[0x10];
7763         u8         op_mod[0x10];
7764
7765         u8         mkey[0x20];
7766
7767         u8         reserved_2[0x20];
7768 };
7769
7770 struct mlx5_ifc_set_rate_limit_out_bits {
7771         u8         status[0x8];
7772         u8         reserved_at_8[0x18];
7773
7774         u8         syndrome[0x20];
7775
7776         u8         reserved_at_40[0x40];
7777 };
7778
7779 struct mlx5_ifc_set_rate_limit_in_bits {
7780         u8         opcode[0x10];
7781         u8         reserved_at_10[0x10];
7782
7783         u8         reserved_at_20[0x10];
7784         u8         op_mod[0x10];
7785
7786         u8         reserved_at_40[0x10];
7787         u8         rate_limit_index[0x10];
7788
7789         u8         reserved_at_60[0x20];
7790
7791         u8         rate_limit[0x20];
7792         u8         burst_upper_bound[0x20];
7793 };
7794
7795 struct mlx5_ifc_access_register_out_bits {
7796         u8         status[0x8];
7797         u8         reserved_0[0x18];
7798
7799         u8         syndrome[0x20];
7800
7801         u8         reserved_1[0x40];
7802
7803         u8         register_data[0][0x20];
7804 };
7805
7806 enum {
7807         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7808         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7809 };
7810
7811 struct mlx5_ifc_access_register_in_bits {
7812         u8         opcode[0x10];
7813         u8         reserved_0[0x10];
7814
7815         u8         reserved_1[0x10];
7816         u8         op_mod[0x10];
7817
7818         u8         reserved_2[0x10];
7819         u8         register_id[0x10];
7820
7821         u8         argument[0x20];
7822
7823         u8         register_data[0][0x20];
7824 };
7825
7826 struct mlx5_ifc_sltp_reg_bits {
7827         u8         status[0x4];
7828         u8         version[0x4];
7829         u8         local_port[0x8];
7830         u8         pnat[0x2];
7831         u8         reserved_0[0x2];
7832         u8         lane[0x4];
7833         u8         reserved_1[0x8];
7834
7835         u8         reserved_2[0x20];
7836
7837         u8         reserved_3[0x7];
7838         u8         polarity[0x1];
7839         u8         ob_tap0[0x8];
7840         u8         ob_tap1[0x8];
7841         u8         ob_tap2[0x8];
7842
7843         u8         reserved_4[0xc];
7844         u8         ob_preemp_mode[0x4];
7845         u8         ob_reg[0x8];
7846         u8         ob_bias[0x8];
7847
7848         u8         reserved_5[0x20];
7849 };
7850
7851 struct mlx5_ifc_slrp_reg_bits {
7852         u8         status[0x4];
7853         u8         version[0x4];
7854         u8         local_port[0x8];
7855         u8         pnat[0x2];
7856         u8         reserved_0[0x2];
7857         u8         lane[0x4];
7858         u8         reserved_1[0x8];
7859
7860         u8         ib_sel[0x2];
7861         u8         reserved_2[0x11];
7862         u8         dp_sel[0x1];
7863         u8         dp90sel[0x4];
7864         u8         mix90phase[0x8];
7865
7866         u8         ffe_tap0[0x8];
7867         u8         ffe_tap1[0x8];
7868         u8         ffe_tap2[0x8];
7869         u8         ffe_tap3[0x8];
7870
7871         u8         ffe_tap4[0x8];
7872         u8         ffe_tap5[0x8];
7873         u8         ffe_tap6[0x8];
7874         u8         ffe_tap7[0x8];
7875
7876         u8         ffe_tap8[0x8];
7877         u8         mixerbias_tap_amp[0x8];
7878         u8         reserved_3[0x7];
7879         u8         ffe_tap_en[0x9];
7880
7881         u8         ffe_tap_offset0[0x8];
7882         u8         ffe_tap_offset1[0x8];
7883         u8         slicer_offset0[0x10];
7884
7885         u8         mixer_offset0[0x10];
7886         u8         mixer_offset1[0x10];
7887
7888         u8         mixerbgn_inp[0x8];
7889         u8         mixerbgn_inn[0x8];
7890         u8         mixerbgn_refp[0x8];
7891         u8         mixerbgn_refn[0x8];
7892
7893         u8         sel_slicer_lctrl_h[0x1];
7894         u8         sel_slicer_lctrl_l[0x1];
7895         u8         reserved_4[0x1];
7896         u8         ref_mixer_vreg[0x5];
7897         u8         slicer_gctrl[0x8];
7898         u8         lctrl_input[0x8];
7899         u8         mixer_offset_cm1[0x8];
7900
7901         u8         common_mode[0x6];
7902         u8         reserved_5[0x1];
7903         u8         mixer_offset_cm0[0x9];
7904         u8         reserved_6[0x7];
7905         u8         slicer_offset_cm[0x9];
7906 };
7907
7908 struct mlx5_ifc_slrg_reg_bits {
7909         u8         status[0x4];
7910         u8         version[0x4];
7911         u8         local_port[0x8];
7912         u8         pnat[0x2];
7913         u8         reserved_0[0x2];
7914         u8         lane[0x4];
7915         u8         reserved_1[0x8];
7916
7917         u8         time_to_link_up[0x10];
7918         u8         reserved_2[0xc];
7919         u8         grade_lane_speed[0x4];
7920
7921         u8         grade_version[0x8];
7922         u8         grade[0x18];
7923
7924         u8         reserved_3[0x4];
7925         u8         height_grade_type[0x4];
7926         u8         height_grade[0x18];
7927
7928         u8         height_dz[0x10];
7929         u8         height_dv[0x10];
7930
7931         u8         reserved_4[0x10];
7932         u8         height_sigma[0x10];
7933
7934         u8         reserved_5[0x20];
7935
7936         u8         reserved_6[0x4];
7937         u8         phase_grade_type[0x4];
7938         u8         phase_grade[0x18];
7939
7940         u8         reserved_7[0x8];
7941         u8         phase_eo_pos[0x8];
7942         u8         reserved_8[0x8];
7943         u8         phase_eo_neg[0x8];
7944
7945         u8         ffe_set_tested[0x10];
7946         u8         test_errors_per_lane[0x10];
7947 };
7948
7949 struct mlx5_ifc_pvlc_reg_bits {
7950         u8         reserved_0[0x8];
7951         u8         local_port[0x8];
7952         u8         reserved_1[0x10];
7953
7954         u8         reserved_2[0x1c];
7955         u8         vl_hw_cap[0x4];
7956
7957         u8         reserved_3[0x1c];
7958         u8         vl_admin[0x4];
7959
7960         u8         reserved_4[0x1c];
7961         u8         vl_operational[0x4];
7962 };
7963
7964 struct mlx5_ifc_pude_reg_bits {
7965         u8         swid[0x8];
7966         u8         local_port[0x8];
7967         u8         reserved_0[0x4];
7968         u8         admin_status[0x4];
7969         u8         reserved_1[0x4];
7970         u8         oper_status[0x4];
7971
7972         u8         reserved_2[0x60];
7973 };
7974
7975 enum {
7976         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7977         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7978 };
7979
7980 struct mlx5_ifc_ptys_reg_bits {
7981         u8         reserved_0[0x1];
7982         u8         an_disable_admin[0x1];
7983         u8         an_disable_cap[0x1];
7984         u8         reserved_1[0x4];
7985         u8         force_tx_aba_param[0x1];
7986         u8         local_port[0x8];
7987         u8         reserved_2[0xd];
7988         u8         proto_mask[0x3];
7989
7990         u8         an_status[0x4];
7991         u8         reserved_3[0xc];
7992         u8         data_rate_oper[0x10];
7993
7994         u8         ext_eth_proto_capability[0x20];
7995
7996         u8         eth_proto_capability[0x20];
7997
7998         u8         ib_link_width_capability[0x10];
7999         u8         ib_proto_capability[0x10];
8000
8001         u8         ext_eth_proto_admin[0x20];
8002
8003         u8         eth_proto_admin[0x20];
8004
8005         u8         ib_link_width_admin[0x10];
8006         u8         ib_proto_admin[0x10];
8007
8008         u8         ext_eth_proto_oper[0x20];
8009
8010         u8         eth_proto_oper[0x20];
8011
8012         u8         ib_link_width_oper[0x10];
8013         u8         ib_proto_oper[0x10];
8014
8015         u8         reserved_4[0x1c];
8016         u8         connector_type[0x4];
8017
8018         u8         eth_proto_lp_advertise[0x20];
8019
8020         u8         reserved_5[0x60];
8021 };
8022
8023 struct mlx5_ifc_ptas_reg_bits {
8024         u8         reserved_0[0x20];
8025
8026         u8         algorithm_options[0x10];
8027         u8         reserved_1[0x4];
8028         u8         repetitions_mode[0x4];
8029         u8         num_of_repetitions[0x8];
8030
8031         u8         grade_version[0x8];
8032         u8         height_grade_type[0x4];
8033         u8         phase_grade_type[0x4];
8034         u8         height_grade_weight[0x8];
8035         u8         phase_grade_weight[0x8];
8036
8037         u8         gisim_measure_bits[0x10];
8038         u8         adaptive_tap_measure_bits[0x10];
8039
8040         u8         ber_bath_high_error_threshold[0x10];
8041         u8         ber_bath_mid_error_threshold[0x10];
8042
8043         u8         ber_bath_low_error_threshold[0x10];
8044         u8         one_ratio_high_threshold[0x10];
8045
8046         u8         one_ratio_high_mid_threshold[0x10];
8047         u8         one_ratio_low_mid_threshold[0x10];
8048
8049         u8         one_ratio_low_threshold[0x10];
8050         u8         ndeo_error_threshold[0x10];
8051
8052         u8         mixer_offset_step_size[0x10];
8053         u8         reserved_2[0x8];
8054         u8         mix90_phase_for_voltage_bath[0x8];
8055
8056         u8         mixer_offset_start[0x10];
8057         u8         mixer_offset_end[0x10];
8058
8059         u8         reserved_3[0x15];
8060         u8         ber_test_time[0xb];
8061 };
8062
8063 struct mlx5_ifc_pspa_reg_bits {
8064         u8         swid[0x8];
8065         u8         local_port[0x8];
8066         u8         sub_port[0x8];
8067         u8         reserved_0[0x8];
8068
8069         u8         reserved_1[0x20];
8070 };
8071
8072 struct mlx5_ifc_ppsc_reg_bits {
8073         u8         reserved_0[0x8];
8074         u8         local_port[0x8];
8075         u8         reserved_1[0x10];
8076
8077         u8         reserved_2[0x60];
8078
8079         u8         reserved_3[0x1c];
8080         u8         wrps_admin[0x4];
8081
8082         u8         reserved_4[0x1c];
8083         u8         wrps_status[0x4];
8084
8085         u8         up_th_vld[0x1];
8086         u8         down_th_vld[0x1];
8087         u8         reserved_5[0x6];
8088         u8         up_threshold[0x8];
8089         u8         reserved_6[0x8];
8090         u8         down_threshold[0x8];
8091
8092         u8         reserved_7[0x20];
8093
8094         u8         reserved_8[0x1c];
8095         u8         srps_admin[0x4];
8096
8097         u8         reserved_9[0x60];
8098 };
8099
8100 struct mlx5_ifc_pplr_reg_bits {
8101         u8         reserved_0[0x8];
8102         u8         local_port[0x8];
8103         u8         reserved_1[0x10];
8104
8105         u8         reserved_2[0x8];
8106         u8         lb_cap[0x8];
8107         u8         reserved_3[0x8];
8108         u8         lb_en[0x8];
8109 };
8110
8111 struct mlx5_ifc_pplm_reg_bits {
8112         u8         reserved_at_0[0x8];
8113         u8         local_port[0x8];
8114         u8         reserved_at_10[0x10];
8115
8116         u8         reserved_at_20[0x20];
8117
8118         u8         port_profile_mode[0x8];
8119         u8         static_port_profile[0x8];
8120         u8         active_port_profile[0x8];
8121         u8         reserved_at_58[0x8];
8122
8123         u8         retransmission_active[0x8];
8124         u8         fec_mode_active[0x18];
8125
8126         u8         rs_fec_correction_bypass_cap[0x4];
8127         u8         reserved_at_84[0x8];
8128         u8         fec_override_cap_56g[0x4];
8129         u8         fec_override_cap_100g[0x4];
8130         u8         fec_override_cap_50g[0x4];
8131         u8         fec_override_cap_25g[0x4];
8132         u8         fec_override_cap_10g_40g[0x4];
8133
8134         u8         rs_fec_correction_bypass_admin[0x4];
8135         u8         reserved_at_a4[0x8];
8136         u8         fec_override_admin_56g[0x4];
8137         u8         fec_override_admin_100g[0x4];
8138         u8         fec_override_admin_50g[0x4];
8139         u8         fec_override_admin_25g[0x4];
8140         u8         fec_override_admin_10g_40g[0x4];
8141
8142         u8         fec_override_cap_400g_8x[0x10];
8143         u8         fec_override_cap_200g_4x[0x10];
8144         u8         fec_override_cap_100g_2x[0x10];
8145         u8         fec_override_cap_50g_1x[0x10];
8146
8147         u8         fec_override_admin_400g_8x[0x10];
8148         u8         fec_override_admin_200g_4x[0x10];
8149         u8         fec_override_admin_100g_2x[0x10];
8150         u8         fec_override_admin_50g_1x[0x10];
8151
8152         u8         reserved_at_140[0xC0];
8153 };
8154
8155 struct mlx5_ifc_ppll_reg_bits {
8156         u8         num_pll_groups[0x8];
8157         u8         pll_group[0x8];
8158         u8         reserved_0[0x4];
8159         u8         num_plls[0x4];
8160         u8         reserved_1[0x8];
8161
8162         u8         reserved_2[0x1f];
8163         u8         ae[0x1];
8164
8165         u8         pll_status[4][0x40];
8166 };
8167
8168 struct mlx5_ifc_ppad_reg_bits {
8169         u8         reserved_0[0x3];
8170         u8         single_mac[0x1];
8171         u8         reserved_1[0x4];
8172         u8         local_port[0x8];
8173         u8         mac_47_32[0x10];
8174
8175         u8         mac_31_0[0x20];
8176
8177         u8         reserved_2[0x40];
8178 };
8179
8180 struct mlx5_ifc_pmtu_reg_bits {
8181         u8         reserved_0[0x8];
8182         u8         local_port[0x8];
8183         u8         reserved_1[0x10];
8184
8185         u8         max_mtu[0x10];
8186         u8         reserved_2[0x10];
8187
8188         u8         admin_mtu[0x10];
8189         u8         reserved_3[0x10];
8190
8191         u8         oper_mtu[0x10];
8192         u8         reserved_4[0x10];
8193 };
8194
8195 struct mlx5_ifc_pmpr_reg_bits {
8196         u8         reserved_0[0x8];
8197         u8         module[0x8];
8198         u8         reserved_1[0x10];
8199
8200         u8         reserved_2[0x18];
8201         u8         attenuation_5g[0x8];
8202
8203         u8         reserved_3[0x18];
8204         u8         attenuation_7g[0x8];
8205
8206         u8         reserved_4[0x18];
8207         u8         attenuation_12g[0x8];
8208 };
8209
8210 struct mlx5_ifc_pmpe_reg_bits {
8211         u8         reserved_0[0x8];
8212         u8         module[0x8];
8213         u8         reserved_1[0xc];
8214         u8         module_status[0x4];
8215
8216         u8         reserved_2[0x14];
8217         u8         error_type[0x4];
8218         u8         reserved_3[0x8];
8219
8220         u8         reserved_4[0x40];
8221 };
8222
8223 struct mlx5_ifc_pmpc_reg_bits {
8224         u8         module_state_updated[32][0x8];
8225 };
8226
8227 struct mlx5_ifc_pmlpn_reg_bits {
8228         u8         reserved_0[0x4];
8229         u8         mlpn_status[0x4];
8230         u8         local_port[0x8];
8231         u8         reserved_1[0x10];
8232
8233         u8         e[0x1];
8234         u8         reserved_2[0x1f];
8235 };
8236
8237 struct mlx5_ifc_pmlp_reg_bits {
8238         u8         rxtx[0x1];
8239         u8         reserved_0[0x7];
8240         u8         local_port[0x8];
8241         u8         reserved_1[0x8];
8242         u8         width[0x8];
8243
8244         u8         lane0_module_mapping[0x20];
8245
8246         u8         lane1_module_mapping[0x20];
8247
8248         u8         lane2_module_mapping[0x20];
8249
8250         u8         lane3_module_mapping[0x20];
8251
8252         u8         reserved_2[0x160];
8253 };
8254
8255 struct mlx5_ifc_pmaos_reg_bits {
8256         u8         reserved_0[0x8];
8257         u8         module[0x8];
8258         u8         reserved_1[0x4];
8259         u8         admin_status[0x4];
8260         u8         reserved_2[0x4];
8261         u8         oper_status[0x4];
8262
8263         u8         ase[0x1];
8264         u8         ee[0x1];
8265         u8         reserved_3[0x12];
8266         u8         error_type[0x4];
8267         u8         reserved_4[0x6];
8268         u8         e[0x2];
8269
8270         u8         reserved_5[0x40];
8271 };
8272
8273 struct mlx5_ifc_plpc_reg_bits {
8274         u8         reserved_0[0x4];
8275         u8         profile_id[0xc];
8276         u8         reserved_1[0x4];
8277         u8         proto_mask[0x4];
8278         u8         reserved_2[0x8];
8279
8280         u8         reserved_3[0x10];
8281         u8         lane_speed[0x10];
8282
8283         u8         reserved_4[0x17];
8284         u8         lpbf[0x1];
8285         u8         fec_mode_policy[0x8];
8286
8287         u8         retransmission_capability[0x8];
8288         u8         fec_mode_capability[0x18];
8289
8290         u8         retransmission_support_admin[0x8];
8291         u8         fec_mode_support_admin[0x18];
8292
8293         u8         retransmission_request_admin[0x8];
8294         u8         fec_mode_request_admin[0x18];
8295
8296         u8         reserved_5[0x80];
8297 };
8298
8299 struct mlx5_ifc_pll_status_data_bits {
8300         u8         reserved_0[0x1];
8301         u8         lock_cal[0x1];
8302         u8         lock_status[0x2];
8303         u8         reserved_1[0x2];
8304         u8         algo_f_ctrl[0xa];
8305         u8         analog_algo_num_var[0x6];
8306         u8         f_ctrl_measure[0xa];
8307
8308         u8         reserved_2[0x2];
8309         u8         analog_var[0x6];
8310         u8         reserved_3[0x2];
8311         u8         high_var[0x6];
8312         u8         reserved_4[0x2];
8313         u8         low_var[0x6];
8314         u8         reserved_5[0x2];
8315         u8         mid_val[0x6];
8316 };
8317
8318 struct mlx5_ifc_plib_reg_bits {
8319         u8         reserved_0[0x8];
8320         u8         local_port[0x8];
8321         u8         reserved_1[0x8];
8322         u8         ib_port[0x8];
8323
8324         u8         reserved_2[0x60];
8325 };
8326
8327 struct mlx5_ifc_plbf_reg_bits {
8328         u8         reserved_0[0x8];
8329         u8         local_port[0x8];
8330         u8         reserved_1[0xd];
8331         u8         lbf_mode[0x3];
8332
8333         u8         reserved_2[0x20];
8334 };
8335
8336 struct mlx5_ifc_pipg_reg_bits {
8337         u8         reserved_0[0x8];
8338         u8         local_port[0x8];
8339         u8         reserved_1[0x10];
8340
8341         u8         dic[0x1];
8342         u8         reserved_2[0x19];
8343         u8         ipg[0x4];
8344         u8         reserved_3[0x2];
8345 };
8346
8347 struct mlx5_ifc_pifr_reg_bits {
8348         u8         reserved_0[0x8];
8349         u8         local_port[0x8];
8350         u8         reserved_1[0x10];
8351
8352         u8         reserved_2[0xe0];
8353
8354         u8         port_filter[8][0x20];
8355
8356         u8         port_filter_update_en[8][0x20];
8357 };
8358
8359 struct mlx5_ifc_phys_layer_cntrs_bits {
8360         u8         time_since_last_clear_high[0x20];
8361
8362         u8         time_since_last_clear_low[0x20];
8363
8364         u8         symbol_errors_high[0x20];
8365
8366         u8         symbol_errors_low[0x20];
8367
8368         u8         sync_headers_errors_high[0x20];
8369
8370         u8         sync_headers_errors_low[0x20];
8371
8372         u8         edpl_bip_errors_lane0_high[0x20];
8373
8374         u8         edpl_bip_errors_lane0_low[0x20];
8375
8376         u8         edpl_bip_errors_lane1_high[0x20];
8377
8378         u8         edpl_bip_errors_lane1_low[0x20];
8379
8380         u8         edpl_bip_errors_lane2_high[0x20];
8381
8382         u8         edpl_bip_errors_lane2_low[0x20];
8383
8384         u8         edpl_bip_errors_lane3_high[0x20];
8385
8386         u8         edpl_bip_errors_lane3_low[0x20];
8387
8388         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8389
8390         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8391
8392         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8393
8394         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8395
8396         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8397
8398         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8399
8400         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8401
8402         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8403
8404         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8405
8406         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8407
8408         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8409
8410         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8411
8412         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8413
8414         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8415
8416         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8417
8418         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8419
8420         u8         rs_fec_corrected_blocks_high[0x20];
8421
8422         u8         rs_fec_corrected_blocks_low[0x20];
8423
8424         u8         rs_fec_uncorrectable_blocks_high[0x20];
8425
8426         u8         rs_fec_uncorrectable_blocks_low[0x20];
8427
8428         u8         rs_fec_no_errors_blocks_high[0x20];
8429
8430         u8         rs_fec_no_errors_blocks_low[0x20];
8431
8432         u8         rs_fec_single_error_blocks_high[0x20];
8433
8434         u8         rs_fec_single_error_blocks_low[0x20];
8435
8436         u8         rs_fec_corrected_symbols_total_high[0x20];
8437
8438         u8         rs_fec_corrected_symbols_total_low[0x20];
8439
8440         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8441
8442         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8443
8444         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8445
8446         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8447
8448         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8449
8450         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8451
8452         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8453
8454         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8455
8456         u8         link_down_events[0x20];
8457
8458         u8         successful_recovery_events[0x20];
8459
8460         u8         reserved_0[0x180];
8461 };
8462
8463 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8464         u8         symbol_error_counter[0x10];
8465
8466         u8         link_error_recovery_counter[0x8];
8467
8468         u8         link_downed_counter[0x8];
8469
8470         u8         port_rcv_errors[0x10];
8471
8472         u8         port_rcv_remote_physical_errors[0x10];
8473
8474         u8         port_rcv_switch_relay_errors[0x10];
8475
8476         u8         port_xmit_discards[0x10];
8477
8478         u8         port_xmit_constraint_errors[0x8];
8479
8480         u8         port_rcv_constraint_errors[0x8];
8481
8482         u8         reserved_at_70[0x8];
8483
8484         u8         link_overrun_errors[0x8];
8485
8486         u8         reserved_at_80[0x10];
8487
8488         u8         vl_15_dropped[0x10];
8489
8490         u8         reserved_at_a0[0xa0];
8491 };
8492
8493 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8494         u8         time_since_last_clear_high[0x20];
8495
8496         u8         time_since_last_clear_low[0x20];
8497
8498         u8         phy_received_bits_high[0x20];
8499
8500         u8         phy_received_bits_low[0x20];
8501
8502         u8         phy_symbol_errors_high[0x20];
8503
8504         u8         phy_symbol_errors_low[0x20];
8505
8506         u8         phy_corrected_bits_high[0x20];
8507
8508         u8         phy_corrected_bits_low[0x20];
8509
8510         u8         phy_corrected_bits_lane0_high[0x20];
8511
8512         u8         phy_corrected_bits_lane0_low[0x20];
8513
8514         u8         phy_corrected_bits_lane1_high[0x20];
8515
8516         u8         phy_corrected_bits_lane1_low[0x20];
8517
8518         u8         phy_corrected_bits_lane2_high[0x20];
8519
8520         u8         phy_corrected_bits_lane2_low[0x20];
8521
8522         u8         phy_corrected_bits_lane3_high[0x20];
8523
8524         u8         phy_corrected_bits_lane3_low[0x20];
8525
8526         u8         reserved_at_200[0x5c0];
8527 };
8528
8529 struct mlx5_ifc_infiniband_port_cntrs_bits {
8530         u8         symbol_error_counter[0x10];
8531         u8         link_error_recovery_counter[0x8];
8532         u8         link_downed_counter[0x8];
8533
8534         u8         port_rcv_errors[0x10];
8535         u8         port_rcv_remote_physical_errors[0x10];
8536
8537         u8         port_rcv_switch_relay_errors[0x10];
8538         u8         port_xmit_discards[0x10];
8539
8540         u8         port_xmit_constraint_errors[0x8];
8541         u8         port_rcv_constraint_errors[0x8];
8542         u8         reserved_0[0x8];
8543         u8         local_link_integrity_errors[0x4];
8544         u8         excessive_buffer_overrun_errors[0x4];
8545
8546         u8         reserved_1[0x10];
8547         u8         vl_15_dropped[0x10];
8548
8549         u8         port_xmit_data[0x20];
8550
8551         u8         port_rcv_data[0x20];
8552
8553         u8         port_xmit_pkts[0x20];
8554
8555         u8         port_rcv_pkts[0x20];
8556
8557         u8         port_xmit_wait[0x20];
8558
8559         u8         reserved_2[0x680];
8560 };
8561
8562 struct mlx5_ifc_phrr_reg_bits {
8563         u8         clr[0x1];
8564         u8         reserved_0[0x7];
8565         u8         local_port[0x8];
8566         u8         reserved_1[0x10];
8567
8568         u8         hist_group[0x8];
8569         u8         reserved_2[0x10];
8570         u8         hist_id[0x8];
8571
8572         u8         reserved_3[0x40];
8573
8574         u8         time_since_last_clear_high[0x20];
8575
8576         u8         time_since_last_clear_low[0x20];
8577
8578         u8         bin[10][0x20];
8579 };
8580
8581 struct mlx5_ifc_phbr_for_prio_reg_bits {
8582         u8         reserved_0[0x18];
8583         u8         prio[0x8];
8584 };
8585
8586 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8587         u8         reserved_0[0x18];
8588         u8         tclass[0x8];
8589 };
8590
8591 struct mlx5_ifc_phbr_binding_reg_bits {
8592         u8         opcode[0x4];
8593         u8         reserved_0[0x4];
8594         u8         local_port[0x8];
8595         u8         pnat[0x2];
8596         u8         reserved_1[0xe];
8597
8598         u8         hist_group[0x8];
8599         u8         reserved_2[0x10];
8600         u8         hist_id[0x8];
8601
8602         u8         reserved_3[0x10];
8603         u8         hist_type[0x10];
8604
8605         u8         hist_parameters[0x20];
8606
8607         u8         hist_min_value[0x20];
8608
8609         u8         hist_max_value[0x20];
8610
8611         u8         sample_time[0x20];
8612 };
8613
8614 enum {
8615         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8616         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8617 };
8618
8619 struct mlx5_ifc_pfcc_reg_bits {
8620         u8         dcbx_operation_type[0x2];
8621         u8         cap_local_admin[0x1];
8622         u8         cap_remote_admin[0x1];
8623         u8         reserved_0[0x4];
8624         u8         local_port[0x8];
8625         u8         pnat[0x2];
8626         u8         reserved_1[0xc];
8627         u8         shl_cap[0x1];
8628         u8         shl_opr[0x1];
8629
8630         u8         ppan[0x4];
8631         u8         reserved_2[0x4];
8632         u8         prio_mask_tx[0x8];
8633         u8         reserved_3[0x8];
8634         u8         prio_mask_rx[0x8];
8635
8636         u8         pptx[0x1];
8637         u8         aptx[0x1];
8638         u8         reserved_4[0x6];
8639         u8         pfctx[0x8];
8640         u8         reserved_5[0x8];
8641         u8         cbftx[0x8];
8642
8643         u8         pprx[0x1];
8644         u8         aprx[0x1];
8645         u8         reserved_6[0x6];
8646         u8         pfcrx[0x8];
8647         u8         reserved_7[0x8];
8648         u8         cbfrx[0x8];
8649
8650         u8         device_stall_minor_watermark[0x10];
8651         u8         device_stall_critical_watermark[0x10];
8652
8653         u8         reserved_8[0x60];
8654 };
8655
8656 struct mlx5_ifc_pelc_reg_bits {
8657         u8         op[0x4];
8658         u8         reserved_0[0x4];
8659         u8         local_port[0x8];
8660         u8         reserved_1[0x10];
8661
8662         u8         op_admin[0x8];
8663         u8         op_capability[0x8];
8664         u8         op_request[0x8];
8665         u8         op_active[0x8];
8666
8667         u8         admin[0x40];
8668
8669         u8         capability[0x40];
8670
8671         u8         request[0x40];
8672
8673         u8         active[0x40];
8674
8675         u8         reserved_2[0x80];
8676 };
8677
8678 struct mlx5_ifc_peir_reg_bits {
8679         u8         reserved_0[0x8];
8680         u8         local_port[0x8];
8681         u8         reserved_1[0x10];
8682
8683         u8         reserved_2[0xc];
8684         u8         error_count[0x4];
8685         u8         reserved_3[0x10];
8686
8687         u8         reserved_4[0xc];
8688         u8         lane[0x4];
8689         u8         reserved_5[0x8];
8690         u8         error_type[0x8];
8691 };
8692
8693 struct mlx5_ifc_qcam_access_reg_cap_mask {
8694         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8695         u8         qpdpm[0x1];
8696         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8697         u8         qdpm[0x1];
8698         u8         qpts[0x1];
8699         u8         qcap[0x1];
8700         u8         qcam_access_reg_cap_mask_0[0x1];
8701 };
8702
8703 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8704         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8705         u8         qpts_trust_both[0x1];
8706 };
8707
8708 struct mlx5_ifc_qcam_reg_bits {
8709         u8         reserved_at_0[0x8];
8710         u8         feature_group[0x8];
8711         u8         reserved_at_10[0x8];
8712         u8         access_reg_group[0x8];
8713         u8         reserved_at_20[0x20];
8714
8715         union {
8716                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8717                 u8  reserved_at_0[0x80];
8718         } qos_access_reg_cap_mask;
8719
8720         u8         reserved_at_c0[0x80];
8721
8722         union {
8723                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8724                 u8  reserved_at_0[0x80];
8725         } qos_feature_cap_mask;
8726
8727         u8         reserved_at_1c0[0x80];
8728 };
8729
8730 struct mlx5_ifc_pcam_enhanced_features_bits {
8731         u8         reserved_at_0[0x6d];
8732         u8         rx_icrc_encapsulated_counter[0x1];
8733         u8         reserved_at_6e[0x4];
8734         u8         ptys_extended_ethernet[0x1];
8735         u8         reserved_at_73[0x3];
8736         u8         pfcc_mask[0x1];
8737         u8         reserved_at_77[0x3];
8738         u8         per_lane_error_counters[0x1];
8739         u8         rx_buffer_fullness_counters[0x1];
8740         u8         ptys_connector_type[0x1];
8741         u8         reserved_at_7d[0x1];
8742         u8         ppcnt_discard_group[0x1];
8743         u8         ppcnt_statistical_group[0x1];
8744 };
8745
8746 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8747         u8         port_access_reg_cap_mask_127_to_96[0x20];
8748         u8         port_access_reg_cap_mask_95_to_64[0x20];
8749
8750         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8751         u8         pplm[0x1];
8752         u8         port_access_reg_cap_mask_34_to_32[0x3];
8753
8754         u8         port_access_reg_cap_mask_31_to_13[0x13];
8755         u8         pbmc[0x1];
8756         u8         pptb[0x1];
8757         u8         port_access_reg_cap_mask_10_to_09[0x2];
8758         u8         ppcnt[0x1];
8759         u8         port_access_reg_cap_mask_07_to_00[0x8];
8760 };
8761
8762 struct mlx5_ifc_pcam_reg_bits {
8763         u8         reserved_at_0[0x8];
8764         u8         feature_group[0x8];
8765         u8         reserved_at_10[0x8];
8766         u8         access_reg_group[0x8];
8767
8768         u8         reserved_at_20[0x20];
8769
8770         union {
8771                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8772                 u8         reserved_at_0[0x80];
8773         } port_access_reg_cap_mask;
8774
8775         u8         reserved_at_c0[0x80];
8776
8777         union {
8778                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8779                 u8         reserved_at_0[0x80];
8780         } feature_cap_mask;
8781
8782         u8         reserved_at_1c0[0xc0];
8783 };
8784
8785 struct mlx5_ifc_mcam_enhanced_features_bits {
8786         u8         reserved_at_0[0x6e];
8787         u8         pcie_status_and_power[0x1];
8788         u8         reserved_at_111[0x10];
8789         u8         pcie_performance_group[0x1];
8790 };
8791
8792 struct mlx5_ifc_mcam_access_reg_bits {
8793         u8         reserved_at_0[0x1c];
8794         u8         mcda[0x1];
8795         u8         mcc[0x1];
8796         u8         mcqi[0x1];
8797         u8         reserved_at_1f[0x1];
8798
8799         u8         regs_95_to_64[0x20];
8800         u8         regs_63_to_32[0x20];
8801         u8         regs_31_to_0[0x20];
8802 };
8803
8804 struct mlx5_ifc_mcam_reg_bits {
8805         u8         reserved_at_0[0x8];
8806         u8         feature_group[0x8];
8807         u8         reserved_at_10[0x8];
8808         u8         access_reg_group[0x8];
8809
8810         u8         reserved_at_20[0x20];
8811
8812         union {
8813                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8814                 u8         reserved_at_0[0x80];
8815         } mng_access_reg_cap_mask;
8816
8817         u8         reserved_at_c0[0x80];
8818
8819         union {
8820                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8821                 u8         reserved_at_0[0x80];
8822         } mng_feature_cap_mask;
8823
8824         u8         reserved_at_1c0[0x80];
8825 };
8826
8827 struct mlx5_ifc_pcap_reg_bits {
8828         u8         reserved_0[0x8];
8829         u8         local_port[0x8];
8830         u8         reserved_1[0x10];
8831
8832         u8         port_capability_mask[4][0x20];
8833 };
8834
8835 struct mlx5_ifc_pbmc_reg_bits {
8836         u8         reserved_at_0[0x8];
8837         u8         local_port[0x8];
8838         u8         reserved_at_10[0x10];
8839
8840         u8         xoff_timer_value[0x10];
8841         u8         xoff_refresh[0x10];
8842
8843         u8         reserved_at_40[0x9];
8844         u8         fullness_threshold[0x7];
8845         u8         port_buffer_size[0x10];
8846
8847         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8848
8849         u8         reserved_at_2e0[0x40];
8850 };
8851
8852 struct mlx5_ifc_paos_reg_bits {
8853         u8         swid[0x8];
8854         u8         local_port[0x8];
8855         u8         reserved_0[0x4];
8856         u8         admin_status[0x4];
8857         u8         reserved_1[0x4];
8858         u8         oper_status[0x4];
8859
8860         u8         ase[0x1];
8861         u8         ee[0x1];
8862         u8         reserved_2[0x1c];
8863         u8         e[0x2];
8864
8865         u8         reserved_3[0x40];
8866 };
8867
8868 struct mlx5_ifc_pamp_reg_bits {
8869         u8         reserved_0[0x8];
8870         u8         opamp_group[0x8];
8871         u8         reserved_1[0xc];
8872         u8         opamp_group_type[0x4];
8873
8874         u8         start_index[0x10];
8875         u8         reserved_2[0x4];
8876         u8         num_of_indices[0xc];
8877
8878         u8         index_data[18][0x10];
8879 };
8880
8881 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8882         u8         llr_rx_cells_high[0x20];
8883
8884         u8         llr_rx_cells_low[0x20];
8885
8886         u8         llr_rx_error_high[0x20];
8887
8888         u8         llr_rx_error_low[0x20];
8889
8890         u8         llr_rx_crc_error_high[0x20];
8891
8892         u8         llr_rx_crc_error_low[0x20];
8893
8894         u8         llr_tx_cells_high[0x20];
8895
8896         u8         llr_tx_cells_low[0x20];
8897
8898         u8         llr_tx_ret_cells_high[0x20];
8899
8900         u8         llr_tx_ret_cells_low[0x20];
8901
8902         u8         llr_tx_ret_events_high[0x20];
8903
8904         u8         llr_tx_ret_events_low[0x20];
8905
8906         u8         reserved_0[0x640];
8907 };
8908
8909 struct mlx5_ifc_mtmp_reg_bits {
8910         u8         i[0x1];
8911         u8         reserved_at_1[0x18];
8912         u8         sensor_index[0x7];
8913
8914         u8         reserved_at_20[0x10];
8915         u8         temperature[0x10];
8916
8917         u8         mte[0x1];
8918         u8         mtr[0x1];
8919         u8         reserved_at_42[0x0e];
8920         u8         max_temperature[0x10];
8921
8922         u8         tee[0x2];
8923         u8         reserved_at_62[0x0e];
8924         u8         temperature_threshold_hi[0x10];
8925
8926         u8         reserved_at_80[0x10];
8927         u8         temperature_threshold_lo[0x10];
8928
8929         u8         reserved_at_100[0x20];
8930
8931         u8         sensor_name[0x40];
8932 };
8933
8934 struct mlx5_ifc_lane_2_module_mapping_bits {
8935         u8         reserved_0[0x6];
8936         u8         rx_lane[0x2];
8937         u8         reserved_1[0x6];
8938         u8         tx_lane[0x2];
8939         u8         reserved_2[0x8];
8940         u8         module[0x8];
8941 };
8942
8943 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8944         u8         transmit_queue_high[0x20];
8945
8946         u8         transmit_queue_low[0x20];
8947
8948         u8         reserved_0[0x780];
8949 };
8950
8951 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8952         u8         no_buffer_discard_uc_high[0x20];
8953
8954         u8         no_buffer_discard_uc_low[0x20];
8955
8956         u8         wred_discard_high[0x20];
8957
8958         u8         wred_discard_low[0x20];
8959
8960         u8         reserved_0[0x740];
8961 };
8962
8963 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8964         u8         rx_octets_high[0x20];
8965
8966         u8         rx_octets_low[0x20];
8967
8968         u8         reserved_0[0xc0];
8969
8970         u8         rx_frames_high[0x20];
8971
8972         u8         rx_frames_low[0x20];
8973
8974         u8         tx_octets_high[0x20];
8975
8976         u8         tx_octets_low[0x20];
8977
8978         u8         reserved_1[0xc0];
8979
8980         u8         tx_frames_high[0x20];
8981
8982         u8         tx_frames_low[0x20];
8983
8984         u8         rx_pause_high[0x20];
8985
8986         u8         rx_pause_low[0x20];
8987
8988         u8         rx_pause_duration_high[0x20];
8989
8990         u8         rx_pause_duration_low[0x20];
8991
8992         u8         tx_pause_high[0x20];
8993
8994         u8         tx_pause_low[0x20];
8995
8996         u8         tx_pause_duration_high[0x20];
8997
8998         u8         tx_pause_duration_low[0x20];
8999
9000         u8         rx_pause_transition_high[0x20];
9001
9002         u8         rx_pause_transition_low[0x20];
9003
9004         u8         rx_discards_high[0x20];
9005
9006         u8         rx_discards_low[0x20];
9007
9008         u8         device_stall_minor_watermark_cnt_high[0x20];
9009
9010         u8         device_stall_minor_watermark_cnt_low[0x20];
9011
9012         u8         device_stall_critical_watermark_cnt_high[0x20];
9013
9014         u8         device_stall_critical_watermark_cnt_low[0x20];
9015
9016         u8         reserved_2[0x340];
9017 };
9018
9019 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9020         u8         port_transmit_wait_high[0x20];
9021
9022         u8         port_transmit_wait_low[0x20];
9023
9024         u8         ecn_marked_high[0x20];
9025
9026         u8         ecn_marked_low[0x20];
9027
9028         u8         no_buffer_discard_mc_high[0x20];
9029
9030         u8         no_buffer_discard_mc_low[0x20];
9031
9032         u8         rx_ebp_high[0x20];
9033
9034         u8         rx_ebp_low[0x20];
9035
9036         u8         tx_ebp_high[0x20];
9037
9038         u8         tx_ebp_low[0x20];
9039
9040         u8         rx_buffer_almost_full_high[0x20];
9041
9042         u8         rx_buffer_almost_full_low[0x20];
9043
9044         u8         rx_buffer_full_high[0x20];
9045
9046         u8         rx_buffer_full_low[0x20];
9047
9048         u8         rx_icrc_encapsulated_high[0x20];
9049
9050         u8         rx_icrc_encapsulated_low[0x20];
9051
9052         u8         reserved_0[0x80];
9053
9054         u8         tx_stats_pkts64octets_high[0x20];
9055
9056         u8         tx_stats_pkts64octets_low[0x20];
9057
9058         u8         tx_stats_pkts65to127octets_high[0x20];
9059
9060         u8         tx_stats_pkts65to127octets_low[0x20];
9061
9062         u8         tx_stats_pkts128to255octets_high[0x20];
9063
9064         u8         tx_stats_pkts128to255octets_low[0x20];
9065
9066         u8         tx_stats_pkts256to511octets_high[0x20];
9067
9068         u8         tx_stats_pkts256to511octets_low[0x20];
9069
9070         u8         tx_stats_pkts512to1023octets_high[0x20];
9071
9072         u8         tx_stats_pkts512to1023octets_low[0x20];
9073
9074         u8         tx_stats_pkts1024to1518octets_high[0x20];
9075
9076         u8         tx_stats_pkts1024to1518octets_low[0x20];
9077
9078         u8         tx_stats_pkts1519to2047octets_high[0x20];
9079
9080         u8         tx_stats_pkts1519to2047octets_low[0x20];
9081
9082         u8         tx_stats_pkts2048to4095octets_high[0x20];
9083
9084         u8         tx_stats_pkts2048to4095octets_low[0x20];
9085
9086         u8         tx_stats_pkts4096to8191octets_high[0x20];
9087
9088         u8         tx_stats_pkts4096to8191octets_low[0x20];
9089
9090         u8         tx_stats_pkts8192to10239octets_high[0x20];
9091
9092         u8         tx_stats_pkts8192to10239octets_low[0x20];
9093
9094         u8         reserved_1[0x2C0];
9095 };
9096
9097 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9098         u8         a_frames_transmitted_ok_high[0x20];
9099
9100         u8         a_frames_transmitted_ok_low[0x20];
9101
9102         u8         a_frames_received_ok_high[0x20];
9103
9104         u8         a_frames_received_ok_low[0x20];
9105
9106         u8         a_frame_check_sequence_errors_high[0x20];
9107
9108         u8         a_frame_check_sequence_errors_low[0x20];
9109
9110         u8         a_alignment_errors_high[0x20];
9111
9112         u8         a_alignment_errors_low[0x20];
9113
9114         u8         a_octets_transmitted_ok_high[0x20];
9115
9116         u8         a_octets_transmitted_ok_low[0x20];
9117
9118         u8         a_octets_received_ok_high[0x20];
9119
9120         u8         a_octets_received_ok_low[0x20];
9121
9122         u8         a_multicast_frames_xmitted_ok_high[0x20];
9123
9124         u8         a_multicast_frames_xmitted_ok_low[0x20];
9125
9126         u8         a_broadcast_frames_xmitted_ok_high[0x20];
9127
9128         u8         a_broadcast_frames_xmitted_ok_low[0x20];
9129
9130         u8         a_multicast_frames_received_ok_high[0x20];
9131
9132         u8         a_multicast_frames_received_ok_low[0x20];
9133
9134         u8         a_broadcast_frames_recieved_ok_high[0x20];
9135
9136         u8         a_broadcast_frames_recieved_ok_low[0x20];
9137
9138         u8         a_in_range_length_errors_high[0x20];
9139
9140         u8         a_in_range_length_errors_low[0x20];
9141
9142         u8         a_out_of_range_length_field_high[0x20];
9143
9144         u8         a_out_of_range_length_field_low[0x20];
9145
9146         u8         a_frame_too_long_errors_high[0x20];
9147
9148         u8         a_frame_too_long_errors_low[0x20];
9149
9150         u8         a_symbol_error_during_carrier_high[0x20];
9151
9152         u8         a_symbol_error_during_carrier_low[0x20];
9153
9154         u8         a_mac_control_frames_transmitted_high[0x20];
9155
9156         u8         a_mac_control_frames_transmitted_low[0x20];
9157
9158         u8         a_mac_control_frames_received_high[0x20];
9159
9160         u8         a_mac_control_frames_received_low[0x20];
9161
9162         u8         a_unsupported_opcodes_received_high[0x20];
9163
9164         u8         a_unsupported_opcodes_received_low[0x20];
9165
9166         u8         a_pause_mac_ctrl_frames_received_high[0x20];
9167
9168         u8         a_pause_mac_ctrl_frames_received_low[0x20];
9169
9170         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9171
9172         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9173
9174         u8         reserved_0[0x300];
9175 };
9176
9177 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9178         u8         dot3stats_alignment_errors_high[0x20];
9179
9180         u8         dot3stats_alignment_errors_low[0x20];
9181
9182         u8         dot3stats_fcs_errors_high[0x20];
9183
9184         u8         dot3stats_fcs_errors_low[0x20];
9185
9186         u8         dot3stats_single_collision_frames_high[0x20];
9187
9188         u8         dot3stats_single_collision_frames_low[0x20];
9189
9190         u8         dot3stats_multiple_collision_frames_high[0x20];
9191
9192         u8         dot3stats_multiple_collision_frames_low[0x20];
9193
9194         u8         dot3stats_sqe_test_errors_high[0x20];
9195
9196         u8         dot3stats_sqe_test_errors_low[0x20];
9197
9198         u8         dot3stats_deferred_transmissions_high[0x20];
9199
9200         u8         dot3stats_deferred_transmissions_low[0x20];
9201
9202         u8         dot3stats_late_collisions_high[0x20];
9203
9204         u8         dot3stats_late_collisions_low[0x20];
9205
9206         u8         dot3stats_excessive_collisions_high[0x20];
9207
9208         u8         dot3stats_excessive_collisions_low[0x20];
9209
9210         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9211
9212         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9213
9214         u8         dot3stats_carrier_sense_errors_high[0x20];
9215
9216         u8         dot3stats_carrier_sense_errors_low[0x20];
9217
9218         u8         dot3stats_frame_too_longs_high[0x20];
9219
9220         u8         dot3stats_frame_too_longs_low[0x20];
9221
9222         u8         dot3stats_internal_mac_receive_errors_high[0x20];
9223
9224         u8         dot3stats_internal_mac_receive_errors_low[0x20];
9225
9226         u8         dot3stats_symbol_errors_high[0x20];
9227
9228         u8         dot3stats_symbol_errors_low[0x20];
9229
9230         u8         dot3control_in_unknown_opcodes_high[0x20];
9231
9232         u8         dot3control_in_unknown_opcodes_low[0x20];
9233
9234         u8         dot3in_pause_frames_high[0x20];
9235
9236         u8         dot3in_pause_frames_low[0x20];
9237
9238         u8         dot3out_pause_frames_high[0x20];
9239
9240         u8         dot3out_pause_frames_low[0x20];
9241
9242         u8         reserved_0[0x3c0];
9243 };
9244
9245 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9246         u8         if_in_octets_high[0x20];
9247
9248         u8         if_in_octets_low[0x20];
9249
9250         u8         if_in_ucast_pkts_high[0x20];
9251
9252         u8         if_in_ucast_pkts_low[0x20];
9253
9254         u8         if_in_discards_high[0x20];
9255
9256         u8         if_in_discards_low[0x20];
9257
9258         u8         if_in_errors_high[0x20];
9259
9260         u8         if_in_errors_low[0x20];
9261
9262         u8         if_in_unknown_protos_high[0x20];
9263
9264         u8         if_in_unknown_protos_low[0x20];
9265
9266         u8         if_out_octets_high[0x20];
9267
9268         u8         if_out_octets_low[0x20];
9269
9270         u8         if_out_ucast_pkts_high[0x20];
9271
9272         u8         if_out_ucast_pkts_low[0x20];
9273
9274         u8         if_out_discards_high[0x20];
9275
9276         u8         if_out_discards_low[0x20];
9277
9278         u8         if_out_errors_high[0x20];
9279
9280         u8         if_out_errors_low[0x20];
9281
9282         u8         if_in_multicast_pkts_high[0x20];
9283
9284         u8         if_in_multicast_pkts_low[0x20];
9285
9286         u8         if_in_broadcast_pkts_high[0x20];
9287
9288         u8         if_in_broadcast_pkts_low[0x20];
9289
9290         u8         if_out_multicast_pkts_high[0x20];
9291
9292         u8         if_out_multicast_pkts_low[0x20];
9293
9294         u8         if_out_broadcast_pkts_high[0x20];
9295
9296         u8         if_out_broadcast_pkts_low[0x20];
9297
9298         u8         reserved_0[0x480];
9299 };
9300
9301 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9302         u8         ether_stats_drop_events_high[0x20];
9303
9304         u8         ether_stats_drop_events_low[0x20];
9305
9306         u8         ether_stats_octets_high[0x20];
9307
9308         u8         ether_stats_octets_low[0x20];
9309
9310         u8         ether_stats_pkts_high[0x20];
9311
9312         u8         ether_stats_pkts_low[0x20];
9313
9314         u8         ether_stats_broadcast_pkts_high[0x20];
9315
9316         u8         ether_stats_broadcast_pkts_low[0x20];
9317
9318         u8         ether_stats_multicast_pkts_high[0x20];
9319
9320         u8         ether_stats_multicast_pkts_low[0x20];
9321
9322         u8         ether_stats_crc_align_errors_high[0x20];
9323
9324         u8         ether_stats_crc_align_errors_low[0x20];
9325
9326         u8         ether_stats_undersize_pkts_high[0x20];
9327
9328         u8         ether_stats_undersize_pkts_low[0x20];
9329
9330         u8         ether_stats_oversize_pkts_high[0x20];
9331
9332         u8         ether_stats_oversize_pkts_low[0x20];
9333
9334         u8         ether_stats_fragments_high[0x20];
9335
9336         u8         ether_stats_fragments_low[0x20];
9337
9338         u8         ether_stats_jabbers_high[0x20];
9339
9340         u8         ether_stats_jabbers_low[0x20];
9341
9342         u8         ether_stats_collisions_high[0x20];
9343
9344         u8         ether_stats_collisions_low[0x20];
9345
9346         u8         ether_stats_pkts64octets_high[0x20];
9347
9348         u8         ether_stats_pkts64octets_low[0x20];
9349
9350         u8         ether_stats_pkts65to127octets_high[0x20];
9351
9352         u8         ether_stats_pkts65to127octets_low[0x20];
9353
9354         u8         ether_stats_pkts128to255octets_high[0x20];
9355
9356         u8         ether_stats_pkts128to255octets_low[0x20];
9357
9358         u8         ether_stats_pkts256to511octets_high[0x20];
9359
9360         u8         ether_stats_pkts256to511octets_low[0x20];
9361
9362         u8         ether_stats_pkts512to1023octets_high[0x20];
9363
9364         u8         ether_stats_pkts512to1023octets_low[0x20];
9365
9366         u8         ether_stats_pkts1024to1518octets_high[0x20];
9367
9368         u8         ether_stats_pkts1024to1518octets_low[0x20];
9369
9370         u8         ether_stats_pkts1519to2047octets_high[0x20];
9371
9372         u8         ether_stats_pkts1519to2047octets_low[0x20];
9373
9374         u8         ether_stats_pkts2048to4095octets_high[0x20];
9375
9376         u8         ether_stats_pkts2048to4095octets_low[0x20];
9377
9378         u8         ether_stats_pkts4096to8191octets_high[0x20];
9379
9380         u8         ether_stats_pkts4096to8191octets_low[0x20];
9381
9382         u8         ether_stats_pkts8192to10239octets_high[0x20];
9383
9384         u8         ether_stats_pkts8192to10239octets_low[0x20];
9385
9386         u8         reserved_0[0x280];
9387 };
9388
9389 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9390         u8         symbol_error_counter[0x10];
9391         u8         link_error_recovery_counter[0x8];
9392         u8         link_downed_counter[0x8];
9393
9394         u8         port_rcv_errors[0x10];
9395         u8         port_rcv_remote_physical_errors[0x10];
9396
9397         u8         port_rcv_switch_relay_errors[0x10];
9398         u8         port_xmit_discards[0x10];
9399
9400         u8         port_xmit_constraint_errors[0x8];
9401         u8         port_rcv_constraint_errors[0x8];
9402         u8         reserved_0[0x8];
9403         u8         local_link_integrity_errors[0x4];
9404         u8         excessive_buffer_overrun_errors[0x4];
9405
9406         u8         reserved_1[0x10];
9407         u8         vl_15_dropped[0x10];
9408
9409         u8         port_xmit_data[0x20];
9410
9411         u8         port_rcv_data[0x20];
9412
9413         u8         port_xmit_pkts[0x20];
9414
9415         u8         port_rcv_pkts[0x20];
9416
9417         u8         port_xmit_wait[0x20];
9418
9419         u8         reserved_2[0x680];
9420 };
9421
9422 struct mlx5_ifc_trc_tlb_reg_bits {
9423         u8         reserved_0[0x80];
9424
9425         u8         tlb_addr[0][0x40];
9426 };
9427
9428 struct mlx5_ifc_trc_read_fifo_reg_bits {
9429         u8         reserved_0[0x10];
9430         u8         requested_event_num[0x10];
9431
9432         u8         reserved_1[0x20];
9433
9434         u8         reserved_2[0x10];
9435         u8         acual_event_num[0x10];
9436
9437         u8         reserved_3[0x20];
9438
9439         u8         event[0][0x40];
9440 };
9441
9442 struct mlx5_ifc_trc_lock_reg_bits {
9443         u8         reserved_0[0x1f];
9444         u8         lock[0x1];
9445
9446         u8         reserved_1[0x60];
9447 };
9448
9449 struct mlx5_ifc_trc_filter_reg_bits {
9450         u8         status[0x1];
9451         u8         reserved_0[0xf];
9452         u8         filter_index[0x10];
9453
9454         u8         reserved_1[0x20];
9455
9456         u8         filter_val[0x20];
9457
9458         u8         reserved_2[0x1a0];
9459 };
9460
9461 struct mlx5_ifc_trc_event_reg_bits {
9462         u8         status[0x1];
9463         u8         reserved_0[0xf];
9464         u8         event_index[0x10];
9465
9466         u8         reserved_1[0x20];
9467
9468         u8         event_id[0x20];
9469
9470         u8         event_selector_val[0x10];
9471         u8         event_selector_size[0x10];
9472
9473         u8         reserved_2[0x180];
9474 };
9475
9476 struct mlx5_ifc_trc_conf_reg_bits {
9477         u8         limit_en[0x1];
9478         u8         reserved_0[0x3];
9479         u8         dump_mode[0x4];
9480         u8         reserved_1[0x15];
9481         u8         state[0x3];
9482
9483         u8         reserved_2[0x20];
9484
9485         u8         limit_event_index[0x20];
9486
9487         u8         mkey[0x20];
9488
9489         u8         fifo_ready_ev_num[0x20];
9490
9491         u8         reserved_3[0x160];
9492 };
9493
9494 struct mlx5_ifc_trc_cap_reg_bits {
9495         u8         reserved_0[0x18];
9496         u8         dump_mode[0x8];
9497
9498         u8         reserved_1[0x20];
9499
9500         u8         num_of_events[0x10];
9501         u8         num_of_filters[0x10];
9502
9503         u8         fifo_size[0x20];
9504
9505         u8         tlb_size[0x10];
9506         u8         event_size[0x10];
9507
9508         u8         reserved_2[0x160];
9509 };
9510
9511 struct mlx5_ifc_set_node_in_bits {
9512         u8         node_description[64][0x8];
9513 };
9514
9515 struct mlx5_ifc_register_power_settings_bits {
9516         u8         reserved_0[0x18];
9517         u8         power_settings_level[0x8];
9518
9519         u8         reserved_1[0x60];
9520 };
9521
9522 struct mlx5_ifc_register_host_endianess_bits {
9523         u8         he[0x1];
9524         u8         reserved_0[0x1f];
9525
9526         u8         reserved_1[0x60];
9527 };
9528
9529 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9530         u8         physical_address[0x40];
9531 };
9532
9533 struct mlx5_ifc_qtct_reg_bits {
9534         u8         operation_type[0x2];
9535         u8         cap_local_admin[0x1];
9536         u8         cap_remote_admin[0x1];
9537         u8         reserved_0[0x4];
9538         u8         port_number[0x8];
9539         u8         reserved_1[0xd];
9540         u8         prio[0x3];
9541
9542         u8         reserved_2[0x1d];
9543         u8         tclass[0x3];
9544 };
9545
9546 struct mlx5_ifc_qpdp_reg_bits {
9547         u8         reserved_0[0x8];
9548         u8         port_number[0x8];
9549         u8         reserved_1[0x10];
9550
9551         u8         reserved_2[0x1d];
9552         u8         pprio[0x3];
9553 };
9554
9555 struct mlx5_ifc_port_info_ro_fields_param_bits {
9556         u8         reserved_0[0x8];
9557         u8         port[0x8];
9558         u8         max_gid[0x10];
9559
9560         u8         reserved_1[0x20];
9561
9562         u8         port_guid[0x40];
9563 };
9564
9565 struct mlx5_ifc_nvqc_reg_bits {
9566         u8         type[0x20];
9567
9568         u8         reserved_0[0x18];
9569         u8         version[0x4];
9570         u8         reserved_1[0x2];
9571         u8         support_wr[0x1];
9572         u8         support_rd[0x1];
9573 };
9574
9575 struct mlx5_ifc_nvia_reg_bits {
9576         u8         reserved_0[0x1d];
9577         u8         target[0x3];
9578
9579         u8         reserved_1[0x20];
9580 };
9581
9582 struct mlx5_ifc_nvdi_reg_bits {
9583         struct mlx5_ifc_config_item_bits configuration_item_header;
9584 };
9585
9586 struct mlx5_ifc_nvda_reg_bits {
9587         struct mlx5_ifc_config_item_bits configuration_item_header;
9588
9589         u8         configuration_item_data[0x20];
9590 };
9591
9592 struct mlx5_ifc_node_info_ro_fields_param_bits {
9593         u8         system_image_guid[0x40];
9594
9595         u8         reserved_0[0x40];
9596
9597         u8         node_guid[0x40];
9598
9599         u8         reserved_1[0x10];
9600         u8         max_pkey[0x10];
9601
9602         u8         reserved_2[0x20];
9603 };
9604
9605 struct mlx5_ifc_ets_tcn_config_reg_bits {
9606         u8         g[0x1];
9607         u8         b[0x1];
9608         u8         r[0x1];
9609         u8         reserved_0[0x9];
9610         u8         group[0x4];
9611         u8         reserved_1[0x9];
9612         u8         bw_allocation[0x7];
9613
9614         u8         reserved_2[0xc];
9615         u8         max_bw_units[0x4];
9616         u8         reserved_3[0x8];
9617         u8         max_bw_value[0x8];
9618 };
9619
9620 struct mlx5_ifc_ets_global_config_reg_bits {
9621         u8         reserved_0[0x2];
9622         u8         r[0x1];
9623         u8         reserved_1[0x1d];
9624
9625         u8         reserved_2[0xc];
9626         u8         max_bw_units[0x4];
9627         u8         reserved_3[0x8];
9628         u8         max_bw_value[0x8];
9629 };
9630
9631 struct mlx5_ifc_qetc_reg_bits {
9632         u8                                         reserved_at_0[0x8];
9633         u8                                         port_number[0x8];
9634         u8                                         reserved_at_10[0x30];
9635
9636         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9637         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9638 };
9639
9640 struct mlx5_ifc_nodnic_mac_filters_bits {
9641         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9642
9643         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9644
9645         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9646
9647         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9648
9649         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9650
9651         u8         reserved_0[0xc0];
9652 };
9653
9654 struct mlx5_ifc_nodnic_gid_filters_bits {
9655         u8         mgid_filter0[16][0x8];
9656
9657         u8         mgid_filter1[16][0x8];
9658
9659         u8         mgid_filter2[16][0x8];
9660
9661         u8         mgid_filter3[16][0x8];
9662 };
9663
9664 enum {
9665         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9666         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9667 };
9668
9669 enum {
9670         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9671         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9672 };
9673
9674 struct mlx5_ifc_nodnic_config_reg_bits {
9675         u8         no_dram_nic_revision[0x8];
9676         u8         hardware_format[0x8];
9677         u8         support_receive_filter[0x1];
9678         u8         support_promisc_filter[0x1];
9679         u8         support_promisc_multicast_filter[0x1];
9680         u8         reserved_0[0x2];
9681         u8         log_working_buffer_size[0x3];
9682         u8         log_pkey_table_size[0x4];
9683         u8         reserved_1[0x3];
9684         u8         num_ports[0x1];
9685
9686         u8         reserved_2[0x2];
9687         u8         log_max_ring_size[0x6];
9688         u8         reserved_3[0x18];
9689
9690         u8         lkey[0x20];
9691
9692         u8         cqe_format[0x4];
9693         u8         reserved_4[0x1c];
9694
9695         u8         node_guid[0x40];
9696
9697         u8         reserved_5[0x740];
9698
9699         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9700
9701         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9702 };
9703
9704 struct mlx5_ifc_vlan_layout_bits {
9705         u8         reserved_0[0x14];
9706         u8         vlan[0xc];
9707
9708         u8         reserved_1[0x20];
9709 };
9710
9711 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9712         u8         reserved_0[0x20];
9713
9714         u8         mkey[0x20];
9715
9716         u8         addressh_63_32[0x20];
9717
9718         u8         addressl_31_0[0x20];
9719 };
9720
9721 struct mlx5_ifc_ud_adrs_vector_bits {
9722         u8         dc_key[0x40];
9723
9724         u8         ext[0x1];
9725         u8         reserved_0[0x7];
9726         u8         destination_qp_dct[0x18];
9727
9728         u8         static_rate[0x4];
9729         u8         sl_eth_prio[0x4];
9730         u8         fl[0x1];
9731         u8         mlid[0x7];
9732         u8         rlid_udp_sport[0x10];
9733
9734         u8         reserved_1[0x20];
9735
9736         u8         rmac_47_16[0x20];
9737
9738         u8         rmac_15_0[0x10];
9739         u8         tclass[0x8];
9740         u8         hop_limit[0x8];
9741
9742         u8         reserved_2[0x1];
9743         u8         grh[0x1];
9744         u8         reserved_3[0x2];
9745         u8         src_addr_index[0x8];
9746         u8         flow_label[0x14];
9747
9748         u8         rgid_rip[16][0x8];
9749 };
9750
9751 struct mlx5_ifc_port_module_event_bits {
9752         u8         reserved_0[0x8];
9753         u8         module[0x8];
9754         u8         reserved_1[0xc];
9755         u8         module_status[0x4];
9756
9757         u8         reserved_2[0x14];
9758         u8         error_type[0x4];
9759         u8         reserved_3[0x8];
9760
9761         u8         reserved_4[0xa0];
9762 };
9763
9764 struct mlx5_ifc_icmd_control_bits {
9765         u8         opcode[0x10];
9766         u8         status[0x8];
9767         u8         reserved_0[0x7];
9768         u8         busy[0x1];
9769 };
9770
9771 struct mlx5_ifc_eqe_bits {
9772         u8         reserved_0[0x8];
9773         u8         event_type[0x8];
9774         u8         reserved_1[0x8];
9775         u8         event_sub_type[0x8];
9776
9777         u8         reserved_2[0xe0];
9778
9779         union mlx5_ifc_event_auto_bits event_data;
9780
9781         u8         reserved_3[0x10];
9782         u8         signature[0x8];
9783         u8         reserved_4[0x7];
9784         u8         owner[0x1];
9785 };
9786
9787 enum {
9788         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9789 };
9790
9791 struct mlx5_ifc_cmd_queue_entry_bits {
9792         u8         type[0x8];
9793         u8         reserved_0[0x18];
9794
9795         u8         input_length[0x20];
9796
9797         u8         input_mailbox_pointer_63_32[0x20];
9798
9799         u8         input_mailbox_pointer_31_9[0x17];
9800         u8         reserved_1[0x9];
9801
9802         u8         command_input_inline_data[16][0x8];
9803
9804         u8         command_output_inline_data[16][0x8];
9805
9806         u8         output_mailbox_pointer_63_32[0x20];
9807
9808         u8         output_mailbox_pointer_31_9[0x17];
9809         u8         reserved_2[0x9];
9810
9811         u8         output_length[0x20];
9812
9813         u8         token[0x8];
9814         u8         signature[0x8];
9815         u8         reserved_3[0x8];
9816         u8         status[0x7];
9817         u8         ownership[0x1];
9818 };
9819
9820 struct mlx5_ifc_cmd_out_bits {
9821         u8         status[0x8];
9822         u8         reserved_0[0x18];
9823
9824         u8         syndrome[0x20];
9825
9826         u8         command_output[0x20];
9827 };
9828
9829 struct mlx5_ifc_cmd_in_bits {
9830         u8         opcode[0x10];
9831         u8         reserved_0[0x10];
9832
9833         u8         reserved_1[0x10];
9834         u8         op_mod[0x10];
9835
9836         u8         command[0][0x20];
9837 };
9838
9839 struct mlx5_ifc_cmd_if_box_bits {
9840         u8         mailbox_data[512][0x8];
9841
9842         u8         reserved_0[0x180];
9843
9844         u8         next_pointer_63_32[0x20];
9845
9846         u8         next_pointer_31_10[0x16];
9847         u8         reserved_1[0xa];
9848
9849         u8         block_number[0x20];
9850
9851         u8         reserved_2[0x8];
9852         u8         token[0x8];
9853         u8         ctrl_signature[0x8];
9854         u8         signature[0x8];
9855 };
9856
9857 struct mlx5_ifc_mtt_bits {
9858         u8         ptag_63_32[0x20];
9859
9860         u8         ptag_31_8[0x18];
9861         u8         reserved_0[0x6];
9862         u8         wr_en[0x1];
9863         u8         rd_en[0x1];
9864 };
9865
9866 struct mlx5_ifc_tls_progress_params_bits {
9867         u8         valid[0x1];
9868         u8         reserved_at_1[0x7];
9869         u8         pd[0x18];
9870
9871         u8         next_record_tcp_sn[0x20];
9872
9873         u8         hw_resync_tcp_sn[0x20];
9874
9875         u8         record_tracker_state[0x2];
9876         u8         auth_state[0x2];
9877         u8         reserved_at_64[0x4];
9878         u8         hw_offset_record_number[0x18];
9879 };
9880
9881 struct mlx5_ifc_tls_static_params_bits {
9882         u8         const_2[0x2];
9883         u8         tls_version[0x4];
9884         u8         const_1[0x2];
9885         u8         reserved_at_8[0x14];
9886         u8         encryption_standard[0x4];
9887
9888         u8         reserved_at_20[0x20];
9889
9890         u8         initial_record_number[0x40];
9891
9892         u8         resync_tcp_sn[0x20];
9893
9894         u8         gcm_iv[0x20];
9895
9896         u8         implicit_iv[0x40];
9897
9898         u8         reserved_at_100[0x8];
9899         u8         dek_index[0x18];
9900
9901         u8         reserved_at_120[0xe0];
9902 };
9903
9904 /* Vendor Specific Capabilities, VSC */
9905 enum {
9906         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9907         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9908         MLX5_VSC_DOMAIN_SCAN_CRSPACE            = 0x7,
9909         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9910 };
9911
9912 struct mlx5_ifc_vendor_specific_cap_bits {
9913         u8         type[0x8];
9914         u8         length[0x8];
9915         u8         next_pointer[0x8];
9916         u8         capability_id[0x8];
9917
9918         u8         status[0x3];
9919         u8         reserved_0[0xd];
9920         u8         space[0x10];
9921
9922         u8         counter[0x20];
9923
9924         u8         semaphore[0x20];
9925
9926         u8         flag[0x1];
9927         u8         reserved_1[0x1];
9928         u8         address[0x1e];
9929
9930         u8         data[0x20];
9931 };
9932
9933 struct mlx5_ifc_vsc_space_bits {
9934         u8 status[0x3];
9935         u8 reserved0[0xd];
9936         u8 space[0x10];
9937 };
9938
9939 struct mlx5_ifc_vsc_addr_bits {
9940         u8 flag[0x1];
9941         u8 reserved0[0x1];
9942         u8 address[0x1e];
9943 };
9944
9945 enum {
9946         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9947         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9948         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9949 };
9950
9951 enum {
9952         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9953         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9954         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9955 };
9956
9957 enum {
9958         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9959         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9960         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9961         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9962         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9963         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9964         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9965         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9966         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9967         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9968         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9969 };
9970
9971 struct mlx5_ifc_initial_seg_bits {
9972         u8         fw_rev_minor[0x10];
9973         u8         fw_rev_major[0x10];
9974
9975         u8         cmd_interface_rev[0x10];
9976         u8         fw_rev_subminor[0x10];
9977
9978         u8         reserved_0[0x40];
9979
9980         u8         cmdq_phy_addr_63_32[0x20];
9981
9982         u8         cmdq_phy_addr_31_12[0x14];
9983         u8         reserved_1[0x2];
9984         u8         nic_interface[0x2];
9985         u8         log_cmdq_size[0x4];
9986         u8         log_cmdq_stride[0x4];
9987
9988         u8         command_doorbell_vector[0x20];
9989
9990         u8         reserved_2[0xf00];
9991
9992         u8         initializing[0x1];
9993         u8         reserved_3[0x4];
9994         u8         nic_interface_supported[0x3];
9995         u8         reserved_4[0x18];
9996
9997         struct mlx5_ifc_health_buffer_bits health_buffer;
9998
9999         u8         no_dram_nic_offset[0x20];
10000
10001         u8         reserved_5[0x6de0];
10002
10003         u8         internal_timer_h[0x20];
10004
10005         u8         internal_timer_l[0x20];
10006
10007         u8         reserved_6[0x20];
10008
10009         u8         reserved_7[0x1f];
10010         u8         clear_int[0x1];
10011
10012         u8         health_syndrome[0x8];
10013         u8         health_counter[0x18];
10014
10015         u8         reserved_8[0x17fc0];
10016 };
10017
10018 union mlx5_ifc_icmd_interface_document_bits {
10019         struct mlx5_ifc_fw_version_bits fw_version;
10020         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10021         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10022         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10023         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10024         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10025         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10026         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10027         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10028         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10029         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10030         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10031         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10032         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10033         u8         reserved_0[0x42c0];
10034 };
10035
10036 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10037         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10038         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10039         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10040         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10041         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10042         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10043         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10044         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10045         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10046         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10047         u8         reserved_0[0x7c0];
10048 };
10049
10050 struct mlx5_ifc_ppcnt_reg_bits {
10051         u8         swid[0x8];
10052         u8         local_port[0x8];
10053         u8         pnat[0x2];
10054         u8         reserved_0[0x8];
10055         u8         grp[0x6];
10056
10057         u8         clr[0x1];
10058         u8         reserved_1[0x1c];
10059         u8         prio_tc[0x3];
10060
10061         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10062 };
10063
10064 struct mlx5_ifc_pcie_lanes_counters_bits {
10065         u8         life_time_counter_high[0x20];
10066
10067         u8         life_time_counter_low[0x20];
10068
10069         u8         error_counter_lane0[0x20];
10070
10071         u8         error_counter_lane1[0x20];
10072
10073         u8         error_counter_lane2[0x20];
10074
10075         u8         error_counter_lane3[0x20];
10076
10077         u8         error_counter_lane4[0x20];
10078
10079         u8         error_counter_lane5[0x20];
10080
10081         u8         error_counter_lane6[0x20];
10082
10083         u8         error_counter_lane7[0x20];
10084
10085         u8         error_counter_lane8[0x20];
10086
10087         u8         error_counter_lane9[0x20];
10088
10089         u8         error_counter_lane10[0x20];
10090
10091         u8         error_counter_lane11[0x20];
10092
10093         u8         error_counter_lane12[0x20];
10094
10095         u8         error_counter_lane13[0x20];
10096
10097         u8         error_counter_lane14[0x20];
10098
10099         u8         error_counter_lane15[0x20];
10100
10101         u8         reserved_at_240[0x580];
10102 };
10103
10104 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10105         u8         reserved_at_0[0x40];
10106
10107         u8         error_counter_lane0[0x20];
10108
10109         u8         error_counter_lane1[0x20];
10110
10111         u8         error_counter_lane2[0x20];
10112
10113         u8         error_counter_lane3[0x20];
10114
10115         u8         error_counter_lane4[0x20];
10116
10117         u8         error_counter_lane5[0x20];
10118
10119         u8         error_counter_lane6[0x20];
10120
10121         u8         error_counter_lane7[0x20];
10122
10123         u8         error_counter_lane8[0x20];
10124
10125         u8         error_counter_lane9[0x20];
10126
10127         u8         error_counter_lane10[0x20];
10128
10129         u8         error_counter_lane11[0x20];
10130
10131         u8         error_counter_lane12[0x20];
10132
10133         u8         error_counter_lane13[0x20];
10134
10135         u8         error_counter_lane14[0x20];
10136
10137         u8         error_counter_lane15[0x20];
10138
10139         u8         reserved_at_240[0x580];
10140 };
10141
10142 struct mlx5_ifc_pcie_perf_counters_bits {
10143         u8         life_time_counter_high[0x20];
10144
10145         u8         life_time_counter_low[0x20];
10146
10147         u8         rx_errors[0x20];
10148
10149         u8         tx_errors[0x20];
10150
10151         u8         l0_to_recovery_eieos[0x20];
10152
10153         u8         l0_to_recovery_ts[0x20];
10154
10155         u8         l0_to_recovery_framing[0x20];
10156
10157         u8         l0_to_recovery_retrain[0x20];
10158
10159         u8         crc_error_dllp[0x20];
10160
10161         u8         crc_error_tlp[0x20];
10162
10163         u8         tx_overflow_buffer_pkt[0x40];
10164
10165         u8         outbound_stalled_reads[0x20];
10166
10167         u8         outbound_stalled_writes[0x20];
10168
10169         u8         outbound_stalled_reads_events[0x20];
10170
10171         u8         outbound_stalled_writes_events[0x20];
10172
10173         u8         tx_overflow_buffer_marked_pkt[0x40];
10174
10175         u8         reserved_at_240[0x580];
10176 };
10177
10178 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10179         u8         reserved_at_0[0x40];
10180
10181         u8         rx_errors[0x20];
10182
10183         u8         tx_errors[0x20];
10184
10185         u8         reserved_at_80[0xc0];
10186
10187         u8         tx_overflow_buffer_pkt[0x40];
10188
10189         u8         outbound_stalled_reads[0x20];
10190
10191         u8         outbound_stalled_writes[0x20];
10192
10193         u8         outbound_stalled_reads_events[0x20];
10194
10195         u8         outbound_stalled_writes_events[0x20];
10196
10197         u8         tx_overflow_buffer_marked_pkt[0x40];
10198
10199         u8         reserved_at_240[0x580];
10200 };
10201
10202 struct mlx5_ifc_pcie_timers_states_bits {
10203         u8         life_time_counter_high[0x20];
10204
10205         u8         life_time_counter_low[0x20];
10206
10207         u8         time_to_boot_image_start[0x20];
10208
10209         u8         time_to_link_image[0x20];
10210
10211         u8         calibration_time[0x20];
10212
10213         u8         time_to_first_perst[0x20];
10214
10215         u8         time_to_detect_state[0x20];
10216
10217         u8         time_to_l0[0x20];
10218
10219         u8         time_to_crs_en[0x20];
10220
10221         u8         time_to_plastic_image_start[0x20];
10222
10223         u8         time_to_iron_image_start[0x20];
10224
10225         u8         perst_handler[0x20];
10226
10227         u8         times_in_l1[0x20];
10228
10229         u8         times_in_l23[0x20];
10230
10231         u8         dl_down[0x20];
10232
10233         u8         config_cycle1usec[0x20];
10234
10235         u8         config_cycle2to7usec[0x20];
10236
10237         u8         config_cycle8to15usec[0x20];
10238
10239         u8         config_cycle16to63usec[0x20];
10240
10241         u8         config_cycle64usec[0x20];
10242
10243         u8         correctable_err_msg_sent[0x20];
10244
10245         u8         non_fatal_err_msg_sent[0x20];
10246
10247         u8         fatal_err_msg_sent[0x20];
10248
10249         u8         reserved_at_2e0[0x4e0];
10250 };
10251
10252 struct mlx5_ifc_pcie_timers_states_ext_bits {
10253         u8         reserved_at_0[0x40];
10254
10255         u8         time_to_boot_image_start[0x20];
10256
10257         u8         time_to_link_image[0x20];
10258
10259         u8         calibration_time[0x20];
10260
10261         u8         time_to_first_perst[0x20];
10262
10263         u8         time_to_detect_state[0x20];
10264
10265         u8         time_to_l0[0x20];
10266
10267         u8         time_to_crs_en[0x20];
10268
10269         u8         time_to_plastic_image_start[0x20];
10270
10271         u8         time_to_iron_image_start[0x20];
10272
10273         u8         perst_handler[0x20];
10274
10275         u8         times_in_l1[0x20];
10276
10277         u8         times_in_l23[0x20];
10278
10279         u8         dl_down[0x20];
10280
10281         u8         config_cycle1usec[0x20];
10282
10283         u8         config_cycle2to7usec[0x20];
10284
10285         u8         config_cycle8to15usec[0x20];
10286
10287         u8         config_cycle16to63usec[0x20];
10288
10289         u8         config_cycle64usec[0x20];
10290
10291         u8         correctable_err_msg_sent[0x20];
10292
10293         u8         non_fatal_err_msg_sent[0x20];
10294
10295         u8         fatal_err_msg_sent[0x20];
10296
10297         u8         reserved_at_2e0[0x4e0];
10298 };
10299
10300 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10301         struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10302         struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10303         struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10304         u8         reserved_at_0[0x7c0];
10305 };
10306
10307 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10308         struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10309         struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10310         struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10311         u8         reserved_at_0[0x7c0];
10312 };
10313
10314 struct mlx5_ifc_mpcnt_reg_bits {
10315         u8         reserved_at_0[0x2];
10316         u8         depth[0x6];
10317         u8         pcie_index[0x8];
10318         u8         node[0x8];
10319         u8         reserved_at_18[0x2];
10320         u8         grp[0x6];
10321
10322         u8         clr[0x1];
10323         u8         reserved_at_21[0x1f];
10324
10325         union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10326 };
10327
10328 struct mlx5_ifc_mpcnt_reg_ext_bits {
10329         u8         reserved_at_0[0x2];
10330         u8         depth[0x6];
10331         u8         pcie_index[0x8];
10332         u8         node[0x8];
10333         u8         reserved_at_18[0x2];
10334         u8         grp[0x6];
10335
10336         u8         clr[0x1];
10337         u8         reserved_at_21[0x1f];
10338
10339         union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10340 };
10341
10342 enum {
10343         MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10344         MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10345         MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10346         MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10347 };
10348
10349 struct mlx5_ifc_mpein_reg_bits {
10350         u8         reserved_at_0[0x2];
10351         u8         depth[0x6];
10352         u8         pcie_index[0x8];
10353         u8         node[0x8];
10354         u8         reserved_at_18[0x8];
10355
10356         u8         capability_mask[0x20];
10357
10358         u8         reserved_at_40[0x8];
10359         u8         link_width_enabled[0x8];
10360         u8         link_speed_enabled[0x10];
10361
10362         u8         lane0_physical_position[0x8];
10363         u8         link_width_active[0x8];
10364         u8         link_speed_active[0x10];
10365
10366         u8         num_of_pfs[0x10];
10367         u8         num_of_vfs[0x10];
10368
10369         u8         bdf0[0x10];
10370         u8         reserved_at_b0[0x10];
10371
10372         u8         max_read_request_size[0x4];
10373         u8         max_payload_size[0x4];
10374         u8         reserved_at_c8[0x5];
10375         u8         pwr_status[0x3];
10376         u8         port_type[0x4];
10377         u8         reserved_at_d4[0xb];
10378         u8         lane_reversal[0x1];
10379
10380         u8         reserved_at_e0[0x14];
10381         u8         pci_power[0xc];
10382
10383         u8         reserved_at_100[0x20];
10384
10385         u8         device_status[0x10];
10386         u8         port_state[0x8];
10387         u8         reserved_at_138[0x8];
10388
10389         u8         reserved_at_140[0x10];
10390         u8         receiver_detect_result[0x10];
10391
10392         u8         reserved_at_160[0x20];
10393 };
10394
10395 struct mlx5_ifc_mpein_reg_ext_bits {
10396         u8         reserved_at_0[0x2];
10397         u8         depth[0x6];
10398         u8         pcie_index[0x8];
10399         u8         node[0x8];
10400         u8         reserved_at_18[0x8];
10401
10402         u8         reserved_at_20[0x20];
10403
10404         u8         reserved_at_40[0x8];
10405         u8         link_width_enabled[0x8];
10406         u8         link_speed_enabled[0x10];
10407
10408         u8         lane0_physical_position[0x8];
10409         u8         link_width_active[0x8];
10410         u8         link_speed_active[0x10];
10411
10412         u8         num_of_pfs[0x10];
10413         u8         num_of_vfs[0x10];
10414
10415         u8         bdf0[0x10];
10416         u8         reserved_at_b0[0x10];
10417
10418         u8         max_read_request_size[0x4];
10419         u8         max_payload_size[0x4];
10420         u8         reserved_at_c8[0x5];
10421         u8         pwr_status[0x3];
10422         u8         port_type[0x4];
10423         u8         reserved_at_d4[0xb];
10424         u8         lane_reversal[0x1];
10425 };
10426
10427 struct mlx5_ifc_mcqi_cap_bits {
10428         u8         supported_info_bitmask[0x20];
10429
10430         u8         component_size[0x20];
10431
10432         u8         max_component_size[0x20];
10433
10434         u8         log_mcda_word_size[0x4];
10435         u8         reserved_at_64[0xc];
10436         u8         mcda_max_write_size[0x10];
10437
10438         u8         rd_en[0x1];
10439         u8         reserved_at_81[0x1];
10440         u8         match_chip_id[0x1];
10441         u8         match_psid[0x1];
10442         u8         check_user_timestamp[0x1];
10443         u8         match_base_guid_mac[0x1];
10444         u8         reserved_at_86[0x1a];
10445 };
10446
10447 struct mlx5_ifc_mcqi_reg_bits {
10448         u8         read_pending_component[0x1];
10449         u8         reserved_at_1[0xf];
10450         u8         component_index[0x10];
10451
10452         u8         reserved_at_20[0x20];
10453
10454         u8         reserved_at_40[0x1b];
10455         u8         info_type[0x5];
10456
10457         u8         info_size[0x20];
10458
10459         u8         offset[0x20];
10460
10461         u8         reserved_at_a0[0x10];
10462         u8         data_size[0x10];
10463
10464         u8         data[0][0x20];
10465 };
10466
10467 struct mlx5_ifc_mcc_reg_bits {
10468         u8         reserved_at_0[0x4];
10469         u8         time_elapsed_since_last_cmd[0xc];
10470         u8         reserved_at_10[0x8];
10471         u8         instruction[0x8];
10472
10473         u8         reserved_at_20[0x10];
10474         u8         component_index[0x10];
10475
10476         u8         reserved_at_40[0x8];
10477         u8         update_handle[0x18];
10478
10479         u8         handle_owner_type[0x4];
10480         u8         handle_owner_host_id[0x4];
10481         u8         reserved_at_68[0x1];
10482         u8         control_progress[0x7];
10483         u8         error_code[0x8];
10484         u8         reserved_at_78[0x4];
10485         u8         control_state[0x4];
10486
10487         u8         component_size[0x20];
10488
10489         u8         reserved_at_a0[0x60];
10490 };
10491
10492 struct mlx5_ifc_mcda_reg_bits {
10493         u8         reserved_at_0[0x8];
10494         u8         update_handle[0x18];
10495
10496         u8         offset[0x20];
10497
10498         u8         reserved_at_40[0x10];
10499         u8         size[0x10];
10500
10501         u8         reserved_at_60[0x20];
10502
10503         u8         data[0][0x20];
10504 };
10505
10506 union mlx5_ifc_ports_control_registers_document_bits {
10507         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10508         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10509         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10510         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10511         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10512         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10513         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10514         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10515         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10516         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10517         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10518         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10519         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10520         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10521         struct mlx5_ifc_paos_reg_bits paos_reg;
10522         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10523         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10524         struct mlx5_ifc_peir_reg_bits peir_reg;
10525         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10526         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10527         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10528         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10529         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10530         struct mlx5_ifc_phrr_reg_bits phrr_reg;
10531         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10532         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10533         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10534         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10535         struct mlx5_ifc_plib_reg_bits plib_reg;
10536         struct mlx5_ifc_pll_status_data_bits pll_status_data;
10537         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10538         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10539         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10540         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10541         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10542         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10543         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10544         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10545         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10546         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10547         struct mlx5_ifc_ppll_reg_bits ppll_reg;
10548         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10549         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10550         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10551         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10552         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10553         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10554         struct mlx5_ifc_pude_reg_bits pude_reg;
10555         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10556         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10557         struct mlx5_ifc_slrp_reg_bits slrp_reg;
10558         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10559         u8         reserved_0[0x7880];
10560 };
10561
10562 union mlx5_ifc_debug_enhancements_document_bits {
10563         struct mlx5_ifc_health_buffer_bits health_buffer;
10564         u8         reserved_0[0x200];
10565 };
10566
10567 union mlx5_ifc_no_dram_nic_document_bits {
10568         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10569         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10570         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10571         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10572         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10573         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10574         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10575         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10576         u8         reserved_0[0x3160];
10577 };
10578
10579 union mlx5_ifc_uplink_pci_interface_document_bits {
10580         struct mlx5_ifc_initial_seg_bits initial_seg;
10581         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10582         u8         reserved_0[0x20120];
10583 };
10584
10585 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10586         u8         e[0x1];
10587         u8         reserved_at_01[0x0b];
10588         u8         prio[0x04];
10589 };
10590
10591 struct mlx5_ifc_qpdpm_reg_bits {
10592         u8                                     reserved_at_0[0x8];
10593         u8                                     local_port[0x8];
10594         u8                                     reserved_at_10[0x10];
10595         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10596 };
10597
10598 struct mlx5_ifc_qpts_reg_bits {
10599         u8         reserved_at_0[0x8];
10600         u8         local_port[0x8];
10601         u8         reserved_at_10[0x2d];
10602         u8         trust_state[0x3];
10603 };
10604
10605 struct mlx5_ifc_mfrl_reg_bits {
10606         u8         reserved_at_0[0x38];
10607         u8         reset_level[0x8];
10608 };
10609
10610 #endif /* MLX5_IFC_H */