sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 enum {
  32         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  33         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  34         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  35         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  36         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  37         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  38         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  39         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  40         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  41         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  42         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  43         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  44         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  45         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  46         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  47         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  48         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  49         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  50         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  51         MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
  52         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  53         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  54         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  55         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  56         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  57         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  58         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  59         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  60         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  61         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
  62 };
  63
  64 enum {
  65         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  66         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  67         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  68         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  69         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  70 };
  71
  72 enum {
  73         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  74 };
  75
  76 enum {
  77         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  78         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  79 };
  80
  81 enum {
  82         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  83         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  84         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  85         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  86         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  87         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  88         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  89         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  90         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  91         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  92         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  93         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  94         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
  95         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
  96         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  97         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  98         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  99         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 100         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 101         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 102         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 103         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 104         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 105         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 106         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 107         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 108         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 109         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 110         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 111         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 112         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 113         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 114         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 115         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 116         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 117         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 118         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 119         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 120         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 121         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 122         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 123         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 124         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 125         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 126         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 127         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 128         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 129         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 130         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 131         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 132         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 133         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 134         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 135         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 136         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 137         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 138         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 139         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 140         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 141         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 142         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 143         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 144         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 145         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 146         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 147         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 148         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 149         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 150         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 151         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 152         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 153         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 154         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 155         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 156         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 157         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 158         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 159         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 160         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 161         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 162         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 163         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 164         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 165         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 166         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 167         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 168         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 169         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 170         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 171         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 172         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 173         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 174         MLX5_CMD_OP_NOP                           = 0x80d,
 175         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 176         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 177         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 178         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 179         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 180         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 181         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 182         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 183         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 184         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 185         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 186         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 187         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 188         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 189         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 190         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 191         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 192         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 193         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 194         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 195         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 196         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 197         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 198         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 199         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 200         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 201         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 202         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 203         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 204         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 205         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 206         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 207         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 208         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 209         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 210         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 211         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 212         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 213         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 214         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 215         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 216         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 217         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 218         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 219         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 220         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 221         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 222         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 223         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 224         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 225         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 226         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 227         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 228         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 229         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 230         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 231         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 232         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 233         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 234         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 235         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 236         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 237         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 238         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 239         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 240         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 241         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 242         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 243         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 244         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 245 };
 246
 247 enum {
 248         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 249         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 250         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 251         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 252         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 253         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 254         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 255         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 256         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 257         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 258         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 259         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 260 };
 261
 262 struct mlx5_ifc_flow_table_fields_supported_bits {
 263         u8         outer_dmac[0x1];
 264         u8         outer_smac[0x1];
 265         u8         outer_ether_type[0x1];
 266         u8         reserved_0[0x1];
 267         u8         outer_first_prio[0x1];
 268         u8         outer_first_cfi[0x1];
 269         u8         outer_first_vid[0x1];
 270         u8         reserved_1[0x1];
 271         u8         outer_second_prio[0x1];
 272         u8         outer_second_cfi[0x1];
 273         u8         outer_second_vid[0x1];
 274         u8         outer_ipv6_flow_label[0x1];
 275         u8         outer_sip[0x1];
 276         u8         outer_dip[0x1];
 277         u8         outer_frag[0x1];
 278         u8         outer_ip_protocol[0x1];
 279         u8         outer_ip_ecn[0x1];
 280         u8         outer_ip_dscp[0x1];
 281         u8         outer_udp_sport[0x1];
 282         u8         outer_udp_dport[0x1];
 283         u8         outer_tcp_sport[0x1];
 284         u8         outer_tcp_dport[0x1];
 285         u8         outer_tcp_flags[0x1];
 286         u8         outer_gre_protocol[0x1];
 287         u8         outer_gre_key[0x1];
 288         u8         outer_vxlan_vni[0x1];
 289         u8         outer_geneve_vni[0x1];
 290         u8         outer_geneve_oam[0x1];
 291         u8         outer_geneve_protocol_type[0x1];
 292         u8         outer_geneve_opt_len[0x1];
 293         u8         reserved_2[0x1];
 294         u8         source_eswitch_port[0x1];
 295
 296         u8         inner_dmac[0x1];
 297         u8         inner_smac[0x1];
 298         u8         inner_ether_type[0x1];
 299         u8         reserved_3[0x1];
 300         u8         inner_first_prio[0x1];
 301         u8         inner_first_cfi[0x1];
 302         u8         inner_first_vid[0x1];
 303         u8         reserved_4[0x1];
 304         u8         inner_second_prio[0x1];
 305         u8         inner_second_cfi[0x1];
 306         u8         inner_second_vid[0x1];
 307         u8         inner_ipv6_flow_label[0x1];
 308         u8         inner_sip[0x1];
 309         u8         inner_dip[0x1];
 310         u8         inner_frag[0x1];
 311         u8         inner_ip_protocol[0x1];
 312         u8         inner_ip_ecn[0x1];
 313         u8         inner_ip_dscp[0x1];
 314         u8         inner_udp_sport[0x1];
 315         u8         inner_udp_dport[0x1];
 316         u8         inner_tcp_sport[0x1];
 317         u8         inner_tcp_dport[0x1];
 318         u8         inner_tcp_flags[0x1];
 319         u8         reserved_5[0x9];
 320
 321         u8         reserved_6[0x1a];
 322         u8         bth_dst_qp[0x1];
 323         u8         reserved_7[0x4];
 324         u8         source_sqn[0x1];
 325
 326         u8         reserved_8[0x20];
 327 };
 328
 329 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 330         u8         ingress_general_high[0x20];
 331
 332         u8         ingress_general_low[0x20];
 333
 334         u8         ingress_policy_engine_high[0x20];
 335
 336         u8         ingress_policy_engine_low[0x20];
 337
 338         u8         ingress_vlan_membership_high[0x20];
 339
 340         u8         ingress_vlan_membership_low[0x20];
 341
 342         u8         ingress_tag_frame_type_high[0x20];
 343
 344         u8         ingress_tag_frame_type_low[0x20];
 345
 346         u8         egress_vlan_membership_high[0x20];
 347
 348         u8         egress_vlan_membership_low[0x20];
 349
 350         u8         loopback_filter_high[0x20];
 351
 352         u8         loopback_filter_low[0x20];
 353
 354         u8         egress_general_high[0x20];
 355
 356         u8         egress_general_low[0x20];
 357
 358         u8         reserved_at_1c0[0x40];
 359
 360         u8         egress_hoq_high[0x20];
 361
 362         u8         egress_hoq_low[0x20];
 363
 364         u8         port_isolation_high[0x20];
 365
 366         u8         port_isolation_low[0x20];
 367
 368         u8         egress_policy_engine_high[0x20];
 369
 370         u8         egress_policy_engine_low[0x20];
 371
 372         u8         ingress_tx_link_down_high[0x20];
 373
 374         u8         ingress_tx_link_down_low[0x20];
 375
 376         u8         egress_stp_filter_high[0x20];
 377
 378         u8         egress_stp_filter_low[0x20];
 379
 380         u8         egress_hoq_stall_high[0x20];
 381
 382         u8         egress_hoq_stall_low[0x20];
 383
 384         u8         reserved_at_340[0x440];
 385 };
 386 struct mlx5_ifc_flow_table_prop_layout_bits {
 387         u8         ft_support[0x1];
 388         u8         flow_tag[0x1];
 389         u8         flow_counter[0x1];
 390         u8         flow_modify_en[0x1];
 391         u8         modify_root[0x1];
 392         u8         identified_miss_table[0x1];
 393         u8         flow_table_modify[0x1];
 394         u8         encap[0x1];
 395         u8         decap[0x1];
 396         u8         reset_root_to_default[0x1];
 397         u8         reserved_at_a[0x16];
 398
 399         u8         reserved_at_20[0x2];
 400         u8         log_max_ft_size[0x6];
 401         u8         reserved_at_28[0x10];
 402         u8         max_ft_level[0x8];
 403
 404         u8         reserved_at_40[0x20];
 405
 406         u8         reserved_at_60[0x18];
 407         u8         log_max_ft_num[0x8];
 408
 409         u8         reserved_at_80[0x10];
 410         u8         log_max_flow_counter[0x8];
 411         u8         log_max_destination[0x8];
 412
 413         u8         reserved_at_a0[0x18];
 414         u8         log_max_flow[0x8];
 415
 416         u8         reserved_at_c0[0x40];
 417
 418         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 419
 420         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 421 };
 422
 423 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 424         u8         send[0x1];
 425         u8         receive[0x1];
 426         u8         write[0x1];
 427         u8         read[0x1];
 428         u8         atomic[0x1];
 429         u8         srq_receive[0x1];
 430         u8         reserved_0[0x1a];
 431 };
 432
 433 struct mlx5_ifc_flow_counter_list_bits {
 434         u8         reserved_0[0x10];
 435         u8         flow_counter_id[0x10];
 436
 437         u8         reserved_1[0x20];
 438 };
 439
 440 enum {
 441         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 442         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 443         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 444         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 445 };
 446
 447 struct mlx5_ifc_dest_format_struct_bits {
 448         u8         destination_type[0x8];
 449         u8         destination_id[0x18];
 450
 451         u8         reserved_0[0x20];
 452 };
 453
 454 struct mlx5_ifc_ipv4_layout_bits {
 455         u8         reserved_at_0[0x60];
 456
 457         u8         ipv4[0x20];
 458 };
 459
 460 struct mlx5_ifc_ipv6_layout_bits {
 461         u8         ipv6[16][0x8];
 462 };
 463
 464 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 465         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 466         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 467         u8         reserved_at_0[0x80];
 468 };
 469
 470 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 471         u8         smac_47_16[0x20];
 472
 473         u8         smac_15_0[0x10];
 474         u8         ethertype[0x10];
 475
 476         u8         dmac_47_16[0x20];
 477
 478         u8         dmac_15_0[0x10];
 479         u8         first_prio[0x3];
 480         u8         first_cfi[0x1];
 481         u8         first_vid[0xc];
 482
 483         u8         ip_protocol[0x8];
 484         u8         ip_dscp[0x6];
 485         u8         ip_ecn[0x2];
 486         u8         cvlan_tag[0x1];
 487         u8         svlan_tag[0x1];
 488         u8         frag[0x1];
 489         u8         reserved_1[0x4];
 490         u8         tcp_flags[0x9];
 491
 492         u8         tcp_sport[0x10];
 493         u8         tcp_dport[0x10];
 494
 495         u8         reserved_2[0x20];
 496
 497         u8         udp_sport[0x10];
 498         u8         udp_dport[0x10];
 499
 500         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 501
 502         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 503 };
 504
 505 struct mlx5_ifc_fte_match_set_misc_bits {
 506         u8         reserved_0[0x8];
 507         u8         source_sqn[0x18];
 508
 509         u8         reserved_1[0x10];
 510         u8         source_port[0x10];
 511
 512         u8         outer_second_prio[0x3];
 513         u8         outer_second_cfi[0x1];
 514         u8         outer_second_vid[0xc];
 515         u8         inner_second_prio[0x3];
 516         u8         inner_second_cfi[0x1];
 517         u8         inner_second_vid[0xc];
 518
 519         u8         outer_second_vlan_tag[0x1];
 520         u8         inner_second_vlan_tag[0x1];
 521         u8         reserved_2[0xe];
 522         u8         gre_protocol[0x10];
 523
 524         u8         gre_key_h[0x18];
 525         u8         gre_key_l[0x8];
 526
 527         u8         vxlan_vni[0x18];
 528         u8         reserved_3[0x8];
 529
 530         u8         geneve_vni[0x18];
 531         u8         reserved4[0x7];
 532         u8         geneve_oam[0x1];
 533
 534         u8         reserved_5[0xc];
 535         u8         outer_ipv6_flow_label[0x14];
 536
 537         u8         reserved_6[0xc];
 538         u8         inner_ipv6_flow_label[0x14];
 539
 540         u8         reserved_7[0xa];
 541         u8         geneve_opt_len[0x6];
 542         u8         geneve_protocol_type[0x10];
 543
 544         u8         reserved_8[0x8];
 545         u8         bth_dst_qp[0x18];
 546
 547         u8         reserved_9[0xa0];
 548 };
 549
 550 struct mlx5_ifc_cmd_pas_bits {
 551         u8         pa_h[0x20];
 552
 553         u8         pa_l[0x14];
 554         u8         reserved_0[0xc];
 555 };
 556
 557 struct mlx5_ifc_uint64_bits {
 558         u8         hi[0x20];
 559
 560         u8         lo[0x20];
 561 };
 562
 563 struct mlx5_ifc_application_prio_entry_bits {
 564         u8         reserved_0[0x8];
 565         u8         priority[0x3];
 566         u8         reserved_1[0x2];
 567         u8         sel[0x3];
 568         u8         protocol_id[0x10];
 569 };
 570
 571 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 572         u8         reserved_0[0x8];
 573         u8         ring_pi[0x10];
 574         u8         reserved_1[0x8];
 575 };
 576
 577 enum {
 578         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 579         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 580         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 581         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 582         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 583         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 584         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 585         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 586         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 587         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 588 };
 589
 590 struct mlx5_ifc_ads_bits {
 591         u8         fl[0x1];
 592         u8         free_ar[0x1];
 593         u8         reserved_0[0xe];
 594         u8         pkey_index[0x10];
 595
 596         u8         reserved_1[0x8];
 597         u8         grh[0x1];
 598         u8         mlid[0x7];
 599         u8         rlid[0x10];
 600
 601         u8         ack_timeout[0x5];
 602         u8         reserved_2[0x3];
 603         u8         src_addr_index[0x8];
 604         u8         log_rtm[0x4];
 605         u8         stat_rate[0x4];
 606         u8         hop_limit[0x8];
 607
 608         u8         reserved_3[0x4];
 609         u8         tclass[0x8];
 610         u8         flow_label[0x14];
 611
 612         u8         rgid_rip[16][0x8];
 613
 614         u8         reserved_4[0x4];
 615         u8         f_dscp[0x1];
 616         u8         f_ecn[0x1];
 617         u8         reserved_5[0x1];
 618         u8         f_eth_prio[0x1];
 619         u8         ecn[0x2];
 620         u8         dscp[0x6];
 621         u8         udp_sport[0x10];
 622
 623         u8         dei_cfi[0x1];
 624         u8         eth_prio[0x3];
 625         u8         sl[0x4];
 626         u8         port[0x8];
 627         u8         rmac_47_32[0x10];
 628
 629         u8         rmac_31_0[0x20];
 630 };
 631
 632 struct mlx5_ifc_diagnostic_counter_cap_bits {
 633         u8         sync[0x1];
 634         u8         reserved_0[0xf];
 635         u8         counter_id[0x10];
 636 };
 637
 638 struct mlx5_ifc_debug_cap_bits {
 639         u8         reserved_0[0x18];
 640         u8         log_max_samples[0x8];
 641
 642         u8         single[0x1];
 643         u8         repetitive[0x1];
 644         u8         health_mon_rx_activity[0x1];
 645         u8         reserved_1[0x15];
 646         u8         log_min_sample_period[0x8];
 647
 648         u8         reserved_2[0x1c0];
 649
 650         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 651 };
 652
 653 struct mlx5_ifc_qos_cap_bits {
 654         u8         packet_pacing[0x1];
 655         u8         esw_scheduling[0x1];
 656         u8         esw_bw_share[0x1];
 657         u8         esw_rate_limit[0x1];
 658         u8         hll[0x1];
 659         u8         packet_pacing_burst_bound[0x1];
 660         u8         reserved_at_6[0x1a];
 661
 662         u8         reserved_at_20[0x20];
 663
 664         u8         packet_pacing_max_rate[0x20];
 665
 666         u8         packet_pacing_min_rate[0x20];
 667
 668         u8         reserved_at_80[0x10];
 669         u8         packet_pacing_rate_table_size[0x10];
 670
 671         u8         esw_element_type[0x10];
 672         u8         esw_tsar_type[0x10];
 673
 674         u8         reserved_at_c0[0x10];
 675         u8         max_qos_para_vport[0x10];
 676
 677         u8         max_tsar_bw_share[0x20];
 678
 679         u8         reserved_at_100[0x700];
 680 };
 681
 682 struct mlx5_ifc_snapshot_cap_bits {
 683         u8         reserved_0[0x1d];
 684         u8         suspend_qp_uc[0x1];
 685         u8         suspend_qp_ud[0x1];
 686         u8         suspend_qp_rc[0x1];
 687
 688         u8         reserved_1[0x1c];
 689         u8         restore_pd[0x1];
 690         u8         restore_uar[0x1];
 691         u8         restore_mkey[0x1];
 692         u8         restore_qp[0x1];
 693
 694         u8         reserved_2[0x1e];
 695         u8         named_mkey[0x1];
 696         u8         named_qp[0x1];
 697
 698         u8         reserved_3[0x7a0];
 699 };
 700
 701 struct mlx5_ifc_e_switch_cap_bits {
 702         u8         vport_svlan_strip[0x1];
 703         u8         vport_cvlan_strip[0x1];
 704         u8         vport_svlan_insert[0x1];
 705         u8         vport_cvlan_insert_if_not_exist[0x1];
 706         u8         vport_cvlan_insert_overwrite[0x1];
 707
 708         u8         reserved_0[0x19];
 709
 710         u8         nic_vport_node_guid_modify[0x1];
 711         u8         nic_vport_port_guid_modify[0x1];
 712
 713         u8         reserved_1[0x7e0];
 714 };
 715
 716 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 717         u8         reserved_0[0x200];
 718
 719         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 720
 721         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 722
 723         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 724
 725         u8         reserved_1[0x7800];
 726 };
 727
 728 struct mlx5_ifc_flow_table_nic_cap_bits {
 729         u8         nic_rx_multi_path_tirs[0x1];
 730         u8         nic_rx_multi_path_tirs_fts[0x1];
 731         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 732         u8         reserved_at_3[0x1fd];
 733
 734         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 735
 736         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 737
 738         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 739
 740         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 741
 742         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 743
 744         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 745
 746         u8         reserved_1[0x7200];
 747 };
 748
 749 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 750         u8         csum_cap[0x1];
 751         u8         vlan_cap[0x1];
 752         u8         lro_cap[0x1];
 753         u8         lro_psh_flag[0x1];
 754         u8         lro_time_stamp[0x1];
 755         u8         lro_max_msg_sz_mode[0x2];
 756         u8         wqe_vlan_insert[0x1];
 757         u8         self_lb_en_modifiable[0x1];
 758         u8         self_lb_mc[0x1];
 759         u8         self_lb_uc[0x1];
 760         u8         max_lso_cap[0x5];
 761         u8         multi_pkt_send_wqe[0x2];
 762         u8         wqe_inline_mode[0x2];
 763         u8         rss_ind_tbl_cap[0x4];
 764         u8         scatter_fcs[0x1];
 765         u8         reserved_1[0x2];
 766         u8         tunnel_lso_const_out_ip_id[0x1];
 767         u8         tunnel_lro_gre[0x1];
 768         u8         tunnel_lro_vxlan[0x1];
 769         u8         tunnel_statless_gre[0x1];
 770         u8         tunnel_stateless_vxlan[0x1];
 771
 772         u8         swp[0x1];
 773         u8         swp_csum[0x1];
 774         u8         swp_lso[0x1];
 775         u8         reserved_2[0x1b];
 776         u8         max_geneve_opt_len[0x1];
 777         u8         tunnel_stateless_geneve_rx[0x1];
 778
 779         u8         reserved_3[0x10];
 780         u8         lro_min_mss_size[0x10];
 781
 782         u8         reserved_4[0x120];
 783
 784         u8         lro_timer_supported_periods[4][0x20];
 785
 786         u8         reserved_5[0x600];
 787 };
 788
 789 enum {
 790         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 791         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 792         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 793 };
 794
 795 struct mlx5_ifc_roce_cap_bits {
 796         u8         roce_apm[0x1];
 797         u8         rts2rts_primary_eth_prio[0x1];
 798         u8         roce_rx_allow_untagged[0x1];
 799         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 800
 801         u8         reserved_0[0x1c];
 802
 803         u8         reserved_1[0x60];
 804
 805         u8         reserved_2[0xc];
 806         u8         l3_type[0x4];
 807         u8         reserved_3[0x8];
 808         u8         roce_version[0x8];
 809
 810         u8         reserved_4[0x10];
 811         u8         r_roce_dest_udp_port[0x10];
 812
 813         u8         r_roce_max_src_udp_port[0x10];
 814         u8         r_roce_min_src_udp_port[0x10];
 815
 816         u8         reserved_5[0x10];
 817         u8         roce_address_table_size[0x10];
 818
 819         u8         reserved_6[0x700];
 820 };
 821
 822 enum {
 823         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 824         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 825         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 826         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 827         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 828         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 829         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 830         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 831         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 832 };
 833
 834 enum {
 835         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 836         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 837         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 838         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 839         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 840         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 841         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 842         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 843         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 844 };
 845
 846 struct mlx5_ifc_atomic_caps_bits {
 847         u8         reserved_0[0x40];
 848
 849         u8         atomic_req_8B_endianess_mode[0x2];
 850         u8         reserved_1[0x4];
 851         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 852
 853         u8         reserved_2[0x19];
 854
 855         u8         reserved_3[0x20];
 856
 857         u8         reserved_4[0x10];
 858         u8         atomic_operations[0x10];
 859
 860         u8         reserved_5[0x10];
 861         u8         atomic_size_qp[0x10];
 862
 863         u8         reserved_6[0x10];
 864         u8         atomic_size_dc[0x10];
 865
 866         u8         reserved_7[0x720];
 867 };
 868
 869 struct mlx5_ifc_odp_cap_bits {
 870         u8         reserved_0[0x40];
 871
 872         u8         sig[0x1];
 873         u8         reserved_1[0x1f];
 874
 875         u8         reserved_2[0x20];
 876
 877         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 878
 879         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 880
 881         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 882
 883         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 884
 885         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
 886
 887         u8         reserved_3[0x6e0];
 888 };
 889
 890 enum {
 891         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 892         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 893         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 894         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 895         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 896 };
 897
 898 enum {
 899         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 900         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 901         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 902         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 903         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 904         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 905 };
 906
 907 enum {
 908         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 909         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 910 };
 911
 912 enum {
 913         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 914         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 915         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 916 };
 917
 918 struct mlx5_ifc_cmd_hca_cap_bits {
 919         u8         reserved_0[0x80];
 920
 921         u8         log_max_srq_sz[0x8];
 922         u8         log_max_qp_sz[0x8];
 923         u8         reserved_1[0xb];
 924         u8         log_max_qp[0x5];
 925
 926         u8         reserved_2[0xb];
 927         u8         log_max_srq[0x5];
 928         u8         reserved_3[0x10];
 929
 930         u8         reserved_4[0x8];
 931         u8         log_max_cq_sz[0x8];
 932         u8         reserved_5[0xb];
 933         u8         log_max_cq[0x5];
 934
 935         u8         log_max_eq_sz[0x8];
 936         u8         reserved_6[0x2];
 937         u8         log_max_mkey[0x6];
 938         u8         reserved_7[0xc];
 939         u8         log_max_eq[0x4];
 940
 941         u8         max_indirection[0x8];
 942         u8         reserved_8[0x1];
 943         u8         log_max_mrw_sz[0x7];
 944         u8         force_teardown[0x1];
 945         u8         reserved_9[0x1];
 946         u8         log_max_bsf_list_size[0x6];
 947         u8         reserved_10[0x2];
 948         u8         log_max_klm_list_size[0x6];
 949
 950         u8         reserved_11[0xa];
 951         u8         log_max_ra_req_dc[0x6];
 952         u8         reserved_12[0xa];
 953         u8         log_max_ra_res_dc[0x6];
 954
 955         u8         reserved_13[0xa];
 956         u8         log_max_ra_req_qp[0x6];
 957         u8         reserved_14[0xa];
 958         u8         log_max_ra_res_qp[0x6];
 959
 960         u8         pad_cap[0x1];
 961         u8         cc_query_allowed[0x1];
 962         u8         cc_modify_allowed[0x1];
 963         u8         start_pad[0x1];
 964         u8         cache_line_128byte[0x1];
 965         u8         reserved_at_165[0xa];
 966         u8         qcam_reg[0x1];
 967         u8         gid_table_size[0x10];
 968
 969         u8         out_of_seq_cnt[0x1];
 970         u8         vport_counters[0x1];
 971         u8         retransmission_q_counters[0x1];
 972         u8         debug[0x1];
 973         u8         modify_rq_counters_set_id[0x1];
 974         u8         rq_delay_drop[0x1];
 975         u8         max_qp_cnt[0xa];
 976         u8         pkey_table_size[0x10];
 977
 978         u8         vport_group_manager[0x1];
 979         u8         vhca_group_manager[0x1];
 980         u8         ib_virt[0x1];
 981         u8         eth_virt[0x1];
 982         u8         reserved_17[0x1];
 983         u8         ets[0x1];
 984         u8         nic_flow_table[0x1];
 985         u8         eswitch_flow_table[0x1];
 986         u8         reserved_18[0x3];
 987         u8         local_ca_ack_delay[0x5];
 988         u8         port_module_event[0x1];
 989         u8         reserved_19[0x5];
 990         u8         port_type[0x2];
 991         u8         num_ports[0x8];
 992
 993         u8         snapshot[0x1];
 994         u8         reserved_20[0x2];
 995         u8         log_max_msg[0x5];
 996         u8         reserved_21[0x4];
 997         u8         max_tc[0x4];
 998         u8         temp_warn_event[0x1];
 999         u8         dcbx[0x1];
1000         u8         reserved_22[0x4];
1001         u8         rol_s[0x1];
1002         u8         rol_g[0x1];
1003         u8         reserved_23[0x1];
1004         u8         wol_s[0x1];
1005         u8         wol_g[0x1];
1006         u8         wol_a[0x1];
1007         u8         wol_b[0x1];
1008         u8         wol_m[0x1];
1009         u8         wol_u[0x1];
1010         u8         wol_p[0x1];
1011
1012         u8         stat_rate_support[0x10];
1013         u8         reserved_24[0xc];
1014         u8         cqe_version[0x4];
1015
1016         u8         compact_address_vector[0x1];
1017         u8         striding_rq[0x1];
1018         u8         reserved_25[0x1];
1019         u8         ipoib_enhanced_offloads[0x1];
1020         u8         ipoib_ipoib_offloads[0x1];
1021         u8         reserved_26[0x8];
1022         u8         dc_connect_qp[0x1];
1023         u8         dc_cnak_trace[0x1];
1024         u8         drain_sigerr[0x1];
1025         u8         cmdif_checksum[0x2];
1026         u8         sigerr_cqe[0x1];
1027         u8         reserved_27[0x1];
1028         u8         wq_signature[0x1];
1029         u8         sctr_data_cqe[0x1];
1030         u8         reserved_28[0x1];
1031         u8         sho[0x1];
1032         u8         tph[0x1];
1033         u8         rf[0x1];
1034         u8         dct[0x1];
1035         u8         qos[0x1];
1036         u8         eth_net_offloads[0x1];
1037         u8         roce[0x1];
1038         u8         atomic[0x1];
1039         u8         reserved_30[0x1];
1040
1041         u8         cq_oi[0x1];
1042         u8         cq_resize[0x1];
1043         u8         cq_moderation[0x1];
1044         u8         cq_period_mode_modify[0x1];
1045         u8         cq_invalidate[0x1];
1046         u8         reserved_at_225[0x1];
1047         u8         cq_eq_remap[0x1];
1048         u8         pg[0x1];
1049         u8         block_lb_mc[0x1];
1050         u8         exponential_backoff[0x1];
1051         u8         scqe_break_moderation[0x1];
1052         u8         cq_period_start_from_cqe[0x1];
1053         u8         cd[0x1];
1054         u8         atm[0x1];
1055         u8         apm[0x1];
1056         u8         imaicl[0x1];
1057         u8         reserved_32[0x6];
1058         u8         qkv[0x1];
1059         u8         pkv[0x1];
1060         u8         set_deth_sqpn[0x1];
1061         u8         reserved_33[0x3];
1062         u8         xrc[0x1];
1063         u8         ud[0x1];
1064         u8         uc[0x1];
1065         u8         rc[0x1];
1066
1067         u8         reserved_34[0xa];
1068         u8         uar_sz[0x6];
1069         u8         reserved_35[0x8];
1070         u8         log_pg_sz[0x8];
1071
1072         u8         bf[0x1];
1073         u8         driver_version[0x1];
1074         u8         pad_tx_eth_packet[0x1];
1075         u8         reserved_36[0x8];
1076         u8         log_bf_reg_size[0x5];
1077         u8         reserved_37[0x10];
1078
1079         u8         num_of_diagnostic_counters[0x10];
1080         u8         max_wqe_sz_sq[0x10];
1081
1082         u8         reserved_38[0x10];
1083         u8         max_wqe_sz_rq[0x10];
1084
1085         u8         reserved_39[0x10];
1086         u8         max_wqe_sz_sq_dc[0x10];
1087
1088         u8         reserved_40[0x7];
1089         u8         max_qp_mcg[0x19];
1090
1091         u8         reserved_41[0x18];
1092         u8         log_max_mcg[0x8];
1093
1094         u8         reserved_42[0x3];
1095         u8         log_max_transport_domain[0x5];
1096         u8         reserved_43[0x3];
1097         u8         log_max_pd[0x5];
1098         u8         reserved_44[0xb];
1099         u8         log_max_xrcd[0x5];
1100
1101         u8         reserved_45[0x10];
1102         u8         max_flow_counter[0x10];
1103
1104         u8         reserved_46[0x3];
1105         u8         log_max_rq[0x5];
1106         u8         reserved_47[0x3];
1107         u8         log_max_sq[0x5];
1108         u8         reserved_48[0x3];
1109         u8         log_max_tir[0x5];
1110         u8         reserved_49[0x3];
1111         u8         log_max_tis[0x5];
1112
1113         u8         basic_cyclic_rcv_wqe[0x1];
1114         u8         reserved_50[0x2];
1115         u8         log_max_rmp[0x5];
1116         u8         reserved_51[0x3];
1117         u8         log_max_rqt[0x5];
1118         u8         reserved_52[0x3];
1119         u8         log_max_rqt_size[0x5];
1120         u8         reserved_53[0x3];
1121         u8         log_max_tis_per_sq[0x5];
1122
1123         u8         reserved_54[0x3];
1124         u8         log_max_stride_sz_rq[0x5];
1125         u8         reserved_55[0x3];
1126         u8         log_min_stride_sz_rq[0x5];
1127         u8         reserved_56[0x3];
1128         u8         log_max_stride_sz_sq[0x5];
1129         u8         reserved_57[0x3];
1130         u8         log_min_stride_sz_sq[0x5];
1131
1132         u8         reserved_58[0x1b];
1133         u8         log_max_wq_sz[0x5];
1134
1135         u8         nic_vport_change_event[0x1];
1136         u8         disable_local_lb[0x1];
1137         u8         reserved_59[0x9];
1138         u8         log_max_vlan_list[0x5];
1139         u8         reserved_60[0x3];
1140         u8         log_max_current_mc_list[0x5];
1141         u8         reserved_61[0x3];
1142         u8         log_max_current_uc_list[0x5];
1143
1144         u8         reserved_62[0x80];
1145
1146         u8         reserved_63[0x3];
1147         u8         log_max_l2_table[0x5];
1148         u8         reserved_64[0x8];
1149         u8         log_uar_page_sz[0x10];
1150
1151         u8         reserved_65[0x20];
1152
1153         u8         device_frequency_mhz[0x20];
1154
1155         u8         device_frequency_khz[0x20];
1156
1157         u8         reserved_66[0x80];
1158
1159         u8         log_max_atomic_size_qp[0x8];
1160         u8         reserved_67[0x10];
1161         u8         log_max_atomic_size_dc[0x8];
1162
1163         u8         reserved_68[0x1f];
1164         u8         cqe_compression[0x1];
1165
1166         u8         cqe_compression_timeout[0x10];
1167         u8         cqe_compression_max_num[0x10];
1168
1169         u8         reserved_69[0x220];
1170 };
1171
1172 enum mlx5_flow_destination_type {
1173         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1174         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1175         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1176 };
1177
1178 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1179         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1180         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1181         u8         reserved_0[0x40];
1182 };
1183
1184 struct mlx5_ifc_fte_match_param_bits {
1185         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1186
1187         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1188
1189         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1190
1191         u8         reserved_0[0xa00];
1192 };
1193
1194 enum {
1195         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1196         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1197         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1198         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1199         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1200 };
1201
1202 struct mlx5_ifc_rx_hash_field_select_bits {
1203         u8         l3_prot_type[0x1];
1204         u8         l4_prot_type[0x1];
1205         u8         selected_fields[0x1e];
1206 };
1207
1208 enum {
1209         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1210         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1211         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1212         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1213 };
1214
1215 enum rq_type {
1216         RQ_TYPE_NONE,
1217         RQ_TYPE_STRIDE,
1218 };
1219
1220 enum {
1221         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1222         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1223 };
1224
1225 struct mlx5_ifc_wq_bits {
1226         u8         wq_type[0x4];
1227         u8         wq_signature[0x1];
1228         u8         end_padding_mode[0x2];
1229         u8         cd_slave[0x1];
1230         u8         reserved_0[0x18];
1231
1232         u8         hds_skip_first_sge[0x1];
1233         u8         log2_hds_buf_size[0x3];
1234         u8         reserved_1[0x7];
1235         u8         page_offset[0x5];
1236         u8         lwm[0x10];
1237
1238         u8         reserved_2[0x8];
1239         u8         pd[0x18];
1240
1241         u8         reserved_3[0x8];
1242         u8         uar_page[0x18];
1243
1244         u8         dbr_addr[0x40];
1245
1246         u8         hw_counter[0x20];
1247
1248         u8         sw_counter[0x20];
1249
1250         u8         reserved_4[0xc];
1251         u8         log_wq_stride[0x4];
1252         u8         reserved_5[0x3];
1253         u8         log_wq_pg_sz[0x5];
1254         u8         reserved_6[0x3];
1255         u8         log_wq_sz[0x5];
1256
1257         u8         reserved_7[0x15];
1258         u8         single_wqe_log_num_of_strides[0x3];
1259         u8         two_byte_shift_en[0x1];
1260         u8         reserved_8[0x4];
1261         u8         single_stride_log_num_of_bytes[0x3];
1262
1263         u8         reserved_9[0x4c0];
1264
1265         struct mlx5_ifc_cmd_pas_bits pas[0];
1266 };
1267
1268 struct mlx5_ifc_rq_num_bits {
1269         u8         reserved_0[0x8];
1270         u8         rq_num[0x18];
1271 };
1272
1273 struct mlx5_ifc_mac_address_layout_bits {
1274         u8         reserved_0[0x10];
1275         u8         mac_addr_47_32[0x10];
1276
1277         u8         mac_addr_31_0[0x20];
1278 };
1279
1280 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1281         u8         reserved_0[0xa0];
1282
1283         u8         min_time_between_cnps[0x20];
1284
1285         u8         reserved_1[0x12];
1286         u8         cnp_dscp[0x6];
1287         u8         reserved_2[0x4];
1288         u8         cnp_prio_mode[0x1];
1289         u8         cnp_802p_prio[0x3];
1290
1291         u8         reserved_3[0x720];
1292 };
1293
1294 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1295         u8         reserved_0[0x60];
1296
1297         u8         reserved_1[0x4];
1298         u8         clamp_tgt_rate[0x1];
1299         u8         reserved_2[0x3];
1300         u8         clamp_tgt_rate_after_time_inc[0x1];
1301         u8         reserved_3[0x17];
1302
1303         u8         reserved_4[0x20];
1304
1305         u8         rpg_time_reset[0x20];
1306
1307         u8         rpg_byte_reset[0x20];
1308
1309         u8         rpg_threshold[0x20];
1310
1311         u8         rpg_max_rate[0x20];
1312
1313         u8         rpg_ai_rate[0x20];
1314
1315         u8         rpg_hai_rate[0x20];
1316
1317         u8         rpg_gd[0x20];
1318
1319         u8         rpg_min_dec_fac[0x20];
1320
1321         u8         rpg_min_rate[0x20];
1322
1323         u8         reserved_5[0xe0];
1324
1325         u8         rate_to_set_on_first_cnp[0x20];
1326
1327         u8         dce_tcp_g[0x20];
1328
1329         u8         dce_tcp_rtt[0x20];
1330
1331         u8         rate_reduce_monitor_period[0x20];
1332
1333         u8         reserved_6[0x20];
1334
1335         u8         initial_alpha_value[0x20];
1336
1337         u8         reserved_7[0x4a0];
1338 };
1339
1340 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1341         u8         reserved_0[0x80];
1342
1343         u8         rppp_max_rps[0x20];
1344
1345         u8         rpg_time_reset[0x20];
1346
1347         u8         rpg_byte_reset[0x20];
1348
1349         u8         rpg_threshold[0x20];
1350
1351         u8         rpg_max_rate[0x20];
1352
1353         u8         rpg_ai_rate[0x20];
1354
1355         u8         rpg_hai_rate[0x20];
1356
1357         u8         rpg_gd[0x20];
1358
1359         u8         rpg_min_dec_fac[0x20];
1360
1361         u8         rpg_min_rate[0x20];
1362
1363         u8         reserved_1[0x640];
1364 };
1365
1366 enum {
1367         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1368         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1369         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1370 };
1371
1372 struct mlx5_ifc_resize_field_select_bits {
1373         u8         resize_field_select[0x20];
1374 };
1375
1376 enum {
1377         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1378         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1379         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1380         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1381         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1382         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1383 };
1384
1385 struct mlx5_ifc_modify_field_select_bits {
1386         u8         modify_field_select[0x20];
1387 };
1388
1389 struct mlx5_ifc_field_select_r_roce_np_bits {
1390         u8         field_select_r_roce_np[0x20];
1391 };
1392
1393 enum {
1394         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1395         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1396         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1397         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1398         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1399         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1400         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1401         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1402         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1403         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1404         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1405         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1406         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1407         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1408         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1409 };
1410
1411 struct mlx5_ifc_field_select_r_roce_rp_bits {
1412         u8         field_select_r_roce_rp[0x20];
1413 };
1414
1415 enum {
1416         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1417         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1418         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1419         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1420         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1421         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1422         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1423         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1424         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1425         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1426 };
1427
1428 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1429         u8         field_select_8021qaurp[0x20];
1430 };
1431
1432 struct mlx5_ifc_pptb_reg_bits {
1433         u8         reserved_0[0x2];
1434         u8         mm[0x2];
1435         u8         reserved_1[0x4];
1436         u8         local_port[0x8];
1437         u8         reserved_2[0x6];
1438         u8         cm[0x1];
1439         u8         um[0x1];
1440         u8         pm[0x8];
1441
1442         u8         prio7buff[0x4];
1443         u8         prio6buff[0x4];
1444         u8         prio5buff[0x4];
1445         u8         prio4buff[0x4];
1446         u8         prio3buff[0x4];
1447         u8         prio2buff[0x4];
1448         u8         prio1buff[0x4];
1449         u8         prio0buff[0x4];
1450
1451         u8         pm_msb[0x8];
1452         u8         reserved_3[0x10];
1453         u8         ctrl_buff[0x4];
1454         u8         untagged_buff[0x4];
1455 };
1456
1457 struct mlx5_ifc_dcbx_app_reg_bits {
1458         u8         reserved_0[0x8];
1459         u8         port_number[0x8];
1460         u8         reserved_1[0x10];
1461
1462         u8         reserved_2[0x1a];
1463         u8         num_app_prio[0x6];
1464
1465         u8         reserved_3[0x40];
1466
1467         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1468 };
1469
1470 struct mlx5_ifc_dcbx_param_reg_bits {
1471         u8         dcbx_cee_cap[0x1];
1472         u8         dcbx_ieee_cap[0x1];
1473         u8         dcbx_standby_cap[0x1];
1474         u8         reserved_0[0x5];
1475         u8         port_number[0x8];
1476         u8         reserved_1[0xa];
1477         u8         max_application_table_size[0x6];
1478
1479         u8         reserved_2[0x15];
1480         u8         version_oper[0x3];
1481         u8         reserved_3[0x5];
1482         u8         version_admin[0x3];
1483
1484         u8         willing_admin[0x1];
1485         u8         reserved_4[0x3];
1486         u8         pfc_cap_oper[0x4];
1487         u8         reserved_5[0x4];
1488         u8         pfc_cap_admin[0x4];
1489         u8         reserved_6[0x4];
1490         u8         num_of_tc_oper[0x4];
1491         u8         reserved_7[0x4];
1492         u8         num_of_tc_admin[0x4];
1493
1494         u8         remote_willing[0x1];
1495         u8         reserved_8[0x3];
1496         u8         remote_pfc_cap[0x4];
1497         u8         reserved_9[0x14];
1498         u8         remote_num_of_tc[0x4];
1499
1500         u8         reserved_10[0x18];
1501         u8         error[0x8];
1502
1503         u8         reserved_11[0x160];
1504 };
1505
1506 struct mlx5_ifc_qhll_bits {
1507         u8         reserved_at_0[0x8];
1508         u8         local_port[0x8];
1509         u8         reserved_at_10[0x10];
1510
1511         u8         reserved_at_20[0x1b];
1512         u8         hll_time[0x5];
1513
1514         u8         stall_en[0x1];
1515         u8         reserved_at_41[0x1c];
1516         u8         stall_cnt[0x3];
1517 };
1518
1519 struct mlx5_ifc_qetcr_reg_bits {
1520         u8         operation_type[0x2];
1521         u8         cap_local_admin[0x1];
1522         u8         cap_remote_admin[0x1];
1523         u8         reserved_0[0x4];
1524         u8         port_number[0x8];
1525         u8         reserved_1[0x10];
1526
1527         u8         reserved_2[0x20];
1528
1529         u8         tc[8][0x40];
1530
1531         u8         global_configuration[0x40];
1532 };
1533
1534 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1535         u8         queue_address_63_32[0x20];
1536
1537         u8         queue_address_31_12[0x14];
1538         u8         reserved_0[0x6];
1539         u8         log_size[0x6];
1540
1541         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1542
1543         u8         reserved_1[0x8];
1544         u8         queue_number[0x18];
1545
1546         u8         q_key[0x20];
1547
1548         u8         reserved_2[0x10];
1549         u8         pkey_index[0x10];
1550
1551         u8         reserved_3[0x40];
1552 };
1553
1554 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1555         u8         reserved_0[0x8];
1556         u8         cq_ci[0x10];
1557         u8         reserved_1[0x8];
1558 };
1559
1560 enum {
1561         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1562         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1563 };
1564
1565 enum {
1566         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1567         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1568         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1569         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1570 };
1571
1572 struct mlx5_ifc_nodnic_event_word_bits {
1573         u8         driver_reset_needed[0x1];
1574         u8         port_management_change_event[0x1];
1575         u8         reserved_0[0x19];
1576         u8         link_type[0x1];
1577         u8         port_state[0x4];
1578 };
1579
1580 struct mlx5_ifc_nic_vport_change_event_bits {
1581         u8         reserved_0[0x10];
1582         u8         vport_num[0x10];
1583
1584         u8         reserved_1[0xc0];
1585 };
1586
1587 struct mlx5_ifc_pages_req_event_bits {
1588         u8         reserved_0[0x10];
1589         u8         function_id[0x10];
1590
1591         u8         num_pages[0x20];
1592
1593         u8         reserved_1[0xa0];
1594 };
1595
1596 struct mlx5_ifc_cmd_inter_comp_event_bits {
1597         u8         command_completion_vector[0x20];
1598
1599         u8         reserved_0[0xc0];
1600 };
1601
1602 struct mlx5_ifc_stall_vl_event_bits {
1603         u8         reserved_0[0x18];
1604         u8         port_num[0x1];
1605         u8         reserved_1[0x3];
1606         u8         vl[0x4];
1607
1608         u8         reserved_2[0xa0];
1609 };
1610
1611 struct mlx5_ifc_db_bf_congestion_event_bits {
1612         u8         event_subtype[0x8];
1613         u8         reserved_0[0x8];
1614         u8         congestion_level[0x8];
1615         u8         reserved_1[0x8];
1616
1617         u8         reserved_2[0xa0];
1618 };
1619
1620 struct mlx5_ifc_gpio_event_bits {
1621         u8         reserved_0[0x60];
1622
1623         u8         gpio_event_hi[0x20];
1624
1625         u8         gpio_event_lo[0x20];
1626
1627         u8         reserved_1[0x40];
1628 };
1629
1630 struct mlx5_ifc_port_state_change_event_bits {
1631         u8         reserved_0[0x40];
1632
1633         u8         port_num[0x4];
1634         u8         reserved_1[0x1c];
1635
1636         u8         reserved_2[0x80];
1637 };
1638
1639 struct mlx5_ifc_dropped_packet_logged_bits {
1640         u8         reserved_0[0xe0];
1641 };
1642
1643 enum {
1644         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1645         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1646 };
1647
1648 struct mlx5_ifc_cq_error_bits {
1649         u8         reserved_0[0x8];
1650         u8         cqn[0x18];
1651
1652         u8         reserved_1[0x20];
1653
1654         u8         reserved_2[0x18];
1655         u8         syndrome[0x8];
1656
1657         u8         reserved_3[0x80];
1658 };
1659
1660 struct mlx5_ifc_rdma_page_fault_event_bits {
1661         u8         bytes_commited[0x20];
1662
1663         u8         r_key[0x20];
1664
1665         u8         reserved_0[0x10];
1666         u8         packet_len[0x10];
1667
1668         u8         rdma_op_len[0x20];
1669
1670         u8         rdma_va[0x40];
1671
1672         u8         reserved_1[0x5];
1673         u8         rdma[0x1];
1674         u8         write[0x1];
1675         u8         requestor[0x1];
1676         u8         qp_number[0x18];
1677 };
1678
1679 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1680         u8         bytes_committed[0x20];
1681
1682         u8         reserved_0[0x10];
1683         u8         wqe_index[0x10];
1684
1685         u8         reserved_1[0x10];
1686         u8         len[0x10];
1687
1688         u8         reserved_2[0x60];
1689
1690         u8         reserved_3[0x5];
1691         u8         rdma[0x1];
1692         u8         write_read[0x1];
1693         u8         requestor[0x1];
1694         u8         qpn[0x18];
1695 };
1696
1697 enum {
1698         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1699         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1700         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1701 };
1702
1703 struct mlx5_ifc_qp_events_bits {
1704         u8         reserved_0[0xa0];
1705
1706         u8         type[0x8];
1707         u8         reserved_1[0x18];
1708
1709         u8         reserved_2[0x8];
1710         u8         qpn_rqn_sqn[0x18];
1711 };
1712
1713 struct mlx5_ifc_dct_events_bits {
1714         u8         reserved_0[0xc0];
1715
1716         u8         reserved_1[0x8];
1717         u8         dct_number[0x18];
1718 };
1719
1720 struct mlx5_ifc_comp_event_bits {
1721         u8         reserved_0[0xc0];
1722
1723         u8         reserved_1[0x8];
1724         u8         cq_number[0x18];
1725 };
1726
1727 struct mlx5_ifc_fw_version_bits {
1728         u8         major[0x10];
1729         u8         reserved_0[0x10];
1730
1731         u8         minor[0x10];
1732         u8         subminor[0x10];
1733
1734         u8         second[0x8];
1735         u8         minute[0x8];
1736         u8         hour[0x8];
1737         u8         reserved_1[0x8];
1738
1739         u8         year[0x10];
1740         u8         month[0x8];
1741         u8         day[0x8];
1742 };
1743
1744 enum {
1745         MLX5_QPC_STATE_RST        = 0x0,
1746         MLX5_QPC_STATE_INIT       = 0x1,
1747         MLX5_QPC_STATE_RTR        = 0x2,
1748         MLX5_QPC_STATE_RTS        = 0x3,
1749         MLX5_QPC_STATE_SQER       = 0x4,
1750         MLX5_QPC_STATE_SQD        = 0x5,
1751         MLX5_QPC_STATE_ERR        = 0x6,
1752         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1753 };
1754
1755 enum {
1756         MLX5_QPC_ST_RC            = 0x0,
1757         MLX5_QPC_ST_UC            = 0x1,
1758         MLX5_QPC_ST_UD            = 0x2,
1759         MLX5_QPC_ST_XRC           = 0x3,
1760         MLX5_QPC_ST_DCI           = 0x5,
1761         MLX5_QPC_ST_QP0           = 0x7,
1762         MLX5_QPC_ST_QP1           = 0x8,
1763         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1764         MLX5_QPC_ST_REG_UMR       = 0xc,
1765 };
1766
1767 enum {
1768         MLX5_QP_PM_ARMED            = 0x0,
1769         MLX5_QP_PM_REARM            = 0x1,
1770         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1771         MLX5_QP_PM_MIGRATED         = 0x3,
1772 };
1773
1774 enum {
1775         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1776         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1777 };
1778
1779 enum {
1780         MLX5_QPC_MTU_256_BYTES        = 0x1,
1781         MLX5_QPC_MTU_512_BYTES        = 0x2,
1782         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1783         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1784         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1785         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1786 };
1787
1788 enum {
1789         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1790         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1791         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1792         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1793         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1794         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1795         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1796         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1797 };
1798
1799 enum {
1800         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1801         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1802         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1803 };
1804
1805 enum {
1806         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1807         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1808         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1809 };
1810
1811 struct mlx5_ifc_qpc_bits {
1812         u8         state[0x4];
1813         u8         lag_tx_port_affinity[0x4];
1814         u8         st[0x8];
1815         u8         reserved_1[0x3];
1816         u8         pm_state[0x2];
1817         u8         reserved_2[0x7];
1818         u8         end_padding_mode[0x2];
1819         u8         reserved_3[0x2];
1820
1821         u8         wq_signature[0x1];
1822         u8         block_lb_mc[0x1];
1823         u8         atomic_like_write_en[0x1];
1824         u8         latency_sensitive[0x1];
1825         u8         reserved_4[0x1];
1826         u8         drain_sigerr[0x1];
1827         u8         reserved_5[0x2];
1828         u8         pd[0x18];
1829
1830         u8         mtu[0x3];
1831         u8         log_msg_max[0x5];
1832         u8         reserved_6[0x1];
1833         u8         log_rq_size[0x4];
1834         u8         log_rq_stride[0x3];
1835         u8         no_sq[0x1];
1836         u8         log_sq_size[0x4];
1837         u8         reserved_7[0x6];
1838         u8         rlky[0x1];
1839         u8         ulp_stateless_offload_mode[0x4];
1840
1841         u8         counter_set_id[0x8];
1842         u8         uar_page[0x18];
1843
1844         u8         reserved_8[0x8];
1845         u8         user_index[0x18];
1846
1847         u8         reserved_9[0x3];
1848         u8         log_page_size[0x5];
1849         u8         remote_qpn[0x18];
1850
1851         struct mlx5_ifc_ads_bits primary_address_path;
1852
1853         struct mlx5_ifc_ads_bits secondary_address_path;
1854
1855         u8         log_ack_req_freq[0x4];
1856         u8         reserved_10[0x4];
1857         u8         log_sra_max[0x3];
1858         u8         reserved_11[0x2];
1859         u8         retry_count[0x3];
1860         u8         rnr_retry[0x3];
1861         u8         reserved_12[0x1];
1862         u8         fre[0x1];
1863         u8         cur_rnr_retry[0x3];
1864         u8         cur_retry_count[0x3];
1865         u8         reserved_13[0x5];
1866
1867         u8         reserved_14[0x20];
1868
1869         u8         reserved_15[0x8];
1870         u8         next_send_psn[0x18];
1871
1872         u8         reserved_16[0x8];
1873         u8         cqn_snd[0x18];
1874
1875         u8         reserved_at_400[0x8];
1876
1877         u8         deth_sqpn[0x18];
1878         u8         reserved_17[0x20];
1879
1880         u8         reserved_18[0x8];
1881         u8         last_acked_psn[0x18];
1882
1883         u8         reserved_19[0x8];
1884         u8         ssn[0x18];
1885
1886         u8         reserved_20[0x8];
1887         u8         log_rra_max[0x3];
1888         u8         reserved_21[0x1];
1889         u8         atomic_mode[0x4];
1890         u8         rre[0x1];
1891         u8         rwe[0x1];
1892         u8         rae[0x1];
1893         u8         reserved_22[0x1];
1894         u8         page_offset[0x6];
1895         u8         reserved_23[0x3];
1896         u8         cd_slave_receive[0x1];
1897         u8         cd_slave_send[0x1];
1898         u8         cd_master[0x1];
1899
1900         u8         reserved_24[0x3];
1901         u8         min_rnr_nak[0x5];
1902         u8         next_rcv_psn[0x18];
1903
1904         u8         reserved_25[0x8];
1905         u8         xrcd[0x18];
1906
1907         u8         reserved_26[0x8];
1908         u8         cqn_rcv[0x18];
1909
1910         u8         dbr_addr[0x40];
1911
1912         u8         q_key[0x20];
1913
1914         u8         reserved_27[0x5];
1915         u8         rq_type[0x3];
1916         u8         srqn_rmpn[0x18];
1917
1918         u8         reserved_28[0x8];
1919         u8         rmsn[0x18];
1920
1921         u8         hw_sq_wqebb_counter[0x10];
1922         u8         sw_sq_wqebb_counter[0x10];
1923
1924         u8         hw_rq_counter[0x20];
1925
1926         u8         sw_rq_counter[0x20];
1927
1928         u8         reserved_29[0x20];
1929
1930         u8         reserved_30[0xf];
1931         u8         cgs[0x1];
1932         u8         cs_req[0x8];
1933         u8         cs_res[0x8];
1934
1935         u8         dc_access_key[0x40];
1936
1937         u8         rdma_active[0x1];
1938         u8         comm_est[0x1];
1939         u8         suspended[0x1];
1940         u8         reserved_31[0x5];
1941         u8         send_msg_psn[0x18];
1942
1943         u8         reserved_32[0x8];
1944         u8         rcv_msg_psn[0x18];
1945
1946         u8         rdma_va[0x40];
1947
1948         u8         rdma_key[0x20];
1949
1950         u8         reserved_33[0x20];
1951 };
1952
1953 struct mlx5_ifc_roce_addr_layout_bits {
1954         u8         source_l3_address[16][0x8];
1955
1956         u8         reserved_0[0x3];
1957         u8         vlan_valid[0x1];
1958         u8         vlan_id[0xc];
1959         u8         source_mac_47_32[0x10];
1960
1961         u8         source_mac_31_0[0x20];
1962
1963         u8         reserved_1[0x14];
1964         u8         roce_l3_type[0x4];
1965         u8         roce_version[0x8];
1966
1967         u8         reserved_2[0x20];
1968 };
1969
1970 struct mlx5_ifc_rdbc_bits {
1971         u8         reserved_0[0x1c];
1972         u8         type[0x4];
1973
1974         u8         reserved_1[0x20];
1975
1976         u8         reserved_2[0x8];
1977         u8         psn[0x18];
1978
1979         u8         rkey[0x20];
1980
1981         u8         address[0x40];
1982
1983         u8         byte_count[0x20];
1984
1985         u8         reserved_3[0x20];
1986
1987         u8         atomic_resp[32][0x8];
1988 };
1989
1990 enum {
1991         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1992         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1993         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1994         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1995 };
1996
1997 struct mlx5_ifc_flow_context_bits {
1998         u8         reserved_0[0x20];
1999
2000         u8         group_id[0x20];
2001
2002         u8         reserved_1[0x8];
2003         u8         flow_tag[0x18];
2004
2005         u8         reserved_2[0x10];
2006         u8         action[0x10];
2007
2008         u8         reserved_3[0x8];
2009         u8         destination_list_size[0x18];
2010
2011         u8         reserved_4[0x8];
2012         u8         flow_counter_list_size[0x18];
2013
2014         u8         reserved_5[0x140];
2015
2016         struct mlx5_ifc_fte_match_param_bits match_value;
2017
2018         u8         reserved_6[0x600];
2019
2020         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2021 };
2022
2023 enum {
2024         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2025         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2026 };
2027
2028 struct mlx5_ifc_xrc_srqc_bits {
2029         u8         state[0x4];
2030         u8         log_xrc_srq_size[0x4];
2031         u8         reserved_0[0x18];
2032
2033         u8         wq_signature[0x1];
2034         u8         cont_srq[0x1];
2035         u8         reserved_1[0x1];
2036         u8         rlky[0x1];
2037         u8         basic_cyclic_rcv_wqe[0x1];
2038         u8         log_rq_stride[0x3];
2039         u8         xrcd[0x18];
2040
2041         u8         page_offset[0x6];
2042         u8         reserved_2[0x2];
2043         u8         cqn[0x18];
2044
2045         u8         reserved_3[0x20];
2046
2047         u8         reserved_4[0x2];
2048         u8         log_page_size[0x6];
2049         u8         user_index[0x18];
2050
2051         u8         reserved_5[0x20];
2052
2053         u8         reserved_6[0x8];
2054         u8         pd[0x18];
2055
2056         u8         lwm[0x10];
2057         u8         wqe_cnt[0x10];
2058
2059         u8         reserved_7[0x40];
2060
2061         u8         db_record_addr_h[0x20];
2062
2063         u8         db_record_addr_l[0x1e];
2064         u8         reserved_8[0x2];
2065
2066         u8         reserved_9[0x80];
2067 };
2068
2069 struct mlx5_ifc_traffic_counter_bits {
2070         u8         packets[0x40];
2071
2072         u8         octets[0x40];
2073 };
2074
2075 struct mlx5_ifc_tisc_bits {
2076         u8         strict_lag_tx_port_affinity[0x1];
2077         u8         reserved_at_1[0x3];
2078         u8         lag_tx_port_affinity[0x04];
2079
2080         u8         reserved_at_8[0x4];
2081         u8         prio[0x4];
2082         u8         reserved_1[0x10];
2083
2084         u8         reserved_2[0x100];
2085
2086         u8         reserved_3[0x8];
2087         u8         transport_domain[0x18];
2088
2089         u8         reserved_4[0x8];
2090         u8         underlay_qpn[0x18];
2091
2092         u8         reserved_5[0x3a0];
2093 };
2094
2095 enum {
2096         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2097         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2098 };
2099
2100 enum {
2101         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2102         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2103 };
2104
2105 enum {
2106         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2107         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2108         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2109 };
2110
2111 enum {
2112         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2113         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2114 };
2115
2116 struct mlx5_ifc_tirc_bits {
2117         u8         reserved_0[0x20];
2118
2119         u8         disp_type[0x4];
2120         u8         reserved_1[0x1c];
2121
2122         u8         reserved_2[0x40];
2123
2124         u8         reserved_3[0x4];
2125         u8         lro_timeout_period_usecs[0x10];
2126         u8         lro_enable_mask[0x4];
2127         u8         lro_max_msg_sz[0x8];
2128
2129         u8         reserved_4[0x40];
2130
2131         u8         reserved_5[0x8];
2132         u8         inline_rqn[0x18];
2133
2134         u8         rx_hash_symmetric[0x1];
2135         u8         reserved_6[0x1];
2136         u8         tunneled_offload_en[0x1];
2137         u8         reserved_7[0x5];
2138         u8         indirect_table[0x18];
2139
2140         u8         rx_hash_fn[0x4];
2141         u8         reserved_8[0x2];
2142         u8         self_lb_en[0x2];
2143         u8         transport_domain[0x18];
2144
2145         u8         rx_hash_toeplitz_key[10][0x20];
2146
2147         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2148
2149         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2150
2151         u8         reserved_9[0x4c0];
2152 };
2153
2154 enum {
2155         MLX5_SRQC_STATE_GOOD   = 0x0,
2156         MLX5_SRQC_STATE_ERROR  = 0x1,
2157 };
2158
2159 struct mlx5_ifc_srqc_bits {
2160         u8         state[0x4];
2161         u8         log_srq_size[0x4];
2162         u8         reserved_0[0x18];
2163
2164         u8         wq_signature[0x1];
2165         u8         cont_srq[0x1];
2166         u8         reserved_1[0x1];
2167         u8         rlky[0x1];
2168         u8         reserved_2[0x1];
2169         u8         log_rq_stride[0x3];
2170         u8         xrcd[0x18];
2171
2172         u8         page_offset[0x6];
2173         u8         reserved_3[0x2];
2174         u8         cqn[0x18];
2175
2176         u8         reserved_4[0x20];
2177
2178         u8         reserved_5[0x2];
2179         u8         log_page_size[0x6];
2180         u8         reserved_6[0x18];
2181
2182         u8         reserved_7[0x20];
2183
2184         u8         reserved_8[0x8];
2185         u8         pd[0x18];
2186
2187         u8         lwm[0x10];
2188         u8         wqe_cnt[0x10];
2189
2190         u8         reserved_9[0x40];
2191
2192         u8         dbr_addr[0x40];
2193
2194         u8         reserved_10[0x80];
2195 };
2196
2197 enum {
2198         MLX5_SQC_STATE_RST  = 0x0,
2199         MLX5_SQC_STATE_RDY  = 0x1,
2200         MLX5_SQC_STATE_ERR  = 0x3,
2201 };
2202
2203 struct mlx5_ifc_sqc_bits {
2204         u8         rlkey[0x1];
2205         u8         cd_master[0x1];
2206         u8         fre[0x1];
2207         u8         flush_in_error_en[0x1];
2208         u8         allow_multi_pkt_send_wqe[0x1];
2209         u8         min_wqe_inline_mode[0x3];
2210         u8         state[0x4];
2211         u8         reg_umr[0x1];
2212         u8         allow_swp[0x1];
2213         u8         reserved_0[0x12];
2214
2215         u8         reserved_1[0x8];
2216         u8         user_index[0x18];
2217
2218         u8         reserved_2[0x8];
2219         u8         cqn[0x18];
2220
2221         u8         reserved_3[0x80];
2222
2223         u8         qos_para_vport_number[0x10];
2224         u8         packet_pacing_rate_limit_index[0x10];
2225
2226         u8         tis_lst_sz[0x10];
2227         u8         reserved_4[0x10];
2228
2229         u8         reserved_5[0x40];
2230
2231         u8         reserved_6[0x8];
2232         u8         tis_num_0[0x18];
2233
2234         struct mlx5_ifc_wq_bits wq;
2235 };
2236
2237 enum {
2238         MLX5_TSAR_TYPE_DWRR = 0,
2239         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2240         MLX5_TSAR_TYPE_ETS = 2
2241 };
2242
2243 struct mlx5_ifc_tsar_element_attributes_bits {
2244         u8         reserved_0[0x8];
2245         u8         tsar_type[0x8];
2246         u8         reserved_1[0x10];
2247 };
2248
2249 struct mlx5_ifc_vport_element_attributes_bits {
2250         u8         reserved_0[0x10];
2251         u8         vport_number[0x10];
2252 };
2253
2254 struct mlx5_ifc_vport_tc_element_attributes_bits {
2255         u8         traffic_class[0x10];
2256         u8         vport_number[0x10];
2257 };
2258
2259 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2260         u8         reserved_0[0x0C];
2261         u8         traffic_class[0x04];
2262         u8         qos_para_vport_number[0x10];
2263 };
2264
2265 enum {
2266         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2267         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2268         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2269         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2270 };
2271
2272 struct mlx5_ifc_scheduling_context_bits {
2273         u8         element_type[0x8];
2274         u8         reserved_at_8[0x18];
2275
2276         u8         element_attributes[0x20];
2277
2278         u8         parent_element_id[0x20];
2279
2280         u8         reserved_at_60[0x40];
2281
2282         u8         bw_share[0x20];
2283
2284         u8         max_average_bw[0x20];
2285
2286         u8         reserved_at_e0[0x120];
2287 };
2288
2289 struct mlx5_ifc_rqtc_bits {
2290         u8         reserved_0[0xa0];
2291
2292         u8         reserved_1[0x10];
2293         u8         rqt_max_size[0x10];
2294
2295         u8         reserved_2[0x10];
2296         u8         rqt_actual_size[0x10];
2297
2298         u8         reserved_3[0x6a0];
2299
2300         struct mlx5_ifc_rq_num_bits rq_num[0];
2301 };
2302
2303 enum {
2304         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2305         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2306 };
2307
2308 enum {
2309         MLX5_RQC_STATE_RST  = 0x0,
2310         MLX5_RQC_STATE_RDY  = 0x1,
2311         MLX5_RQC_STATE_ERR  = 0x3,
2312 };
2313
2314 enum {
2315         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2316         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2317 };
2318
2319 struct mlx5_ifc_rqc_bits {
2320         u8         rlkey[0x1];
2321         u8         delay_drop_en[0x1];
2322         u8         scatter_fcs[0x1];
2323         u8         vlan_strip_disable[0x1];
2324         u8         mem_rq_type[0x4];
2325         u8         state[0x4];
2326         u8         reserved_1[0x1];
2327         u8         flush_in_error_en[0x1];
2328         u8         reserved_2[0x12];
2329
2330         u8         reserved_3[0x8];
2331         u8         user_index[0x18];
2332
2333         u8         reserved_4[0x8];
2334         u8         cqn[0x18];
2335
2336         u8         counter_set_id[0x8];
2337         u8         reserved_5[0x18];
2338
2339         u8         reserved_6[0x8];
2340         u8         rmpn[0x18];
2341
2342         u8         reserved_7[0xe0];
2343
2344         struct mlx5_ifc_wq_bits wq;
2345 };
2346
2347 enum {
2348         MLX5_RMPC_STATE_RDY  = 0x1,
2349         MLX5_RMPC_STATE_ERR  = 0x3,
2350 };
2351
2352 struct mlx5_ifc_rmpc_bits {
2353         u8         reserved_0[0x8];
2354         u8         state[0x4];
2355         u8         reserved_1[0x14];
2356
2357         u8         basic_cyclic_rcv_wqe[0x1];
2358         u8         reserved_2[0x1f];
2359
2360         u8         reserved_3[0x140];
2361
2362         struct mlx5_ifc_wq_bits wq;
2363 };
2364
2365 enum {
2366         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2367         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2368         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2369 };
2370
2371 struct mlx5_ifc_nic_vport_context_bits {
2372         u8         reserved_0[0x5];
2373         u8         min_wqe_inline_mode[0x3];
2374         u8         reserved_1[0x15];
2375         u8         disable_mc_local_lb[0x1];
2376         u8         disable_uc_local_lb[0x1];
2377         u8         roce_en[0x1];
2378
2379         u8         arm_change_event[0x1];
2380         u8         reserved_2[0x1a];
2381         u8         event_on_mtu[0x1];
2382         u8         event_on_promisc_change[0x1];
2383         u8         event_on_vlan_change[0x1];
2384         u8         event_on_mc_address_change[0x1];
2385         u8         event_on_uc_address_change[0x1];
2386
2387         u8         reserved_3[0xe0];
2388
2389         u8         reserved_4[0x10];
2390         u8         mtu[0x10];
2391
2392         u8         system_image_guid[0x40];
2393
2394         u8         port_guid[0x40];
2395
2396         u8         node_guid[0x40];
2397
2398         u8         reserved_5[0x140];
2399
2400         u8         qkey_violation_counter[0x10];
2401         u8         reserved_6[0x10];
2402
2403         u8         reserved_7[0x420];
2404
2405         u8         promisc_uc[0x1];
2406         u8         promisc_mc[0x1];
2407         u8         promisc_all[0x1];
2408         u8         reserved_8[0x2];
2409         u8         allowed_list_type[0x3];
2410         u8         reserved_9[0xc];
2411         u8         allowed_list_size[0xc];
2412
2413         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2414
2415         u8         reserved_10[0x20];
2416
2417         u8         current_uc_mac_address[0][0x40];
2418 };
2419
2420 enum {
2421         MLX5_ACCESS_MODE_PA        = 0x0,
2422         MLX5_ACCESS_MODE_MTT       = 0x1,
2423         MLX5_ACCESS_MODE_KLM       = 0x2,
2424 };
2425
2426 struct mlx5_ifc_mkc_bits {
2427         u8         reserved_0[0x1];
2428         u8         free[0x1];
2429         u8         reserved_1[0xd];
2430         u8         small_fence_on_rdma_read_response[0x1];
2431         u8         umr_en[0x1];
2432         u8         a[0x1];
2433         u8         rw[0x1];
2434         u8         rr[0x1];
2435         u8         lw[0x1];
2436         u8         lr[0x1];
2437         u8         access_mode[0x2];
2438         u8         reserved_2[0x8];
2439
2440         u8         qpn[0x18];
2441         u8         mkey_7_0[0x8];
2442
2443         u8         reserved_3[0x20];
2444
2445         u8         length64[0x1];
2446         u8         bsf_en[0x1];
2447         u8         sync_umr[0x1];
2448         u8         reserved_4[0x2];
2449         u8         expected_sigerr_count[0x1];
2450         u8         reserved_5[0x1];
2451         u8         en_rinval[0x1];
2452         u8         pd[0x18];
2453
2454         u8         start_addr[0x40];
2455
2456         u8         len[0x40];
2457
2458         u8         bsf_octword_size[0x20];
2459
2460         u8         reserved_6[0x80];
2461
2462         u8         translations_octword_size[0x20];
2463
2464         u8         reserved_7[0x1b];
2465         u8         log_page_size[0x5];
2466
2467         u8         reserved_8[0x20];
2468 };
2469
2470 struct mlx5_ifc_pkey_bits {
2471         u8         reserved_0[0x10];
2472         u8         pkey[0x10];
2473 };
2474
2475 struct mlx5_ifc_array128_auto_bits {
2476         u8         array128_auto[16][0x8];
2477 };
2478
2479 enum {
2480         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2481         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2482         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2483 };
2484
2485 enum {
2486         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2487         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2488         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2489         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2490         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2491         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2492         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2493 };
2494
2495 enum {
2496         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2497         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2498         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2499 };
2500
2501 enum {
2502         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2503         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2504         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2505         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2506 };
2507
2508 enum {
2509         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2510         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2511         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2512         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2513 };
2514
2515 struct mlx5_ifc_hca_vport_context_bits {
2516         u8         field_select[0x20];
2517
2518         u8         reserved_0[0xe0];
2519
2520         u8         sm_virt_aware[0x1];
2521         u8         has_smi[0x1];
2522         u8         has_raw[0x1];
2523         u8         grh_required[0x1];
2524         u8         reserved_1[0x1];
2525         u8         min_wqe_inline_mode[0x3];
2526         u8         reserved_2[0x8];
2527         u8         port_physical_state[0x4];
2528         u8         vport_state_policy[0x4];
2529         u8         port_state[0x4];
2530         u8         vport_state[0x4];
2531
2532         u8         reserved_3[0x20];
2533
2534         u8         system_image_guid[0x40];
2535
2536         u8         port_guid[0x40];
2537
2538         u8         node_guid[0x40];
2539
2540         u8         cap_mask1[0x20];
2541
2542         u8         cap_mask1_field_select[0x20];
2543
2544         u8         cap_mask2[0x20];
2545
2546         u8         cap_mask2_field_select[0x20];
2547
2548         u8         reserved_4[0x80];
2549
2550         u8         lid[0x10];
2551         u8         reserved_5[0x4];
2552         u8         init_type_reply[0x4];
2553         u8         lmc[0x3];
2554         u8         subnet_timeout[0x5];
2555
2556         u8         sm_lid[0x10];
2557         u8         sm_sl[0x4];
2558         u8         reserved_6[0xc];
2559
2560         u8         qkey_violation_counter[0x10];
2561         u8         pkey_violation_counter[0x10];
2562
2563         u8         reserved_7[0xca0];
2564 };
2565
2566 union mlx5_ifc_hca_cap_union_bits {
2567         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2568         struct mlx5_ifc_odp_cap_bits odp_cap;
2569         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2570         struct mlx5_ifc_roce_cap_bits roce_cap;
2571         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2572         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2573         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2574         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2575         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2576         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2577         struct mlx5_ifc_qos_cap_bits qos_cap;
2578         u8         reserved_0[0x8000];
2579 };
2580
2581 enum {
2582         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2583         MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2584 };
2585
2586 struct mlx5_ifc_flow_table_context_bits {
2587         u8         encap_en[0x1];
2588         u8         decap_en[0x1];
2589         u8         reserved_at_2[0x2];
2590         u8         table_miss_action[0x4];
2591         u8         level[0x8];
2592         u8         reserved_at_10[0x8];
2593         u8         log_size[0x8];
2594
2595         u8         reserved_at_20[0x8];
2596         u8         table_miss_id[0x18];
2597
2598         u8         reserved_at_40[0x8];
2599         u8         lag_master_next_table_id[0x18];
2600
2601         u8         reserved_at_60[0xe0];
2602 };
2603
2604 struct mlx5_ifc_esw_vport_context_bits {
2605         u8         reserved_0[0x3];
2606         u8         vport_svlan_strip[0x1];
2607         u8         vport_cvlan_strip[0x1];
2608         u8         vport_svlan_insert[0x1];
2609         u8         vport_cvlan_insert[0x2];
2610         u8         reserved_1[0x18];
2611
2612         u8         reserved_2[0x20];
2613
2614         u8         svlan_cfi[0x1];
2615         u8         svlan_pcp[0x3];
2616         u8         svlan_id[0xc];
2617         u8         cvlan_cfi[0x1];
2618         u8         cvlan_pcp[0x3];
2619         u8         cvlan_id[0xc];
2620
2621         u8         reserved_3[0x7a0];
2622 };
2623
2624 enum {
2625         MLX5_EQC_STATUS_OK                = 0x0,
2626         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2627 };
2628
2629 enum {
2630         MLX5_EQ_STATE_ARMED = 0x9,
2631         MLX5_EQ_STATE_FIRED = 0xa,
2632 };
2633
2634 struct mlx5_ifc_eqc_bits {
2635         u8         status[0x4];
2636         u8         reserved_0[0x9];
2637         u8         ec[0x1];
2638         u8         oi[0x1];
2639         u8         reserved_1[0x5];
2640         u8         st[0x4];
2641         u8         reserved_2[0x8];
2642
2643         u8         reserved_3[0x20];
2644
2645         u8         reserved_4[0x14];
2646         u8         page_offset[0x6];
2647         u8         reserved_5[0x6];
2648
2649         u8         reserved_6[0x3];
2650         u8         log_eq_size[0x5];
2651         u8         uar_page[0x18];
2652
2653         u8         reserved_7[0x20];
2654
2655         u8         reserved_8[0x18];
2656         u8         intr[0x8];
2657
2658         u8         reserved_9[0x3];
2659         u8         log_page_size[0x5];
2660         u8         reserved_10[0x18];
2661
2662         u8         reserved_11[0x60];
2663
2664         u8         reserved_12[0x8];
2665         u8         consumer_counter[0x18];
2666
2667         u8         reserved_13[0x8];
2668         u8         producer_counter[0x18];
2669
2670         u8         reserved_14[0x80];
2671 };
2672
2673 enum {
2674         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2675         MLX5_DCTC_STATE_DRAINING  = 0x1,
2676         MLX5_DCTC_STATE_DRAINED   = 0x2,
2677 };
2678
2679 enum {
2680         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2681         MLX5_DCTC_CS_RES_NA         = 0x1,
2682         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2683 };
2684
2685 enum {
2686         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2687         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2688         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2689         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2690         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2691 };
2692
2693 struct mlx5_ifc_dctc_bits {
2694         u8         reserved_0[0x4];
2695         u8         state[0x4];
2696         u8         reserved_1[0x18];
2697
2698         u8         reserved_2[0x8];
2699         u8         user_index[0x18];
2700
2701         u8         reserved_3[0x8];
2702         u8         cqn[0x18];
2703
2704         u8         counter_set_id[0x8];
2705         u8         atomic_mode[0x4];
2706         u8         rre[0x1];
2707         u8         rwe[0x1];
2708         u8         rae[0x1];
2709         u8         atomic_like_write_en[0x1];
2710         u8         latency_sensitive[0x1];
2711         u8         rlky[0x1];
2712         u8         reserved_4[0xe];
2713
2714         u8         reserved_5[0x8];
2715         u8         cs_res[0x8];
2716         u8         reserved_6[0x3];
2717         u8         min_rnr_nak[0x5];
2718         u8         reserved_7[0x8];
2719
2720         u8         reserved_8[0x8];
2721         u8         srqn[0x18];
2722
2723         u8         reserved_9[0x8];
2724         u8         pd[0x18];
2725
2726         u8         tclass[0x8];
2727         u8         reserved_10[0x4];
2728         u8         flow_label[0x14];
2729
2730         u8         dc_access_key[0x40];
2731
2732         u8         reserved_11[0x5];
2733         u8         mtu[0x3];
2734         u8         port[0x8];
2735         u8         pkey_index[0x10];
2736
2737         u8         reserved_12[0x8];
2738         u8         my_addr_index[0x8];
2739         u8         reserved_13[0x8];
2740         u8         hop_limit[0x8];
2741
2742         u8         dc_access_key_violation_count[0x20];
2743
2744         u8         reserved_14[0x14];
2745         u8         dei_cfi[0x1];
2746         u8         eth_prio[0x3];
2747         u8         ecn[0x2];
2748         u8         dscp[0x6];
2749
2750         u8         reserved_15[0x40];
2751 };
2752
2753 enum {
2754         MLX5_CQC_STATUS_OK             = 0x0,
2755         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2756         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2757 };
2758
2759 enum {
2760         CQE_SIZE_64                = 0x0,
2761         CQE_SIZE_128               = 0x1,
2762 };
2763
2764 enum {
2765         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2766         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2767 };
2768
2769 enum {
2770         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2771         MLX5_CQ_STATE_ARMED                               = 0x9,
2772         MLX5_CQ_STATE_FIRED                               = 0xa,
2773 };
2774
2775 struct mlx5_ifc_cqc_bits {
2776         u8         status[0x4];
2777         u8         reserved_0[0x4];
2778         u8         cqe_sz[0x3];
2779         u8         cc[0x1];
2780         u8         reserved_1[0x1];
2781         u8         scqe_break_moderation_en[0x1];
2782         u8         oi[0x1];
2783         u8         cq_period_mode[0x2];
2784         u8         cqe_compression_en[0x1];
2785         u8         mini_cqe_res_format[0x2];
2786         u8         st[0x4];
2787         u8         reserved_2[0x8];
2788
2789         u8         reserved_3[0x20];
2790
2791         u8         reserved_4[0x14];
2792         u8         page_offset[0x6];
2793         u8         reserved_5[0x6];
2794
2795         u8         reserved_6[0x3];
2796         u8         log_cq_size[0x5];
2797         u8         uar_page[0x18];
2798
2799         u8         reserved_7[0x4];
2800         u8         cq_period[0xc];
2801         u8         cq_max_count[0x10];
2802
2803         u8         reserved_8[0x18];
2804         u8         c_eqn[0x8];
2805
2806         u8         reserved_9[0x3];
2807         u8         log_page_size[0x5];
2808         u8         reserved_10[0x18];
2809
2810         u8         reserved_11[0x20];
2811
2812         u8         reserved_12[0x8];
2813         u8         last_notified_index[0x18];
2814
2815         u8         reserved_13[0x8];
2816         u8         last_solicit_index[0x18];
2817
2818         u8         reserved_14[0x8];
2819         u8         consumer_counter[0x18];
2820
2821         u8         reserved_15[0x8];
2822         u8         producer_counter[0x18];
2823
2824         u8         reserved_16[0x40];
2825
2826         u8         dbr_addr[0x40];
2827 };
2828
2829 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2830         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2831         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2832         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2833         u8         reserved_0[0x800];
2834 };
2835
2836 struct mlx5_ifc_query_adapter_param_block_bits {
2837         u8         reserved_0[0xc0];
2838
2839         u8         reserved_1[0x8];
2840         u8         ieee_vendor_id[0x18];
2841
2842         u8         reserved_2[0x10];
2843         u8         vsd_vendor_id[0x10];
2844
2845         u8         vsd[208][0x8];
2846
2847         u8         vsd_contd_psid[16][0x8];
2848 };
2849
2850 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2851         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2852         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2853         u8         reserved_0[0x20];
2854 };
2855
2856 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2857         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2858         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2859         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2860         u8         reserved_0[0x20];
2861 };
2862
2863 struct mlx5_ifc_bufferx_reg_bits {
2864         u8         reserved_0[0x6];
2865         u8         lossy[0x1];
2866         u8         epsb[0x1];
2867         u8         reserved_1[0xc];
2868         u8         size[0xc];
2869
2870         u8         xoff_threshold[0x10];
2871         u8         xon_threshold[0x10];
2872 };
2873
2874 struct mlx5_ifc_config_item_bits {
2875         u8         valid[0x2];
2876         u8         reserved_0[0x2];
2877         u8         header_type[0x2];
2878         u8         reserved_1[0x2];
2879         u8         default_location[0x1];
2880         u8         reserved_2[0x7];
2881         u8         version[0x4];
2882         u8         reserved_3[0x3];
2883         u8         length[0x9];
2884
2885         u8         type[0x20];
2886
2887         u8         reserved_4[0x10];
2888         u8         crc16[0x10];
2889 };
2890
2891 struct mlx5_ifc_nodnic_port_config_reg_bits {
2892         struct mlx5_ifc_nodnic_event_word_bits event;
2893
2894         u8         network_en[0x1];
2895         u8         dma_en[0x1];
2896         u8         promisc_en[0x1];
2897         u8         promisc_multicast_en[0x1];
2898         u8         reserved_0[0x17];
2899         u8         receive_filter_en[0x5];
2900
2901         u8         reserved_1[0x10];
2902         u8         mac_47_32[0x10];
2903
2904         u8         mac_31_0[0x20];
2905
2906         u8         receive_filters_mgid_mac[64][0x8];
2907
2908         u8         gid[16][0x8];
2909
2910         u8         reserved_2[0x10];
2911         u8         lid[0x10];
2912
2913         u8         reserved_3[0xc];
2914         u8         sm_sl[0x4];
2915         u8         sm_lid[0x10];
2916
2917         u8         completion_address_63_32[0x20];
2918
2919         u8         completion_address_31_12[0x14];
2920         u8         reserved_4[0x6];
2921         u8         log_cq_size[0x6];
2922
2923         u8         working_buffer_address_63_32[0x20];
2924
2925         u8         working_buffer_address_31_12[0x14];
2926         u8         reserved_5[0xc];
2927
2928         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2929
2930         u8         pkey_index[0x10];
2931         u8         pkey[0x10];
2932
2933         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2934
2935         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2936
2937         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2938
2939         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2940
2941         u8         reserved_6[0x400];
2942 };
2943
2944 union mlx5_ifc_event_auto_bits {
2945         struct mlx5_ifc_comp_event_bits comp_event;
2946         struct mlx5_ifc_dct_events_bits dct_events;
2947         struct mlx5_ifc_qp_events_bits qp_events;
2948         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2949         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2950         struct mlx5_ifc_cq_error_bits cq_error;
2951         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2952         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2953         struct mlx5_ifc_gpio_event_bits gpio_event;
2954         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2955         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2956         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2957         struct mlx5_ifc_pages_req_event_bits pages_req_event;
2958         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2959         u8         reserved_0[0xe0];
2960 };
2961
2962 struct mlx5_ifc_health_buffer_bits {
2963         u8         reserved_0[0x100];
2964
2965         u8         assert_existptr[0x20];
2966
2967         u8         assert_callra[0x20];
2968
2969         u8         reserved_1[0x40];
2970
2971         u8         fw_version[0x20];
2972
2973         u8         hw_id[0x20];
2974
2975         u8         reserved_2[0x20];
2976
2977         u8         irisc_index[0x8];
2978         u8         synd[0x8];
2979         u8         ext_synd[0x10];
2980 };
2981
2982 struct mlx5_ifc_register_loopback_control_bits {
2983         u8         no_lb[0x1];
2984         u8         reserved_0[0x7];
2985         u8         port[0x8];
2986         u8         reserved_1[0x10];
2987
2988         u8         reserved_2[0x60];
2989 };
2990
2991 struct mlx5_ifc_lrh_bits {
2992         u8      vl[4];
2993         u8      lver[4];
2994         u8      sl[4];
2995         u8      reserved2[2];
2996         u8      lnh[2];
2997         u8      dlid[16];
2998         u8      reserved5[5];
2999         u8      pkt_len[11];
3000         u8      slid[16];
3001 };
3002
3003 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3004         u8         reserved_0[0x40];
3005
3006         u8         reserved_1[0x10];
3007         u8         rol_mode[0x8];
3008         u8         wol_mode[0x8];
3009 };
3010
3011 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3012         u8         reserved_0[0x40];
3013
3014         u8         rol_mode_valid[0x1];
3015         u8         wol_mode_valid[0x1];
3016         u8         reserved_1[0xe];
3017         u8         rol_mode[0x8];
3018         u8         wol_mode[0x8];
3019
3020         u8         reserved_2[0x7a0];
3021 };
3022
3023 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3024         u8         virtual_mac_en[0x1];
3025         u8         mac_aux_v[0x1];
3026         u8         reserved_0[0x1e];
3027
3028         u8         reserved_1[0x40];
3029
3030         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3031
3032         u8         reserved_2[0x760];
3033 };
3034
3035 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3036         u8         virtual_mac_en[0x1];
3037         u8         mac_aux_v[0x1];
3038         u8         reserved_0[0x1e];
3039
3040         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3041
3042         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3043
3044         u8         reserved_1[0x760];
3045 };
3046
3047 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3048         struct mlx5_ifc_fw_version_bits fw_version;
3049
3050         u8         reserved_0[0x10];
3051         u8         hash_signature[0x10];
3052
3053         u8         psid[16][0x8];
3054
3055         u8         reserved_1[0x6e0];
3056 };
3057
3058 struct mlx5_ifc_icmd_query_cap_in_bits {
3059         u8         reserved_0[0x10];
3060         u8         capability_group[0x10];
3061 };
3062
3063 struct mlx5_ifc_icmd_query_cap_general_bits {
3064         u8         nv_access[0x1];
3065         u8         fw_info_psid[0x1];
3066         u8         reserved_0[0x1e];
3067
3068         u8         reserved_1[0x16];
3069         u8         rol_s[0x1];
3070         u8         rol_g[0x1];
3071         u8         reserved_2[0x1];
3072         u8         wol_s[0x1];
3073         u8         wol_g[0x1];
3074         u8         wol_a[0x1];
3075         u8         wol_b[0x1];
3076         u8         wol_m[0x1];
3077         u8         wol_u[0x1];
3078         u8         wol_p[0x1];
3079 };
3080
3081 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3082         u8         status[0x8];
3083         u8         reserved_0[0x18];
3084
3085         u8         reserved_1[0x7e0];
3086 };
3087
3088 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3089         u8         status[0x8];
3090         u8         reserved_0[0x18];
3091
3092         u8         reserved_1[0x7e0];
3093 };
3094
3095 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3096         u8         address_hi[0x20];
3097
3098         u8         address_lo[0x20];
3099
3100         u8         reserved_0[0x7c0];
3101 };
3102
3103 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3104         u8         reserved_0[0x20];
3105
3106         u8         address_hi[0x20];
3107
3108         u8         address_lo[0x20];
3109
3110         u8         reserved_1[0x7a0];
3111 };
3112
3113 struct mlx5_ifc_icmd_access_reg_out_bits {
3114         u8         reserved_0[0x11];
3115         u8         status[0x7];
3116         u8         reserved_1[0x8];
3117
3118         u8         register_id[0x10];
3119         u8         reserved_2[0x10];
3120
3121         u8         reserved_3[0x40];
3122
3123         u8         reserved_4[0x5];
3124         u8         len[0xb];
3125         u8         reserved_5[0x10];
3126
3127         u8         register_data[0][0x20];
3128 };
3129
3130 enum {
3131         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3132         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3133 };
3134
3135 struct mlx5_ifc_icmd_access_reg_in_bits {
3136         u8         constant_1[0x5];
3137         u8         constant_2[0xb];
3138         u8         reserved_0[0x10];
3139
3140         u8         register_id[0x10];
3141         u8         reserved_1[0x1];
3142         u8         method[0x7];
3143         u8         constant_3[0x8];
3144
3145         u8         reserved_2[0x40];
3146
3147         u8         constant_4[0x5];
3148         u8         len[0xb];
3149         u8         reserved_3[0x10];
3150
3151         u8         register_data[0][0x20];
3152 };
3153
3154 enum {
3155         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3156         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3157 };
3158
3159 struct mlx5_ifc_teardown_hca_out_bits {
3160         u8         status[0x8];
3161         u8         reserved_0[0x18];
3162
3163         u8         syndrome[0x20];
3164
3165         u8         reserved_1[0x3f];
3166
3167         u8         force_state[0x1];
3168 };
3169
3170 enum {
3171         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3172         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3173 };
3174
3175 struct mlx5_ifc_teardown_hca_in_bits {
3176         u8         opcode[0x10];
3177         u8         reserved_0[0x10];
3178
3179         u8         reserved_1[0x10];
3180         u8         op_mod[0x10];
3181
3182         u8         reserved_2[0x10];
3183         u8         profile[0x10];
3184
3185         u8         reserved_3[0x20];
3186 };
3187
3188 struct mlx5_ifc_set_delay_drop_params_out_bits {
3189         u8         status[0x8];
3190         u8         reserved_at_8[0x18];
3191
3192         u8         syndrome[0x20];
3193
3194         u8         reserved_at_40[0x40];
3195 };
3196
3197 struct mlx5_ifc_set_delay_drop_params_in_bits {
3198         u8         opcode[0x10];
3199         u8         reserved_at_10[0x10];
3200
3201         u8         reserved_at_20[0x10];
3202         u8         op_mod[0x10];
3203
3204         u8         reserved_at_40[0x20];
3205
3206         u8         reserved_at_60[0x10];
3207         u8         delay_drop_timeout[0x10];
3208 };
3209
3210 struct mlx5_ifc_query_delay_drop_params_out_bits {
3211         u8         status[0x8];
3212         u8         reserved_at_8[0x18];
3213
3214         u8         syndrome[0x20];
3215
3216         u8         reserved_at_40[0x20];
3217
3218         u8         reserved_at_60[0x10];
3219         u8         delay_drop_timeout[0x10];
3220 };
3221
3222 struct mlx5_ifc_query_delay_drop_params_in_bits {
3223         u8         opcode[0x10];
3224         u8         reserved_at_10[0x10];
3225
3226         u8         reserved_at_20[0x10];
3227         u8         op_mod[0x10];
3228
3229         u8         reserved_at_40[0x40];
3230 };
3231
3232 struct mlx5_ifc_suspend_qp_out_bits {
3233         u8         status[0x8];
3234         u8         reserved_0[0x18];
3235
3236         u8         syndrome[0x20];
3237
3238         u8         reserved_1[0x40];
3239 };
3240
3241 struct mlx5_ifc_suspend_qp_in_bits {
3242         u8         opcode[0x10];
3243         u8         reserved_0[0x10];
3244
3245         u8         reserved_1[0x10];
3246         u8         op_mod[0x10];
3247
3248         u8         reserved_2[0x8];
3249         u8         qpn[0x18];
3250
3251         u8         reserved_3[0x20];
3252 };
3253
3254 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3255         u8         status[0x8];
3256         u8         reserved_0[0x18];
3257
3258         u8         syndrome[0x20];
3259
3260         u8         reserved_1[0x40];
3261 };
3262
3263 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3264         u8         opcode[0x10];
3265         u8         reserved_0[0x10];
3266
3267         u8         reserved_1[0x10];
3268         u8         op_mod[0x10];
3269
3270         u8         reserved_2[0x8];
3271         u8         qpn[0x18];
3272
3273         u8         reserved_3[0x20];
3274
3275         u8         opt_param_mask[0x20];
3276
3277         u8         reserved_4[0x20];
3278
3279         struct mlx5_ifc_qpc_bits qpc;
3280
3281         u8         reserved_5[0x80];
3282 };
3283
3284 struct mlx5_ifc_sqd2rts_qp_out_bits {
3285         u8         status[0x8];
3286         u8         reserved_0[0x18];
3287
3288         u8         syndrome[0x20];
3289
3290         u8         reserved_1[0x40];
3291 };
3292
3293 struct mlx5_ifc_sqd2rts_qp_in_bits {
3294         u8         opcode[0x10];
3295         u8         reserved_0[0x10];
3296
3297         u8         reserved_1[0x10];
3298         u8         op_mod[0x10];
3299
3300         u8         reserved_2[0x8];
3301         u8         qpn[0x18];
3302
3303         u8         reserved_3[0x20];
3304
3305         u8         opt_param_mask[0x20];
3306
3307         u8         reserved_4[0x20];
3308
3309         struct mlx5_ifc_qpc_bits qpc;
3310
3311         u8         reserved_5[0x80];
3312 };
3313
3314 struct mlx5_ifc_set_wol_rol_out_bits {
3315         u8         status[0x8];
3316         u8         reserved_0[0x18];
3317
3318         u8         syndrome[0x20];
3319
3320         u8         reserved_1[0x40];
3321 };
3322
3323 struct mlx5_ifc_set_wol_rol_in_bits {
3324         u8         opcode[0x10];
3325         u8         reserved_0[0x10];
3326
3327         u8         reserved_1[0x10];
3328         u8         op_mod[0x10];
3329
3330         u8         rol_mode_valid[0x1];
3331         u8         wol_mode_valid[0x1];
3332         u8         reserved_2[0xe];
3333         u8         rol_mode[0x8];
3334         u8         wol_mode[0x8];
3335
3336         u8         reserved_3[0x20];
3337 };
3338
3339 struct mlx5_ifc_set_roce_address_out_bits {
3340         u8         status[0x8];
3341         u8         reserved_0[0x18];
3342
3343         u8         syndrome[0x20];
3344
3345         u8         reserved_1[0x40];
3346 };
3347
3348 struct mlx5_ifc_set_roce_address_in_bits {
3349         u8         opcode[0x10];
3350         u8         reserved_0[0x10];
3351
3352         u8         reserved_1[0x10];
3353         u8         op_mod[0x10];
3354
3355         u8         roce_address_index[0x10];
3356         u8         reserved_2[0x10];
3357
3358         u8         reserved_3[0x20];
3359
3360         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3361 };
3362
3363 struct mlx5_ifc_set_rdb_out_bits {
3364         u8         status[0x8];
3365         u8         reserved_0[0x18];
3366
3367         u8         syndrome[0x20];
3368
3369         u8         reserved_1[0x40];
3370 };
3371
3372 struct mlx5_ifc_set_rdb_in_bits {
3373         u8         opcode[0x10];
3374         u8         reserved_0[0x10];
3375
3376         u8         reserved_1[0x10];
3377         u8         op_mod[0x10];
3378
3379         u8         reserved_2[0x8];
3380         u8         qpn[0x18];
3381
3382         u8         reserved_3[0x18];
3383         u8         rdb_list_size[0x8];
3384
3385         struct mlx5_ifc_rdbc_bits rdb_context[0];
3386 };
3387
3388 struct mlx5_ifc_set_mad_demux_out_bits {
3389         u8         status[0x8];
3390         u8         reserved_0[0x18];
3391
3392         u8         syndrome[0x20];
3393
3394         u8         reserved_1[0x40];
3395 };
3396
3397 enum {
3398         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3399         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3400 };
3401
3402 struct mlx5_ifc_set_mad_demux_in_bits {
3403         u8         opcode[0x10];
3404         u8         reserved_0[0x10];
3405
3406         u8         reserved_1[0x10];
3407         u8         op_mod[0x10];
3408
3409         u8         reserved_2[0x20];
3410
3411         u8         reserved_3[0x6];
3412         u8         demux_mode[0x2];
3413         u8         reserved_4[0x18];
3414 };
3415
3416 struct mlx5_ifc_set_l2_table_entry_out_bits {
3417         u8         status[0x8];
3418         u8         reserved_0[0x18];
3419
3420         u8         syndrome[0x20];
3421
3422         u8         reserved_1[0x40];
3423 };
3424
3425 struct mlx5_ifc_set_l2_table_entry_in_bits {
3426         u8         opcode[0x10];
3427         u8         reserved_0[0x10];
3428
3429         u8         reserved_1[0x10];
3430         u8         op_mod[0x10];
3431
3432         u8         reserved_2[0x60];
3433
3434         u8         reserved_3[0x8];
3435         u8         table_index[0x18];
3436
3437         u8         reserved_4[0x20];
3438
3439         u8         reserved_5[0x13];
3440         u8         vlan_valid[0x1];
3441         u8         vlan[0xc];
3442
3443         struct mlx5_ifc_mac_address_layout_bits mac_address;
3444
3445         u8         reserved_6[0xc0];
3446 };
3447
3448 struct mlx5_ifc_set_issi_out_bits {
3449         u8         status[0x8];
3450         u8         reserved_0[0x18];
3451
3452         u8         syndrome[0x20];
3453
3454         u8         reserved_1[0x40];
3455 };
3456
3457 struct mlx5_ifc_set_issi_in_bits {
3458         u8         opcode[0x10];
3459         u8         reserved_0[0x10];
3460
3461         u8         reserved_1[0x10];
3462         u8         op_mod[0x10];
3463
3464         u8         reserved_2[0x10];
3465         u8         current_issi[0x10];
3466
3467         u8         reserved_3[0x20];
3468 };
3469
3470 struct mlx5_ifc_set_hca_cap_out_bits {
3471         u8         status[0x8];
3472         u8         reserved_0[0x18];
3473
3474         u8         syndrome[0x20];
3475
3476         u8         reserved_1[0x40];
3477 };
3478
3479 struct mlx5_ifc_set_hca_cap_in_bits {
3480         u8         opcode[0x10];
3481         u8         reserved_0[0x10];
3482
3483         u8         reserved_1[0x10];
3484         u8         op_mod[0x10];
3485
3486         u8         reserved_2[0x40];
3487
3488         union mlx5_ifc_hca_cap_union_bits capability;
3489 };
3490
3491 enum {
3492         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3493         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3494         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3495         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3496 };
3497
3498 struct mlx5_ifc_set_flow_table_root_out_bits {
3499         u8         status[0x8];
3500         u8         reserved_0[0x18];
3501
3502         u8         syndrome[0x20];
3503
3504         u8         reserved_1[0x40];
3505 };
3506
3507 struct mlx5_ifc_set_flow_table_root_in_bits {
3508         u8         opcode[0x10];
3509         u8         reserved_0[0x10];
3510
3511         u8         reserved_1[0x10];
3512         u8         op_mod[0x10];
3513
3514         u8         other_vport[0x1];
3515         u8         reserved_2[0xf];
3516         u8         vport_number[0x10];
3517
3518         u8         reserved_3[0x20];
3519
3520         u8         table_type[0x8];
3521         u8         reserved_4[0x18];
3522
3523         u8         reserved_5[0x8];
3524         u8         table_id[0x18];
3525
3526         u8         reserved_6[0x8];
3527         u8         underlay_qpn[0x18];
3528
3529         u8         reserved_7[0x120];
3530 };
3531
3532 struct mlx5_ifc_set_fte_out_bits {
3533         u8         status[0x8];
3534         u8         reserved_0[0x18];
3535
3536         u8         syndrome[0x20];
3537
3538         u8         reserved_1[0x40];
3539 };
3540
3541 struct mlx5_ifc_set_fte_in_bits {
3542         u8         opcode[0x10];
3543         u8         reserved_0[0x10];
3544
3545         u8         reserved_1[0x10];
3546         u8         op_mod[0x10];
3547
3548         u8         other_vport[0x1];
3549         u8         reserved_2[0xf];
3550         u8         vport_number[0x10];
3551
3552         u8         reserved_3[0x20];
3553
3554         u8         table_type[0x8];
3555         u8         reserved_4[0x18];
3556
3557         u8         reserved_5[0x8];
3558         u8         table_id[0x18];
3559
3560         u8         reserved_6[0x18];
3561         u8         modify_enable_mask[0x8];
3562
3563         u8         reserved_7[0x20];
3564
3565         u8         flow_index[0x20];
3566
3567         u8         reserved_8[0xe0];
3568
3569         struct mlx5_ifc_flow_context_bits flow_context;
3570 };
3571
3572 struct mlx5_ifc_set_driver_version_out_bits {
3573         u8         status[0x8];
3574         u8         reserved_0[0x18];
3575
3576         u8         syndrome[0x20];
3577
3578         u8         reserved_1[0x40];
3579 };
3580
3581 struct mlx5_ifc_set_driver_version_in_bits {
3582         u8         opcode[0x10];
3583         u8         reserved_0[0x10];
3584
3585         u8         reserved_1[0x10];
3586         u8         op_mod[0x10];
3587
3588         u8         reserved_2[0x40];
3589
3590         u8         driver_version[64][0x8];
3591 };
3592
3593 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3594         u8         status[0x8];
3595         u8         reserved_0[0x18];
3596
3597         u8         syndrome[0x20];
3598
3599         u8         reserved_1[0x40];
3600 };
3601
3602 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3603         u8         opcode[0x10];
3604         u8         reserved_0[0x10];
3605
3606         u8         reserved_1[0x10];
3607         u8         op_mod[0x10];
3608
3609         u8         enable[0x1];
3610         u8         reserved_2[0x1f];
3611
3612         u8         reserved_3[0x160];
3613
3614         struct mlx5_ifc_cmd_pas_bits pas;
3615 };
3616
3617 struct mlx5_ifc_set_burst_size_out_bits {
3618         u8         status[0x8];
3619         u8         reserved_0[0x18];
3620
3621         u8         syndrome[0x20];
3622
3623         u8         reserved_1[0x40];
3624 };
3625
3626 struct mlx5_ifc_set_burst_size_in_bits {
3627         u8         opcode[0x10];
3628         u8         reserved_0[0x10];
3629
3630         u8         reserved_1[0x10];
3631         u8         op_mod[0x10];
3632
3633         u8         reserved_2[0x20];
3634
3635         u8         reserved_3[0x9];
3636         u8         device_burst_size[0x17];
3637 };
3638
3639 struct mlx5_ifc_rts2rts_qp_out_bits {
3640         u8         status[0x8];
3641         u8         reserved_0[0x18];
3642
3643         u8         syndrome[0x20];
3644
3645         u8         reserved_1[0x40];
3646 };
3647
3648 struct mlx5_ifc_rts2rts_qp_in_bits {
3649         u8         opcode[0x10];
3650         u8         reserved_0[0x10];
3651
3652         u8         reserved_1[0x10];
3653         u8         op_mod[0x10];
3654
3655         u8         reserved_2[0x8];
3656         u8         qpn[0x18];
3657
3658         u8         reserved_3[0x20];
3659
3660         u8         opt_param_mask[0x20];
3661
3662         u8         reserved_4[0x20];
3663
3664         struct mlx5_ifc_qpc_bits qpc;
3665
3666         u8         reserved_5[0x80];
3667 };
3668
3669 struct mlx5_ifc_rtr2rts_qp_out_bits {
3670         u8         status[0x8];
3671         u8         reserved_0[0x18];
3672
3673         u8         syndrome[0x20];
3674
3675         u8         reserved_1[0x40];
3676 };
3677
3678 struct mlx5_ifc_rtr2rts_qp_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_0[0x10];
3681
3682         u8         reserved_1[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         reserved_2[0x8];
3686         u8         qpn[0x18];
3687
3688         u8         reserved_3[0x20];
3689
3690         u8         opt_param_mask[0x20];
3691
3692         u8         reserved_4[0x20];
3693
3694         struct mlx5_ifc_qpc_bits qpc;
3695
3696         u8         reserved_5[0x80];
3697 };
3698
3699 struct mlx5_ifc_rst2init_qp_out_bits {
3700         u8         status[0x8];
3701         u8         reserved_0[0x18];
3702
3703         u8         syndrome[0x20];
3704
3705         u8         reserved_1[0x40];
3706 };
3707
3708 struct mlx5_ifc_rst2init_qp_in_bits {
3709         u8         opcode[0x10];
3710         u8         reserved_0[0x10];
3711
3712         u8         reserved_1[0x10];
3713         u8         op_mod[0x10];
3714
3715         u8         reserved_2[0x8];
3716         u8         qpn[0x18];
3717
3718         u8         reserved_3[0x20];
3719
3720         u8         opt_param_mask[0x20];
3721
3722         u8         reserved_4[0x20];
3723
3724         struct mlx5_ifc_qpc_bits qpc;
3725
3726         u8         reserved_5[0x80];
3727 };
3728
3729 struct mlx5_ifc_resume_qp_out_bits {
3730         u8         status[0x8];
3731         u8         reserved_0[0x18];
3732
3733         u8         syndrome[0x20];
3734
3735         u8         reserved_1[0x40];
3736 };
3737
3738 struct mlx5_ifc_resume_qp_in_bits {
3739         u8         opcode[0x10];
3740         u8         reserved_0[0x10];
3741
3742         u8         reserved_1[0x10];
3743         u8         op_mod[0x10];
3744
3745         u8         reserved_2[0x8];
3746         u8         qpn[0x18];
3747
3748         u8         reserved_3[0x20];
3749 };
3750
3751 struct mlx5_ifc_query_xrc_srq_out_bits {
3752         u8         status[0x8];
3753         u8         reserved_0[0x18];
3754
3755         u8         syndrome[0x20];
3756
3757         u8         reserved_1[0x40];
3758
3759         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3760
3761         u8         reserved_2[0x600];
3762
3763         u8         pas[0][0x40];
3764 };
3765
3766 struct mlx5_ifc_query_xrc_srq_in_bits {
3767         u8         opcode[0x10];
3768         u8         reserved_0[0x10];
3769
3770         u8         reserved_1[0x10];
3771         u8         op_mod[0x10];
3772
3773         u8         reserved_2[0x8];
3774         u8         xrc_srqn[0x18];
3775
3776         u8         reserved_3[0x20];
3777 };
3778
3779 struct mlx5_ifc_query_wol_rol_out_bits {
3780         u8         status[0x8];
3781         u8         reserved_0[0x18];
3782
3783         u8         syndrome[0x20];
3784
3785         u8         reserved_1[0x10];
3786         u8         rol_mode[0x8];
3787         u8         wol_mode[0x8];
3788
3789         u8         reserved_2[0x20];
3790 };
3791
3792 struct mlx5_ifc_query_wol_rol_in_bits {
3793         u8         opcode[0x10];
3794         u8         reserved_0[0x10];
3795
3796         u8         reserved_1[0x10];
3797         u8         op_mod[0x10];
3798
3799         u8         reserved_2[0x40];
3800 };
3801
3802 enum {
3803         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3804         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3805 };
3806
3807 struct mlx5_ifc_query_vport_state_out_bits {
3808         u8         status[0x8];
3809         u8         reserved_0[0x18];
3810
3811         u8         syndrome[0x20];
3812
3813         u8         reserved_1[0x20];
3814
3815         u8         reserved_2[0x18];
3816         u8         admin_state[0x4];
3817         u8         state[0x4];
3818 };
3819
3820 enum {
3821         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3822         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3823         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3824 };
3825
3826 struct mlx5_ifc_query_vport_state_in_bits {
3827         u8         opcode[0x10];
3828         u8         reserved_0[0x10];
3829
3830         u8         reserved_1[0x10];
3831         u8         op_mod[0x10];
3832
3833         u8         other_vport[0x1];
3834         u8         reserved_2[0xf];
3835         u8         vport_number[0x10];
3836
3837         u8         reserved_3[0x20];
3838 };
3839
3840 struct mlx5_ifc_query_vport_counter_out_bits {
3841         u8         status[0x8];
3842         u8         reserved_0[0x18];
3843
3844         u8         syndrome[0x20];
3845
3846         u8         reserved_1[0x40];
3847
3848         struct mlx5_ifc_traffic_counter_bits received_errors;
3849
3850         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3851
3852         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3853
3854         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3855
3856         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3857
3858         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3859
3860         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3861
3862         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3863
3864         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3865
3866         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3867
3868         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3869
3870         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3871
3872         u8         reserved_2[0xa00];
3873 };
3874
3875 enum {
3876         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3877 };
3878
3879 struct mlx5_ifc_query_vport_counter_in_bits {
3880         u8         opcode[0x10];
3881         u8         reserved_0[0x10];
3882
3883         u8         reserved_1[0x10];
3884         u8         op_mod[0x10];
3885
3886         u8         other_vport[0x1];
3887         u8         reserved_2[0xb];
3888         u8         port_num[0x4];
3889         u8         vport_number[0x10];
3890
3891         u8         reserved_3[0x60];
3892
3893         u8         clear[0x1];
3894         u8         reserved_4[0x1f];
3895
3896         u8         reserved_5[0x20];
3897 };
3898
3899 struct mlx5_ifc_query_tis_out_bits {
3900         u8         status[0x8];
3901         u8         reserved_0[0x18];
3902
3903         u8         syndrome[0x20];
3904
3905         u8         reserved_1[0x40];
3906
3907         struct mlx5_ifc_tisc_bits tis_context;
3908 };
3909
3910 struct mlx5_ifc_query_tis_in_bits {
3911         u8         opcode[0x10];
3912         u8         reserved_0[0x10];
3913
3914         u8         reserved_1[0x10];
3915         u8         op_mod[0x10];
3916
3917         u8         reserved_2[0x8];
3918         u8         tisn[0x18];
3919
3920         u8         reserved_3[0x20];
3921 };
3922
3923 struct mlx5_ifc_query_tir_out_bits {
3924         u8         status[0x8];
3925         u8         reserved_0[0x18];
3926
3927         u8         syndrome[0x20];
3928
3929         u8         reserved_1[0xc0];
3930
3931         struct mlx5_ifc_tirc_bits tir_context;
3932 };
3933
3934 struct mlx5_ifc_query_tir_in_bits {
3935         u8         opcode[0x10];
3936         u8         reserved_0[0x10];
3937
3938         u8         reserved_1[0x10];
3939         u8         op_mod[0x10];
3940
3941         u8         reserved_2[0x8];
3942         u8         tirn[0x18];
3943
3944         u8         reserved_3[0x20];
3945 };
3946
3947 struct mlx5_ifc_query_srq_out_bits {
3948         u8         status[0x8];
3949         u8         reserved_0[0x18];
3950
3951         u8         syndrome[0x20];
3952
3953         u8         reserved_1[0x40];
3954
3955         struct mlx5_ifc_srqc_bits srq_context_entry;
3956
3957         u8         reserved_2[0x600];
3958
3959         u8         pas[0][0x40];
3960 };
3961
3962 struct mlx5_ifc_query_srq_in_bits {
3963         u8         opcode[0x10];
3964         u8         reserved_0[0x10];
3965
3966         u8         reserved_1[0x10];
3967         u8         op_mod[0x10];
3968
3969         u8         reserved_2[0x8];
3970         u8         srqn[0x18];
3971
3972         u8         reserved_3[0x20];
3973 };
3974
3975 struct mlx5_ifc_query_sq_out_bits {
3976         u8         status[0x8];
3977         u8         reserved_0[0x18];
3978
3979         u8         syndrome[0x20];
3980
3981         u8         reserved_1[0xc0];
3982
3983         struct mlx5_ifc_sqc_bits sq_context;
3984 };
3985
3986 struct mlx5_ifc_query_sq_in_bits {
3987         u8         opcode[0x10];
3988         u8         reserved_0[0x10];
3989
3990         u8         reserved_1[0x10];
3991         u8         op_mod[0x10];
3992
3993         u8         reserved_2[0x8];
3994         u8         sqn[0x18];
3995
3996         u8         reserved_3[0x20];
3997 };
3998
3999 struct mlx5_ifc_query_special_contexts_out_bits {
4000         u8         status[0x8];
4001         u8         reserved_0[0x18];
4002
4003         u8         syndrome[0x20];
4004
4005         u8         dump_fill_mkey[0x20];
4006
4007         u8         resd_lkey[0x20];
4008 };
4009
4010 struct mlx5_ifc_query_special_contexts_in_bits {
4011         u8         opcode[0x10];
4012         u8         reserved_0[0x10];
4013
4014         u8         reserved_1[0x10];
4015         u8         op_mod[0x10];
4016
4017         u8         reserved_2[0x40];
4018 };
4019
4020 struct mlx5_ifc_query_scheduling_element_out_bits {
4021         u8         status[0x8];
4022         u8         reserved_at_8[0x18];
4023
4024         u8         syndrome[0x20];
4025
4026         u8         reserved_at_40[0xc0];
4027
4028         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4029
4030         u8         reserved_at_300[0x100];
4031 };
4032
4033 enum {
4034         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4035 };
4036
4037 struct mlx5_ifc_query_scheduling_element_in_bits {
4038         u8         opcode[0x10];
4039         u8         reserved_at_10[0x10];
4040
4041         u8         reserved_at_20[0x10];
4042         u8         op_mod[0x10];
4043
4044         u8         scheduling_hierarchy[0x8];
4045         u8         reserved_at_48[0x18];
4046
4047         u8         scheduling_element_id[0x20];
4048
4049         u8         reserved_at_80[0x180];
4050 };
4051
4052 struct mlx5_ifc_query_rqt_out_bits {
4053         u8         status[0x8];
4054         u8         reserved_0[0x18];
4055
4056         u8         syndrome[0x20];
4057
4058         u8         reserved_1[0xc0];
4059
4060         struct mlx5_ifc_rqtc_bits rqt_context;
4061 };
4062
4063 struct mlx5_ifc_query_rqt_in_bits {
4064         u8         opcode[0x10];
4065         u8         reserved_0[0x10];
4066
4067         u8         reserved_1[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_2[0x8];
4071         u8         rqtn[0x18];
4072
4073         u8         reserved_3[0x20];
4074 };
4075
4076 struct mlx5_ifc_query_rq_out_bits {
4077         u8         status[0x8];
4078         u8         reserved_0[0x18];
4079
4080         u8         syndrome[0x20];
4081
4082         u8         reserved_1[0xc0];
4083
4084         struct mlx5_ifc_rqc_bits rq_context;
4085 };
4086
4087 struct mlx5_ifc_query_rq_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_0[0x10];
4090
4091         u8         reserved_1[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         reserved_2[0x8];
4095         u8         rqn[0x18];
4096
4097         u8         reserved_3[0x20];
4098 };
4099
4100 struct mlx5_ifc_query_roce_address_out_bits {
4101         u8         status[0x8];
4102         u8         reserved_0[0x18];
4103
4104         u8         syndrome[0x20];
4105
4106         u8         reserved_1[0x40];
4107
4108         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4109 };
4110
4111 struct mlx5_ifc_query_roce_address_in_bits {
4112         u8         opcode[0x10];
4113         u8         reserved_0[0x10];
4114
4115         u8         reserved_1[0x10];
4116         u8         op_mod[0x10];
4117
4118         u8         roce_address_index[0x10];
4119         u8         reserved_2[0x10];
4120
4121         u8         reserved_3[0x20];
4122 };
4123
4124 struct mlx5_ifc_query_rmp_out_bits {
4125         u8         status[0x8];
4126         u8         reserved_0[0x18];
4127
4128         u8         syndrome[0x20];
4129
4130         u8         reserved_1[0xc0];
4131
4132         struct mlx5_ifc_rmpc_bits rmp_context;
4133 };
4134
4135 struct mlx5_ifc_query_rmp_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_0[0x10];
4138
4139         u8         reserved_1[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_2[0x8];
4143         u8         rmpn[0x18];
4144
4145         u8         reserved_3[0x20];
4146 };
4147
4148 struct mlx5_ifc_query_rdb_out_bits {
4149         u8         status[0x8];
4150         u8         reserved_0[0x18];
4151
4152         u8         syndrome[0x20];
4153
4154         u8         reserved_1[0x20];
4155
4156         u8         reserved_2[0x18];
4157         u8         rdb_list_size[0x8];
4158
4159         struct mlx5_ifc_rdbc_bits rdb_context[0];
4160 };
4161
4162 struct mlx5_ifc_query_rdb_in_bits {
4163         u8         opcode[0x10];
4164         u8         reserved_0[0x10];
4165
4166         u8         reserved_1[0x10];
4167         u8         op_mod[0x10];
4168
4169         u8         reserved_2[0x8];
4170         u8         qpn[0x18];
4171
4172         u8         reserved_3[0x20];
4173 };
4174
4175 struct mlx5_ifc_query_qp_out_bits {
4176         u8         status[0x8];
4177         u8         reserved_0[0x18];
4178
4179         u8         syndrome[0x20];
4180
4181         u8         reserved_1[0x40];
4182
4183         u8         opt_param_mask[0x20];
4184
4185         u8         reserved_2[0x20];
4186
4187         struct mlx5_ifc_qpc_bits qpc;
4188
4189         u8         reserved_3[0x80];
4190
4191         u8         pas[0][0x40];
4192 };
4193
4194 struct mlx5_ifc_query_qp_in_bits {
4195         u8         opcode[0x10];
4196         u8         reserved_0[0x10];
4197
4198         u8         reserved_1[0x10];
4199         u8         op_mod[0x10];
4200
4201         u8         reserved_2[0x8];
4202         u8         qpn[0x18];
4203
4204         u8         reserved_3[0x20];
4205 };
4206
4207 struct mlx5_ifc_query_q_counter_out_bits {
4208         u8         status[0x8];
4209         u8         reserved_0[0x18];
4210
4211         u8         syndrome[0x20];
4212
4213         u8         reserved_1[0x40];
4214
4215         u8         rx_write_requests[0x20];
4216
4217         u8         reserved_2[0x20];
4218
4219         u8         rx_read_requests[0x20];
4220
4221         u8         reserved_3[0x20];
4222
4223         u8         rx_atomic_requests[0x20];
4224
4225         u8         reserved_4[0x20];
4226
4227         u8         rx_dct_connect[0x20];
4228
4229         u8         reserved_5[0x20];
4230
4231         u8         out_of_buffer[0x20];
4232
4233         u8         reserved_7[0x20];
4234
4235         u8         out_of_sequence[0x20];
4236
4237         u8         reserved_8[0x20];
4238
4239         u8         duplicate_request[0x20];
4240
4241         u8         reserved_9[0x20];
4242
4243         u8         rnr_nak_retry_err[0x20];
4244
4245         u8         reserved_10[0x20];
4246
4247         u8         packet_seq_err[0x20];
4248
4249         u8         reserved_11[0x20];
4250
4251         u8         implied_nak_seq_err[0x20];
4252
4253         u8         reserved_12[0x20];
4254
4255         u8         local_ack_timeout_err[0x20];
4256
4257         u8         reserved_13[0x20];
4258
4259         u8         resp_rnr_nak[0x20];
4260
4261         u8         reserved_14[0x20];
4262
4263         u8         req_rnr_retries_exceeded[0x20];
4264
4265         u8         reserved_15[0x460];
4266 };
4267
4268 struct mlx5_ifc_query_q_counter_in_bits {
4269         u8         opcode[0x10];
4270         u8         reserved_0[0x10];
4271
4272         u8         reserved_1[0x10];
4273         u8         op_mod[0x10];
4274
4275         u8         reserved_2[0x80];
4276
4277         u8         clear[0x1];
4278         u8         reserved_3[0x1f];
4279
4280         u8         reserved_4[0x18];
4281         u8         counter_set_id[0x8];
4282 };
4283
4284 struct mlx5_ifc_query_pages_out_bits {
4285         u8         status[0x8];
4286         u8         reserved_0[0x18];
4287
4288         u8         syndrome[0x20];
4289
4290         u8         reserved_1[0x10];
4291         u8         function_id[0x10];
4292
4293         u8         num_pages[0x20];
4294 };
4295
4296 enum {
4297         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4298         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4299         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4300 };
4301
4302 struct mlx5_ifc_query_pages_in_bits {
4303         u8         opcode[0x10];
4304         u8         reserved_0[0x10];
4305
4306         u8         reserved_1[0x10];
4307         u8         op_mod[0x10];
4308
4309         u8         reserved_2[0x10];
4310         u8         function_id[0x10];
4311
4312         u8         reserved_3[0x20];
4313 };
4314
4315 struct mlx5_ifc_query_nic_vport_context_out_bits {
4316         u8         status[0x8];
4317         u8         reserved_0[0x18];
4318
4319         u8         syndrome[0x20];
4320
4321         u8         reserved_1[0x40];
4322
4323         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4324 };
4325
4326 struct mlx5_ifc_query_nic_vport_context_in_bits {
4327         u8         opcode[0x10];
4328         u8         reserved_0[0x10];
4329
4330         u8         reserved_1[0x10];
4331         u8         op_mod[0x10];
4332
4333         u8         other_vport[0x1];
4334         u8         reserved_2[0xf];
4335         u8         vport_number[0x10];
4336
4337         u8         reserved_3[0x5];
4338         u8         allowed_list_type[0x3];
4339         u8         reserved_4[0x18];
4340 };
4341
4342 struct mlx5_ifc_query_mkey_out_bits {
4343         u8         status[0x8];
4344         u8         reserved_0[0x18];
4345
4346         u8         syndrome[0x20];
4347
4348         u8         reserved_1[0x40];
4349
4350         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4351
4352         u8         reserved_2[0x600];
4353
4354         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4355
4356         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4357 };
4358
4359 struct mlx5_ifc_query_mkey_in_bits {
4360         u8         opcode[0x10];
4361         u8         reserved_0[0x10];
4362
4363         u8         reserved_1[0x10];
4364         u8         op_mod[0x10];
4365
4366         u8         reserved_2[0x8];
4367         u8         mkey_index[0x18];
4368
4369         u8         pg_access[0x1];
4370         u8         reserved_3[0x1f];
4371 };
4372
4373 struct mlx5_ifc_query_mad_demux_out_bits {
4374         u8         status[0x8];
4375         u8         reserved_0[0x18];
4376
4377         u8         syndrome[0x20];
4378
4379         u8         reserved_1[0x40];
4380
4381         u8         mad_dumux_parameters_block[0x20];
4382 };
4383
4384 struct mlx5_ifc_query_mad_demux_in_bits {
4385         u8         opcode[0x10];
4386         u8         reserved_0[0x10];
4387
4388         u8         reserved_1[0x10];
4389         u8         op_mod[0x10];
4390
4391         u8         reserved_2[0x40];
4392 };
4393
4394 struct mlx5_ifc_query_l2_table_entry_out_bits {
4395         u8         status[0x8];
4396         u8         reserved_0[0x18];
4397
4398         u8         syndrome[0x20];
4399
4400         u8         reserved_1[0xa0];
4401
4402         u8         reserved_2[0x13];
4403         u8         vlan_valid[0x1];
4404         u8         vlan[0xc];
4405
4406         struct mlx5_ifc_mac_address_layout_bits mac_address;
4407
4408         u8         reserved_3[0xc0];
4409 };
4410
4411 struct mlx5_ifc_query_l2_table_entry_in_bits {
4412         u8         opcode[0x10];
4413         u8         reserved_0[0x10];
4414
4415         u8         reserved_1[0x10];
4416         u8         op_mod[0x10];
4417
4418         u8         reserved_2[0x60];
4419
4420         u8         reserved_3[0x8];
4421         u8         table_index[0x18];
4422
4423         u8         reserved_4[0x140];
4424 };
4425
4426 struct mlx5_ifc_query_issi_out_bits {
4427         u8         status[0x8];
4428         u8         reserved_0[0x18];
4429
4430         u8         syndrome[0x20];
4431
4432         u8         reserved_1[0x10];
4433         u8         current_issi[0x10];
4434
4435         u8         reserved_2[0xa0];
4436
4437         u8         supported_issi_reserved[76][0x8];
4438         u8         supported_issi_dw0[0x20];
4439 };
4440
4441 struct mlx5_ifc_query_issi_in_bits {
4442         u8         opcode[0x10];
4443         u8         reserved_0[0x10];
4444
4445         u8         reserved_1[0x10];
4446         u8         op_mod[0x10];
4447
4448         u8         reserved_2[0x40];
4449 };
4450
4451 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4452         u8         status[0x8];
4453         u8         reserved_0[0x18];
4454
4455         u8         syndrome[0x20];
4456
4457         u8         reserved_1[0x40];
4458
4459         struct mlx5_ifc_pkey_bits pkey[0];
4460 };
4461
4462 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4463         u8         opcode[0x10];
4464         u8         reserved_0[0x10];
4465
4466         u8         reserved_1[0x10];
4467         u8         op_mod[0x10];
4468
4469         u8         other_vport[0x1];
4470         u8         reserved_2[0xb];
4471         u8         port_num[0x4];
4472         u8         vport_number[0x10];
4473
4474         u8         reserved_3[0x10];
4475         u8         pkey_index[0x10];
4476 };
4477
4478 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4479         u8         status[0x8];
4480         u8         reserved_0[0x18];
4481
4482         u8         syndrome[0x20];
4483
4484         u8         reserved_1[0x20];
4485
4486         u8         gids_num[0x10];
4487         u8         reserved_2[0x10];
4488
4489         struct mlx5_ifc_array128_auto_bits gid[0];
4490 };
4491
4492 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4493         u8         opcode[0x10];
4494         u8         reserved_0[0x10];
4495
4496         u8         reserved_1[0x10];
4497         u8         op_mod[0x10];
4498
4499         u8         other_vport[0x1];
4500         u8         reserved_2[0xb];
4501         u8         port_num[0x4];
4502         u8         vport_number[0x10];
4503
4504         u8         reserved_3[0x10];
4505         u8         gid_index[0x10];
4506 };
4507
4508 struct mlx5_ifc_query_hca_vport_context_out_bits {
4509         u8         status[0x8];
4510         u8         reserved_0[0x18];
4511
4512         u8         syndrome[0x20];
4513
4514         u8         reserved_1[0x40];
4515
4516         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4517 };
4518
4519 struct mlx5_ifc_query_hca_vport_context_in_bits {
4520         u8         opcode[0x10];
4521         u8         reserved_0[0x10];
4522
4523         u8         reserved_1[0x10];
4524         u8         op_mod[0x10];
4525
4526         u8         other_vport[0x1];
4527         u8         reserved_2[0xb];
4528         u8         port_num[0x4];
4529         u8         vport_number[0x10];
4530
4531         u8         reserved_3[0x20];
4532 };
4533
4534 struct mlx5_ifc_query_hca_cap_out_bits {
4535         u8         status[0x8];
4536         u8         reserved_0[0x18];
4537
4538         u8         syndrome[0x20];
4539
4540         u8         reserved_1[0x40];
4541
4542         union mlx5_ifc_hca_cap_union_bits capability;
4543 };
4544
4545 struct mlx5_ifc_query_hca_cap_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_0[0x10];
4548
4549         u8         reserved_1[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         reserved_2[0x40];
4553 };
4554
4555 struct mlx5_ifc_query_flow_table_out_bits {
4556         u8         status[0x8];
4557         u8         reserved_at_8[0x18];
4558
4559         u8         syndrome[0x20];
4560
4561         u8         reserved_at_40[0x80];
4562
4563         struct mlx5_ifc_flow_table_context_bits flow_table_context;
4564 };
4565
4566 struct mlx5_ifc_query_flow_table_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_0[0x10];
4569
4570         u8         reserved_1[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         other_vport[0x1];
4574         u8         reserved_2[0xf];
4575         u8         vport_number[0x10];
4576
4577         u8         reserved_3[0x20];
4578
4579         u8         table_type[0x8];
4580         u8         reserved_4[0x18];
4581
4582         u8         reserved_5[0x8];
4583         u8         table_id[0x18];
4584
4585         u8         reserved_6[0x140];
4586 };
4587
4588 struct mlx5_ifc_query_fte_out_bits {
4589         u8         status[0x8];
4590         u8         reserved_0[0x18];
4591
4592         u8         syndrome[0x20];
4593
4594         u8         reserved_1[0x1c0];
4595
4596         struct mlx5_ifc_flow_context_bits flow_context;
4597 };
4598
4599 struct mlx5_ifc_query_fte_in_bits {
4600         u8         opcode[0x10];
4601         u8         reserved_0[0x10];
4602
4603         u8         reserved_1[0x10];
4604         u8         op_mod[0x10];
4605
4606         u8         other_vport[0x1];
4607         u8         reserved_2[0xf];
4608         u8         vport_number[0x10];
4609
4610         u8         reserved_3[0x20];
4611
4612         u8         table_type[0x8];
4613         u8         reserved_4[0x18];
4614
4615         u8         reserved_5[0x8];
4616         u8         table_id[0x18];
4617
4618         u8         reserved_6[0x40];
4619
4620         u8         flow_index[0x20];
4621
4622         u8         reserved_7[0xe0];
4623 };
4624
4625 enum {
4626         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4627         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4628         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4629 };
4630
4631 struct mlx5_ifc_query_flow_group_out_bits {
4632         u8         status[0x8];
4633         u8         reserved_0[0x18];
4634
4635         u8         syndrome[0x20];
4636
4637         u8         reserved_1[0xa0];
4638
4639         u8         start_flow_index[0x20];
4640
4641         u8         reserved_2[0x20];
4642
4643         u8         end_flow_index[0x20];
4644
4645         u8         reserved_3[0xa0];
4646
4647         u8         reserved_4[0x18];
4648         u8         match_criteria_enable[0x8];
4649
4650         struct mlx5_ifc_fte_match_param_bits match_criteria;
4651
4652         u8         reserved_5[0xe00];
4653 };
4654
4655 struct mlx5_ifc_query_flow_group_in_bits {
4656         u8         opcode[0x10];
4657         u8         reserved_0[0x10];
4658
4659         u8         reserved_1[0x10];
4660         u8         op_mod[0x10];
4661
4662         u8         other_vport[0x1];
4663         u8         reserved_2[0xf];
4664         u8         vport_number[0x10];
4665
4666         u8         reserved_3[0x20];
4667
4668         u8         table_type[0x8];
4669         u8         reserved_4[0x18];
4670
4671         u8         reserved_5[0x8];
4672         u8         table_id[0x18];
4673
4674         u8         group_id[0x20];
4675
4676         u8         reserved_6[0x120];
4677 };
4678
4679 struct mlx5_ifc_query_flow_counter_out_bits {
4680         u8         status[0x8];
4681         u8         reserved_at_8[0x18];
4682
4683         u8         syndrome[0x20];
4684
4685         u8         reserved_at_40[0x40];
4686
4687         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4688 };
4689
4690 struct mlx5_ifc_query_flow_counter_in_bits {
4691         u8         opcode[0x10];
4692         u8         reserved_at_10[0x10];
4693
4694         u8         reserved_at_20[0x10];
4695         u8         op_mod[0x10];
4696
4697         u8         reserved_at_40[0x80];
4698
4699         u8         clear[0x1];
4700         u8         reserved_at_c1[0xf];
4701         u8         num_of_counters[0x10];
4702
4703         u8         reserved_at_e0[0x10];
4704         u8         flow_counter_id[0x10];
4705 };
4706
4707 struct mlx5_ifc_query_esw_vport_context_out_bits {
4708         u8         status[0x8];
4709         u8         reserved_0[0x18];
4710
4711         u8         syndrome[0x20];
4712
4713         u8         reserved_1[0x40];
4714
4715         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4716 };
4717
4718 struct mlx5_ifc_query_esw_vport_context_in_bits {
4719         u8         opcode[0x10];
4720         u8         reserved_0[0x10];
4721
4722         u8         reserved_1[0x10];
4723         u8         op_mod[0x10];
4724
4725         u8         other_vport[0x1];
4726         u8         reserved_2[0xf];
4727         u8         vport_number[0x10];
4728
4729         u8         reserved_3[0x20];
4730 };
4731
4732 struct mlx5_ifc_query_eq_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_0[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_1[0x40];
4739
4740         struct mlx5_ifc_eqc_bits eq_context_entry;
4741
4742         u8         reserved_2[0x40];
4743
4744         u8         event_bitmask[0x40];
4745
4746         u8         reserved_3[0x580];
4747
4748         u8         pas[0][0x40];
4749 };
4750
4751 struct mlx5_ifc_query_eq_in_bits {
4752         u8         opcode[0x10];
4753         u8         reserved_0[0x10];
4754
4755         u8         reserved_1[0x10];
4756         u8         op_mod[0x10];
4757
4758         u8         reserved_2[0x18];
4759         u8         eq_number[0x8];
4760
4761         u8         reserved_3[0x20];
4762 };
4763
4764 struct mlx5_ifc_query_dct_out_bits {
4765         u8         status[0x8];
4766         u8         reserved_0[0x18];
4767
4768         u8         syndrome[0x20];
4769
4770         u8         reserved_1[0x40];
4771
4772         struct mlx5_ifc_dctc_bits dct_context_entry;
4773
4774         u8         reserved_2[0x180];
4775 };
4776
4777 struct mlx5_ifc_query_dct_in_bits {
4778         u8         opcode[0x10];
4779         u8         reserved_0[0x10];
4780
4781         u8         reserved_1[0x10];
4782         u8         op_mod[0x10];
4783
4784         u8         reserved_2[0x8];
4785         u8         dctn[0x18];
4786
4787         u8         reserved_3[0x20];
4788 };
4789
4790 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4791         u8         status[0x8];
4792         u8         reserved_0[0x18];
4793
4794         u8         syndrome[0x20];
4795
4796         u8         enable[0x1];
4797         u8         reserved_1[0x1f];
4798
4799         u8         reserved_2[0x160];
4800
4801         struct mlx5_ifc_cmd_pas_bits pas;
4802 };
4803
4804 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4805         u8         opcode[0x10];
4806         u8         reserved_0[0x10];
4807
4808         u8         reserved_1[0x10];
4809         u8         op_mod[0x10];
4810
4811         u8         reserved_2[0x40];
4812 };
4813
4814 struct mlx5_ifc_query_cq_out_bits {
4815         u8         status[0x8];
4816         u8         reserved_0[0x18];
4817
4818         u8         syndrome[0x20];
4819
4820         u8         reserved_1[0x40];
4821
4822         struct mlx5_ifc_cqc_bits cq_context;
4823
4824         u8         reserved_2[0x600];
4825
4826         u8         pas[0][0x40];
4827 };
4828
4829 struct mlx5_ifc_query_cq_in_bits {
4830         u8         opcode[0x10];
4831         u8         reserved_0[0x10];
4832
4833         u8         reserved_1[0x10];
4834         u8         op_mod[0x10];
4835
4836         u8         reserved_2[0x8];
4837         u8         cqn[0x18];
4838
4839         u8         reserved_3[0x20];
4840 };
4841
4842 struct mlx5_ifc_query_cong_status_out_bits {
4843         u8         status[0x8];
4844         u8         reserved_0[0x18];
4845
4846         u8         syndrome[0x20];
4847
4848         u8         reserved_1[0x20];
4849
4850         u8         enable[0x1];
4851         u8         tag_enable[0x1];
4852         u8         reserved_2[0x1e];
4853 };
4854
4855 struct mlx5_ifc_query_cong_status_in_bits {
4856         u8         opcode[0x10];
4857         u8         reserved_0[0x10];
4858
4859         u8         reserved_1[0x10];
4860         u8         op_mod[0x10];
4861
4862         u8         reserved_2[0x18];
4863         u8         priority[0x4];
4864         u8         cong_protocol[0x4];
4865
4866         u8         reserved_3[0x20];
4867 };
4868
4869 struct mlx5_ifc_query_cong_statistics_out_bits {
4870         u8         status[0x8];
4871         u8         reserved_0[0x18];
4872
4873         u8         syndrome[0x20];
4874
4875         u8         reserved_1[0x40];
4876
4877         u8         rp_cur_flows[0x20];
4878
4879         u8         sum_flows[0x20];
4880
4881         u8         rp_cnp_ignored_high[0x20];
4882
4883         u8         rp_cnp_ignored_low[0x20];
4884
4885         u8         rp_cnp_handled_high[0x20];
4886
4887         u8         rp_cnp_handled_low[0x20];
4888
4889         u8         reserved_2[0x100];
4890
4891         u8         time_stamp_high[0x20];
4892
4893         u8         time_stamp_low[0x20];
4894
4895         u8         accumulators_period[0x20];
4896
4897         u8         np_ecn_marked_roce_packets_high[0x20];
4898
4899         u8         np_ecn_marked_roce_packets_low[0x20];
4900
4901         u8         np_cnp_sent_high[0x20];
4902
4903         u8         np_cnp_sent_low[0x20];
4904
4905         u8         reserved_3[0x560];
4906 };
4907
4908 struct mlx5_ifc_query_cong_statistics_in_bits {
4909         u8         opcode[0x10];
4910         u8         reserved_0[0x10];
4911
4912         u8         reserved_1[0x10];
4913         u8         op_mod[0x10];
4914
4915         u8         clear[0x1];
4916         u8         reserved_2[0x1f];
4917
4918         u8         reserved_3[0x20];
4919 };
4920
4921 struct mlx5_ifc_query_cong_params_out_bits {
4922         u8         status[0x8];
4923         u8         reserved_0[0x18];
4924
4925         u8         syndrome[0x20];
4926
4927         u8         reserved_1[0x40];
4928
4929         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4930 };
4931
4932 struct mlx5_ifc_query_cong_params_in_bits {
4933         u8         opcode[0x10];
4934         u8         reserved_0[0x10];
4935
4936         u8         reserved_1[0x10];
4937         u8         op_mod[0x10];
4938
4939         u8         reserved_2[0x1c];
4940         u8         cong_protocol[0x4];
4941
4942         u8         reserved_3[0x20];
4943 };
4944
4945 struct mlx5_ifc_query_burst_size_out_bits {
4946         u8         status[0x8];
4947         u8         reserved_0[0x18];
4948
4949         u8         syndrome[0x20];
4950
4951         u8         reserved_1[0x20];
4952
4953         u8         reserved_2[0x9];
4954         u8         device_burst_size[0x17];
4955 };
4956
4957 struct mlx5_ifc_query_burst_size_in_bits {
4958         u8         opcode[0x10];
4959         u8         reserved_0[0x10];
4960
4961         u8         reserved_1[0x10];
4962         u8         op_mod[0x10];
4963
4964         u8         reserved_2[0x40];
4965 };
4966
4967 struct mlx5_ifc_query_adapter_out_bits {
4968         u8         status[0x8];
4969         u8         reserved_0[0x18];
4970
4971         u8         syndrome[0x20];
4972
4973         u8         reserved_1[0x40];
4974
4975         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4976 };
4977
4978 struct mlx5_ifc_query_adapter_in_bits {
4979         u8         opcode[0x10];
4980         u8         reserved_0[0x10];
4981
4982         u8         reserved_1[0x10];
4983         u8         op_mod[0x10];
4984
4985         u8         reserved_2[0x40];
4986 };
4987
4988 struct mlx5_ifc_qp_2rst_out_bits {
4989         u8         status[0x8];
4990         u8         reserved_0[0x18];
4991
4992         u8         syndrome[0x20];
4993
4994         u8         reserved_1[0x40];
4995 };
4996
4997 struct mlx5_ifc_qp_2rst_in_bits {
4998         u8         opcode[0x10];
4999         u8         reserved_0[0x10];
5000
5001         u8         reserved_1[0x10];
5002         u8         op_mod[0x10];
5003
5004         u8         reserved_2[0x8];
5005         u8         qpn[0x18];
5006
5007         u8         reserved_3[0x20];
5008 };
5009
5010 struct mlx5_ifc_qp_2err_out_bits {
5011         u8         status[0x8];
5012         u8         reserved_0[0x18];
5013
5014         u8         syndrome[0x20];
5015
5016         u8         reserved_1[0x40];
5017 };
5018
5019 struct mlx5_ifc_qp_2err_in_bits {
5020         u8         opcode[0x10];
5021         u8         reserved_0[0x10];
5022
5023         u8         reserved_1[0x10];
5024         u8         op_mod[0x10];
5025
5026         u8         reserved_2[0x8];
5027         u8         qpn[0x18];
5028
5029         u8         reserved_3[0x20];
5030 };
5031
5032 struct mlx5_ifc_para_vport_element_bits {
5033         u8         reserved_at_0[0xc];
5034         u8         traffic_class[0x4];
5035         u8         qos_para_vport_number[0x10];
5036 };
5037
5038 struct mlx5_ifc_page_fault_resume_out_bits {
5039         u8         status[0x8];
5040         u8         reserved_0[0x18];
5041
5042         u8         syndrome[0x20];
5043
5044         u8         reserved_1[0x40];
5045 };
5046
5047 struct mlx5_ifc_page_fault_resume_in_bits {
5048         u8         opcode[0x10];
5049         u8         reserved_0[0x10];
5050
5051         u8         reserved_1[0x10];
5052         u8         op_mod[0x10];
5053
5054         u8         error[0x1];
5055         u8         reserved_2[0x4];
5056         u8         rdma[0x1];
5057         u8         read_write[0x1];
5058         u8         req_res[0x1];
5059         u8         qpn[0x18];
5060
5061         u8         reserved_3[0x20];
5062 };
5063
5064 struct mlx5_ifc_nop_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_0[0x18];
5067
5068         u8         syndrome[0x20];
5069
5070         u8         reserved_1[0x40];
5071 };
5072
5073 struct mlx5_ifc_nop_in_bits {
5074         u8         opcode[0x10];
5075         u8         reserved_0[0x10];
5076
5077         u8         reserved_1[0x10];
5078         u8         op_mod[0x10];
5079
5080         u8         reserved_2[0x40];
5081 };
5082
5083 struct mlx5_ifc_modify_vport_state_out_bits {
5084         u8         status[0x8];
5085         u8         reserved_0[0x18];
5086
5087         u8         syndrome[0x20];
5088
5089         u8         reserved_1[0x40];
5090 };
5091
5092 enum {
5093         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5094         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5095         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5096 };
5097
5098 enum {
5099         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5100         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5101         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5102 };
5103
5104 struct mlx5_ifc_modify_vport_state_in_bits {
5105         u8         opcode[0x10];
5106         u8         reserved_0[0x10];
5107
5108         u8         reserved_1[0x10];
5109         u8         op_mod[0x10];
5110
5111         u8         other_vport[0x1];
5112         u8         reserved_2[0xf];
5113         u8         vport_number[0x10];
5114
5115         u8         reserved_3[0x18];
5116         u8         admin_state[0x4];
5117         u8         reserved_4[0x4];
5118 };
5119
5120 struct mlx5_ifc_modify_tis_out_bits {
5121         u8         status[0x8];
5122         u8         reserved_0[0x18];
5123
5124         u8         syndrome[0x20];
5125
5126         u8         reserved_1[0x40];
5127 };
5128
5129 struct mlx5_ifc_modify_tis_bitmask_bits {
5130         u8         reserved_at_0[0x20];
5131
5132         u8         reserved_at_20[0x1d];
5133         u8         lag_tx_port_affinity[0x1];
5134         u8         strict_lag_tx_port_affinity[0x1];
5135         u8         prio[0x1];
5136 };
5137
5138 struct mlx5_ifc_modify_tis_in_bits {
5139         u8         opcode[0x10];
5140         u8         reserved_0[0x10];
5141
5142         u8         reserved_1[0x10];
5143         u8         op_mod[0x10];
5144
5145         u8         reserved_2[0x8];
5146         u8         tisn[0x18];
5147
5148         u8         reserved_3[0x20];
5149
5150         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5151
5152         u8         reserved_4[0x40];
5153
5154         struct mlx5_ifc_tisc_bits ctx;
5155 };
5156
5157 struct mlx5_ifc_modify_tir_out_bits {
5158         u8         status[0x8];
5159         u8         reserved_0[0x18];
5160
5161         u8         syndrome[0x20];
5162
5163         u8         reserved_1[0x40];
5164 };
5165
5166 enum
5167 {
5168         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5169         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5170 };
5171
5172 struct mlx5_ifc_modify_tir_in_bits {
5173         u8         opcode[0x10];
5174         u8         reserved_0[0x10];
5175
5176         u8         reserved_1[0x10];
5177         u8         op_mod[0x10];
5178
5179         u8         reserved_2[0x8];
5180         u8         tirn[0x18];
5181
5182         u8         reserved_3[0x20];
5183
5184         u8         modify_bitmask[0x40];
5185
5186         u8         reserved_4[0x40];
5187
5188         struct mlx5_ifc_tirc_bits tir_context;
5189 };
5190
5191 struct mlx5_ifc_modify_sq_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_0[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_1[0x40];
5198 };
5199
5200 struct mlx5_ifc_modify_sq_in_bits {
5201         u8         opcode[0x10];
5202         u8         reserved_0[0x10];
5203
5204         u8         reserved_1[0x10];
5205         u8         op_mod[0x10];
5206
5207         u8         sq_state[0x4];
5208         u8         reserved_2[0x4];
5209         u8         sqn[0x18];
5210
5211         u8         reserved_3[0x20];
5212
5213         u8         modify_bitmask[0x40];
5214
5215         u8         reserved_4[0x40];
5216
5217         struct mlx5_ifc_sqc_bits ctx;
5218 };
5219
5220 struct mlx5_ifc_modify_scheduling_element_out_bits {
5221         u8         status[0x8];
5222         u8         reserved_at_8[0x18];
5223
5224         u8         syndrome[0x20];
5225
5226         u8         reserved_at_40[0x1c0];
5227 };
5228
5229 enum {
5230         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5231 };
5232
5233 enum {
5234         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5235         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5236 };
5237
5238 struct mlx5_ifc_modify_scheduling_element_in_bits {
5239         u8         opcode[0x10];
5240         u8         reserved_at_10[0x10];
5241
5242         u8         reserved_at_20[0x10];
5243         u8         op_mod[0x10];
5244
5245         u8         scheduling_hierarchy[0x8];
5246         u8         reserved_at_48[0x18];
5247
5248         u8         scheduling_element_id[0x20];
5249
5250         u8         reserved_at_80[0x20];
5251
5252         u8         modify_bitmask[0x20];
5253
5254         u8         reserved_at_c0[0x40];
5255
5256         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5257
5258         u8         reserved_at_300[0x100];
5259 };
5260
5261 struct mlx5_ifc_modify_rqt_out_bits {
5262         u8         status[0x8];
5263         u8         reserved_0[0x18];
5264
5265         u8         syndrome[0x20];
5266
5267         u8         reserved_1[0x40];
5268 };
5269
5270 struct mlx5_ifc_modify_rqt_in_bits {
5271         u8         opcode[0x10];
5272         u8         reserved_0[0x10];
5273
5274         u8         reserved_1[0x10];
5275         u8         op_mod[0x10];
5276
5277         u8         reserved_2[0x8];
5278         u8         rqtn[0x18];
5279
5280         u8         reserved_3[0x20];
5281
5282         u8         modify_bitmask[0x40];
5283
5284         u8         reserved_4[0x40];
5285
5286         struct mlx5_ifc_rqtc_bits ctx;
5287 };
5288
5289 struct mlx5_ifc_modify_rq_out_bits {
5290         u8         status[0x8];
5291         u8         reserved_0[0x18];
5292
5293         u8         syndrome[0x20];
5294
5295         u8         reserved_1[0x40];
5296 };
5297
5298 enum {
5299         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5300         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5301 };
5302
5303 struct mlx5_ifc_modify_rq_in_bits {
5304         u8         opcode[0x10];
5305         u8         reserved_0[0x10];
5306
5307         u8         reserved_1[0x10];
5308         u8         op_mod[0x10];
5309
5310         u8         rq_state[0x4];
5311         u8         reserved_2[0x4];
5312         u8         rqn[0x18];
5313
5314         u8         reserved_3[0x20];
5315
5316         u8         modify_bitmask[0x40];
5317
5318         u8         reserved_4[0x40];
5319
5320         struct mlx5_ifc_rqc_bits ctx;
5321 };
5322
5323 struct mlx5_ifc_modify_rmp_out_bits {
5324         u8         status[0x8];
5325         u8         reserved_0[0x18];
5326
5327         u8         syndrome[0x20];
5328
5329         u8         reserved_1[0x40];
5330 };
5331
5332 struct mlx5_ifc_rmp_bitmask_bits {
5333         u8         reserved[0x20];
5334
5335         u8         reserved1[0x1f];
5336         u8         lwm[0x1];
5337 };
5338
5339 struct mlx5_ifc_modify_rmp_in_bits {
5340         u8         opcode[0x10];
5341         u8         reserved_0[0x10];
5342
5343         u8         reserved_1[0x10];
5344         u8         op_mod[0x10];
5345
5346         u8         rmp_state[0x4];
5347         u8         reserved_2[0x4];
5348         u8         rmpn[0x18];
5349
5350         u8         reserved_3[0x20];
5351
5352         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5353
5354         u8         reserved_4[0x40];
5355
5356         struct mlx5_ifc_rmpc_bits ctx;
5357 };
5358
5359 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5360         u8         status[0x8];
5361         u8         reserved_0[0x18];
5362
5363         u8         syndrome[0x20];
5364
5365         u8         reserved_1[0x40];
5366 };
5367
5368 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5369         u8         reserved_0[0x14];
5370         u8         disable_uc_local_lb[0x1];
5371         u8         disable_mc_local_lb[0x1];
5372         u8         node_guid[0x1];
5373         u8         port_guid[0x1];
5374         u8         min_wqe_inline_mode[0x1];
5375         u8         mtu[0x1];
5376         u8         change_event[0x1];
5377         u8         promisc[0x1];
5378         u8         permanent_address[0x1];
5379         u8         addresses_list[0x1];
5380         u8         roce_en[0x1];
5381         u8         reserved_1[0x1];
5382 };
5383
5384 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5385         u8         opcode[0x10];
5386         u8         reserved_0[0x10];
5387
5388         u8         reserved_1[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         other_vport[0x1];
5392         u8         reserved_2[0xf];
5393         u8         vport_number[0x10];
5394
5395         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5396
5397         u8         reserved_3[0x780];
5398
5399         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5400 };
5401
5402 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5403         u8         status[0x8];
5404         u8         reserved_0[0x18];
5405
5406         u8         syndrome[0x20];
5407
5408         u8         reserved_1[0x40];
5409 };
5410
5411 struct mlx5_ifc_grh_bits {
5412         u8      ip_version[4];
5413         u8      traffic_class[8];
5414         u8      flow_label[20];
5415         u8      payload_length[16];
5416         u8      next_header[8];
5417         u8      hop_limit[8];
5418         u8      sgid[128];
5419         u8      dgid[128];
5420 };
5421
5422 struct mlx5_ifc_bth_bits {
5423         u8      opcode[8];
5424         u8      se[1];
5425         u8      migreq[1];
5426         u8      pad_count[2];
5427         u8      tver[4];
5428         u8      p_key[16];
5429         u8      reserved8[8];
5430         u8      dest_qp[24];
5431         u8      ack_req[1];
5432         u8      reserved7[7];
5433         u8      psn[24];
5434 };
5435
5436 struct mlx5_ifc_aeth_bits {
5437         u8      syndrome[8];
5438         u8      msn[24];
5439 };
5440
5441 struct mlx5_ifc_dceth_bits {
5442         u8      reserved0[8];
5443         u8      session_id[24];
5444         u8      reserved1[8];
5445         u8      dci_dct[24];
5446 };
5447
5448 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5449         u8         opcode[0x10];
5450         u8         reserved_0[0x10];
5451
5452         u8         reserved_1[0x10];
5453         u8         op_mod[0x10];
5454
5455         u8         other_vport[0x1];
5456         u8         reserved_2[0xb];
5457         u8         port_num[0x4];
5458         u8         vport_number[0x10];
5459
5460         u8         reserved_3[0x20];
5461
5462         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5463 };
5464
5465 struct mlx5_ifc_modify_flow_table_out_bits {
5466         u8         status[0x8];
5467         u8         reserved_at_8[0x18];
5468
5469         u8         syndrome[0x20];
5470
5471         u8         reserved_at_40[0x40];
5472 };
5473
5474 enum {
5475         MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5476         MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5477 };
5478
5479 struct mlx5_ifc_modify_flow_table_in_bits {
5480         u8         opcode[0x10];
5481         u8         reserved_at_10[0x10];
5482
5483         u8         reserved_at_20[0x10];
5484         u8         op_mod[0x10];
5485
5486         u8         other_vport[0x1];
5487         u8         reserved_at_41[0xf];
5488         u8         vport_number[0x10];
5489
5490         u8         reserved_at_60[0x10];
5491         u8         modify_field_select[0x10];
5492
5493         u8         table_type[0x8];
5494         u8         reserved_at_88[0x18];
5495
5496         u8         reserved_at_a0[0x8];
5497         u8         table_id[0x18];
5498
5499         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5500 };
5501
5502 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5503         u8         status[0x8];
5504         u8         reserved_0[0x18];
5505
5506         u8         syndrome[0x20];
5507
5508         u8         reserved_1[0x40];
5509 };
5510
5511 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5512         u8         reserved[0x1c];
5513         u8         vport_cvlan_insert[0x1];
5514         u8         vport_svlan_insert[0x1];
5515         u8         vport_cvlan_strip[0x1];
5516         u8         vport_svlan_strip[0x1];
5517 };
5518
5519 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5520         u8         opcode[0x10];
5521         u8         reserved_0[0x10];
5522
5523         u8         reserved_1[0x10];
5524         u8         op_mod[0x10];
5525
5526         u8         other_vport[0x1];
5527         u8         reserved_2[0xf];
5528         u8         vport_number[0x10];
5529
5530         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5531
5532         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5533 };
5534
5535 struct mlx5_ifc_modify_cq_out_bits {
5536         u8         status[0x8];
5537         u8         reserved_0[0x18];
5538
5539         u8         syndrome[0x20];
5540
5541         u8         reserved_1[0x40];
5542 };
5543
5544 enum {
5545         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5546         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5547 };
5548
5549 struct mlx5_ifc_modify_cq_in_bits {
5550         u8         opcode[0x10];
5551         u8         reserved_0[0x10];
5552
5553         u8         reserved_1[0x10];
5554         u8         op_mod[0x10];
5555
5556         u8         reserved_2[0x8];
5557         u8         cqn[0x18];
5558
5559         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5560
5561         struct mlx5_ifc_cqc_bits cq_context;
5562
5563         u8         reserved_3[0x600];
5564
5565         u8         pas[0][0x40];
5566 };
5567
5568 struct mlx5_ifc_modify_cong_status_out_bits {
5569         u8         status[0x8];
5570         u8         reserved_0[0x18];
5571
5572         u8         syndrome[0x20];
5573
5574         u8         reserved_1[0x40];
5575 };
5576
5577 struct mlx5_ifc_modify_cong_status_in_bits {
5578         u8         opcode[0x10];
5579         u8         reserved_0[0x10];
5580
5581         u8         reserved_1[0x10];
5582         u8         op_mod[0x10];
5583
5584         u8         reserved_2[0x18];
5585         u8         priority[0x4];
5586         u8         cong_protocol[0x4];
5587
5588         u8         enable[0x1];
5589         u8         tag_enable[0x1];
5590         u8         reserved_3[0x1e];
5591 };
5592
5593 struct mlx5_ifc_modify_cong_params_out_bits {
5594         u8         status[0x8];
5595         u8         reserved_0[0x18];
5596
5597         u8         syndrome[0x20];
5598
5599         u8         reserved_1[0x40];
5600 };
5601
5602 struct mlx5_ifc_modify_cong_params_in_bits {
5603         u8         opcode[0x10];
5604         u8         reserved_0[0x10];
5605
5606         u8         reserved_1[0x10];
5607         u8         op_mod[0x10];
5608
5609         u8         reserved_2[0x1c];
5610         u8         cong_protocol[0x4];
5611
5612         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5613
5614         u8         reserved_3[0x80];
5615
5616         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5617 };
5618
5619 struct mlx5_ifc_manage_pages_out_bits {
5620         u8         status[0x8];
5621         u8         reserved_0[0x18];
5622
5623         u8         syndrome[0x20];
5624
5625         u8         output_num_entries[0x20];
5626
5627         u8         reserved_1[0x20];
5628
5629         u8         pas[0][0x40];
5630 };
5631
5632 enum {
5633         MLX5_PAGES_CANT_GIVE                            = 0x0,
5634         MLX5_PAGES_GIVE                                 = 0x1,
5635         MLX5_PAGES_TAKE                                 = 0x2,
5636 };
5637
5638 struct mlx5_ifc_manage_pages_in_bits {
5639         u8         opcode[0x10];
5640         u8         reserved_0[0x10];
5641
5642         u8         reserved_1[0x10];
5643         u8         op_mod[0x10];
5644
5645         u8         reserved_2[0x10];
5646         u8         function_id[0x10];
5647
5648         u8         input_num_entries[0x20];
5649
5650         u8         pas[0][0x40];
5651 };
5652
5653 struct mlx5_ifc_mad_ifc_out_bits {
5654         u8         status[0x8];
5655         u8         reserved_0[0x18];
5656
5657         u8         syndrome[0x20];
5658
5659         u8         reserved_1[0x40];
5660
5661         u8         response_mad_packet[256][0x8];
5662 };
5663
5664 struct mlx5_ifc_mad_ifc_in_bits {
5665         u8         opcode[0x10];
5666         u8         reserved_0[0x10];
5667
5668         u8         reserved_1[0x10];
5669         u8         op_mod[0x10];
5670
5671         u8         remote_lid[0x10];
5672         u8         reserved_2[0x8];
5673         u8         port[0x8];
5674
5675         u8         reserved_3[0x20];
5676
5677         u8         mad[256][0x8];
5678 };
5679
5680 struct mlx5_ifc_init_hca_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_0[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_1[0x40];
5687 };
5688
5689 enum {
5690         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5691         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5692 };
5693
5694 struct mlx5_ifc_init_hca_in_bits {
5695         u8         opcode[0x10];
5696         u8         reserved_0[0x10];
5697
5698         u8         reserved_1[0x10];
5699         u8         op_mod[0x10];
5700
5701         u8         reserved_2[0x40];
5702 };
5703
5704 struct mlx5_ifc_init2rtr_qp_out_bits {
5705         u8         status[0x8];
5706         u8         reserved_0[0x18];
5707
5708         u8         syndrome[0x20];
5709
5710         u8         reserved_1[0x40];
5711 };
5712
5713 struct mlx5_ifc_init2rtr_qp_in_bits {
5714         u8         opcode[0x10];
5715         u8         reserved_0[0x10];
5716
5717         u8         reserved_1[0x10];
5718         u8         op_mod[0x10];
5719
5720         u8         reserved_2[0x8];
5721         u8         qpn[0x18];
5722
5723         u8         reserved_3[0x20];
5724
5725         u8         opt_param_mask[0x20];
5726
5727         u8         reserved_4[0x20];
5728
5729         struct mlx5_ifc_qpc_bits qpc;
5730
5731         u8         reserved_5[0x80];
5732 };
5733
5734 struct mlx5_ifc_init2init_qp_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_0[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_1[0x40];
5741 };
5742
5743 struct mlx5_ifc_init2init_qp_in_bits {
5744         u8         opcode[0x10];
5745         u8         reserved_0[0x10];
5746
5747         u8         reserved_1[0x10];
5748         u8         op_mod[0x10];
5749
5750         u8         reserved_2[0x8];
5751         u8         qpn[0x18];
5752
5753         u8         reserved_3[0x20];
5754
5755         u8         opt_param_mask[0x20];
5756
5757         u8         reserved_4[0x20];
5758
5759         struct mlx5_ifc_qpc_bits qpc;
5760
5761         u8         reserved_5[0x80];
5762 };
5763
5764 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5765         u8         status[0x8];
5766         u8         reserved_0[0x18];
5767
5768         u8         syndrome[0x20];
5769
5770         u8         reserved_1[0x40];
5771
5772         u8         packet_headers_log[128][0x8];
5773
5774         u8         packet_syndrome[64][0x8];
5775 };
5776
5777 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_0[0x10];
5780
5781         u8         reserved_1[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         reserved_2[0x40];
5785 };
5786
5787 struct mlx5_ifc_gen_eqe_in_bits {
5788         u8         opcode[0x10];
5789         u8         reserved_0[0x10];
5790
5791         u8         reserved_1[0x10];
5792         u8         op_mod[0x10];
5793
5794         u8         reserved_2[0x18];
5795         u8         eq_number[0x8];
5796
5797         u8         reserved_3[0x20];
5798
5799         u8         eqe[64][0x8];
5800 };
5801
5802 struct mlx5_ifc_gen_eq_out_bits {
5803         u8         status[0x8];
5804         u8         reserved_0[0x18];
5805
5806         u8         syndrome[0x20];
5807
5808         u8         reserved_1[0x40];
5809 };
5810
5811 struct mlx5_ifc_enable_hca_out_bits {
5812         u8         status[0x8];
5813         u8         reserved_0[0x18];
5814
5815         u8         syndrome[0x20];
5816
5817         u8         reserved_1[0x20];
5818 };
5819
5820 struct mlx5_ifc_enable_hca_in_bits {
5821         u8         opcode[0x10];
5822         u8         reserved_0[0x10];
5823
5824         u8         reserved_1[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         reserved_2[0x10];
5828         u8         function_id[0x10];
5829
5830         u8         reserved_3[0x20];
5831 };
5832
5833 struct mlx5_ifc_drain_dct_out_bits {
5834         u8         status[0x8];
5835         u8         reserved_0[0x18];
5836
5837         u8         syndrome[0x20];
5838
5839         u8         reserved_1[0x40];
5840 };
5841
5842 struct mlx5_ifc_drain_dct_in_bits {
5843         u8         opcode[0x10];
5844         u8         reserved_0[0x10];
5845
5846         u8         reserved_1[0x10];
5847         u8         op_mod[0x10];
5848
5849         u8         reserved_2[0x8];
5850         u8         dctn[0x18];
5851
5852         u8         reserved_3[0x20];
5853 };
5854
5855 struct mlx5_ifc_disable_hca_out_bits {
5856         u8         status[0x8];
5857         u8         reserved_0[0x18];
5858
5859         u8         syndrome[0x20];
5860
5861         u8         reserved_1[0x20];
5862 };
5863
5864 struct mlx5_ifc_disable_hca_in_bits {
5865         u8         opcode[0x10];
5866         u8         reserved_0[0x10];
5867
5868         u8         reserved_1[0x10];
5869         u8         op_mod[0x10];
5870
5871         u8         reserved_2[0x10];
5872         u8         function_id[0x10];
5873
5874         u8         reserved_3[0x20];
5875 };
5876
5877 struct mlx5_ifc_detach_from_mcg_out_bits {
5878         u8         status[0x8];
5879         u8         reserved_0[0x18];
5880
5881         u8         syndrome[0x20];
5882
5883         u8         reserved_1[0x40];
5884 };
5885
5886 struct mlx5_ifc_detach_from_mcg_in_bits {
5887         u8         opcode[0x10];
5888         u8         reserved_0[0x10];
5889
5890         u8         reserved_1[0x10];
5891         u8         op_mod[0x10];
5892
5893         u8         reserved_2[0x8];
5894         u8         qpn[0x18];
5895
5896         u8         reserved_3[0x20];
5897
5898         u8         multicast_gid[16][0x8];
5899 };
5900
5901 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5902         u8         status[0x8];
5903         u8         reserved_0[0x18];
5904
5905         u8         syndrome[0x20];
5906
5907         u8         reserved_1[0x40];
5908 };
5909
5910 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5911         u8         opcode[0x10];
5912         u8         reserved_0[0x10];
5913
5914         u8         reserved_1[0x10];
5915         u8         op_mod[0x10];
5916
5917         u8         reserved_2[0x8];
5918         u8         xrc_srqn[0x18];
5919
5920         u8         reserved_3[0x20];
5921 };
5922
5923 struct mlx5_ifc_destroy_tis_out_bits {
5924         u8         status[0x8];
5925         u8         reserved_0[0x18];
5926
5927         u8         syndrome[0x20];
5928
5929         u8         reserved_1[0x40];
5930 };
5931
5932 struct mlx5_ifc_destroy_tis_in_bits {
5933         u8         opcode[0x10];
5934         u8         reserved_0[0x10];
5935
5936         u8         reserved_1[0x10];
5937         u8         op_mod[0x10];
5938
5939         u8         reserved_2[0x8];
5940         u8         tisn[0x18];
5941
5942         u8         reserved_3[0x20];
5943 };
5944
5945 struct mlx5_ifc_destroy_tir_out_bits {
5946         u8         status[0x8];
5947         u8         reserved_0[0x18];
5948
5949         u8         syndrome[0x20];
5950
5951         u8         reserved_1[0x40];
5952 };
5953
5954 struct mlx5_ifc_destroy_tir_in_bits {
5955         u8         opcode[0x10];
5956         u8         reserved_0[0x10];
5957
5958         u8         reserved_1[0x10];
5959         u8         op_mod[0x10];
5960
5961         u8         reserved_2[0x8];
5962         u8         tirn[0x18];
5963
5964         u8         reserved_3[0x20];
5965 };
5966
5967 struct mlx5_ifc_destroy_srq_out_bits {
5968         u8         status[0x8];
5969         u8         reserved_0[0x18];
5970
5971         u8         syndrome[0x20];
5972
5973         u8         reserved_1[0x40];
5974 };
5975
5976 struct mlx5_ifc_destroy_srq_in_bits {
5977         u8         opcode[0x10];
5978         u8         reserved_0[0x10];
5979
5980         u8         reserved_1[0x10];
5981         u8         op_mod[0x10];
5982
5983         u8         reserved_2[0x8];
5984         u8         srqn[0x18];
5985
5986         u8         reserved_3[0x20];
5987 };
5988
5989 struct mlx5_ifc_destroy_sq_out_bits {
5990         u8         status[0x8];
5991         u8         reserved_0[0x18];
5992
5993         u8         syndrome[0x20];
5994
5995         u8         reserved_1[0x40];
5996 };
5997
5998 struct mlx5_ifc_destroy_sq_in_bits {
5999         u8         opcode[0x10];
6000         u8         reserved_0[0x10];
6001
6002         u8         reserved_1[0x10];
6003         u8         op_mod[0x10];
6004
6005         u8         reserved_2[0x8];
6006         u8         sqn[0x18];
6007
6008         u8         reserved_3[0x20];
6009 };
6010
6011 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6012         u8         status[0x8];
6013         u8         reserved_at_8[0x18];
6014
6015         u8         syndrome[0x20];
6016
6017         u8         reserved_at_40[0x1c0];
6018 };
6019
6020 enum {
6021         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6022 };
6023
6024 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6025         u8         opcode[0x10];
6026         u8         reserved_at_10[0x10];
6027
6028         u8         reserved_at_20[0x10];
6029         u8         op_mod[0x10];
6030
6031         u8         scheduling_hierarchy[0x8];
6032         u8         reserved_at_48[0x18];
6033
6034         u8         scheduling_element_id[0x20];
6035
6036         u8         reserved_at_80[0x180];
6037 };
6038
6039 struct mlx5_ifc_destroy_rqt_out_bits {
6040         u8         status[0x8];
6041         u8         reserved_0[0x18];
6042
6043         u8         syndrome[0x20];
6044
6045         u8         reserved_1[0x40];
6046 };
6047
6048 struct mlx5_ifc_destroy_rqt_in_bits {
6049         u8         opcode[0x10];
6050         u8         reserved_0[0x10];
6051
6052         u8         reserved_1[0x10];
6053         u8         op_mod[0x10];
6054
6055         u8         reserved_2[0x8];
6056         u8         rqtn[0x18];
6057
6058         u8         reserved_3[0x20];
6059 };
6060
6061 struct mlx5_ifc_destroy_rq_out_bits {
6062         u8         status[0x8];
6063         u8         reserved_0[0x18];
6064
6065         u8         syndrome[0x20];
6066
6067         u8         reserved_1[0x40];
6068 };
6069
6070 struct mlx5_ifc_destroy_rq_in_bits {
6071         u8         opcode[0x10];
6072         u8         reserved_0[0x10];
6073
6074         u8         reserved_1[0x10];
6075         u8         op_mod[0x10];
6076
6077         u8         reserved_2[0x8];
6078         u8         rqn[0x18];
6079
6080         u8         reserved_3[0x20];
6081 };
6082
6083 struct mlx5_ifc_destroy_rmp_out_bits {
6084         u8         status[0x8];
6085         u8         reserved_0[0x18];
6086
6087         u8         syndrome[0x20];
6088
6089         u8         reserved_1[0x40];
6090 };
6091
6092 struct mlx5_ifc_destroy_rmp_in_bits {
6093         u8         opcode[0x10];
6094         u8         reserved_0[0x10];
6095
6096         u8         reserved_1[0x10];
6097         u8         op_mod[0x10];
6098
6099         u8         reserved_2[0x8];
6100         u8         rmpn[0x18];
6101
6102         u8         reserved_3[0x20];
6103 };
6104
6105 struct mlx5_ifc_destroy_qp_out_bits {
6106         u8         status[0x8];
6107         u8         reserved_0[0x18];
6108
6109         u8         syndrome[0x20];
6110
6111         u8         reserved_1[0x40];
6112 };
6113
6114 struct mlx5_ifc_destroy_qp_in_bits {
6115         u8         opcode[0x10];
6116         u8         reserved_0[0x10];
6117
6118         u8         reserved_1[0x10];
6119         u8         op_mod[0x10];
6120
6121         u8         reserved_2[0x8];
6122         u8         qpn[0x18];
6123
6124         u8         reserved_3[0x20];
6125 };
6126
6127 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6128         u8         status[0x8];
6129         u8         reserved_at_8[0x18];
6130
6131         u8         syndrome[0x20];
6132
6133         u8         reserved_at_40[0x1c0];
6134 };
6135
6136 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6137         u8         opcode[0x10];
6138         u8         reserved_at_10[0x10];
6139
6140         u8         reserved_at_20[0x10];
6141         u8         op_mod[0x10];
6142
6143         u8         reserved_at_40[0x20];
6144
6145         u8         reserved_at_60[0x10];
6146         u8         qos_para_vport_number[0x10];
6147
6148         u8         reserved_at_80[0x180];
6149 };
6150
6151 struct mlx5_ifc_destroy_psv_out_bits {
6152         u8         status[0x8];
6153         u8         reserved_0[0x18];
6154
6155         u8         syndrome[0x20];
6156
6157         u8         reserved_1[0x40];
6158 };
6159
6160 struct mlx5_ifc_destroy_psv_in_bits {
6161         u8         opcode[0x10];
6162         u8         reserved_0[0x10];
6163
6164         u8         reserved_1[0x10];
6165         u8         op_mod[0x10];
6166
6167         u8         reserved_2[0x8];
6168         u8         psvn[0x18];
6169
6170         u8         reserved_3[0x20];
6171 };
6172
6173 struct mlx5_ifc_destroy_mkey_out_bits {
6174         u8         status[0x8];
6175         u8         reserved_0[0x18];
6176
6177         u8         syndrome[0x20];
6178
6179         u8         reserved_1[0x40];
6180 };
6181
6182 struct mlx5_ifc_destroy_mkey_in_bits {
6183         u8         opcode[0x10];
6184         u8         reserved_0[0x10];
6185
6186         u8         reserved_1[0x10];
6187         u8         op_mod[0x10];
6188
6189         u8         reserved_2[0x8];
6190         u8         mkey_index[0x18];
6191
6192         u8         reserved_3[0x20];
6193 };
6194
6195 struct mlx5_ifc_destroy_flow_table_out_bits {
6196         u8         status[0x8];
6197         u8         reserved_0[0x18];
6198
6199         u8         syndrome[0x20];
6200
6201         u8         reserved_1[0x40];
6202 };
6203
6204 struct mlx5_ifc_destroy_flow_table_in_bits {
6205         u8         opcode[0x10];
6206         u8         reserved_0[0x10];
6207
6208         u8         reserved_1[0x10];
6209         u8         op_mod[0x10];
6210
6211         u8         other_vport[0x1];
6212         u8         reserved_2[0xf];
6213         u8         vport_number[0x10];
6214
6215         u8         reserved_3[0x20];
6216
6217         u8         table_type[0x8];
6218         u8         reserved_4[0x18];
6219
6220         u8         reserved_5[0x8];
6221         u8         table_id[0x18];
6222
6223         u8         reserved_6[0x140];
6224 };
6225
6226 struct mlx5_ifc_destroy_flow_group_out_bits {
6227         u8         status[0x8];
6228         u8         reserved_0[0x18];
6229
6230         u8         syndrome[0x20];
6231
6232         u8         reserved_1[0x40];
6233 };
6234
6235 struct mlx5_ifc_destroy_flow_group_in_bits {
6236         u8         opcode[0x10];
6237         u8         reserved_0[0x10];
6238
6239         u8         reserved_1[0x10];
6240         u8         op_mod[0x10];
6241
6242         u8         other_vport[0x1];
6243         u8         reserved_2[0xf];
6244         u8         vport_number[0x10];
6245
6246         u8         reserved_3[0x20];
6247
6248         u8         table_type[0x8];
6249         u8         reserved_4[0x18];
6250
6251         u8         reserved_5[0x8];
6252         u8         table_id[0x18];
6253
6254         u8         group_id[0x20];
6255
6256         u8         reserved_6[0x120];
6257 };
6258
6259 struct mlx5_ifc_destroy_eq_out_bits {
6260         u8         status[0x8];
6261         u8         reserved_0[0x18];
6262
6263         u8         syndrome[0x20];
6264
6265         u8         reserved_1[0x40];
6266 };
6267
6268 struct mlx5_ifc_destroy_eq_in_bits {
6269         u8         opcode[0x10];
6270         u8         reserved_0[0x10];
6271
6272         u8         reserved_1[0x10];
6273         u8         op_mod[0x10];
6274
6275         u8         reserved_2[0x18];
6276         u8         eq_number[0x8];
6277
6278         u8         reserved_3[0x20];
6279 };
6280
6281 struct mlx5_ifc_destroy_dct_out_bits {
6282         u8         status[0x8];
6283         u8         reserved_0[0x18];
6284
6285         u8         syndrome[0x20];
6286
6287         u8         reserved_1[0x40];
6288 };
6289
6290 struct mlx5_ifc_destroy_dct_in_bits {
6291         u8         opcode[0x10];
6292         u8         reserved_0[0x10];
6293
6294         u8         reserved_1[0x10];
6295         u8         op_mod[0x10];
6296
6297         u8         reserved_2[0x8];
6298         u8         dctn[0x18];
6299
6300         u8         reserved_3[0x20];
6301 };
6302
6303 struct mlx5_ifc_destroy_cq_out_bits {
6304         u8         status[0x8];
6305         u8         reserved_0[0x18];
6306
6307         u8         syndrome[0x20];
6308
6309         u8         reserved_1[0x40];
6310 };
6311
6312 struct mlx5_ifc_destroy_cq_in_bits {
6313         u8         opcode[0x10];
6314         u8         reserved_0[0x10];
6315
6316         u8         reserved_1[0x10];
6317         u8         op_mod[0x10];
6318
6319         u8         reserved_2[0x8];
6320         u8         cqn[0x18];
6321
6322         u8         reserved_3[0x20];
6323 };
6324
6325 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6326         u8         status[0x8];
6327         u8         reserved_0[0x18];
6328
6329         u8         syndrome[0x20];
6330
6331         u8         reserved_1[0x40];
6332 };
6333
6334 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6335         u8         opcode[0x10];
6336         u8         reserved_0[0x10];
6337
6338         u8         reserved_1[0x10];
6339         u8         op_mod[0x10];
6340
6341         u8         reserved_2[0x20];
6342
6343         u8         reserved_3[0x10];
6344         u8         vxlan_udp_port[0x10];
6345 };
6346
6347 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6348         u8         status[0x8];
6349         u8         reserved_0[0x18];
6350
6351         u8         syndrome[0x20];
6352
6353         u8         reserved_1[0x40];
6354 };
6355
6356 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6357         u8         opcode[0x10];
6358         u8         reserved_0[0x10];
6359
6360         u8         reserved_1[0x10];
6361         u8         op_mod[0x10];
6362
6363         u8         reserved_2[0x60];
6364
6365         u8         reserved_3[0x8];
6366         u8         table_index[0x18];
6367
6368         u8         reserved_4[0x140];
6369 };
6370
6371 struct mlx5_ifc_delete_fte_out_bits {
6372         u8         status[0x8];
6373         u8         reserved_0[0x18];
6374
6375         u8         syndrome[0x20];
6376
6377         u8         reserved_1[0x40];
6378 };
6379
6380 struct mlx5_ifc_delete_fte_in_bits {
6381         u8         opcode[0x10];
6382         u8         reserved_0[0x10];
6383
6384         u8         reserved_1[0x10];
6385         u8         op_mod[0x10];
6386
6387         u8         other_vport[0x1];
6388         u8         reserved_2[0xf];
6389         u8         vport_number[0x10];
6390
6391         u8         reserved_3[0x20];
6392
6393         u8         table_type[0x8];
6394         u8         reserved_4[0x18];
6395
6396         u8         reserved_5[0x8];
6397         u8         table_id[0x18];
6398
6399         u8         reserved_6[0x40];
6400
6401         u8         flow_index[0x20];
6402
6403         u8         reserved_7[0xe0];
6404 };
6405
6406 struct mlx5_ifc_dealloc_xrcd_out_bits {
6407         u8         status[0x8];
6408         u8         reserved_0[0x18];
6409
6410         u8         syndrome[0x20];
6411
6412         u8         reserved_1[0x40];
6413 };
6414
6415 struct mlx5_ifc_dealloc_xrcd_in_bits {
6416         u8         opcode[0x10];
6417         u8         reserved_0[0x10];
6418
6419         u8         reserved_1[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_2[0x8];
6423         u8         xrcd[0x18];
6424
6425         u8         reserved_3[0x20];
6426 };
6427
6428 struct mlx5_ifc_dealloc_uar_out_bits {
6429         u8         status[0x8];
6430         u8         reserved_0[0x18];
6431
6432         u8         syndrome[0x20];
6433
6434         u8         reserved_1[0x40];
6435 };
6436
6437 struct mlx5_ifc_dealloc_uar_in_bits {
6438         u8         opcode[0x10];
6439         u8         reserved_0[0x10];
6440
6441         u8         reserved_1[0x10];
6442         u8         op_mod[0x10];
6443
6444         u8         reserved_2[0x8];
6445         u8         uar[0x18];
6446
6447         u8         reserved_3[0x20];
6448 };
6449
6450 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6451         u8         status[0x8];
6452         u8         reserved_0[0x18];
6453
6454         u8         syndrome[0x20];
6455
6456         u8         reserved_1[0x40];
6457 };
6458
6459 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6460         u8         opcode[0x10];
6461         u8         reserved_0[0x10];
6462
6463         u8         reserved_1[0x10];
6464         u8         op_mod[0x10];
6465
6466         u8         reserved_2[0x8];
6467         u8         transport_domain[0x18];
6468
6469         u8         reserved_3[0x20];
6470 };
6471
6472 struct mlx5_ifc_dealloc_q_counter_out_bits {
6473         u8         status[0x8];
6474         u8         reserved_0[0x18];
6475
6476         u8         syndrome[0x20];
6477
6478         u8         reserved_1[0x40];
6479 };
6480
6481 struct mlx5_ifc_counter_id_bits {
6482         u8         reserved[0x10];
6483         u8         counter_id[0x10];
6484 };
6485
6486 struct mlx5_ifc_diagnostic_params_context_bits {
6487         u8         num_of_counters[0x10];
6488         u8         reserved_2[0x8];
6489         u8         log_num_of_samples[0x8];
6490
6491         u8         single[0x1];
6492         u8         repetitive[0x1];
6493         u8         sync[0x1];
6494         u8         clear[0x1];
6495         u8         on_demand[0x1];
6496         u8         enable[0x1];
6497         u8         reserved_3[0x12];
6498         u8         log_sample_period[0x8];
6499
6500         u8         reserved_4[0x80];
6501
6502         struct mlx5_ifc_counter_id_bits counter_id[0];
6503 };
6504
6505 struct mlx5_ifc_set_diagnostic_params_in_bits {
6506         u8         opcode[0x10];
6507         u8         reserved_0[0x10];
6508
6509         u8         reserved_1[0x10];
6510         u8         op_mod[0x10];
6511
6512         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6513 };
6514
6515 struct mlx5_ifc_set_diagnostic_params_out_bits {
6516         u8         status[0x8];
6517         u8         reserved_0[0x18];
6518
6519         u8         syndrome[0x20];
6520
6521         u8         reserved_1[0x40];
6522 };
6523
6524 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6525         u8         opcode[0x10];
6526         u8         reserved_0[0x10];
6527
6528         u8         reserved_1[0x10];
6529         u8         op_mod[0x10];
6530
6531         u8         num_of_samples[0x10];
6532         u8         sample_index[0x10];
6533
6534         u8         reserved_2[0x20];
6535 };
6536
6537 struct mlx5_ifc_diagnostic_counter_bits {
6538         u8         counter_id[0x10];
6539         u8         sample_id[0x10];
6540
6541         u8         time_stamp_31_0[0x20];
6542
6543         u8         counter_value_h[0x20];
6544
6545         u8         counter_value_l[0x20];
6546 };
6547
6548 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_0[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_1[0x40];
6555
6556         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6557 };
6558
6559 struct mlx5_ifc_dealloc_q_counter_in_bits {
6560         u8         opcode[0x10];
6561         u8         reserved_0[0x10];
6562
6563         u8         reserved_1[0x10];
6564         u8         op_mod[0x10];
6565
6566         u8         reserved_2[0x18];
6567         u8         counter_set_id[0x8];
6568
6569         u8         reserved_3[0x20];
6570 };
6571
6572 struct mlx5_ifc_dealloc_pd_out_bits {
6573         u8         status[0x8];
6574         u8         reserved_0[0x18];
6575
6576         u8         syndrome[0x20];
6577
6578         u8         reserved_1[0x40];
6579 };
6580
6581 struct mlx5_ifc_dealloc_pd_in_bits {
6582         u8         opcode[0x10];
6583         u8         reserved_0[0x10];
6584
6585         u8         reserved_1[0x10];
6586         u8         op_mod[0x10];
6587
6588         u8         reserved_2[0x8];
6589         u8         pd[0x18];
6590
6591         u8         reserved_3[0x20];
6592 };
6593
6594 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6595         u8         status[0x8];
6596         u8         reserved_0[0x18];
6597
6598         u8         syndrome[0x20];
6599
6600         u8         reserved_1[0x40];
6601 };
6602
6603 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6604         u8         opcode[0x10];
6605         u8         reserved_0[0x10];
6606
6607         u8         reserved_1[0x10];
6608         u8         op_mod[0x10];
6609
6610         u8         reserved_2[0x10];
6611         u8         flow_counter_id[0x10];
6612
6613         u8         reserved_3[0x20];
6614 };
6615
6616 struct mlx5_ifc_deactivate_tracer_out_bits {
6617         u8         status[0x8];
6618         u8         reserved_0[0x18];
6619
6620         u8         syndrome[0x20];
6621
6622         u8         reserved_1[0x40];
6623 };
6624
6625 struct mlx5_ifc_deactivate_tracer_in_bits {
6626         u8         opcode[0x10];
6627         u8         reserved_0[0x10];
6628
6629         u8         reserved_1[0x10];
6630         u8         op_mod[0x10];
6631
6632         u8         mkey[0x20];
6633
6634         u8         reserved_2[0x20];
6635 };
6636
6637 struct mlx5_ifc_create_xrc_srq_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_0[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_1[0x8];
6644         u8         xrc_srqn[0x18];
6645
6646         u8         reserved_2[0x20];
6647 };
6648
6649 struct mlx5_ifc_create_xrc_srq_in_bits {
6650         u8         opcode[0x10];
6651         u8         reserved_0[0x10];
6652
6653         u8         reserved_1[0x10];
6654         u8         op_mod[0x10];
6655
6656         u8         reserved_2[0x40];
6657
6658         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6659
6660         u8         reserved_3[0x600];
6661
6662         u8         pas[0][0x40];
6663 };
6664
6665 struct mlx5_ifc_create_tis_out_bits {
6666         u8         status[0x8];
6667         u8         reserved_0[0x18];
6668
6669         u8         syndrome[0x20];
6670
6671         u8         reserved_1[0x8];
6672         u8         tisn[0x18];
6673
6674         u8         reserved_2[0x20];
6675 };
6676
6677 struct mlx5_ifc_create_tis_in_bits {
6678         u8         opcode[0x10];
6679         u8         reserved_0[0x10];
6680
6681         u8         reserved_1[0x10];
6682         u8         op_mod[0x10];
6683
6684         u8         reserved_2[0xc0];
6685
6686         struct mlx5_ifc_tisc_bits ctx;
6687 };
6688
6689 struct mlx5_ifc_create_tir_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_0[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         reserved_1[0x8];
6696         u8         tirn[0x18];
6697
6698         u8         reserved_2[0x20];
6699 };
6700
6701 struct mlx5_ifc_create_tir_in_bits {
6702         u8         opcode[0x10];
6703         u8         reserved_0[0x10];
6704
6705         u8         reserved_1[0x10];
6706         u8         op_mod[0x10];
6707
6708         u8         reserved_2[0xc0];
6709
6710         struct mlx5_ifc_tirc_bits tir_context;
6711 };
6712
6713 struct mlx5_ifc_create_srq_out_bits {
6714         u8         status[0x8];
6715         u8         reserved_0[0x18];
6716
6717         u8         syndrome[0x20];
6718
6719         u8         reserved_1[0x8];
6720         u8         srqn[0x18];
6721
6722         u8         reserved_2[0x20];
6723 };
6724
6725 struct mlx5_ifc_create_srq_in_bits {
6726         u8         opcode[0x10];
6727         u8         reserved_0[0x10];
6728
6729         u8         reserved_1[0x10];
6730         u8         op_mod[0x10];
6731
6732         u8         reserved_2[0x40];
6733
6734         struct mlx5_ifc_srqc_bits srq_context_entry;
6735
6736         u8         reserved_3[0x600];
6737
6738         u8         pas[0][0x40];
6739 };
6740
6741 struct mlx5_ifc_create_sq_out_bits {
6742         u8         status[0x8];
6743         u8         reserved_0[0x18];
6744
6745         u8         syndrome[0x20];
6746
6747         u8         reserved_1[0x8];
6748         u8         sqn[0x18];
6749
6750         u8         reserved_2[0x20];
6751 };
6752
6753 struct mlx5_ifc_create_sq_in_bits {
6754         u8         opcode[0x10];
6755         u8         reserved_0[0x10];
6756
6757         u8         reserved_1[0x10];
6758         u8         op_mod[0x10];
6759
6760         u8         reserved_2[0xc0];
6761
6762         struct mlx5_ifc_sqc_bits ctx;
6763 };
6764
6765 struct mlx5_ifc_create_scheduling_element_out_bits {
6766         u8         status[0x8];
6767         u8         reserved_at_8[0x18];
6768
6769         u8         syndrome[0x20];
6770
6771         u8         reserved_at_40[0x40];
6772
6773         u8         scheduling_element_id[0x20];
6774
6775         u8         reserved_at_a0[0x160];
6776 };
6777
6778 enum {
6779         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6780 };
6781
6782 struct mlx5_ifc_create_scheduling_element_in_bits {
6783         u8         opcode[0x10];
6784         u8         reserved_at_10[0x10];
6785
6786         u8         reserved_at_20[0x10];
6787         u8         op_mod[0x10];
6788
6789         u8         scheduling_hierarchy[0x8];
6790         u8         reserved_at_48[0x18];
6791
6792         u8         reserved_at_60[0xa0];
6793
6794         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6795
6796         u8         reserved_at_300[0x100];
6797 };
6798
6799 struct mlx5_ifc_create_rqt_out_bits {
6800         u8         status[0x8];
6801         u8         reserved_0[0x18];
6802
6803         u8         syndrome[0x20];
6804
6805         u8         reserved_1[0x8];
6806         u8         rqtn[0x18];
6807
6808         u8         reserved_2[0x20];
6809 };
6810
6811 struct mlx5_ifc_create_rqt_in_bits {
6812         u8         opcode[0x10];
6813         u8         reserved_0[0x10];
6814
6815         u8         reserved_1[0x10];
6816         u8         op_mod[0x10];
6817
6818         u8         reserved_2[0xc0];
6819
6820         struct mlx5_ifc_rqtc_bits rqt_context;
6821 };
6822
6823 struct mlx5_ifc_create_rq_out_bits {
6824         u8         status[0x8];
6825         u8         reserved_0[0x18];
6826
6827         u8         syndrome[0x20];
6828
6829         u8         reserved_1[0x8];
6830         u8         rqn[0x18];
6831
6832         u8         reserved_2[0x20];
6833 };
6834
6835 struct mlx5_ifc_create_rq_in_bits {
6836         u8         opcode[0x10];
6837         u8         reserved_0[0x10];
6838
6839         u8         reserved_1[0x10];
6840         u8         op_mod[0x10];
6841
6842         u8         reserved_2[0xc0];
6843
6844         struct mlx5_ifc_rqc_bits ctx;
6845 };
6846
6847 struct mlx5_ifc_create_rmp_out_bits {
6848         u8         status[0x8];
6849         u8         reserved_0[0x18];
6850
6851         u8         syndrome[0x20];
6852
6853         u8         reserved_1[0x8];
6854         u8         rmpn[0x18];
6855
6856         u8         reserved_2[0x20];
6857 };
6858
6859 struct mlx5_ifc_create_rmp_in_bits {
6860         u8         opcode[0x10];
6861         u8         reserved_0[0x10];
6862
6863         u8         reserved_1[0x10];
6864         u8         op_mod[0x10];
6865
6866         u8         reserved_2[0xc0];
6867
6868         struct mlx5_ifc_rmpc_bits ctx;
6869 };
6870
6871 struct mlx5_ifc_create_qp_out_bits {
6872         u8         status[0x8];
6873         u8         reserved_0[0x18];
6874
6875         u8         syndrome[0x20];
6876
6877         u8         reserved_1[0x8];
6878         u8         qpn[0x18];
6879
6880         u8         reserved_2[0x20];
6881 };
6882
6883 struct mlx5_ifc_create_qp_in_bits {
6884         u8         opcode[0x10];
6885         u8         reserved_0[0x10];
6886
6887         u8         reserved_1[0x10];
6888         u8         op_mod[0x10];
6889
6890         u8         reserved_2[0x8];
6891         u8         input_qpn[0x18];
6892
6893         u8         reserved_3[0x20];
6894
6895         u8         opt_param_mask[0x20];
6896
6897         u8         reserved_4[0x20];
6898
6899         struct mlx5_ifc_qpc_bits qpc;
6900
6901         u8         reserved_5[0x80];
6902
6903         u8         pas[0][0x40];
6904 };
6905
6906 struct mlx5_ifc_create_qos_para_vport_out_bits {
6907         u8         status[0x8];
6908         u8         reserved_at_8[0x18];
6909
6910         u8         syndrome[0x20];
6911
6912         u8         reserved_at_40[0x20];
6913
6914         u8         reserved_at_60[0x10];
6915         u8         qos_para_vport_number[0x10];
6916
6917         u8         reserved_at_80[0x180];
6918 };
6919
6920 struct mlx5_ifc_create_qos_para_vport_in_bits {
6921         u8         opcode[0x10];
6922         u8         reserved_at_10[0x10];
6923
6924         u8         reserved_at_20[0x10];
6925         u8         op_mod[0x10];
6926
6927         u8         reserved_at_40[0x1c0];
6928 };
6929
6930 struct mlx5_ifc_create_psv_out_bits {
6931         u8         status[0x8];
6932         u8         reserved_0[0x18];
6933
6934         u8         syndrome[0x20];
6935
6936         u8         reserved_1[0x40];
6937
6938         u8         reserved_2[0x8];
6939         u8         psv0_index[0x18];
6940
6941         u8         reserved_3[0x8];
6942         u8         psv1_index[0x18];
6943
6944         u8         reserved_4[0x8];
6945         u8         psv2_index[0x18];
6946
6947         u8         reserved_5[0x8];
6948         u8         psv3_index[0x18];
6949 };
6950
6951 struct mlx5_ifc_create_psv_in_bits {
6952         u8         opcode[0x10];
6953         u8         reserved_0[0x10];
6954
6955         u8         reserved_1[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         num_psv[0x4];
6959         u8         reserved_2[0x4];
6960         u8         pd[0x18];
6961
6962         u8         reserved_3[0x20];
6963 };
6964
6965 struct mlx5_ifc_create_mkey_out_bits {
6966         u8         status[0x8];
6967         u8         reserved_0[0x18];
6968
6969         u8         syndrome[0x20];
6970
6971         u8         reserved_1[0x8];
6972         u8         mkey_index[0x18];
6973
6974         u8         reserved_2[0x20];
6975 };
6976
6977 struct mlx5_ifc_create_mkey_in_bits {
6978         u8         opcode[0x10];
6979         u8         reserved_0[0x10];
6980
6981         u8         reserved_1[0x10];
6982         u8         op_mod[0x10];
6983
6984         u8         reserved_2[0x20];
6985
6986         u8         pg_access[0x1];
6987         u8         reserved_3[0x1f];
6988
6989         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6990
6991         u8         reserved_4[0x80];
6992
6993         u8         translations_octword_actual_size[0x20];
6994
6995         u8         reserved_5[0x560];
6996
6997         u8         klm_pas_mtt[0][0x20];
6998 };
6999
7000 struct mlx5_ifc_create_flow_table_out_bits {
7001         u8         status[0x8];
7002         u8         reserved_0[0x18];
7003
7004         u8         syndrome[0x20];
7005
7006         u8         reserved_1[0x8];
7007         u8         table_id[0x18];
7008
7009         u8         reserved_2[0x20];
7010 };
7011
7012 struct mlx5_ifc_create_flow_table_in_bits {
7013         u8         opcode[0x10];
7014         u8         reserved_at_10[0x10];
7015
7016         u8         reserved_at_20[0x10];
7017         u8         op_mod[0x10];
7018
7019         u8         other_vport[0x1];
7020         u8         reserved_at_41[0xf];
7021         u8         vport_number[0x10];
7022
7023         u8         reserved_at_60[0x20];
7024
7025         u8         table_type[0x8];
7026         u8         reserved_at_88[0x18];
7027
7028         u8         reserved_at_a0[0x20];
7029
7030         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7031 };
7032
7033 struct mlx5_ifc_create_flow_group_out_bits {
7034         u8         status[0x8];
7035         u8         reserved_0[0x18];
7036
7037         u8         syndrome[0x20];
7038
7039         u8         reserved_1[0x8];
7040         u8         group_id[0x18];
7041
7042         u8         reserved_2[0x20];
7043 };
7044
7045 enum {
7046         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7047         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7048         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7049 };
7050
7051 struct mlx5_ifc_create_flow_group_in_bits {
7052         u8         opcode[0x10];
7053         u8         reserved_0[0x10];
7054
7055         u8         reserved_1[0x10];
7056         u8         op_mod[0x10];
7057
7058         u8         other_vport[0x1];
7059         u8         reserved_2[0xf];
7060         u8         vport_number[0x10];
7061
7062         u8         reserved_3[0x20];
7063
7064         u8         table_type[0x8];
7065         u8         reserved_4[0x18];
7066
7067         u8         reserved_5[0x8];
7068         u8         table_id[0x18];
7069
7070         u8         reserved_6[0x20];
7071
7072         u8         start_flow_index[0x20];
7073
7074         u8         reserved_7[0x20];
7075
7076         u8         end_flow_index[0x20];
7077
7078         u8         reserved_8[0xa0];
7079
7080         u8         reserved_9[0x18];
7081         u8         match_criteria_enable[0x8];
7082
7083         struct mlx5_ifc_fte_match_param_bits match_criteria;
7084
7085         u8         reserved_10[0xe00];
7086 };
7087
7088 struct mlx5_ifc_create_eq_out_bits {
7089         u8         status[0x8];
7090         u8         reserved_0[0x18];
7091
7092         u8         syndrome[0x20];
7093
7094         u8         reserved_1[0x18];
7095         u8         eq_number[0x8];
7096
7097         u8         reserved_2[0x20];
7098 };
7099
7100 struct mlx5_ifc_create_eq_in_bits {
7101         u8         opcode[0x10];
7102         u8         reserved_0[0x10];
7103
7104         u8         reserved_1[0x10];
7105         u8         op_mod[0x10];
7106
7107         u8         reserved_2[0x40];
7108
7109         struct mlx5_ifc_eqc_bits eq_context_entry;
7110
7111         u8         reserved_3[0x40];
7112
7113         u8         event_bitmask[0x40];
7114
7115         u8         reserved_4[0x580];
7116
7117         u8         pas[0][0x40];
7118 };
7119
7120 struct mlx5_ifc_create_dct_out_bits {
7121         u8         status[0x8];
7122         u8         reserved_0[0x18];
7123
7124         u8         syndrome[0x20];
7125
7126         u8         reserved_1[0x8];
7127         u8         dctn[0x18];
7128
7129         u8         reserved_2[0x20];
7130 };
7131
7132 struct mlx5_ifc_create_dct_in_bits {
7133         u8         opcode[0x10];
7134         u8         reserved_0[0x10];
7135
7136         u8         reserved_1[0x10];
7137         u8         op_mod[0x10];
7138
7139         u8         reserved_2[0x40];
7140
7141         struct mlx5_ifc_dctc_bits dct_context_entry;
7142
7143         u8         reserved_3[0x180];
7144 };
7145
7146 struct mlx5_ifc_create_cq_out_bits {
7147         u8         status[0x8];
7148         u8         reserved_0[0x18];
7149
7150         u8         syndrome[0x20];
7151
7152         u8         reserved_1[0x8];
7153         u8         cqn[0x18];
7154
7155         u8         reserved_2[0x20];
7156 };
7157
7158 struct mlx5_ifc_create_cq_in_bits {
7159         u8         opcode[0x10];
7160         u8         reserved_0[0x10];
7161
7162         u8         reserved_1[0x10];
7163         u8         op_mod[0x10];
7164
7165         u8         reserved_2[0x40];
7166
7167         struct mlx5_ifc_cqc_bits cq_context;
7168
7169         u8         reserved_3[0x600];
7170
7171         u8         pas[0][0x40];
7172 };
7173
7174 struct mlx5_ifc_config_int_moderation_out_bits {
7175         u8         status[0x8];
7176         u8         reserved_0[0x18];
7177
7178         u8         syndrome[0x20];
7179
7180         u8         reserved_1[0x4];
7181         u8         min_delay[0xc];
7182         u8         int_vector[0x10];
7183
7184         u8         reserved_2[0x20];
7185 };
7186
7187 enum {
7188         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7189         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7190 };
7191
7192 struct mlx5_ifc_config_int_moderation_in_bits {
7193         u8         opcode[0x10];
7194         u8         reserved_0[0x10];
7195
7196         u8         reserved_1[0x10];
7197         u8         op_mod[0x10];
7198
7199         u8         reserved_2[0x4];
7200         u8         min_delay[0xc];
7201         u8         int_vector[0x10];
7202
7203         u8         reserved_3[0x20];
7204 };
7205
7206 struct mlx5_ifc_attach_to_mcg_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_0[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_1[0x40];
7213 };
7214
7215 struct mlx5_ifc_attach_to_mcg_in_bits {
7216         u8         opcode[0x10];
7217         u8         reserved_0[0x10];
7218
7219         u8         reserved_1[0x10];
7220         u8         op_mod[0x10];
7221
7222         u8         reserved_2[0x8];
7223         u8         qpn[0x18];
7224
7225         u8         reserved_3[0x20];
7226
7227         u8         multicast_gid[16][0x8];
7228 };
7229
7230 struct mlx5_ifc_arm_xrc_srq_out_bits {
7231         u8         status[0x8];
7232         u8         reserved_0[0x18];
7233
7234         u8         syndrome[0x20];
7235
7236         u8         reserved_1[0x40];
7237 };
7238
7239 enum {
7240         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7241 };
7242
7243 struct mlx5_ifc_arm_xrc_srq_in_bits {
7244         u8         opcode[0x10];
7245         u8         reserved_0[0x10];
7246
7247         u8         reserved_1[0x10];
7248         u8         op_mod[0x10];
7249
7250         u8         reserved_2[0x8];
7251         u8         xrc_srqn[0x18];
7252
7253         u8         reserved_3[0x10];
7254         u8         lwm[0x10];
7255 };
7256
7257 struct mlx5_ifc_arm_rq_out_bits {
7258         u8         status[0x8];
7259         u8         reserved_0[0x18];
7260
7261         u8         syndrome[0x20];
7262
7263         u8         reserved_1[0x40];
7264 };
7265
7266 enum {
7267         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7268 };
7269
7270 struct mlx5_ifc_arm_rq_in_bits {
7271         u8         opcode[0x10];
7272         u8         reserved_0[0x10];
7273
7274         u8         reserved_1[0x10];
7275         u8         op_mod[0x10];
7276
7277         u8         reserved_2[0x8];
7278         u8         srq_number[0x18];
7279
7280         u8         reserved_3[0x10];
7281         u8         lwm[0x10];
7282 };
7283
7284 struct mlx5_ifc_arm_dct_out_bits {
7285         u8         status[0x8];
7286         u8         reserved_0[0x18];
7287
7288         u8         syndrome[0x20];
7289
7290         u8         reserved_1[0x40];
7291 };
7292
7293 struct mlx5_ifc_arm_dct_in_bits {
7294         u8         opcode[0x10];
7295         u8         reserved_0[0x10];
7296
7297         u8         reserved_1[0x10];
7298         u8         op_mod[0x10];
7299
7300         u8         reserved_2[0x8];
7301         u8         dctn[0x18];
7302
7303         u8         reserved_3[0x20];
7304 };
7305
7306 struct mlx5_ifc_alloc_xrcd_out_bits {
7307         u8         status[0x8];
7308         u8         reserved_0[0x18];
7309
7310         u8         syndrome[0x20];
7311
7312         u8         reserved_1[0x8];
7313         u8         xrcd[0x18];
7314
7315         u8         reserved_2[0x20];
7316 };
7317
7318 struct mlx5_ifc_alloc_xrcd_in_bits {
7319         u8         opcode[0x10];
7320         u8         reserved_0[0x10];
7321
7322         u8         reserved_1[0x10];
7323         u8         op_mod[0x10];
7324
7325         u8         reserved_2[0x40];
7326 };
7327
7328 struct mlx5_ifc_alloc_uar_out_bits {
7329         u8         status[0x8];
7330         u8         reserved_0[0x18];
7331
7332         u8         syndrome[0x20];
7333
7334         u8         reserved_1[0x8];
7335         u8         uar[0x18];
7336
7337         u8         reserved_2[0x20];
7338 };
7339
7340 struct mlx5_ifc_alloc_uar_in_bits {
7341         u8         opcode[0x10];
7342         u8         reserved_0[0x10];
7343
7344         u8         reserved_1[0x10];
7345         u8         op_mod[0x10];
7346
7347         u8         reserved_2[0x40];
7348 };
7349
7350 struct mlx5_ifc_alloc_transport_domain_out_bits {
7351         u8         status[0x8];
7352         u8         reserved_0[0x18];
7353
7354         u8         syndrome[0x20];
7355
7356         u8         reserved_1[0x8];
7357         u8         transport_domain[0x18];
7358
7359         u8         reserved_2[0x20];
7360 };
7361
7362 struct mlx5_ifc_alloc_transport_domain_in_bits {
7363         u8         opcode[0x10];
7364         u8         reserved_0[0x10];
7365
7366         u8         reserved_1[0x10];
7367         u8         op_mod[0x10];
7368
7369         u8         reserved_2[0x40];
7370 };
7371
7372 struct mlx5_ifc_alloc_q_counter_out_bits {
7373         u8         status[0x8];
7374         u8         reserved_0[0x18];
7375
7376         u8         syndrome[0x20];
7377
7378         u8         reserved_1[0x18];
7379         u8         counter_set_id[0x8];
7380
7381         u8         reserved_2[0x20];
7382 };
7383
7384 struct mlx5_ifc_alloc_q_counter_in_bits {
7385         u8         opcode[0x10];
7386         u8         reserved_0[0x10];
7387
7388         u8         reserved_1[0x10];
7389         u8         op_mod[0x10];
7390
7391         u8         reserved_2[0x40];
7392 };
7393
7394 struct mlx5_ifc_alloc_pd_out_bits {
7395         u8         status[0x8];
7396         u8         reserved_0[0x18];
7397
7398         u8         syndrome[0x20];
7399
7400         u8         reserved_1[0x8];
7401         u8         pd[0x18];
7402
7403         u8         reserved_2[0x20];
7404 };
7405
7406 struct mlx5_ifc_alloc_pd_in_bits {
7407         u8         opcode[0x10];
7408         u8         reserved_0[0x10];
7409
7410         u8         reserved_1[0x10];
7411         u8         op_mod[0x10];
7412
7413         u8         reserved_2[0x40];
7414 };
7415
7416 struct mlx5_ifc_alloc_flow_counter_out_bits {
7417         u8         status[0x8];
7418         u8         reserved_0[0x18];
7419
7420         u8         syndrome[0x20];
7421
7422         u8         reserved_1[0x10];
7423         u8         flow_counter_id[0x10];
7424
7425         u8         reserved_2[0x20];
7426 };
7427
7428 struct mlx5_ifc_alloc_flow_counter_in_bits {
7429         u8         opcode[0x10];
7430         u8         reserved_0[0x10];
7431
7432         u8         reserved_1[0x10];
7433         u8         op_mod[0x10];
7434
7435         u8         reserved_2[0x40];
7436 };
7437
7438 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7439         u8         status[0x8];
7440         u8         reserved_0[0x18];
7441
7442         u8         syndrome[0x20];
7443
7444         u8         reserved_1[0x40];
7445 };
7446
7447 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7448         u8         opcode[0x10];
7449         u8         reserved_0[0x10];
7450
7451         u8         reserved_1[0x10];
7452         u8         op_mod[0x10];
7453
7454         u8         reserved_2[0x20];
7455
7456         u8         reserved_3[0x10];
7457         u8         vxlan_udp_port[0x10];
7458 };
7459
7460 struct mlx5_ifc_activate_tracer_out_bits {
7461         u8         status[0x8];
7462         u8         reserved_0[0x18];
7463
7464         u8         syndrome[0x20];
7465
7466         u8         reserved_1[0x40];
7467 };
7468
7469 struct mlx5_ifc_activate_tracer_in_bits {
7470         u8         opcode[0x10];
7471         u8         reserved_0[0x10];
7472
7473         u8         reserved_1[0x10];
7474         u8         op_mod[0x10];
7475
7476         u8         mkey[0x20];
7477
7478         u8         reserved_2[0x20];
7479 };
7480
7481 struct mlx5_ifc_set_rate_limit_out_bits {
7482         u8         status[0x8];
7483         u8         reserved_at_8[0x18];
7484
7485         u8         syndrome[0x20];
7486
7487         u8         reserved_at_40[0x40];
7488 };
7489
7490 struct mlx5_ifc_set_rate_limit_in_bits {
7491         u8         opcode[0x10];
7492         u8         reserved_at_10[0x10];
7493
7494         u8         reserved_at_20[0x10];
7495         u8         op_mod[0x10];
7496
7497         u8         reserved_at_40[0x10];
7498         u8         rate_limit_index[0x10];
7499
7500         u8         reserved_at_60[0x20];
7501
7502         u8         rate_limit[0x20];
7503         u8         burst_upper_bound[0x20];
7504 };
7505
7506 struct mlx5_ifc_access_register_out_bits {
7507         u8         status[0x8];
7508         u8         reserved_0[0x18];
7509
7510         u8         syndrome[0x20];
7511
7512         u8         reserved_1[0x40];
7513
7514         u8         register_data[0][0x20];
7515 };
7516
7517 enum {
7518         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7519         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7520 };
7521
7522 struct mlx5_ifc_access_register_in_bits {
7523         u8         opcode[0x10];
7524         u8         reserved_0[0x10];
7525
7526         u8         reserved_1[0x10];
7527         u8         op_mod[0x10];
7528
7529         u8         reserved_2[0x10];
7530         u8         register_id[0x10];
7531
7532         u8         argument[0x20];
7533
7534         u8         register_data[0][0x20];
7535 };
7536
7537 struct mlx5_ifc_sltp_reg_bits {
7538         u8         status[0x4];
7539         u8         version[0x4];
7540         u8         local_port[0x8];
7541         u8         pnat[0x2];
7542         u8         reserved_0[0x2];
7543         u8         lane[0x4];
7544         u8         reserved_1[0x8];
7545
7546         u8         reserved_2[0x20];
7547
7548         u8         reserved_3[0x7];
7549         u8         polarity[0x1];
7550         u8         ob_tap0[0x8];
7551         u8         ob_tap1[0x8];
7552         u8         ob_tap2[0x8];
7553
7554         u8         reserved_4[0xc];
7555         u8         ob_preemp_mode[0x4];
7556         u8         ob_reg[0x8];
7557         u8         ob_bias[0x8];
7558
7559         u8         reserved_5[0x20];
7560 };
7561
7562 struct mlx5_ifc_slrp_reg_bits {
7563         u8         status[0x4];
7564         u8         version[0x4];
7565         u8         local_port[0x8];
7566         u8         pnat[0x2];
7567         u8         reserved_0[0x2];
7568         u8         lane[0x4];
7569         u8         reserved_1[0x8];
7570
7571         u8         ib_sel[0x2];
7572         u8         reserved_2[0x11];
7573         u8         dp_sel[0x1];
7574         u8         dp90sel[0x4];
7575         u8         mix90phase[0x8];
7576
7577         u8         ffe_tap0[0x8];
7578         u8         ffe_tap1[0x8];
7579         u8         ffe_tap2[0x8];
7580         u8         ffe_tap3[0x8];
7581
7582         u8         ffe_tap4[0x8];
7583         u8         ffe_tap5[0x8];
7584         u8         ffe_tap6[0x8];
7585         u8         ffe_tap7[0x8];
7586
7587         u8         ffe_tap8[0x8];
7588         u8         mixerbias_tap_amp[0x8];
7589         u8         reserved_3[0x7];
7590         u8         ffe_tap_en[0x9];
7591
7592         u8         ffe_tap_offset0[0x8];
7593         u8         ffe_tap_offset1[0x8];
7594         u8         slicer_offset0[0x10];
7595
7596         u8         mixer_offset0[0x10];
7597         u8         mixer_offset1[0x10];
7598
7599         u8         mixerbgn_inp[0x8];
7600         u8         mixerbgn_inn[0x8];
7601         u8         mixerbgn_refp[0x8];
7602         u8         mixerbgn_refn[0x8];
7603
7604         u8         sel_slicer_lctrl_h[0x1];
7605         u8         sel_slicer_lctrl_l[0x1];
7606         u8         reserved_4[0x1];
7607         u8         ref_mixer_vreg[0x5];
7608         u8         slicer_gctrl[0x8];
7609         u8         lctrl_input[0x8];
7610         u8         mixer_offset_cm1[0x8];
7611
7612         u8         common_mode[0x6];
7613         u8         reserved_5[0x1];
7614         u8         mixer_offset_cm0[0x9];
7615         u8         reserved_6[0x7];
7616         u8         slicer_offset_cm[0x9];
7617 };
7618
7619 struct mlx5_ifc_slrg_reg_bits {
7620         u8         status[0x4];
7621         u8         version[0x4];
7622         u8         local_port[0x8];
7623         u8         pnat[0x2];
7624         u8         reserved_0[0x2];
7625         u8         lane[0x4];
7626         u8         reserved_1[0x8];
7627
7628         u8         time_to_link_up[0x10];
7629         u8         reserved_2[0xc];
7630         u8         grade_lane_speed[0x4];
7631
7632         u8         grade_version[0x8];
7633         u8         grade[0x18];
7634
7635         u8         reserved_3[0x4];
7636         u8         height_grade_type[0x4];
7637         u8         height_grade[0x18];
7638
7639         u8         height_dz[0x10];
7640         u8         height_dv[0x10];
7641
7642         u8         reserved_4[0x10];
7643         u8         height_sigma[0x10];
7644
7645         u8         reserved_5[0x20];
7646
7647         u8         reserved_6[0x4];
7648         u8         phase_grade_type[0x4];
7649         u8         phase_grade[0x18];
7650
7651         u8         reserved_7[0x8];
7652         u8         phase_eo_pos[0x8];
7653         u8         reserved_8[0x8];
7654         u8         phase_eo_neg[0x8];
7655
7656         u8         ffe_set_tested[0x10];
7657         u8         test_errors_per_lane[0x10];
7658 };
7659
7660 struct mlx5_ifc_pvlc_reg_bits {
7661         u8         reserved_0[0x8];
7662         u8         local_port[0x8];
7663         u8         reserved_1[0x10];
7664
7665         u8         reserved_2[0x1c];
7666         u8         vl_hw_cap[0x4];
7667
7668         u8         reserved_3[0x1c];
7669         u8         vl_admin[0x4];
7670
7671         u8         reserved_4[0x1c];
7672         u8         vl_operational[0x4];
7673 };
7674
7675 struct mlx5_ifc_pude_reg_bits {
7676         u8         swid[0x8];
7677         u8         local_port[0x8];
7678         u8         reserved_0[0x4];
7679         u8         admin_status[0x4];
7680         u8         reserved_1[0x4];
7681         u8         oper_status[0x4];
7682
7683         u8         reserved_2[0x60];
7684 };
7685
7686 enum {
7687         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7688         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7689 };
7690
7691 struct mlx5_ifc_ptys_reg_bits {
7692         u8         reserved_0[0x1];
7693         u8         an_disable_admin[0x1];
7694         u8         an_disable_cap[0x1];
7695         u8         reserved_1[0x4];
7696         u8         force_tx_aba_param[0x1];
7697         u8         local_port[0x8];
7698         u8         reserved_2[0xd];
7699         u8         proto_mask[0x3];
7700
7701         u8         an_status[0x4];
7702         u8         reserved_3[0xc];
7703         u8         data_rate_oper[0x10];
7704
7705         u8         fc_proto_capability[0x20];
7706
7707         u8         eth_proto_capability[0x20];
7708
7709         u8         ib_link_width_capability[0x10];
7710         u8         ib_proto_capability[0x10];
7711
7712         u8         fc_proto_admin[0x20];
7713
7714         u8         eth_proto_admin[0x20];
7715
7716         u8         ib_link_width_admin[0x10];
7717         u8         ib_proto_admin[0x10];
7718
7719         u8         fc_proto_oper[0x20];
7720
7721         u8         eth_proto_oper[0x20];
7722
7723         u8         ib_link_width_oper[0x10];
7724         u8         ib_proto_oper[0x10];
7725
7726         u8         reserved_4[0x20];
7727
7728         u8         eth_proto_lp_advertise[0x20];
7729
7730         u8         reserved_5[0x60];
7731 };
7732
7733 struct mlx5_ifc_ptas_reg_bits {
7734         u8         reserved_0[0x20];
7735
7736         u8         algorithm_options[0x10];
7737         u8         reserved_1[0x4];
7738         u8         repetitions_mode[0x4];
7739         u8         num_of_repetitions[0x8];
7740
7741         u8         grade_version[0x8];
7742         u8         height_grade_type[0x4];
7743         u8         phase_grade_type[0x4];
7744         u8         height_grade_weight[0x8];
7745         u8         phase_grade_weight[0x8];
7746
7747         u8         gisim_measure_bits[0x10];
7748         u8         adaptive_tap_measure_bits[0x10];
7749
7750         u8         ber_bath_high_error_threshold[0x10];
7751         u8         ber_bath_mid_error_threshold[0x10];
7752
7753         u8         ber_bath_low_error_threshold[0x10];
7754         u8         one_ratio_high_threshold[0x10];
7755
7756         u8         one_ratio_high_mid_threshold[0x10];
7757         u8         one_ratio_low_mid_threshold[0x10];
7758
7759         u8         one_ratio_low_threshold[0x10];
7760         u8         ndeo_error_threshold[0x10];
7761
7762         u8         mixer_offset_step_size[0x10];
7763         u8         reserved_2[0x8];
7764         u8         mix90_phase_for_voltage_bath[0x8];
7765
7766         u8         mixer_offset_start[0x10];
7767         u8         mixer_offset_end[0x10];
7768
7769         u8         reserved_3[0x15];
7770         u8         ber_test_time[0xb];
7771 };
7772
7773 struct mlx5_ifc_pspa_reg_bits {
7774         u8         swid[0x8];
7775         u8         local_port[0x8];
7776         u8         sub_port[0x8];
7777         u8         reserved_0[0x8];
7778
7779         u8         reserved_1[0x20];
7780 };
7781
7782 struct mlx5_ifc_ppsc_reg_bits {
7783         u8         reserved_0[0x8];
7784         u8         local_port[0x8];
7785         u8         reserved_1[0x10];
7786
7787         u8         reserved_2[0x60];
7788
7789         u8         reserved_3[0x1c];
7790         u8         wrps_admin[0x4];
7791
7792         u8         reserved_4[0x1c];
7793         u8         wrps_status[0x4];
7794
7795         u8         up_th_vld[0x1];
7796         u8         down_th_vld[0x1];
7797         u8         reserved_5[0x6];
7798         u8         up_threshold[0x8];
7799         u8         reserved_6[0x8];
7800         u8         down_threshold[0x8];
7801
7802         u8         reserved_7[0x20];
7803
7804         u8         reserved_8[0x1c];
7805         u8         srps_admin[0x4];
7806
7807         u8         reserved_9[0x60];
7808 };
7809
7810 struct mlx5_ifc_pplr_reg_bits {
7811         u8         reserved_0[0x8];
7812         u8         local_port[0x8];
7813         u8         reserved_1[0x10];
7814
7815         u8         reserved_2[0x8];
7816         u8         lb_cap[0x8];
7817         u8         reserved_3[0x8];
7818         u8         lb_en[0x8];
7819 };
7820
7821 struct mlx5_ifc_pplm_reg_bits {
7822         u8         reserved_0[0x8];
7823         u8         local_port[0x8];
7824         u8         reserved_1[0x10];
7825
7826         u8         reserved_2[0x20];
7827
7828         u8         port_profile_mode[0x8];
7829         u8         static_port_profile[0x8];
7830         u8         active_port_profile[0x8];
7831         u8         reserved_3[0x8];
7832
7833         u8         retransmission_active[0x8];
7834         u8         fec_mode_active[0x18];
7835
7836         u8         reserved_4[0x10];
7837         u8         v_100g_fec_override_cap[0x4];
7838         u8         v_50g_fec_override_cap[0x4];
7839         u8         v_25g_fec_override_cap[0x4];
7840         u8         v_10g_40g_fec_override_cap[0x4];
7841
7842         u8         reserved_5[0x10];
7843         u8         v_100g_fec_override_admin[0x4];
7844         u8         v_50g_fec_override_admin[0x4];
7845         u8         v_25g_fec_override_admin[0x4];
7846         u8         v_10g_40g_fec_override_admin[0x4];
7847 };
7848
7849 struct mlx5_ifc_ppll_reg_bits {
7850         u8         num_pll_groups[0x8];
7851         u8         pll_group[0x8];
7852         u8         reserved_0[0x4];
7853         u8         num_plls[0x4];
7854         u8         reserved_1[0x8];
7855
7856         u8         reserved_2[0x1f];
7857         u8         ae[0x1];
7858
7859         u8         pll_status[4][0x40];
7860 };
7861
7862 struct mlx5_ifc_ppad_reg_bits {
7863         u8         reserved_0[0x3];
7864         u8         single_mac[0x1];
7865         u8         reserved_1[0x4];
7866         u8         local_port[0x8];
7867         u8         mac_47_32[0x10];
7868
7869         u8         mac_31_0[0x20];
7870
7871         u8         reserved_2[0x40];
7872 };
7873
7874 struct mlx5_ifc_pmtu_reg_bits {
7875         u8         reserved_0[0x8];
7876         u8         local_port[0x8];
7877         u8         reserved_1[0x10];
7878
7879         u8         max_mtu[0x10];
7880         u8         reserved_2[0x10];
7881
7882         u8         admin_mtu[0x10];
7883         u8         reserved_3[0x10];
7884
7885         u8         oper_mtu[0x10];
7886         u8         reserved_4[0x10];
7887 };
7888
7889 struct mlx5_ifc_pmpr_reg_bits {
7890         u8         reserved_0[0x8];
7891         u8         module[0x8];
7892         u8         reserved_1[0x10];
7893
7894         u8         reserved_2[0x18];
7895         u8         attenuation_5g[0x8];
7896
7897         u8         reserved_3[0x18];
7898         u8         attenuation_7g[0x8];
7899
7900         u8         reserved_4[0x18];
7901         u8         attenuation_12g[0x8];
7902 };
7903
7904 struct mlx5_ifc_pmpe_reg_bits {
7905         u8         reserved_0[0x8];
7906         u8         module[0x8];
7907         u8         reserved_1[0xc];
7908         u8         module_status[0x4];
7909
7910         u8         reserved_2[0x14];
7911         u8         error_type[0x4];
7912         u8         reserved_3[0x8];
7913
7914         u8         reserved_4[0x40];
7915 };
7916
7917 struct mlx5_ifc_pmpc_reg_bits {
7918         u8         module_state_updated[32][0x8];
7919 };
7920
7921 struct mlx5_ifc_pmlpn_reg_bits {
7922         u8         reserved_0[0x4];
7923         u8         mlpn_status[0x4];
7924         u8         local_port[0x8];
7925         u8         reserved_1[0x10];
7926
7927         u8         e[0x1];
7928         u8         reserved_2[0x1f];
7929 };
7930
7931 struct mlx5_ifc_pmlp_reg_bits {
7932         u8         rxtx[0x1];
7933         u8         reserved_0[0x7];
7934         u8         local_port[0x8];
7935         u8         reserved_1[0x8];
7936         u8         width[0x8];
7937
7938         u8         lane0_module_mapping[0x20];
7939
7940         u8         lane1_module_mapping[0x20];
7941
7942         u8         lane2_module_mapping[0x20];
7943
7944         u8         lane3_module_mapping[0x20];
7945
7946         u8         reserved_2[0x160];
7947 };
7948
7949 struct mlx5_ifc_pmaos_reg_bits {
7950         u8         reserved_0[0x8];
7951         u8         module[0x8];
7952         u8         reserved_1[0x4];
7953         u8         admin_status[0x4];
7954         u8         reserved_2[0x4];
7955         u8         oper_status[0x4];
7956
7957         u8         ase[0x1];
7958         u8         ee[0x1];
7959         u8         reserved_3[0x12];
7960         u8         error_type[0x4];
7961         u8         reserved_4[0x6];
7962         u8         e[0x2];
7963
7964         u8         reserved_5[0x40];
7965 };
7966
7967 struct mlx5_ifc_plpc_reg_bits {
7968         u8         reserved_0[0x4];
7969         u8         profile_id[0xc];
7970         u8         reserved_1[0x4];
7971         u8         proto_mask[0x4];
7972         u8         reserved_2[0x8];
7973
7974         u8         reserved_3[0x10];
7975         u8         lane_speed[0x10];
7976
7977         u8         reserved_4[0x17];
7978         u8         lpbf[0x1];
7979         u8         fec_mode_policy[0x8];
7980
7981         u8         retransmission_capability[0x8];
7982         u8         fec_mode_capability[0x18];
7983
7984         u8         retransmission_support_admin[0x8];
7985         u8         fec_mode_support_admin[0x18];
7986
7987         u8         retransmission_request_admin[0x8];
7988         u8         fec_mode_request_admin[0x18];
7989
7990         u8         reserved_5[0x80];
7991 };
7992
7993 struct mlx5_ifc_pll_status_data_bits {
7994         u8         reserved_0[0x1];
7995         u8         lock_cal[0x1];
7996         u8         lock_status[0x2];
7997         u8         reserved_1[0x2];
7998         u8         algo_f_ctrl[0xa];
7999         u8         analog_algo_num_var[0x6];
8000         u8         f_ctrl_measure[0xa];
8001
8002         u8         reserved_2[0x2];
8003         u8         analog_var[0x6];
8004         u8         reserved_3[0x2];
8005         u8         high_var[0x6];
8006         u8         reserved_4[0x2];
8007         u8         low_var[0x6];
8008         u8         reserved_5[0x2];
8009         u8         mid_val[0x6];
8010 };
8011
8012 struct mlx5_ifc_plib_reg_bits {
8013         u8         reserved_0[0x8];
8014         u8         local_port[0x8];
8015         u8         reserved_1[0x8];
8016         u8         ib_port[0x8];
8017
8018         u8         reserved_2[0x60];
8019 };
8020
8021 struct mlx5_ifc_plbf_reg_bits {
8022         u8         reserved_0[0x8];
8023         u8         local_port[0x8];
8024         u8         reserved_1[0xd];
8025         u8         lbf_mode[0x3];
8026
8027         u8         reserved_2[0x20];
8028 };
8029
8030 struct mlx5_ifc_pipg_reg_bits {
8031         u8         reserved_0[0x8];
8032         u8         local_port[0x8];
8033         u8         reserved_1[0x10];
8034
8035         u8         dic[0x1];
8036         u8         reserved_2[0x19];
8037         u8         ipg[0x4];
8038         u8         reserved_3[0x2];
8039 };
8040
8041 struct mlx5_ifc_pifr_reg_bits {
8042         u8         reserved_0[0x8];
8043         u8         local_port[0x8];
8044         u8         reserved_1[0x10];
8045
8046         u8         reserved_2[0xe0];
8047
8048         u8         port_filter[8][0x20];
8049
8050         u8         port_filter_update_en[8][0x20];
8051 };
8052
8053 struct mlx5_ifc_phys_layer_cntrs_bits {
8054         u8         time_since_last_clear_high[0x20];
8055
8056         u8         time_since_last_clear_low[0x20];
8057
8058         u8         symbol_errors_high[0x20];
8059
8060         u8         symbol_errors_low[0x20];
8061
8062         u8         sync_headers_errors_high[0x20];
8063
8064         u8         sync_headers_errors_low[0x20];
8065
8066         u8         edpl_bip_errors_lane0_high[0x20];
8067
8068         u8         edpl_bip_errors_lane0_low[0x20];
8069
8070         u8         edpl_bip_errors_lane1_high[0x20];
8071
8072         u8         edpl_bip_errors_lane1_low[0x20];
8073
8074         u8         edpl_bip_errors_lane2_high[0x20];
8075
8076         u8         edpl_bip_errors_lane2_low[0x20];
8077
8078         u8         edpl_bip_errors_lane3_high[0x20];
8079
8080         u8         edpl_bip_errors_lane3_low[0x20];
8081
8082         u8         fc_fec_corrected_blocks_lane0_high[0x20];
8083
8084         u8         fc_fec_corrected_blocks_lane0_low[0x20];
8085
8086         u8         fc_fec_corrected_blocks_lane1_high[0x20];
8087
8088         u8         fc_fec_corrected_blocks_lane1_low[0x20];
8089
8090         u8         fc_fec_corrected_blocks_lane2_high[0x20];
8091
8092         u8         fc_fec_corrected_blocks_lane2_low[0x20];
8093
8094         u8         fc_fec_corrected_blocks_lane3_high[0x20];
8095
8096         u8         fc_fec_corrected_blocks_lane3_low[0x20];
8097
8098         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8099
8100         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8101
8102         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8103
8104         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8105
8106         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8107
8108         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8109
8110         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8111
8112         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8113
8114         u8         rs_fec_corrected_blocks_high[0x20];
8115
8116         u8         rs_fec_corrected_blocks_low[0x20];
8117
8118         u8         rs_fec_uncorrectable_blocks_high[0x20];
8119
8120         u8         rs_fec_uncorrectable_blocks_low[0x20];
8121
8122         u8         rs_fec_no_errors_blocks_high[0x20];
8123
8124         u8         rs_fec_no_errors_blocks_low[0x20];
8125
8126         u8         rs_fec_single_error_blocks_high[0x20];
8127
8128         u8         rs_fec_single_error_blocks_low[0x20];
8129
8130         u8         rs_fec_corrected_symbols_total_high[0x20];
8131
8132         u8         rs_fec_corrected_symbols_total_low[0x20];
8133
8134         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8135
8136         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8137
8138         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8139
8140         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8141
8142         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8143
8144         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8145
8146         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8147
8148         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8149
8150         u8         link_down_events[0x20];
8151
8152         u8         successful_recovery_events[0x20];
8153
8154         u8         reserved_0[0x180];
8155 };
8156
8157 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8158         u8         symbol_error_counter[0x10];
8159
8160         u8         link_error_recovery_counter[0x8];
8161
8162         u8         link_downed_counter[0x8];
8163
8164         u8         port_rcv_errors[0x10];
8165
8166         u8         port_rcv_remote_physical_errors[0x10];
8167
8168         u8         port_rcv_switch_relay_errors[0x10];
8169
8170         u8         port_xmit_discards[0x10];
8171
8172         u8         port_xmit_constraint_errors[0x8];
8173
8174         u8         port_rcv_constraint_errors[0x8];
8175
8176         u8         reserved_at_70[0x8];
8177
8178         u8         link_overrun_errors[0x8];
8179
8180         u8         reserved_at_80[0x10];
8181
8182         u8         vl_15_dropped[0x10];
8183
8184         u8         reserved_at_a0[0xa0];
8185 };
8186
8187 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8188         u8         time_since_last_clear_high[0x20];
8189
8190         u8         time_since_last_clear_low[0x20];
8191
8192         u8         phy_received_bits_high[0x20];
8193
8194         u8         phy_received_bits_low[0x20];
8195
8196         u8         phy_symbol_errors_high[0x20];
8197
8198         u8         phy_symbol_errors_low[0x20];
8199
8200         u8         phy_corrected_bits_high[0x20];
8201
8202         u8         phy_corrected_bits_low[0x20];
8203
8204         u8         phy_corrected_bits_lane0_high[0x20];
8205
8206         u8         phy_corrected_bits_lane0_low[0x20];
8207
8208         u8         phy_corrected_bits_lane1_high[0x20];
8209
8210         u8         phy_corrected_bits_lane1_low[0x20];
8211
8212         u8         phy_corrected_bits_lane2_high[0x20];
8213
8214         u8         phy_corrected_bits_lane2_low[0x20];
8215
8216         u8         phy_corrected_bits_lane3_high[0x20];
8217
8218         u8         phy_corrected_bits_lane3_low[0x20];
8219
8220         u8         reserved_at_200[0x5c0];
8221 };
8222
8223 struct mlx5_ifc_infiniband_port_cntrs_bits {
8224         u8         symbol_error_counter[0x10];
8225         u8         link_error_recovery_counter[0x8];
8226         u8         link_downed_counter[0x8];
8227
8228         u8         port_rcv_errors[0x10];
8229         u8         port_rcv_remote_physical_errors[0x10];
8230
8231         u8         port_rcv_switch_relay_errors[0x10];
8232         u8         port_xmit_discards[0x10];
8233
8234         u8         port_xmit_constraint_errors[0x8];
8235         u8         port_rcv_constraint_errors[0x8];
8236         u8         reserved_0[0x8];
8237         u8         local_link_integrity_errors[0x4];
8238         u8         excessive_buffer_overrun_errors[0x4];
8239
8240         u8         reserved_1[0x10];
8241         u8         vl_15_dropped[0x10];
8242
8243         u8         port_xmit_data[0x20];
8244
8245         u8         port_rcv_data[0x20];
8246
8247         u8         port_xmit_pkts[0x20];
8248
8249         u8         port_rcv_pkts[0x20];
8250
8251         u8         port_xmit_wait[0x20];
8252
8253         u8         reserved_2[0x680];
8254 };
8255
8256 struct mlx5_ifc_phrr_reg_bits {
8257         u8         clr[0x1];
8258         u8         reserved_0[0x7];
8259         u8         local_port[0x8];
8260         u8         reserved_1[0x10];
8261
8262         u8         hist_group[0x8];
8263         u8         reserved_2[0x10];
8264         u8         hist_id[0x8];
8265
8266         u8         reserved_3[0x40];
8267
8268         u8         time_since_last_clear_high[0x20];
8269
8270         u8         time_since_last_clear_low[0x20];
8271
8272         u8         bin[10][0x20];
8273 };
8274
8275 struct mlx5_ifc_phbr_for_prio_reg_bits {
8276         u8         reserved_0[0x18];
8277         u8         prio[0x8];
8278 };
8279
8280 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8281         u8         reserved_0[0x18];
8282         u8         tclass[0x8];
8283 };
8284
8285 struct mlx5_ifc_phbr_binding_reg_bits {
8286         u8         opcode[0x4];
8287         u8         reserved_0[0x4];
8288         u8         local_port[0x8];
8289         u8         pnat[0x2];
8290         u8         reserved_1[0xe];
8291
8292         u8         hist_group[0x8];
8293         u8         reserved_2[0x10];
8294         u8         hist_id[0x8];
8295
8296         u8         reserved_3[0x10];
8297         u8         hist_type[0x10];
8298
8299         u8         hist_parameters[0x20];
8300
8301         u8         hist_min_value[0x20];
8302
8303         u8         hist_max_value[0x20];
8304
8305         u8         sample_time[0x20];
8306 };
8307
8308 enum {
8309         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8310         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8311 };
8312
8313 struct mlx5_ifc_pfcc_reg_bits {
8314         u8         dcbx_operation_type[0x2];
8315         u8         cap_local_admin[0x1];
8316         u8         cap_remote_admin[0x1];
8317         u8         reserved_0[0x4];
8318         u8         local_port[0x8];
8319         u8         pnat[0x2];
8320         u8         reserved_1[0xc];
8321         u8         shl_cap[0x1];
8322         u8         shl_opr[0x1];
8323
8324         u8         ppan[0x4];
8325         u8         reserved_2[0x4];
8326         u8         prio_mask_tx[0x8];
8327         u8         reserved_3[0x8];
8328         u8         prio_mask_rx[0x8];
8329
8330         u8         pptx[0x1];
8331         u8         aptx[0x1];
8332         u8         reserved_4[0x6];
8333         u8         pfctx[0x8];
8334         u8         reserved_5[0x8];
8335         u8         cbftx[0x8];
8336
8337         u8         pprx[0x1];
8338         u8         aprx[0x1];
8339         u8         reserved_6[0x6];
8340         u8         pfcrx[0x8];
8341         u8         reserved_7[0x8];
8342         u8         cbfrx[0x8];
8343
8344         u8         device_stall_minor_watermark[0x10];
8345         u8         device_stall_critical_watermark[0x10];
8346
8347         u8         reserved_8[0x60];
8348 };
8349
8350 struct mlx5_ifc_pelc_reg_bits {
8351         u8         op[0x4];
8352         u8         reserved_0[0x4];
8353         u8         local_port[0x8];
8354         u8         reserved_1[0x10];
8355
8356         u8         op_admin[0x8];
8357         u8         op_capability[0x8];
8358         u8         op_request[0x8];
8359         u8         op_active[0x8];
8360
8361         u8         admin[0x40];
8362
8363         u8         capability[0x40];
8364
8365         u8         request[0x40];
8366
8367         u8         active[0x40];
8368
8369         u8         reserved_2[0x80];
8370 };
8371
8372 struct mlx5_ifc_peir_reg_bits {
8373         u8         reserved_0[0x8];
8374         u8         local_port[0x8];
8375         u8         reserved_1[0x10];
8376
8377         u8         reserved_2[0xc];
8378         u8         error_count[0x4];
8379         u8         reserved_3[0x10];
8380
8381         u8         reserved_4[0xc];
8382         u8         lane[0x4];
8383         u8         reserved_5[0x8];
8384         u8         error_type[0x8];
8385 };
8386
8387 struct mlx5_ifc_qcam_access_reg_cap_mask {
8388         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8389         u8         qpdpm[0x1];
8390         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8391         u8         qdpm[0x1];
8392         u8         qpts[0x1];
8393         u8         qcap[0x1];
8394         u8         qcam_access_reg_cap_mask_0[0x1];
8395 };
8396
8397 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8398         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8399         u8         qpts_trust_both[0x1];
8400 };
8401
8402 struct mlx5_ifc_qcam_reg_bits {
8403         u8         reserved_at_0[0x8];
8404         u8         feature_group[0x8];
8405         u8         reserved_at_10[0x8];
8406         u8         access_reg_group[0x8];
8407         u8         reserved_at_20[0x20];
8408
8409         union {
8410                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8411                 u8  reserved_at_0[0x80];
8412         } qos_access_reg_cap_mask;
8413
8414         u8         reserved_at_c0[0x80];
8415
8416         union {
8417                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8418                 u8  reserved_at_0[0x80];
8419         } qos_feature_cap_mask;
8420
8421         u8         reserved_at_1c0[0x80];
8422 };
8423
8424 struct mlx5_ifc_pcap_reg_bits {
8425         u8         reserved_0[0x8];
8426         u8         local_port[0x8];
8427         u8         reserved_1[0x10];
8428
8429         u8         port_capability_mask[4][0x20];
8430 };
8431
8432 struct mlx5_ifc_pbmc_reg_bits {
8433         u8         reserved_0[0x8];
8434         u8         local_port[0x8];
8435         u8         reserved_1[0x10];
8436
8437         u8         xoff_timer_value[0x10];
8438         u8         xoff_refresh[0x10];
8439
8440         u8         reserved_2[0x10];
8441         u8         port_buffer_size[0x10];
8442
8443         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8444
8445         u8         reserved_3[0x40];
8446
8447         u8         port_shared_buffer[0x40];
8448 };
8449
8450 struct mlx5_ifc_paos_reg_bits {
8451         u8         swid[0x8];
8452         u8         local_port[0x8];
8453         u8         reserved_0[0x4];
8454         u8         admin_status[0x4];
8455         u8         reserved_1[0x4];
8456         u8         oper_status[0x4];
8457
8458         u8         ase[0x1];
8459         u8         ee[0x1];
8460         u8         reserved_2[0x1c];
8461         u8         e[0x2];
8462
8463         u8         reserved_3[0x40];
8464 };
8465
8466 struct mlx5_ifc_pamp_reg_bits {
8467         u8         reserved_0[0x8];
8468         u8         opamp_group[0x8];
8469         u8         reserved_1[0xc];
8470         u8         opamp_group_type[0x4];
8471
8472         u8         start_index[0x10];
8473         u8         reserved_2[0x4];
8474         u8         num_of_indices[0xc];
8475
8476         u8         index_data[18][0x10];
8477 };
8478
8479 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8480         u8         llr_rx_cells_high[0x20];
8481
8482         u8         llr_rx_cells_low[0x20];
8483
8484         u8         llr_rx_error_high[0x20];
8485
8486         u8         llr_rx_error_low[0x20];
8487
8488         u8         llr_rx_crc_error_high[0x20];
8489
8490         u8         llr_rx_crc_error_low[0x20];
8491
8492         u8         llr_tx_cells_high[0x20];
8493
8494         u8         llr_tx_cells_low[0x20];
8495
8496         u8         llr_tx_ret_cells_high[0x20];
8497
8498         u8         llr_tx_ret_cells_low[0x20];
8499
8500         u8         llr_tx_ret_events_high[0x20];
8501
8502         u8         llr_tx_ret_events_low[0x20];
8503
8504         u8         reserved_0[0x640];
8505 };
8506
8507 struct mlx5_ifc_lane_2_module_mapping_bits {
8508         u8         reserved_0[0x6];
8509         u8         rx_lane[0x2];
8510         u8         reserved_1[0x6];
8511         u8         tx_lane[0x2];
8512         u8         reserved_2[0x8];
8513         u8         module[0x8];
8514 };
8515
8516 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8517         u8         transmit_queue_high[0x20];
8518
8519         u8         transmit_queue_low[0x20];
8520
8521         u8         reserved_0[0x780];
8522 };
8523
8524 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8525         u8         no_buffer_discard_uc_high[0x20];
8526
8527         u8         no_buffer_discard_uc_low[0x20];
8528
8529         u8         wred_discard_high[0x20];
8530
8531         u8         wred_discard_low[0x20];
8532
8533         u8         reserved_0[0x740];
8534 };
8535
8536 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8537         u8         rx_octets_high[0x20];
8538
8539         u8         rx_octets_low[0x20];
8540
8541         u8         reserved_0[0xc0];
8542
8543         u8         rx_frames_high[0x20];
8544
8545         u8         rx_frames_low[0x20];
8546
8547         u8         tx_octets_high[0x20];
8548
8549         u8         tx_octets_low[0x20];
8550
8551         u8         reserved_1[0xc0];
8552
8553         u8         tx_frames_high[0x20];
8554
8555         u8         tx_frames_low[0x20];
8556
8557         u8         rx_pause_high[0x20];
8558
8559         u8         rx_pause_low[0x20];
8560
8561         u8         rx_pause_duration_high[0x20];
8562
8563         u8         rx_pause_duration_low[0x20];
8564
8565         u8         tx_pause_high[0x20];
8566
8567         u8         tx_pause_low[0x20];
8568
8569         u8         tx_pause_duration_high[0x20];
8570
8571         u8         tx_pause_duration_low[0x20];
8572
8573         u8         rx_pause_transition_high[0x20];
8574
8575         u8         rx_pause_transition_low[0x20];
8576
8577         u8         rx_discards_high[0x20];
8578
8579         u8         rx_discards_low[0x20];
8580
8581         u8         device_stall_minor_watermark_cnt_high[0x20];
8582
8583         u8         device_stall_minor_watermark_cnt_low[0x20];
8584
8585         u8         device_stall_critical_watermark_cnt_high[0x20];
8586
8587         u8         device_stall_critical_watermark_cnt_low[0x20];
8588
8589         u8         reserved_2[0x340];
8590 };
8591
8592 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8593         u8         port_transmit_wait_high[0x20];
8594
8595         u8         port_transmit_wait_low[0x20];
8596
8597         u8         ecn_marked_high[0x20];
8598
8599         u8         ecn_marked_low[0x20];
8600
8601         u8         no_buffer_discard_mc_high[0x20];
8602
8603         u8         no_buffer_discard_mc_low[0x20];
8604
8605         u8         reserved_0[0x700];
8606 };
8607
8608 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8609         u8         a_frames_transmitted_ok_high[0x20];
8610
8611         u8         a_frames_transmitted_ok_low[0x20];
8612
8613         u8         a_frames_received_ok_high[0x20];
8614
8615         u8         a_frames_received_ok_low[0x20];
8616
8617         u8         a_frame_check_sequence_errors_high[0x20];
8618
8619         u8         a_frame_check_sequence_errors_low[0x20];
8620
8621         u8         a_alignment_errors_high[0x20];
8622
8623         u8         a_alignment_errors_low[0x20];
8624
8625         u8         a_octets_transmitted_ok_high[0x20];
8626
8627         u8         a_octets_transmitted_ok_low[0x20];
8628
8629         u8         a_octets_received_ok_high[0x20];
8630
8631         u8         a_octets_received_ok_low[0x20];
8632
8633         u8         a_multicast_frames_xmitted_ok_high[0x20];
8634
8635         u8         a_multicast_frames_xmitted_ok_low[0x20];
8636
8637         u8         a_broadcast_frames_xmitted_ok_high[0x20];
8638
8639         u8         a_broadcast_frames_xmitted_ok_low[0x20];
8640
8641         u8         a_multicast_frames_received_ok_high[0x20];
8642
8643         u8         a_multicast_frames_received_ok_low[0x20];
8644
8645         u8         a_broadcast_frames_recieved_ok_high[0x20];
8646
8647         u8         a_broadcast_frames_recieved_ok_low[0x20];
8648
8649         u8         a_in_range_length_errors_high[0x20];
8650
8651         u8         a_in_range_length_errors_low[0x20];
8652
8653         u8         a_out_of_range_length_field_high[0x20];
8654
8655         u8         a_out_of_range_length_field_low[0x20];
8656
8657         u8         a_frame_too_long_errors_high[0x20];
8658
8659         u8         a_frame_too_long_errors_low[0x20];
8660
8661         u8         a_symbol_error_during_carrier_high[0x20];
8662
8663         u8         a_symbol_error_during_carrier_low[0x20];
8664
8665         u8         a_mac_control_frames_transmitted_high[0x20];
8666
8667         u8         a_mac_control_frames_transmitted_low[0x20];
8668
8669         u8         a_mac_control_frames_received_high[0x20];
8670
8671         u8         a_mac_control_frames_received_low[0x20];
8672
8673         u8         a_unsupported_opcodes_received_high[0x20];
8674
8675         u8         a_unsupported_opcodes_received_low[0x20];
8676
8677         u8         a_pause_mac_ctrl_frames_received_high[0x20];
8678
8679         u8         a_pause_mac_ctrl_frames_received_low[0x20];
8680
8681         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8682
8683         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8684
8685         u8         reserved_0[0x300];
8686 };
8687
8688 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8689         u8         dot3stats_alignment_errors_high[0x20];
8690
8691         u8         dot3stats_alignment_errors_low[0x20];
8692
8693         u8         dot3stats_fcs_errors_high[0x20];
8694
8695         u8         dot3stats_fcs_errors_low[0x20];
8696
8697         u8         dot3stats_single_collision_frames_high[0x20];
8698
8699         u8         dot3stats_single_collision_frames_low[0x20];
8700
8701         u8         dot3stats_multiple_collision_frames_high[0x20];
8702
8703         u8         dot3stats_multiple_collision_frames_low[0x20];
8704
8705         u8         dot3stats_sqe_test_errors_high[0x20];
8706
8707         u8         dot3stats_sqe_test_errors_low[0x20];
8708
8709         u8         dot3stats_deferred_transmissions_high[0x20];
8710
8711         u8         dot3stats_deferred_transmissions_low[0x20];
8712
8713         u8         dot3stats_late_collisions_high[0x20];
8714
8715         u8         dot3stats_late_collisions_low[0x20];
8716
8717         u8         dot3stats_excessive_collisions_high[0x20];
8718
8719         u8         dot3stats_excessive_collisions_low[0x20];
8720
8721         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8722
8723         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8724
8725         u8         dot3stats_carrier_sense_errors_high[0x20];
8726
8727         u8         dot3stats_carrier_sense_errors_low[0x20];
8728
8729         u8         dot3stats_frame_too_longs_high[0x20];
8730
8731         u8         dot3stats_frame_too_longs_low[0x20];
8732
8733         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8734
8735         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8736
8737         u8         dot3stats_symbol_errors_high[0x20];
8738
8739         u8         dot3stats_symbol_errors_low[0x20];
8740
8741         u8         dot3control_in_unknown_opcodes_high[0x20];
8742
8743         u8         dot3control_in_unknown_opcodes_low[0x20];
8744
8745         u8         dot3in_pause_frames_high[0x20];
8746
8747         u8         dot3in_pause_frames_low[0x20];
8748
8749         u8         dot3out_pause_frames_high[0x20];
8750
8751         u8         dot3out_pause_frames_low[0x20];
8752
8753         u8         reserved_0[0x3c0];
8754 };
8755
8756 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8757         u8         if_in_octets_high[0x20];
8758
8759         u8         if_in_octets_low[0x20];
8760
8761         u8         if_in_ucast_pkts_high[0x20];
8762
8763         u8         if_in_ucast_pkts_low[0x20];
8764
8765         u8         if_in_discards_high[0x20];
8766
8767         u8         if_in_discards_low[0x20];
8768
8769         u8         if_in_errors_high[0x20];
8770
8771         u8         if_in_errors_low[0x20];
8772
8773         u8         if_in_unknown_protos_high[0x20];
8774
8775         u8         if_in_unknown_protos_low[0x20];
8776
8777         u8         if_out_octets_high[0x20];
8778
8779         u8         if_out_octets_low[0x20];
8780
8781         u8         if_out_ucast_pkts_high[0x20];
8782
8783         u8         if_out_ucast_pkts_low[0x20];
8784
8785         u8         if_out_discards_high[0x20];
8786
8787         u8         if_out_discards_low[0x20];
8788
8789         u8         if_out_errors_high[0x20];
8790
8791         u8         if_out_errors_low[0x20];
8792
8793         u8         if_in_multicast_pkts_high[0x20];
8794
8795         u8         if_in_multicast_pkts_low[0x20];
8796
8797         u8         if_in_broadcast_pkts_high[0x20];
8798
8799         u8         if_in_broadcast_pkts_low[0x20];
8800
8801         u8         if_out_multicast_pkts_high[0x20];
8802
8803         u8         if_out_multicast_pkts_low[0x20];
8804
8805         u8         if_out_broadcast_pkts_high[0x20];
8806
8807         u8         if_out_broadcast_pkts_low[0x20];
8808
8809         u8         reserved_0[0x480];
8810 };
8811
8812 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8813         u8         ether_stats_drop_events_high[0x20];
8814
8815         u8         ether_stats_drop_events_low[0x20];
8816
8817         u8         ether_stats_octets_high[0x20];
8818
8819         u8         ether_stats_octets_low[0x20];
8820
8821         u8         ether_stats_pkts_high[0x20];
8822
8823         u8         ether_stats_pkts_low[0x20];
8824
8825         u8         ether_stats_broadcast_pkts_high[0x20];
8826
8827         u8         ether_stats_broadcast_pkts_low[0x20];
8828
8829         u8         ether_stats_multicast_pkts_high[0x20];
8830
8831         u8         ether_stats_multicast_pkts_low[0x20];
8832
8833         u8         ether_stats_crc_align_errors_high[0x20];
8834
8835         u8         ether_stats_crc_align_errors_low[0x20];
8836
8837         u8         ether_stats_undersize_pkts_high[0x20];
8838
8839         u8         ether_stats_undersize_pkts_low[0x20];
8840
8841         u8         ether_stats_oversize_pkts_high[0x20];
8842
8843         u8         ether_stats_oversize_pkts_low[0x20];
8844
8845         u8         ether_stats_fragments_high[0x20];
8846
8847         u8         ether_stats_fragments_low[0x20];
8848
8849         u8         ether_stats_jabbers_high[0x20];
8850
8851         u8         ether_stats_jabbers_low[0x20];
8852
8853         u8         ether_stats_collisions_high[0x20];
8854
8855         u8         ether_stats_collisions_low[0x20];
8856
8857         u8         ether_stats_pkts64octets_high[0x20];
8858
8859         u8         ether_stats_pkts64octets_low[0x20];
8860
8861         u8         ether_stats_pkts65to127octets_high[0x20];
8862
8863         u8         ether_stats_pkts65to127octets_low[0x20];
8864
8865         u8         ether_stats_pkts128to255octets_high[0x20];
8866
8867         u8         ether_stats_pkts128to255octets_low[0x20];
8868
8869         u8         ether_stats_pkts256to511octets_high[0x20];
8870
8871         u8         ether_stats_pkts256to511octets_low[0x20];
8872
8873         u8         ether_stats_pkts512to1023octets_high[0x20];
8874
8875         u8         ether_stats_pkts512to1023octets_low[0x20];
8876
8877         u8         ether_stats_pkts1024to1518octets_high[0x20];
8878
8879         u8         ether_stats_pkts1024to1518octets_low[0x20];
8880
8881         u8         ether_stats_pkts1519to2047octets_high[0x20];
8882
8883         u8         ether_stats_pkts1519to2047octets_low[0x20];
8884
8885         u8         ether_stats_pkts2048to4095octets_high[0x20];
8886
8887         u8         ether_stats_pkts2048to4095octets_low[0x20];
8888
8889         u8         ether_stats_pkts4096to8191octets_high[0x20];
8890
8891         u8         ether_stats_pkts4096to8191octets_low[0x20];
8892
8893         u8         ether_stats_pkts8192to10239octets_high[0x20];
8894
8895         u8         ether_stats_pkts8192to10239octets_low[0x20];
8896
8897         u8         reserved_0[0x280];
8898 };
8899
8900 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8901         u8         symbol_error_counter[0x10];
8902         u8         link_error_recovery_counter[0x8];
8903         u8         link_downed_counter[0x8];
8904
8905         u8         port_rcv_errors[0x10];
8906         u8         port_rcv_remote_physical_errors[0x10];
8907
8908         u8         port_rcv_switch_relay_errors[0x10];
8909         u8         port_xmit_discards[0x10];
8910
8911         u8         port_xmit_constraint_errors[0x8];
8912         u8         port_rcv_constraint_errors[0x8];
8913         u8         reserved_0[0x8];
8914         u8         local_link_integrity_errors[0x4];
8915         u8         excessive_buffer_overrun_errors[0x4];
8916
8917         u8         reserved_1[0x10];
8918         u8         vl_15_dropped[0x10];
8919
8920         u8         port_xmit_data[0x20];
8921
8922         u8         port_rcv_data[0x20];
8923
8924         u8         port_xmit_pkts[0x20];
8925
8926         u8         port_rcv_pkts[0x20];
8927
8928         u8         port_xmit_wait[0x20];
8929
8930         u8         reserved_2[0x680];
8931 };
8932
8933 struct mlx5_ifc_trc_tlb_reg_bits {
8934         u8         reserved_0[0x80];
8935
8936         u8         tlb_addr[0][0x40];
8937 };
8938
8939 struct mlx5_ifc_trc_read_fifo_reg_bits {
8940         u8         reserved_0[0x10];
8941         u8         requested_event_num[0x10];
8942
8943         u8         reserved_1[0x20];
8944
8945         u8         reserved_2[0x10];
8946         u8         acual_event_num[0x10];
8947
8948         u8         reserved_3[0x20];
8949
8950         u8         event[0][0x40];
8951 };
8952
8953 struct mlx5_ifc_trc_lock_reg_bits {
8954         u8         reserved_0[0x1f];
8955         u8         lock[0x1];
8956
8957         u8         reserved_1[0x60];
8958 };
8959
8960 struct mlx5_ifc_trc_filter_reg_bits {
8961         u8         status[0x1];
8962         u8         reserved_0[0xf];
8963         u8         filter_index[0x10];
8964
8965         u8         reserved_1[0x20];
8966
8967         u8         filter_val[0x20];
8968
8969         u8         reserved_2[0x1a0];
8970 };
8971
8972 struct mlx5_ifc_trc_event_reg_bits {
8973         u8         status[0x1];
8974         u8         reserved_0[0xf];
8975         u8         event_index[0x10];
8976
8977         u8         reserved_1[0x20];
8978
8979         u8         event_id[0x20];
8980
8981         u8         event_selector_val[0x10];
8982         u8         event_selector_size[0x10];
8983
8984         u8         reserved_2[0x180];
8985 };
8986
8987 struct mlx5_ifc_trc_conf_reg_bits {
8988         u8         limit_en[0x1];
8989         u8         reserved_0[0x3];
8990         u8         dump_mode[0x4];
8991         u8         reserved_1[0x15];
8992         u8         state[0x3];
8993
8994         u8         reserved_2[0x20];
8995
8996         u8         limit_event_index[0x20];
8997
8998         u8         mkey[0x20];
8999
9000         u8         fifo_ready_ev_num[0x20];
9001
9002         u8         reserved_3[0x160];
9003 };
9004
9005 struct mlx5_ifc_trc_cap_reg_bits {
9006         u8         reserved_0[0x18];
9007         u8         dump_mode[0x8];
9008
9009         u8         reserved_1[0x20];
9010
9011         u8         num_of_events[0x10];
9012         u8         num_of_filters[0x10];
9013
9014         u8         fifo_size[0x20];
9015
9016         u8         tlb_size[0x10];
9017         u8         event_size[0x10];
9018
9019         u8         reserved_2[0x160];
9020 };
9021
9022 struct mlx5_ifc_set_node_in_bits {
9023         u8         node_description[64][0x8];
9024 };
9025
9026 struct mlx5_ifc_register_power_settings_bits {
9027         u8         reserved_0[0x18];
9028         u8         power_settings_level[0x8];
9029
9030         u8         reserved_1[0x60];
9031 };
9032
9033 struct mlx5_ifc_register_host_endianess_bits {
9034         u8         he[0x1];
9035         u8         reserved_0[0x1f];
9036
9037         u8         reserved_1[0x60];
9038 };
9039
9040 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9041         u8         physical_address[0x40];
9042 };
9043
9044 struct mlx5_ifc_qtct_reg_bits {
9045         u8         operation_type[0x2];
9046         u8         cap_local_admin[0x1];
9047         u8         cap_remote_admin[0x1];
9048         u8         reserved_0[0x4];
9049         u8         port_number[0x8];
9050         u8         reserved_1[0xd];
9051         u8         prio[0x3];
9052
9053         u8         reserved_2[0x1d];
9054         u8         tclass[0x3];
9055 };
9056
9057 struct mlx5_ifc_qpdp_reg_bits {
9058         u8         reserved_0[0x8];
9059         u8         port_number[0x8];
9060         u8         reserved_1[0x10];
9061
9062         u8         reserved_2[0x1d];
9063         u8         pprio[0x3];
9064 };
9065
9066 struct mlx5_ifc_port_info_ro_fields_param_bits {
9067         u8         reserved_0[0x8];
9068         u8         port[0x8];
9069         u8         max_gid[0x10];
9070
9071         u8         reserved_1[0x20];
9072
9073         u8         port_guid[0x40];
9074 };
9075
9076 struct mlx5_ifc_nvqc_reg_bits {
9077         u8         type[0x20];
9078
9079         u8         reserved_0[0x18];
9080         u8         version[0x4];
9081         u8         reserved_1[0x2];
9082         u8         support_wr[0x1];
9083         u8         support_rd[0x1];
9084 };
9085
9086 struct mlx5_ifc_nvia_reg_bits {
9087         u8         reserved_0[0x1d];
9088         u8         target[0x3];
9089
9090         u8         reserved_1[0x20];
9091 };
9092
9093 struct mlx5_ifc_nvdi_reg_bits {
9094         struct mlx5_ifc_config_item_bits configuration_item_header;
9095 };
9096
9097 struct mlx5_ifc_nvda_reg_bits {
9098         struct mlx5_ifc_config_item_bits configuration_item_header;
9099
9100         u8         configuration_item_data[0x20];
9101 };
9102
9103 struct mlx5_ifc_node_info_ro_fields_param_bits {
9104         u8         system_image_guid[0x40];
9105
9106         u8         reserved_0[0x40];
9107
9108         u8         node_guid[0x40];
9109
9110         u8         reserved_1[0x10];
9111         u8         max_pkey[0x10];
9112
9113         u8         reserved_2[0x20];
9114 };
9115
9116 struct mlx5_ifc_ets_tcn_config_reg_bits {
9117         u8         g[0x1];
9118         u8         b[0x1];
9119         u8         r[0x1];
9120         u8         reserved_0[0x9];
9121         u8         group[0x4];
9122         u8         reserved_1[0x9];
9123         u8         bw_allocation[0x7];
9124
9125         u8         reserved_2[0xc];
9126         u8         max_bw_units[0x4];
9127         u8         reserved_3[0x8];
9128         u8         max_bw_value[0x8];
9129 };
9130
9131 struct mlx5_ifc_ets_global_config_reg_bits {
9132         u8         reserved_0[0x2];
9133         u8         r[0x1];
9134         u8         reserved_1[0x1d];
9135
9136         u8         reserved_2[0xc];
9137         u8         max_bw_units[0x4];
9138         u8         reserved_3[0x8];
9139         u8         max_bw_value[0x8];
9140 };
9141
9142 struct mlx5_ifc_qetc_reg_bits {
9143         u8                                         reserved_at_0[0x8];
9144         u8                                         port_number[0x8];
9145         u8                                         reserved_at_10[0x30];
9146
9147         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9148         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9149 };
9150
9151 struct mlx5_ifc_nodnic_mac_filters_bits {
9152         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9153
9154         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9155
9156         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9157
9158         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9159
9160         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9161
9162         u8         reserved_0[0xc0];
9163 };
9164
9165 struct mlx5_ifc_nodnic_gid_filters_bits {
9166         u8         mgid_filter0[16][0x8];
9167
9168         u8         mgid_filter1[16][0x8];
9169
9170         u8         mgid_filter2[16][0x8];
9171
9172         u8         mgid_filter3[16][0x8];
9173 };
9174
9175 enum {
9176         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9177         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9178 };
9179
9180 enum {
9181         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9182         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9183 };
9184
9185 struct mlx5_ifc_nodnic_config_reg_bits {
9186         u8         no_dram_nic_revision[0x8];
9187         u8         hardware_format[0x8];
9188         u8         support_receive_filter[0x1];
9189         u8         support_promisc_filter[0x1];
9190         u8         support_promisc_multicast_filter[0x1];
9191         u8         reserved_0[0x2];
9192         u8         log_working_buffer_size[0x3];
9193         u8         log_pkey_table_size[0x4];
9194         u8         reserved_1[0x3];
9195         u8         num_ports[0x1];
9196
9197         u8         reserved_2[0x2];
9198         u8         log_max_ring_size[0x6];
9199         u8         reserved_3[0x18];
9200
9201         u8         lkey[0x20];
9202
9203         u8         cqe_format[0x4];
9204         u8         reserved_4[0x1c];
9205
9206         u8         node_guid[0x40];
9207
9208         u8         reserved_5[0x740];
9209
9210         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9211
9212         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9213 };
9214
9215 struct mlx5_ifc_vlan_layout_bits {
9216         u8         reserved_0[0x14];
9217         u8         vlan[0xc];
9218
9219         u8         reserved_1[0x20];
9220 };
9221
9222 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9223         u8         reserved_0[0x20];
9224
9225         u8         mkey[0x20];
9226
9227         u8         addressh_63_32[0x20];
9228
9229         u8         addressl_31_0[0x20];
9230 };
9231
9232 struct mlx5_ifc_ud_adrs_vector_bits {
9233         u8         dc_key[0x40];
9234
9235         u8         ext[0x1];
9236         u8         reserved_0[0x7];
9237         u8         destination_qp_dct[0x18];
9238
9239         u8         static_rate[0x4];
9240         u8         sl_eth_prio[0x4];
9241         u8         fl[0x1];
9242         u8         mlid[0x7];
9243         u8         rlid_udp_sport[0x10];
9244
9245         u8         reserved_1[0x20];
9246
9247         u8         rmac_47_16[0x20];
9248
9249         u8         rmac_15_0[0x10];
9250         u8         tclass[0x8];
9251         u8         hop_limit[0x8];
9252
9253         u8         reserved_2[0x1];
9254         u8         grh[0x1];
9255         u8         reserved_3[0x2];
9256         u8         src_addr_index[0x8];
9257         u8         flow_label[0x14];
9258
9259         u8         rgid_rip[16][0x8];
9260 };
9261
9262 struct mlx5_ifc_port_module_event_bits {
9263         u8         reserved_0[0x8];
9264         u8         module[0x8];
9265         u8         reserved_1[0xc];
9266         u8         module_status[0x4];
9267
9268         u8         reserved_2[0x14];
9269         u8         error_type[0x4];
9270         u8         reserved_3[0x8];
9271
9272         u8         reserved_4[0xa0];
9273 };
9274
9275 struct mlx5_ifc_icmd_control_bits {
9276         u8         opcode[0x10];
9277         u8         status[0x8];
9278         u8         reserved_0[0x7];
9279         u8         busy[0x1];
9280 };
9281
9282 struct mlx5_ifc_eqe_bits {
9283         u8         reserved_0[0x8];
9284         u8         event_type[0x8];
9285         u8         reserved_1[0x8];
9286         u8         event_sub_type[0x8];
9287
9288         u8         reserved_2[0xe0];
9289
9290         union mlx5_ifc_event_auto_bits event_data;
9291
9292         u8         reserved_3[0x10];
9293         u8         signature[0x8];
9294         u8         reserved_4[0x7];
9295         u8         owner[0x1];
9296 };
9297
9298 enum {
9299         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9300 };
9301
9302 struct mlx5_ifc_cmd_queue_entry_bits {
9303         u8         type[0x8];
9304         u8         reserved_0[0x18];
9305
9306         u8         input_length[0x20];
9307
9308         u8         input_mailbox_pointer_63_32[0x20];
9309
9310         u8         input_mailbox_pointer_31_9[0x17];
9311         u8         reserved_1[0x9];
9312
9313         u8         command_input_inline_data[16][0x8];
9314
9315         u8         command_output_inline_data[16][0x8];
9316
9317         u8         output_mailbox_pointer_63_32[0x20];
9318
9319         u8         output_mailbox_pointer_31_9[0x17];
9320         u8         reserved_2[0x9];
9321
9322         u8         output_length[0x20];
9323
9324         u8         token[0x8];
9325         u8         signature[0x8];
9326         u8         reserved_3[0x8];
9327         u8         status[0x7];
9328         u8         ownership[0x1];
9329 };
9330
9331 struct mlx5_ifc_cmd_out_bits {
9332         u8         status[0x8];
9333         u8         reserved_0[0x18];
9334
9335         u8         syndrome[0x20];
9336
9337         u8         command_output[0x20];
9338 };
9339
9340 struct mlx5_ifc_cmd_in_bits {
9341         u8         opcode[0x10];
9342         u8         reserved_0[0x10];
9343
9344         u8         reserved_1[0x10];
9345         u8         op_mod[0x10];
9346
9347         u8         command[0][0x20];
9348 };
9349
9350 struct mlx5_ifc_cmd_if_box_bits {
9351         u8         mailbox_data[512][0x8];
9352
9353         u8         reserved_0[0x180];
9354
9355         u8         next_pointer_63_32[0x20];
9356
9357         u8         next_pointer_31_10[0x16];
9358         u8         reserved_1[0xa];
9359
9360         u8         block_number[0x20];
9361
9362         u8         reserved_2[0x8];
9363         u8         token[0x8];
9364         u8         ctrl_signature[0x8];
9365         u8         signature[0x8];
9366 };
9367
9368 struct mlx5_ifc_mtt_bits {
9369         u8         ptag_63_32[0x20];
9370
9371         u8         ptag_31_8[0x18];
9372         u8         reserved_0[0x6];
9373         u8         wr_en[0x1];
9374         u8         rd_en[0x1];
9375 };
9376
9377 /* Vendor Specific Capabilities, VSC */
9378 enum {
9379         MLX5_VSC_DOMAIN_ICMD                    = 0x1,
9380         MLX5_VSC_DOMAIN_PROTECTED_CRSPACE       = 0x6,
9381         MLX5_VSC_DOMAIN_SEMAPHORES              = 0xA,
9382 };
9383
9384 struct mlx5_ifc_vendor_specific_cap_bits {
9385         u8         type[0x8];
9386         u8         length[0x8];
9387         u8         next_pointer[0x8];
9388         u8         capability_id[0x8];
9389
9390         u8         status[0x3];
9391         u8         reserved_0[0xd];
9392         u8         space[0x10];
9393
9394         u8         counter[0x20];
9395
9396         u8         semaphore[0x20];
9397
9398         u8         flag[0x1];
9399         u8         reserved_1[0x1];
9400         u8         address[0x1e];
9401
9402         u8         data[0x20];
9403 };
9404
9405 enum {
9406         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9407         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9408         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9409 };
9410
9411 enum {
9412         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9413         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9414         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9415 };
9416
9417 enum {
9418         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9419         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9420         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9421         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9422         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9423         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9424         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9425         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9426         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9427         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9428         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9429 };
9430
9431 struct mlx5_ifc_initial_seg_bits {
9432         u8         fw_rev_minor[0x10];
9433         u8         fw_rev_major[0x10];
9434
9435         u8         cmd_interface_rev[0x10];
9436         u8         fw_rev_subminor[0x10];
9437
9438         u8         reserved_0[0x40];
9439
9440         u8         cmdq_phy_addr_63_32[0x20];
9441
9442         u8         cmdq_phy_addr_31_12[0x14];
9443         u8         reserved_1[0x2];
9444         u8         nic_interface[0x2];
9445         u8         log_cmdq_size[0x4];
9446         u8         log_cmdq_stride[0x4];
9447
9448         u8         command_doorbell_vector[0x20];
9449
9450         u8         reserved_2[0xf00];
9451
9452         u8         initializing[0x1];
9453         u8         reserved_3[0x4];
9454         u8         nic_interface_supported[0x3];
9455         u8         reserved_4[0x18];
9456
9457         struct mlx5_ifc_health_buffer_bits health_buffer;
9458
9459         u8         no_dram_nic_offset[0x20];
9460
9461         u8         reserved_5[0x6de0];
9462
9463         u8         internal_timer_h[0x20];
9464
9465         u8         internal_timer_l[0x20];
9466
9467         u8         reserved_6[0x20];
9468
9469         u8         reserved_7[0x1f];
9470         u8         clear_int[0x1];
9471
9472         u8         health_syndrome[0x8];
9473         u8         health_counter[0x18];
9474
9475         u8         reserved_8[0x17fc0];
9476 };
9477
9478 union mlx5_ifc_icmd_interface_document_bits {
9479         struct mlx5_ifc_fw_version_bits fw_version;
9480         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9481         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9482         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9483         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9484         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9485         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9486         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9487         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9488         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9489         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9490         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9491         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9492         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9493         u8         reserved_0[0x42c0];
9494 };
9495
9496 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9497         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9498         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9499         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9500         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9501         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9502         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9503         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9504         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9505         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9506         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9507         u8         reserved_0[0x7c0];
9508 };
9509
9510 struct mlx5_ifc_ppcnt_reg_bits {
9511         u8         swid[0x8];
9512         u8         local_port[0x8];
9513         u8         pnat[0x2];
9514         u8         reserved_0[0x8];
9515         u8         grp[0x6];
9516
9517         u8         clr[0x1];
9518         u8         reserved_1[0x1c];
9519         u8         prio_tc[0x3];
9520
9521         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9522 };
9523
9524 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9525         u8         life_time_counter_high[0x20];
9526
9527         u8         life_time_counter_low[0x20];
9528
9529         u8         rx_errors[0x20];
9530
9531         u8         tx_errors[0x20];
9532
9533         u8         l0_to_recovery_eieos[0x20];
9534
9535         u8         l0_to_recovery_ts[0x20];
9536
9537         u8         l0_to_recovery_framing[0x20];
9538
9539         u8         l0_to_recovery_retrain[0x20];
9540
9541         u8         crc_error_dllp[0x20];
9542
9543         u8         crc_error_tlp[0x20];
9544
9545         u8         reserved_0[0x680];
9546 };
9547
9548 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9549         u8         life_time_counter_high[0x20];
9550
9551         u8         life_time_counter_low[0x20];
9552
9553         u8         time_to_boot_image_start[0x20];
9554
9555         u8         time_to_link_image[0x20];
9556
9557         u8         calibration_time[0x20];
9558
9559         u8         time_to_first_perst[0x20];
9560
9561         u8         time_to_detect_state[0x20];
9562
9563         u8         time_to_l0[0x20];
9564
9565         u8         time_to_crs_en[0x20];
9566
9567         u8         time_to_plastic_image_start[0x20];
9568
9569         u8         time_to_iron_image_start[0x20];
9570
9571         u8         perst_handler[0x20];
9572
9573         u8         times_in_l1[0x20];
9574
9575         u8         times_in_l23[0x20];
9576
9577         u8         dl_down[0x20];
9578
9579         u8         config_cycle1usec[0x20];
9580
9581         u8         config_cycle2to7usec[0x20];
9582
9583         u8         config_cycle8to15usec[0x20];
9584
9585         u8         config_cycle16to63usec[0x20];
9586
9587         u8         config_cycle64usec[0x20];
9588
9589         u8         correctable_err_msg_sent[0x20];
9590
9591         u8         non_fatal_err_msg_sent[0x20];
9592
9593         u8         fatal_err_msg_sent[0x20];
9594
9595         u8         reserved_0[0x4e0];
9596 };
9597
9598 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9599         u8         life_time_counter_high[0x20];
9600
9601         u8         life_time_counter_low[0x20];
9602
9603         u8         error_counter_lane0[0x20];
9604
9605         u8         error_counter_lane1[0x20];
9606
9607         u8         error_counter_lane2[0x20];
9608
9609         u8         error_counter_lane3[0x20];
9610
9611         u8         error_counter_lane4[0x20];
9612
9613         u8         error_counter_lane5[0x20];
9614
9615         u8         error_counter_lane6[0x20];
9616
9617         u8         error_counter_lane7[0x20];
9618
9619         u8         error_counter_lane8[0x20];
9620
9621         u8         error_counter_lane9[0x20];
9622
9623         u8         error_counter_lane10[0x20];
9624
9625         u8         error_counter_lane11[0x20];
9626
9627         u8         error_counter_lane12[0x20];
9628
9629         u8         error_counter_lane13[0x20];
9630
9631         u8         error_counter_lane14[0x20];
9632
9633         u8         error_counter_lane15[0x20];
9634
9635         u8         reserved_0[0x580];
9636 };
9637
9638 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9639         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9640         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9641         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9642         u8         reserved_0[0xf8];
9643 };
9644
9645 struct mlx5_ifc_mpcnt_reg_bits {
9646         u8         reserved_0[0x8];
9647         u8         pcie_index[0x8];
9648         u8         reserved_1[0xa];
9649         u8         grp[0x6];
9650
9651         u8         clr[0x1];
9652         u8         reserved_2[0x1f];
9653
9654         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9655 };
9656
9657 union mlx5_ifc_ports_control_registers_document_bits {
9658         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9659         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9660         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9661         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9662         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9663         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9664         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9665         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9666         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9667         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9668         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9669         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9670         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9671         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9672         struct mlx5_ifc_paos_reg_bits paos_reg;
9673         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9674         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9675         struct mlx5_ifc_peir_reg_bits peir_reg;
9676         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9677         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9678         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9679         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9680         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9681         struct mlx5_ifc_phrr_reg_bits phrr_reg;
9682         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9683         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9684         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9685         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9686         struct mlx5_ifc_plib_reg_bits plib_reg;
9687         struct mlx5_ifc_pll_status_data_bits pll_status_data;
9688         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9689         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9690         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9691         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9692         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9693         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9694         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9695         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9696         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9697         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9698         struct mlx5_ifc_ppll_reg_bits ppll_reg;
9699         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9700         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9701         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9702         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9703         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9704         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9705         struct mlx5_ifc_pude_reg_bits pude_reg;
9706         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9707         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9708         struct mlx5_ifc_slrp_reg_bits slrp_reg;
9709         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9710         u8         reserved_0[0x7880];
9711 };
9712
9713 union mlx5_ifc_debug_enhancements_document_bits {
9714         struct mlx5_ifc_health_buffer_bits health_buffer;
9715         u8         reserved_0[0x200];
9716 };
9717
9718 union mlx5_ifc_no_dram_nic_document_bits {
9719         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9720         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9721         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9722         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9723         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9724         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9725         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9726         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9727         u8         reserved_0[0x3160];
9728 };
9729
9730 union mlx5_ifc_uplink_pci_interface_document_bits {
9731         struct mlx5_ifc_initial_seg_bits initial_seg;
9732         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9733         u8         reserved_0[0x20120];
9734 };
9735
9736 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9737         u8         e[0x1];
9738         u8         reserved_at_01[0x0b];
9739         u8         prio[0x04];
9740 };
9741
9742 struct mlx5_ifc_qpdpm_reg_bits {
9743         u8                                     reserved_at_0[0x8];
9744         u8                                     local_port[0x8];
9745         u8                                     reserved_at_10[0x10];
9746         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9747 };
9748
9749 struct mlx5_ifc_qpts_reg_bits {
9750         u8         reserved_at_0[0x8];
9751         u8         local_port[0x8];
9752         u8         reserved_at_10[0x2d];
9753         u8         trust_state[0x3];
9754 };
9755
9756 #endif /* MLX5_IFC_H */