2 * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _DEV_MLX5_MLX5IO_H_
29 #define _DEV_MLX5_MLX5IO_H_
31 #include <sys/ioccom.h>
33 struct mlx5_fwdump_reg {
38 struct mlx5_fwdump_addr {
45 struct mlx5_fwdump_get {
46 struct mlx5_fwdump_addr devaddr;
47 struct mlx5_fwdump_reg *buf;
49 size_t reg_filled; /* out */
52 #define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get)
53 #define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_fwdump_addr)
54 #define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_fwdump_addr)
57 #define MLX5_DEV_PATH _PATH_DEV"mlx5ctl"
67 enum mlx5_fpga_image {
68 MLX5_FPGA_IMAGE_USER = 0,
69 MLX5_FPGA_IMAGE_FACTORY = 1,
70 MLX5_FPGA_IMAGE_MAX = MLX5_FPGA_IMAGE_FACTORY,
71 MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
74 enum mlx5_fpga_status {
75 MLX5_FPGA_STATUS_SUCCESS = 0,
76 MLX5_FPGA_STATUS_FAILURE = 1,
77 MLX5_FPGA_STATUS_IN_PROGRESS = 2,
78 MLX5_FPGA_STATUS_DISCONNECTED = 3,
81 struct mlx5_fpga_query {
82 enum mlx5_fpga_image admin_image;
83 enum mlx5_fpga_image oper_image;
84 enum mlx5_fpga_status image_status;
88 MLX5_FPGA_TEE_DISABLE = 0,
89 MLX5_FPGA_TEE_GENERATE_EVENT = 1,
90 MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
93 enum mlx5_fpga_connect {
94 MLX5_FPGA_CONNECT_QUERY = 0,
95 MLX5_FPGA_CONNECT_DISCONNECT = 0x9,
96 MLX5_FPGA_CONNECT_CONNECT = 0xA,
100 * enum mlx5_fpga_access_type - Enumerated the different methods possible for
101 * accessing the device memory address space
103 enum mlx5_fpga_access_type {
104 /** Use the slow CX-FPGA I2C bus*/
105 MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
106 /** Use the fast 'shell QP' */
107 MLX5_FPGA_ACCESS_TYPE_RDMA,
108 /** Use the fastest available method */
109 MLX5_FPGA_ACCESS_TYPE_DONTCARE,
110 MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
113 #define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
114 #define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
116 struct mlx5_fpga_temperature {
117 uint32_t temperature;
120 uint32_t max_temperature;
121 uint32_t temperature_threshold_hi;
122 uint32_t temperature_threshold_lo;
125 char sensor_name[16];
128 #define MLX5_FPGA_CAP_ARR_SZ 0x40
130 #define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80)
131 #define MLX5_FPGA_LOAD _IOWINT('m', 0x81)
132 #define MLX5_FPGA_RESET _IO('m', 0x82)
133 #define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83)
134 #define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query)
135 #define MLX5_FPGA_CAP _IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ])
136 #define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature)
137 #define MLX5_FPGA_CONNECT _IOWR('m', 0x87, enum mlx5_fpga_connect)
139 #define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools"