2 * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _DEV_MLX5_MLX5IO_H_
29 #define _DEV_MLX5_MLX5IO_H_
31 #include <sys/ioccom.h>
33 struct mlx5_fwdump_reg {
38 struct mlx5_tool_addr {
45 struct mlx5_fwdump_get {
46 struct mlx5_tool_addr devaddr;
47 struct mlx5_fwdump_reg *buf;
49 size_t reg_filled; /* out */
52 struct mlx5_fw_update {
53 struct mlx5_tool_addr devaddr;
55 size_t img_fw_data_len;
58 struct mlx5_eeprom_get {
59 struct mlx5_tool_addr devaddr;
60 uint32_t *eeprom_info_buf;
61 uint8_t eeprom_info_page_valid;
62 size_t eeprom_info_out_len;
65 #define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get)
66 #define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_tool_addr)
67 #define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_tool_addr)
68 #define MLX5_FW_UPDATE _IOW('m', 4, struct mlx5_fw_update)
69 #define MLX5_FW_RESET _IOW('m', 5, struct mlx5_tool_addr)
70 #define MLX5_EEPROM_GET _IOWR('m', 6, struct mlx5_eeprom_get)
73 #define MLX5_DEV_PATH _PATH_DEV"mlx5ctl"
83 enum mlx5_fpga_image {
84 MLX5_FPGA_IMAGE_USER = 0,
85 MLX5_FPGA_IMAGE_FACTORY = 1,
86 MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
87 MLX5_FPGA_IMAGE_RESET = 17,
88 MLX5_FPGA_IMAGE_RELOAD = 18,
91 enum mlx5_fpga_status {
92 MLX5_FPGA_STATUS_SUCCESS = 0,
93 MLX5_FPGA_STATUS_FAILURE = 1,
94 MLX5_FPGA_STATUS_IN_PROGRESS = 2,
95 MLX5_FPGA_STATUS_DISCONNECTED = 3,
98 struct mlx5_fpga_query {
99 enum mlx5_fpga_image admin_image;
100 enum mlx5_fpga_image oper_image;
101 enum mlx5_fpga_status image_status;
105 MLX5_FPGA_TEE_DISABLE = 0,
106 MLX5_FPGA_TEE_GENERATE_EVENT = 1,
107 MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
110 enum mlx5_fpga_connect {
111 MLX5_FPGA_CONNECT_QUERY = 0,
112 MLX5_FPGA_CONNECT_DISCONNECT = 0x9,
113 MLX5_FPGA_CONNECT_CONNECT = 0xA,
117 * enum mlx5_fpga_access_type - Enumerated the different methods possible for
118 * accessing the device memory address space
120 enum mlx5_fpga_access_type {
121 /** Use the slow CX-FPGA I2C bus*/
122 MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
123 /** Use the fast 'shell QP' */
124 MLX5_FPGA_ACCESS_TYPE_RDMA,
125 /** Use the fastest available method */
126 MLX5_FPGA_ACCESS_TYPE_DONTCARE,
127 MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
130 #define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
131 #define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
133 struct mlx5_fpga_temperature {
134 uint32_t temperature;
137 uint32_t max_temperature;
138 uint32_t temperature_threshold_hi;
139 uint32_t temperature_threshold_lo;
142 char sensor_name[16];
145 #define MLX5_FPGA_CAP_ARR_SZ 0x40
147 #define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80)
148 #define MLX5_FPGA_LOAD _IOWINT('m', 0x81)
149 #define MLX5_FPGA_RESET _IO('m', 0x82)
150 #define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83)
151 #define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query)
152 #define MLX5_FPGA_CAP _IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ])
153 #define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature)
154 #define MLX5_FPGA_CONNECT _IOWR('m', 0x87, enum mlx5_fpga_connect)
155 #define MLX5_FPGA_RELOAD _IO('m', 0x88)
157 #define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools"