sys/dev/mlx5/qp.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_QP_H
  29 #define MLX5_QP_H
  30
  31 #include <dev/mlx5/driver.h>
  32
  33 #define MLX5_INVALID_LKEY       0x100
  34 #define MLX5_SIG_WQE_SIZE       (MLX5_SEND_WQE_BB * 5)
  35 #define MLX5_DIF_SIZE           8
  36 #define MLX5_STRIDE_BLOCK_OP    0x400
  37 #define MLX5_CPY_GRD_MASK       0xc0
  38 #define MLX5_CPY_APP_MASK       0x30
  39 #define MLX5_CPY_REF_MASK       0x0f
  40 #define MLX5_BSF_INC_REFTAG     (1 << 6)
  41 #define MLX5_BSF_INL_VALID      (1 << 15)
  42 #define MLX5_BSF_REFRESH_DIF    (1 << 14)
  43 #define MLX5_BSF_REPEAT_BLOCK   (1 << 7)
  44 #define MLX5_BSF_APPTAG_ESCAPE  0x1
  45 #define MLX5_BSF_APPREF_ESCAPE  0x2
  46 #define MLX5_WQE_DS_UNITS 16
  47
  48 enum mlx5_qp_optpar {
  49         MLX5_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  50         MLX5_QP_OPTPAR_RRE                      = 1 << 1,
  51         MLX5_QP_OPTPAR_RAE                      = 1 << 2,
  52         MLX5_QP_OPTPAR_RWE                      = 1 << 3,
  53         MLX5_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  54         MLX5_QP_OPTPAR_Q_KEY                    = 1 << 5,
  55         MLX5_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  56         MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  57         MLX5_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  58         MLX5_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  59         MLX5_QP_OPTPAR_PM_STATE                 = 1 << 10,
  60         MLX5_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  61         MLX5_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  62         MLX5_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  63         MLX5_QP_OPTPAR_PRI_PORT                 = 1 << 16,
  64         MLX5_QP_OPTPAR_SRQN                     = 1 << 18,
  65         MLX5_QP_OPTPAR_CQN_RCV                  = 1 << 19,
  66         MLX5_QP_OPTPAR_DC_HS                    = 1 << 20,
  67         MLX5_QP_OPTPAR_DC_KEY                   = 1 << 21,
  68 };
  69
  70 enum mlx5_qp_state {
  71         MLX5_QP_STATE_RST                       = 0,
  72         MLX5_QP_STATE_INIT                      = 1,
  73         MLX5_QP_STATE_RTR                       = 2,
  74         MLX5_QP_STATE_RTS                       = 3,
  75         MLX5_QP_STATE_SQER                      = 4,
  76         MLX5_QP_STATE_SQD                       = 5,
  77         MLX5_QP_STATE_ERR                       = 6,
  78         MLX5_QP_STATE_SQ_DRAINING               = 7,
  79         MLX5_QP_STATE_SUSPENDED                 = 9,
  80         MLX5_QP_NUM_STATE,
  81         MLX5_QP_STATE,
  82         MLX5_QP_STATE_BAD,
  83 };
  84
  85 enum {
  86         MLX5_SQ_STATE_NA        = MLX5_SQC_STATE_ERR + 1,
  87         MLX5_SQ_NUM_STATE       = MLX5_SQ_STATE_NA + 1,
  88         MLX5_RQ_STATE_NA        = MLX5_RQC_STATE_ERR + 1,
  89         MLX5_RQ_NUM_STATE       = MLX5_RQ_STATE_NA + 1,
  90 };
  91
  92 enum {
  93         MLX5_QP_ST_RC                           = 0x0,
  94         MLX5_QP_ST_UC                           = 0x1,
  95         MLX5_QP_ST_UD                           = 0x2,
  96         MLX5_QP_ST_XRC                          = 0x3,
  97         MLX5_QP_ST_MLX                          = 0x4,
  98         MLX5_QP_ST_DCI                          = 0x5,
  99         MLX5_QP_ST_DCT                          = 0x6,
 100         MLX5_QP_ST_QP0                          = 0x7,
 101         MLX5_QP_ST_QP1                          = 0x8,
 102         MLX5_QP_ST_RAW_ETHERTYPE                = 0x9,
 103         MLX5_QP_ST_RAW_IPV6                     = 0xa,
 104         MLX5_QP_ST_SNIFFER                      = 0xb,
 105         MLX5_QP_ST_SYNC_UMR                     = 0xe,
 106         MLX5_QP_ST_PTP_1588                     = 0xd,
 107         MLX5_QP_ST_REG_UMR                      = 0xc,
 108         MLX5_QP_ST_SW_CNAK                      = 0x10,
 109         MLX5_QP_ST_MAX
 110 };
 111
 112 enum {
 113         MLX5_NON_ZERO_RQ        = 0x0,
 114         MLX5_SRQ_RQ             = 0x1,
 115         MLX5_CRQ_RQ             = 0x2,
 116         MLX5_ZERO_LEN_RQ        = 0x3
 117 };
 118
 119 enum {
 120         /* params1 */
 121         MLX5_QP_BIT_SRE                         = 1 << 15,
 122         MLX5_QP_BIT_SWE                         = 1 << 14,
 123         MLX5_QP_BIT_SAE                         = 1 << 13,
 124         /* params2 */
 125         MLX5_QP_BIT_RRE                         = 1 << 15,
 126         MLX5_QP_BIT_RWE                         = 1 << 14,
 127         MLX5_QP_BIT_RAE                         = 1 << 13,
 128         MLX5_QP_BIT_RIC                         = 1 <<  4,
 129         MLX5_QP_BIT_COLL_SYNC_RQ                = 1 << 2,
 130         MLX5_QP_BIT_COLL_SYNC_SQ                = 1 << 1,
 131         MLX5_QP_BIT_COLL_MASTER                 = 1 << 0
 132 };
 133
 134 enum {
 135         MLX5_DCT_BIT_RRE                = 1 << 19,
 136         MLX5_DCT_BIT_RWE                = 1 << 18,
 137         MLX5_DCT_BIT_RAE                = 1 << 17,
 138 };
 139
 140 enum {
 141         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
 142         MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
 143         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
 144 };
 145
 146 #define MLX5_SEND_WQE_DS        16
 147 #define MLX5_SEND_WQE_BB        64
 148 #define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
 149
 150 enum {
 151         MLX5_SEND_WQE_MAX_WQEBBS        = 16,
 152 };
 153
 154 enum {
 155         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 156         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 157         MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 158         MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 159         MLX5_WQE_FMR_PERM_ATOMIC        = 1U << 31
 160 };
 161
 162 enum {
 163         MLX5_FENCE_MODE_NONE                    = 0 << 5,
 164         MLX5_FENCE_MODE_INITIATOR_SMALL         = 1 << 5,
 165         MLX5_FENCE_MODE_FENCE                   = 2 << 5,
 166         MLX5_FENCE_MODE_STRONG_ORDERING         = 3 << 5,
 167         MLX5_FENCE_MODE_SMALL_AND_FENCE         = 4 << 5,
 168 };
 169
 170 enum {
 171         MLX5_RCV_DBR    = 0,
 172         MLX5_SND_DBR    = 1,
 173 };
 174
 175 enum {
 176         MLX5_FLAGS_INLINE       = 1<<7,
 177         MLX5_FLAGS_CHECK_FREE   = 1<<5,
 178 };
 179
 180 struct mlx5_wqe_fmr_seg {
 181         __be32                  flags;
 182         __be32                  mem_key;
 183         __be64                  buf_list;
 184         __be64                  start_addr;
 185         __be64                  reg_len;
 186         __be32                  offset;
 187         __be32                  page_size;
 188         u32                     reserved[2];
 189 };
 190
 191 struct mlx5_wqe_ctrl_seg {
 192         __be32                  opmod_idx_opcode;
 193         __be32                  qpn_ds;
 194         u8                      signature;
 195         u8                      rsvd[2];
 196         u8                      fm_ce_se;
 197         __be32                  imm;
 198 };
 199
 200 #define MLX5_WQE_CTRL_DS_MASK 0x3f
 201
 202 enum {
 203         MLX5_MLX_FLAG_MASK_VL15 = 0x40,
 204         MLX5_MLX_FLAG_MASK_SLR  = 0x20,
 205         MLX5_MLX_FLAG_MASK_ICRC = 0x8,
 206         MLX5_MLX_FLAG_MASK_FL   = 4
 207 };
 208
 209 struct mlx5_mlx_seg {
 210         __be32          rsvd0;
 211         u8              flags;
 212         u8              stat_rate_sl;
 213         u8              rsvd1[8];
 214         __be16          dlid;
 215 };
 216
 217 enum {
 218         MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
 219         MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
 220         MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
 221         MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
 222 };
 223
 224 enum {
 225         MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0,
 226         MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1,
 227         MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4,
 228         MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5,
 229 };
 230
 231 struct mlx5_wqe_eth_seg {
 232         u8              swp_outer_l4_offset;
 233         u8              swp_outer_l3_offset;
 234         u8              swp_inner_l4_offset;
 235         u8              swp_inner_l3_offset;
 236         u8              cs_flags;
 237         u8              swp_flags;
 238         __be16          mss;
 239         __be32          rsvd2;
 240         union {
 241                 struct {
 242                         __be16          inline_hdr_sz;
 243                         u8              inline_hdr_start[2];
 244                 };
 245                 struct {
 246                         __be16          vlan_cmd;
 247                         __be16          vlan_hdr;
 248                 };
 249         };
 250 };
 251
 252 struct mlx5_wqe_xrc_seg {
 253         __be32                  xrc_srqn;
 254         u8                      rsvd[12];
 255 };
 256
 257 struct mlx5_wqe_masked_atomic_seg {
 258         __be64                  swap_add;
 259         __be64                  compare;
 260         __be64                  swap_add_mask;
 261         __be64                  compare_mask;
 262 };
 263
 264 struct mlx5_av {
 265         union {
 266                 struct {
 267                         __be32  qkey;
 268                         __be32  reserved;
 269                 } qkey;
 270                 __be64  dc_key;
 271         } key;
 272         __be32  dqp_dct;
 273         u8      stat_rate_sl;
 274         u8      fl_mlid;
 275         union {
 276                 __be16  rlid;
 277                 __be16  udp_sport;
 278         };
 279         u8      reserved0[4];
 280         u8      rmac[6];
 281         u8      tclass;
 282         u8      hop_limit;
 283         __be32  grh_gid_fl;
 284         u8      rgid[16];
 285 };
 286
 287 struct mlx5_wqe_datagram_seg {
 288         struct mlx5_av  av;
 289 };
 290
 291 struct mlx5_wqe_raddr_seg {
 292         __be64                  raddr;
 293         __be32                  rkey;
 294         u32                     reserved;
 295 };
 296
 297 struct mlx5_wqe_atomic_seg {
 298         __be64                  swap_add;
 299         __be64                  compare;
 300 };
 301
 302 struct mlx5_wqe_data_seg {
 303         __be32                  byte_count;
 304         __be32                  lkey;
 305         __be64                  addr;
 306 };
 307
 308 struct mlx5_wqe_umr_ctrl_seg {
 309         u8              flags;
 310         u8              rsvd0[3];
 311         __be16          klm_octowords;
 312         __be16          bsf_octowords;
 313         __be64          mkey_mask;
 314         u8              rsvd1[32];
 315 };
 316
 317 struct mlx5_seg_set_psv {
 318         __be32          psv_num;
 319         __be16          syndrome;
 320         __be16          status;
 321         __be32          transient_sig;
 322         __be32          ref_tag;
 323 };
 324
 325 struct mlx5_seg_get_psv {
 326         u8              rsvd[19];
 327         u8              num_psv;
 328         __be32          l_key;
 329         __be64          va;
 330         __be32          psv_index[4];
 331 };
 332
 333 struct mlx5_seg_check_psv {
 334         u8              rsvd0[2];
 335         __be16          err_coalescing_op;
 336         u8              rsvd1[2];
 337         __be16          xport_err_op;
 338         u8              rsvd2[2];
 339         __be16          xport_err_mask;
 340         u8              rsvd3[7];
 341         u8              num_psv;
 342         __be32          l_key;
 343         __be64          va;
 344         __be32          psv_index[4];
 345 };
 346
 347 struct mlx5_rwqe_sig {
 348         u8      rsvd0[4];
 349         u8      signature;
 350         u8      rsvd1[11];
 351 };
 352
 353 struct mlx5_wqe_signature_seg {
 354         u8      rsvd0[4];
 355         u8      signature;
 356         u8      rsvd1[11];
 357 };
 358
 359 struct mlx5_wqe_inline_seg {
 360         __be32  byte_count;
 361 };
 362
 363 enum mlx5_sig_type {
 364         MLX5_DIF_CRC = 0x1,
 365         MLX5_DIF_IPCS = 0x2,
 366 };
 367
 368 struct mlx5_bsf_inl {
 369         __be16          vld_refresh;
 370         __be16          dif_apptag;
 371         __be32          dif_reftag;
 372         u8              sig_type;
 373         u8              rp_inv_seed;
 374         u8              rsvd[3];
 375         u8              dif_inc_ref_guard_check;
 376         __be16          dif_app_bitmask_check;
 377 };
 378
 379 struct mlx5_bsf {
 380         struct mlx5_bsf_basic {
 381                 u8              bsf_size_sbs;
 382                 u8              check_byte_mask;
 383                 union {
 384                         u8      copy_byte_mask;
 385                         u8      bs_selector;
 386                         u8      rsvd_wflags;
 387                 } wire;
 388                 union {
 389                         u8      bs_selector;
 390                         u8      rsvd_mflags;
 391                 } mem;
 392                 __be32          raw_data_size;
 393                 __be32          w_bfs_psv;
 394                 __be32          m_bfs_psv;
 395         } basic;
 396         struct mlx5_bsf_ext {
 397                 __be32          t_init_gen_pro_size;
 398                 __be32          rsvd_epi_size;
 399                 __be32          w_tfs_psv;
 400                 __be32          m_tfs_psv;
 401         } ext;
 402         struct mlx5_bsf_inl     w_inl;
 403         struct mlx5_bsf_inl     m_inl;
 404 };
 405
 406 struct mlx5_klm {
 407         __be32          bcount;
 408         __be32          key;
 409         __be64          va;
 410 };
 411
 412 struct mlx5_stride_block_entry {
 413         __be16          stride;
 414         __be16          bcount;
 415         __be32          key;
 416         __be64          va;
 417 };
 418
 419 struct mlx5_stride_block_ctrl_seg {
 420         __be32          bcount_per_cycle;
 421         __be32          op;
 422         __be32          repeat_count;
 423         u16             rsvd;
 424         __be16          num_entries;
 425 };
 426
 427 enum mlx5_pagefault_flags {
 428         MLX5_PFAULT_REQUESTOR = 1 << 0,
 429         MLX5_PFAULT_WRITE     = 1 << 1,
 430         MLX5_PFAULT_RDMA      = 1 << 2,
 431 };
 432
 433 /* Contains the details of a pagefault. */
 434 struct mlx5_pagefault {
 435         u32                     bytes_committed;
 436         u8                      event_subtype;
 437         enum mlx5_pagefault_flags flags;
 438         union {
 439                 /* Initiator or send message responder pagefault details. */
 440                 struct {
 441                         /* Received packet size, only valid for responders. */
 442                         u32     packet_size;
 443                         /*
 444                          * WQE index. Refers to either the send queue or
 445                          * receive queue, according to event_subtype.
 446                          */
 447                         u16     wqe_index;
 448                 } wqe;
 449                 /* RDMA responder pagefault details */
 450                 struct {
 451                         u32     r_key;
 452                         /*
 453                          * Received packet size, minimal size page fault
 454                          * resolution required for forward progress.
 455                          */
 456                         u32     packet_size;
 457                         u32     rdma_op_len;
 458                         u64     rdma_va;
 459                 } rdma;
 460         };
 461 };
 462
 463 struct mlx5_core_qp {
 464         struct mlx5_core_rsc_common     common; /* must be first */
 465         void (*event)           (struct mlx5_core_qp *, int);
 466         int                     qpn;
 467         struct mlx5_rsc_debug   *dbg;
 468         int                     pid;
 469 };
 470
 471 struct mlx5_qp_path {
 472         u8                      fl_free_ar;
 473         u8                      rsvd3;
 474         __be16                  pkey_index;
 475         u8                      rsvd0;
 476         u8                      grh_mlid;
 477         __be16                  rlid;
 478         u8                      ackto_lt;
 479         u8                      mgid_index;
 480         u8                      static_rate;
 481         u8                      hop_limit;
 482         __be32                  tclass_flowlabel;
 483         union {
 484                 u8              rgid[16];
 485                 u8              rip[16];
 486         };
 487         u8                      f_dscp_ecn_prio;
 488         u8                      ecn_dscp;
 489         __be16                  udp_sport;
 490         u8                      dci_cfi_prio_sl;
 491         u8                      port;
 492         u8                      rmac[6];
 493 };
 494
 495 struct mlx5_qp_context {
 496         __be32                  flags;
 497         __be32                  flags_pd;
 498         u8                      mtu_msgmax;
 499         u8                      rq_size_stride;
 500         __be16                  sq_crq_size;
 501         __be32                  qp_counter_set_usr_page;
 502         __be32                  wire_qpn;
 503         __be32                  log_pg_sz_remote_qpn;
 504         struct                  mlx5_qp_path pri_path;
 505         struct                  mlx5_qp_path alt_path;
 506         __be32                  params1;
 507         u8                      reserved2[4];
 508         __be32                  next_send_psn;
 509         __be32                  cqn_send;
 510         __be32                  deth_sqpn;
 511         u8                      reserved3[4];
 512         __be32                  last_acked_psn;
 513         __be32                  ssn;
 514         __be32                  params2;
 515         __be32                  rnr_nextrecvpsn;
 516         __be32                  xrcd;
 517         __be32                  cqn_recv;
 518         __be64                  db_rec_addr;
 519         __be32                  qkey;
 520         __be32                  rq_type_srqn;
 521         __be32                  rmsn;
 522         __be16                  hw_sq_wqe_counter;
 523         __be16                  sw_sq_wqe_counter;
 524         __be16                  hw_rcyclic_byte_counter;
 525         __be16                  hw_rq_counter;
 526         __be16                  sw_rcyclic_byte_counter;
 527         __be16                  sw_rq_counter;
 528         u8                      rsvd0[5];
 529         u8                      cgs;
 530         u8                      cs_req;
 531         u8                      cs_res;
 532         __be64                  dc_access_key;
 533         u8                      rsvd1[24];
 534 };
 535
 536 struct mlx5_dct_context {
 537         u8                      state;
 538         u8                      rsvd0[7];
 539         __be32                  cqn;
 540         __be32                  flags;
 541         u8                      rsvd1;
 542         u8                      cs_res;
 543         u8                      min_rnr;
 544         u8                      rsvd2;
 545         __be32                  srqn;
 546         __be32                  pdn;
 547         __be32                  tclass_flow_label;
 548         __be64                  access_key;
 549         u8                      mtu;
 550         u8                      port;
 551         __be16                  pkey_index;
 552         u8                      rsvd4;
 553         u8                      mgid_index;
 554         u8                      rsvd5;
 555         u8                      hop_limit;
 556         __be32                  access_violations;
 557         u8                      rsvd[12];
 558 };
 559
 560 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
 561 {
 562         return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
 563 }
 564
 565 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
 566 {
 567         return radix_tree_lookup(&dev->priv.mr_table.tree, key);
 568 }
 569
 570 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
 571                         struct mlx5_core_qp *qp,
 572                         u32 *in,
 573                         int inlen);
 574 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
 575                         u32 opt_param_mask, void *qpc,
 576                         struct mlx5_core_qp *qp);
 577 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
 578                          struct mlx5_core_qp *qp);
 579 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
 580                        u32 *out, int outlen);
 581 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct,
 582                         u32 *out, int outlen);
 583 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct);
 584
 585 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
 586 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
 587 int mlx5_core_create_dct(struct mlx5_core_dev *dev,
 588                          struct mlx5_core_dct *dct,
 589                          u32 *in);
 590 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev,
 591                           struct mlx5_core_dct *dct);
 592 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
 593                                 struct mlx5_core_qp *rq);
 594 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
 595                                   struct mlx5_core_qp *rq);
 596 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
 597                                 struct mlx5_core_qp *sq);
 598 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
 599                                   struct mlx5_core_qp *sq);
 600 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
 601 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
 602 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 603 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 604
 605 static inline const char *mlx5_qp_type_str(int type)
 606 {
 607         switch (type) {
 608         case MLX5_QP_ST_RC: return "RC";
 609         case MLX5_QP_ST_UC: return "C";
 610         case MLX5_QP_ST_UD: return "UD";
 611         case MLX5_QP_ST_XRC: return "XRC";
 612         case MLX5_QP_ST_MLX: return "MLX";
 613         case MLX5_QP_ST_DCI: return "DCI";
 614         case MLX5_QP_ST_QP0: return "QP0";
 615         case MLX5_QP_ST_QP1: return "QP1";
 616         case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
 617         case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
 618         case MLX5_QP_ST_SNIFFER: return "SNIFFER";
 619         case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
 620         case MLX5_QP_ST_PTP_1588: return "PTP_1588";
 621         case MLX5_QP_ST_REG_UMR: return "REG_UMR";
 622         case MLX5_QP_ST_SW_CNAK: return "DC_CNAK";
 623         default: return "Invalid transport type";
 624         }
 625 }
 626
 627 static inline const char *mlx5_qp_state_str(int state)
 628 {
 629         switch (state) {
 630         case MLX5_QP_STATE_RST:
 631         return "RST";
 632         case MLX5_QP_STATE_INIT:
 633         return "INIT";
 634         case MLX5_QP_STATE_RTR:
 635         return "RTR";
 636         case MLX5_QP_STATE_RTS:
 637         return "RTS";
 638         case MLX5_QP_STATE_SQER:
 639         return "SQER";
 640         case MLX5_QP_STATE_SQD:
 641         return "SQD";
 642         case MLX5_QP_STATE_ERR:
 643         return "ERR";
 644         case MLX5_QP_STATE_SQ_DRAINING:
 645         return "SQ_DRAINING";
 646         case MLX5_QP_STATE_SUSPENDED:
 647         return "SUSPENDED";
 648         default: return "Invalid QP state";
 649         }
 650 }
 651
 652 #endif /* MLX5_QP_H */