2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <dev/mlx5/driver.h>
33 #define MLX5_INVALID_LKEY 0x100
34 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
35 #define MLX5_DIF_SIZE 8
36 #define MLX5_STRIDE_BLOCK_OP 0x400
37 #define MLX5_CPY_GRD_MASK 0xc0
38 #define MLX5_CPY_APP_MASK 0x30
39 #define MLX5_CPY_REF_MASK 0x0f
40 #define MLX5_BSF_INC_REFTAG (1 << 6)
41 #define MLX5_BSF_INL_VALID (1 << 15)
42 #define MLX5_BSF_REFRESH_DIF (1 << 14)
43 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
44 #define MLX5_BSF_APPTAG_ESCAPE 0x1
45 #define MLX5_BSF_APPREF_ESCAPE 0x2
46 #define MLX5_WQE_DS_UNITS 16
49 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
50 MLX5_QP_OPTPAR_RRE = 1 << 1,
51 MLX5_QP_OPTPAR_RAE = 1 << 2,
52 MLX5_QP_OPTPAR_RWE = 1 << 3,
53 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
54 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
55 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
56 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
57 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
58 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
59 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
60 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
61 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
62 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
63 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
64 MLX5_QP_OPTPAR_SRQN = 1 << 18,
65 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
66 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
67 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
71 MLX5_QP_STATE_RST = 0,
72 MLX5_QP_STATE_INIT = 1,
73 MLX5_QP_STATE_RTR = 2,
74 MLX5_QP_STATE_RTS = 3,
75 MLX5_QP_STATE_SQER = 4,
76 MLX5_QP_STATE_SQD = 5,
77 MLX5_QP_STATE_ERR = 6,
78 MLX5_QP_STATE_SQ_DRAINING = 7,
79 MLX5_QP_STATE_SUSPENDED = 9,
86 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
87 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
88 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
89 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
100 MLX5_QP_ST_QP0 = 0x7,
101 MLX5_QP_ST_QP1 = 0x8,
102 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
103 MLX5_QP_ST_RAW_IPV6 = 0xa,
104 MLX5_QP_ST_SNIFFER = 0xb,
105 MLX5_QP_ST_SYNC_UMR = 0xe,
106 MLX5_QP_ST_PTP_1588 = 0xd,
107 MLX5_QP_ST_REG_UMR = 0xc,
108 MLX5_QP_ST_SW_CNAK = 0x10,
113 MLX5_NON_ZERO_RQ = 0x0,
116 MLX5_ZERO_LEN_RQ = 0x3
121 MLX5_QP_BIT_SRE = 1 << 15,
122 MLX5_QP_BIT_SWE = 1 << 14,
123 MLX5_QP_BIT_SAE = 1 << 13,
125 MLX5_QP_BIT_RRE = 1 << 15,
126 MLX5_QP_BIT_RWE = 1 << 14,
127 MLX5_QP_BIT_RAE = 1 << 13,
128 MLX5_QP_BIT_RIC = 1 << 4,
129 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2,
130 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1,
131 MLX5_QP_BIT_COLL_MASTER = 1 << 0
135 MLX5_DCT_BIT_RRE = 1 << 19,
136 MLX5_DCT_BIT_RWE = 1 << 18,
137 MLX5_DCT_BIT_RAE = 1 << 17,
141 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
142 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
143 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
147 MLX5_SEND_WQE_DS = 16,
148 MLX5_SEND_WQE_BB = 64,
151 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
154 MLX5_SEND_WQE_MAX_WQEBBS = 16,
158 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
159 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
160 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
161 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
162 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
166 MLX5_FENCE_MODE_NONE = 0 << 5,
167 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
168 MLX5_FENCE_MODE_FENCE = 2 << 5,
169 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
170 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
174 MLX5_QP_DRAIN_SIGERR = 1 << 26,
175 MLX5_QP_LAT_SENSITIVE = 1 << 28,
176 MLX5_QP_BLOCK_MCAST = 1 << 30,
177 MLX5_QP_ENABLE_SIG = 1 << 31,
186 MLX5_FLAGS_INLINE = 1<<7,
187 MLX5_FLAGS_CHECK_FREE = 1<<5,
190 struct mlx5_wqe_fmr_seg {
201 struct mlx5_wqe_ctrl_seg {
202 __be32 opmod_idx_opcode;
210 #define MLX5_WQE_CTRL_DS_MASK 0x3f
213 MLX5_MLX_FLAG_MASK_VL15 = 0x40,
214 MLX5_MLX_FLAG_MASK_SLR = 0x20,
215 MLX5_MLX_FLAG_MASK_ICRC = 0x8,
216 MLX5_MLX_FLAG_MASK_FL = 4
219 struct mlx5_mlx_seg {
228 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
229 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
230 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
231 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
235 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0,
236 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1,
237 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4,
238 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5,
241 struct mlx5_wqe_eth_seg {
242 u8 swp_outer_l4_offset;
243 u8 swp_outer_l3_offset;
244 u8 swp_inner_l4_offset;
245 u8 swp_inner_l3_offset;
250 __be16 inline_hdr_sz;
251 u8 inline_hdr_start[2];
254 struct mlx5_wqe_xrc_seg {
259 struct mlx5_wqe_masked_atomic_seg {
262 __be64 swap_add_mask;
289 struct mlx5_wqe_datagram_seg {
293 struct mlx5_wqe_raddr_seg {
299 struct mlx5_wqe_atomic_seg {
304 struct mlx5_wqe_data_seg {
310 struct mlx5_wqe_umr_ctrl_seg {
313 __be16 klm_octowords;
314 __be16 bsf_octowords;
319 struct mlx5_seg_set_psv {
323 __be32 transient_sig;
327 struct mlx5_seg_get_psv {
335 struct mlx5_seg_check_psv {
337 __be16 err_coalescing_op;
341 __be16 xport_err_mask;
349 struct mlx5_rwqe_sig {
355 struct mlx5_wqe_signature_seg {
361 struct mlx5_wqe_inline_seg {
370 struct mlx5_bsf_inl {
377 u8 dif_inc_ref_guard_check;
378 __be16 dif_app_bitmask_check;
382 struct mlx5_bsf_basic {
394 __be32 raw_data_size;
398 struct mlx5_bsf_ext {
399 __be32 t_init_gen_pro_size;
400 __be32 rsvd_epi_size;
404 struct mlx5_bsf_inl w_inl;
405 struct mlx5_bsf_inl m_inl;
414 struct mlx5_stride_block_entry {
421 struct mlx5_stride_block_ctrl_seg {
422 __be32 bcount_per_cycle;
429 enum mlx5_pagefault_flags {
430 MLX5_PFAULT_REQUESTOR = 1 << 0,
431 MLX5_PFAULT_WRITE = 1 << 1,
432 MLX5_PFAULT_RDMA = 1 << 2,
435 /* Contains the details of a pagefault. */
436 struct mlx5_pagefault {
439 enum mlx5_pagefault_flags flags;
441 /* Initiator or send message responder pagefault details. */
443 /* Received packet size, only valid for responders. */
446 * WQE index. Refers to either the send queue or
447 * receive queue, according to event_subtype.
451 /* RDMA responder pagefault details */
455 * Received packet size, minimal size page fault
456 * resolution required for forward progress.
465 struct mlx5_core_qp {
466 struct mlx5_core_rsc_common common; /* must be first */
467 void (*event) (struct mlx5_core_qp *, int);
469 struct mlx5_rsc_debug *dbg;
473 struct mlx5_qp_path {
484 __be32 tclass_flowlabel;
497 struct mlx5_qp_context {
503 __be32 qp_counter_set_usr_page;
505 __be32 log_pg_sz_remote_qpn;
506 struct mlx5_qp_path pri_path;
507 struct mlx5_qp_path alt_path;
510 __be32 next_send_psn;
514 __be32 last_acked_psn;
517 __be32 rnr_nextrecvpsn;
524 __be16 hw_sq_wqe_counter;
525 __be16 sw_sq_wqe_counter;
526 __be16 hw_rcyclic_byte_counter;
527 __be16 hw_rq_counter;
528 __be16 sw_rcyclic_byte_counter;
529 __be16 sw_rq_counter;
534 __be64 dc_access_key;
538 struct mlx5_create_qp_mbox_in {
539 struct mlx5_inbox_hdr hdr;
542 __be32 opt_param_mask;
544 struct mlx5_qp_context ctx;
549 struct mlx5_dct_context {
560 __be32 tclass_flow_label;
569 __be32 access_violations;
573 struct mlx5_create_dct_mbox_in {
574 struct mlx5_inbox_hdr hdr;
576 struct mlx5_dct_context context;
580 struct mlx5_create_dct_mbox_out {
581 struct mlx5_outbox_hdr hdr;
586 struct mlx5_destroy_dct_mbox_in {
587 struct mlx5_inbox_hdr hdr;
592 struct mlx5_destroy_dct_mbox_out {
593 struct mlx5_outbox_hdr hdr;
597 struct mlx5_drain_dct_mbox_in {
598 struct mlx5_inbox_hdr hdr;
603 struct mlx5_drain_dct_mbox_out {
604 struct mlx5_outbox_hdr hdr;
608 struct mlx5_create_qp_mbox_out {
609 struct mlx5_outbox_hdr hdr;
614 struct mlx5_destroy_qp_mbox_in {
615 struct mlx5_inbox_hdr hdr;
620 struct mlx5_destroy_qp_mbox_out {
621 struct mlx5_outbox_hdr hdr;
625 struct mlx5_modify_qp_mbox_in {
626 struct mlx5_inbox_hdr hdr;
631 struct mlx5_qp_context ctx;
635 struct mlx5_modify_qp_mbox_out {
636 struct mlx5_outbox_hdr hdr;
640 struct mlx5_query_qp_mbox_in {
641 struct mlx5_inbox_hdr hdr;
646 struct mlx5_query_qp_mbox_out {
647 struct mlx5_outbox_hdr hdr;
651 struct mlx5_qp_context ctx;
656 struct mlx5_query_dct_mbox_in {
657 struct mlx5_inbox_hdr hdr;
662 struct mlx5_query_dct_mbox_out {
663 struct mlx5_outbox_hdr hdr;
665 struct mlx5_dct_context ctx;
669 struct mlx5_arm_dct_mbox_in {
670 struct mlx5_inbox_hdr hdr;
675 struct mlx5_arm_dct_mbox_out {
676 struct mlx5_outbox_hdr hdr;
680 struct mlx5_conf_sqp_mbox_in {
681 struct mlx5_inbox_hdr hdr;
687 struct mlx5_conf_sqp_mbox_out {
688 struct mlx5_outbox_hdr hdr;
692 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
694 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
697 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
699 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
702 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
703 struct mlx5_core_qp *qp,
704 struct mlx5_create_qp_mbox_in *in,
706 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation,
707 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
708 struct mlx5_core_qp *qp);
709 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
710 struct mlx5_core_qp *qp);
711 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
712 struct mlx5_query_qp_mbox_out *out, int outlen);
713 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct,
714 struct mlx5_query_dct_mbox_out *out);
715 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct);
717 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
718 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
719 int mlx5_core_create_dct(struct mlx5_core_dev *dev,
720 struct mlx5_core_dct *dct,
721 struct mlx5_create_dct_mbox_in *in);
722 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev,
723 struct mlx5_core_dct *dct);
724 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
725 struct mlx5_core_qp *rq);
726 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
727 struct mlx5_core_qp *rq);
728 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
729 struct mlx5_core_qp *sq);
730 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
731 struct mlx5_core_qp *sq);
732 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
733 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
734 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
735 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
737 static inline const char *mlx5_qp_type_str(int type)
740 case MLX5_QP_ST_RC: return "RC";
741 case MLX5_QP_ST_UC: return "C";
742 case MLX5_QP_ST_UD: return "UD";
743 case MLX5_QP_ST_XRC: return "XRC";
744 case MLX5_QP_ST_MLX: return "MLX";
745 case MLX5_QP_ST_DCI: return "DCI";
746 case MLX5_QP_ST_QP0: return "QP0";
747 case MLX5_QP_ST_QP1: return "QP1";
748 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
749 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
750 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
751 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
752 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
753 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
754 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK";
755 default: return "Invalid transport type";
759 static inline const char *mlx5_qp_state_str(int state)
762 case MLX5_QP_STATE_RST:
764 case MLX5_QP_STATE_INIT:
766 case MLX5_QP_STATE_RTR:
768 case MLX5_QP_STATE_RTS:
770 case MLX5_QP_STATE_SQER:
772 case MLX5_QP_STATE_SQD:
774 case MLX5_QP_STATE_ERR:
776 case MLX5_QP_STATE_SQ_DRAINING:
777 return "SQ_DRAINING";
778 case MLX5_QP_STATE_SUSPENDED:
780 default: return "Invalid QP state";
784 #endif /* MLX5_QP_H */