sys/dev/mmc/host/dwmmc.c

   1 /*-
   2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * This software was developed by SRI International and the University of
   6  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   7  * ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /*
  32  * Synopsys DesignWare Mobile Storage Host Controller
  33  * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 #include <sys/param.h>
  40 #include <sys/systm.h>
  41 #include <sys/bus.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/malloc.h>
  45 #include <sys/rman.h>
  46 #include <sys/timeet.h>
  47 #include <sys/timetc.h>
  48
  49 #include <dev/mmc/bridge.h>
  50 #include <dev/mmc/mmcreg.h>
  51 #include <dev/mmc/mmcbrvar.h>
  52
  53 #include <dev/fdt/fdt_common.h>
  54 #include <dev/ofw/openfirm.h>
  55 #include <dev/ofw/ofw_bus.h>
  56 #include <dev/ofw/ofw_bus_subr.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/fdt.h>
  60 #include <machine/cpu.h>
  61 #include <machine/intr.h>
  62
  63 #include <dev/mmc/host/dwmmc.h>
  64
  65 #include "mmcbr_if.h"
  66
  67 #define dprintf(x, arg...)
  68
  69 #define READ4(_sc, _reg) \
  70         bus_read_4((_sc)->res[0], _reg)
  71 #define WRITE4(_sc, _reg, _val) \
  72         bus_write_4((_sc)->res[0], _reg, _val)
  73
  74 #define DIV_ROUND_UP(n, d)              (((n) + (d) - 1) / (d))
  75
  76 #define DWMMC_LOCK(_sc)                 mtx_lock(&(_sc)->sc_mtx)
  77 #define DWMMC_UNLOCK(_sc)               mtx_unlock(&(_sc)->sc_mtx)
  78 #define DWMMC_LOCK_INIT(_sc) \
  79         mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
  80             "dwmmc", MTX_DEF)
  81 #define DWMMC_LOCK_DESTROY(_sc)         mtx_destroy(&_sc->sc_mtx);
  82 #define DWMMC_ASSERT_LOCKED(_sc)        mtx_assert(&_sc->sc_mtx, MA_OWNED);
  83 #define DWMMC_ASSERT_UNLOCKED(_sc)      mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
  84
  85 #define PENDING_CMD     0x01
  86 #define PENDING_STOP    0x02
  87 #define CARD_INIT_DONE  0x04
  88
  89 #define DWMMC_DATA_ERR_FLAGS    (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \
  90                                 |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \
  91                                 |SDMMC_INTMASK_EBE)
  92 #define DWMMC_CMD_ERR_FLAGS     (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \
  93                                 |SDMMC_INTMASK_RE)
  94 #define DWMMC_ERR_FLAGS         (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \
  95                                 |SDMMC_INTMASK_HLE)
  96
  97 #define DES0_DIC        (1 << 1)
  98 #define DES0_LD         (1 << 2)
  99 #define DES0_FS         (1 << 3)
 100 #define DES0_CH         (1 << 4)
 101 #define DES0_ER         (1 << 5)
 102 #define DES0_CES        (1 << 30)
 103 #define DES0_OWN        (1 << 31)
 104
 105 #define DES1_BS1_MASK   0xfff
 106 #define DES1_BS1_SHIFT  0
 107
 108 struct idmac_desc {
 109         uint32_t        des0;   /* control */
 110         uint32_t        des1;   /* bufsize */
 111         uint32_t        des2;   /* buf1 phys addr */
 112         uint32_t        des3;   /* buf2 phys addr or next descr */
 113 };
 114
 115 #define DESC_COUNT      256
 116 #define DESC_SIZE       (sizeof(struct idmac_desc) * DESC_COUNT)
 117 #define DEF_MSIZE       0x2     /* Burst size of multiple transaction */
 118
 119 struct dwmmc_softc {
 120         struct resource         *res[2];
 121         bus_space_tag_t         bst;
 122         bus_space_handle_t      bsh;
 123         device_t                dev;
 124         void                    *intr_cookie;
 125         struct mmc_host         host;
 126         struct mtx              sc_mtx;
 127         struct mmc_request      *req;
 128         struct mmc_command      *curcmd;
 129         uint32_t                flags;
 130         uint32_t                hwtype;
 131         uint32_t                use_auto_stop;
 132
 133         bus_dma_tag_t           desc_tag;
 134         bus_dmamap_t            desc_map;
 135         struct idmac_desc       *desc_ring;
 136         bus_addr_t              desc_ring_paddr;
 137         bus_dma_tag_t           buf_tag;
 138         bus_dmamap_t            buf_map;
 139
 140         uint32_t                bus_busy;
 141         uint32_t                dto_rcvd;
 142         uint32_t                acd_rcvd;
 143         uint32_t                cmd_done;
 144         uint32_t                bus_hz;
 145         uint32_t                fifo_depth;
 146         uint32_t                num_slots;
 147         uint32_t                sdr_timing;
 148         uint32_t                ddr_timing;
 149 };
 150
 151 static void dwmmc_next_operation(struct dwmmc_softc *);
 152 static int dwmmc_setup_bus(struct dwmmc_softc *, int);
 153 static int dma_done(struct dwmmc_softc *, struct mmc_command *);
 154 static int dma_stop(struct dwmmc_softc *);
 155
 156 static struct resource_spec dwmmc_spec[] = {
 157         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 158         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 159         { -1, 0 }
 160 };
 161
 162 enum {
 163         HWTYPE_NONE,
 164         HWTYPE_ALTERA,
 165         HWTYPE_EXYNOS,
 166 };
 167
 168 #define HWTYPE_MASK             (0x0000ffff)
 169 #define HWFLAG_MASK             (0xffff << 16)
 170
 171 static struct ofw_compat_data compat_data[] = {
 172         {"altr,socfpga-dw-mshc",        HWTYPE_ALTERA},
 173         {"samsung,exynos5420-dw-mshc",  HWTYPE_EXYNOS},
 174         {NULL,                          HWTYPE_NONE},
 175 };
 176
 177 static void
 178 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 179 {
 180
 181         if (error != 0)
 182                 return;
 183         *(bus_addr_t *)arg = segs[0].ds_addr;
 184 }
 185
 186 static void
 187 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 188 {
 189         struct dwmmc_softc *sc;
 190         int idx;
 191
 192         if (error != 0)
 193                 return;
 194
 195         sc = arg;
 196
 197         dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len);
 198
 199         for (idx = 0; idx < nsegs; idx++) {
 200                 sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH);
 201                 sc->desc_ring[idx].des1 = segs[idx].ds_len;
 202                 sc->desc_ring[idx].des2 = segs[idx].ds_addr;
 203
 204                 if (idx == 0)
 205                         sc->desc_ring[idx].des0 |= DES0_FS;
 206
 207                 if (idx == (nsegs - 1)) {
 208                         sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH);
 209                         sc->desc_ring[idx].des0 |= DES0_LD;
 210                 }
 211         }
 212 }
 213
 214 static int
 215 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits)
 216 {
 217         int reg;
 218         int i;
 219
 220         reg = READ4(sc, SDMMC_CTRL);
 221         reg |= (reset_bits);
 222         WRITE4(sc, SDMMC_CTRL, reg);
 223
 224         /* Wait reset done */
 225         for (i = 0; i < 100; i++) {
 226                 if (!(READ4(sc, SDMMC_CTRL) & reset_bits))
 227                         return (0);
 228                 DELAY(10);
 229         };
 230
 231         device_printf(sc->dev, "Reset failed\n");
 232
 233         return (1);
 234 }
 235
 236 static int
 237 dma_setup(struct dwmmc_softc *sc)
 238 {
 239         int error;
 240         int nidx;
 241         int idx;
 242
 243         /*
 244          * Set up TX descriptor ring, descriptors, and dma maps.
 245          */
 246         error = bus_dma_tag_create(
 247             bus_get_dma_tag(sc->dev),   /* Parent tag. */
 248             4096, 0,                    /* alignment, boundary */
 249             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
 250             BUS_SPACE_MAXADDR,          /* highaddr */
 251             NULL, NULL,                 /* filter, filterarg */
 252             DESC_SIZE, 1,               /* maxsize, nsegments */
 253             DESC_SIZE,                  /* maxsegsize */
 254             0,                          /* flags */
 255             NULL, NULL,                 /* lockfunc, lockarg */
 256             &sc->desc_tag);
 257         if (error != 0) {
 258                 device_printf(sc->dev,
 259                     "could not create ring DMA tag.\n");
 260                 return (1);
 261         }
 262
 263         error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring,
 264             BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
 265             &sc->desc_map);
 266         if (error != 0) {
 267                 device_printf(sc->dev,
 268                     "could not allocate descriptor ring.\n");
 269                 return (1);
 270         }
 271
 272         error = bus_dmamap_load(sc->desc_tag, sc->desc_map,
 273             sc->desc_ring, DESC_SIZE, dwmmc_get1paddr,
 274             &sc->desc_ring_paddr, 0);
 275         if (error != 0) {
 276                 device_printf(sc->dev,
 277                     "could not load descriptor ring map.\n");
 278                 return (1);
 279         }
 280
 281         for (idx = 0; idx < DESC_COUNT; idx++) {
 282                 sc->desc_ring[idx].des0 = DES0_CH;
 283                 sc->desc_ring[idx].des1 = 0;
 284                 nidx = (idx + 1) % DESC_COUNT;
 285                 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \
 286                     (nidx * sizeof(struct idmac_desc));
 287         }
 288
 289         error = bus_dma_tag_create(
 290             bus_get_dma_tag(sc->dev),   /* Parent tag. */
 291             4096, 0,                    /* alignment, boundary */
 292             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
 293             BUS_SPACE_MAXADDR,          /* highaddr */
 294             NULL, NULL,                 /* filter, filterarg */
 295             DESC_COUNT*MMC_SECTOR_SIZE, /* maxsize */
 296             DESC_COUNT,                 /* nsegments */
 297             MMC_SECTOR_SIZE,            /* maxsegsize */
 298             0,                          /* flags */
 299             NULL, NULL,                 /* lockfunc, lockarg */
 300             &sc->buf_tag);
 301         if (error != 0) {
 302                 device_printf(sc->dev,
 303                     "could not create ring DMA tag.\n");
 304                 return (1);
 305         }
 306
 307         error = bus_dmamap_create(sc->buf_tag, 0,
 308             &sc->buf_map);
 309         if (error != 0) {
 310                 device_printf(sc->dev,
 311                     "could not create TX buffer DMA map.\n");
 312                 return (1);
 313         }
 314
 315         return (0);
 316 }
 317
 318 static void
 319 dwmmc_cmd_done(struct dwmmc_softc *sc)
 320 {
 321         struct mmc_command *cmd;
 322
 323         cmd = sc->curcmd;
 324         if (cmd == NULL)
 325                 return;
 326
 327         if (cmd->flags & MMC_RSP_PRESENT) {
 328                 if (cmd->flags & MMC_RSP_136) {
 329                         cmd->resp[3] = READ4(sc, SDMMC_RESP0);
 330                         cmd->resp[2] = READ4(sc, SDMMC_RESP1);
 331                         cmd->resp[1] = READ4(sc, SDMMC_RESP2);
 332                         cmd->resp[0] = READ4(sc, SDMMC_RESP3);
 333                 } else {
 334                         cmd->resp[3] = 0;
 335                         cmd->resp[2] = 0;
 336                         cmd->resp[1] = 0;
 337                         cmd->resp[0] = READ4(sc, SDMMC_RESP0);
 338                 }
 339         }
 340 }
 341
 342 static void
 343 dwmmc_tasklet(struct dwmmc_softc *sc)
 344 {
 345         struct mmc_command *cmd;
 346
 347         cmd = sc->curcmd;
 348         if (cmd == NULL)
 349                 return;
 350
 351         if (cmd->error != MMC_ERR_NONE) {
 352                 dwmmc_next_operation(sc);
 353         } else if (!cmd->data && sc->cmd_done) {
 354                 dwmmc_next_operation(sc);
 355         } else if (cmd->data && sc->dto_rcvd) {
 356                 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
 357                      cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
 358                      sc->use_auto_stop) {
 359                         if (sc->acd_rcvd)
 360                                 dwmmc_next_operation(sc);
 361                 } else {
 362                         dwmmc_next_operation(sc);
 363                 }
 364         }
 365 }
 366
 367 static void
 368 dwmmc_intr(void *arg)
 369 {
 370         struct mmc_command *cmd;
 371         struct dwmmc_softc *sc;
 372         uint32_t reg;
 373
 374         sc = arg;
 375
 376         DWMMC_LOCK(sc);
 377
 378         cmd = sc->curcmd;
 379
 380         /* First handle SDMMC controller interrupts */
 381         reg = READ4(sc, SDMMC_MINTSTS);
 382         if (reg) {
 383                 dprintf("%s 0x%08x\n", __func__, reg);
 384
 385                 if (reg & DWMMC_CMD_ERR_FLAGS) {
 386                         WRITE4(sc, SDMMC_RINTSTS, DWMMC_CMD_ERR_FLAGS);
 387                         dprintf("cmd err 0x%08x cmd 0x%08x\n",
 388                                 reg, cmd->opcode);
 389                         cmd->error = MMC_ERR_TIMEOUT;
 390                 }
 391
 392                 if (reg & DWMMC_DATA_ERR_FLAGS) {
 393                         WRITE4(sc, SDMMC_RINTSTS, DWMMC_DATA_ERR_FLAGS);
 394                         dprintf("data err 0x%08x cmd 0x%08x\n",
 395                                 reg, cmd->opcode);
 396                         cmd->error = MMC_ERR_FAILED;
 397
 398                         dma_done(sc, cmd);
 399                         dma_stop(sc);
 400                         DWMMC_UNLOCK(sc);
 401                         return;
 402                 }
 403
 404                 if (reg & SDMMC_INTMASK_CMD_DONE) {
 405                         dwmmc_cmd_done(sc);
 406                         sc->cmd_done = 1;
 407                         WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CMD_DONE);
 408                 }
 409
 410                 if (reg & SDMMC_INTMASK_ACD) {
 411                         sc->acd_rcvd = 1;
 412                         WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_ACD);
 413                 }
 414
 415                 if (reg & SDMMC_INTMASK_DTO) {
 416                         sc->dto_rcvd = 1;
 417                         WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_DTO);
 418                 }
 419
 420                 if (reg & SDMMC_INTMASK_CD) {
 421                         /* XXX: Handle card detect */
 422                         WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CD);
 423                 }
 424         }
 425
 426         /* Now handle DMA interrupts */
 427         reg = READ4(sc, SDMMC_IDSTS);
 428         if (reg) {
 429                 dprintf("dma intr 0x%08x\n", reg);
 430                 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) {
 431                         WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
 432                                                  SDMMC_IDINTEN_RI));
 433                         WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
 434                         dma_done(sc, cmd);
 435                 }
 436         }
 437
 438         dwmmc_tasklet(sc);
 439
 440         DWMMC_UNLOCK(sc);
 441 }
 442
 443 static int
 444 parse_fdt(struct dwmmc_softc *sc)
 445 {
 446         pcell_t dts_value[3];
 447         phandle_t node;
 448         int len;
 449
 450         if ((node = ofw_bus_get_node(sc->dev)) == -1)
 451                 return (ENXIO);
 452
 453         /* fifo-depth */
 454         if ((len = OF_getproplen(node, "fifo-depth")) <= 0)
 455                 return (ENXIO);
 456         OF_getencprop(node, "fifo-depth", dts_value, len);
 457         sc->fifo_depth = dts_value[0];
 458
 459         /* num-slots */
 460         if ((len = OF_getproplen(node, "num-slots")) <= 0)
 461                 return (ENXIO);
 462         OF_getencprop(node, "num-slots", dts_value, len);
 463         sc->num_slots = dts_value[0];
 464
 465         /*
 466          * We need some platform-specific code to know
 467          * what the clock is supplied for our device.
 468          * For now rely on the value specified in FDT.
 469          */
 470         if ((len = OF_getproplen(node, "bus-frequency")) <= 0)
 471                 return (ENXIO);
 472         OF_getencprop(node, "bus-frequency", dts_value, len);
 473         sc->bus_hz = dts_value[0];
 474
 475         /*
 476          * Platform-specific stuff
 477          * XXX: Move to separate file
 478          */
 479
 480         if ((sc->hwtype & HWTYPE_MASK) != HWTYPE_EXYNOS)
 481                 return (0);
 482
 483         if ((len = OF_getproplen(node, "samsung,dw-mshc-ciu-div")) <= 0)
 484                 return (ENXIO);
 485         OF_getencprop(node, "samsung,dw-mshc-ciu-div", dts_value, len);
 486         sc->sdr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
 487         sc->ddr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
 488
 489         if ((len = OF_getproplen(node, "samsung,dw-mshc-sdr-timing")) <= 0)
 490                 return (ENXIO);
 491         OF_getencprop(node, "samsung,dw-mshc-sdr-timing", dts_value, len);
 492         sc->sdr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
 493                           (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
 494
 495         if ((len = OF_getproplen(node, "samsung,dw-mshc-ddr-timing")) <= 0)
 496                 return (ENXIO);
 497         OF_getencprop(node, "samsung,dw-mshc-ddr-timing", dts_value, len);
 498         sc->ddr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
 499                           (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
 500
 501         return (0);
 502 }
 503
 504 static int
 505 dwmmc_probe(device_t dev)
 506 {
 507         uintptr_t hwtype;
 508
 509         if (!ofw_bus_status_okay(dev))
 510                 return (ENXIO);
 511
 512         hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 513         if (hwtype == HWTYPE_NONE)
 514                 return (ENXIO);
 515
 516         device_set_desc(dev, "Synopsys DesignWare Mobile "
 517                                 "Storage Host Controller");
 518         return (BUS_PROBE_DEFAULT);
 519 }
 520
 521 static int
 522 dwmmc_attach(device_t dev)
 523 {
 524         struct dwmmc_softc *sc;
 525         device_t child;
 526         int error;
 527         int slot;
 528
 529         sc = device_get_softc(dev);
 530
 531         sc->dev = dev;
 532         sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
 533
 534         /* Why not to use Auto Stop? It save a hundred of irq per second */
 535         sc->use_auto_stop = 1;
 536
 537         error = parse_fdt(sc);
 538         if (error != 0) {
 539                 device_printf(dev, "Can't get FDT property.\n");
 540                 return (ENXIO);
 541         }
 542
 543         DWMMC_LOCK_INIT(sc);
 544
 545         if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) {
 546                 device_printf(dev, "could not allocate resources\n");
 547                 return (ENXIO);
 548         }
 549
 550         /* Memory interface */
 551         sc->bst = rman_get_bustag(sc->res[0]);
 552         sc->bsh = rman_get_bushandle(sc->res[0]);
 553
 554         /* Setup interrupt handler. */
 555         error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
 556             NULL, dwmmc_intr, sc, &sc->intr_cookie);
 557         if (error != 0) {
 558                 device_printf(dev, "could not setup interrupt handler.\n");
 559                 return (ENXIO);
 560         }
 561
 562         device_printf(dev, "Hardware version ID is %04x\n",
 563                 READ4(sc, SDMMC_VERID) & 0xffff);
 564
 565         WRITE4(sc, EMMCP_MPSBEGIN0, 0);
 566         WRITE4(sc, EMMCP_SEND0, 0);
 567         WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
 568                                  MPSCTRL_SECURE_WRITE_BIT |
 569                                  MPSCTRL_NON_SECURE_READ_BIT |
 570                                  MPSCTRL_NON_SECURE_WRITE_BIT |
 571                                  MPSCTRL_VALID));
 572
 573         /* XXX: we support operation for slot index 0 only */
 574         slot = 0;
 575         WRITE4(sc, SDMMC_PWREN, (1 << slot));
 576
 577         /* Reset all */
 578         if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET |
 579                                   SDMMC_CTRL_FIFO_RESET |
 580                                   SDMMC_CTRL_DMA_RESET)))
 581                 return (ENXIO);
 582
 583         dwmmc_setup_bus(sc, sc->host.f_min);
 584
 585         if (dma_setup(sc))
 586                 return (ENXIO);
 587
 588         /* Install desc base */
 589         WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
 590
 591         /* Enable DMA interrupts */
 592         WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
 593         WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |
 594                                    SDMMC_IDINTEN_RI |
 595                                    SDMMC_IDINTEN_TI));
 596
 597         /* Clear and disable interrups for a while */
 598         WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
 599         WRITE4(sc, SDMMC_INTMASK, 0);
 600
 601         /* Maximum timeout */
 602         WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
 603
 604         /* Enable interrupts */
 605         WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
 606         WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE |
 607                                    SDMMC_INTMASK_DTO |
 608                                    SDMMC_INTMASK_ACD |
 609                                    SDMMC_INTMASK_TXDR |
 610                                    SDMMC_INTMASK_RXDR |
 611                                    DWMMC_ERR_FLAGS |
 612                                    SDMMC_INTMASK_CD));
 613         WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);
 614
 615         sc->host.f_min = 400000;
 616         sc->host.f_max = 200000000;
 617         sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
 618         sc->host.caps = MMC_CAP_4_BIT_DATA;
 619
 620         child = device_add_child(dev, "mmc", 0);
 621         return (bus_generic_attach(dev));
 622 }
 623
 624 static int
 625 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq)
 626 {
 627         int tout;
 628         int div;
 629
 630         if (freq == 0) {
 631                 WRITE4(sc, SDMMC_CLKENA, 0);
 632                 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
 633                         SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
 634
 635                 tout = 1000;
 636                 do {
 637                         if (tout-- < 0) {
 638                                 device_printf(sc->dev, "Failed update clk\n");
 639                                 return (1);
 640                         }
 641                 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
 642
 643                 return (0);
 644         }
 645
 646         WRITE4(sc, SDMMC_CLKENA, 0);
 647         WRITE4(sc, SDMMC_CLKSRC, 0);
 648
 649         div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0;
 650
 651         WRITE4(sc, SDMMC_CLKDIV, div);
 652         WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
 653                         SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
 654
 655         tout = 1000;
 656         do {
 657                 if (tout-- < 0) {
 658                         device_printf(sc->dev, "Failed to update clk");
 659                         return (1);
 660                 }
 661         } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
 662
 663         WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP));
 664         WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA |
 665                         SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START);
 666
 667         tout = 1000;
 668         do {
 669                 if (tout-- < 0) {
 670                         device_printf(sc->dev, "Failed to enable clk\n");
 671                         return (1);
 672                 }
 673         } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
 674
 675         return (0);
 676 }
 677
 678 static int
 679 dwmmc_update_ios(device_t brdev, device_t reqdev)
 680 {
 681         struct dwmmc_softc *sc;
 682         struct mmc_ios *ios;
 683
 684         sc = device_get_softc(brdev);
 685         ios = &sc->host.ios;
 686
 687         dprintf("Setting up clk %u bus_width %d\n",
 688                 ios->clock, ios->bus_width);
 689
 690         dwmmc_setup_bus(sc, ios->clock);
 691
 692         if (ios->bus_width == bus_width_8)
 693                 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
 694         else if (ios->bus_width == bus_width_4)
 695                 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);
 696         else
 697                 WRITE4(sc, SDMMC_CTYPE, 0);
 698
 699         if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) {
 700                 /* XXX: take care about DDR or SDR use here */
 701                 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);
 702         }
 703
 704         /*
 705          * XXX: take care about DDR bit
 706          *
 707          * reg = READ4(sc, SDMMC_UHS_REG);
 708          * reg |= (SDMMC_UHS_REG_DDR);
 709          * WRITE4(sc, SDMMC_UHS_REG, reg);
 710          */
 711
 712         return (0);
 713 }
 714
 715 static int
 716 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd)
 717 {
 718         struct mmc_data *data;
 719
 720         data = cmd->data;
 721
 722         if (data->flags & MMC_DATA_WRITE)
 723                 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
 724                         BUS_DMASYNC_POSTWRITE);
 725         else
 726                 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
 727                         BUS_DMASYNC_POSTREAD);
 728
 729         bus_dmamap_unload(sc->buf_tag, sc->buf_map);
 730
 731         return (0);
 732 }
 733
 734 static int
 735 dma_stop(struct dwmmc_softc *sc)
 736 {
 737         int reg;
 738
 739         reg = READ4(sc, SDMMC_CTRL);
 740         reg &= ~(SDMMC_CTRL_USE_IDMAC);
 741         reg |= (SDMMC_CTRL_DMA_RESET);
 742         WRITE4(sc, SDMMC_CTRL, reg);
 743
 744         reg = READ4(sc, SDMMC_BMOD);
 745         reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB);
 746         reg |= (SDMMC_BMOD_SWR);
 747         WRITE4(sc, SDMMC_BMOD, reg);
 748
 749         return (0);
 750 }
 751
 752 static int
 753 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
 754 {
 755         struct mmc_data *data;
 756         int len;
 757         int err;
 758         int reg;
 759
 760         data = cmd->data;
 761         len = data->len;
 762
 763         reg = READ4(sc, SDMMC_INTMASK);
 764         reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR);
 765         WRITE4(sc, SDMMC_INTMASK, reg);
 766
 767         err = bus_dmamap_load(sc->buf_tag, sc->buf_map,
 768                 data->data, data->len, dwmmc_ring_setup,
 769                 sc, BUS_DMA_NOWAIT);
 770         if (err != 0)
 771                 panic("dmamap_load failed\n");
 772
 773         if (data->flags & MMC_DATA_WRITE)
 774                 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
 775                         BUS_DMASYNC_PREWRITE);
 776         else
 777                 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
 778                         BUS_DMASYNC_PREREAD);
 779
 780         reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);
 781         reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
 782         reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
 783
 784         WRITE4(sc, SDMMC_FIFOTH, reg);
 785         wmb();
 786
 787         reg = READ4(sc, SDMMC_CTRL);
 788         reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE);
 789         WRITE4(sc, SDMMC_CTRL, reg);
 790         wmb();
 791
 792         reg = READ4(sc, SDMMC_BMOD);
 793         reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB);
 794         WRITE4(sc, SDMMC_BMOD, reg);
 795
 796         /* Start */
 797         WRITE4(sc, SDMMC_PLDMND, 1);
 798
 799         return (0);
 800 }
 801
 802 static void
 803 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd)
 804 {
 805         struct mmc_data *data;
 806         uint32_t blksz;
 807         uint32_t cmdr;
 808
 809         sc->curcmd = cmd;
 810         data = cmd->data;
 811
 812         /* XXX Upper layers don't always set this */
 813         cmd->mrq = sc->req;
 814
 815         /* Begin setting up command register. */
 816
 817         cmdr = cmd->opcode;
 818
 819         dprintf("cmd->opcode 0x%08x\n", cmd->opcode);
 820
 821         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 822             cmd->opcode == MMC_GO_IDLE_STATE ||
 823             cmd->opcode == MMC_GO_INACTIVE_STATE)
 824                 cmdr |= SDMMC_CMD_STOP_ABORT;
 825         else if (cmd->opcode != MMC_SEND_STATUS && data)
 826                 cmdr |= SDMMC_CMD_WAIT_PRVDATA;
 827
 828         /* Set up response handling. */
 829         if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) {
 830                 cmdr |= SDMMC_CMD_RESP_EXP;
 831                 if (cmd->flags & MMC_RSP_136)
 832                         cmdr |= SDMMC_CMD_RESP_LONG;
 833         }
 834
 835         if (cmd->flags & MMC_RSP_CRC)
 836                 cmdr |= SDMMC_CMD_RESP_CRC;
 837
 838         /*
 839          * XXX: Not all platforms want this.
 840          */
 841         cmdr |= SDMMC_CMD_USE_HOLD_REG;
 842
 843         if ((sc->flags & CARD_INIT_DONE) == 0) {
 844                 sc->flags |= (CARD_INIT_DONE);
 845                 cmdr |= SDMMC_CMD_SEND_INIT;
 846         }
 847
 848         if (data) {
 849                 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
 850                      cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
 851                      sc->use_auto_stop)
 852                         cmdr |= SDMMC_CMD_SEND_ASTOP;
 853
 854                 cmdr |= SDMMC_CMD_DATA_EXP;
 855                 if (data->flags & MMC_DATA_STREAM)
 856                         cmdr |= SDMMC_CMD_MODE_STREAM;
 857                 if (data->flags & MMC_DATA_WRITE)
 858                         cmdr |= SDMMC_CMD_DATA_WRITE;
 859
 860                 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
 861                 WRITE4(sc, SDMMC_BYTCNT, data->len);
 862                 blksz = (data->len < MMC_SECTOR_SIZE) ? \
 863                          data->len : MMC_SECTOR_SIZE;
 864                 WRITE4(sc, SDMMC_BLKSIZ, blksz);
 865
 866                 dma_prepare(sc, cmd);
 867                 wmb();
 868         }
 869
 870         dprintf("cmdr 0x%08x\n", cmdr);
 871
 872         WRITE4(sc, SDMMC_CMDARG, cmd->arg);
 873         wmb();
 874         WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START);
 875 };
 876
 877 static void
 878 dwmmc_next_operation(struct dwmmc_softc *sc)
 879 {
 880         struct mmc_request *req;
 881
 882         req = sc->req;
 883         if (req == NULL)
 884                 return;
 885
 886         sc->acd_rcvd = 0;
 887         sc->dto_rcvd = 0;
 888         sc->cmd_done = 0;
 889
 890         /*
 891          * XXX: Wait until card is still busy.
 892          * We do need this to prevent data timeouts,
 893          * mostly caused by multi-block write command
 894          * followed by single-read.
 895          */
 896         while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))
 897                 continue;
 898
 899         if (sc->flags & PENDING_CMD) {
 900                 sc->flags &= ~PENDING_CMD;
 901                 dwmmc_start_cmd(sc, req->cmd);
 902                 return;
 903         } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) {
 904                 sc->flags &= ~PENDING_STOP;
 905                 dwmmc_start_cmd(sc, req->stop);
 906                 return;
 907         }
 908
 909         sc->req = NULL;
 910         sc->curcmd = NULL;
 911         req->done(req);
 912 }
 913
 914 static int
 915 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req)
 916 {
 917         struct dwmmc_softc *sc;
 918
 919         sc = device_get_softc(brdev);
 920
 921         dprintf("%s\n", __func__);
 922
 923         DWMMC_LOCK(sc);
 924
 925         if (sc->req != NULL) {
 926                 DWMMC_UNLOCK(sc);
 927                 return (EBUSY);
 928         }
 929
 930         sc->req = req;
 931         sc->flags |= PENDING_CMD;
 932         if (sc->req->stop)
 933                 sc->flags |= PENDING_STOP;
 934         dwmmc_next_operation(sc);
 935
 936         DWMMC_UNLOCK(sc);
 937         return (0);
 938 }
 939
 940 static int
 941 dwmmc_get_ro(device_t brdev, device_t reqdev)
 942 {
 943
 944         dprintf("%s\n", __func__);
 945
 946         return (0);
 947 }
 948
 949 static int
 950 dwmmc_acquire_host(device_t brdev, device_t reqdev)
 951 {
 952         struct dwmmc_softc *sc;
 953
 954         sc = device_get_softc(brdev);
 955
 956         DWMMC_LOCK(sc);
 957         while (sc->bus_busy)
 958                 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5);
 959         sc->bus_busy++;
 960         DWMMC_UNLOCK(sc);
 961         return (0);
 962 }
 963
 964 static int
 965 dwmmc_release_host(device_t brdev, device_t reqdev)
 966 {
 967         struct dwmmc_softc *sc;
 968
 969         sc = device_get_softc(brdev);
 970
 971         DWMMC_LOCK(sc);
 972         sc->bus_busy--;
 973         wakeup(sc);
 974         DWMMC_UNLOCK(sc);
 975         return (0);
 976 }
 977
 978 static int
 979 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
 980 {
 981         struct dwmmc_softc *sc;
 982
 983         sc = device_get_softc(bus);
 984
 985         switch (which) {
 986         default:
 987                 return (EINVAL);
 988         case MMCBR_IVAR_BUS_MODE:
 989                 *(int *)result = sc->host.ios.bus_mode;
 990                 break;
 991         case MMCBR_IVAR_BUS_WIDTH:
 992                 *(int *)result = sc->host.ios.bus_width;
 993                 break;
 994         case MMCBR_IVAR_CHIP_SELECT:
 995                 *(int *)result = sc->host.ios.chip_select;
 996                 break;
 997         case MMCBR_IVAR_CLOCK:
 998                 *(int *)result = sc->host.ios.clock;
 999                 break;
1000         case MMCBR_IVAR_F_MIN:
1001                 *(int *)result = sc->host.f_min;
1002                 break;
1003         case MMCBR_IVAR_F_MAX:
1004                 *(int *)result = sc->host.f_max;
1005                 break;
1006         case MMCBR_IVAR_HOST_OCR:
1007                 *(int *)result = sc->host.host_ocr;
1008                 break;
1009         case MMCBR_IVAR_MODE:
1010                 *(int *)result = sc->host.mode;
1011                 break;
1012         case MMCBR_IVAR_OCR:
1013                 *(int *)result = sc->host.ocr;
1014                 break;
1015         case MMCBR_IVAR_POWER_MODE:
1016                 *(int *)result = sc->host.ios.power_mode;
1017                 break;
1018         case MMCBR_IVAR_VDD:
1019                 *(int *)result = sc->host.ios.vdd;
1020                 break;
1021         case MMCBR_IVAR_CAPS:
1022                 sc->host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
1023                 *(int *)result = sc->host.caps;
1024                 break;
1025         case MMCBR_IVAR_MAX_DATA:
1026                 *(int *)result = DESC_COUNT;
1027         }
1028         return (0);
1029 }
1030
1031 static int
1032 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1033 {
1034         struct dwmmc_softc *sc;
1035
1036         sc = device_get_softc(bus);
1037
1038         switch (which) {
1039         default:
1040                 return (EINVAL);
1041         case MMCBR_IVAR_BUS_MODE:
1042                 sc->host.ios.bus_mode = value;
1043                 break;
1044         case MMCBR_IVAR_BUS_WIDTH:
1045                 sc->host.ios.bus_width = value;
1046                 break;
1047         case MMCBR_IVAR_CHIP_SELECT:
1048                 sc->host.ios.chip_select = value;
1049                 break;
1050         case MMCBR_IVAR_CLOCK:
1051                 sc->host.ios.clock = value;
1052                 break;
1053         case MMCBR_IVAR_MODE:
1054                 sc->host.mode = value;
1055                 break;
1056         case MMCBR_IVAR_OCR:
1057                 sc->host.ocr = value;
1058                 break;
1059         case MMCBR_IVAR_POWER_MODE:
1060                 sc->host.ios.power_mode = value;
1061                 break;
1062         case MMCBR_IVAR_VDD:
1063                 sc->host.ios.vdd = value;
1064                 break;
1065         /* These are read-only */
1066         case MMCBR_IVAR_CAPS:
1067         case MMCBR_IVAR_HOST_OCR:
1068         case MMCBR_IVAR_F_MIN:
1069         case MMCBR_IVAR_F_MAX:
1070         case MMCBR_IVAR_MAX_DATA:
1071                 return (EINVAL);
1072         }
1073         return (0);
1074 }
1075
1076 static device_method_t dwmmc_methods[] = {
1077         DEVMETHOD(device_probe,         dwmmc_probe),
1078         DEVMETHOD(device_attach,        dwmmc_attach),
1079
1080         /* Bus interface */
1081         DEVMETHOD(bus_read_ivar,        dwmmc_read_ivar),
1082         DEVMETHOD(bus_write_ivar,       dwmmc_write_ivar),
1083
1084         /* mmcbr_if */
1085         DEVMETHOD(mmcbr_update_ios,     dwmmc_update_ios),
1086         DEVMETHOD(mmcbr_request,        dwmmc_request),
1087         DEVMETHOD(mmcbr_get_ro,         dwmmc_get_ro),
1088         DEVMETHOD(mmcbr_acquire_host,   dwmmc_acquire_host),
1089         DEVMETHOD(mmcbr_release_host,   dwmmc_release_host),
1090
1091         DEVMETHOD_END
1092 };
1093
1094 static driver_t dwmmc_driver = {
1095         "dwmmc",
1096         dwmmc_methods,
1097         sizeof(struct dwmmc_softc),
1098 };
1099
1100 static devclass_t dwmmc_devclass;
1101
1102 DRIVER_MODULE(dwmmc, simplebus, dwmmc_driver, dwmmc_devclass, 0, 0);
1103