2 * SPDX-License-Identifier: Beerware
4 * ----------------------------------------------------------------------------
5 * "THE BEER-WARE LICENSE" (Revision 42):
6 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
7 * can do whatever you want with this stuff. If we meet some day, and you think
8 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
9 * ----------------------------------------------------------------------------
13 * Driver for Siemens reference design card "Easy321-R1".
15 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
18 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
21 * The FALC54 and MUNICH32X have far too many registers and weird modes for
22 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
23 * you will (badly!) need the documentation anyway if you want to mess with
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Stuff to describe the MUNIC32X and FALC54 chips.
34 #define M32_CHAN 32 /* We have 32 channels */
35 #define M32_TS 32 /* We have 32 timeslots */
37 #define NG_MN_NODE_TYPE "mn"
39 #include <sys/param.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
44 #include <sys/systm.h>
45 #include <sys/malloc.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
51 #include <machine/bus.h>
52 #include <machine/resource.h>
59 #include <netgraph/ng_message.h>
60 #include <netgraph/netgraph.h>
63 static int mn_maxlatency = 1000;
64 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
66 "The number of milliseconds a packet is allowed to spend in the output queue. "
67 "If the output queue is longer than this number of milliseconds when the packet "
68 "arrives for output, the packet will be dropped."
72 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
76 /* From: PEB 20321 data sheet, p187, table 22 */
78 u_int32_t conf, cmd, stat, imask;
79 u_int32_t fill10, piqba, piql, fill1c;
80 u_int32_t mode1, mode2, ccba, txpoll;
81 u_int32_t tiqba, tiql, riqba, riql;
82 u_int32_t lconf, lccba, fill48, ltran;
83 u_int32_t ltiqba, ltiql, lriqba, lriql;
84 u_int32_t lreg0, lreg1, lreg2, lreg3;
85 u_int32_t lreg4, lreg5, lre6, lstat;
86 u_int32_t gpdir, gpdata, gpod, fill8c;
87 u_int32_t ssccon, sscbr, ssctb, sscrb;
88 u_int32_t ssccse, sscim, fillab, fillac;
89 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
91 u_int32_t iomtmo, iomrmo, filld8, filldc;
92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
96 /* From: PEB 2254 data sheet, p80, table 10 */
99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
106 u_int8_t lim2, fill39[7];
111 u_int8_t dec, fill61, test2, fill63[5];
116 /* From: PEB 2254 data sheet, p117, table 10 */
119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
126 u_int8_t lim2, fill39[7];
128 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
129 u_int16_t fec, cvc, cec1, ebc;
130 u_int16_t cec2, cec3;
131 u_int8_t rsa4, rsa5, rsa6, rsa7;
132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
138 /* Transmit & receive descriptors */
143 u_int32_t status; /* only used for receive */
144 struct mbuf *m; /* software use only */
145 struct trxd *vnext; /* software use only */
148 /* Channel specification */
159 u_int32_t reserve1[2];
160 u_int32_t ts[M32_TS];
161 struct cspec cs[M32_CHAN];
162 vm_offset_t crxd[M32_CHAN];
163 vm_offset_t ctxd[M32_CHAN];
169 static int mn_probe(device_t self);
170 static int mn_attach(device_t self);
171 static void mn_create_channel(struct mn_softc *sc, int chan);
172 static int mn_reset(struct mn_softc *sc);
173 static struct trxd * mn_alloc_desc(void);
174 static void mn_free_desc(struct trxd *dp);
175 static void mn_intr(void *xsc);
176 static u_int32_t mn_parse_ts(const char *s, int *nbit);
178 static void m32_dump(struct mn_softc *sc);
179 static void f54_dump(struct mn_softc *sc);
180 static void mn_fmt_ts(char *p, u_int32_t ts);
182 static void f54_init(struct mn_softc *sc);
184 static ng_constructor_t ngmn_constructor;
185 static ng_rcvmsg_t ngmn_rcvmsg;
186 static ng_shutdown_t ngmn_shutdown;
187 static ng_newhook_t ngmn_newhook;
188 static ng_connect_t ngmn_connect;
189 static ng_rcvdata_t ngmn_rcvdata;
190 static ng_disconnect_t ngmn_disconnect;
192 static struct ng_type mntypestruct = {
193 .version = NG_ABI_VERSION,
194 .name = NG_MN_NODE_TYPE,
195 .constructor = ngmn_constructor,
196 .rcvmsg = ngmn_rcvmsg,
197 .shutdown = ngmn_shutdown,
198 .newhook = ngmn_newhook,
199 .connect = ngmn_connect,
200 .rcvdata = ngmn_rcvdata,
201 .disconnect = ngmn_disconnect,
204 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
209 enum {DOWN, UP} state;
214 struct trxd *r1, *rl;
215 struct trxd *x1, *xl;
226 u_long dribble_error;
229 u_long overflow_error;
238 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
243 struct resource *irq;
245 enum framing framing;
248 vm_offset_t m0p, m1p;
249 struct m32xreg *m32x;
250 struct f54wreg *f54w;
251 struct f54rreg *f54r;
252 struct m32_mem m32_mem;
253 u_int32_t tiqb[NIQB];
254 u_int32_t riqb[NIQB];
255 u_int32_t piqb[NIQB];
256 u_int32_t ltiqb[NIQB];
257 u_int32_t lriqb[NIQB];
259 u_int32_t falc_irq, falc_state, framer_state;
260 struct schan *ch[M32_CHAN];
261 char nodename[NG_NODESIZ];
274 ngmn_constructor(node_p node)
281 ngmn_shutdown(node_p nodep)
288 ngmn_config(node_p node, char *set, char *ret)
291 enum framing wframing;
293 sc = NG_NODE_PRIVATE(node);
296 if (!strncmp(set, "line ", 5)) {
297 wframing = sc->framing;
298 if (!strcmp(set, "line e1")) {
300 } else if (!strcmp(set, "line e1u")) {
303 strcat(ret, "ENOGROK\n");
306 if (wframing == sc->framing)
308 if (sc->nhooks > 0) {
309 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
312 sc->framing = wframing;
319 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
320 strcat(ret, "ENOGROK\n");
328 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
331 struct ng_mesg *resp = NULL;
337 NGI_GET_MSG(item, msg);
338 sc = NG_NODE_PRIVATE(node);
340 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
346 if (msg->header.cmd != NGM_TEXT_CONFIG &&
347 msg->header.cmd != NGM_TEXT_STATUS) {
353 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
361 if (msg->header.arglen)
362 s = (char *)msg->data;
365 r = (char *)resp->data;
368 if (msg->header.cmd == NGM_TEXT_CONFIG) {
369 ngmn_config(node, s, r);
370 resp->header.arglen = strlen(r) + 1;
371 NG_RESPOND_MSG(i, node, item, resp);
376 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
377 "\40LOS\37AIS\36LFA\35RRA"
378 "\34AUXP\33NMF\32LMFA\31frs0.0"
379 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
380 "\24TS16LFA\23frs1.2\22XLS\21XLO"
381 "\20RS1\17rsw.6\16RRA\15RY0"
382 "\14RY1\13RY2\12RY3\11RY4"
383 "\10SI1\7SI2\6rsp.5\5rsp.4"
384 "\4rsp.3\3RSIF\2RS13\1RS15");
385 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
386 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
388 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
389 "\40LOS\37AIS\36LFA\35RRA"
390 "\34AUXP\33NMF\32LMFA\31frs0.0"
391 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
392 "\24TS16LFA\23frs1.2\22XLS\21XLO"
393 "\20RS1\17rsw.6\16RRA\15RY0"
394 "\14RY1\13RY2\12RY3\11RY4"
395 "\10SI1\7SI2\6rsp.5\5rsp.4"
396 "\4rsp.3\3RSIF\2RS13\1RS15");
397 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
398 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
399 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
400 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
401 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
402 for (i = 0; i < M32_CHAN; i++) {
407 pos += sprintf(r + pos, " Chan %d <%s> ",
408 i, NG_HOOK_NAME(sch->hook));
410 pos += sprintf(r + pos, " Last Rx: ");
412 pos += sprintf(r + pos, "%lu s",
413 (unsigned long)(time_second - sch->last_recv));
415 pos += sprintf(r + pos, "never");
417 pos += sprintf(r + pos, ", last RxErr: ");
419 pos += sprintf(r + pos, "%lu s",
420 (unsigned long)(time_second - sch->last_rxerr));
422 pos += sprintf(r + pos, "never");
424 pos += sprintf(r + pos, ", last Tx: ");
426 pos += sprintf(r + pos, "%lu s\n",
427 (unsigned long)(time_second - sch->last_xmit));
429 pos += sprintf(r + pos, "never\n");
431 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
432 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
433 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
434 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
435 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
436 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
437 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
439 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
440 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
441 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
442 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
445 resp->header.arglen = pos + 1;
447 /* Take care of synchronous response, if any */
448 NG_RESPOND_MSG(i, node, item, resp);
454 ngmn_newhook(node_p node, hook_p hook, const char *name)
460 sc = NG_NODE_PRIVATE(node);
462 if (name[0] != 't' || name[1] != 's')
465 ts = mn_parse_ts(name + 2, &nbit);
466 printf("%d bits %x\n", nbit, ts);
467 if (sc->framing == E1 && (ts & 1))
469 if (sc->framing == E1U && nbit != 32)
473 if (sc->framing == E1)
478 mn_create_channel(sc, chan);
479 else if (sc->ch[chan]->state == UP)
481 sc->ch[chan]->ts = ts;
482 sc->ch[chan]->hook = hook;
483 sc->ch[chan]->tx_limit = nbit * 8;
484 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
490 static struct trxd *mn_desc_free;
499 mn_desc_free = dp->vnext;
501 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
506 mn_free_desc(struct trxd *dp)
508 dp->vnext = mn_desc_free;
513 mn_parse_ts(const char *s, int *nbit)
523 i = strtol(s, &p, 0);
526 while (j != -1 && j < i) {
536 } else if (*p == '-') {
551 mn_fmt_ts(char *p, u_int32_t ts)
558 for (j = 0; j < 32; j++) {
559 if (!(ts & (1 << j)))
561 sprintf(p, "%s%d", s, j);
564 if (!(ts & (1 << (j+1))))
567 if (!(ts & (1 << (j+1))))
569 sprintf(p, "-%d", j);
581 ngmn_rcvdata(hook_p hook, item_p item)
584 struct trxd *dp, *dp2;
587 int chan, pitch, len;
590 sch = NG_HOOK_PRIVATE(hook);
594 if (sch->state != UP) {
599 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
607 dp2 = sc->ch[chan]->xl;
608 len = m->m_pkthdr.len;
610 dp = mn_alloc_desc();
614 sc->ch[chan]->xl = dp2;
621 sc->ch[chan]->xl->vnext = NULL;
624 dp->data = vtophys(m2->m_data);
625 dp->flags = m2->m_len << 16;
628 dp->next = vtophys(dp);
630 sc->ch[chan]->xl->next = vtophys(dp);
631 sc->ch[chan]->xl->vnext = dp;
632 sc->ch[chan]->xl = dp;
635 dp->flags |= 0xc0000000;
636 dp2->flags &= ~0x40000000;
643 printf("%s%d: Short on mem, pitched %d packets\n",
644 sc->name, chan, pitch);
647 printf("%d = %d + %d (%p)\n",
648 sch->tx_pending + m->m_pkthdr.len,
649 sch->tx_pending , m->m_pkthdr.len, m);
651 sch->tx_pending += m->m_pkthdr.len;
652 sc->m32x->txpoll &= ~(1 << chan);
661 ngmn_connect(hook_p hook)
664 struct trxd *dp, *dp2;
670 sch = NG_HOOK_PRIVATE(hook);
674 if (sch->state == UP)
678 /* Count and configure the timeslots for this channel */
679 for (nts = i = 0; i < 32; i++)
680 if (sch->ts & (1 << i)) {
681 sc->m32_mem.ts[i] = 0x00ff00ff |
682 (chan << 24) | (chan << 8);
686 /* Init the receiver & xmitter to HDLC */
687 sc->m32_mem.cs[chan].flags = 0x80e90006;
688 /* Allocate two buffers per timeslot */
690 sc->m32_mem.cs[chan].itbs = 63;
692 sc->m32_mem.cs[chan].itbs = nts * 2;
694 /* Setup a transmit chain with one descriptor */
695 /* XXX: we actually send a 1 byte packet */
696 dp = mn_alloc_desc();
697 MGETHDR(m, M_WAITOK, MT_DATA);
700 dp->flags = 0xc0000000 + (1 << 16);
701 dp->next = vtophys(dp);
703 dp->data = vtophys(sc->name);
704 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
705 sc->ch[chan]->x1 = dp;
706 sc->ch[chan]->xl = dp;
708 /* Setup a receive chain with 5 + NTS descriptors */
710 dp = mn_alloc_desc();
712 MGETHDR(m, M_WAITOK, MT_DATA);
715 dp->data = vtophys(m->m_data);
716 dp->flags = 0x40000000;
717 dp->flags += 1600 << 16;
718 dp->next = vtophys(dp);
720 sc->ch[chan]->rl = dp;
722 for (i = 0; i < (nts + 10); i++) {
724 dp = mn_alloc_desc();
726 MGETHDR(m, M_WAITOK, MT_DATA);
729 dp->data = vtophys(m->m_data);
730 dp->flags = 0x00000000;
731 dp->flags += 1600 << 16;
732 dp->next = vtophys(dp2);
735 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
736 sc->ch[chan]->r1 = dp;
738 /* Initialize this channel */
739 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
744 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
746 /* probably not at splnet, force outward queueing */
747 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
756 ngmn_disconnect(hook_p hook)
761 struct trxd *dp, *dp2;
764 sch = NG_HOOK_PRIVATE(hook);
768 if (sch->state == DOWN)
772 /* Set receiver & transmitter off */
773 sc->m32_mem.cs[chan].flags = 0x80920006;
774 sc->m32_mem.cs[chan].itbs = 0;
776 /* free the timeslots */
777 for (i = 0; i < 32; i++)
778 if (sc->ch[chan]->ts & (1 << i))
779 sc->m32_mem.ts[i] = 0x20002000;
781 /* Initialize this channel */
782 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
787 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
790 /* Free all receive descriptors and mbufs */
791 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
794 sc->ch[chan]->r1 = dp2 = dp->vnext;
798 /* Free all transmit descriptors and mbufs */
799 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
801 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
804 sc->ch[chan]->x1 = dp2 = dp->vnext;
812 * Create a new channel.
815 mn_create_channel(struct mn_softc *sc, int chan)
819 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
820 M_MN, M_WAITOK | M_ZERO);
824 sprintf(sch->name, "%s%d", sc->name, chan);
830 * Dump Munich32x state
833 m32_dump(struct mn_softc *sc)
838 printf("mn%d: MUNICH32X dump\n", sc->unit);
839 tp4 = (u_int32_t *)sc->m0v;
840 for(j = 0; j < 64; j += 8) {
841 printf("%02x", j * sizeof *tp4);
842 for(i = 0; i < 8; i++)
843 printf(" %08x", tp4[i+j]);
846 for(j = 0; j < M32_CHAN; j++) {
849 printf("CH%d: state %d ts %08x",
850 j, sc->ch[j]->state, sc->ch[j]->ts);
851 printf(" %08x %08x %08x %08x %08x %08x\n",
852 sc->m32_mem.cs[j].flags,
853 sc->m32_mem.cs[j].rdesc,
854 sc->m32_mem.cs[j].tdesc,
855 sc->m32_mem.cs[j].itbs,
857 sc->m32_mem.ctxd[j] );
865 f54_dump(struct mn_softc *sc)
870 printf("%s: FALC54 dump\n", sc->name);
871 tp1 = (u_int8_t *)sc->m1v;
872 for(j = 0; j < 128; j += 16) {
873 printf("%s: %02x |", sc->name, j * sizeof *tp1);
874 for(i = 0; i < 16; i++)
875 printf(" %02x", tp1[i+j]);
885 m32_init(struct mn_softc *sc)
888 sc->m32x->conf = 0x00000000;
889 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
891 sc->m32x->mode2 = 0x00000081;
892 sc->m32x->txpoll = 0xffffffff;
894 sc->m32x->mode2 = 0x00000081;
895 sc->m32x->txpoll = 0xffffffff;
897 sc->m32x->mode2 = 0x00000101;
899 sc->m32x->lconf = 0x6060009B;
900 sc->m32x->imask = 0x00000000;
907 f54_init(struct mn_softc *sc)
909 sc->f54w->ipc = 0x07;
911 sc->f54w->xpm0 = 0xbd;
912 sc->f54w->xpm1 = 0x03;
913 sc->f54w->xpm2 = 0x00;
915 sc->f54w->imr0 = 0x18; /* RMB, CASC */
916 sc->f54w->imr1 = 0x08; /* XMB */
917 sc->f54w->imr2 = 0x00;
918 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
919 sc->f54w->imr4 = 0x00;
921 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
922 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
923 if (sc->framing == E1)
924 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
925 else if (sc->framing == E1U)
926 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
928 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
929 sc->f54w->pcd = 0x0a;
930 sc->f54w->pcr = 0x15;
931 sc->f54w->xsw = 0x9f; /* fmr4 */
932 if (sc->framing == E1)
933 sc->f54w->xsp = 0x1c; /* fmr5 */
934 else if (sc->framing == E1U)
935 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
936 sc->f54w->xc0 = 0x07;
937 sc->f54w->xc1 = 0x3d;
938 sc->f54w->rc0 = 0x05;
939 sc->f54w->rc1 = 0x00;
940 sc->f54w->cmdr = 0x51;
944 mn_reset(struct mn_softc *sc)
949 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
950 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
952 bzero(sc->tiqb, sizeof sc->tiqb);
953 sc->m32x->tiqba = vtophys(&sc->tiqb);
954 sc->m32x->tiql = NIQB / 16 - 1;
956 bzero(sc->riqb, sizeof sc->riqb);
957 sc->m32x->riqba = vtophys(&sc->riqb);
958 sc->m32x->riql = NIQB / 16 - 1;
960 bzero(sc->ltiqb, sizeof sc->ltiqb);
961 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
962 sc->m32x->ltiql = NIQB / 16 - 1;
964 bzero(sc->lriqb, sizeof sc->lriqb);
965 sc->m32x->lriqba = vtophys(&sc->lriqb);
966 sc->m32x->lriql = NIQB / 16 - 1;
968 bzero(sc->piqb, sizeof sc->piqb);
969 sc->m32x->piqba = vtophys(&sc->piqb);
970 sc->m32x->piql = NIQB / 16 - 1;
977 sc->m32_mem.ccb = 0x4;
983 /* set all timeslots to known state */
984 for (i = 0; i < 32; i++)
985 sc->m32_mem.ts[i] = 0x20002000;
989 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
990 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
998 * FALC54 interrupt handling
1001 f54_intr(struct mn_softc *sc)
1006 u = sc->f54r->isr0 << 24;
1007 u |= sc->f54r->isr1 << 16;
1008 u |= sc->f54r->isr2 << 8;
1009 u |= sc->f54r->isr3;
1011 /* don't chat about the 1 sec heart beat */
1014 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1015 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1016 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1017 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1018 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1020 s = sc->f54r->frs0 << 24;
1021 s |= sc->f54r->frs1 << 16;
1022 s |= sc->f54r->rsw << 8;
1026 s &= ~0x01844038; /* undefined or static bits */
1027 s &= ~0x00009fc7; /* bits we don't care about */
1028 s &= ~0x00780000; /* XXX: TS16 related */
1029 s &= ~0x06000000; /* XXX: Multiframe related */
1031 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1032 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1033 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1034 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1035 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1037 if (s != sc->framer_state) {
1039 for (i = 0; i < M32_CHAN; i++) {
1042 sp = &sc->ch[i]->ifsppp;
1043 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1046 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1048 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1051 sc->framer_state = s;
1054 /* Once per second check error counters */
1055 /* XXX: not clear if this is actually ok */
1058 sc->cnt_fec += sc->f54r->fec;
1059 sc->cnt_cvc += sc->f54r->cvc;
1060 sc->cnt_cec1 += sc->f54r->cec1;
1061 sc->cnt_ebc += sc->f54r->ebc;
1062 sc->cnt_cec2 += sc->f54r->cec2;
1063 sc->cnt_cec3 += sc->f54r->cec3;
1064 sc->cnt_rbc += sc->f54r->rbc;
1068 * Transmit interrupt for one channel
1071 mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1077 chan = vector & 0x1f;
1080 if (sc->ch[chan]->state != UP) {
1081 printf("%s: tx_intr when not UP\n", sc->name);
1085 dp = sc->ch[chan]->x1;
1086 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1091 printf("%d = %d - %d (%p)\n",
1092 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1093 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1095 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1098 sc->ch[chan]->last_xmit = time_second;
1099 sc->ch[chan]->x1 = dp->vnext;
1105 * Receive interrupt for one channel
1108 mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1110 u_int32_t chan, err;
1115 chan = vector & 0x1f;
1119 if (sch->state != UP) {
1120 printf("%s: rx_intr when not UP\n", sc->name);
1124 if (vector == 0x30000b00)
1128 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1132 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1133 err = (dp->status >> 8) & 0xff;
1136 NG_SEND_DATA_ONLY(error, sch->hook, m);
1137 sch->last_recv = time_second;
1138 /* we could be down by now... */
1139 if (sch->state != UP)
1141 } else if (err & 0x40) {
1143 } else if (err & 0x10) {
1145 } else if (err & 0x08) {
1146 sch->dribble_error++;
1147 } else if (err & 0x04) {
1149 } else if (err & 0x02) {
1151 } else if (err & 0x01) {
1152 sch->overflow_error++;
1155 sch->last_rxerr = time_second;
1156 sch->prev_error = sch->last_error;
1157 sch->last_error = err;
1160 sc->ch[chan]->r1 = dp->vnext;
1162 /* Replenish desc + mbuf supplies */
1164 MGETHDR(m, M_NOWAIT, MT_DATA);
1167 return; /* ENOBUFS */
1169 if (!(MCLGET(m, M_NOWAIT))) {
1172 return; /* ENOBUFS */
1176 dp->data = vtophys(m->m_data);
1177 dp->flags = 0x40000000;
1178 dp->flags += 1600 << 16;
1179 dp->next = vtophys(dp);
1181 sc->ch[chan]->rl->next = vtophys(dp);
1182 sc->ch[chan]->rl->vnext = dp;
1183 sc->ch[chan]->rl->flags &= ~0x40000000;
1184 sc->ch[chan]->rl = dp;
1196 struct mn_softc *sc;
1197 u_int32_t stat, lstat, u;
1201 stat = sc->m32x->stat;
1202 lstat = sc->m32x->lstat;
1204 if (!stat && !(lstat & 2))
1208 if (stat & ~0xc200) {
1209 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1212 if ((stat & 0x200) || (lstat & 2))
1215 for (j = i = 0; i < 64; i ++) {
1220 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1222 u &= ~0x30000400; /* bits we don't care about */
1223 if ((u & ~0x1f) == 0x00000900)
1228 printf("%s*: RIQB:", sc->name);
1229 printf(" [%d]=%08x", i, u);
1236 for (j = i = 0; i < 64; i ++) {
1241 if ((u & ~0x1f) == 0x20000800)
1243 u &= ~0x20000000; /* bits we don't care about */
1247 printf("%s*: TIQB:", sc->name);
1248 printf(" [%d]=%08x", i, u);
1254 sc->m32x->stat = stat;
1258 * PCI initialization stuff
1262 mn_probe (device_t self)
1264 u_int id = pci_get_devid(self);
1266 if (sizeof (struct m32xreg) != 256) {
1267 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1270 if (sizeof (struct f54rreg) != 128) {
1271 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1274 if (sizeof (struct f54wreg) != 128) {
1275 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1279 if (id != 0x2101110a)
1282 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1283 return (BUS_PROBE_DEFAULT);
1287 mn_attach (device_t self)
1289 struct mn_softc *sc;
1294 struct resource *res;
1297 if (ng_newtype(&mntypestruct))
1298 printf("ng_newtype failed\n");
1302 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1303 device_set_softc(self, sc);
1306 sc->unit = device_get_unit(self);
1308 sprintf(sc->name, "mn%d", sc->unit);
1311 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1313 device_printf(self, "Could not map memory\n");
1317 sc->m0v = rman_get_virtual(res);
1318 sc->m0p = rman_get_start(res);
1321 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1323 device_printf(self, "Could not map memory\n");
1327 sc->m1v = rman_get_virtual(res);
1328 sc->m1p = rman_get_start(res);
1330 /* Allocate interrupt */
1332 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1333 RF_SHAREABLE | RF_ACTIVE);
1335 if (sc->irq == NULL) {
1336 printf("couldn't map interrupt\n");
1341 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1344 printf("couldn't set up irq\n");
1349 u = pci_read_config(self, PCIR_COMMAND, 2);
1351 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2);
1353 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1355 u = pci_read_config(self, PCIR_COMMAND, 1);
1358 ver = pci_get_revid(self);
1360 sc->m32x = (struct m32xreg *) sc->m0v;
1361 sc->f54w = (struct f54wreg *) sc->m1v;
1362 sc->f54r = (struct f54rreg *) sc->m1v;
1364 /* We must reset before poking at FALC54 registers */
1369 printf("mn%d: Munich32X", sc->unit);
1375 printf(" Rev 0x%x\n", ver);
1378 switch (sc->f54r->vstr) {
1380 printf(" Rev < 1.3\n");
1383 printf(" Rev 1.3\n");
1386 printf(" Rev 1.4\n");
1389 printf("-LH Rev 1.1\n");
1392 printf("-LH Rev 1.3\n");
1395 printf(" Rev 0x%x\n", sc->f54r->vstr);
1398 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1399 printf("ng_make_node_common failed\n");
1402 NG_NODE_SET_PRIVATE(sc->node, sc);
1403 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1404 if (ng_name_node(sc->node, sc->nodename)) {
1405 NG_NODE_UNREF(sc->node);
1413 static device_method_t mn_methods[] = {
1414 /* Device interface */
1415 DEVMETHOD(device_probe, mn_probe),
1416 DEVMETHOD(device_attach, mn_attach),
1417 DEVMETHOD(device_suspend, bus_generic_suspend),
1418 DEVMETHOD(device_resume, bus_generic_resume),
1419 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1424 static driver_t mn_driver = {
1430 static devclass_t mn_devclass;
1432 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);