2 * SPDX-License-Identifier: Beerware
4 * ----------------------------------------------------------------------------
5 * "THE BEER-WARE LICENSE" (Revision 42):
6 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
7 * can do whatever you want with this stuff. If we meet some day, and you think
8 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
9 * ----------------------------------------------------------------------------
13 * Driver for Siemens reference design card "Easy321-R1".
15 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
18 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
21 * The FALC54 and MUNICH32X have far too many registers and weird modes for
22 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
23 * you will (badly!) need the documentation anyway if you want to mess with
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Stuff to describe the MUNIC32X and FALC54 chips.
34 #define M32_CHAN 32 /* We have 32 channels */
35 #define M32_TS 32 /* We have 32 timeslots */
37 #define NG_MN_NODE_TYPE "mn"
39 #include <sys/param.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
44 #include <sys/systm.h>
45 #include <sys/malloc.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
51 #include <machine/bus.h>
52 #include <machine/resource.h>
59 #include <netgraph/ng_message.h>
60 #include <netgraph/netgraph.h>
63 static int mn_maxlatency = 1000;
64 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
66 "The number of milliseconds a packet is allowed to spend in the output queue. "
67 "If the output queue is longer than this number of milliseconds when the packet "
68 "arrives for output, the packet will be dropped."
72 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
76 /* From: PEB 20321 data sheet, p187, table 22 */
78 u_int32_t conf, cmd, stat, imask;
79 u_int32_t fill10, piqba, piql, fill1c;
80 u_int32_t mode1, mode2, ccba, txpoll;
81 u_int32_t tiqba, tiql, riqba, riql;
82 u_int32_t lconf, lccba, fill48, ltran;
83 u_int32_t ltiqba, ltiql, lriqba, lriql;
84 u_int32_t lreg0, lreg1, lreg2, lreg3;
85 u_int32_t lreg4, lreg5, lre6, lstat;
86 u_int32_t gpdir, gpdata, gpod, fill8c;
87 u_int32_t ssccon, sscbr, ssctb, sscrb;
88 u_int32_t ssccse, sscim, fillab, fillac;
89 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
91 u_int32_t iomtmo, iomrmo, filld8, filldc;
92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
96 /* From: PEB 2254 data sheet, p80, table 10 */
99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
106 u_int8_t lim2, fill39[7];
111 u_int8_t dec, fill61, test2, fill63[5];
116 /* From: PEB 2254 data sheet, p117, table 10 */
119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
126 u_int8_t lim2, fill39[7];
128 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
129 u_int16_t fec, cvc, cec1, ebc;
130 u_int16_t cec2, cec3;
131 u_int8_t rsa4, rsa5, rsa6, rsa7;
132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
138 /* Transmit & receive descriptors */
143 u_int32_t status; /* only used for receive */
144 struct mbuf *m; /* software use only */
145 struct trxd *vnext; /* software use only */
148 /* Channel specification */
159 u_int32_t reserve1[2];
160 u_int32_t ts[M32_TS];
161 struct cspec cs[M32_CHAN];
162 vm_offset_t crxd[M32_CHAN];
163 vm_offset_t ctxd[M32_CHAN];
170 static int mn_probe(device_t self);
171 static int mn_attach(device_t self);
172 static void mn_create_channel(struct mn_softc *sc, int chan);
173 static int mn_reset(struct mn_softc *sc);
174 static struct trxd * mn_alloc_desc(void);
175 static void mn_free_desc(struct trxd *dp);
176 static void mn_intr(void *xsc);
177 static u_int32_t mn_parse_ts(const char *s, int *nbit);
179 static void m32_dump(struct mn_softc *sc);
180 static void f54_dump(struct mn_softc *sc);
181 static void mn_fmt_ts(char *p, u_int32_t ts);
183 static void f54_init(struct mn_softc *sc);
185 static ng_constructor_t ngmn_constructor;
186 static ng_rcvmsg_t ngmn_rcvmsg;
187 static ng_shutdown_t ngmn_shutdown;
188 static ng_newhook_t ngmn_newhook;
189 static ng_connect_t ngmn_connect;
190 static ng_rcvdata_t ngmn_rcvdata;
191 static ng_disconnect_t ngmn_disconnect;
193 static struct ng_type mntypestruct = {
194 .version = NG_ABI_VERSION,
195 .name = NG_MN_NODE_TYPE,
196 .constructor = ngmn_constructor,
197 .rcvmsg = ngmn_rcvmsg,
198 .shutdown = ngmn_shutdown,
199 .newhook = ngmn_newhook,
200 .connect = ngmn_connect,
201 .rcvdata = ngmn_rcvdata,
202 .disconnect = ngmn_disconnect,
205 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
210 enum {DOWN, UP} state;
215 struct trxd *r1, *rl;
216 struct trxd *x1, *xl;
227 u_long dribble_error;
230 u_long overflow_error;
239 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
244 struct resource *irq;
246 enum framing framing;
249 vm_offset_t m0p, m1p;
250 struct m32xreg *m32x;
251 struct f54wreg *f54w;
252 struct f54rreg *f54r;
253 struct m32_mem m32_mem;
254 u_int32_t tiqb[NIQB];
255 u_int32_t riqb[NIQB];
256 u_int32_t piqb[NIQB];
257 u_int32_t ltiqb[NIQB];
258 u_int32_t lriqb[NIQB];
260 u_int32_t falc_irq, falc_state, framer_state;
261 struct schan *ch[M32_CHAN];
262 char nodename[NG_NODESIZ];
275 ngmn_constructor(node_p node)
282 ngmn_shutdown(node_p nodep)
289 ngmn_config(node_p node, char *set, char *ret)
292 enum framing wframing;
294 sc = NG_NODE_PRIVATE(node);
297 if (!strncmp(set, "line ", 5)) {
298 wframing = sc->framing;
299 if (!strcmp(set, "line e1")) {
301 } else if (!strcmp(set, "line e1u")) {
304 strcat(ret, "ENOGROK\n");
307 if (wframing == sc->framing)
309 if (sc->nhooks > 0) {
310 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
313 sc->framing = wframing;
320 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
321 strcat(ret, "ENOGROK\n");
329 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
332 struct ng_mesg *resp = NULL;
338 NGI_GET_MSG(item, msg);
339 sc = NG_NODE_PRIVATE(node);
341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
347 if (msg->header.cmd != NGM_TEXT_CONFIG &&
348 msg->header.cmd != NGM_TEXT_STATUS) {
354 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
362 if (msg->header.arglen)
363 s = (char *)msg->data;
366 r = (char *)resp->data;
369 if (msg->header.cmd == NGM_TEXT_CONFIG) {
370 ngmn_config(node, s, r);
371 resp->header.arglen = strlen(r) + 1;
372 NG_RESPOND_MSG(i, node, item, resp);
377 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
378 "\40LOS\37AIS\36LFA\35RRA"
379 "\34AUXP\33NMF\32LMFA\31frs0.0"
380 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
381 "\24TS16LFA\23frs1.2\22XLS\21XLO"
382 "\20RS1\17rsw.6\16RRA\15RY0"
383 "\14RY1\13RY2\12RY3\11RY4"
384 "\10SI1\7SI2\6rsp.5\5rsp.4"
385 "\4rsp.3\3RSIF\2RS13\1RS15");
386 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
387 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
389 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
390 "\40LOS\37AIS\36LFA\35RRA"
391 "\34AUXP\33NMF\32LMFA\31frs0.0"
392 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
393 "\24TS16LFA\23frs1.2\22XLS\21XLO"
394 "\20RS1\17rsw.6\16RRA\15RY0"
395 "\14RY1\13RY2\12RY3\11RY4"
396 "\10SI1\7SI2\6rsp.5\5rsp.4"
397 "\4rsp.3\3RSIF\2RS13\1RS15");
398 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
399 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
400 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
401 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
402 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
403 for (i = 0; i < M32_CHAN; i++) {
408 pos += sprintf(r + pos, " Chan %d <%s> ",
409 i, NG_HOOK_NAME(sch->hook));
411 pos += sprintf(r + pos, " Last Rx: ");
413 pos += sprintf(r + pos, "%lu s",
414 (unsigned long)(time_second - sch->last_recv));
416 pos += sprintf(r + pos, "never");
418 pos += sprintf(r + pos, ", last RxErr: ");
420 pos += sprintf(r + pos, "%lu s",
421 (unsigned long)(time_second - sch->last_rxerr));
423 pos += sprintf(r + pos, "never");
425 pos += sprintf(r + pos, ", last Tx: ");
427 pos += sprintf(r + pos, "%lu s\n",
428 (unsigned long)(time_second - sch->last_xmit));
430 pos += sprintf(r + pos, "never\n");
432 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
433 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
434 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
435 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
436 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
437 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
438 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
440 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
441 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
442 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
443 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
446 resp->header.arglen = pos + 1;
448 /* Take care of synchronous response, if any */
449 NG_RESPOND_MSG(i, node, item, resp);
455 ngmn_newhook(node_p node, hook_p hook, const char *name)
461 sc = NG_NODE_PRIVATE(node);
463 if (name[0] != 't' || name[1] != 's')
466 ts = mn_parse_ts(name + 2, &nbit);
467 printf("%d bits %x\n", nbit, ts);
468 if (sc->framing == E1 && (ts & 1))
470 if (sc->framing == E1U && nbit != 32)
474 if (sc->framing == E1)
479 mn_create_channel(sc, chan);
480 else if (sc->ch[chan]->state == UP)
482 sc->ch[chan]->ts = ts;
483 sc->ch[chan]->hook = hook;
484 sc->ch[chan]->tx_limit = nbit * 8;
485 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
491 static struct trxd *mn_desc_free;
500 mn_desc_free = dp->vnext;
502 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
507 mn_free_desc(struct trxd *dp)
509 dp->vnext = mn_desc_free;
514 mn_parse_ts(const char *s, int *nbit)
524 i = strtol(s, &p, 0);
527 while (j != -1 && j < i) {
537 } else if (*p == '-') {
552 mn_fmt_ts(char *p, u_int32_t ts)
559 for (j = 0; j < 32; j++) {
560 if (!(ts & (1 << j)))
562 sprintf(p, "%s%d", s, j);
565 if (!(ts & (1 << (j+1))))
568 if (!(ts & (1 << (j+1))))
570 sprintf(p, "-%d", j);
582 ngmn_rcvdata(hook_p hook, item_p item)
585 struct trxd *dp, *dp2;
588 int chan, pitch, len;
591 sch = NG_HOOK_PRIVATE(hook);
595 if (sch->state != UP) {
600 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
608 dp2 = sc->ch[chan]->xl;
609 len = m->m_pkthdr.len;
611 dp = mn_alloc_desc();
615 sc->ch[chan]->xl = dp2;
622 sc->ch[chan]->xl->vnext = NULL;
625 dp->data = vtophys(m2->m_data);
626 dp->flags = m2->m_len << 16;
629 dp->next = vtophys(dp);
631 sc->ch[chan]->xl->next = vtophys(dp);
632 sc->ch[chan]->xl->vnext = dp;
633 sc->ch[chan]->xl = dp;
636 dp->flags |= 0xc0000000;
637 dp2->flags &= ~0x40000000;
644 printf("%s%d: Short on mem, pitched %d packets\n",
645 sc->name, chan, pitch);
648 printf("%d = %d + %d (%p)\n",
649 sch->tx_pending + m->m_pkthdr.len,
650 sch->tx_pending , m->m_pkthdr.len, m);
652 sch->tx_pending += m->m_pkthdr.len;
653 sc->m32x->txpoll &= ~(1 << chan);
662 ngmn_connect(hook_p hook)
665 struct trxd *dp, *dp2;
671 sch = NG_HOOK_PRIVATE(hook);
675 if (sch->state == UP)
679 /* Count and configure the timeslots for this channel */
680 for (nts = i = 0; i < 32; i++)
681 if (sch->ts & (1 << i)) {
682 sc->m32_mem.ts[i] = 0x00ff00ff |
683 (chan << 24) | (chan << 8);
687 /* Init the receiver & xmitter to HDLC */
688 sc->m32_mem.cs[chan].flags = 0x80e90006;
689 /* Allocate two buffers per timeslot */
691 sc->m32_mem.cs[chan].itbs = 63;
693 sc->m32_mem.cs[chan].itbs = nts * 2;
695 /* Setup a transmit chain with one descriptor */
696 /* XXX: we actually send a 1 byte packet */
697 dp = mn_alloc_desc();
698 MGETHDR(m, M_WAITOK, MT_DATA);
701 dp->flags = 0xc0000000 + (1 << 16);
702 dp->next = vtophys(dp);
704 dp->data = vtophys(sc->name);
705 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
706 sc->ch[chan]->x1 = dp;
707 sc->ch[chan]->xl = dp;
709 /* Setup a receive chain with 5 + NTS descriptors */
711 dp = mn_alloc_desc();
713 MGETHDR(m, M_WAITOK, MT_DATA);
716 dp->data = vtophys(m->m_data);
717 dp->flags = 0x40000000;
718 dp->flags += 1600 << 16;
719 dp->next = vtophys(dp);
721 sc->ch[chan]->rl = dp;
723 for (i = 0; i < (nts + 10); i++) {
725 dp = mn_alloc_desc();
727 MGETHDR(m, M_WAITOK, MT_DATA);
730 dp->data = vtophys(m->m_data);
731 dp->flags = 0x00000000;
732 dp->flags += 1600 << 16;
733 dp->next = vtophys(dp2);
736 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
737 sc->ch[chan]->r1 = dp;
739 /* Initialize this channel */
740 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
745 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
747 /* probably not at splnet, force outward queueing */
748 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
757 ngmn_disconnect(hook_p hook)
762 struct trxd *dp, *dp2;
765 sch = NG_HOOK_PRIVATE(hook);
769 if (sch->state == DOWN)
773 /* Set receiver & transmitter off */
774 sc->m32_mem.cs[chan].flags = 0x80920006;
775 sc->m32_mem.cs[chan].itbs = 0;
777 /* free the timeslots */
778 for (i = 0; i < 32; i++)
779 if (sc->ch[chan]->ts & (1 << i))
780 sc->m32_mem.ts[i] = 0x20002000;
782 /* Initialize this channel */
783 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
788 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
791 /* Free all receive descriptors and mbufs */
792 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
795 sc->ch[chan]->r1 = dp2 = dp->vnext;
799 /* Free all transmit descriptors and mbufs */
800 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
802 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
805 sc->ch[chan]->x1 = dp2 = dp->vnext;
813 * Create a new channel.
816 mn_create_channel(struct mn_softc *sc, int chan)
820 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
821 M_MN, M_WAITOK | M_ZERO);
825 sprintf(sch->name, "%s%d", sc->name, chan);
831 * Dump Munich32x state
834 m32_dump(struct mn_softc *sc)
839 printf("mn%d: MUNICH32X dump\n", sc->unit);
840 tp4 = (u_int32_t *)sc->m0v;
841 for(j = 0; j < 64; j += 8) {
842 printf("%02x", j * sizeof *tp4);
843 for(i = 0; i < 8; i++)
844 printf(" %08x", tp4[i+j]);
847 for(j = 0; j < M32_CHAN; j++) {
850 printf("CH%d: state %d ts %08x",
851 j, sc->ch[j]->state, sc->ch[j]->ts);
852 printf(" %08x %08x %08x %08x %08x %08x\n",
853 sc->m32_mem.cs[j].flags,
854 sc->m32_mem.cs[j].rdesc,
855 sc->m32_mem.cs[j].tdesc,
856 sc->m32_mem.cs[j].itbs,
858 sc->m32_mem.ctxd[j] );
866 f54_dump(struct mn_softc *sc)
871 printf("%s: FALC54 dump\n", sc->name);
872 tp1 = (u_int8_t *)sc->m1v;
873 for(j = 0; j < 128; j += 16) {
874 printf("%s: %02x |", sc->name, j * sizeof *tp1);
875 for(i = 0; i < 16; i++)
876 printf(" %02x", tp1[i+j]);
886 m32_init(struct mn_softc *sc)
889 sc->m32x->conf = 0x00000000;
890 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
892 sc->m32x->mode2 = 0x00000081;
893 sc->m32x->txpoll = 0xffffffff;
895 sc->m32x->mode2 = 0x00000081;
896 sc->m32x->txpoll = 0xffffffff;
898 sc->m32x->mode2 = 0x00000101;
900 sc->m32x->lconf = 0x6060009B;
901 sc->m32x->imask = 0x00000000;
908 f54_init(struct mn_softc *sc)
910 sc->f54w->ipc = 0x07;
912 sc->f54w->xpm0 = 0xbd;
913 sc->f54w->xpm1 = 0x03;
914 sc->f54w->xpm2 = 0x00;
916 sc->f54w->imr0 = 0x18; /* RMB, CASC */
917 sc->f54w->imr1 = 0x08; /* XMB */
918 sc->f54w->imr2 = 0x00;
919 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
920 sc->f54w->imr4 = 0x00;
922 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
923 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
924 if (sc->framing == E1)
925 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
926 else if (sc->framing == E1U)
927 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
929 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
930 sc->f54w->pcd = 0x0a;
931 sc->f54w->pcr = 0x15;
932 sc->f54w->xsw = 0x9f; /* fmr4 */
933 if (sc->framing == E1)
934 sc->f54w->xsp = 0x1c; /* fmr5 */
935 else if (sc->framing == E1U)
936 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
937 sc->f54w->xc0 = 0x07;
938 sc->f54w->xc1 = 0x3d;
939 sc->f54w->rc0 = 0x05;
940 sc->f54w->rc1 = 0x00;
941 sc->f54w->cmdr = 0x51;
945 mn_reset(struct mn_softc *sc)
950 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
951 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
953 bzero(sc->tiqb, sizeof sc->tiqb);
954 sc->m32x->tiqba = vtophys(&sc->tiqb);
955 sc->m32x->tiql = NIQB / 16 - 1;
957 bzero(sc->riqb, sizeof sc->riqb);
958 sc->m32x->riqba = vtophys(&sc->riqb);
959 sc->m32x->riql = NIQB / 16 - 1;
961 bzero(sc->ltiqb, sizeof sc->ltiqb);
962 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
963 sc->m32x->ltiql = NIQB / 16 - 1;
965 bzero(sc->lriqb, sizeof sc->lriqb);
966 sc->m32x->lriqba = vtophys(&sc->lriqb);
967 sc->m32x->lriql = NIQB / 16 - 1;
969 bzero(sc->piqb, sizeof sc->piqb);
970 sc->m32x->piqba = vtophys(&sc->piqb);
971 sc->m32x->piql = NIQB / 16 - 1;
978 sc->m32_mem.ccb = 0x4;
984 /* set all timeslots to known state */
985 for (i = 0; i < 32; i++)
986 sc->m32_mem.ts[i] = 0x20002000;
990 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
991 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
999 * FALC54 interrupt handling
1002 f54_intr(struct mn_softc *sc)
1007 u = sc->f54r->isr0 << 24;
1008 u |= sc->f54r->isr1 << 16;
1009 u |= sc->f54r->isr2 << 8;
1010 u |= sc->f54r->isr3;
1012 /* don't chat about the 1 sec heart beat */
1015 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1016 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1017 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1018 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1019 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1021 s = sc->f54r->frs0 << 24;
1022 s |= sc->f54r->frs1 << 16;
1023 s |= sc->f54r->rsw << 8;
1027 s &= ~0x01844038; /* undefined or static bits */
1028 s &= ~0x00009fc7; /* bits we don't care about */
1029 s &= ~0x00780000; /* XXX: TS16 related */
1030 s &= ~0x06000000; /* XXX: Multiframe related */
1032 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1033 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1034 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1035 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1036 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1038 if (s != sc->framer_state) {
1040 for (i = 0; i < M32_CHAN; i++) {
1043 sp = &sc->ch[i]->ifsppp;
1044 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1047 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1049 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1052 sc->framer_state = s;
1055 /* Once per second check error counters */
1056 /* XXX: not clear if this is actually ok */
1059 sc->cnt_fec += sc->f54r->fec;
1060 sc->cnt_cvc += sc->f54r->cvc;
1061 sc->cnt_cec1 += sc->f54r->cec1;
1062 sc->cnt_ebc += sc->f54r->ebc;
1063 sc->cnt_cec2 += sc->f54r->cec2;
1064 sc->cnt_cec3 += sc->f54r->cec3;
1065 sc->cnt_rbc += sc->f54r->rbc;
1069 * Transmit interrupt for one channel
1072 mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1078 chan = vector & 0x1f;
1081 if (sc->ch[chan]->state != UP) {
1082 printf("%s: tx_intr when not UP\n", sc->name);
1086 dp = sc->ch[chan]->x1;
1087 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1092 printf("%d = %d - %d (%p)\n",
1093 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1094 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1096 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1099 sc->ch[chan]->last_xmit = time_second;
1100 sc->ch[chan]->x1 = dp->vnext;
1106 * Receive interrupt for one channel
1109 mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1111 u_int32_t chan, err;
1116 chan = vector & 0x1f;
1120 if (sch->state != UP) {
1121 printf("%s: rx_intr when not UP\n", sc->name);
1125 if (vector == 0x30000b00)
1129 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1133 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1134 err = (dp->status >> 8) & 0xff;
1137 NG_SEND_DATA_ONLY(error, sch->hook, m);
1138 sch->last_recv = time_second;
1139 /* we could be down by now... */
1140 if (sch->state != UP)
1142 } else if (err & 0x40) {
1144 } else if (err & 0x10) {
1146 } else if (err & 0x08) {
1147 sch->dribble_error++;
1148 } else if (err & 0x04) {
1150 } else if (err & 0x02) {
1152 } else if (err & 0x01) {
1153 sch->overflow_error++;
1156 sch->last_rxerr = time_second;
1157 sch->prev_error = sch->last_error;
1158 sch->last_error = err;
1161 sc->ch[chan]->r1 = dp->vnext;
1163 /* Replenish desc + mbuf supplies */
1165 MGETHDR(m, M_NOWAIT, MT_DATA);
1168 return; /* ENOBUFS */
1170 if (!(MCLGET(m, M_NOWAIT))) {
1173 return; /* ENOBUFS */
1177 dp->data = vtophys(m->m_data);
1178 dp->flags = 0x40000000;
1179 dp->flags += 1600 << 16;
1180 dp->next = vtophys(dp);
1182 sc->ch[chan]->rl->next = vtophys(dp);
1183 sc->ch[chan]->rl->vnext = dp;
1184 sc->ch[chan]->rl->flags &= ~0x40000000;
1185 sc->ch[chan]->rl = dp;
1197 struct mn_softc *sc;
1198 u_int32_t stat, lstat, u;
1202 stat = sc->m32x->stat;
1203 lstat = sc->m32x->lstat;
1205 if (!stat && !(lstat & 2))
1209 if (stat & ~0xc200) {
1210 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1213 if ((stat & 0x200) || (lstat & 2))
1216 for (j = i = 0; i < 64; i ++) {
1221 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1223 u &= ~0x30000400; /* bits we don't care about */
1224 if ((u & ~0x1f) == 0x00000900)
1229 printf("%s*: RIQB:", sc->name);
1230 printf(" [%d]=%08x", i, u);
1237 for (j = i = 0; i < 64; i ++) {
1242 if ((u & ~0x1f) == 0x20000800)
1244 u &= ~0x20000000; /* bits we don't care about */
1248 printf("%s*: TIQB:", sc->name);
1249 printf(" [%d]=%08x", i, u);
1255 sc->m32x->stat = stat;
1259 * PCI initialization stuff
1263 mn_probe (device_t self)
1265 u_int id = pci_get_devid(self);
1267 if (sizeof (struct m32xreg) != 256) {
1268 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1271 if (sizeof (struct f54rreg) != 128) {
1272 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1275 if (sizeof (struct f54wreg) != 128) {
1276 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1280 if (id != 0x2101110a)
1283 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1284 return (BUS_PROBE_DEFAULT);
1288 mn_attach (device_t self)
1290 struct mn_softc *sc;
1295 struct resource *res;
1298 if (ng_newtype(&mntypestruct))
1299 printf("ng_newtype failed\n");
1303 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1304 device_set_softc(self, sc);
1307 sc->unit = device_get_unit(self);
1309 sprintf(sc->name, "mn%d", sc->unit);
1312 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1314 device_printf(self, "Could not map memory\n");
1318 sc->m0v = rman_get_virtual(res);
1319 sc->m0p = rman_get_start(res);
1322 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1324 device_printf(self, "Could not map memory\n");
1328 sc->m1v = rman_get_virtual(res);
1329 sc->m1p = rman_get_start(res);
1331 /* Allocate interrupt */
1333 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1334 RF_SHAREABLE | RF_ACTIVE);
1336 if (sc->irq == NULL) {
1337 printf("couldn't map interrupt\n");
1342 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1345 printf("couldn't set up irq\n");
1350 u = pci_read_config(self, PCIR_COMMAND, 2);
1352 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2);
1354 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1356 u = pci_read_config(self, PCIR_COMMAND, 1);
1359 ver = pci_get_revid(self);
1361 sc->m32x = (struct m32xreg *) sc->m0v;
1362 sc->f54w = (struct f54wreg *) sc->m1v;
1363 sc->f54r = (struct f54rreg *) sc->m1v;
1365 /* We must reset before poking at FALC54 registers */
1370 printf("mn%d: Munich32X", sc->unit);
1376 printf(" Rev 0x%x\n", ver);
1379 switch (sc->f54r->vstr) {
1381 printf(" Rev < 1.3\n");
1384 printf(" Rev 1.3\n");
1387 printf(" Rev 1.4\n");
1390 printf("-LH Rev 1.1\n");
1393 printf("-LH Rev 1.3\n");
1396 printf(" Rev 0x%x\n", sc->f54r->vstr);
1399 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1400 printf("ng_make_node_common failed\n");
1403 NG_NODE_SET_PRIVATE(sc->node, sc);
1404 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1405 if (ng_name_node(sc->node, sc->nodename)) {
1406 NG_NODE_UNREF(sc->node);
1414 static device_method_t mn_methods[] = {
1415 /* Device interface */
1416 DEVMETHOD(device_probe, mn_probe),
1417 DEVMETHOD(device_attach, mn_attach),
1418 DEVMETHOD(device_suspend, bus_generic_suspend),
1419 DEVMETHOD(device_resume, bus_generic_resume),
1420 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1425 static driver_t mn_driver = {
1431 static devclass_t mn_devclass;
1433 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);