2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
34 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
38 * Title: MPI Message independent structures and definitions
39 * including System Interface Register Set and
40 * scatter/gather formats.
41 * Creation Date: June 21, 2006
43 * mpi2.h Version: 02.00.52
45 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
46 * prefix are for use only on MPI v2.5 products, and must not be used
47 * with MPI v2.0 products. Unless otherwise noted, names beginning with
48 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
53 * Date Version Description
54 * -------- -------- ------------------------------------------------------
55 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
56 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
57 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
58 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
59 * Moved ReplyPostHostIndex register to offset 0x6C of the
60 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
61 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
62 * Added union of request descriptors.
63 * Added union of reply descriptors.
64 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added define for MPI2_VERSION_02_00.
66 * Fixed the size of the FunctionDependent5 field in the
67 * MPI2_DEFAULT_REPLY structure.
68 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
69 * Removed the MPI-defined Fault Codes and extended the
70 * product specific codes up to 0xEFFF.
71 * Added a sixth key value for the WriteSequence register
72 * and changed the flush value to 0x0.
73 * Added message function codes for Diagnostic Buffer Post
74 * and Diagnsotic Release.
75 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
76 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
77 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Added #defines for marking a reply descriptor as unused.
81 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Moved LUN field defines from mpi2_init.h.
84 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
86 * In all request and reply descriptors, replaced VF_ID
87 * field with MSIxIndex field.
88 * Removed DevHandle field from
89 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
91 * Added RAID Accelerator functionality.
92 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
94 * Added MSI-x index mask and shift for Reply Post Host
96 * Added function code for Host Based Discovery Action.
97 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
98 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
99 * Added defines for product-specific range of message
100 * function codes, 0xF0 to 0xFF.
101 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
102 * Added alternative defines for the SGE Direction bit.
103 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
105 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
106 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
107 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
108 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
109 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
110 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
111 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
112 * Incorporating additions for MPI v2.5.
113 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
115 * Added Hard Reset delay timings.
116 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
120 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
121 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
123 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
124 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
125 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
126 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
127 * 11-18-14 02.00.36 Updated copyright information.
128 * Bumped MPI2_HEADER_VERSION_UNIT.
129 * 03-16-15 02.00.37 Updated for MPI v2.6.
130 * Bumped MPI2_HEADER_VERSION_UNIT.
131 * Added Scratchpad registers and
132 * AtomicRequestDescriptorPost register to
133 * MPI2_SYSTEM_INTERFACE_REGS.
134 * Added MPI2_DIAG_SBR_RELOAD.
135 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER.
136 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
137 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT
138 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
139 * Added V7 HostDiagnostic register defines
140 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
141 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
142 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
143 * to be unique within first 32 characters.
144 * Removed AHCI support.
145 * Removed SOP support.
146 * Bumped MPI2_HEADER_VERSION_UNIT.
147 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
148 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
149 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
150 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT.
151 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
152 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT.
153 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT.
154 * 07-22-18 02.00.51 Added SECURE_BOOT define.
155 * Bumped MPI2_HEADER_VERSION_UNIT
156 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT.
157 * --------------------------------------------------------------------------
164 /*****************************************************************************
166 * MPI Version Definitions
168 *****************************************************************************/
170 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
171 #define MPI2_VERSION_MAJOR_SHIFT (8)
172 #define MPI2_VERSION_MINOR_MASK (0x00FF)
173 #define MPI2_VERSION_MINOR_SHIFT (0)
175 /* major version for all MPI v2.x */
176 #define MPI2_VERSION_MAJOR (0x02)
178 /* minor version for MPI v2.0 compatible products */
179 #define MPI2_VERSION_MINOR (0x00)
180 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
182 #define MPI2_VERSION_02_00 (0x0200)
185 /* minor version for MPI v2.5 compatible products */
186 #define MPI25_VERSION_MINOR (0x05)
187 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
189 #define MPI2_VERSION_02_05 (0x0205)
192 /* minor version for MPI v2.6 compatible products */
193 #define MPI26_VERSION_MINOR (0x06)
194 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
196 #define MPI2_VERSION_02_06 (0x0206)
199 /* Unit and Dev versioning for this MPI header set */
200 #define MPI2_HEADER_VERSION_UNIT (0x34)
201 #define MPI2_HEADER_VERSION_DEV (0x00)
202 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
203 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
204 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
205 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
206 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
209 /*****************************************************************************
211 * IOC State Definitions
213 *****************************************************************************/
215 #define MPI2_IOC_STATE_RESET (0x00000000)
216 #define MPI2_IOC_STATE_READY (0x10000000)
217 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
218 #define MPI2_IOC_STATE_FAULT (0x40000000)
220 #define MPI2_IOC_STATE_MASK (0xF0000000)
221 #define MPI2_IOC_STATE_SHIFT (28)
223 /* Fault state range for prodcut specific codes */
224 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
225 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
228 /*****************************************************************************
230 * System Interface Register Definitions
232 *****************************************************************************/
234 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
236 U32 Doorbell; /* 0x00 */
237 U32 WriteSequence; /* 0x04 */
238 U32 HostDiagnostic; /* 0x08 */
239 U32 Reserved1; /* 0x0C */
240 U32 DiagRWData; /* 0x10 */
241 U32 DiagRWAddressLow; /* 0x14 */
242 U32 DiagRWAddressHigh; /* 0x18 */
243 U32 Reserved2[5]; /* 0x1C */
244 U32 HostInterruptStatus; /* 0x30 */
245 U32 HostInterruptMask; /* 0x34 */
246 U32 DCRData; /* 0x38 */
247 U32 DCRAddress; /* 0x3C */
248 U32 Reserved3[2]; /* 0x40 */
249 U32 ReplyFreeHostIndex; /* 0x48 */
250 U32 Reserved4[8]; /* 0x4C */
251 U32 ReplyPostHostIndex; /* 0x6C */
252 U32 Reserved5; /* 0x70 */
253 U32 HCBSize; /* 0x74 */
254 U32 HCBAddressLow; /* 0x78 */
255 U32 HCBAddressHigh; /* 0x7C */
256 U32 Reserved6[12]; /* 0x80 */
257 U32 Scratchpad[4]; /* 0xB0 */
258 U32 RequestDescriptorPostLow; /* 0xC0 */
259 U32 RequestDescriptorPostHigh; /* 0xC4 */
260 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */
261 U32 Reserved7[13]; /* 0xCC */
262 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
263 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
266 * Defines for working with the Doorbell register.
268 #define MPI2_DOORBELL_OFFSET (0x00000000)
270 /* IOC --> System values */
271 #define MPI2_DOORBELL_USED (0x08000000)
272 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
273 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
274 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
275 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
277 /* System --> IOC values */
278 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
279 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
280 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
281 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
285 * Defines for the WriteSequence register
287 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
288 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
289 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
290 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
291 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
292 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
293 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
294 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
295 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
298 * Defines for the HostDiagnostic register
300 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
302 #define MPI26_DIAG_SECURE_BOOT (0x80000000)
304 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
306 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
307 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
308 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
310 /* Defines for V7A/V7R HostDiagnostic Register */
311 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
312 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
313 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
314 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
316 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
317 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
318 #define MPI2_DIAG_HCB_MODE (0x00000100)
319 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
320 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
321 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
322 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
323 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
324 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
327 * Offsets for DiagRWData and address
329 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
330 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
331 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
334 * Defines for the HostInterruptStatus register
336 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
337 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
338 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
339 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
340 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
341 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
342 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
345 * Defines for the HostInterruptMask register
347 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
348 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
349 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
350 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
351 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
352 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
355 * Offsets for DCRData and address
357 #define MPI2_DCR_DATA_OFFSET (0x00000038)
358 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
361 * Offset for the Reply Free Queue
363 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
366 * Defines for the Reply Descriptor Post Queue
368 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
369 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
370 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
371 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
372 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
376 * Defines for the HCBSize and address
378 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
379 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
380 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
382 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
383 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
386 * Offsets for the Scratchpad registers
388 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
389 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
390 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
391 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
394 * Offsets for the Request Descriptor Post Queue
396 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
397 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
398 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
401 /* Hard Reset delay timings */
402 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
403 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
404 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
406 /*****************************************************************************
408 * Message Descriptors
410 *****************************************************************************/
412 /* Request Descriptors */
414 /* Default Request Descriptor */
415 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
417 U8 RequestFlags; /* 0x00 */
418 U8 MSIxIndex; /* 0x01 */
421 U16 DescriptorTypeDependent; /* 0x06 */
422 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
423 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
424 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
426 /* defines for the RequestFlags field */
427 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
428 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */
429 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
430 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
431 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
432 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
433 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
434 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
435 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
437 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
440 /* High Priority Request Descriptor */
441 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
443 U8 RequestFlags; /* 0x00 */
444 U8 MSIxIndex; /* 0x01 */
447 U16 Reserved1; /* 0x06 */
448 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
449 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
450 Mpi2HighPriorityRequestDescriptor_t,
451 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
454 /* SCSI IO Request Descriptor */
455 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
457 U8 RequestFlags; /* 0x00 */
458 U8 MSIxIndex; /* 0x01 */
461 U16 DevHandle; /* 0x06 */
462 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
463 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
464 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
467 /* SCSI Target Request Descriptor */
468 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
470 U8 RequestFlags; /* 0x00 */
471 U8 MSIxIndex; /* 0x01 */
474 U16 IoIndex; /* 0x06 */
475 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
476 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
477 Mpi2SCSITargetRequestDescriptor_t,
478 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
481 /* RAID Accelerator Request Descriptor */
482 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
484 U8 RequestFlags; /* 0x00 */
485 U8 MSIxIndex; /* 0x01 */
488 U16 Reserved; /* 0x06 */
489 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
490 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
491 Mpi2RAIDAcceleratorRequestDescriptor_t,
492 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
495 /* Fast Path SCSI IO Request Descriptor */
496 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
497 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
498 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
499 Mpi25FastPathSCSIIORequestDescriptor_t,
500 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
503 /* PCIe Encapsulated Request Descriptor */
504 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
505 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
506 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
507 Mpi26PCIeEncapsulatedRequestDescriptor_t,
508 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t;
511 /* union of Request Descriptors */
512 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
514 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
515 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
516 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
517 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
518 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
519 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
520 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
522 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
523 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
526 /* Atomic Request Descriptors */
529 * All Atomic Request Descriptors have the same format, so the following
530 * structure is used for all Atomic Request Descriptors:
531 * Atomic Default Request Descriptor
532 * Atomic High Priority Request Descriptor
533 * Atomic SCSI IO Request Descriptor
534 * Atomic SCSI Target Request Descriptor
535 * Atomic RAID Accelerator Request Descriptor
536 * Atomic Fast Path SCSI IO Request Descriptor
537 * Atomic PCIe Encapsulated Request Descriptor
540 /* Atomic Request Descriptor */
541 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR
543 U8 RequestFlags; /* 0x00 */
544 U8 MSIxIndex; /* 0x01 */
546 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
547 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
548 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t;
550 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */
553 /* Reply Descriptors */
555 /* Default Reply Descriptor */
556 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
558 U8 ReplyFlags; /* 0x00 */
559 U8 MSIxIndex; /* 0x01 */
560 U16 DescriptorTypeDependent1; /* 0x02 */
561 U32 DescriptorTypeDependent2; /* 0x04 */
562 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
563 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
565 /* defines for the ReplyFlags field */
566 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
567 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
568 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
569 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
570 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
571 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
572 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
573 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
574 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
576 /* values for marking a reply descriptor as unused */
577 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
578 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
580 /* Address Reply Descriptor */
581 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
583 U8 ReplyFlags; /* 0x00 */
584 U8 MSIxIndex; /* 0x01 */
586 U32 ReplyFrameAddress; /* 0x04 */
587 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
588 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
590 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
593 /* SCSI IO Success Reply Descriptor */
594 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
596 U8 ReplyFlags; /* 0x00 */
597 U8 MSIxIndex; /* 0x01 */
599 U16 TaskTag; /* 0x04 */
600 U16 Reserved1; /* 0x06 */
601 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
602 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
603 Mpi2SCSIIOSuccessReplyDescriptor_t,
604 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
607 /* TargetAssist Success Reply Descriptor */
608 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
610 U8 ReplyFlags; /* 0x00 */
611 U8 MSIxIndex; /* 0x01 */
613 U8 SequenceNumber; /* 0x04 */
614 U8 Reserved1; /* 0x05 */
615 U16 IoIndex; /* 0x06 */
616 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
617 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
618 Mpi2TargetAssistSuccessReplyDescriptor_t,
619 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
622 /* Target Command Buffer Reply Descriptor */
623 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
625 U8 ReplyFlags; /* 0x00 */
626 U8 MSIxIndex; /* 0x01 */
629 U16 InitiatorDevHandle; /* 0x04 */
630 U16 IoIndex; /* 0x06 */
631 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
632 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
633 Mpi2TargetCommandBufferReplyDescriptor_t,
634 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
636 /* defines for Flags field */
637 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
640 /* RAID Accelerator Success Reply Descriptor */
641 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
643 U8 ReplyFlags; /* 0x00 */
644 U8 MSIxIndex; /* 0x01 */
646 U32 Reserved; /* 0x04 */
647 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
648 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
649 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
650 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
653 /* Fast Path SCSI IO Success Reply Descriptor */
654 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
655 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
656 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
657 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
658 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
661 /* PCIe Encapsulated Success Reply Descriptor */
662 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
663 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
664 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
665 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
666 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
669 /* union of Reply Descriptors */
670 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
672 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
673 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
674 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
675 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
676 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
677 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
678 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
679 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess;
681 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
682 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
686 /*****************************************************************************
690 *****************************************************************************/
692 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
693 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
694 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
695 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
696 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
697 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
698 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
699 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
700 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
701 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
702 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
703 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
704 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
705 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
706 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
707 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
708 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
709 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
710 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
711 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */
712 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */
713 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
714 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
715 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
716 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
717 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
718 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
719 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
720 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
721 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
722 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */
723 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
724 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
728 /* Doorbell functions */
729 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
730 #define MPI2_FUNCTION_HANDSHAKE (0x42)
733 /*****************************************************************************
737 *****************************************************************************/
739 /* mask for IOCStatus status value */
740 #define MPI2_IOCSTATUS_MASK (0x7FFF)
742 /****************************************************************************
743 * Common IOCStatus values for all replies
744 ****************************************************************************/
746 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
747 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
748 #define MPI2_IOCSTATUS_BUSY (0x0002)
749 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
750 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
751 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
752 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
753 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
754 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
755 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
756 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */
758 /****************************************************************************
759 * Config IOCStatus values
760 ****************************************************************************/
762 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
763 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
764 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
765 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
766 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
767 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
769 /****************************************************************************
771 ****************************************************************************/
773 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
774 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
775 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
776 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
777 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
778 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
779 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
780 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
781 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
782 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
783 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
784 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
786 /****************************************************************************
787 * For use by SCSI Initiator and SCSI Target end-to-end data protection
788 ****************************************************************************/
790 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
791 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
792 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
794 /****************************************************************************
796 ****************************************************************************/
798 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
799 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
800 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
801 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
802 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
803 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
804 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
805 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
806 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
807 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
809 /****************************************************************************
810 * Serial Attached SCSI values
811 ****************************************************************************/
813 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
814 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
816 /****************************************************************************
817 * Diagnostic Buffer Post / Diagnostic Release values
818 ****************************************************************************/
820 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
822 /****************************************************************************
823 * RAID Accelerator values
824 ****************************************************************************/
826 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
828 /****************************************************************************
829 * IOCStatus flag to indicate that log info is available
830 ****************************************************************************/
832 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
834 /****************************************************************************
836 ****************************************************************************/
838 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
839 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
840 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
841 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
842 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
843 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
844 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
845 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
848 /*****************************************************************************
850 * Standard Message Structures
852 *****************************************************************************/
854 /****************************************************************************
855 * Request Message Header for all request messages
856 ****************************************************************************/
858 typedef struct _MPI2_REQUEST_HEADER
860 U16 FunctionDependent1; /* 0x00 */
861 U8 ChainOffset; /* 0x02 */
862 U8 Function; /* 0x03 */
863 U16 FunctionDependent2; /* 0x04 */
864 U8 FunctionDependent3; /* 0x06 */
865 U8 MsgFlags; /* 0x07 */
868 U16 Reserved1; /* 0x0A */
869 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
870 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
873 /****************************************************************************
875 ****************************************************************************/
877 typedef struct _MPI2_DEFAULT_REPLY
879 U16 FunctionDependent1; /* 0x00 */
880 U8 MsgLength; /* 0x02 */
881 U8 Function; /* 0x03 */
882 U16 FunctionDependent2; /* 0x04 */
883 U8 FunctionDependent3; /* 0x06 */
884 U8 MsgFlags; /* 0x07 */
887 U16 Reserved1; /* 0x0A */
888 U16 FunctionDependent5; /* 0x0C */
889 U16 IOCStatus; /* 0x0E */
890 U32 IOCLogInfo; /* 0x10 */
891 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
892 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
895 /* common version structure/union used in messages and configuration pages */
897 typedef struct _MPI2_VERSION_STRUCT
903 } MPI2_VERSION_STRUCT;
905 typedef union _MPI2_VERSION_UNION
907 MPI2_VERSION_STRUCT Struct;
909 } MPI2_VERSION_UNION;
912 /* LUN field defines, common to many structures */
913 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
914 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
915 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
916 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
917 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
918 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
921 /*****************************************************************************
923 * Fusion-MPT MPI Scatter Gather Elements
925 *****************************************************************************/
927 /****************************************************************************
928 * MPI Simple Element structures
929 ****************************************************************************/
931 typedef struct _MPI2_SGE_SIMPLE32
935 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
936 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
938 typedef struct _MPI2_SGE_SIMPLE64
942 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
943 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
945 typedef struct _MPI2_SGE_SIMPLE_UNION
953 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
954 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
957 /****************************************************************************
958 * MPI Chain Element structures - for MPI v2.0 products only
959 ****************************************************************************/
961 typedef struct _MPI2_SGE_CHAIN32
967 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
968 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
970 typedef struct _MPI2_SGE_CHAIN64
976 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
977 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
979 typedef struct _MPI2_SGE_CHAIN_UNION
989 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
990 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
993 /****************************************************************************
994 * MPI Transaction Context Element structures - for MPI v2.0 products only
995 ****************************************************************************/
997 typedef struct _MPI2_SGE_TRANSACTION32
1003 U32 TransactionContext[1];
1004 U32 TransactionDetails[1];
1005 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
1006 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
1008 typedef struct _MPI2_SGE_TRANSACTION64
1014 U32 TransactionContext[2];
1015 U32 TransactionDetails[1];
1016 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
1017 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
1019 typedef struct _MPI2_SGE_TRANSACTION96
1025 U32 TransactionContext[3];
1026 U32 TransactionDetails[1];
1027 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
1028 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
1030 typedef struct _MPI2_SGE_TRANSACTION128
1036 U32 TransactionContext[4];
1037 U32 TransactionDetails[1];
1038 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
1039 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
1041 typedef struct _MPI2_SGE_TRANSACTION_UNION
1049 U32 TransactionContext32[1];
1050 U32 TransactionContext64[2];
1051 U32 TransactionContext96[3];
1052 U32 TransactionContext128[4];
1054 U32 TransactionDetails[1];
1055 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
1056 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
1059 /****************************************************************************
1060 * MPI SGE union for IO SGL's - for MPI v2.0 products only
1061 ****************************************************************************/
1063 typedef struct _MPI2_MPI_SGE_IO_UNION
1067 MPI2_SGE_SIMPLE_UNION Simple;
1068 MPI2_SGE_CHAIN_UNION Chain;
1070 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
1071 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
1074 /****************************************************************************
1075 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1076 ****************************************************************************/
1078 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
1082 MPI2_SGE_SIMPLE_UNION Simple;
1083 MPI2_SGE_TRANSACTION_UNION Transaction;
1085 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1086 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
1089 /****************************************************************************
1090 * All MPI SGE types union
1091 ****************************************************************************/
1093 typedef struct _MPI2_MPI_SGE_UNION
1097 MPI2_SGE_SIMPLE_UNION Simple;
1098 MPI2_SGE_CHAIN_UNION Chain;
1099 MPI2_SGE_TRANSACTION_UNION Transaction;
1101 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
1102 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
1105 /****************************************************************************
1106 * MPI SGE field definition and masks
1107 ****************************************************************************/
1109 /* Flags field bit definitions */
1111 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1112 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1113 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1114 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1115 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1116 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1117 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1119 #define MPI2_SGE_FLAGS_SHIFT (24)
1121 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1122 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1126 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */
1127 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1128 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */
1129 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1131 /* Address location */
1133 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1137 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1138 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1140 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1141 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1145 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1146 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1150 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1151 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1152 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1153 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1155 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1156 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1158 /****************************************************************************
1159 * MPI SGE operation Macros
1160 ****************************************************************************/
1162 /* SIMPLE FlagsLength manipulations... */
1163 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1164 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
1165 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1166 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1168 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
1170 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1171 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1172 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
1174 /* CAUTION - The following are READ-MODIFY-WRITE! */
1175 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1176 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1178 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1181 /*****************************************************************************
1183 * Fusion-MPT IEEE Scatter Gather Elements
1185 *****************************************************************************/
1187 /****************************************************************************
1188 * IEEE Simple Element structures
1189 ****************************************************************************/
1191 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1192 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1196 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1197 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1199 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1206 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1207 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1209 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1211 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1212 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1213 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1214 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1217 /****************************************************************************
1218 * IEEE Chain Element structures
1219 ****************************************************************************/
1221 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1222 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1224 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1225 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1227 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1229 MPI2_IEEE_SGE_CHAIN32 Chain32;
1230 MPI2_IEEE_SGE_CHAIN64 Chain64;
1231 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1232 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1234 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1235 typedef struct _MPI25_IEEE_SGE_CHAIN64
1242 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1243 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1246 /****************************************************************************
1247 * All IEEE SGE types union
1248 ****************************************************************************/
1250 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1251 typedef struct _MPI2_IEEE_SGE_UNION
1255 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1256 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1258 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1259 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1262 /****************************************************************************
1263 * IEEE SGE union for IO SGL's
1264 ****************************************************************************/
1266 typedef union _MPI25_SGE_IO_UNION
1268 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1269 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1270 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION,
1271 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t;
1274 /****************************************************************************
1275 * IEEE SGE field definitions and masks
1276 ****************************************************************************/
1278 /* Flags field bit definitions */
1280 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1281 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1283 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1285 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1289 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1290 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1292 /* Next Segment Format */
1294 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1295 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1296 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1297 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1299 /* Data Location Address Space */
1301 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1302 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */
1303 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1304 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1305 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1306 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1307 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1309 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */
1311 /****************************************************************************
1312 * IEEE SGE operation Macros
1313 ****************************************************************************/
1315 /* SIMPLE FlagsLength manipulations... */
1316 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1317 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1318 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1320 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1322 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1323 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1324 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1326 /* CAUTION - The following are READ-MODIFY-WRITE! */
1327 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1328 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1332 /*****************************************************************************
1334 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1336 *****************************************************************************/
1338 typedef union _MPI2_SIMPLE_SGE_UNION
1340 MPI2_SGE_SIMPLE_UNION MpiSimple;
1341 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1342 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1343 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1346 typedef union _MPI2_SGE_IO_UNION
1348 MPI2_SGE_SIMPLE_UNION MpiSimple;
1349 MPI2_SGE_CHAIN_UNION MpiChain;
1350 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1351 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1352 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1353 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1356 /****************************************************************************
1358 * Values for SGLFlags field, used in many request messages with an SGL
1360 ****************************************************************************/
1362 /* values for MPI SGL Data Location Address Space subfield */
1363 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1364 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1365 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1366 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */
1367 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */
1368 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */
1369 /* values for SGL Type subfield */
1370 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1371 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1372 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1373 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)