2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
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5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
34 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
38 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
39 * Creation Date: October 11, 2006
41 * mpi2_ioc.h Version: 02.00.36
43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
44 * prefix are for use only on MPI v2.5 products, and must not be used
45 * with MPI v2.0 products. Unless otherwise noted, names beginning with
46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
51 * Date Version Description
52 * -------- -------- ------------------------------------------------------
53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
54 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
56 * Added TotalImageSize field to FWDownload Request.
57 * Added reserved words to FWUpload Request.
58 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
59 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
60 * request and replaced it with
61 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
62 * Replaced the MinReplyQueueDepth field of the IOCFacts
63 * reply with MaxReplyDescriptorPostQueueDepth.
64 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
65 * depth for the Reply Descriptor Post Queue.
66 * Added SASAddress field to Initiator Device Table
67 * Overflow Event data.
68 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
69 * for SAS Initiator Device Status Change Event data.
70 * Modified Reason Code defines for SAS Topology Change
71 * List Event data, including adding a bit for PHY Vacant
72 * status, and adding a mask for the Reason Code.
74 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
75 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
76 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
78 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
79 * Moved MPI2_VERSION_UNION to mpi2.h.
80 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
81 * instead of enables, and added SASBroadcastPrimitiveMasks
83 * Added Log Entry Added Event and related structure.
84 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
85 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
86 * Added MaxVolumes and MaxPersistentEntries fields to
88 * Added ProtocalFlags and IOCCapabilities fields to
89 * MPI2_FW_IMAGE_HEADER.
90 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
91 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
93 * Removed extra 's' from EventMasks name.
94 * 06-27-08 02.00.08 Fixed an offset in a comment.
95 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
96 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
97 * renamed MinReplyFrameSize to ReplyFrameSize.
98 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
99 * Added two new RAIDOperation values for Integrated RAID
100 * Operations Status Event data.
101 * Added four new IR Configuration Change List Event data
103 * Added two new ReasonCode defines for SAS Device Status
105 * Added three new DiscoveryStatus bits for the SAS
106 * Discovery event data.
107 * Added Multiplexing Status Change bit to the PhyStatus
108 * field of the SAS Topology Change List event data.
109 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
110 * BootFlags are now product-specific.
111 * Added defines for the indivdual signature bytes
112 * for MPI2_INIT_IMAGE_FOOTER.
113 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
114 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
116 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
118 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
119 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
120 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
121 * Added two new reason codes for SAS Device Status Change
123 * Added new event: SAS PHY Counter.
124 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
125 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
126 * Added new product id family for 2208.
127 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
128 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
129 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
130 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
131 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
132 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
133 * Added Host Based Discovery Phy Event data.
134 * Added defines for ProductID Product field
135 * (MPI2_FW_HEADER_PID_).
136 * Modified values for SAS ProductID Family
137 * (MPI2_FW_HEADER_PID_FAMILY_).
138 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
139 * Added PowerManagementControl Request structures and
141 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
142 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
143 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
144 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
145 * SASNotifyPrimitiveMasks field to
146 * MPI2_EVENT_NOTIFICATION_REQUEST.
147 * Added Temperature Threshold Event.
148 * Added Host Message Event.
149 * Added Send Host Message request and reply.
150 * 05-25-11 02.00.18 For Extended Image Header, added
151 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
152 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
153 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
154 * 08-24-11 02.00.19 Added PhysicalPort field to
155 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
156 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
157 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
158 * 03-29-12 02.00.21 Added a product specific range to event values.
159 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
160 * Added ElapsedSeconds field to
161 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
162 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
163 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
164 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
165 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
166 * Added Encrypted Hash Extended Image.
167 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
168 * 11-18-14 02.00.25 Updated copyright information.
169 * 03-16-15 02.00.26 Updated for MPI v2.6.
170 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
171 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
172 * Added MPI2_EVENT_PCIE_LINK_COUNTER and
173 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER.
174 * Added MPI26_CTRL_OP_SHUTDOWN.
175 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG
176 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
177 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
178 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
179 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
180 * Added ConigurationFlags field to IOCInit message to
181 * support NVMe SGL format control.
182 * Added PCIe SRIOV support.
183 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
184 * Added PCIe 4 16.0 GT/sec speec support.
185 * Removed AHCI support.
186 * Removed SOP support.
187 * 07-01-16 02.00.29 Added Archclass for 4008 product.
188 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
189 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
191 * Added new defines for the ImageType field of FWUpload
193 * Added new values for the RegionType field in the Layout
194 * Data sections of the FLASH Layout Extended Image Data.
195 * Added new defines for the ReasonCode field of
196 * Active Cable Exception Event.
197 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
198 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
199 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
200 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
201 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
202 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
203 * defines for the ReasonCode field.
204 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
205 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
206 * to the ReasonCode field in PCIe Device Status Change
208 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
209 * Moved FW image definitions ionto new mpi2_image,h
210 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
211 * --------------------------------------------------------------------------
217 /*****************************************************************************
221 *****************************************************************************/
223 /****************************************************************************
225 ****************************************************************************/
227 /* IOCInit Request message */
228 typedef struct _MPI2_IOC_INIT_REQUEST
230 U8 WhoInit; /* 0x00 */
231 U8 Reserved1; /* 0x01 */
232 U8 ChainOffset; /* 0x02 */
233 U8 Function; /* 0x03 */
234 U16 Reserved2; /* 0x04 */
235 U8 Reserved3; /* 0x06 */
236 U8 MsgFlags; /* 0x07 */
239 U16 Reserved4; /* 0x0A */
240 U16 MsgVersion; /* 0x0C */
241 U16 HeaderVersion; /* 0x0E */
242 U32 Reserved5; /* 0x10 */
243 U16 ConfigurationFlags; /* 0x14 */
244 U8 HostPageSize; /* 0x16 */
245 U8 HostMSIxVectors; /* 0x17 */
246 U16 Reserved8; /* 0x18 */
247 U16 SystemRequestFrameSize; /* 0x1A */
248 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
249 U16 ReplyFreeQueueDepth; /* 0x1E */
250 U32 SenseBufferAddressHigh; /* 0x20 */
251 U32 SystemReplyAddressHigh; /* 0x24 */
252 U64 SystemRequestFrameBaseAddress; /* 0x28 */
253 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
254 U64 ReplyFreeQueueAddress; /* 0x38 */
255 U64 TimeStamp; /* 0x40 */
256 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
257 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
260 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
261 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
262 #define MPI2_WHOINIT_ROM_BIOS (0x02)
263 #define MPI2_WHOINIT_PCI_PEER (0x03)
264 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
265 #define MPI2_WHOINIT_MANUFACTURER (0x05)
268 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
271 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
272 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
273 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
274 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
277 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
278 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
279 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
280 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
282 /* ConfigurationFlags */
283 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
285 /* minimum depth for a Reply Descriptor Post Queue */
286 #define MPI2_RDPQ_DEPTH_MIN (16)
288 /* Reply Descriptor Post Queue Array Entry */
289 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY
291 U64 RDPQBaseAddress; /* 0x00 */
292 U32 Reserved1; /* 0x08 */
293 U32 Reserved2; /* 0x0C */
294 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
295 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
296 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
298 /* IOCInit Reply message */
299 typedef struct _MPI2_IOC_INIT_REPLY
301 U8 WhoInit; /* 0x00 */
302 U8 Reserved1; /* 0x01 */
303 U8 MsgLength; /* 0x02 */
304 U8 Function; /* 0x03 */
305 U16 Reserved2; /* 0x04 */
306 U8 Reserved3; /* 0x06 */
307 U8 MsgFlags; /* 0x07 */
310 U16 Reserved4; /* 0x0A */
311 U16 Reserved5; /* 0x0C */
312 U16 IOCStatus; /* 0x0E */
313 U32 IOCLogInfo; /* 0x10 */
314 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
315 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
318 /****************************************************************************
320 ****************************************************************************/
322 /* IOCFacts Request message */
323 typedef struct _MPI2_IOC_FACTS_REQUEST
325 U16 Reserved1; /* 0x00 */
326 U8 ChainOffset; /* 0x02 */
327 U8 Function; /* 0x03 */
328 U16 Reserved2; /* 0x04 */
329 U8 Reserved3; /* 0x06 */
330 U8 MsgFlags; /* 0x07 */
333 U16 Reserved4; /* 0x0A */
334 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
335 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
338 /* IOCFacts Reply message */
339 typedef struct _MPI2_IOC_FACTS_REPLY
341 U16 MsgVersion; /* 0x00 */
342 U8 MsgLength; /* 0x02 */
343 U8 Function; /* 0x03 */
344 U16 HeaderVersion; /* 0x04 */
345 U8 IOCNumber; /* 0x06 */
346 U8 MsgFlags; /* 0x07 */
349 U16 Reserved1; /* 0x0A */
350 U16 IOCExceptions; /* 0x0C */
351 U16 IOCStatus; /* 0x0E */
352 U32 IOCLogInfo; /* 0x10 */
353 U8 MaxChainDepth; /* 0x14 */
354 U8 WhoInit; /* 0x15 */
355 U8 NumberOfPorts; /* 0x16 */
356 U8 MaxMSIxVectors; /* 0x17 */
357 U16 RequestCredit; /* 0x18 */
358 U16 ProductID; /* 0x1A */
359 U32 IOCCapabilities; /* 0x1C */
360 MPI2_VERSION_UNION FWVersion; /* 0x20 */
361 U16 IOCRequestFrameSize; /* 0x24 */
362 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */
363 U16 MaxInitiators; /* 0x28 */
364 U16 MaxTargets; /* 0x2A */
365 U16 MaxSasExpanders; /* 0x2C */
366 U16 MaxEnclosures; /* 0x2E */
367 U16 ProtocolFlags; /* 0x30 */
368 U16 HighPriorityCredit; /* 0x32 */
369 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
370 U8 ReplyFrameSize; /* 0x36 */
371 U8 MaxVolumes; /* 0x37 */
372 U16 MaxDevHandle; /* 0x38 */
373 U16 MaxPersistentEntries; /* 0x3A */
374 U16 MinDevHandle; /* 0x3C */
375 U8 CurrentHostPageSize; /* 0x3E */
376 U8 Reserved4; /* 0x3F */
377 U8 SGEModifierMask; /* 0x40 */
378 U8 SGEModifierValue; /* 0x41 */
379 U8 SGEModifierShift; /* 0x42 */
380 U8 Reserved5; /* 0x43 */
381 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
382 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
385 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
386 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
387 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
388 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
391 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
392 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
393 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
394 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
397 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
398 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
399 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
401 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
402 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
403 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
404 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
405 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
407 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
408 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
409 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
410 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
411 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
413 /* defines for WhoInit field are after the IOCInit Request */
415 /* ProductID field uses MPI2_FW_HEADER_PID_ */
417 /* IOCCapabilities */
418 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
419 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
420 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
421 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
422 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
423 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
424 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
425 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
426 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
427 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
428 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
429 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
430 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
431 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
432 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
433 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
434 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
437 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */
438 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
439 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
442 /****************************************************************************
444 ****************************************************************************/
446 /* PortFacts Request message */
447 typedef struct _MPI2_PORT_FACTS_REQUEST
449 U16 Reserved1; /* 0x00 */
450 U8 ChainOffset; /* 0x02 */
451 U8 Function; /* 0x03 */
452 U16 Reserved2; /* 0x04 */
453 U8 PortNumber; /* 0x06 */
454 U8 MsgFlags; /* 0x07 */
457 U16 Reserved3; /* 0x0A */
458 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
459 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
461 /* PortFacts Reply message */
462 typedef struct _MPI2_PORT_FACTS_REPLY
464 U16 Reserved1; /* 0x00 */
465 U8 MsgLength; /* 0x02 */
466 U8 Function; /* 0x03 */
467 U16 Reserved2; /* 0x04 */
468 U8 PortNumber; /* 0x06 */
469 U8 MsgFlags; /* 0x07 */
472 U16 Reserved3; /* 0x0A */
473 U16 Reserved4; /* 0x0C */
474 U16 IOCStatus; /* 0x0E */
475 U32 IOCLogInfo; /* 0x10 */
476 U8 Reserved5; /* 0x14 */
477 U8 PortType; /* 0x15 */
478 U16 Reserved6; /* 0x16 */
479 U16 MaxPostedCmdBuffers; /* 0x18 */
480 U16 Reserved7; /* 0x1A */
481 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
482 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
484 /* PortType values */
485 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
486 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
487 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
488 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
489 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
490 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */
493 /****************************************************************************
495 ****************************************************************************/
497 /* PortEnable Request message */
498 typedef struct _MPI2_PORT_ENABLE_REQUEST
500 U16 Reserved1; /* 0x00 */
501 U8 ChainOffset; /* 0x02 */
502 U8 Function; /* 0x03 */
503 U8 Reserved2; /* 0x04 */
504 U8 PortFlags; /* 0x05 */
505 U8 Reserved3; /* 0x06 */
506 U8 MsgFlags; /* 0x07 */
509 U16 Reserved4; /* 0x0A */
510 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
511 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
514 /* PortEnable Reply message */
515 typedef struct _MPI2_PORT_ENABLE_REPLY
517 U16 Reserved1; /* 0x00 */
518 U8 MsgLength; /* 0x02 */
519 U8 Function; /* 0x03 */
520 U8 Reserved2; /* 0x04 */
521 U8 PortFlags; /* 0x05 */
522 U8 Reserved3; /* 0x06 */
523 U8 MsgFlags; /* 0x07 */
526 U16 Reserved4; /* 0x0A */
527 U16 Reserved5; /* 0x0C */
528 U16 IOCStatus; /* 0x0E */
529 U32 IOCLogInfo; /* 0x10 */
530 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
531 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
534 /****************************************************************************
535 * EventNotification message
536 ****************************************************************************/
538 /* EventNotification Request message */
539 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
541 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
543 U16 Reserved1; /* 0x00 */
544 U8 ChainOffset; /* 0x02 */
545 U8 Function; /* 0x03 */
546 U16 Reserved2; /* 0x04 */
547 U8 Reserved3; /* 0x06 */
548 U8 MsgFlags; /* 0x07 */
551 U16 Reserved4; /* 0x0A */
552 U32 Reserved5; /* 0x0C */
553 U32 Reserved6; /* 0x10 */
554 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
555 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
556 U16 SASNotifyPrimitiveMasks; /* 0x26 */
557 U32 Reserved8; /* 0x28 */
558 } MPI2_EVENT_NOTIFICATION_REQUEST,
559 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
560 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
563 /* EventNotification Reply message */
564 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
566 U16 EventDataLength; /* 0x00 */
567 U8 MsgLength; /* 0x02 */
568 U8 Function; /* 0x03 */
569 U16 Reserved1; /* 0x04 */
570 U8 AckRequired; /* 0x06 */
571 U8 MsgFlags; /* 0x07 */
574 U16 Reserved2; /* 0x0A */
575 U16 Reserved3; /* 0x0C */
576 U16 IOCStatus; /* 0x0E */
577 U32 IOCLogInfo; /* 0x10 */
578 U16 Event; /* 0x14 */
579 U16 Reserved4; /* 0x16 */
580 U32 EventContext; /* 0x18 */
581 U32 EventData[1]; /* 0x1C */
582 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
583 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
586 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
587 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
590 #define MPI2_EVENT_LOG_DATA (0x0001)
591 #define MPI2_EVENT_STATE_CHANGE (0x0002)
592 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
593 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
594 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
595 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
596 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
597 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
598 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
599 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
600 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
601 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
602 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
603 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */
604 #define MPI2_EVENT_IR_VOLUME (0x001E)
605 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
606 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
607 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
608 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
609 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
610 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
611 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
612 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
613 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
614 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
615 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
616 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */
617 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */
618 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */
619 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */
620 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */
621 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035) /* MPI v2.5 and later */
622 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
623 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
626 /* Log Entry Added Event data */
628 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
629 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
631 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
633 U64 TimeStamp; /* 0x00 */
634 U32 Reserved1; /* 0x08 */
635 U16 LogSequence; /* 0x0C */
636 U16 LogEntryQualifier; /* 0x0E */
639 U16 Reserved2; /* 0x12 */
640 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
641 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
642 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
643 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
646 /* GPIO Interrupt Event data */
648 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
650 U8 GPIONum; /* 0x00 */
651 U8 Reserved1; /* 0x01 */
652 U16 Reserved2; /* 0x02 */
653 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
654 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
655 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
658 /* Temperature Threshold Event data */
660 typedef struct _MPI2_EVENT_DATA_TEMPERATURE
662 U16 Status; /* 0x00 */
663 U8 SensorNum; /* 0x02 */
664 U8 Reserved1; /* 0x03 */
665 U16 CurrentTemperature; /* 0x04 */
666 U16 Reserved2; /* 0x06 */
667 U32 Reserved3; /* 0x08 */
668 U32 Reserved4; /* 0x0C */
669 } MPI2_EVENT_DATA_TEMPERATURE,
670 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
671 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
673 /* Temperature Threshold Event data Status bits */
674 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
675 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
676 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
677 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
680 /* Host Message Event data */
682 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE
684 U8 SourceVF_ID; /* 0x00 */
685 U8 Reserved1; /* 0x01 */
686 U16 Reserved2; /* 0x02 */
687 U32 Reserved3; /* 0x04 */
688 U32 HostData[1]; /* 0x08 */
689 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
690 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
693 /* Power Performance Change Event data */
695 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
697 U8 CurrentPowerMode; /* 0x00 */
698 U8 PreviousPowerMode; /* 0x01 */
699 U16 Reserved1; /* 0x02 */
700 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
701 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
702 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t;
704 /* defines for CurrentPowerMode and PreviousPowerMode fields */
705 #define MPI2_EVENT_PM_INIT_MASK (0xC0)
706 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
707 #define MPI2_EVENT_PM_INIT_HOST (0x40)
708 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
709 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
711 #define MPI2_EVENT_PM_MODE_MASK (0x07)
712 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
713 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
714 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
715 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
716 #define MPI2_EVENT_PM_MODE_STANDBY (0x06)
719 /* Active Cable Exception Event data */
721 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT
723 U32 ActiveCablePowerRequirement; /* 0x00 */
724 U8 ReasonCode; /* 0x04 */
725 U8 ReceptacleID; /* 0x05 */
726 U16 Reserved1; /* 0x06 */
727 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
728 MPI2_POINTER PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
729 Mpi25EventDataActiveCableExcept_t,
730 MPI2_POINTER pMpi25EventDataActiveCableExcept_t,
731 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
732 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
733 Mpi26EventDataActiveCableExcept_t,
734 MPI2_POINTER pMpi26EventDataActiveCableExcept_t;
736 /* MPI2.5 defines for the ReasonCode field */
737 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
738 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
739 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
741 /* MPI2.6 defines for the ReasonCode field */
742 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
743 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
744 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
746 /* Hard Reset Received Event data */
748 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
750 U8 Reserved1; /* 0x00 */
752 U16 Reserved2; /* 0x02 */
753 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
754 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
755 Mpi2EventDataHardResetReceived_t,
756 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
759 /* Task Set Full Event data */
760 /* this event is obsolete */
762 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
764 U16 DevHandle; /* 0x00 */
765 U16 CurrentDepth; /* 0x02 */
766 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
767 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
770 /* SAS Device Status Change Event data */
772 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
774 U16 TaskTag; /* 0x00 */
775 U8 ReasonCode; /* 0x02 */
776 U8 PhysicalPort; /* 0x03 */
779 U16 DevHandle; /* 0x06 */
780 U32 Reserved2; /* 0x08 */
781 U64 SASAddress; /* 0x0C */
782 U8 LUN[8]; /* 0x14 */
783 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
784 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
785 Mpi2EventDataSasDeviceStatusChange_t,
786 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
788 /* SAS Device Status Change Event data ReasonCode values */
789 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
790 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
791 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
792 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
793 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
794 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
795 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
796 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
797 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
798 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
799 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
800 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
801 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
804 /* Integrated RAID Operation Status Event data */
806 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
808 U16 VolDevHandle; /* 0x00 */
809 U16 Reserved1; /* 0x02 */
810 U8 RAIDOperation; /* 0x04 */
811 U8 PercentComplete; /* 0x05 */
812 U16 Reserved2; /* 0x06 */
813 U32 ElapsedSeconds; /* 0x08 */
814 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
815 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
816 Mpi2EventDataIrOperationStatus_t,
817 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
819 /* Integrated RAID Operation Status Event data RAIDOperation values */
820 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
821 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
822 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
823 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
824 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
827 /* Integrated RAID Volume Event data */
829 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
831 U16 VolDevHandle; /* 0x00 */
832 U8 ReasonCode; /* 0x02 */
833 U8 Reserved1; /* 0x03 */
834 U32 NewValue; /* 0x04 */
835 U32 PreviousValue; /* 0x08 */
836 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
837 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
839 /* Integrated RAID Volume Event data ReasonCode values */
840 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
841 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
842 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
845 /* Integrated RAID Physical Disk Event data */
847 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
849 U16 Reserved1; /* 0x00 */
850 U8 ReasonCode; /* 0x02 */
851 U8 PhysDiskNum; /* 0x03 */
852 U16 PhysDiskDevHandle; /* 0x04 */
853 U16 Reserved2; /* 0x06 */
855 U16 EnclosureHandle; /* 0x0A */
856 U32 NewValue; /* 0x0C */
857 U32 PreviousValue; /* 0x10 */
858 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
859 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
860 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
862 /* Integrated RAID Physical Disk Event data ReasonCode values */
863 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
864 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
865 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
868 /* Integrated RAID Configuration Change List Event data */
871 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
872 * one and check NumElements at runtime.
874 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
875 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
878 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
880 U16 ElementFlags; /* 0x00 */
881 U16 VolDevHandle; /* 0x02 */
882 U8 ReasonCode; /* 0x04 */
883 U8 PhysDiskNum; /* 0x05 */
884 U16 PhysDiskDevHandle; /* 0x06 */
885 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
886 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
888 /* IR Configuration Change List Event data ElementFlags values */
889 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
890 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
891 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
892 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
894 /* IR Configuration Change List Event data ReasonCode values */
895 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
896 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
897 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
898 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
899 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
900 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
901 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
902 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
903 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
905 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
907 U8 NumElements; /* 0x00 */
908 U8 Reserved1; /* 0x01 */
909 U8 Reserved2; /* 0x02 */
910 U8 ConfigNum; /* 0x03 */
911 U32 Flags; /* 0x04 */
912 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
913 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
914 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
915 Mpi2EventDataIrConfigChangeList_t,
916 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
918 /* IR Configuration Change List Event data Flags values */
919 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
922 /* SAS Discovery Event data */
924 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
927 U8 ReasonCode; /* 0x01 */
928 U8 PhysicalPort; /* 0x02 */
929 U8 Reserved1; /* 0x03 */
930 U32 DiscoveryStatus; /* 0x04 */
931 } MPI2_EVENT_DATA_SAS_DISCOVERY,
932 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
933 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
935 /* SAS Discovery Event data Flags values */
936 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
937 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
939 /* SAS Discovery Event data ReasonCode values */
940 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
941 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
943 /* SAS Discovery Event data DiscoveryStatus values */
944 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
945 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
946 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
947 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
948 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
949 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
950 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
951 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
952 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
953 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
954 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
955 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
956 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
957 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
958 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
959 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
960 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
961 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
962 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
963 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
966 /* SAS Broadcast Primitive Event data */
968 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
970 U8 PhyNum; /* 0x00 */
972 U8 PortWidth; /* 0x02 */
973 U8 Primitive; /* 0x03 */
974 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
975 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
976 Mpi2EventDataSasBroadcastPrimitive_t,
977 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
979 /* defines for the Primitive field */
980 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
981 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
982 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
983 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
984 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
985 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
986 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
987 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
990 /* SAS Notify Primitive Event data */
992 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE
994 U8 PhyNum; /* 0x00 */
996 U8 Reserved1; /* 0x02 */
997 U8 Primitive; /* 0x03 */
998 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
999 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
1000 Mpi2EventDataSasNotifyPrimitive_t,
1001 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
1003 /* defines for the Primitive field */
1004 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
1005 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
1006 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
1007 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
1010 /* SAS Initiator Device Status Change Event data */
1012 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
1014 U8 ReasonCode; /* 0x00 */
1015 U8 PhysicalPort; /* 0x01 */
1016 U16 DevHandle; /* 0x02 */
1017 U64 SASAddress; /* 0x04 */
1018 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
1019 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
1020 Mpi2EventDataSasInitDevStatusChange_t,
1021 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
1023 /* SAS Initiator Device Status Change event ReasonCode values */
1024 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
1025 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
1028 /* SAS Initiator Device Table Overflow Event data */
1030 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
1032 U16 MaxInit; /* 0x00 */
1033 U16 CurrentInit; /* 0x02 */
1034 U64 SASAddress; /* 0x04 */
1035 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
1036 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
1037 Mpi2EventDataSasInitTableOverflow_t,
1038 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
1041 /* SAS Topology Change List Event data */
1044 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1045 * one and check NumEntries at runtime.
1047 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
1048 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
1051 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
1053 U16 AttachedDevHandle; /* 0x00 */
1054 U8 LinkRate; /* 0x02 */
1055 U8 PhyStatus; /* 0x03 */
1056 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
1057 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
1059 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
1061 U16 EnclosureHandle; /* 0x00 */
1062 U16 ExpanderDevHandle; /* 0x02 */
1063 U8 NumPhys; /* 0x04 */
1064 U8 Reserved1; /* 0x05 */
1065 U16 Reserved2; /* 0x06 */
1066 U8 NumEntries; /* 0x08 */
1067 U8 StartPhyNum; /* 0x09 */
1068 U8 ExpStatus; /* 0x0A */
1069 U8 PhysicalPort; /* 0x0B */
1070 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
1071 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
1072 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
1073 Mpi2EventDataSasTopologyChangeList_t,
1074 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
1076 /* values for the ExpStatus field */
1077 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
1078 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
1079 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
1080 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
1081 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
1083 /* defines for the LinkRate field */
1084 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
1085 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
1086 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1087 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1089 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1090 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1091 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1092 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1093 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1094 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1095 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1096 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1097 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1098 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1099 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1100 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1102 /* values for the PhyStatus field */
1103 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1104 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1105 /* values for the PhyStatus ReasonCode sub-field */
1106 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1107 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1108 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1109 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1110 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1111 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1114 /* SAS Enclosure Device Status Change Event data */
1116 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
1118 U16 EnclosureHandle; /* 0x00 */
1119 U8 ReasonCode; /* 0x02 */
1120 U8 PhysicalPort; /* 0x03 */
1121 U64 EnclosureLogicalID; /* 0x04 */
1122 U16 NumSlots; /* 0x0C */
1123 U16 StartSlot; /* 0x0E */
1124 U32 PhyBits; /* 0x10 */
1125 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1126 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1127 Mpi2EventDataSasEnclDevStatusChange_t,
1128 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t,
1129 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1130 MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1131 Mpi26EventDataEnclDevStatusChange_t,
1132 MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t;
1134 /* SAS Enclosure Device Status Change event ReasonCode values */
1135 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1136 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1138 /* Enclosure Device Status Change event ReasonCode values */
1139 #define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1140 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1142 /* SAS PHY Counter Event data */
1144 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
1146 U64 TimeStamp; /* 0x00 */
1147 U32 Reserved1; /* 0x08 */
1148 U8 PhyEventCode; /* 0x0C */
1149 U8 PhyNum; /* 0x0D */
1150 U16 Reserved2; /* 0x0E */
1151 U32 PhyEventInfo; /* 0x10 */
1152 U8 CounterType; /* 0x14 */
1153 U8 ThresholdWindow; /* 0x15 */
1154 U8 TimeUnits; /* 0x16 */
1155 U8 Reserved3; /* 0x17 */
1156 U32 EventThreshold; /* 0x18 */
1157 U16 ThresholdFlags; /* 0x1C */
1158 U16 Reserved4; /* 0x1E */
1159 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1160 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1161 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
1163 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
1165 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
1167 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
1169 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
1172 /* SAS Quiesce Event data */
1174 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
1176 U8 ReasonCode; /* 0x00 */
1177 U8 Reserved1; /* 0x01 */
1178 U16 Reserved2; /* 0x02 */
1179 U32 Reserved3; /* 0x04 */
1180 } MPI2_EVENT_DATA_SAS_QUIESCE,
1181 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1182 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1184 /* SAS Quiesce Event data ReasonCode values */
1185 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1186 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1189 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR
1191 U16 DevHandle; /* 0x00 */
1192 U8 ReasonCode; /* 0x02 */
1193 U8 PhysicalPort; /* 0x03 */
1194 U32 Reserved1[2]; /* 0x04 */
1195 U64 SASAddress; /* 0x0C */
1196 U32 Reserved2[2]; /* 0x14 */
1197 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1198 MPI2_POINTER PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1199 Mpi25EventDataSasDeviceDiscoveryError_t,
1200 MPI2_POINTER pMpi25EventDataSasDeviceDiscoveryError_t;
1202 /* SAS Device Discovery Error Event data ReasonCode values */
1203 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1204 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1207 /* Host Based Discovery Phy Event data */
1209 typedef struct _MPI2_EVENT_HBD_PHY_SAS
1211 U8 Flags; /* 0x00 */
1212 U8 NegotiatedLinkRate; /* 0x01 */
1213 U8 PhyNum; /* 0x02 */
1214 U8 PhysicalPort; /* 0x03 */
1215 U32 Reserved1; /* 0x04 */
1216 U8 InitialFrame[28]; /* 0x08 */
1217 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1218 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1220 /* values for the Flags field */
1221 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1222 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1224 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
1226 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
1228 MPI2_EVENT_HBD_PHY_SAS Sas;
1229 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1230 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1232 typedef struct _MPI2_EVENT_DATA_HBD_PHY
1234 U8 DescriptorType; /* 0x00 */
1235 U8 Reserved1; /* 0x01 */
1236 U16 Reserved2; /* 0x02 */
1237 U32 Reserved3; /* 0x04 */
1238 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1239 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1240 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1242 /* values for the DescriptorType field */
1243 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1246 /* PCIe Device Status Change Event data (MPI v2.6 and later) */
1248 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE
1250 U16 TaskTag; /* 0x00 */
1251 U8 ReasonCode; /* 0x02 */
1252 U8 PhysicalPort; /* 0x03 */
1255 U16 DevHandle; /* 0x06 */
1256 U32 Reserved2; /* 0x08 */
1257 U64 WWID; /* 0x0C */
1258 U8 LUN[8]; /* 0x14 */
1259 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1260 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1261 Mpi26EventDataPCIeDeviceStatusChange_t,
1262 MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t;
1264 /* PCIe Device Status Change Event data ReasonCode values */
1265 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1266 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1267 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1268 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1269 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1270 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1271 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1272 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1273 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1274 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1275 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1276 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11)
1279 /* PCIe Enumeration Event data (MPI v2.6 and later) */
1281 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION
1283 U8 Flags; /* 0x00 */
1284 U8 ReasonCode; /* 0x01 */
1285 U8 PhysicalPort; /* 0x02 */
1286 U8 Reserved1; /* 0x03 */
1287 U32 EnumerationStatus; /* 0x04 */
1288 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
1289 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1290 Mpi26EventDataPCIeEnumeration_t,
1291 MPI2_POINTER pMpi26EventDataPCIeEnumeration_t;
1293 /* PCIe Enumeration Event data Flags values */
1294 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1295 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1297 /* PCIe Enumeration Event data ReasonCode values */
1298 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1299 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1301 /* PCIe Enumeration Event data EnumerationStatus values */
1302 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1303 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1304 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1307 /* PCIe Topology Change List Event data (MPI v2.6 and later) */
1310 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1311 * one and check NumEntries at runtime.
1313 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1314 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
1317 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1319 U16 AttachedDevHandle; /* 0x00 */
1320 U8 PortStatus; /* 0x02 */
1321 U8 Reserved1; /* 0x03 */
1322 U8 CurrentPortInfo; /* 0x04 */
1323 U8 Reserved2; /* 0x05 */
1324 U8 PreviousPortInfo; /* 0x06 */
1325 U8 Reserved3; /* 0x07 */
1326 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1327 MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1328 Mpi26EventPCIeTopoPortEntry_t,
1329 MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t;
1331 /* PCIe Topology Change List Event data PortStatus values */
1332 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1333 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1334 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1335 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1336 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1338 /* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */
1339 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1340 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1341 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1342 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1343 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1344 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1346 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1347 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1348 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1349 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1350 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1351 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1352 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1354 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST
1356 U16 EnclosureHandle; /* 0x00 */
1357 U16 SwitchDevHandle; /* 0x02 */
1358 U8 NumPorts; /* 0x04 */
1359 U8 Reserved1; /* 0x05 */
1360 U16 Reserved2; /* 0x06 */
1361 U8 NumEntries; /* 0x08 */
1362 U8 StartPortNum; /* 0x09 */
1363 U8 SwitchStatus; /* 0x0A */
1364 U8 PhysicalPort; /* 0x0B */
1365 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */
1366 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1367 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1368 Mpi26EventDataPCIeTopologyChangeList_t,
1369 MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t;
1371 /* PCIe Topology Change List Event data SwitchStatus values */
1372 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1373 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1374 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1375 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1376 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1378 /* PCIe Link Counter Event data (MPI v2.6 and later) */
1380 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER
1382 U64 TimeStamp; /* 0x00 */
1383 U32 Reserved1; /* 0x08 */
1384 U8 LinkEventCode; /* 0x0C */
1385 U8 LinkNum; /* 0x0D */
1386 U16 Reserved2; /* 0x0E */
1387 U32 LinkEventInfo; /* 0x10 */
1388 U8 CounterType; /* 0x14 */
1389 U8 ThresholdWindow; /* 0x15 */
1390 U8 TimeUnits; /* 0x16 */
1391 U8 Reserved3; /* 0x17 */
1392 U32 EventThreshold; /* 0x18 */
1393 U16 ThresholdFlags; /* 0x1C */
1394 U16 Reserved4; /* 0x1E */
1395 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1396 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1397 Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t;
1400 /* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */
1402 /* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
1404 /* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
1406 /* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
1408 /****************************************************************************
1410 ****************************************************************************/
1412 /* EventAck Request message */
1413 typedef struct _MPI2_EVENT_ACK_REQUEST
1415 U16 Reserved1; /* 0x00 */
1416 U8 ChainOffset; /* 0x02 */
1417 U8 Function; /* 0x03 */
1418 U16 Reserved2; /* 0x04 */
1419 U8 Reserved3; /* 0x06 */
1420 U8 MsgFlags; /* 0x07 */
1421 U8 VP_ID; /* 0x08 */
1422 U8 VF_ID; /* 0x09 */
1423 U16 Reserved4; /* 0x0A */
1424 U16 Event; /* 0x0C */
1425 U16 Reserved5; /* 0x0E */
1426 U32 EventContext; /* 0x10 */
1427 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1428 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1431 /* EventAck Reply message */
1432 typedef struct _MPI2_EVENT_ACK_REPLY
1434 U16 Reserved1; /* 0x00 */
1435 U8 MsgLength; /* 0x02 */
1436 U8 Function; /* 0x03 */
1437 U16 Reserved2; /* 0x04 */
1438 U8 Reserved3; /* 0x06 */
1439 U8 MsgFlags; /* 0x07 */
1440 U8 VP_ID; /* 0x08 */
1441 U8 VF_ID; /* 0x09 */
1442 U16 Reserved4; /* 0x0A */
1443 U16 Reserved5; /* 0x0C */
1444 U16 IOCStatus; /* 0x0E */
1445 U32 IOCLogInfo; /* 0x10 */
1446 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1447 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1450 /****************************************************************************
1451 * SendHostMessage message
1452 ****************************************************************************/
1454 /* SendHostMessage Request message */
1455 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST
1457 U16 HostDataLength; /* 0x00 */
1458 U8 ChainOffset; /* 0x02 */
1459 U8 Function; /* 0x03 */
1460 U16 Reserved1; /* 0x04 */
1461 U8 Reserved2; /* 0x06 */
1462 U8 MsgFlags; /* 0x07 */
1463 U8 VP_ID; /* 0x08 */
1464 U8 VF_ID; /* 0x09 */
1465 U16 Reserved3; /* 0x0A */
1466 U8 Reserved4; /* 0x0C */
1467 U8 DestVF_ID; /* 0x0D */
1468 U16 Reserved5; /* 0x0E */
1469 U32 Reserved6; /* 0x10 */
1470 U32 Reserved7; /* 0x14 */
1471 U32 Reserved8; /* 0x18 */
1472 U32 Reserved9; /* 0x1C */
1473 U32 Reserved10; /* 0x20 */
1474 U32 HostData[1]; /* 0x24 */
1475 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1476 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1477 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1480 /* SendHostMessage Reply message */
1481 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY
1483 U16 HostDataLength; /* 0x00 */
1484 U8 MsgLength; /* 0x02 */
1485 U8 Function; /* 0x03 */
1486 U16 Reserved1; /* 0x04 */
1487 U8 Reserved2; /* 0x06 */
1488 U8 MsgFlags; /* 0x07 */
1489 U8 VP_ID; /* 0x08 */
1490 U8 VF_ID; /* 0x09 */
1491 U16 Reserved3; /* 0x0A */
1492 U16 Reserved4; /* 0x0C */
1493 U16 IOCStatus; /* 0x0E */
1494 U32 IOCLogInfo; /* 0x10 */
1495 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1496 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1499 /****************************************************************************
1500 * FWDownload message
1501 ****************************************************************************/
1503 /* MPI v2.0 FWDownload Request message */
1504 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1506 U8 ImageType; /* 0x00 */
1507 U8 Reserved1; /* 0x01 */
1508 U8 ChainOffset; /* 0x02 */
1509 U8 Function; /* 0x03 */
1510 U16 Reserved2; /* 0x04 */
1511 U8 Reserved3; /* 0x06 */
1512 U8 MsgFlags; /* 0x07 */
1513 U8 VP_ID; /* 0x08 */
1514 U8 VF_ID; /* 0x09 */
1515 U16 Reserved4; /* 0x0A */
1516 U32 TotalImageSize; /* 0x0C */
1517 U32 Reserved5; /* 0x10 */
1518 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1519 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1520 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1522 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1524 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1525 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1526 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1527 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1528 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1529 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1530 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1531 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1532 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */
1533 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1534 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1535 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1536 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1537 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1538 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1539 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1540 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1541 #define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15) /* MPI v2.6 and newer */
1542 #define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) /* MPI v2.6 and newer */
1543 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1544 #define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF) /* MPI v2.6 and newer */
1547 /* MPI v2.0 FWDownload TransactionContext Element */
1548 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1550 U8 Reserved1; /* 0x00 */
1551 U8 ContextSize; /* 0x01 */
1552 U8 DetailsLength; /* 0x02 */
1553 U8 Flags; /* 0x03 */
1554 U32 Reserved2; /* 0x04 */
1555 U32 ImageOffset; /* 0x08 */
1556 U32 ImageSize; /* 0x0C */
1557 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1558 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1561 /* MPI v2.5 FWDownload Request message */
1562 typedef struct _MPI25_FW_DOWNLOAD_REQUEST
1564 U8 ImageType; /* 0x00 */
1565 U8 Reserved1; /* 0x01 */
1566 U8 ChainOffset; /* 0x02 */
1567 U8 Function; /* 0x03 */
1568 U16 Reserved2; /* 0x04 */
1569 U8 Reserved3; /* 0x06 */
1570 U8 MsgFlags; /* 0x07 */
1571 U8 VP_ID; /* 0x08 */
1572 U8 VF_ID; /* 0x09 */
1573 U16 Reserved4; /* 0x0A */
1574 U32 TotalImageSize; /* 0x0C */
1575 U32 Reserved5; /* 0x10 */
1576 U32 Reserved6; /* 0x14 */
1577 U32 ImageOffset; /* 0x18 */
1578 U32 ImageSize; /* 0x1C */
1579 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1580 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
1581 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
1584 /* FWDownload Reply message */
1585 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1587 U8 ImageType; /* 0x00 */
1588 U8 Reserved1; /* 0x01 */
1589 U8 MsgLength; /* 0x02 */
1590 U8 Function; /* 0x03 */
1591 U16 Reserved2; /* 0x04 */
1592 U8 Reserved3; /* 0x06 */
1593 U8 MsgFlags; /* 0x07 */
1594 U8 VP_ID; /* 0x08 */
1595 U8 VF_ID; /* 0x09 */
1596 U16 Reserved4; /* 0x0A */
1597 U16 Reserved5; /* 0x0C */
1598 U16 IOCStatus; /* 0x0E */
1599 U32 IOCLogInfo; /* 0x10 */
1600 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1601 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1604 /****************************************************************************
1606 ****************************************************************************/
1608 /* MPI v2.0 FWUpload Request message */
1609 typedef struct _MPI2_FW_UPLOAD_REQUEST
1611 U8 ImageType; /* 0x00 */
1612 U8 Reserved1; /* 0x01 */
1613 U8 ChainOffset; /* 0x02 */
1614 U8 Function; /* 0x03 */
1615 U16 Reserved2; /* 0x04 */
1616 U8 Reserved3; /* 0x06 */
1617 U8 MsgFlags; /* 0x07 */
1618 U8 VP_ID; /* 0x08 */
1619 U8 VF_ID; /* 0x09 */
1620 U16 Reserved4; /* 0x0A */
1621 U32 Reserved5; /* 0x0C */
1622 U32 Reserved6; /* 0x10 */
1623 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1624 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1625 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1627 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1628 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1629 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1630 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1631 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1632 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1633 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1634 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1635 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1636 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1637 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1638 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1639 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1640 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1641 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1642 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1643 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1644 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1646 /* MPI v2.0 FWUpload TransactionContext Element */
1647 typedef struct _MPI2_FW_UPLOAD_TCSGE
1649 U8 Reserved1; /* 0x00 */
1650 U8 ContextSize; /* 0x01 */
1651 U8 DetailsLength; /* 0x02 */
1652 U8 Flags; /* 0x03 */
1653 U32 Reserved2; /* 0x04 */
1654 U32 ImageOffset; /* 0x08 */
1655 U32 ImageSize; /* 0x0C */
1656 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1657 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1660 /* MPI v2.5 FWUpload Request message */
1661 typedef struct _MPI25_FW_UPLOAD_REQUEST
1663 U8 ImageType; /* 0x00 */
1664 U8 Reserved1; /* 0x01 */
1665 U8 ChainOffset; /* 0x02 */
1666 U8 Function; /* 0x03 */
1667 U16 Reserved2; /* 0x04 */
1668 U8 Reserved3; /* 0x06 */
1669 U8 MsgFlags; /* 0x07 */
1670 U8 VP_ID; /* 0x08 */
1671 U8 VF_ID; /* 0x09 */
1672 U16 Reserved4; /* 0x0A */
1673 U32 Reserved5; /* 0x0C */
1674 U32 Reserved6; /* 0x10 */
1675 U32 Reserved7; /* 0x14 */
1676 U32 ImageOffset; /* 0x18 */
1677 U32 ImageSize; /* 0x1C */
1678 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1679 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
1680 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
1683 /* FWUpload Reply message */
1684 typedef struct _MPI2_FW_UPLOAD_REPLY
1686 U8 ImageType; /* 0x00 */
1687 U8 Reserved1; /* 0x01 */
1688 U8 MsgLength; /* 0x02 */
1689 U8 Function; /* 0x03 */
1690 U16 Reserved2; /* 0x04 */
1691 U8 Reserved3; /* 0x06 */
1692 U8 MsgFlags; /* 0x07 */
1693 U8 VP_ID; /* 0x08 */
1694 U8 VF_ID; /* 0x09 */
1695 U16 Reserved4; /* 0x0A */
1696 U16 Reserved5; /* 0x0C */
1697 U16 IOCStatus; /* 0x0E */
1698 U32 IOCLogInfo; /* 0x10 */
1699 U32 ActualImageSize; /* 0x14 */
1700 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1701 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1704 /****************************************************************************
1705 * PowerManagementControl message
1706 ****************************************************************************/
1708 /* PowerManagementControl Request message */
1709 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
1711 U8 Feature; /* 0x00 */
1712 U8 Reserved1; /* 0x01 */
1713 U8 ChainOffset; /* 0x02 */
1714 U8 Function; /* 0x03 */
1715 U16 Reserved2; /* 0x04 */
1716 U8 Reserved3; /* 0x06 */
1717 U8 MsgFlags; /* 0x07 */
1718 U8 VP_ID; /* 0x08 */
1719 U8 VF_ID; /* 0x09 */
1720 U16 Reserved4; /* 0x0A */
1721 U8 Parameter1; /* 0x0C */
1722 U8 Parameter2; /* 0x0D */
1723 U8 Parameter3; /* 0x0E */
1724 U8 Parameter4; /* 0x0F */
1725 U32 Reserved5; /* 0x10 */
1726 U32 Reserved6; /* 0x14 */
1727 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1728 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1730 /* defines for the Feature field */
1731 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1732 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1733 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
1734 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1735 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */
1736 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1737 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1739 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1740 /* Parameter1 contains a PHY number */
1741 /* Parameter2 indicates power condition action using these defines */
1742 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1743 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1744 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1745 /* Parameter3 and Parameter4 are reserved */
1747 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
1748 /* Parameter1 contains SAS port width modulation group number */
1749 /* Parameter2 indicates IOC action using these defines */
1750 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1751 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1752 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1753 /* Parameter3 indicates desired modulation level using these defines */
1754 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1755 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1756 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1757 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1758 /* Parameter4 is reserved */
1760 /* this next set (_PCIE_LINK) is obsolete */
1761 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1762 /* Parameter1 indicates desired PCIe link speed using these defines */
1763 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
1764 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
1765 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
1766 /* Parameter2 indicates desired PCIe link width using these defines */
1767 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
1768 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
1769 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
1770 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
1771 /* Parameter3 and Parameter4 are reserved */
1773 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1774 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1775 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1776 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1777 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1778 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1779 /* Parameter2, Parameter3, and Parameter4 are reserved */
1781 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */
1782 /* Parameter1 indicates host action regarding global power management mode */
1783 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1784 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1785 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1786 /* Parameter2 indicates the requested global power management mode */
1787 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1788 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1789 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1790 /* Parameter3 and Parameter4 are reserved */
1793 /* PowerManagementControl Reply message */
1794 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
1796 U8 Feature; /* 0x00 */
1797 U8 Reserved1; /* 0x01 */
1798 U8 MsgLength; /* 0x02 */
1799 U8 Function; /* 0x03 */
1800 U16 Reserved2; /* 0x04 */
1801 U8 Reserved3; /* 0x06 */
1802 U8 MsgFlags; /* 0x07 */
1803 U8 VP_ID; /* 0x08 */
1804 U8 VF_ID; /* 0x09 */
1805 U16 Reserved4; /* 0x0A */
1806 U16 Reserved5; /* 0x0C */
1807 U16 IOCStatus; /* 0x0E */
1808 U32 IOCLogInfo; /* 0x10 */
1809 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1810 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1813 /****************************************************************************
1814 * IO Unit Control messages (MPI v2.6 and later only.)
1815 ****************************************************************************/
1817 /* IO Unit Control Request Message */
1818 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST
1820 U8 Operation; /* 0x00 */
1821 U8 Reserved1; /* 0x01 */
1822 U8 ChainOffset; /* 0x02 */
1823 U8 Function; /* 0x03 */
1824 U16 DevHandle; /* 0x04 */
1825 U8 IOCParameter; /* 0x06 */
1826 U8 MsgFlags; /* 0x07 */
1827 U8 VP_ID; /* 0x08 */
1828 U8 VF_ID; /* 0x09 */
1829 U16 Reserved3; /* 0x0A */
1830 U16 Reserved4; /* 0x0C */
1831 U8 PhyNum; /* 0x0E */
1832 U8 PrimFlags; /* 0x0F */
1833 U32 Primitive; /* 0x10 */
1834 U8 LookupMethod; /* 0x14 */
1835 U8 Reserved5; /* 0x15 */
1836 U16 SlotNumber; /* 0x16 */
1837 U64 LookupAddress; /* 0x18 */
1838 U32 IOCParameterValue; /* 0x20 */
1839 U32 Reserved7; /* 0x24 */
1840 U32 Reserved8; /* 0x28 */
1841 } MPI26_IOUNIT_CONTROL_REQUEST,
1842 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1843 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t;
1845 /* values for the Operation field */
1846 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
1847 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
1848 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
1849 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
1850 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
1851 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
1852 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
1853 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
1854 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
1855 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
1856 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
1857 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
1858 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
1859 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
1860 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
1861 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
1862 #define MPI26_CTRL_OP_SHUTDOWN (0x16)
1863 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
1864 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
1865 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
1866 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
1867 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
1868 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
1870 /* values for the PrimFlags field */
1871 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
1872 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
1873 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
1875 /* values for the LookupMethod field */
1876 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1877 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1878 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1881 /* IO Unit Control Reply Message */
1882 typedef struct _MPI26_IOUNIT_CONTROL_REPLY
1884 U8 Operation; /* 0x00 */
1885 U8 Reserved1; /* 0x01 */
1886 U8 MsgLength; /* 0x02 */
1887 U8 Function; /* 0x03 */
1888 U16 DevHandle; /* 0x04 */
1889 U8 IOCParameter; /* 0x06 */
1890 U8 MsgFlags; /* 0x07 */
1891 U8 VP_ID; /* 0x08 */
1892 U8 VF_ID; /* 0x09 */
1893 U16 Reserved3; /* 0x0A */
1894 U16 Reserved4; /* 0x0C */
1895 U16 IOCStatus; /* 0x0E */
1896 U32 IOCLogInfo; /* 0x10 */
1897 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY,
1898 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t;