2 * Copyright (c) 2009 Yahoo! Inc.
3 * Copyright (c) 2011-2015 LSI Corp.
4 * Copyright (c) 2013-2016 Avago Technologies
5 * Copyright 2000-2020 Broadcom Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 /* Communications core for Avago Technologies (LSI) MPT3 */
38 /* TODO Move headers to mprvar */
39 #include <sys/types.h>
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/selinfo.h>
45 #include <sys/mutex.h>
46 #include <sys/module.h>
50 #include <sys/malloc.h>
52 #include <sys/sysctl.h>
54 #include <sys/queue.h>
55 #include <sys/kthread.h>
56 #include <sys/taskqueue.h>
57 #include <sys/endian.h>
58 #include <sys/eventhandler.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <dev/pci/pcivar.h>
70 #include <cam/cam_ccb.h>
71 #include <cam/scsi/scsi_all.h>
73 #include <dev/mpr/mpi/mpi2_type.h>
74 #include <dev/mpr/mpi/mpi2.h>
75 #include <dev/mpr/mpi/mpi2_ioc.h>
76 #include <dev/mpr/mpi/mpi2_sas.h>
77 #include <dev/mpr/mpi/mpi2_pci.h>
78 #include <dev/mpr/mpi/mpi2_cnfg.h>
79 #include <dev/mpr/mpi/mpi2_init.h>
80 #include <dev/mpr/mpi/mpi2_tool.h>
81 #include <dev/mpr/mpr_ioctl.h>
82 #include <dev/mpr/mprvar.h>
83 #include <dev/mpr/mpr_table.h>
84 #include <dev/mpr/mpr_sas.h>
86 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag);
87 static int mpr_init_queues(struct mpr_softc *sc);
88 static void mpr_resize_queues(struct mpr_softc *sc);
89 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag);
90 static int mpr_transition_operational(struct mpr_softc *sc);
91 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching);
92 static void mpr_iocfacts_free(struct mpr_softc *sc);
93 static void mpr_startup(void *arg);
94 static int mpr_send_iocinit(struct mpr_softc *sc);
95 static int mpr_alloc_queues(struct mpr_softc *sc);
96 static int mpr_alloc_hw_queues(struct mpr_softc *sc);
97 static int mpr_alloc_replies(struct mpr_softc *sc);
98 static int mpr_alloc_requests(struct mpr_softc *sc);
99 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc);
100 static int mpr_attach_log(struct mpr_softc *sc);
101 static __inline void mpr_complete_command(struct mpr_softc *sc,
102 struct mpr_command *cm);
103 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
104 MPI2_EVENT_NOTIFICATION_REPLY *reply);
105 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm);
106 static void mpr_periodic(void *);
107 static int mpr_reregister_events(struct mpr_softc *sc);
108 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm);
109 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts);
110 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag);
111 static int mpr_debug_sysctl(SYSCTL_HANDLER_ARGS);
112 static int mpr_dump_reqs(SYSCTL_HANDLER_ARGS);
113 static void mpr_parse_debug(struct mpr_softc *sc, char *list);
115 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
116 "MPR Driver Parameters");
118 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory");
121 * Do a "Diagnostic Reset" aka a hard reset. This should get the chip out of
122 * any state and back to its initialization state machine.
124 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d };
127 * Added this union to smoothly convert le64toh cm->cm_desc.Words.
128 * Compiler only supports uint64_t to be passed as an argument.
129 * Otherwise it will throw this error:
130 * "aggregate value used where an integer was expected"
138 } request_descriptor_t;
140 /* Rate limit chain-fail messages to 1 per minute */
141 static struct timeval mpr_chainfail_interval = { 60, 0 };
144 * sleep_flag can be either CAN_SLEEP or NO_SLEEP.
145 * If this function is called from process context, it can sleep
146 * and there is no harm to sleep, in case if this fuction is called
147 * from Interrupt handler, we can not sleep and need NO_SLEEP flag set.
148 * based on sleep flags driver will call either msleep, pause or DELAY.
149 * msleep and pause are of same variant, but pause is used when mpr_mtx
150 * is not hold by driver.
153 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag)
156 int i, error, tries = 0;
157 uint8_t first_wait_done = FALSE;
159 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
161 /* Clear any pending interrupts */
162 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
165 * Force NO_SLEEP for threads prohibited to sleep
166 * e.a Thread from interrupt handler are prohibited to sleep.
168 if (curthread->td_no_sleeping)
169 sleep_flag = NO_SLEEP;
171 mpr_dprint(sc, MPR_INIT, "sequence start, sleep_flag=%d\n", sleep_flag);
172 /* Push the magic sequence */
174 while (tries++ < 20) {
175 for (i = 0; i < sizeof(mpt2_reset_magic); i++)
176 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET,
177 mpt2_reset_magic[i]);
180 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
181 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
183 else if (sleep_flag == CAN_SLEEP)
184 pause("mprdiag", hz/10);
188 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
189 if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {
195 mpr_dprint(sc, MPR_INIT, "sequence failed, error=%d, exit\n",
200 /* Send the actual reset. XXX need to refresh the reg? */
201 reg |= MPI2_DIAG_RESET_ADAPTER;
202 mpr_dprint(sc, MPR_INIT, "sequence success, sending reset, reg= 0x%x\n",
204 mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg);
206 /* Wait up to 300 seconds in 50ms intervals */
208 for (i = 0; i < 6000; i++) {
210 * Wait 50 msec. If this is the first time through, wait 256
211 * msec to satisfy Diag Reset timing requirements.
213 if (first_wait_done) {
214 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
215 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
217 else if (sleep_flag == CAN_SLEEP)
218 pause("mprdiag", hz/20);
223 first_wait_done = TRUE;
226 * Check for the RESET_ADAPTER bit to be cleared first, then
227 * wait for the RESET state to be cleared, which takes a little
230 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
231 if (reg & MPI2_DIAG_RESET_ADAPTER) {
234 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
235 if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {
241 mpr_dprint(sc, MPR_INIT, "reset failed, error= %d, exit\n",
246 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0);
247 mpr_dprint(sc, MPR_INIT, "diag reset success, exit\n");
253 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag)
259 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
262 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
263 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET <<
264 MPI2_DOORBELL_FUNCTION_SHIFT);
266 if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) {
267 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
268 "Doorbell handshake failed\n");
272 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
277 mpr_transition_ready(struct mpr_softc *sc)
280 int error, tries = 0;
284 /* If we are in attach call, do not sleep */
285 sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE)
286 ? CAN_SLEEP : NO_SLEEP;
290 mpr_dprint(sc, MPR_INIT, "%s entered, sleep_flags= %d\n",
291 __func__, sleep_flags);
293 while (tries++ < 1200) {
294 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
295 mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg);
298 * Ensure the IOC is ready to talk. If it's not, try
301 if (reg & MPI2_DOORBELL_USED) {
302 mpr_dprint(sc, MPR_INIT, " Not ready, sending diag "
304 mpr_diag_reset(sc, sleep_flags);
309 /* Is the adapter owned by another peer? */
310 if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==
311 (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) {
312 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC is under the "
313 "control of another peer host, aborting "
314 "initialization.\n");
319 state = reg & MPI2_IOC_STATE_MASK;
320 if (state == MPI2_IOC_STATE_READY) {
324 } else if (state == MPI2_IOC_STATE_FAULT) {
325 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC in fault "
326 "state 0x%x, resetting\n",
327 state & MPI2_DOORBELL_FAULT_CODE_MASK);
328 mpr_diag_reset(sc, sleep_flags);
329 } else if (state == MPI2_IOC_STATE_OPERATIONAL) {
330 /* Need to take ownership */
331 mpr_message_unit_reset(sc, sleep_flags);
332 } else if (state == MPI2_IOC_STATE_RESET) {
333 /* Wait a bit, IOC might be in transition */
334 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
335 "IOC in unexpected reset state\n");
337 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
338 "IOC in unknown state 0x%x\n", state);
343 /* Wait 50ms for things to settle down. */
348 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
349 "Cannot transition IOC to ready\n");
350 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
355 mpr_transition_operational(struct mpr_softc *sc)
363 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
364 mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg);
366 state = reg & MPI2_IOC_STATE_MASK;
367 if (state != MPI2_IOC_STATE_READY) {
368 mpr_dprint(sc, MPR_INIT, "IOC not ready\n");
369 if ((error = mpr_transition_ready(sc)) != 0) {
370 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
371 "failed to transition ready, exit\n");
376 error = mpr_send_iocinit(sc);
377 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
383 mpr_resize_queues(struct mpr_softc *sc)
385 u_int reqcr, prireqcr, maxio, sges_per_frame, chain_seg_size;
388 * Size the queues. Since the reply queues always need one free
389 * entry, we'll deduct one reply message here. The LSI documents
390 * suggest instead to add a count to the request queue, but I think
391 * that it's better to deduct from reply queue.
393 prireqcr = MAX(1, sc->max_prireqframes);
394 prireqcr = MIN(prireqcr, sc->facts->HighPriorityCredit);
396 reqcr = MAX(2, sc->max_reqframes);
397 reqcr = MIN(reqcr, sc->facts->RequestCredit);
399 sc->num_reqs = prireqcr + reqcr;
400 sc->num_prireqs = prireqcr;
401 sc->num_replies = MIN(sc->max_replyframes + sc->max_evtframes,
402 sc->facts->MaxReplyDescriptorPostQueueDepth) - 1;
404 /* Store the request frame size in bytes rather than as 32bit words */
405 sc->reqframesz = sc->facts->IOCRequestFrameSize * 4;
408 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to
409 * get the size of a Chain Frame. Previous versions use the size as a
410 * Request Frame for the Chain Frame size. If IOCMaxChainSegmentSize
411 * is 0, use the default value. The IOCMaxChainSegmentSize is the
412 * number of 16-byte elelements that can fit in a Chain Frame, which is
413 * the size of an IEEE Simple SGE.
415 if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) {
416 chain_seg_size = htole16(sc->facts->IOCMaxChainSegmentSize);
417 if (chain_seg_size == 0)
418 chain_seg_size = MPR_DEFAULT_CHAIN_SEG_SIZE;
419 sc->chain_frame_size = chain_seg_size *
420 MPR_MAX_CHAIN_ELEMENT_SIZE;
422 sc->chain_frame_size = sc->reqframesz;
426 * Max IO Size is Page Size * the following:
427 * ((SGEs per frame - 1 for chain element) * Max Chain Depth)
428 * + 1 for no chain needed in last frame
430 * If user suggests a Max IO size to use, use the smaller of the
431 * user's value and the calculated value as long as the user's
432 * value is larger than 0. The user's value is in pages.
434 sges_per_frame = sc->chain_frame_size/sizeof(MPI2_IEEE_SGE_SIMPLE64)-1;
435 maxio = (sges_per_frame * sc->facts->MaxChainDepth + 1) * PAGE_SIZE;
438 * If I/O size limitation requested then use it and pass up to CAM.
439 * If not, use maxphys as an optimization hint, but report HW limit.
441 if (sc->max_io_pages > 0) {
442 maxio = min(maxio, sc->max_io_pages * PAGE_SIZE);
446 maxio = min(maxio, maxphys);
449 sc->num_chains = (maxio / PAGE_SIZE + sges_per_frame - 2) /
450 sges_per_frame * reqcr;
451 if (sc->max_chains > 0 && sc->max_chains < sc->num_chains)
452 sc->num_chains = sc->max_chains;
455 * Figure out the number of MSIx-based queues. If the firmware or
456 * user has done something crazy and not allowed enough credit for
457 * the queues to be useful then don't enable multi-queue.
459 if (sc->facts->MaxMSIxVectors < 2)
462 if (sc->msi_msgs > 1) {
463 sc->msi_msgs = MIN(sc->msi_msgs, mp_ncpus);
464 sc->msi_msgs = MIN(sc->msi_msgs, sc->facts->MaxMSIxVectors);
465 if (sc->num_reqs / sc->msi_msgs < 2)
469 mpr_dprint(sc, MPR_INIT, "Sized queues to q=%d reqs=%d replies=%d\n",
470 sc->msi_msgs, sc->num_reqs, sc->num_replies);
474 * This is called during attach and when re-initializing due to a Diag Reset.
475 * IOC Facts is used to allocate many of the structures needed by the driver.
476 * If called from attach, de-allocation is not required because the driver has
477 * not allocated any structures yet, but if called from a Diag Reset, previously
478 * allocated structures based on IOC Facts will need to be freed and re-
479 * allocated bases on the latest IOC Facts.
482 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching)
485 Mpi2IOCFactsReply_t saved_facts;
486 uint8_t saved_mode, reallocating;
488 mpr_dprint(sc, MPR_INIT|MPR_TRACE, "%s entered\n", __func__);
490 /* Save old IOC Facts and then only reallocate if Facts have changed */
492 bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY));
496 * Get IOC Facts. In all cases throughout this function, panic if doing
497 * a re-initialization and only return the error if attaching so the OS
500 if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) {
502 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to get "
503 "IOC Facts with error %d, exit\n", error);
506 panic("%s failed to get IOC Facts with error %d\n",
511 MPR_DPRINT_PAGE(sc, MPR_XINFO, iocfacts, sc->facts);
513 snprintf(sc->fw_version, sizeof(sc->fw_version),
514 "%02d.%02d.%02d.%02d",
515 sc->facts->FWVersion.Struct.Major,
516 sc->facts->FWVersion.Struct.Minor,
517 sc->facts->FWVersion.Struct.Unit,
518 sc->facts->FWVersion.Struct.Dev);
520 snprintf(sc->msg_version, sizeof(sc->msg_version), "%d.%d",
521 (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK) >>
522 MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT,
523 (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MINOR_MASK) >>
524 MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT);
526 mpr_dprint(sc, MPR_INFO, "Firmware: %s, Driver: %s\n", sc->fw_version,
528 mpr_dprint(sc, MPR_INFO,
529 "IOCCapabilities: %b\n", sc->facts->IOCCapabilities,
530 "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf"
531 "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR"
532 "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc"
533 "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV");
536 * If the chip doesn't support event replay then a hard reset will be
537 * required to trigger a full discovery. Do the reset here then
538 * retransition to Ready. A hard reset might have already been done,
539 * but it doesn't hurt to do it again. Only do this if attaching, not
542 if (attaching && ((sc->facts->IOCCapabilities &
543 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0)) {
544 mpr_dprint(sc, MPR_INIT, "No event replay, resetting\n");
545 mpr_diag_reset(sc, NO_SLEEP);
546 if ((error = mpr_transition_ready(sc)) != 0) {
547 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to "
548 "transition to ready with error %d, exit\n",
555 * Set flag if IR Firmware is loaded. If the RAID Capability has
556 * changed from the previous IOC Facts, log a warning, but only if
557 * checking this after a Diag Reset and not during attach.
559 saved_mode = sc->ir_firmware;
560 if (sc->facts->IOCCapabilities &
561 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)
564 if (sc->ir_firmware != saved_mode) {
565 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "new IR/IT mode "
566 "in IOC Facts does not match previous mode\n");
570 /* Only deallocate and reallocate if relevant IOC Facts have changed */
571 reallocating = FALSE;
572 sc->mpr_flags &= ~MPR_FLAGS_REALLOCATED;
575 ((saved_facts.MsgVersion != sc->facts->MsgVersion) ||
576 (saved_facts.HeaderVersion != sc->facts->HeaderVersion) ||
577 (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) ||
578 (saved_facts.RequestCredit != sc->facts->RequestCredit) ||
579 (saved_facts.ProductID != sc->facts->ProductID) ||
580 (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) ||
581 (saved_facts.IOCRequestFrameSize !=
582 sc->facts->IOCRequestFrameSize) ||
583 (saved_facts.IOCMaxChainSegmentSize !=
584 sc->facts->IOCMaxChainSegmentSize) ||
585 (saved_facts.MaxTargets != sc->facts->MaxTargets) ||
586 (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) ||
587 (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) ||
588 (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) ||
589 (saved_facts.MaxReplyDescriptorPostQueueDepth !=
590 sc->facts->MaxReplyDescriptorPostQueueDepth) ||
591 (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) ||
592 (saved_facts.MaxVolumes != sc->facts->MaxVolumes) ||
593 (saved_facts.MaxPersistentEntries !=
594 sc->facts->MaxPersistentEntries))) {
597 /* Record that we reallocated everything */
598 sc->mpr_flags |= MPR_FLAGS_REALLOCATED;
602 * Some things should be done if attaching or re-allocating after a Diag
603 * Reset, but are not needed after a Diag Reset if the FW has not
606 if (attaching || reallocating) {
608 * Check if controller supports FW diag buffers and set flag to
611 if (sc->facts->IOCCapabilities &
612 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER)
613 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE].
615 if (sc->facts->IOCCapabilities &
616 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER)
617 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT].
619 if (sc->facts->IOCCapabilities &
620 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER)
621 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED].
625 * Set flags for some supported items.
627 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP)
628 sc->eedp_enabled = TRUE;
629 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR)
630 sc->control_TLR = TRUE;
631 if ((sc->facts->IOCCapabilities &
632 MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) &&
633 (sc->mpr_flags & MPR_FLAGS_SEA_IOC))
634 sc->atomic_desc_capable = TRUE;
636 mpr_resize_queues(sc);
639 * Initialize all Tail Queues
641 TAILQ_INIT(&sc->req_list);
642 TAILQ_INIT(&sc->high_priority_req_list);
643 TAILQ_INIT(&sc->chain_list);
644 TAILQ_INIT(&sc->prp_page_list);
645 TAILQ_INIT(&sc->tm_list);
649 * If doing a Diag Reset and the FW is significantly different
650 * (reallocating will be set above in IOC Facts comparison), then all
651 * buffers based on the IOC Facts will need to be freed before they are
655 mpr_iocfacts_free(sc);
656 mprsas_realloc_targets(sc, saved_facts.MaxTargets +
657 saved_facts.MaxVolumes);
661 * Any deallocation has been completed. Now start reallocating
662 * if needed. Will only need to reallocate if attaching or if the new
663 * IOC Facts are different from the previous IOC Facts after a Diag
664 * Reset. Targets have already been allocated above if needed.
667 while (attaching || reallocating) {
668 if ((error = mpr_alloc_hw_queues(sc)) != 0)
670 if ((error = mpr_alloc_replies(sc)) != 0)
672 if ((error = mpr_alloc_requests(sc)) != 0)
674 if ((error = mpr_alloc_queues(sc)) != 0)
679 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
680 "Failed to alloc queues with error %d\n", error);
685 /* Always initialize the queues */
686 bzero(sc->free_queue, sc->fqdepth * 4);
690 * Always get the chip out of the reset state, but only panic if not
691 * attaching. If attaching and there is an error, that is handled by
694 error = mpr_transition_operational(sc);
696 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to "
697 "transition to operational with error %d\n", error);
703 * Finish the queue initialization.
704 * These are set here instead of in mpr_init_queues() because the
705 * IOC resets these values during the state transition in
706 * mpr_transition_operational(). The free index is set to 1
707 * because the corresponding index in the IOC is set to 0, and the
708 * IOC treats the queues as full if both are set to the same value.
709 * Hence the reason that the queue can't hold all of the possible
712 sc->replypostindex = 0;
713 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
714 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0);
717 * Attach the subsystems so they can prepare their event masks.
718 * XXX Should be dynamic so that IM/IR and user modules can attach
722 mpr_dprint(sc, MPR_INIT, "Attaching subsystems\n");
723 if ((error = mpr_attach_log(sc)) != 0)
725 if ((error = mpr_attach_sas(sc)) != 0)
727 if ((error = mpr_attach_user(sc)) != 0)
732 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
733 "Failed to attach all subsystems: error %d\n", error);
739 * XXX If the number of MSI-X vectors changes during re-init, this
740 * won't see it and adjust.
742 if (attaching && (error = mpr_pci_setup_interrupts(sc)) != 0) {
743 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
744 "Failed to setup interrupts\n");
753 * This is called if memory is being free (during detach for example) and when
754 * buffers need to be reallocated due to a Diag Reset.
757 mpr_iocfacts_free(struct mpr_softc *sc)
759 struct mpr_command *cm;
762 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
764 if (sc->free_busaddr != 0)
765 bus_dmamap_unload(sc->queues_dmat, sc->queues_map);
766 if (sc->free_queue != NULL)
767 bus_dmamem_free(sc->queues_dmat, sc->free_queue,
769 if (sc->queues_dmat != NULL)
770 bus_dma_tag_destroy(sc->queues_dmat);
772 if (sc->chain_frames != NULL) {
773 bus_dmamap_unload(sc->chain_dmat, sc->chain_map);
774 bus_dmamem_free(sc->chain_dmat, sc->chain_frames,
777 if (sc->chain_dmat != NULL)
778 bus_dma_tag_destroy(sc->chain_dmat);
780 if (sc->sense_busaddr != 0)
781 bus_dmamap_unload(sc->sense_dmat, sc->sense_map);
782 if (sc->sense_frames != NULL)
783 bus_dmamem_free(sc->sense_dmat, sc->sense_frames,
785 if (sc->sense_dmat != NULL)
786 bus_dma_tag_destroy(sc->sense_dmat);
788 if (sc->prp_page_busaddr != 0)
789 bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map);
790 if (sc->prp_pages != NULL)
791 bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages,
793 if (sc->prp_page_dmat != NULL)
794 bus_dma_tag_destroy(sc->prp_page_dmat);
796 if (sc->reply_busaddr != 0)
797 bus_dmamap_unload(sc->reply_dmat, sc->reply_map);
798 if (sc->reply_frames != NULL)
799 bus_dmamem_free(sc->reply_dmat, sc->reply_frames,
801 if (sc->reply_dmat != NULL)
802 bus_dma_tag_destroy(sc->reply_dmat);
804 if (sc->req_busaddr != 0)
805 bus_dmamap_unload(sc->req_dmat, sc->req_map);
806 if (sc->req_frames != NULL)
807 bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map);
808 if (sc->req_dmat != NULL)
809 bus_dma_tag_destroy(sc->req_dmat);
811 if (sc->chains != NULL)
812 free(sc->chains, M_MPR);
813 if (sc->prps != NULL)
814 free(sc->prps, M_MPR);
815 if (sc->commands != NULL) {
816 for (i = 1; i < sc->num_reqs; i++) {
817 cm = &sc->commands[i];
818 bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap);
820 free(sc->commands, M_MPR);
822 if (sc->buffer_dmat != NULL)
823 bus_dma_tag_destroy(sc->buffer_dmat);
825 mpr_pci_free_interrupts(sc);
826 free(sc->queues, M_MPR);
831 * The terms diag reset and hard reset are used interchangeably in the MPI
832 * docs to mean resetting the controller chip. In this code diag reset
833 * cleans everything up, and the hard reset function just sends the reset
834 * sequence to the chip. This should probably be refactored so that every
835 * subsystem gets a reset notification of some sort, and can clean up
839 mpr_reinit(struct mpr_softc *sc)
842 struct mprsas_softc *sassc;
848 mtx_assert(&sc->mpr_mtx, MA_OWNED);
850 mpr_dprint(sc, MPR_INIT|MPR_INFO, "Reinitializing controller\n");
851 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) {
852 mpr_dprint(sc, MPR_INIT, "Reset already in progress\n");
857 * Make sure the completion callbacks can recognize they're getting
858 * a NULL cm_reply due to a reset.
860 sc->mpr_flags |= MPR_FLAGS_DIAGRESET;
863 * Mask interrupts here.
865 mpr_dprint(sc, MPR_INIT, "Masking interrupts and resetting\n");
868 error = mpr_diag_reset(sc, CAN_SLEEP);
870 panic("%s hard reset failed with error %d\n", __func__, error);
873 /* Restore the PCI state, including the MSI-X registers */
876 /* Give the I/O subsystem special priority to get itself prepared */
877 mprsas_handle_reinit(sc);
880 * Get IOC Facts and allocate all structures based on this information.
881 * The attach function will also call mpr_iocfacts_allocate at startup.
882 * If relevant values have changed in IOC Facts, this function will free
883 * all of the memory based on IOC Facts and reallocate that memory.
885 if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) {
886 panic("%s IOC Facts based allocation failed with error %d\n",
891 * Mapping structures will be re-allocated after getting IOC Page8, so
892 * free these structures here.
894 mpr_mapping_exit(sc);
897 * The static page function currently read is IOC Page8. Others can be
898 * added in future. It's possible that the values in IOC Page8 have
899 * changed after a Diag Reset due to user modification, so always read
900 * these. Interrupts are masked, so unmask them before getting config
904 sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET;
905 mpr_base_static_config_pages(sc);
908 * Some mapping info is based in IOC Page8 data, so re-initialize the
911 mpr_mapping_initialize(sc);
914 * Restart will reload the event masks clobbered by the reset, and
915 * then enable the port.
917 mpr_reregister_events(sc);
919 /* the end of discovery will release the simq, so we're done. */
920 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Finished sc %p post %u free %u\n",
921 sc, sc->replypostindex, sc->replyfreeindex);
922 mprsas_release_simq_reinit(sassc);
923 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error);
928 /* Wait for the chip to ACK a word that we've put into its FIFO
929 * Wait for <timeout> seconds. In single loop wait for busy loop
930 * for 500 microseconds.
931 * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds.
934 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag)
941 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
943 int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
944 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
945 mpr_dprint(sc, MPR_TRACE, "%s: successful count(%d), "
946 "timeout(%d)\n", __func__, count, timeout);
948 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
949 doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
950 if ((doorbell & MPI2_IOC_STATE_MASK) ==
951 MPI2_IOC_STATE_FAULT) {
952 mpr_dprint(sc, MPR_FAULT,
953 "fault_state(0x%04x)!\n", doorbell);
956 } else if (int_status == 0xFFFFFFFF)
960 * If it can sleep, sleep for 1 milisecond, else busy loop for
963 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
964 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba",
966 else if (sleep_flag == CAN_SLEEP)
967 pause("mprdba", hz/1000);
974 mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), "
975 "int_status(%x)!\n", __func__, count, int_status);
979 /* Wait for the chip to signal that the next word in its FIFO can be fetched */
981 mpr_wait_db_int(struct mpr_softc *sc)
985 for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) {
986 if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) &
987 MPI2_HIS_IOC2SYS_DB_STATUS) != 0)
994 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */
996 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply,
997 int req_sz, int reply_sz, int timeout)
1001 int i, count, ioc_sz, residual;
1002 int sleep_flags = CAN_SLEEP;
1004 if (curthread->td_no_sleeping)
1005 sleep_flags = NO_SLEEP;
1008 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1011 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
1015 * Announce that a message is coming through the doorbell. Messages
1016 * are pushed at 32bit words, so round up if needed.
1018 count = (req_sz + 3) / 4;
1019 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
1020 (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) |
1021 (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT));
1024 if (mpr_wait_db_int(sc) ||
1025 (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) {
1026 mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n");
1029 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1030 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
1031 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n");
1036 /* Clock out the message data synchronously in 32-bit dwords*/
1037 data32 = (uint32_t *)req;
1038 for (i = 0; i < count; i++) {
1039 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i]));
1040 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
1041 mpr_dprint(sc, MPR_FAULT,
1042 "Timeout while writing doorbell\n");
1048 /* Clock in the reply in 16-bit words. The total length of the
1049 * message is always in the 4th byte, so clock out the first 2 words
1050 * manually, then loop the rest.
1052 data16 = (uint16_t *)reply;
1053 if (mpr_wait_db_int(sc) != 0) {
1054 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n");
1058 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK;
1059 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1060 if (mpr_wait_db_int(sc) != 0) {
1061 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n");
1065 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK;
1066 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1068 /* Number of 32bit words in the message */
1069 ioc_sz = reply->MsgLength;
1072 * Figure out how many 16bit words to clock in without overrunning.
1073 * The precision loss with dividing reply_sz can safely be
1074 * ignored because the messages can only be multiples of 32bits.
1077 count = MIN((reply_sz / 4), ioc_sz) * 2;
1078 if (count < ioc_sz * 2) {
1079 residual = ioc_sz * 2 - count;
1080 mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d "
1081 "residual message words\n", residual);
1084 for (i = 2; i < count; i++) {
1085 if (mpr_wait_db_int(sc) != 0) {
1086 mpr_dprint(sc, MPR_FAULT,
1087 "Timeout reading doorbell %d\n", i);
1090 data16[i] = mpr_regread(sc, MPI2_DOORBELL_OFFSET) &
1091 MPI2_DOORBELL_DATA_MASK;
1092 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1096 * Pull out residual words that won't fit into the provided buffer.
1097 * This keeps the chip from hanging due to a driver programming
1100 while (residual--) {
1101 if (mpr_wait_db_int(sc) != 0) {
1102 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n");
1105 (void)mpr_regread(sc, MPI2_DOORBELL_OFFSET);
1106 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1110 if (mpr_wait_db_int(sc) != 0) {
1111 mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n");
1114 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
1115 mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n");
1116 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1122 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm)
1124 request_descriptor_t rd;
1127 mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n",
1128 cm->cm_desc.Default.SMID, cm, cm->cm_ccb);
1130 if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags &
1131 MPR_FLAGS_SHUTDOWN))
1132 mtx_assert(&sc->mpr_mtx, MA_OWNED);
1134 if (++sc->io_cmds_active > sc->io_cmds_highwater)
1135 sc->io_cmds_highwater++;
1137 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("command not busy\n"));
1138 cm->cm_state = MPR_CM_STATE_INQUEUE;
1140 if (sc->atomic_desc_capable) {
1141 rd.u.low = cm->cm_desc.Words.Low;
1142 mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET,
1145 rd.u.low = cm->cm_desc.Words.Low;
1146 rd.u.high = cm->cm_desc.Words.High;
1147 rd.word = htole64(rd.word);
1148 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET,
1150 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET,
1156 * Just the FACTS, ma'am.
1159 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts)
1161 MPI2_DEFAULT_REPLY *reply;
1162 MPI2_IOC_FACTS_REQUEST request;
1163 int error, req_sz, reply_sz;
1166 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
1168 req_sz = sizeof(MPI2_IOC_FACTS_REQUEST);
1169 reply_sz = sizeof(MPI2_IOC_FACTS_REPLY);
1170 reply = (MPI2_DEFAULT_REPLY *)facts;
1172 bzero(&request, req_sz);
1173 request.Function = MPI2_FUNCTION_IOC_FACTS;
1174 error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5);
1176 mpr_dprint(sc, MPR_INIT, "%s exit, error= %d\n", __func__, error);
1181 mpr_send_iocinit(struct mpr_softc *sc)
1183 MPI2_IOC_INIT_REQUEST init;
1184 MPI2_DEFAULT_REPLY reply;
1185 int req_sz, reply_sz, error;
1187 uint64_t time_in_msec;
1190 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
1192 /* Do a quick sanity check on proper initialization */
1193 if ((sc->pqdepth == 0) || (sc->fqdepth == 0) || (sc->reqframesz == 0)
1194 || (sc->replyframesz == 0)) {
1195 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
1196 "Driver not fully initialized for IOCInit\n");
1200 req_sz = sizeof(MPI2_IOC_INIT_REQUEST);
1201 reply_sz = sizeof(MPI2_IOC_INIT_REPLY);
1202 bzero(&init, req_sz);
1203 bzero(&reply, reply_sz);
1206 * Fill in the init block. Note that most addresses are
1207 * deliberately in the lower 32bits of memory. This is a micro-
1208 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe.
1210 init.Function = MPI2_FUNCTION_IOC_INIT;
1211 init.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
1212 init.MsgVersion = htole16(MPI2_VERSION);
1213 init.HeaderVersion = htole16(MPI2_HEADER_VERSION);
1214 init.SystemRequestFrameSize = htole16((uint16_t)(sc->reqframesz / 4));
1215 init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth);
1216 init.ReplyFreeQueueDepth = htole16(sc->fqdepth);
1217 init.SenseBufferAddressHigh = 0;
1218 init.SystemReplyAddressHigh = 0;
1219 init.SystemRequestFrameBaseAddress.High = 0;
1220 init.SystemRequestFrameBaseAddress.Low =
1221 htole32((uint32_t)sc->req_busaddr);
1222 init.ReplyDescriptorPostQueueAddress.High = 0;
1223 init.ReplyDescriptorPostQueueAddress.Low =
1224 htole32((uint32_t)sc->post_busaddr);
1225 init.ReplyFreeQueueAddress.High = 0;
1226 init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr);
1228 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000);
1229 init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF);
1230 init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF);
1231 init.HostPageSize = HOST_PAGE_SIZE_4K;
1233 error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5);
1234 if ((reply.IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
1237 mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", reply.IOCStatus);
1238 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
1243 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1248 *addr = segs[0].ds_addr;
1252 mpr_memaddr_wait_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1254 struct mpr_busdma_context *ctx;
1255 int need_unload, need_free;
1257 ctx = (struct mpr_busdma_context *)arg;
1261 mpr_lock(ctx->softc);
1264 if ((error == 0) && (ctx->abandoned == 0)) {
1265 *ctx->addr = segs[0].ds_addr;
1269 if (ctx->abandoned != 0)
1275 mpr_unlock(ctx->softc);
1277 if (need_unload != 0) {
1278 bus_dmamap_unload(ctx->buffer_dmat,
1279 ctx->buffer_dmamap);
1288 mpr_alloc_queues(struct mpr_softc *sc)
1290 struct mpr_queue *q;
1294 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Allocating %d I/O queues\n", nq);
1296 sc->queues = malloc(sizeof(struct mpr_queue) * nq, M_MPR,
1298 if (sc->queues == NULL)
1301 for (i = 0; i < nq; i++) {
1303 mpr_dprint(sc, MPR_INIT, "Configuring queue %d %p\n", i, q);
1311 mpr_alloc_hw_queues(struct mpr_softc *sc)
1313 bus_dma_template_t t;
1314 bus_addr_t queues_busaddr;
1316 int qsize, fqsize, pqsize;
1319 * The reply free queue contains 4 byte entries in multiples of 16 and
1320 * aligned on a 16 byte boundary. There must always be an unused entry.
1321 * This queue supplies fresh reply frames for the firmware to use.
1323 * The reply descriptor post queue contains 8 byte entries in
1324 * multiples of 16 and aligned on a 16 byte boundary. This queue
1325 * contains filled-in reply frames sent from the firmware to the host.
1327 * These two queues are allocated together for simplicity.
1329 sc->fqdepth = roundup2(sc->num_replies + 1, 16);
1330 sc->pqdepth = roundup2(sc->num_replies + 1, 16);
1331 fqsize= sc->fqdepth * 4;
1332 pqsize = sc->pqdepth * 8;
1333 qsize = fqsize + pqsize;
1335 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1336 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(qsize),
1337 BD_MAXSEGSIZE(qsize), BD_NSEGMENTS(1),
1338 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1339 if (bus_dma_template_tag(&t, &sc->queues_dmat)) {
1340 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues DMA tag\n");
1343 if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT,
1345 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues memory\n");
1348 bzero(queues, qsize);
1349 bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize,
1350 mpr_memaddr_cb, &queues_busaddr, 0);
1352 sc->free_queue = (uint32_t *)queues;
1353 sc->free_busaddr = queues_busaddr;
1354 sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize);
1355 sc->post_busaddr = queues_busaddr + fqsize;
1356 mpr_dprint(sc, MPR_INIT, "free queue busaddr= %#016jx size= %d\n",
1357 (uintmax_t)sc->free_busaddr, fqsize);
1358 mpr_dprint(sc, MPR_INIT, "reply queue busaddr= %#016jx size= %d\n",
1359 (uintmax_t)sc->post_busaddr, pqsize);
1365 mpr_alloc_replies(struct mpr_softc *sc)
1367 bus_dma_template_t t;
1368 int rsize, num_replies;
1370 /* Store the reply frame size in bytes rather than as 32bit words */
1371 sc->replyframesz = sc->facts->ReplyFrameSize * 4;
1374 * sc->num_replies should be one less than sc->fqdepth. We need to
1375 * allocate space for sc->fqdepth replies, but only sc->num_replies
1376 * replies can be used at once.
1378 num_replies = max(sc->fqdepth, sc->num_replies);
1380 rsize = sc->replyframesz * num_replies;
1381 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1382 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize),
1383 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1384 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1385 if (bus_dma_template_tag(&t, &sc->reply_dmat)) {
1386 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies DMA tag\n");
1389 if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames,
1390 BUS_DMA_NOWAIT, &sc->reply_map)) {
1391 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies memory\n");
1394 bzero(sc->reply_frames, rsize);
1395 bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize,
1396 mpr_memaddr_cb, &sc->reply_busaddr, 0);
1397 mpr_dprint(sc, MPR_INIT, "reply frames busaddr= %#016jx size= %d\n",
1398 (uintmax_t)sc->reply_busaddr, rsize);
1404 mpr_load_chains_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1406 struct mpr_softc *sc = arg;
1407 struct mpr_chain *chain;
1414 for (i = 0, o = 0, s = 0; s < nsegs; s++) {
1415 for (bo = 0; bo + sc->chain_frame_size <= segs[s].ds_len;
1416 bo += sc->chain_frame_size) {
1417 chain = &sc->chains[i++];
1418 chain->chain =(MPI2_SGE_IO_UNION *)(sc->chain_frames+o);
1419 chain->chain_busaddr = segs[s].ds_addr + bo;
1420 o += sc->chain_frame_size;
1421 mpr_free_chain(sc, chain);
1423 if (bo != segs[s].ds_len)
1424 o += segs[s].ds_len - bo;
1426 sc->chain_free_lowwater = i;
1430 mpr_alloc_requests(struct mpr_softc *sc)
1432 bus_dma_template_t t;
1433 struct mpr_command *cm;
1434 int i, rsize, nsegs;
1436 rsize = sc->reqframesz * sc->num_reqs;
1437 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1438 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize),
1439 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1440 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1441 if (bus_dma_template_tag(&t, &sc->req_dmat)) {
1442 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request DMA tag\n");
1445 if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames,
1446 BUS_DMA_NOWAIT, &sc->req_map)) {
1447 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request memory\n");
1450 bzero(sc->req_frames, rsize);
1451 bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize,
1452 mpr_memaddr_cb, &sc->req_busaddr, 0);
1453 mpr_dprint(sc, MPR_INIT, "request frames busaddr= %#016jx size= %d\n",
1454 (uintmax_t)sc->req_busaddr, rsize);
1456 sc->chains = malloc(sizeof(struct mpr_chain) * sc->num_chains, M_MPR,
1459 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n");
1462 rsize = sc->chain_frame_size * sc->num_chains;
1463 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1464 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize),
1465 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS((howmany(rsize, PAGE_SIZE))));
1466 if (bus_dma_template_tag(&t, &sc->chain_dmat)) {
1467 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain DMA tag\n");
1470 if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames,
1471 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->chain_map)) {
1472 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n");
1475 if (bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames,
1476 rsize, mpr_load_chains_cb, sc, BUS_DMA_NOWAIT)) {
1477 mpr_dprint(sc, MPR_ERROR, "Cannot load chain memory\n");
1478 bus_dmamem_free(sc->chain_dmat, sc->chain_frames,
1483 rsize = MPR_SENSE_LEN * sc->num_reqs;
1484 bus_dma_template_clone(&t, sc->req_dmat);
1485 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(1), BD_MAXSIZE(rsize),
1486 BD_MAXSEGSIZE(rsize));
1487 if (bus_dma_template_tag(&t, &sc->sense_dmat)) {
1488 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense DMA tag\n");
1491 if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames,
1492 BUS_DMA_NOWAIT, &sc->sense_map)) {
1493 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense memory\n");
1496 bzero(sc->sense_frames, rsize);
1497 bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize,
1498 mpr_memaddr_cb, &sc->sense_busaddr, 0);
1499 mpr_dprint(sc, MPR_INIT, "sense frames busaddr= %#016jx size= %d\n",
1500 (uintmax_t)sc->sense_busaddr, rsize);
1503 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports
1506 if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) &&
1507 (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) {
1508 if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM)
1512 nsegs = (sc->maxio / PAGE_SIZE) + 1;
1513 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1514 BUS_DMA_TEMPLATE_FILL(&t, BD_MAXSIZE(BUS_SPACE_MAXSIZE_32BIT),
1515 BD_NSEGMENTS(nsegs), BD_MAXSEGSIZE(BUS_SPACE_MAXSIZE_32BIT),
1516 BD_FLAGS(BUS_DMA_ALLOCNOW), BD_LOCKFUNC(busdma_lock_mutex),
1517 BD_LOCKFUNCARG(&sc->mpr_mtx));
1518 if (bus_dma_template_tag(&t, &sc->buffer_dmat)) {
1519 mpr_dprint(sc, MPR_ERROR, "Cannot allocate buffer DMA tag\n");
1524 * SMID 0 cannot be used as a free command per the firmware spec.
1525 * Just drop that command instead of risking accounting bugs.
1527 sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs,
1528 M_MPR, M_WAITOK | M_ZERO);
1529 for (i = 1; i < sc->num_reqs; i++) {
1530 cm = &sc->commands[i];
1531 cm->cm_req = sc->req_frames + i * sc->reqframesz;
1532 cm->cm_req_busaddr = sc->req_busaddr + i * sc->reqframesz;
1533 cm->cm_sense = &sc->sense_frames[i];
1534 cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN;
1535 cm->cm_desc.Default.SMID = i;
1537 cm->cm_state = MPR_CM_STATE_BUSY;
1538 TAILQ_INIT(&cm->cm_chain_list);
1539 TAILQ_INIT(&cm->cm_prp_page_list);
1540 callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0);
1542 /* XXX Is a failure here a critical problem? */
1543 if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap)
1545 if (i <= sc->num_prireqs)
1546 mpr_free_high_priority_command(sc, cm);
1548 mpr_free_command(sc, cm);
1550 panic("failed to allocate command %d\n", i);
1560 * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs,
1561 * which are scatter/gather lists for NVMe devices.
1563 * This buffer must be contiguous due to the nature of how NVMe PRPs are built
1564 * and translated by FW.
1566 * returns ENOMEM if memory could not be allocated, otherwise returns 0.
1569 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc)
1571 bus_dma_template_t t;
1572 struct mpr_prp_page *prp_page;
1573 int PRPs_per_page, PRPs_required, pages_required;
1577 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number
1578 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is:
1579 * MAX_IO_SIZE / PAGE_SIZE = 256
1581 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs
1582 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one
1583 * page (4096 / 8 = 512), so only one page is required for each I/O.
1585 * Each of these buffers will need to be contiguous. For simplicity,
1586 * only one buffer is allocated here, which has all of the space
1587 * required for the NVMe Queue Depth. If there are problems allocating
1588 * this one buffer, this function will need to change to allocate
1589 * individual, contiguous NVME_QDEPTH buffers.
1591 * The real calculation will use the real max io size. Above is just an
1595 PRPs_required = sc->maxio / PAGE_SIZE;
1596 PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1;
1597 pages_required = (PRPs_required / PRPs_per_page) + 1;
1599 sc->prp_buffer_size = PAGE_SIZE * pages_required;
1600 rsize = sc->prp_buffer_size * NVME_QDEPTH;
1601 bus_dma_template_init(&t, sc->mpr_parent_dmat);
1602 BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize),
1603 BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1604 BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1605 if (bus_dma_template_tag(&t, &sc->prp_page_dmat)) {
1606 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP DMA "
1610 if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages,
1611 BUS_DMA_NOWAIT, &sc->prp_page_map)) {
1612 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP memory\n");
1615 bzero(sc->prp_pages, rsize);
1616 bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages,
1617 rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0);
1619 sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR,
1621 for (i = 0; i < NVME_QDEPTH; i++) {
1622 prp_page = &sc->prps[i];
1623 prp_page->prp_page = (uint64_t *)(sc->prp_pages +
1624 i * sc->prp_buffer_size);
1625 prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr +
1626 i * sc->prp_buffer_size);
1627 mpr_free_prp_page(sc, prp_page);
1628 sc->prp_pages_free_lowwater++;
1635 mpr_init_queues(struct mpr_softc *sc)
1639 memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8);
1642 * According to the spec, we need to use one less reply than we
1643 * have space for on the queue. So sc->num_replies (the number we
1644 * use) should be less than sc->fqdepth (allocated size).
1646 if (sc->num_replies >= sc->fqdepth)
1650 * Initialize all of the free queue entries.
1652 for (i = 0; i < sc->fqdepth; i++) {
1653 sc->free_queue[i] = sc->reply_busaddr + (i * sc->replyframesz);
1655 sc->replyfreeindex = sc->num_replies;
1660 /* Get the driver parameter tunables. Lowest priority are the driver defaults.
1661 * Next are the global settings, if they exist. Highest are the per-unit
1662 * settings, if they exist.
1665 mpr_get_tunables(struct mpr_softc *sc)
1667 char tmpstr[80], mpr_debug[80];
1669 /* XXX default to some debugging for now */
1670 sc->mpr_debug = MPR_INFO | MPR_FAULT;
1671 sc->disable_msix = 0;
1672 sc->disable_msi = 0;
1673 sc->max_msix = MPR_MSIX_MAX;
1674 sc->max_chains = MPR_CHAIN_FRAMES;
1675 sc->max_io_pages = MPR_MAXIO_PAGES;
1676 sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD;
1677 sc->spinup_wait_time = DEFAULT_SPINUP_WAIT;
1679 sc->max_reqframes = MPR_REQ_FRAMES;
1680 sc->max_prireqframes = MPR_PRI_REQ_FRAMES;
1681 sc->max_replyframes = MPR_REPLY_FRAMES;
1682 sc->max_evtframes = MPR_EVT_REPLY_FRAMES;
1685 * Grab the global variables.
1687 bzero(mpr_debug, 80);
1688 if (TUNABLE_STR_FETCH("hw.mpr.debug_level", mpr_debug, 80) != 0)
1689 mpr_parse_debug(sc, mpr_debug);
1690 TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix);
1691 TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi);
1692 TUNABLE_INT_FETCH("hw.mpr.max_msix", &sc->max_msix);
1693 TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains);
1694 TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages);
1695 TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu);
1696 TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time);
1697 TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum);
1698 TUNABLE_INT_FETCH("hw.mpr.max_reqframes", &sc->max_reqframes);
1699 TUNABLE_INT_FETCH("hw.mpr.max_prireqframes", &sc->max_prireqframes);
1700 TUNABLE_INT_FETCH("hw.mpr.max_replyframes", &sc->max_replyframes);
1701 TUNABLE_INT_FETCH("hw.mpr.max_evtframes", &sc->max_evtframes);
1703 /* Grab the unit-instance variables */
1704 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level",
1705 device_get_unit(sc->mpr_dev));
1706 bzero(mpr_debug, 80);
1707 if (TUNABLE_STR_FETCH(tmpstr, mpr_debug, 80) != 0)
1708 mpr_parse_debug(sc, mpr_debug);
1710 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix",
1711 device_get_unit(sc->mpr_dev));
1712 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix);
1714 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi",
1715 device_get_unit(sc->mpr_dev));
1716 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi);
1718 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_msix",
1719 device_get_unit(sc->mpr_dev));
1720 TUNABLE_INT_FETCH(tmpstr, &sc->max_msix);
1722 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains",
1723 device_get_unit(sc->mpr_dev));
1724 TUNABLE_INT_FETCH(tmpstr, &sc->max_chains);
1726 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages",
1727 device_get_unit(sc->mpr_dev));
1728 TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages);
1730 bzero(sc->exclude_ids, sizeof(sc->exclude_ids));
1731 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids",
1732 device_get_unit(sc->mpr_dev));
1733 TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids));
1735 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu",
1736 device_get_unit(sc->mpr_dev));
1737 TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu);
1739 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time",
1740 device_get_unit(sc->mpr_dev));
1741 TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time);
1743 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num",
1744 device_get_unit(sc->mpr_dev));
1745 TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum);
1747 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_reqframes",
1748 device_get_unit(sc->mpr_dev));
1749 TUNABLE_INT_FETCH(tmpstr, &sc->max_reqframes);
1751 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_prireqframes",
1752 device_get_unit(sc->mpr_dev));
1753 TUNABLE_INT_FETCH(tmpstr, &sc->max_prireqframes);
1755 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_replyframes",
1756 device_get_unit(sc->mpr_dev));
1757 TUNABLE_INT_FETCH(tmpstr, &sc->max_replyframes);
1759 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_evtframes",
1760 device_get_unit(sc->mpr_dev));
1761 TUNABLE_INT_FETCH(tmpstr, &sc->max_evtframes);
1765 mpr_setup_sysctl(struct mpr_softc *sc)
1767 struct sysctl_ctx_list *sysctl_ctx = NULL;
1768 struct sysctl_oid *sysctl_tree = NULL;
1769 char tmpstr[80], tmpstr2[80];
1772 * Setup the sysctl variable so the user can change the debug level
1775 snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d",
1776 device_get_unit(sc->mpr_dev));
1777 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev));
1779 sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev);
1780 if (sysctl_ctx != NULL)
1781 sysctl_tree = device_get_sysctl_tree(sc->mpr_dev);
1783 if (sysctl_tree == NULL) {
1784 sysctl_ctx_init(&sc->sysctl_ctx);
1785 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1786 SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2,
1787 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, tmpstr);
1788 if (sc->sysctl_tree == NULL)
1790 sysctl_ctx = &sc->sysctl_ctx;
1791 sysctl_tree = sc->sysctl_tree;
1794 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1795 OID_AUTO, "debug_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
1796 sc, 0, mpr_debug_sysctl, "A", "mpr debug level");
1798 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1799 OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0,
1800 "Disable the use of MSI-X interrupts");
1802 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1803 OID_AUTO, "max_msix", CTLFLAG_RD, &sc->max_msix, 0,
1804 "User-defined maximum number of MSIX queues");
1806 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1807 OID_AUTO, "msix_msgs", CTLFLAG_RD, &sc->msi_msgs, 0,
1808 "Negotiated number of MSIX queues");
1810 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1811 OID_AUTO, "max_reqframes", CTLFLAG_RD, &sc->max_reqframes, 0,
1812 "Total number of allocated request frames");
1814 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1815 OID_AUTO, "max_prireqframes", CTLFLAG_RD, &sc->max_prireqframes, 0,
1816 "Total number of allocated high priority request frames");
1818 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1819 OID_AUTO, "max_replyframes", CTLFLAG_RD, &sc->max_replyframes, 0,
1820 "Total number of allocated reply frames");
1822 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1823 OID_AUTO, "max_evtframes", CTLFLAG_RD, &sc->max_evtframes, 0,
1824 "Total number of event frames allocated");
1826 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1827 OID_AUTO, "firmware_version", CTLFLAG_RD, sc->fw_version,
1828 strlen(sc->fw_version), "firmware version");
1830 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1831 OID_AUTO, "driver_version", CTLFLAG_RD, MPR_DRIVER_VERSION,
1832 strlen(MPR_DRIVER_VERSION), "driver version");
1834 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1835 OID_AUTO, "msg_version", CTLFLAG_RD, sc->msg_version,
1836 strlen(sc->msg_version), "message interface version");
1838 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1839 OID_AUTO, "io_cmds_active", CTLFLAG_RD,
1840 &sc->io_cmds_active, 0, "number of currently active commands");
1842 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1843 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD,
1844 &sc->io_cmds_highwater, 0, "maximum active commands seen");
1846 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1847 OID_AUTO, "chain_free", CTLFLAG_RD,
1848 &sc->chain_free, 0, "number of free chain elements");
1850 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1851 OID_AUTO, "chain_free_lowwater", CTLFLAG_RD,
1852 &sc->chain_free_lowwater, 0,"lowest number of free chain elements");
1854 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1855 OID_AUTO, "max_chains", CTLFLAG_RD,
1856 &sc->max_chains, 0,"maximum chain frames that will be allocated");
1858 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1859 OID_AUTO, "max_io_pages", CTLFLAG_RD,
1860 &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use "
1863 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1864 OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0,
1865 "enable SSU to SATA SSD/HDD at shutdown");
1867 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1868 OID_AUTO, "chain_alloc_fail", CTLFLAG_RD,
1869 &sc->chain_alloc_fail, "chain allocation failures");
1871 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1872 OID_AUTO, "spinup_wait_time", CTLFLAG_RD,
1873 &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for "
1874 "spinup after SATA ID error");
1876 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1877 OID_AUTO, "dump_reqs",
1878 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_NEEDGIANT,
1879 sc, 0, mpr_dump_reqs, "I", "Dump Active Requests");
1881 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1882 OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0,
1883 "Use the phy number for enumeration");
1885 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1886 OID_AUTO, "prp_pages_free", CTLFLAG_RD,
1887 &sc->prp_pages_free, 0, "number of free PRP pages");
1889 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1890 OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD,
1891 &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages");
1893 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1894 OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD,
1895 &sc->prp_page_alloc_fail, "PRP page allocation failures");
1898 static struct mpr_debug_string {
1901 } mpr_debug_strings[] = {
1903 {"fault", MPR_FAULT},
1904 {"event", MPR_EVENT},
1906 {"recovery", MPR_RECOVERY},
1907 {"error", MPR_ERROR},
1909 {"xinfo", MPR_XINFO},
1911 {"mapping", MPR_MAPPING},
1912 {"trace", MPR_TRACE}
1915 enum mpr_debug_level_combiner {
1922 mpr_debug_sysctl(SYSCTL_HANDLER_ARGS)
1924 struct mpr_softc *sc;
1925 struct mpr_debug_string *string;
1929 int i, len, debug, error;
1931 sc = (struct mpr_softc *)arg1;
1933 error = sysctl_wire_old_buffer(req, 0);
1937 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
1938 debug = sc->mpr_debug;
1940 sbuf_printf(sbuf, "%#x", debug);
1942 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]);
1943 for (i = 0; i < sz; i++) {
1944 string = &mpr_debug_strings[i];
1945 if (debug & string->flag)
1946 sbuf_printf(sbuf, ",%s", string->name);
1949 error = sbuf_finish(sbuf);
1952 if (error || req->newptr == NULL)
1955 len = req->newlen - req->newidx;
1959 buffer = malloc(len, M_MPR, M_ZERO|M_WAITOK);
1960 error = SYSCTL_IN(req, buffer, len);
1962 mpr_parse_debug(sc, buffer);
1964 free(buffer, M_MPR);
1969 mpr_parse_debug(struct mpr_softc *sc, char *list)
1971 struct mpr_debug_string *string;
1972 enum mpr_debug_level_combiner op;
1973 char *token, *endtoken;
1977 if (list == NULL || *list == '\0')
1983 } else if (*list == '-') {
1992 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]);
1993 while ((token = strsep(&list, ":,")) != NULL) {
1994 /* Handle integer flags */
1995 flags |= strtol(token, &endtoken, 0);
1996 if (token != endtoken)
1999 /* Handle text flags */
2000 for (i = 0; i < sz; i++) {
2001 string = &mpr_debug_strings[i];
2002 if (strcasecmp(token, string->name) == 0) {
2003 flags |= string->flag;
2011 sc->mpr_debug = flags;
2014 sc->mpr_debug |= flags;
2017 sc->mpr_debug &= (~flags);
2023 struct mpr_dumpreq_hdr {
2032 mpr_dump_reqs(SYSCTL_HANDLER_ARGS)
2034 struct mpr_softc *sc;
2035 struct mpr_chain *chain, *chain1;
2036 struct mpr_command *cm;
2037 struct mpr_dumpreq_hdr hdr;
2039 uint32_t smid, state;
2040 int i, numreqs, error = 0;
2042 sc = (struct mpr_softc *)arg1;
2044 if ((error = priv_check(curthread, PRIV_DRIVER)) != 0) {
2045 printf("priv check error %d\n", error);
2049 state = MPR_CM_STATE_INQUEUE;
2051 numreqs = sc->num_reqs;
2053 if (req->newptr != NULL)
2056 if (smid == 0 || smid > sc->num_reqs)
2058 if (numreqs <= 0 || (numreqs + smid > sc->num_reqs))
2059 numreqs = sc->num_reqs;
2060 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
2062 /* Best effort, no locking */
2063 for (i = smid; i < numreqs; i++) {
2064 cm = &sc->commands[i];
2065 if (cm->cm_state != state)
2068 hdr.state = cm->cm_state;
2070 hdr.deschi = cm->cm_desc.Words.High;
2071 hdr.desclo = cm->cm_desc.Words.Low;
2072 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link,
2075 sbuf_bcat(sb, &hdr, sizeof(hdr));
2076 sbuf_bcat(sb, cm->cm_req, 128);
2077 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link,
2079 sbuf_bcat(sb, chain->chain, 128);
2082 error = sbuf_finish(sb);
2088 mpr_attach(struct mpr_softc *sc)
2093 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2095 mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF);
2096 callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0);
2097 callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0);
2098 TAILQ_INIT(&sc->event_list);
2099 timevalclear(&sc->lastfail);
2101 if ((error = mpr_transition_ready(sc)) != 0) {
2102 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
2103 "Failed to transition ready\n");
2107 sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR,
2110 mpr_dprint(sc, MPR_INIT|MPR_FAULT,
2111 "Cannot allocate memory, exit\n");
2116 * Get IOC Facts and allocate all structures based on this information.
2117 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC
2118 * Facts. If relevant values have changed in IOC Facts, this function
2119 * will free all of the memory based on IOC Facts and reallocate that
2120 * memory. If this fails, any allocated memory should already be freed.
2122 if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) {
2123 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC Facts allocation "
2124 "failed with error %d\n", error);
2128 /* Start the periodic watchdog check on the IOC Doorbell */
2132 * The portenable will kick off discovery events that will drive the
2133 * rest of the initialization process. The CAM/SAS module will
2134 * hold up the boot sequence until discovery is complete.
2136 sc->mpr_ich.ich_func = mpr_startup;
2137 sc->mpr_ich.ich_arg = sc;
2138 if (config_intrhook_establish(&sc->mpr_ich) != 0) {
2139 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
2140 "Cannot establish MPR config hook\n");
2145 * Allow IR to shutdown gracefully when shutdown occurs.
2147 sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final,
2148 mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT);
2150 if (sc->shutdown_eh == NULL)
2151 mpr_dprint(sc, MPR_INIT|MPR_ERROR,
2152 "shutdown event registration failed\n");
2154 mpr_setup_sysctl(sc);
2156 sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE;
2157 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error);
2162 /* Run through any late-start handlers. */
2164 mpr_startup(void *arg)
2166 struct mpr_softc *sc;
2168 sc = (struct mpr_softc *)arg;
2169 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2172 mpr_unmask_intr(sc);
2174 /* initialize device mapping tables */
2175 mpr_base_static_config_pages(sc);
2176 mpr_mapping_initialize(sc);
2180 mpr_dprint(sc, MPR_INIT, "disestablish config intrhook\n");
2181 config_intrhook_disestablish(&sc->mpr_ich);
2182 sc->mpr_ich.ich_arg = NULL;
2184 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
2187 /* Periodic watchdog. Is called with the driver lock already held. */
2189 mpr_periodic(void *arg)
2191 struct mpr_softc *sc;
2194 sc = (struct mpr_softc *)arg;
2195 if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN)
2198 db = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
2199 if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
2200 if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) ==
2201 IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) {
2202 panic("TEMPERATURE FAULT: STOPPING.");
2204 mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db);
2208 callout_reset(&sc->periodic, MPR_PERIODIC_DELAY * hz, mpr_periodic, sc);
2212 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data,
2213 MPI2_EVENT_NOTIFICATION_REPLY *event)
2215 MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry;
2217 MPR_DPRINT_EVENT(sc, generic, event);
2219 switch (event->Event) {
2220 case MPI2_EVENT_LOG_DATA:
2221 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n");
2222 if (sc->mpr_debug & MPR_EVENT)
2223 hexdump(event->EventData, event->EventDataLength, NULL,
2226 case MPI2_EVENT_LOG_ENTRY_ADDED:
2227 entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData;
2228 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event "
2229 "0x%x Sequence %d:\n", entry->LogEntryQualifier,
2230 entry->LogSequence);
2239 mpr_attach_log(struct mpr_softc *sc)
2244 setbit(events, MPI2_EVENT_LOG_DATA);
2245 setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED);
2247 mpr_register_events(sc, events, mpr_log_evt_handler, NULL,
2254 mpr_detach_log(struct mpr_softc *sc)
2257 if (sc->mpr_log_eh != NULL)
2258 mpr_deregister_events(sc, sc->mpr_log_eh);
2263 * Free all of the driver resources and detach submodules. Should be called
2264 * without the lock held.
2267 mpr_free(struct mpr_softc *sc)
2271 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2272 /* Turn off the watchdog */
2274 sc->mpr_flags |= MPR_FLAGS_SHUTDOWN;
2276 /* Lock must not be held for this */
2277 callout_drain(&sc->periodic);
2278 callout_drain(&sc->device_check_callout);
2280 if (((error = mpr_detach_log(sc)) != 0) ||
2281 ((error = mpr_detach_sas(sc)) != 0)) {
2282 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "failed to detach "
2283 "subsystems, error= %d, exit\n", error);
2287 mpr_detach_user(sc);
2289 /* Put the IOC back in the READY state. */
2291 if ((error = mpr_transition_ready(sc)) != 0) {
2297 if (sc->facts != NULL)
2298 free(sc->facts, M_MPR);
2301 * Free all buffers that are based on IOC Facts. A Diag Reset may need
2302 * to free these buffers too.
2304 mpr_iocfacts_free(sc);
2306 if (sc->sysctl_tree != NULL)
2307 sysctl_ctx_free(&sc->sysctl_ctx);
2309 /* Deregister the shutdown function */
2310 if (sc->shutdown_eh != NULL)
2311 EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh);
2313 mtx_destroy(&sc->mpr_mtx);
2314 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
2319 static __inline void
2320 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm)
2325 mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n");
2329 cm->cm_state = MPR_CM_STATE_BUSY;
2330 if (cm->cm_flags & MPR_CM_FLAGS_POLLED)
2331 cm->cm_flags |= MPR_CM_FLAGS_COMPLETE;
2333 if (cm->cm_complete != NULL) {
2334 mpr_dprint(sc, MPR_TRACE,
2335 "%s cm %p calling cm_complete %p data %p reply %p\n",
2336 __func__, cm, cm->cm_complete, cm->cm_complete_data,
2338 cm->cm_complete(sc, cm);
2341 if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) {
2342 mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm);
2346 if (sc->io_cmds_active != 0) {
2347 sc->io_cmds_active--;
2349 mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is "
2350 "out of sync - resynching to 0\n");
2355 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info)
2357 union loginfo_type {
2366 union loginfo_type sas_loginfo;
2367 char *originator_str = NULL;
2369 sas_loginfo.loginfo = log_info;
2370 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
2373 /* each nexus loss loginfo */
2374 if (log_info == 0x31170000)
2377 /* eat the loginfos associated with task aborts */
2378 if ((log_info == 30050000) || (log_info == 0x31140000) ||
2379 (log_info == 0x31130000))
2382 switch (sas_loginfo.dw.originator) {
2384 originator_str = "IOP";
2387 originator_str = "PL";
2390 originator_str = "IR";
2394 mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), "
2395 "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str,
2396 sas_loginfo.dw.code, sas_loginfo.dw.subcode);
2400 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply)
2402 MPI2DefaultReply_t *mpi_reply;
2405 mpi_reply = (MPI2DefaultReply_t*)reply;
2406 sc_status = le16toh(mpi_reply->IOCStatus);
2407 if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
2408 mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo));
2412 mpr_intr(void *data)
2414 struct mpr_softc *sc;
2417 sc = (struct mpr_softc *)data;
2418 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2421 * Check interrupt status register to flush the bus. This is
2422 * needed for both INTx interrupts and driver-driven polling
2424 status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
2425 if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0)
2429 mpr_intr_locked(data);
2435 * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the
2436 * chip. Hopefully this theory is correct.
2439 mpr_intr_msi(void *data)
2441 struct mpr_softc *sc;
2443 sc = (struct mpr_softc *)data;
2444 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2446 mpr_intr_locked(data);
2452 * The locking is overly broad and simplistic, but easy to deal with for now.
2455 mpr_intr_locked(void *data)
2457 MPI2_REPLY_DESCRIPTORS_UNION *desc;
2458 MPI2_DIAG_RELEASE_REPLY *rel_rep;
2459 mpr_fw_diagnostic_buffer_t *pBuffer;
2460 struct mpr_softc *sc;
2462 struct mpr_command *cm = NULL;
2466 sc = (struct mpr_softc *)data;
2468 pq = sc->replypostindex;
2469 mpr_dprint(sc, MPR_TRACE,
2470 "%s sc %p starting with replypostindex %u\n",
2471 __func__, sc, sc->replypostindex);
2475 desc = &sc->post_queue[sc->replypostindex];
2478 * Copy and clear out the descriptor so that any reentry will
2479 * immediately know that this descriptor has already been
2480 * looked at. There is unfortunate casting magic because the
2481 * MPI API doesn't have a cardinal 64bit type.
2483 tdesc = 0xffffffffffffffff;
2484 tdesc = atomic_swap_64((uint64_t *)desc, tdesc);
2485 desc = (MPI2_REPLY_DESCRIPTORS_UNION *)&tdesc;
2487 flags = desc->Default.ReplyFlags &
2488 MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
2489 if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) ||
2490 (le32toh(desc->Words.High) == 0xffffffff))
2493 /* increment the replypostindex now, so that event handlers
2494 * and cm completion handlers which decide to do a diag
2495 * reset can zero it without it getting incremented again
2496 * afterwards, and we break out of this loop on the next
2497 * iteration since the reply post queue has been cleared to
2498 * 0xFF and all descriptors look unused (which they are).
2500 if (++sc->replypostindex >= sc->pqdepth)
2501 sc->replypostindex = 0;
2504 case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS:
2505 case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS:
2506 case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS:
2507 cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)];
2508 KASSERT(cm->cm_state == MPR_CM_STATE_INQUEUE,
2509 ("command not inqueue\n"));
2510 cm->cm_state = MPR_CM_STATE_BUSY;
2511 cm->cm_reply = NULL;
2513 case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY:
2519 * Re-compose the reply address from the address
2520 * sent back from the chip. The ReplyFrameAddress
2521 * is the lower 32 bits of the physical address of
2522 * particular reply frame. Convert that address to
2523 * host format, and then use that to provide the
2524 * offset against the virtual address base
2525 * (sc->reply_frames).
2527 baddr = le32toh(desc->AddressReply.ReplyFrameAddress);
2528 reply = sc->reply_frames +
2529 (baddr - ((uint32_t)sc->reply_busaddr));
2531 * Make sure the reply we got back is in a valid
2532 * range. If not, go ahead and panic here, since
2533 * we'll probably panic as soon as we deference the
2534 * reply pointer anyway.
2536 if ((reply < sc->reply_frames)
2537 || (reply > (sc->reply_frames +
2538 (sc->fqdepth * sc->replyframesz)))) {
2539 printf("%s: WARNING: reply %p out of range!\n",
2541 printf("%s: reply_frames %p, fqdepth %d, "
2542 "frame size %d\n", __func__,
2543 sc->reply_frames, sc->fqdepth,
2545 printf("%s: baddr %#x,\n", __func__, baddr);
2546 /* LSI-TODO. See Linux Code for Graceful exit */
2547 panic("Reply address out of range");
2549 if (le16toh(desc->AddressReply.SMID) == 0) {
2550 if (((MPI2_DEFAULT_REPLY *)reply)->Function ==
2551 MPI2_FUNCTION_DIAG_BUFFER_POST) {
2553 * If SMID is 0 for Diag Buffer Post,
2554 * this implies that the reply is due to
2555 * a release function with a status that
2556 * the buffer has been released. Set
2557 * the buffer flags accordingly.
2560 (MPI2_DIAG_RELEASE_REPLY *)reply;
2561 if ((le16toh(rel_rep->IOCStatus) &
2562 MPI2_IOCSTATUS_MASK) ==
2563 MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED)
2566 &sc->fw_diag_buffer_list[
2567 rel_rep->BufferType];
2568 pBuffer->valid_data = TRUE;
2569 pBuffer->owned_by_firmware =
2571 pBuffer->immediate = FALSE;
2574 mpr_dispatch_event(sc, baddr,
2575 (MPI2_EVENT_NOTIFICATION_REPLY *)
2579 le16toh(desc->AddressReply.SMID)];
2580 if (cm->cm_state == MPR_CM_STATE_INQUEUE) {
2581 cm->cm_reply = reply;
2583 le32toh(desc->AddressReply.
2586 mpr_dprint(sc, MPR_RECOVERY,
2587 "Bad state for ADDRESS_REPLY status,"
2588 " ignoring state %d cm %p\n",
2594 case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS:
2595 case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER:
2596 case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS:
2599 mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n",
2600 desc->Default.ReplyFlags);
2606 // Print Error reply frame
2608 mpr_display_reply_info(sc,cm->cm_reply);
2609 mpr_complete_command(sc, cm);
2613 if (pq != sc->replypostindex) {
2614 mpr_dprint(sc, MPR_TRACE, "%s sc %p writing postindex %d\n",
2615 __func__, sc, sc->replypostindex);
2616 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET,
2617 sc->replypostindex);
2624 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
2625 MPI2_EVENT_NOTIFICATION_REPLY *reply)
2627 struct mpr_event_handle *eh;
2628 int event, handled = 0;
2630 event = le16toh(reply->Event);
2631 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2632 if (isset(eh->mask, event)) {
2633 eh->callback(sc, data, reply);
2639 mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n",
2643 * This is the only place that the event/reply should be freed.
2644 * Anything wanting to hold onto the event data should have
2645 * already copied it into their own storage.
2647 mpr_free_reply(sc, data);
2651 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm)
2653 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2656 MPR_DPRINT_EVENT(sc, generic,
2657 (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply);
2659 mpr_free_command(sc, cm);
2661 /* next, send a port enable */
2666 * For both register_events and update_events, the caller supplies a bitmap
2667 * of events that it _wants_. These functions then turn that into a bitmask
2668 * suitable for the controller.
2671 mpr_register_events(struct mpr_softc *sc, uint8_t *mask,
2672 mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle)
2674 struct mpr_event_handle *eh;
2677 eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO);
2680 TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list);
2682 error = mpr_update_events(sc, eh, mask);
2689 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle,
2692 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2693 MPI2_EVENT_NOTIFICATION_REPLY *reply = NULL;
2694 struct mpr_command *cm = NULL;
2695 struct mpr_event_handle *eh;
2698 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2700 if ((mask != NULL) && (handle != NULL))
2701 bcopy(mask, &handle->mask[0], 16);
2702 memset(sc->event_mask, 0xff, 16);
2704 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2705 for (i = 0; i < 16; i++)
2706 sc->event_mask[i] &= ~eh->mask[i];
2709 if ((cm = mpr_alloc_command(sc)) == NULL)
2711 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2712 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2713 evtreq->MsgFlags = 0;
2714 evtreq->SASBroadcastPrimitiveMasks = 0;
2715 #ifdef MPR_DEBUG_ALL_EVENTS
2717 u_char fullmask[16];
2718 memset(fullmask, 0x00, 16);
2719 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2722 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16);
2724 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2727 error = mpr_request_polled(sc, &cm);
2729 reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply;
2730 if ((reply == NULL) ||
2731 (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
2735 MPR_DPRINT_EVENT(sc, generic, reply);
2737 mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error);
2740 mpr_free_command(sc, cm);
2745 mpr_reregister_events(struct mpr_softc *sc)
2747 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2748 struct mpr_command *cm;
2749 struct mpr_event_handle *eh;
2752 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2754 /* first, reregister events */
2756 memset(sc->event_mask, 0xff, 16);
2758 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2759 for (i = 0; i < 16; i++)
2760 sc->event_mask[i] &= ~eh->mask[i];
2763 if ((cm = mpr_alloc_command(sc)) == NULL)
2765 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2766 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2767 evtreq->MsgFlags = 0;
2768 evtreq->SASBroadcastPrimitiveMasks = 0;
2769 #ifdef MPR_DEBUG_ALL_EVENTS
2771 u_char fullmask[16];
2772 memset(fullmask, 0x00, 16);
2773 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2776 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16);
2778 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2780 cm->cm_complete = mpr_reregister_events_complete;
2782 error = mpr_map_command(sc, cm);
2784 mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__,
2790 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle)
2793 TAILQ_REMOVE(&sc->event_list, handle, eh_list);
2794 free(handle, M_MPR);
2795 return (mpr_update_events(sc, NULL, NULL));
2799 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a
2800 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry
2801 * of the NVMe message (PRP1). If the data buffer is small enough to be described
2802 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to
2803 * describe a larger data buffer. If the data buffer is too large to describe
2804 * using the two PRP entriess inside the NVMe message, then PRP1 describes the
2805 * first data memory segment, and PRP2 contains a pointer to a PRP list located
2806 * elsewhere in memory to describe the remaining data memory segments. The PRP
2807 * list will be contiguous.
2809 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
2810 * consists of a list of PRP entries to describe a number of noncontigous
2811 * physical memory segments as a single memory buffer, just as a SGL does. Note
2812 * however, that this function is only used by the IOCTL call, so the memory
2813 * given will be guaranteed to be contiguous. There is no need to translate
2814 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous
2815 * space that is one page size each.
2817 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
2818 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains
2819 * the second PRP element if the memory being described fits within 2 PRP
2820 * entries, or a PRP list pointer if the PRP spans more than two entries.
2822 * A PRP list pointer contains the address of a PRP list, structured as a linear
2823 * array of PRP entries. Each PRP entry in this list describes a segment of
2826 * Each 64-bit PRP entry comprises an address and an offset field. The address
2827 * always points to the beginning of a PAGE_SIZE physical memory page, and the
2828 * offset describes where within that page the memory segment begins. Only the
2829 * first element in a PRP list may contain a non-zero offest, implying that all
2830 * memory segments following the first begin at the start of a PAGE_SIZE page.
2832 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory,
2833 * with exceptions for the first and last elements in the list. If the memory
2834 * being described by the list begins at a non-zero offset within the first page,
2835 * then the first PRP element will contain a non-zero offset indicating where the
2836 * region begins within the page. The last memory segment may end before the end
2837 * of the PAGE_SIZE segment, depending upon the overall size of the memory being
2838 * described by the PRP list.
2840 * Since PRP entries lack any indication of size, the overall data buffer length
2841 * is used to determine where the end of the data memory buffer is located, and
2842 * how many PRP entries are required to describe it.
2847 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
2848 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
2849 uint32_t data_in_sz, uint32_t data_out_sz)
2851 int prp_size = PRP_ENTRY_SIZE;
2852 uint64_t *prp_entry, *prp1_entry, *prp2_entry;
2853 uint64_t *prp_entry_phys, *prp_page, *prp_page_phys;
2854 uint32_t offset, entry_len, page_mask_result, page_mask;
2857 struct mpr_prp_page *prp_page_info = NULL;
2860 * Not all commands require a data transfer. If no data, just return
2861 * without constructing any PRP.
2863 if (!data_in_sz && !data_out_sz)
2867 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is
2868 * located at a 24 byte offset from the start of the NVMe command. Then
2869 * set the current PRP entry pointer to PRP1.
2871 prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2872 NVME_CMD_PRP1_OFFSET);
2873 prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2874 NVME_CMD_PRP2_OFFSET);
2875 prp_entry = prp1_entry;
2878 * For the PRP entries, use the specially allocated buffer of
2879 * contiguous memory. PRP Page allocation failures should not happen
2880 * because there should be enough PRP page buffers to account for the
2881 * possible NVMe QDepth.
2883 prp_page_info = mpr_alloc_prp_page(sc);
2884 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
2885 "used for building a native NVMe SGL.\n", __func__));
2886 prp_page = (uint64_t *)prp_page_info->prp_page;
2887 prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
2890 * Insert the allocated PRP page into the command's PRP page list. This
2891 * will be freed when the command is freed.
2893 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
2896 * Check if we are within 1 entry of a page boundary we don't want our
2897 * first entry to be a PRP List entry.
2899 page_mask = PAGE_SIZE - 1;
2900 page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) &
2902 if (!page_mask_result)
2904 /* Bump up to next page boundary. */
2905 prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size);
2906 prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys +
2911 * Set PRP physical pointer, which initially points to the current PRP
2914 prp_entry_phys = prp_page_phys;
2916 /* Get physical address and length of the data buffer. */
2917 paddr = (bus_addr_t)(uintptr_t)data;
2919 length = data_in_sz;
2921 length = data_out_sz;
2923 /* Loop while the length is not zero. */
2927 * Check if we need to put a list pointer here if we are at page
2928 * boundary - prp_size (8 bytes).
2930 page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys +
2931 prp_size) & page_mask;
2932 if (!page_mask_result)
2935 * This is the last entry in a PRP List, so we need to
2936 * put a PRP list pointer here. What this does is:
2937 * - bump the current memory pointer to the next
2938 * address, which will be the next full page.
2939 * - set the PRP Entry to point to that page. This is
2940 * now the PRP List pointer.
2941 * - bump the PRP Entry pointer the start of the next
2942 * page. Since all of this PRP memory is contiguous,
2943 * no need to get a new page - it's just the next
2948 htole64((uint64_t)(uintptr_t)prp_entry_phys);
2952 /* Need to handle if entry will be part of a page. */
2953 offset = (uint32_t)paddr & page_mask;
2954 entry_len = PAGE_SIZE - offset;
2956 if (prp_entry == prp1_entry)
2959 * Must fill in the first PRP pointer (PRP1) before
2962 *prp1_entry = htole64((uint64_t)paddr);
2965 * Now point to the second PRP entry within the
2968 prp_entry = prp2_entry;
2970 else if (prp_entry == prp2_entry)
2973 * Should the PRP2 entry be a PRP List pointer or just a
2974 * regular PRP pointer? If there is more than one more
2975 * page of data, must use a PRP List pointer.
2977 if (length > PAGE_SIZE)
2980 * PRP2 will contain a PRP List pointer because
2981 * more PRP's are needed with this command. The
2982 * list will start at the beginning of the
2983 * contiguous buffer.
2987 (uint64_t)(uintptr_t)prp_entry_phys);
2990 * The next PRP Entry will be the start of the
2993 prp_entry = prp_page;
2998 * After this, the PRP Entries are complete.
2999 * This command uses 2 PRP's and no PRP list.
3001 *prp2_entry = htole64((uint64_t)paddr);
3007 * Put entry in list and bump the addresses.
3009 * After PRP1 and PRP2 are filled in, this will fill in
3010 * all remaining PRP entries in a PRP List, one per each
3011 * time through the loop.
3013 *prp_entry = htole64((uint64_t)paddr);
3019 * Bump the phys address of the command's data buffer by the
3024 /* Decrement length accounting for last partial page. */
3025 if (entry_len > length)
3028 length -= entry_len;
3033 * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to
3034 * determine if the driver needs to build a native SGL. If so, that native SGL
3035 * is built in the contiguous buffers allocated especially for PCIe SGL
3036 * creation. If the driver will not build a native SGL, return TRUE and a
3037 * normal IEEE SGL will be built. Currently this routine supports NVMe devices
3040 * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built.
3043 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm,
3044 bus_dma_segment_t *segs, int segs_left)
3046 uint32_t i, sge_dwords, length, offset, entry_len;
3047 uint32_t num_entries, buff_len = 0, sges_in_segment;
3048 uint32_t page_mask, page_mask_result, *curr_buff;
3049 uint32_t *ptr_sgl, *ptr_first_sgl, first_page_offset;
3050 uint32_t first_page_data_size, end_residual;
3053 int build_native_sgl = 0, first_prp_entry;
3054 int prp_size = PRP_ENTRY_SIZE;
3055 Mpi25IeeeSgeChain64_t *main_chain_element = NULL;
3056 struct mpr_prp_page *prp_page_info = NULL;
3058 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
3061 * Add up the sizes of each segment length to get the total transfer
3062 * size, which will be checked against the Maximum Data Transfer Size.
3063 * If the data transfer length exceeds the MDTS for this device, just
3064 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O
3065 * up into multiple I/O's. [nvme_mdts = 0 means unlimited]
3067 for (i = 0; i < segs_left; i++)
3068 buff_len += htole32(segs[i].ds_len);
3069 if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS))
3072 /* Create page_mask (to get offset within page) */
3073 page_mask = PAGE_SIZE - 1;
3076 * Check if the number of elements exceeds the max number that can be
3077 * put in the main message frame (H/W can only translate an SGL that
3078 * is contained entirely in the main message frame).
3080 sges_in_segment = (sc->reqframesz -
3081 offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION);
3082 if (segs_left > sges_in_segment)
3083 build_native_sgl = 1;
3087 * NVMe uses one PRP for each physical page (or part of physical
3089 * if 4 pages or less then IEEE is OK
3090 * if > 5 pages then we need to build a native SGL
3091 * if > 4 and <= 5 pages, then check the physical address of
3092 * the first SG entry, then if this first size in the page
3093 * is >= the residual beyond 4 pages then use IEEE,
3094 * otherwise use native SGL
3096 if (buff_len > (PAGE_SIZE * 5))
3097 build_native_sgl = 1;
3098 else if ((buff_len > (PAGE_SIZE * 4)) &&
3099 (buff_len <= (PAGE_SIZE * 5)) )
3101 msg_phys = (uint64_t *)(uintptr_t)segs[0].ds_addr;
3103 ((uint32_t)(uint64_t)(uintptr_t)msg_phys &
3105 first_page_data_size = PAGE_SIZE - first_page_offset;
3106 end_residual = buff_len % PAGE_SIZE;
3109 * If offset into first page pushes the end of the data
3110 * beyond end of the 5th page, we need the extra PRP
3113 if (first_page_data_size < end_residual)
3114 build_native_sgl = 1;
3117 * Check if first SG entry size is < residual beyond 4
3120 if (htole32(segs[0].ds_len) <
3121 (buff_len - (PAGE_SIZE * 4)))
3122 build_native_sgl = 1;
3126 /* check if native SGL is needed */
3127 if (!build_native_sgl)
3131 * Native SGL is needed.
3132 * Put a chain element in main message frame that points to the first
3135 * NOTE: The ChainOffset field must be 0 when using a chain pointer to
3139 /* Set main message chain element pointer */
3140 main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge;
3143 * For NVMe the chain element needs to be the 2nd SGL entry in the main
3146 main_chain_element = (Mpi25IeeeSgeChain64_t *)
3147 ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
3150 * For the PRP entries, use the specially allocated buffer of
3151 * contiguous memory. PRP Page allocation failures should not happen
3152 * because there should be enough PRP page buffers to account for the
3153 * possible NVMe QDepth.
3155 prp_page_info = mpr_alloc_prp_page(sc);
3156 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
3157 "used for building a native NVMe SGL.\n", __func__));
3158 curr_buff = (uint32_t *)prp_page_info->prp_page;
3159 msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
3162 * Insert the allocated PRP page into the command's PRP page list. This
3163 * will be freed when the command is freed.
3165 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
3168 * Check if we are within 1 entry of a page boundary we don't want our
3169 * first entry to be a PRP List entry.
3171 page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) &
3173 if (!page_mask_result) {
3174 /* Bump up to next page boundary. */
3175 curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size);
3176 msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size);
3179 /* Fill in the chain element and make it an NVMe segment type. */
3180 main_chain_element->Address.High =
3181 htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32));
3182 main_chain_element->Address.Low =
3183 htole32((uint32_t)(uintptr_t)msg_phys);
3184 main_chain_element->NextChainOffset = 0;
3185 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
3186 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
3187 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
3189 /* Set SGL pointer to start of contiguous PCIe buffer. */
3190 ptr_sgl = curr_buff;
3195 * NVMe has a very convoluted PRP format. One PRP is required for each
3196 * page or partial page. We need to split up OS SG entries if they are
3197 * longer than one page or cross a page boundary. We also have to insert
3198 * a PRP list pointer entry as the last entry in each physical page of
3201 * NOTE: The first PRP "entry" is actually placed in the first SGL entry
3202 * in the main message in IEEE 64 format. The 2nd entry in the main
3203 * message is the chain element, and the rest of the PRP entries are
3204 * built in the contiguous PCIe buffer.
3206 first_prp_entry = 1;
3207 ptr_first_sgl = (uint32_t *)cm->cm_sge;
3209 for (i = 0; i < segs_left; i++) {
3210 /* Get physical address and length of this SG entry. */
3211 paddr = segs[i].ds_addr;
3212 length = segs[i].ds_len;
3215 * Check whether a given SGE buffer lies on a non-PAGED
3216 * boundary if this is not the first page. If so, this is not
3217 * expected so have FW build the SGL.
3219 if ((i != 0) && (((uint32_t)paddr & page_mask) != 0)) {
3220 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while "
3221 "building NVMe PRPs, low address is 0x%x\n",
3226 /* Apart from last SGE, if any other SGE boundary is not page
3227 * aligned then it means that hole exists. Existence of hole
3228 * leads to data corruption. So fallback to IEEE SGEs.
3230 if (i != (segs_left - 1)) {
3231 if (((uint32_t)paddr + length) & page_mask) {
3232 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE "
3233 "boundary while building NVMe PRPs, low "
3234 "address: 0x%x and length: %u\n",
3235 (uint32_t)paddr, length);
3240 /* Loop while the length is not zero. */
3243 * Check if we need to put a list pointer here if we are
3244 * at page boundary - prp_size.
3246 page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl +
3247 prp_size) & page_mask;
3248 if (!page_mask_result) {
3250 * Need to put a PRP list pointer here.
3252 msg_phys = (uint64_t *)((uint8_t *)msg_phys +
3254 *ptr_sgl = htole32((uintptr_t)msg_phys);
3255 *(ptr_sgl+1) = htole32((uint64_t)(uintptr_t)
3257 ptr_sgl += sge_dwords;
3261 /* Need to handle if entry will be part of a page. */
3262 offset = (uint32_t)paddr & page_mask;
3263 entry_len = PAGE_SIZE - offset;
3264 if (first_prp_entry) {
3266 * Put IEEE entry in first SGE in main message.
3267 * (Simple element, System addr, not end of
3270 *ptr_first_sgl = htole32((uint32_t)paddr);
3271 *(ptr_first_sgl + 1) =
3272 htole32((uint32_t)((uint64_t)paddr >> 32));
3273 *(ptr_first_sgl + 2) = htole32(entry_len);
3274 *(ptr_first_sgl + 3) = 0;
3276 /* No longer the first PRP entry. */
3277 first_prp_entry = 0;
3279 /* Put entry in list. */
3280 *ptr_sgl = htole32((uint32_t)paddr);
3282 htole32((uint32_t)((uint64_t)paddr >> 32));
3284 /* Bump ptr_sgl, msg_phys, and num_entries. */
3285 ptr_sgl += sge_dwords;
3286 msg_phys = (uint64_t *)((uint8_t *)msg_phys +
3291 /* Bump the phys address by the entry_len. */
3294 /* Decrement length accounting for last partial page. */
3295 if (entry_len > length)
3298 length -= entry_len;
3302 /* Set chain element Length. */
3303 main_chain_element->Length = htole32(num_entries * prp_size);
3305 /* Return 0, indicating we built a native SGL. */
3310 * Add a chain element as the next SGE for the specified command.
3311 * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are
3312 * only required for IEEE commands. Therefore there is no code for commands
3313 * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands
3314 * shouldn't be requesting chains).
3317 mpr_add_chain(struct mpr_command *cm, int segsleft)
3319 struct mpr_softc *sc = cm->cm_sc;
3320 MPI2_REQUEST_HEADER *req;
3321 MPI25_IEEE_SGE_CHAIN64 *ieee_sgc;
3322 struct mpr_chain *chain;
3323 int sgc_size, current_segs, rem_segs, segs_per_frame;
3324 uint8_t next_chain_offset = 0;
3327 * Fail if a command is requesting a chain for SIMPLE SGE's. For SAS3
3328 * only IEEE commands should be requesting chains. Return some error
3329 * code other than 0.
3331 if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) {
3332 mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to "
3337 sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64);
3338 if (cm->cm_sglsize < sgc_size)
3339 panic("MPR: Need SGE Error Code\n");
3341 chain = mpr_alloc_chain(cm->cm_sc);
3346 * Note: a double-linked list is used to make it easier to walk for
3349 TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link);
3352 * Need to know if the number of frames left is more than 1 or not. If
3353 * more than 1 frame is required, NextChainOffset will need to be set,
3354 * which will just be the last segment of the frame.
3357 if (cm->cm_sglsize < (sgc_size * segsleft)) {
3359 * rem_segs is the number of segements remaining after the
3360 * segments that will go into the current frame. Since it is
3361 * known that at least one more frame is required, account for
3362 * the chain element. To know if more than one more frame is
3363 * required, just check if there will be a remainder after using
3364 * the current frame (with this chain) and the next frame. If
3365 * so the NextChainOffset must be the last element of the next
3368 current_segs = (cm->cm_sglsize / sgc_size) - 1;
3369 rem_segs = segsleft - current_segs;
3370 segs_per_frame = sc->chain_frame_size / sgc_size;
3371 if (rem_segs > segs_per_frame) {
3372 next_chain_offset = segs_per_frame - 1;
3375 ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain;
3376 ieee_sgc->Length = next_chain_offset ?
3377 htole32((uint32_t)sc->chain_frame_size) :
3378 htole32((uint32_t)rem_segs * (uint32_t)sgc_size);
3379 ieee_sgc->NextChainOffset = next_chain_offset;
3380 ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
3381 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3382 ieee_sgc->Address.Low = htole32(chain->chain_busaddr);
3383 ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32);
3384 cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple;
3385 req = (MPI2_REQUEST_HEADER *)cm->cm_req;
3386 req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4;
3388 cm->cm_sglsize = sc->chain_frame_size;
3393 * Add one scatter-gather element to the scatter-gather list for a command.
3394 * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the
3395 * next SGE to fill in, respectively. In Gen3, the MPI SGL does not have a
3396 * chain, so don't consider any chain additions.
3399 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len,
3402 uint32_t saved_buf_len, saved_address_low, saved_address_high;
3406 * case 1: >=1 more segment, no room for anything (error)
3407 * case 2: 1 more segment and enough room for it
3410 if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) {
3411 mpr_dprint(cm->cm_sc, MPR_ERROR,
3412 "%s: warning: Not enough room for MPI SGL in frame.\n",
3417 KASSERT(segsleft == 1,
3418 ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n",
3422 * There is one more segment left to add for the MPI SGL and there is
3423 * enough room in the frame to add it. This is the normal case because
3424 * MPI SGL's don't have chains, otherwise something is wrong.
3426 * If this is a bi-directional request, need to account for that
3427 * here. Save the pre-filled sge values. These will be used
3428 * either for the 2nd SGL or for a single direction SGL. If
3429 * cm_out_len is non-zero, this is a bi-directional request, so
3430 * fill in the OUT SGL first, then the IN SGL, otherwise just
3431 * fill in the IN SGL. Note that at this time, when filling in
3432 * 2 SGL's for a bi-directional request, they both use the same
3433 * DMA buffer (same cm command).
3435 saved_buf_len = sge->FlagsLength & 0x00FFFFFF;
3436 saved_address_low = sge->Address.Low;
3437 saved_address_high = sge->Address.High;
3438 if (cm->cm_out_len) {
3439 sge->FlagsLength = cm->cm_out_len |
3440 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3441 MPI2_SGE_FLAGS_END_OF_BUFFER |
3442 MPI2_SGE_FLAGS_HOST_TO_IOC |
3443 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
3444 MPI2_SGE_FLAGS_SHIFT);
3445 cm->cm_sglsize -= len;
3446 /* Endian Safe code */
3447 sge_flags = sge->FlagsLength;
3448 sge->FlagsLength = htole32(sge_flags);
3449 sge->Address.High = htole32(sge->Address.High);
3450 sge->Address.Low = htole32(sge->Address.Low);
3451 bcopy(sge, cm->cm_sge, len);
3452 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
3454 sge->FlagsLength = saved_buf_len |
3455 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3456 MPI2_SGE_FLAGS_END_OF_BUFFER |
3457 MPI2_SGE_FLAGS_LAST_ELEMENT |
3458 MPI2_SGE_FLAGS_END_OF_LIST |
3459 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
3460 MPI2_SGE_FLAGS_SHIFT);
3461 if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) {
3463 ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
3464 MPI2_SGE_FLAGS_SHIFT);
3467 ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
3468 MPI2_SGE_FLAGS_SHIFT);
3470 sge->Address.Low = saved_address_low;
3471 sge->Address.High = saved_address_high;
3473 cm->cm_sglsize -= len;
3474 /* Endian Safe code */
3475 sge_flags = sge->FlagsLength;
3476 sge->FlagsLength = htole32(sge_flags);
3477 sge->Address.High = htole32(sge->Address.High);
3478 sge->Address.Low = htole32(sge->Address.Low);
3479 bcopy(sge, cm->cm_sge, len);
3480 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
3485 * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter-
3486 * gather list for a command. Maintain cm_sglsize and cm_sge as the
3487 * remaining size and pointer to the next SGE to fill in, respectively.
3490 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft)
3492 MPI2_IEEE_SGE_SIMPLE64 *sge = sgep;
3493 int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION);
3494 uint32_t saved_buf_len, saved_address_low, saved_address_high;
3495 uint32_t sge_length;
3498 * case 1: No room for chain or segment (error).
3499 * case 2: Two or more segments left but only room for chain.
3500 * case 3: Last segment and room for it, so set flags.
3504 * There should be room for at least one element, or there is a big
3507 if (cm->cm_sglsize < ieee_sge_size)
3508 panic("MPR: Need SGE Error Code\n");
3510 if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) {
3511 if ((error = mpr_add_chain(cm, segsleft)) != 0)
3515 if (segsleft == 1) {
3517 * If this is a bi-directional request, need to account for that
3518 * here. Save the pre-filled sge values. These will be used
3519 * either for the 2nd SGL or for a single direction SGL. If
3520 * cm_out_len is non-zero, this is a bi-directional request, so
3521 * fill in the OUT SGL first, then the IN SGL, otherwise just
3522 * fill in the IN SGL. Note that at this time, when filling in
3523 * 2 SGL's for a bi-directional request, they both use the same
3524 * DMA buffer (same cm command).
3526 saved_buf_len = sge->Length;
3527 saved_address_low = sge->Address.Low;
3528 saved_address_high = sge->Address.High;
3529 if (cm->cm_out_len) {
3530 sge->Length = cm->cm_out_len;
3531 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3532 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3533 cm->cm_sglsize -= ieee_sge_size;
3534 /* Endian Safe code */
3535 sge_length = sge->Length;
3536 sge->Length = htole32(sge_length);
3537 sge->Address.High = htole32(sge->Address.High);
3538 sge->Address.Low = htole32(sge->Address.Low);
3539 bcopy(sgep, cm->cm_sge, ieee_sge_size);
3541 (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3544 sge->Length = saved_buf_len;
3545 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3546 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
3547 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
3548 sge->Address.Low = saved_address_low;
3549 sge->Address.High = saved_address_high;
3552 cm->cm_sglsize -= ieee_sge_size;
3553 /* Endian Safe code */
3554 sge_length = sge->Length;
3555 sge->Length = htole32(sge_length);
3556 sge->Address.High = htole32(sge->Address.High);
3557 sge->Address.Low = htole32(sge->Address.Low);
3558 bcopy(sgep, cm->cm_sge, ieee_sge_size);
3559 cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3565 * Add one dma segment to the scatter-gather list for a command.
3568 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags,
3571 MPI2_SGE_SIMPLE64 sge;
3572 MPI2_IEEE_SGE_SIMPLE64 ieee_sge;
3574 if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) {
3575 ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3576 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3577 ieee_sge.Length = len;
3578 mpr_from_u64(pa, &ieee_sge.Address);
3580 return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft));
3583 * This driver always uses 64-bit address elements for
3586 flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3587 MPI2_SGE_FLAGS_64_BIT_ADDRESSING;
3588 /* Set Endian safe macro in mpr_push_sge */
3589 sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT);
3590 mpr_from_u64(pa, &sge.Address);
3592 return (mpr_push_sge(cm, &sge, sizeof sge, segsleft));
3597 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3599 struct mpr_softc *sc;
3600 struct mpr_command *cm;
3601 u_int i, dir, sflags;
3603 cm = (struct mpr_command *)arg;
3607 * In this case, just print out a warning and let the chip tell the
3608 * user they did the wrong thing.
3610 if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) {
3611 mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d "
3612 "segments, more than the %d allowed\n", __func__, nsegs,
3617 * Set up DMA direction flags. Bi-directional requests are also handled
3618 * here. In that case, both direction flags will be set.
3621 if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) {
3623 * We have to add a special case for SMP passthrough, there
3624 * is no easy way to generically handle it. The first
3625 * S/G element is used for the command (therefore the
3626 * direction bit needs to be set). The second one is used
3627 * for the reply. We'll leave it to the caller to make
3628 * sure we only have two buffers.
3631 * Even though the busdma man page says it doesn't make
3632 * sense to have both direction flags, it does in this case.
3633 * We have one s/g element being accessed in each direction.
3635 dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD;
3638 * Set the direction flag on the first buffer in the SMP
3639 * passthrough request. We'll clear it for the second one.
3641 sflags |= MPI2_SGE_FLAGS_DIRECTION |
3642 MPI2_SGE_FLAGS_END_OF_BUFFER;
3643 } else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) {
3644 sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
3645 dir = BUS_DMASYNC_PREWRITE;
3647 dir = BUS_DMASYNC_PREREAD;
3649 /* Check if a native SG list is needed for an NVMe PCIe device. */
3650 if (cm->cm_targ && cm->cm_targ->is_nvme &&
3651 mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) {
3652 /* A native SG list was built, skip to end. */
3656 for (i = 0; i < nsegs; i++) {
3657 if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) {
3658 sflags &= ~MPI2_SGE_FLAGS_DIRECTION;
3660 error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len,
3663 /* Resource shortage, roll back! */
3664 if (ratecheck(&sc->lastfail, &mpr_chainfail_interval))
3665 mpr_dprint(sc, MPR_INFO, "Out of chain frames, "
3666 "consider increasing hw.mpr.max_chains.\n");
3667 cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED;
3668 mpr_complete_command(sc, cm);
3674 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir);
3675 mpr_enqueue_request(sc, cm);
3681 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize,
3684 mpr_data_cb(arg, segs, nsegs, error);
3688 * This is the routine to enqueue commands ansynchronously.
3689 * Note that the only error path here is from bus_dmamap_load(), which can
3690 * return EINPROGRESS if it is waiting for resources. Other than this, it's
3691 * assumed that if you have a command in-hand, then you have enough credits
3695 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm)
3699 if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) {
3700 error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap,
3701 &cm->cm_uio, mpr_data_cb2, cm, 0);
3702 } else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) {
3703 error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap,
3704 cm->cm_data, mpr_data_cb, cm, 0);
3705 } else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) {
3706 error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap,
3707 cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0);
3709 /* Add a zero-length element as needed */
3710 if (cm->cm_sge != NULL)
3711 mpr_add_dmaseg(cm, 0, 0, 0, 1);
3712 mpr_enqueue_request(sc, cm);
3719 * This is the routine to enqueue commands synchronously. An error of
3720 * EINPROGRESS from mpr_map_command() is ignored since the command will
3721 * be executed and enqueued automatically. Other errors come from msleep().
3724 mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cmp, int timeout,
3728 struct timeval cur_time, start_time;
3729 struct mpr_command *cm = *cmp;
3731 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET)
3734 cm->cm_complete = NULL;
3735 cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED);
3736 error = mpr_map_command(sc, cm);
3737 if ((error != 0) && (error != EINPROGRESS))
3740 // Check for context and wait for 50 mSec at a time until time has
3741 // expired or the command has finished. If msleep can't be used, need
3743 if (curthread->td_no_sleeping)
3744 sleep_flag = NO_SLEEP;
3745 getmicrouptime(&start_time);
3746 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) {
3747 error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz);
3748 if (error == EWOULDBLOCK) {
3750 * Record the actual elapsed time in the case of a
3751 * timeout for the message below.
3753 getmicrouptime(&cur_time);
3754 timevalsub(&cur_time, &start_time);
3757 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3758 mpr_intr_locked(sc);
3759 if (sleep_flag == CAN_SLEEP)
3760 pause("mprwait", hz/20);
3764 getmicrouptime(&cur_time);
3765 timevalsub(&cur_time, &start_time);
3766 if (cur_time.tv_sec > timeout) {
3767 error = EWOULDBLOCK;
3773 if (error == EWOULDBLOCK) {
3774 if (cm->cm_timeout_handler == NULL) {
3775 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s, timeout=%d,"
3776 " elapsed=%jd\n", __func__, timeout,
3777 (intmax_t)cur_time.tv_sec);
3778 rc = mpr_reinit(sc);
3779 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3782 cm->cm_timeout_handler(sc, cm);
3783 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) {
3785 * Tell the caller that we freed the command in a
3796 * This is the routine to enqueue a command synchonously and poll for
3797 * completion. Its use should be rare.
3800 mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cmp)
3803 struct timeval cur_time, start_time;
3804 struct mpr_command *cm = *cmp;
3808 cm->cm_flags |= MPR_CM_FLAGS_POLLED;
3809 cm->cm_complete = NULL;
3810 mpr_map_command(sc, cm);
3812 getmicrouptime(&start_time);
3813 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3814 mpr_intr_locked(sc);
3816 if (mtx_owned(&sc->mpr_mtx))
3817 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
3820 pause("mprpoll", hz/20);
3823 * Check for real-time timeout and fail if more than 60 seconds.
3825 getmicrouptime(&cur_time);
3826 timevalsub(&cur_time, &start_time);
3827 if (cur_time.tv_sec > 60) {
3828 mpr_dprint(sc, MPR_FAULT, "polling failed\n");
3833 cm->cm_state = MPR_CM_STATE_BUSY;
3835 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__);
3836 rc = mpr_reinit(sc);
3837 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3840 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) {
3842 * Tell the caller that we freed the command in a
3852 * The MPT driver had a verbose interface for config pages. In this driver,
3853 * reduce it to much simpler terms, similar to the Linux driver.
3856 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3858 MPI2_CONFIG_REQUEST *req;
3859 struct mpr_command *cm;
3862 if (sc->mpr_flags & MPR_FLAGS_BUSY) {
3866 cm = mpr_alloc_command(sc);
3871 req = (MPI2_CONFIG_REQUEST *)cm->cm_req;
3872 req->Function = MPI2_FUNCTION_CONFIG;
3873 req->Action = params->action;
3875 req->ChainOffset = 0;
3876 req->PageAddress = params->page_address;
3877 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
3878 MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr;
3880 hdr = ¶ms->hdr.Ext;
3881 req->ExtPageType = hdr->ExtPageType;
3882 req->ExtPageLength = hdr->ExtPageLength;
3883 req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED;
3884 req->Header.PageLength = 0; /* Must be set to zero */
3885 req->Header.PageNumber = hdr->PageNumber;
3886 req->Header.PageVersion = hdr->PageVersion;
3888 MPI2_CONFIG_PAGE_HEADER *hdr;
3890 hdr = ¶ms->hdr.Struct;
3891 req->Header.PageType = hdr->PageType;
3892 req->Header.PageNumber = hdr->PageNumber;
3893 req->Header.PageLength = hdr->PageLength;
3894 req->Header.PageVersion = hdr->PageVersion;
3897 cm->cm_data = params->buffer;
3898 cm->cm_length = params->length;
3899 if (cm->cm_data != NULL) {
3900 cm->cm_sge = &req->PageBufferSGE;
3901 cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION);
3902 cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN;
3905 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3907 cm->cm_complete_data = params;
3908 if (params->callback != NULL) {
3909 cm->cm_complete = mpr_config_complete;
3910 return (mpr_map_command(sc, cm));
3912 error = mpr_wait_command(sc, &cm, 0, CAN_SLEEP);
3914 mpr_dprint(sc, MPR_FAULT,
3915 "Error %d reading config page\n", error);
3917 mpr_free_command(sc, cm);
3920 mpr_config_complete(sc, cm);
3927 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3933 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm)
3935 MPI2_CONFIG_REPLY *reply;
3936 struct mpr_config_params *params;
3939 params = cm->cm_complete_data;
3941 if (cm->cm_data != NULL) {
3942 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap,
3943 BUS_DMASYNC_POSTREAD);
3944 bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap);
3948 * XXX KDM need to do more error recovery? This results in the
3949 * device in question not getting probed.
3951 if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) {
3952 params->status = MPI2_IOCSTATUS_BUSY;
3956 reply = (MPI2_CONFIG_REPLY *)cm->cm_reply;
3957 if (reply == NULL) {
3958 params->status = MPI2_IOCSTATUS_BUSY;
3961 params->status = reply->IOCStatus;
3962 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
3963 params->hdr.Ext.ExtPageType = reply->ExtPageType;
3964 params->hdr.Ext.ExtPageLength = reply->ExtPageLength;
3965 params->hdr.Ext.PageType = reply->Header.PageType;
3966 params->hdr.Ext.PageNumber = reply->Header.PageNumber;
3967 params->hdr.Ext.PageVersion = reply->Header.PageVersion;
3969 params->hdr.Struct.PageType = reply->Header.PageType;
3970 params->hdr.Struct.PageNumber = reply->Header.PageNumber;
3971 params->hdr.Struct.PageLength = reply->Header.PageLength;
3972 params->hdr.Struct.PageVersion = reply->Header.PageVersion;
3976 mpr_free_command(sc, cm);
3977 if (params->callback != NULL)
3978 params->callback(sc, params);