2 * Copyright (c) 2006-2015 LSI Corp.
3 * Copyright (c) 2013-2015 Avago Technologies
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
33 * Copyright (c) 2006-2015 LSI Corporation.
34 * Copyright (c) 2013-2015 Avago Technologies
38 * Title: MPI Message independent structures and definitions
39 * including System Interface Register Set and
40 * scatter/gather formats.
41 * Creation Date: June 21, 2006
43 * mpi2.h Version: 02.00.18
48 * Date Version Description
49 * -------- -------- ------------------------------------------------------
50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
51 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
52 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
54 * Moved ReplyPostHostIndex register to offset 0x6C of the
55 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
56 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
57 * Added union of request descriptors.
58 * Added union of reply descriptors.
59 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
60 * Added define for MPI2_VERSION_02_00.
61 * Fixed the size of the FunctionDependent5 field in the
62 * MPI2_DEFAULT_REPLY structure.
63 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
64 * Removed the MPI-defined Fault Codes and extended the
65 * product specific codes up to 0xEFFF.
66 * Added a sixth key value for the WriteSequence register
67 * and changed the flush value to 0x0.
68 * Added message function codes for Diagnostic Buffer Post
69 * and Diagnsotic Release.
70 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
71 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
72 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
74 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added #defines for marking a reply descriptor as unused.
76 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
78 * Moved LUN field defines from mpi2_init.h.
79 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
81 * In all request and reply descriptors, replaced VF_ID
82 * field with MSIxIndex field.
83 * Removed DevHandle field from
84 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
86 * Added RAID Accelerator functionality.
87 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
89 * Added MSI-x index mask and shift for Reply Post Host
91 * Added function code for Host Based Discovery Action.
92 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
93 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
94 * Added defines for product-specific range of message
95 * function codes, 0xF0 to 0xFF.
96 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
97 * Added alternative defines for the SGE Direction bit.
98 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
99 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
100 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
101 * --------------------------------------------------------------------------
108 /*****************************************************************************
110 * MPI Version Definitions
112 *****************************************************************************/
114 #define MPI2_VERSION_MAJOR (0x02)
115 #define MPI2_VERSION_MINOR (0x00)
116 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
117 #define MPI2_VERSION_MAJOR_SHIFT (8)
118 #define MPI2_VERSION_MINOR_MASK (0x00FF)
119 #define MPI2_VERSION_MINOR_SHIFT (0)
120 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
123 #define MPI2_VERSION_02_00 (0x0200)
125 /* versioning for this MPI header set */
126 #define MPI2_HEADER_VERSION_UNIT (0x12)
127 #define MPI2_HEADER_VERSION_DEV (0x00)
128 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
129 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
130 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
131 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
132 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
135 /*****************************************************************************
137 * IOC State Definitions
139 *****************************************************************************/
141 #define MPI2_IOC_STATE_RESET (0x00000000)
142 #define MPI2_IOC_STATE_READY (0x10000000)
143 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
144 #define MPI2_IOC_STATE_FAULT (0x40000000)
146 #define MPI2_IOC_STATE_MASK (0xF0000000)
147 #define MPI2_IOC_STATE_SHIFT (28)
149 /* Fault state range for prodcut specific codes */
150 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
151 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
154 /*****************************************************************************
156 * System Interface Register Definitions
158 *****************************************************************************/
160 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
162 U32 Doorbell; /* 0x00 */
163 U32 WriteSequence; /* 0x04 */
164 U32 HostDiagnostic; /* 0x08 */
165 U32 Reserved1; /* 0x0C */
166 U32 DiagRWData; /* 0x10 */
167 U32 DiagRWAddressLow; /* 0x14 */
168 U32 DiagRWAddressHigh; /* 0x18 */
169 U32 Reserved2[5]; /* 0x1C */
170 U32 HostInterruptStatus; /* 0x30 */
171 U32 HostInterruptMask; /* 0x34 */
172 U32 DCRData; /* 0x38 */
173 U32 DCRAddress; /* 0x3C */
174 U32 Reserved3[2]; /* 0x40 */
175 U32 ReplyFreeHostIndex; /* 0x48 */
176 U32 Reserved4[8]; /* 0x4C */
177 U32 ReplyPostHostIndex; /* 0x6C */
178 U32 Reserved5; /* 0x70 */
179 U32 HCBSize; /* 0x74 */
180 U32 HCBAddressLow; /* 0x78 */
181 U32 HCBAddressHigh; /* 0x7C */
182 U32 Reserved6[16]; /* 0x80 */
183 U32 RequestDescriptorPostLow; /* 0xC0 */
184 U32 RequestDescriptorPostHigh; /* 0xC4 */
185 U32 Reserved7[14]; /* 0xC8 */
186 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
187 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
190 * Defines for working with the Doorbell register.
192 #define MPI2_DOORBELL_OFFSET (0x00000000)
194 /* IOC --> System values */
195 #define MPI2_DOORBELL_USED (0x08000000)
196 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
197 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
198 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
199 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
201 /* System --> IOC values */
202 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
203 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
204 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
205 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
209 * Defines for the WriteSequence register
211 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
212 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
213 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
214 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
215 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
216 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
217 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
218 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
219 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
222 * Defines for the HostDiagnostic register
224 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
226 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
227 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
228 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
230 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
231 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
232 #define MPI2_DIAG_HCB_MODE (0x00000100)
233 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
234 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
235 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
236 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
237 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
238 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
241 * Offsets for DiagRWData and address
243 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
244 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
245 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
248 * Defines for the HostInterruptStatus register
250 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
251 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
252 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
253 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
254 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
255 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
256 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
259 * Defines for the HostInterruptMask register
261 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
262 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
263 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
264 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
265 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
266 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
269 * Offsets for DCRData and address
271 #define MPI2_DCR_DATA_OFFSET (0x00000038)
272 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
275 * Offset for the Reply Free Queue
277 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
280 * Defines for the Reply Descriptor Post Queue
282 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
283 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
284 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
285 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
288 * Defines for the HCBSize and address
290 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
291 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
292 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
294 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
295 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
298 * Offsets for the Request Queue
300 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
301 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
304 /*****************************************************************************
306 * Message Descriptors
308 *****************************************************************************/
310 /* Request Descriptors */
312 /* Default Request Descriptor */
313 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
315 U8 RequestFlags; /* 0x00 */
316 U8 MSIxIndex; /* 0x01 */
319 U16 DescriptorTypeDependent; /* 0x06 */
320 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
321 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
322 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
324 /* defines for the RequestFlags field */
325 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
326 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
327 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
328 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
329 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
330 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
332 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
335 /* High Priority Request Descriptor */
336 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
338 U8 RequestFlags; /* 0x00 */
339 U8 MSIxIndex; /* 0x01 */
342 U16 Reserved1; /* 0x06 */
343 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
344 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
345 Mpi2HighPriorityRequestDescriptor_t,
346 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
349 /* SCSI IO Request Descriptor */
350 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
352 U8 RequestFlags; /* 0x00 */
353 U8 MSIxIndex; /* 0x01 */
356 U16 DevHandle; /* 0x06 */
357 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
358 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
359 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
362 /* SCSI Target Request Descriptor */
363 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
365 U8 RequestFlags; /* 0x00 */
366 U8 MSIxIndex; /* 0x01 */
369 U16 IoIndex; /* 0x06 */
370 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
371 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
372 Mpi2SCSITargetRequestDescriptor_t,
373 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
376 /* RAID Accelerator Request Descriptor */
377 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
379 U8 RequestFlags; /* 0x00 */
380 U8 MSIxIndex; /* 0x01 */
383 U16 Reserved; /* 0x06 */
384 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
385 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
386 Mpi2RAIDAcceleratorRequestDescriptor_t,
387 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
390 /* union of Request Descriptors */
391 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
393 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
394 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
395 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
396 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
397 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
399 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
400 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
403 /* Reply Descriptors */
405 /* Default Reply Descriptor */
406 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
408 U8 ReplyFlags; /* 0x00 */
409 U8 MSIxIndex; /* 0x01 */
410 U16 DescriptorTypeDependent1; /* 0x02 */
411 U32 DescriptorTypeDependent2; /* 0x04 */
412 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
413 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
415 /* defines for the ReplyFlags field */
416 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
417 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
418 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
419 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
420 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
421 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
422 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
424 /* values for marking a reply descriptor as unused */
425 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
426 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
428 /* Address Reply Descriptor */
429 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
431 U8 ReplyFlags; /* 0x00 */
432 U8 MSIxIndex; /* 0x01 */
434 U32 ReplyFrameAddress; /* 0x04 */
435 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
436 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
438 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
441 /* SCSI IO Success Reply Descriptor */
442 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
444 U8 ReplyFlags; /* 0x00 */
445 U8 MSIxIndex; /* 0x01 */
447 U16 TaskTag; /* 0x04 */
448 U16 Reserved1; /* 0x06 */
449 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
450 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
451 Mpi2SCSIIOSuccessReplyDescriptor_t,
452 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
455 /* TargetAssist Success Reply Descriptor */
456 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
458 U8 ReplyFlags; /* 0x00 */
459 U8 MSIxIndex; /* 0x01 */
461 U8 SequenceNumber; /* 0x04 */
462 U8 Reserved1; /* 0x05 */
463 U16 IoIndex; /* 0x06 */
464 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
465 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
466 Mpi2TargetAssistSuccessReplyDescriptor_t,
467 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
470 /* Target Command Buffer Reply Descriptor */
471 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
473 U8 ReplyFlags; /* 0x00 */
474 U8 MSIxIndex; /* 0x01 */
477 U16 InitiatorDevHandle; /* 0x04 */
478 U16 IoIndex; /* 0x06 */
479 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
480 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
481 Mpi2TargetCommandBufferReplyDescriptor_t,
482 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
484 /* defines for Flags field */
485 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
488 /* RAID Accelerator Success Reply Descriptor */
489 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
491 U8 ReplyFlags; /* 0x00 */
492 U8 MSIxIndex; /* 0x01 */
494 U32 Reserved; /* 0x04 */
495 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
496 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
497 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
498 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
501 /* union of Reply Descriptors */
502 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
504 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
505 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
506 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
507 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
508 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
509 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
511 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
512 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
516 /*****************************************************************************
520 *****************************************************************************/
522 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
523 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
524 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
525 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
526 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
527 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
528 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
529 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
530 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
531 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
532 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
533 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
534 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
535 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
536 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
537 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
538 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
539 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
540 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
541 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
542 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
543 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
544 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
545 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
546 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
547 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
548 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
549 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
550 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
551 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
555 /* Doorbell functions */
556 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
557 #define MPI2_FUNCTION_HANDSHAKE (0x42)
560 /*****************************************************************************
564 *****************************************************************************/
566 /* mask for IOCStatus status value */
567 #define MPI2_IOCSTATUS_MASK (0x7FFF)
569 /****************************************************************************
570 * Common IOCStatus values for all replies
571 ****************************************************************************/
573 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
574 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
575 #define MPI2_IOCSTATUS_BUSY (0x0002)
576 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
577 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
578 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
579 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
580 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
581 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
582 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
584 /****************************************************************************
585 * Config IOCStatus values
586 ****************************************************************************/
588 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
589 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
590 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
591 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
592 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
593 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
595 /****************************************************************************
597 ****************************************************************************/
599 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
600 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
601 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
602 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
603 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
604 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
605 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
606 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
607 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
608 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
609 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
610 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
612 /****************************************************************************
613 * For use by SCSI Initiator and SCSI Target end-to-end data protection
614 ****************************************************************************/
616 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
617 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
618 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
620 /****************************************************************************
622 ****************************************************************************/
624 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
625 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
626 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
627 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
628 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
629 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
630 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
631 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
632 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
633 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
635 /****************************************************************************
636 * Serial Attached SCSI values
637 ****************************************************************************/
639 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
640 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
642 /****************************************************************************
643 * Diagnostic Buffer Post / Diagnostic Release values
644 ****************************************************************************/
646 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
648 /****************************************************************************
649 * RAID Accelerator values
650 ****************************************************************************/
652 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
654 /****************************************************************************
655 * IOCStatus flag to indicate that log info is available
656 ****************************************************************************/
658 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
660 /****************************************************************************
662 ****************************************************************************/
664 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
665 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
666 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
667 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
668 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
669 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
670 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
671 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
674 /*****************************************************************************
676 * Standard Message Structures
678 *****************************************************************************/
680 /****************************************************************************
681 * Request Message Header for all request messages
682 ****************************************************************************/
684 typedef struct _MPI2_REQUEST_HEADER
686 U16 FunctionDependent1; /* 0x00 */
687 U8 ChainOffset; /* 0x02 */
688 U8 Function; /* 0x03 */
689 U16 FunctionDependent2; /* 0x04 */
690 U8 FunctionDependent3; /* 0x06 */
691 U8 MsgFlags; /* 0x07 */
694 U16 Reserved1; /* 0x0A */
695 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
696 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
699 /****************************************************************************
701 ****************************************************************************/
703 typedef struct _MPI2_DEFAULT_REPLY
705 U16 FunctionDependent1; /* 0x00 */
706 U8 MsgLength; /* 0x02 */
707 U8 Function; /* 0x03 */
708 U16 FunctionDependent2; /* 0x04 */
709 U8 FunctionDependent3; /* 0x06 */
710 U8 MsgFlags; /* 0x07 */
713 U16 Reserved1; /* 0x0A */
714 U16 FunctionDependent5; /* 0x0C */
715 U16 IOCStatus; /* 0x0E */
716 U32 IOCLogInfo; /* 0x10 */
717 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
718 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
721 /* common version structure/union used in messages and configuration pages */
723 typedef struct _MPI2_VERSION_STRUCT
729 } MPI2_VERSION_STRUCT;
731 typedef union _MPI2_VERSION_UNION
733 MPI2_VERSION_STRUCT Struct;
735 } MPI2_VERSION_UNION;
738 /* LUN field defines, common to many structures */
739 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
740 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
741 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
742 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
743 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
744 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
747 /*****************************************************************************
749 * Fusion-MPT MPI Scatter Gather Elements
751 *****************************************************************************/
753 /****************************************************************************
754 * MPI Simple Element structures
755 ****************************************************************************/
757 typedef struct _MPI2_SGE_SIMPLE32
761 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
762 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
764 typedef struct _MPI2_SGE_SIMPLE64
768 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
769 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
771 typedef struct _MPI2_SGE_SIMPLE_UNION
779 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
780 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
783 /****************************************************************************
784 * MPI Chain Element structures
785 ****************************************************************************/
787 typedef struct _MPI2_SGE_CHAIN32
793 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
794 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
796 typedef struct _MPI2_SGE_CHAIN64
802 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
803 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
805 typedef struct _MPI2_SGE_CHAIN_UNION
815 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
816 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
819 /****************************************************************************
820 * MPI Transaction Context Element structures
821 ****************************************************************************/
823 typedef struct _MPI2_SGE_TRANSACTION32
829 U32 TransactionContext[1];
830 U32 TransactionDetails[1];
831 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
832 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
834 typedef struct _MPI2_SGE_TRANSACTION64
840 U32 TransactionContext[2];
841 U32 TransactionDetails[1];
842 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
843 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
845 typedef struct _MPI2_SGE_TRANSACTION96
851 U32 TransactionContext[3];
852 U32 TransactionDetails[1];
853 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
854 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
856 typedef struct _MPI2_SGE_TRANSACTION128
862 U32 TransactionContext[4];
863 U32 TransactionDetails[1];
864 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
865 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
867 typedef struct _MPI2_SGE_TRANSACTION_UNION
875 U32 TransactionContext32[1];
876 U32 TransactionContext64[2];
877 U32 TransactionContext96[3];
878 U32 TransactionContext128[4];
880 U32 TransactionDetails[1];
881 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
882 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
885 /****************************************************************************
886 * MPI SGE union for IO SGL's
887 ****************************************************************************/
889 typedef struct _MPI2_MPI_SGE_IO_UNION
893 MPI2_SGE_SIMPLE_UNION Simple;
894 MPI2_SGE_CHAIN_UNION Chain;
896 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
897 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
900 /****************************************************************************
901 * MPI SGE union for SGL's with Simple and Transaction elements
902 ****************************************************************************/
904 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
908 MPI2_SGE_SIMPLE_UNION Simple;
909 MPI2_SGE_TRANSACTION_UNION Transaction;
911 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
912 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
915 /****************************************************************************
916 * All MPI SGE types union
917 ****************************************************************************/
919 typedef struct _MPI2_MPI_SGE_UNION
923 MPI2_SGE_SIMPLE_UNION Simple;
924 MPI2_SGE_CHAIN_UNION Chain;
925 MPI2_SGE_TRANSACTION_UNION Transaction;
927 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
928 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
931 /****************************************************************************
932 * MPI SGE field definition and masks
933 ****************************************************************************/
935 /* Flags field bit definitions */
937 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
938 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
939 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
940 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
941 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
942 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
943 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
945 #define MPI2_SGE_FLAGS_SHIFT (24)
947 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
948 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
952 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
953 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
954 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
955 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
957 /* Address location */
959 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
963 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
964 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
966 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
967 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
971 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
972 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
976 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
977 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
978 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
979 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
981 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
982 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
984 /****************************************************************************
985 * MPI SGE operation Macros
986 ****************************************************************************/
988 /* SIMPLE FlagsLength manipulations... */
989 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
990 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
991 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
992 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
994 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
996 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
997 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
998 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
1000 /* CAUTION - The following are READ-MODIFY-WRITE! */
1001 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1002 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1004 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1007 /*****************************************************************************
1009 * Fusion-MPT IEEE Scatter Gather Elements
1011 *****************************************************************************/
1013 /****************************************************************************
1014 * IEEE Simple Element structures
1015 ****************************************************************************/
1017 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1021 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1022 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1024 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1031 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1032 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1034 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1036 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1037 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1038 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1039 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1042 /****************************************************************************
1043 * IEEE Chain Element structures
1044 ****************************************************************************/
1046 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1048 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1050 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1052 MPI2_IEEE_SGE_CHAIN32 Chain32;
1053 MPI2_IEEE_SGE_CHAIN64 Chain64;
1054 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1055 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1058 /****************************************************************************
1059 * All IEEE SGE types union
1060 ****************************************************************************/
1062 typedef struct _MPI2_IEEE_SGE_UNION
1066 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1067 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1069 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1070 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1073 /****************************************************************************
1074 * IEEE SGE field definitions and masks
1075 ****************************************************************************/
1077 /* Flags field bit definitions */
1079 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1081 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1083 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1087 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1088 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1090 /* Data Location Address Space */
1092 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1093 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */
1094 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */
1095 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1096 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */
1097 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */
1099 /****************************************************************************
1100 * IEEE SGE operation Macros
1101 ****************************************************************************/
1103 /* SIMPLE FlagsLength manipulations... */
1104 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1105 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1106 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1108 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1110 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1111 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1112 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1114 /* CAUTION - The following are READ-MODIFY-WRITE! */
1115 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1116 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1121 /*****************************************************************************
1123 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1125 *****************************************************************************/
1127 typedef union _MPI2_SIMPLE_SGE_UNION
1129 MPI2_SGE_SIMPLE_UNION MpiSimple;
1130 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1131 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1132 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1135 typedef union _MPI2_SGE_IO_UNION
1137 MPI2_SGE_SIMPLE_UNION MpiSimple;
1138 MPI2_SGE_CHAIN_UNION MpiChain;
1139 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1140 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1141 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1142 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1145 /****************************************************************************
1147 * Values for SGLFlags field, used in many request messages with an SGL
1149 ****************************************************************************/
1151 /* values for MPI SGL Data Location Address Space subfield */
1152 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1153 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1154 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1155 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1156 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1157 /* values for SGL Type subfield */
1158 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1159 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1160 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1161 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)